diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-09 13:01:39 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-14 17:01:25 +0000 |
| commit | f1b1d92854281b035851719741092388f70e00f0 (patch) | |
| tree | 924a3776ee43bee23e345b5c3cf5d98b0b1985b1 /src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h | |
| parent | 2242919177317dd7827a4fc8f04c17dd8a4f8b32 (diff) | |
intel/fsp: Update cannonlake fsp header
Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
1. Add PeciSxRest option.
2. Add Thermal Velocity Boost option.
3. Add VR power deliver design option.
4. Match MrcChannelSts.
TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Reviewed-on: https://review.coreboot.org/23677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 435eccb4a5..941a891bff 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -84,6 +84,19 @@ typedef struct { } SiMrcVersion; // +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// // Matches MrcDimmSts enum in MRC // #ifndef DIMM_ENABLED |