diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-03-19 17:13:48 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-22 09:00:48 +0000 |
| commit | 5479525c74ce301754aee8a0955f258bdb751614 (patch) | |
| tree | 57c337279300cdbb92db231f755122ffe4eb1c3b /src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | |
| parent | a3ad990089ec0a13df52c7451ee5092229346bf6 (diff) | |
intel/fsp: Update Cannonlake FSP header
Update Cannonlake FSP header to version 7.x.2A.20, the following changes
were made:
1. Add MemtestonWarmBoot option.
2. Add enable8254clockgatingonS3 option.
3. Default disable Tccoffsetlock
BUG=None
TEST=None
Change-Id: Ie794960f0253b2a6dbd55ffda973756d15e35c01
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index d014f81bf9..74cc6728b7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -2291,9 +2291,15 @@ typedef struct { **/ UINT8 PegImrRpSelection; -/** Offset 0x0513 +/** Offset 0x0513 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x0514 **/ - UINT8 ReservedFspmUpd[12]; + UINT8 ReservedFspmUpd[11]; } FSP_M_CONFIG; /** Fsp M Test Configuration |