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authorMartin Roth <martin@coreboot.org>2021-02-14 13:58:31 -0700
committerMartin Roth <martinroth@google.com>2021-02-17 17:30:40 +0000
commit062c4a17a9ad1f30da74b9f1a7b54c030278996b (patch)
tree058ba55e753e8239201679c7c9677562b5777ebb /src/vendorcode/intel/fsp/fsp2_0/alderlake
parent5c7341331dd6fbb4dd9aaaa68693b83c3d47fe66 (diff)
vc/intel/fsp: Change line endings to unix
These files have windows line endings. Change to unix to match the rest of the tree. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5bb3338745a6a47b6714aa268d16866aada27790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/alderlake')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h1952
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h1790
2 files changed, 1871 insertions, 1871 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
index d0421723eb..b5b83630c3 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
@@ -1,976 +1,976 @@
-/** @file
-
-Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision; ///< Chipset Init Info Revision
- UINT8 Rsvd[3]; ///< Reserved
- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
-
-/** Fsp M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Platform Reserved Memory Size
- The minimum platform memory size required to pass control into DXE
-**/
- UINT64 PlatformMemorySize;
-
-/** Offset 0x0048 - SPD Data Length
- Length of SPD Data
- 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
-**/
- UINT16 MemorySpdDataLen;
-
-/** Offset 0x004A - Reserved
-**/
- UINT8 Reserved0[2];
-
-/** Offset 0x004C - MemorySpdPtr00
-**/
- UINT32 MemorySpdPtr00;
-
-/** Offset 0x0050 - MemorySpdPtr01
-**/
- UINT32 MemorySpdPtr01;
-
-/** Offset 0x0054 - MemorySpdPtr02
-**/
- UINT32 MemorySpdPtr02;
-
-/** Offset 0x0058 - MemorySpdPtr03
-**/
- UINT32 MemorySpdPtr03;
-
-/** Offset 0x005C - MemorySpdPtr04
-**/
- UINT32 MemorySpdPtr04;
-
-/** Offset 0x0060 - MemorySpdPtr05
-**/
- UINT32 MemorySpdPtr05;
-
-/** Offset 0x0064 - MemorySpdPtr06
-**/
- UINT32 MemorySpdPtr06;
-
-/** Offset 0x0068 - MemorySpdPtr07
-**/
- UINT32 MemorySpdPtr07;
-
-/** Offset 0x006C - MemorySpdPtr08
-**/
- UINT32 MemorySpdPtr08;
-
-/** Offset 0x0070 - MemorySpdPtr09
-**/
- UINT32 MemorySpdPtr09;
-
-/** Offset 0x0074 - MemorySpdPtr10
-**/
- UINT32 MemorySpdPtr10;
-
-/** Offset 0x0078 - MemorySpdPtr11
-**/
- UINT32 MemorySpdPtr11;
-
-/** Offset 0x007C - MemorySpdPtr12
-**/
- UINT32 MemorySpdPtr12;
-
-/** Offset 0x0080 - MemorySpdPtr13
-**/
- UINT32 MemorySpdPtr13;
-
-/** Offset 0x0084 - MemorySpdPtr14
-**/
- UINT32 MemorySpdPtr14;
-
-/** Offset 0x0088 - MemorySpdPtr15
-**/
- UINT32 MemorySpdPtr15;
-
-/** Offset 0x008C - RcompResistor settings
- Indicates RcompResistor settings: Board-dependent
-**/
- UINT16 RcompResistor;
-
-/** Offset 0x008E - RcompTarget settings
- RcompTarget settings: board-dependent
-**/
- UINT16 RcompTarget[5];
-
-/** Offset 0x0098 - DqsMapCpu2DramCh0
-**/
- UINT8 DqsMapCpu2DramCh0[2];
-
-/** Offset 0x009A - DqsMapCpu2DramCh1
-**/
- UINT8 DqsMapCpu2DramCh1[2];
-
-/** Offset 0x009C - DqsMapCpu2DramCh2
-**/
- UINT8 DqsMapCpu2DramCh2[2];
-
-/** Offset 0x009E - DqsMapCpu2DramCh3
-**/
- UINT8 DqsMapCpu2DramCh3[2];
-
-/** Offset 0x00A0 - DqsMapCpu2DramCh4
-**/
- UINT8 DqsMapCpu2DramCh4[2];
-
-/** Offset 0x00A2 - DqsMapCpu2DramCh5
-**/
- UINT8 DqsMapCpu2DramCh5[2];
-
-/** Offset 0x00A4 - DqsMapCpu2DramCh6
-**/
- UINT8 DqsMapCpu2DramCh6[2];
-
-/** Offset 0x00A6 - DqsMapCpu2DramCh7
-**/
- UINT8 DqsMapCpu2DramCh7[2];
-
-/** Offset 0x00A8 - DqMapCpu2DramCh0
-**/
- UINT8 DqMapCpu2DramCh0[16];
-
-/** Offset 0x00B8 - DqMapCpu2DramCh1
-**/
- UINT8 DqMapCpu2DramCh1[16];
-
-/** Offset 0x00C8 - DqMapCpu2DramCh2
-**/
- UINT8 DqMapCpu2DramCh2[16];
-
-/** Offset 0x00D8 - DqMapCpu2DramCh3
-**/
- UINT8 DqMapCpu2DramCh3[16];
-
-/** Offset 0x00E8 - DqMapCpu2DramCh4
-**/
- UINT8 DqMapCpu2DramCh4[16];
-
-/** Offset 0x00F8 - DqMapCpu2DramCh5
-**/
- UINT8 DqMapCpu2DramCh5[16];
-
-/** Offset 0x0108 - DqMapCpu2DramCh6
-**/
- UINT8 DqMapCpu2DramCh6[16];
-
-/** Offset 0x0118 - DqMapCpu2DramCh7
-**/
- UINT8 DqMapCpu2DramCh7[16];
-
-/** Offset 0x0128 - Dqs Pins Interleaved Setting
- Indicates DqPinsInterleaved setting: board-dependent
- $EN_DIS
-**/
- UINT8 DqPinsInterleaved;
-
-/** Offset 0x0129 - Reserved
-**/
- UINT8 Reserved1[7];
-
-/** Offset 0x0130 - Tseg Size
- Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
- 0x0400000:4MB, 0x01000000:16MB
-**/
- UINT32 TsegSize;
-
-/** Offset 0x0134 - Reserved
-**/
- UINT8 Reserved2[3];
-
-/** Offset 0x0137 - Enable SMBus
- Enable/disable SMBus controller.
- $EN_DIS
-**/
- UINT8 SmbusEnable;
-
-/** Offset 0x0138 - Spd Address Tabl
- Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
- if SPD Address is 00
-**/
- UINT8 SpdAddressTable[16];
-
-/** Offset 0x0148 - Platform Debug Consent
- Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks
- s0ix\n
- Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix
- is viable\n
- Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users
- 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual
-**/
- UINT8 PlatformDebugConsent;
-
-/** Offset 0x0149 - Reserved
-**/
- UINT8 Reserved3[14];
-
-/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table
- 0=Disable/Clear, 1=Enable/Set
- $EN_DIS
-**/
- UINT8 X2ApicOptOut;
-
-/** Offset 0x0158 - Reserved
-**/
- UINT8 Reserved4[40];
-
-/** Offset 0x0180 - Disable VT-d
- 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
- $EN_DIS
-**/
- UINT8 VtdDisable;
-
-/** Offset 0x0181 - Reserved
-**/
- UINT8 Reserved5[4];
-
-/** Offset 0x0185 - Internal Graphics Pre-allocated Memory
- Size of memory preallocated for internal graphics.
- 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
- 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
- 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
-**/
- UINT8 IgdDvmt50PreAlloc;
-
-/** Offset 0x0186 - Internal Graphics
- Enable/disable internal graphics.
- $EN_DIS
-**/
- UINT8 InternalGfx;
-
-/** Offset 0x0187 - Reserved
-**/
- UINT8 Reserved6;
-
-/** Offset 0x0188 - Board Type
- MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
- Halo, 7=UP Server
- 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
-**/
- UINT8 UserBd;
-
-/** Offset 0x0189 - Reserved
-**/
- UINT8 Reserved7[3];
-
-/** Offset 0x018C - SA GV
- System Agent dynamic frequency support and when enabled memory will be training
- at three different frequencies.
- 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
-**/
- UINT8 SaGv;
-
-/** Offset 0x018D - Reserved
-**/
- UINT8 Reserved8[2];
-
-/** Offset 0x018F - Rank Margin Tool
- Enable/disable Rank Margin Tool.
- $EN_DIS
-**/
- UINT8 RMT;
-
-/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control
- Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch0;
-
-/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control
- Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch1;
-
-/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control
- Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch2;
-
-/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control
- Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc0Ch3;
-
-/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control
- Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch0;
-
-/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control
- Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch1;
-
-/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control
- Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch2;
-
-/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control
- Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmMc1Ch3;
-
-/** Offset 0x0198 - Reserved
-**/
- UINT8 Reserved9[2];
-
-/** Offset 0x019A - Memory Reference Clock
- 100MHz, 133MHz.
- 0:133MHz, 1:100MHz
-**/
- UINT8 RefClk;
-
-/** Offset 0x019B - Reserved
-**/
- UINT8 Reserved10[22];
-
-/** Offset 0x01B1 - Enable Intel HD Audio (Azalia)
- 0: Disable, 1: Enable (Default) Azalia controller
- $EN_DIS
-**/
- UINT8 PchHdaEnable;
-
-/** Offset 0x01B2 - Enable PCH ISH Controller
- 0: Disable, 1: Enable (Default) ISH Controller
- $EN_DIS
-**/
- UINT8 PchIshEnable;
-
-/** Offset 0x01B3 - Reserved
-**/
- UINT8 Reserved11[107];
-
-/** Offset 0x021E - IMGU CLKOUT Configuration
- The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 ImguClkOutEn[6];
-
-/** Offset 0x0224 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 CpuPcieRpEnableMask;
-
-/** Offset 0x0228 - Reserved
-**/
- UINT8 Reserved12;
-
-/** Offset 0x0229 - RpClockReqMsgEnable
-**/
- UINT8 RpClockReqMsgEnable[3];
-
-/** Offset 0x022C - RpPcieThresholdBytes
-**/
- UINT8 RpPcieThresholdBytes[4];
-
-/** Offset 0x0230 - Reserved
-**/
- UINT8 Reserved13;
-
-/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device
- 0=Disabled,1(Default)=eDP, 2=MIPI DSI
- 0:Disabled, 1:eDP, 2:MIPI DSI
-**/
- UINT8 DdiPortAConfig;
-
-/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device
- 0(Default)=Disabled,1=eDP, 2=MIPI DSI
- 0:Disabled, 1:eDP, 2:MIPI DSI
-**/
- UINT8 DdiPortBConfig;
-
-/** Offset 0x0233 - Enable or disable HPD of DDI port A
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortAHpd;
-
-/** Offset 0x0234 - Enable or disable HPD of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBHpd;
-
-/** Offset 0x0235 - Enable or disable HPD of DDI port C
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCHpd;
-
-/** Offset 0x0236 - Enable or disable HPD of DDI port 1
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPort1Hpd;
-
-/** Offset 0x0237 - Enable or disable HPD of DDI port 2
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort2Hpd;
-
-/** Offset 0x0238 - Enable or disable HPD of DDI port 3
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort3Hpd;
-
-/** Offset 0x0239 - Enable or disable HPD of DDI port 4
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort4Hpd;
-
-/** Offset 0x023A - Enable or disable DDC of DDI port A
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortADdc;
-
-/** Offset 0x023B - Enable or disable DDC of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBDdc;
-
-/** Offset 0x023C - Enable or disable DDC of DDI port C
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCDdc;
-
-/** Offset 0x023D - Enable DDC setting of DDI Port 1
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort1Ddc;
-
-/** Offset 0x023E - Enable DDC setting of DDI Port 2
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort2Ddc;
-
-/** Offset 0x023F - Enable DDC setting of DDI Port 3
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort3Ddc;
-
-/** Offset 0x0240 - Enable DDC setting of DDI Port 4
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPort4Ddc;
-
-/** Offset 0x0241 - Reserved
-**/
- UINT8 Reserved14[141];
-
-/** Offset 0x02CE - DMI Gen3 Root port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
-**/
- UINT8 DmiGen3RootPortPreset[8];
-
-/** Offset 0x02D6 - Reserved
-**/
- UINT8 Reserved15[150];
-
-/** Offset 0x036C - C6DRAM power gating feature
- This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
- power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
- feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
- $EN_DIS
-**/
- UINT8 EnableC6Dram;
-
-/** Offset 0x036D - Reserved
-**/
- UINT8 Reserved16[5];
-
-/** Offset 0x0372 - Hyper Threading Enable/Disable
- Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 HyperThreading;
-
-/** Offset 0x0373 - Reserved
-**/
- UINT8 Reserved17;
-
-/** Offset 0x0374 - CPU ratio value
- CPU ratio value. Valid Range 0 to 63
-**/
- UINT8 CpuRatio;
-
-/** Offset 0x0375 - Reserved
-**/
- UINT8 Reserved18[2];
-
-/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting
- <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
- 2: 400 MHz. - 3: Reserved
- 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
-**/
- UINT8 FClkFrequency;
-
-/** Offset 0x0378 - Reserved
-**/
- UINT8 Reserved19;
-
-/** Offset 0x0379 - Enable or Disable VMX
- Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 VmxEnable;
-
-/** Offset 0x037A - Reserved
-**/
- UINT8 Reserved20[20];
-
-/** Offset 0x038E - Enable or Disable TME
- Enable or Disable TME; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 TmeEnable;
-
-/** Offset 0x038F - Reserved
-**/
- UINT8 Reserved21[3];
-
-/** Offset 0x0392 - BiosGuard
- Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
- $EN_DIS
-**/
- UINT8 BiosGuard;
-
-/** Offset 0x0393
-**/
- UINT8 BiosGuardToolsInterface;
-
-/** Offset 0x0394 - Reserved
-**/
- UINT8 Reserved22[4];
-
-/** Offset 0x0398 - PrmrrSize
- Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
-**/
- UINT32 PrmrrSize;
-
-/** Offset 0x039C - SinitMemorySize
- Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
-**/
- UINT32 SinitMemorySize;
-
-/** Offset 0x03A0 - Reserved
-**/
- UINT8 Reserved23[8];
-
-/** Offset 0x03A8 - TxtHeapMemorySize
- Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
-**/
- UINT32 TxtHeapMemorySize;
-
-/** Offset 0x03AC - TxtDprMemorySize
- Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
-**/
- UINT32 TxtDprMemorySize;
-
-/** Offset 0x03B0 - Reserved
-**/
- UINT8 Reserved24[625];
-
-/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
- The number of elements in the RsvdSmbusAddressTable.
-**/
- UINT8 PchNumRsvdSmbusAddresses;
-
-/** Offset 0x0622 - Reserved
-**/
- UINT8 Reserved25[3];
-
-/** Offset 0x0625 - Usage type for ClkSrc
- 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
- (free running), 0xFF: not used
-**/
- UINT8 PcieClkSrcUsage[18];
-
-/** Offset 0x0637 - Reserved
-**/
- UINT8 Reserved26[14];
-
-/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
- Number of ClkReq signal assigned to ClkSrc
-**/
- UINT8 PcieClkSrcClkReq[18];
-
-/** Offset 0x0657 - Reserved
-**/
- UINT8 Reserved27[93];
-
-/** Offset 0x06B4 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpEnableMask;
-
-/** Offset 0x06B8 - Reserved
-**/
- UINT8 Reserved28[2];
-
-/** Offset 0x06BA - Enable HD Audio Link
- Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkHdaEnable;
-
-/** Offset 0x06BB - Reserved
-**/
- UINT8 Reserved29[3];
-
-/** Offset 0x06BE - Enable HD Audio DMIC_N Link
- Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
-**/
- UINT8 PchHdaAudioLinkDmicEnable[2];
-
-/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
- Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
-**/
- UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-
-/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing
- Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
-**/
- UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-
-/** Offset 0x06D0 - Enable HD Audio DSP
- Enable/disable HD Audio DSP feature.
- $EN_DIS
-**/
- UINT8 PchHdaDspEnable;
-
-/** Offset 0x06D1 - Reserved
-**/
- UINT8 Reserved30[3];
-
-/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
- Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
-**/
- UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-
-/** Offset 0x06DC - Enable HD Audio SSP0 Link
- Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
-**/
- UINT8 PchHdaAudioLinkSspEnable[6];
-
-/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link
- Enable/disable HD Audio SNDW#N link. Muxed with HDA.
-**/
- UINT8 PchHdaAudioLinkSndwEnable[4];
-
-/** Offset 0x06E6 - iDisp-Link Frequency
- iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
- 4: 96MHz, 3: 48MHz
-**/
- UINT8 PchHdaIDispLinkFrequency;
-
-/** Offset 0x06E7 - iDisp-Link T-mode
- iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
- 0: 2T, 2: 4T, 3: 8T, 4: 16T
-**/
- UINT8 PchHdaIDispLinkTmode;
-
-/** Offset 0x06E8 - iDisplay Audio Codec disconnection
- 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
- $EN_DIS
-**/
- UINT8 PchHdaIDispCodecDisconnect;
-
-/** Offset 0x06E9 - Debug Interfaces
- Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
- BIT2 - Not used.
-**/
- UINT8 PcdDebugInterfaceFlags;
-
-/** Offset 0x06EA - Serial Io Uart Debug Controller Number
- Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
- Core interface, it cannot be used for debug purpose.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 SerialIoUartDebugControllerNumber;
-
-/** Offset 0x06EB - Reserved
-**/
- UINT8 Reserved31[13];
-
-/** Offset 0x06F8 - ISA Serial Base selection
- Select ISA Serial Base address. Default is 0x3F8.
- 0:0x3F8, 1:0x2F8
-**/
- UINT8 PcdIsaSerialUartBase;
-
-/** Offset 0x06F9 - Reserved
-**/
- UINT8 Reserved32[4];
-
-/** Offset 0x06FD - MRC Safe Config
- Enables/Disable MRC Safe Config
- $EN_DIS
-**/
- UINT8 MrcSafeConfig;
-
-/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable
- Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie0En;
-
-/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable
- Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie1En;
-
-/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable
- Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie2En;
-
-/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable
- Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssItbtPcie3En;
-
-/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable
- Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
- $EN_DIS
-**/
- UINT8 TcssXhciEn;
-
-/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable
- Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
- $EN_DIS
-**/
- UINT8 TcssXdciEn;
-
-/** Offset 0x0704 - TCSS DMA0 Enable
- Set TCSS DMA0. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssDma0En;
-
-/** Offset 0x0705 - TCSS DMA1 Enable
- Set TCSS DMA1. 0:Disabled 1:Enabled
- $EN_DIS
-**/
- UINT8 TcssDma1En;
-
-/** Offset 0x0706 - Reserved
-**/
- UINT8 Reserved33[2];
-
-/** Offset 0x0708 - Early Command Training
- Enables/Disable Early Command Training
- $EN_DIS
-**/
- UINT8 ECT;
-
-/** Offset 0x0709 - Reserved
-**/
- UINT8 Reserved34[65];
-
-/** Offset 0x074A - Ch Hash Mask
- Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
- BITS [19:6] Default is 0x30CC
-**/
- UINT16 ChHashMask;
-
-/** Offset 0x074C - Reserved
-**/
- UINT8 Reserved35[66];
-
-/** Offset 0x078E - PcdSerialDebugLevel
- Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
- Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
- Info & Verbose.
- 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
- Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
-**/
- UINT8 PcdSerialDebugLevel;
-
-/** Offset 0x078F - Reserved
-**/
- UINT8 Reserved36[2];
-
-/** Offset 0x0791 - Safe Mode Support
- This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
- $EN_DIS
-**/
- UINT8 SafeMode;
-
-/** Offset 0x0792 - Reserved
-**/
- UINT8 Reserved37[2];
-
-/** Offset 0x0794 - TCSS USB Port Enable
- Bitmap for per port enabling
-**/
- UINT8 UsbTcPortEnPreMem;
-
-/** Offset 0x0795 - Reserved
-**/
- UINT8 Reserved38[33];
-
-/** Offset 0x07B6 - Command Pins Mapping
- BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
- 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
-**/
- UINT8 Lp5CccConfig;
-
-/** Offset 0x07B7 - Reserved
-**/
- UINT8 Reserved39[12];
-
-/** Offset 0x07C3 - Skip external display device scanning
- Enable: Do not scan for external display device, Disable (Default): Scan external
- display devices
- $EN_DIS
-**/
- UINT8 SkipExtGfxScan;
-
-/** Offset 0x07C4 - Reserved
-**/
- UINT8 Reserved40;
-
-/** Offset 0x07C5 - Lock PCU Thermal Management registers
- Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 LockPTMregs;
-
-/** Offset 0x07C6 - Reserved
-**/
- UINT8 Reserved41[131];
-
-/** Offset 0x0849 - Skip CPU replacement check
- Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
- $EN_DIS
-**/
- UINT8 SkipCpuReplacementCheck;
-
-/** Offset 0x084A - Reserved
-**/
- UINT8 Reserved42[292];
-
-/** Offset 0x096E - Serial Io Uart Debug Mode
- Select SerialIo Uart Controller mode
- 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
-**/
- UINT8 SerialIoUartDebugMode;
-
-/** Offset 0x096F - Reserved
-**/
- UINT8 Reserved43[185];
-
-/** Offset 0x0A28 - GPIO Override
- Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
- before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
- configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
-**/
- UINT8 GpioOverride;
-
-/** Offset 0x0A29 - Reserved
-**/
- UINT8 Reserved44[23];
-} FSP_M_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPM_ARCH_UPD FspmArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_M_CONFIG FspmConfig;
-
-/** Offset 0x0A40
-**/
- UINT8 UnusedUpdSpace25[6];
-
-/** Offset 0x0A46
-**/
- UINT16 UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
+/** @file
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Platform Reserved Memory Size
+ The minimum platform memory size required to pass control into DXE
+**/
+ UINT64 PlatformMemorySize;
+
+/** Offset 0x0048 - SPD Data Length
+ Length of SPD Data
+ 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
+**/
+ UINT16 MemorySpdDataLen;
+
+/** Offset 0x004A - Reserved
+**/
+ UINT8 Reserved0[2];
+
+/** Offset 0x004C - MemorySpdPtr00
+**/
+ UINT32 MemorySpdPtr00;
+
+/** Offset 0x0050 - MemorySpdPtr01
+**/
+ UINT32 MemorySpdPtr01;
+
+/** Offset 0x0054 - MemorySpdPtr02
+**/
+ UINT32 MemorySpdPtr02;
+
+/** Offset 0x0058 - MemorySpdPtr03
+**/
+ UINT32 MemorySpdPtr03;
+
+/** Offset 0x005C - MemorySpdPtr04
+**/
+ UINT32 MemorySpdPtr04;
+
+/** Offset 0x0060 - MemorySpdPtr05
+**/
+ UINT32 MemorySpdPtr05;
+
+/** Offset 0x0064 - MemorySpdPtr06
+**/
+ UINT32 MemorySpdPtr06;
+
+/** Offset 0x0068 - MemorySpdPtr07
+**/
+ UINT32 MemorySpdPtr07;
+
+/** Offset 0x006C - MemorySpdPtr08
+**/
+ UINT32 MemorySpdPtr08;
+
+/** Offset 0x0070 - MemorySpdPtr09
+**/
+ UINT32 MemorySpdPtr09;
+
+/** Offset 0x0074 - MemorySpdPtr10
+**/
+ UINT32 MemorySpdPtr10;
+
+/** Offset 0x0078 - MemorySpdPtr11
+**/
+ UINT32 MemorySpdPtr11;
+
+/** Offset 0x007C - MemorySpdPtr12
+**/
+ UINT32 MemorySpdPtr12;
+
+/** Offset 0x0080 - MemorySpdPtr13
+**/
+ UINT32 MemorySpdPtr13;
+
+/** Offset 0x0084 - MemorySpdPtr14
+**/
+ UINT32 MemorySpdPtr14;
+
+/** Offset 0x0088 - MemorySpdPtr15
+**/
+ UINT32 MemorySpdPtr15;
+
+/** Offset 0x008C - RcompResistor settings
+ Indicates RcompResistor settings: Board-dependent
+**/
+ UINT16 RcompResistor;
+
+/** Offset 0x008E - RcompTarget settings
+ RcompTarget settings: board-dependent
+**/
+ UINT16 RcompTarget[5];
+
+/** Offset 0x0098 - DqsMapCpu2DramCh0
+**/
+ UINT8 DqsMapCpu2DramCh0[2];
+
+/** Offset 0x009A - DqsMapCpu2DramCh1
+**/
+ UINT8 DqsMapCpu2DramCh1[2];
+
+/** Offset 0x009C - DqsMapCpu2DramCh2
+**/
+ UINT8 DqsMapCpu2DramCh2[2];
+
+/** Offset 0x009E - DqsMapCpu2DramCh3
+**/
+ UINT8 DqsMapCpu2DramCh3[2];
+
+/** Offset 0x00A0 - DqsMapCpu2DramCh4
+**/
+ UINT8 DqsMapCpu2DramCh4[2];
+
+/** Offset 0x00A2 - DqsMapCpu2DramCh5
+**/
+ UINT8 DqsMapCpu2DramCh5[2];
+
+/** Offset 0x00A4 - DqsMapCpu2DramCh6
+**/
+ UINT8 DqsMapCpu2DramCh6[2];
+
+/** Offset 0x00A6 - DqsMapCpu2DramCh7
+**/
+ UINT8 DqsMapCpu2DramCh7[2];
+
+/** Offset 0x00A8 - DqMapCpu2DramCh0
+**/
+ UINT8 DqMapCpu2DramCh0[16];
+
+/** Offset 0x00B8 - DqMapCpu2DramCh1
+**/
+ UINT8 DqMapCpu2DramCh1[16];
+
+/** Offset 0x00C8 - DqMapCpu2DramCh2
+**/
+ UINT8 DqMapCpu2DramCh2[16];
+
+/** Offset 0x00D8 - DqMapCpu2DramCh3
+**/
+ UINT8 DqMapCpu2DramCh3[16];
+
+/** Offset 0x00E8 - DqMapCpu2DramCh4
+**/
+ UINT8 DqMapCpu2DramCh4[16];
+
+/** Offset 0x00F8 - DqMapCpu2DramCh5
+**/
+ UINT8 DqMapCpu2DramCh5[16];
+
+/** Offset 0x0108 - DqMapCpu2DramCh6
+**/
+ UINT8 DqMapCpu2DramCh6[16];
+
+/** Offset 0x0118 - DqMapCpu2DramCh7
+**/
+ UINT8 DqMapCpu2DramCh7[16];
+
+/** Offset 0x0128 - Dqs Pins Interleaved Setting
+ Indicates DqPinsInterleaved setting: board-dependent
+ $EN_DIS
+**/
+ UINT8 DqPinsInterleaved;
+
+/** Offset 0x0129 - Reserved
+**/
+ UINT8 Reserved1[7];
+
+/** Offset 0x0130 - Tseg Size
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+ 0x0400000:4MB, 0x01000000:16MB
+**/
+ UINT32 TsegSize;
+
+/** Offset 0x0134 - Reserved
+**/
+ UINT8 Reserved2[3];
+
+/** Offset 0x0137 - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x0138 - Spd Address Tabl
+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+ if SPD Address is 00
+**/
+ UINT8 SpdAddressTable[16];
+
+/** Offset 0x0148 - Platform Debug Consent
+ Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks
+ s0ix\n
+ Enabled(Low Power) does not suppoert DCI OOB 4-wire with TraceHub disabled, s0ix
+ is viable\n
+ Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users
+ 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual
+**/
+ UINT8 PlatformDebugConsent;
+
+/** Offset 0x0149 - Reserved
+**/
+ UINT8 Reserved3[14];
+
+/** Offset 0x0157 - State of X2APIC_OPT_OUT bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 X2ApicOptOut;
+
+/** Offset 0x0158 - Reserved
+**/
+ UINT8 Reserved4[40];
+
+/** Offset 0x0180 - Disable VT-d
+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+ $EN_DIS
+**/
+ UINT8 VtdDisable;
+
+/** Offset 0x0181 - Reserved
+**/
+ UINT8 Reserved5[4];
+
+/** Offset 0x0185 - Internal Graphics Pre-allocated Memory
+ Size of memory preallocated for internal graphics.
+ 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
+ 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
+ 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
+**/
+ UINT8 IgdDvmt50PreAlloc;
+
+/** Offset 0x0186 - Internal Graphics
+ Enable/disable internal graphics.
+ $EN_DIS
+**/
+ UINT8 InternalGfx;
+
+/** Offset 0x0187 - Reserved
+**/
+ UINT8 Reserved6;
+
+/** Offset 0x0188 - Board Type
+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+ Halo, 7=UP Server
+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+ UINT8 UserBd;
+
+/** Offset 0x0189 - Reserved
+**/
+ UINT8 Reserved7[3];
+
+/** Offset 0x018C - SA GV
+ System Agent dynamic frequency support and when enabled memory will be training
+ at three different frequencies.
+ 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled
+**/
+ UINT8 SaGv;
+
+/** Offset 0x018D - Reserved
+**/
+ UINT8 Reserved8[2];
+
+/** Offset 0x018F - Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 RMT;
+
+/** Offset 0x0190 - Controller 0 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch0;
+
+/** Offset 0x0191 - Controller 0 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch1;
+
+/** Offset 0x0192 - Controller 0 Channel 2 DIMM Control
+ Controller 0 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch2;
+
+/** Offset 0x0193 - Controller 0 Channel 3 DIMM Control
+ Controller 0 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc0Ch3;
+
+/** Offset 0x0194 - Controller 1 Channel 0 DIMM Control
+ Controller 1 Channel 0 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch0;
+
+/** Offset 0x0195 - Controller 1 Channel 1 DIMM Control
+ Controller 1 Channel 1 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch1;
+
+/** Offset 0x0196 - Controller 1 Channel 2 DIMM Control
+ Controller 1 Channel 2 DIMM Control Support - Enable or Disable Dimms on Channel A.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch2;
+
+/** Offset 0x0197 - Controller 1 Channel 3 DIMM Control
+ Controller 1 Channel 3 DIMM Control Support - Enable or Disable Dimms on Channel B.
+ 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
+**/
+ UINT8 DisableDimmMc1Ch3;
+
+/** Offset 0x0198 - Reserved
+**/
+ UINT8 Reserved9[2];
+
+/** Offset 0x019A - Memory Reference Clock
+ 100MHz, 133MHz.
+ 0:133MHz, 1:100MHz
+**/
+ UINT8 RefClk;
+
+/** Offset 0x019B - Reserved
+**/
+ UINT8 Reserved10[22];
+
+/** Offset 0x01B1 - Enable Intel HD Audio (Azalia)
+ 0: Disable, 1: Enable (Default) Azalia controller
+ $EN_DIS
+**/
+ UINT8 PchHdaEnable;
+
+/** Offset 0x01B2 - Enable PCH ISH Controller
+ 0: Disable, 1: Enable (Default) ISH Controller
+ $EN_DIS
+**/
+ UINT8 PchIshEnable;
+
+/** Offset 0x01B3 - Reserved
+**/
+ UINT8 Reserved11[107];
+
+/** Offset 0x021E - IMGU CLKOUT Configuration
+ The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 ImguClkOutEn[6];
+
+/** Offset 0x0224 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 CpuPcieRpEnableMask;
+
+/** Offset 0x0228 - Reserved
+**/
+ UINT8 Reserved12;
+
+/** Offset 0x0229 - RpClockReqMsgEnable
+**/
+ UINT8 RpClockReqMsgEnable[3];
+
+/** Offset 0x022C - RpPcieThresholdBytes
+**/
+ UINT8 RpPcieThresholdBytes[4];
+
+/** Offset 0x0230 - Reserved
+**/
+ UINT8 Reserved13;
+
+/** Offset 0x0231 - Program GPIOs for LFP on DDI port-A device
+ 0=Disabled,1(Default)=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortAConfig;
+
+/** Offset 0x0232 - Program GPIOs for LFP on DDI port-B device
+ 0(Default)=Disabled,1=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortBConfig;
+
+/** Offset 0x0233 - Enable or disable HPD of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortAHpd;
+
+/** Offset 0x0234 - Enable or disable HPD of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBHpd;
+
+/** Offset 0x0235 - Enable or disable HPD of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCHpd;
+
+/** Offset 0x0236 - Enable or disable HPD of DDI port 1
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Hpd;
+
+/** Offset 0x0237 - Enable or disable HPD of DDI port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Hpd;
+
+/** Offset 0x0238 - Enable or disable HPD of DDI port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Hpd;
+
+/** Offset 0x0239 - Enable or disable HPD of DDI port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Hpd;
+
+/** Offset 0x023A - Enable or disable DDC of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortADdc;
+
+/** Offset 0x023B - Enable or disable DDC of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBDdc;
+
+/** Offset 0x023C - Enable or disable DDC of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCDdc;
+
+/** Offset 0x023D - Enable DDC setting of DDI Port 1
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Ddc;
+
+/** Offset 0x023E - Enable DDC setting of DDI Port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Ddc;
+
+/** Offset 0x023F - Enable DDC setting of DDI Port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Ddc;
+
+/** Offset 0x0240 - Enable DDC setting of DDI Port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Ddc;
+
+/** Offset 0x0241 - Reserved
+**/
+ UINT8 Reserved14[141];
+
+/** Offset 0x02CE - DMI Gen3 Root port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+**/
+ UINT8 DmiGen3RootPortPreset[8];
+
+/** Offset 0x02D6 - Reserved
+**/
+ UINT8 Reserved15[150];
+
+/** Offset 0x036C - C6DRAM power gating feature
+ This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
+ power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
+ feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
+ $EN_DIS
+**/
+ UINT8 EnableC6Dram;
+
+/** Offset 0x036D - Reserved
+**/
+ UINT8 Reserved16[5];
+
+/** Offset 0x0372 - Hyper Threading Enable/Disable
+ Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 HyperThreading;
+
+/** Offset 0x0373 - Reserved
+**/
+ UINT8 Reserved17;
+
+/** Offset 0x0374 - CPU ratio value
+ CPU ratio value. Valid Range 0 to 63
+**/
+ UINT8 CpuRatio;
+
+/** Offset 0x0375 - Reserved
+**/
+ UINT8 Reserved18[2];
+
+/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting
+ <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
+ 2: 400 MHz. - 3: Reserved
+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+ UINT8 FClkFrequency;
+
+/** Offset 0x0378 - Reserved
+**/
+ UINT8 Reserved19;
+
+/** Offset 0x0379 - Enable or Disable VMX
+ Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x037A - Reserved
+**/
+ UINT8 Reserved20[20];
+
+/** Offset 0x038E - Enable or Disable TME
+ Enable or Disable TME; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TmeEnable;
+
+/** Offset 0x038F - Reserved
+**/
+ UINT8 Reserved21[3];
+
+/** Offset 0x0392 - BiosGuard
+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 BiosGuard;
+
+/** Offset 0x0393
+**/
+ UINT8 BiosGuardToolsInterface;
+
+/** Offset 0x0394 - Reserved
+**/
+ UINT8 Reserved22[4];
+
+/** Offset 0x0398 - PrmrrSize
+ Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x039C - SinitMemorySize
+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+ UINT32 SinitMemorySize;
+
+/** Offset 0x03A0 - Reserved
+**/
+ UINT8 Reserved23[8];
+
+/** Offset 0x03A8 - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x03AC - TxtDprMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
+**/
+ UINT32 TxtDprMemorySize;
+
+/** Offset 0x03B0 - Reserved
+**/
+ UINT8 Reserved24[625];
+
+/** Offset 0x0621 - Number of RsvdSmbusAddressTable.
+ The number of elements in the RsvdSmbusAddressTable.
+**/
+ UINT8 PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0622 - Reserved
+**/
+ UINT8 Reserved25[3];
+
+/** Offset 0x0625 - Usage type for ClkSrc
+ 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
+ (free running), 0xFF: not used
+**/
+ UINT8 PcieClkSrcUsage[18];
+
+/** Offset 0x0637 - Reserved
+**/
+ UINT8 Reserved26[14];
+
+/** Offset 0x0645 - ClkReq-to-ClkSrc mapping
+ Number of ClkReq signal assigned to ClkSrc
+**/
+ UINT8 PcieClkSrcClkReq[18];
+
+/** Offset 0x0657 - Reserved
+**/
+ UINT8 Reserved27[93];
+
+/** Offset 0x06B4 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpEnableMask;
+
+/** Offset 0x06B8 - Reserved
+**/
+ UINT8 Reserved28[2];
+
+/** Offset 0x06BA - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHdaEnable;
+
+/** Offset 0x06BB - Reserved
+**/
+ UINT8 Reserved29[3];
+
+/** Offset 0x06BE - Enable HD Audio DMIC_N Link
+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+**/
+ UINT8 PchHdaAudioLinkDmicEnable[2];
+
+/** Offset 0x06C0 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+ Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
+
+/** Offset 0x06C8 - DMIC<N> ClkB Pin Muxing
+ Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
+
+/** Offset 0x06D0 - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x06D1 - Reserved
+**/
+ UINT8 Reserved30[3];
+
+/** Offset 0x06D4 - DMIC<N> Data Pin Muxing
+ Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
+**/
+ UINT32 PchHdaAudioLinkDmicDataPinMux[2];
+
+/** Offset 0x06DC - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
+**/
+ UINT8 PchHdaAudioLinkSspEnable[6];
+
+/** Offset 0x06E2 - Enable HD Audio SoundWire#N Link
+ Enable/disable HD Audio SNDW#N link. Muxed with HDA.
+**/
+ UINT8 PchHdaAudioLinkSndwEnable[4];
+
+/** Offset 0x06E6 - iDisp-Link Frequency
+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+ 4: 96MHz, 3: 48MHz
+**/
+ UINT8 PchHdaIDispLinkFrequency;
+
+/** Offset 0x06E7 - iDisp-Link T-mode
+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ 0: 2T, 2: 4T, 3: 8T, 4: 16T
+**/
+ UINT8 PchHdaIDispLinkTmode;
+
+/** Offset 0x06E8 - iDisplay Audio Codec disconnection
+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+ $EN_DIS
+**/
+ UINT8 PchHdaIDispCodecDisconnect;
+
+/** Offset 0x06E9 - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x06EA - Serial Io Uart Debug Controller Number
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 SerialIoUartDebugControllerNumber;
+
+/** Offset 0x06EB - Reserved
+**/
+ UINT8 Reserved31[13];
+
+/** Offset 0x06F8 - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x06F9 - Reserved
+**/
+ UINT8 Reserved32[4];
+
+/** Offset 0x06FD - MRC Safe Config
+ Enables/Disable MRC Safe Config
+ $EN_DIS
+**/
+ UINT8 MrcSafeConfig;
+
+/** Offset 0x06FE - TCSS Thunderbolt PCIE Root Port 0 Enable
+ Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie0En;
+
+/** Offset 0x06FF - TCSS Thunderbolt PCIE Root Port 1 Enable
+ Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie1En;
+
+/** Offset 0x0700 - TCSS Thunderbolt PCIE Root Port 2 Enable
+ Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie2En;
+
+/** Offset 0x0701 - TCSS Thunderbolt PCIE Root Port 3 Enable
+ Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssItbtPcie3En;
+
+/** Offset 0x0702 - TCSS USB HOST (xHCI) Enable
+ Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
+ $EN_DIS
+**/
+ UINT8 TcssXhciEn;
+
+/** Offset 0x0703 - TCSS USB DEVICE (xDCI) Enable
+ Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
+ $EN_DIS
+**/
+ UINT8 TcssXdciEn;
+
+/** Offset 0x0704 - TCSS DMA0 Enable
+ Set TCSS DMA0. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma0En;
+
+/** Offset 0x0705 - TCSS DMA1 Enable
+ Set TCSS DMA1. 0:Disabled 1:Enabled
+ $EN_DIS
+**/
+ UINT8 TcssDma1En;
+
+/** Offset 0x0706 - Reserved
+**/
+ UINT8 Reserved33[2];
+
+/** Offset 0x0708 - Early Command Training
+ Enables/Disable Early Command Training
+ $EN_DIS
+**/
+ UINT8 ECT;
+
+/** Offset 0x0709 - Reserved
+**/
+ UINT8 Reserved34[65];
+
+/** Offset 0x074A - Ch Hash Mask
+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+ BITS [19:6] Default is 0x30CC
+**/
+ UINT16 ChHashMask;
+
+/** Offset 0x074C - Reserved
+**/
+ UINT8 Reserved35[66];
+
+/** Offset 0x078E - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x078F - Reserved
+**/
+ UINT8 Reserved36[2];
+
+/** Offset 0x0791 - Safe Mode Support
+ This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
+ $EN_DIS
+**/
+ UINT8 SafeMode;
+
+/** Offset 0x0792 - Reserved
+**/
+ UINT8 Reserved37[2];
+
+/** Offset 0x0794 - TCSS USB Port Enable
+ Bitmap for per port enabling
+**/
+ UINT8 UsbTcPortEnPreMem;
+
+/** Offset 0x0795 - Reserved
+**/
+ UINT8 Reserved38[33];
+
+/** Offset 0x07B6 - Command Pins Mapping
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
+**/
+ UINT8 Lp5CccConfig;
+
+/** Offset 0x07B7 - Reserved
+**/
+ UINT8 Reserved39[12];
+
+/** Offset 0x07C3 - Skip external display device scanning
+ Enable: Do not scan for external display device, Disable (Default): Scan external
+ display devices
+ $EN_DIS
+**/
+ UINT8 SkipExtGfxScan;
+
+/** Offset 0x07C4 - Reserved
+**/
+ UINT8 Reserved40;
+
+/** Offset 0x07C5 - Lock PCU Thermal Management registers
+ Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
+ $EN_DIS
+**/
+ UINT8 LockPTMregs;
+
+/** Offset 0x07C6 - Reserved
+**/
+ UINT8 Reserved41[131];
+
+/** Offset 0x0849 - Skip CPU replacement check
+ Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+ $EN_DIS
+**/
+ UINT8 SkipCpuReplacementCheck;
+
+/** Offset 0x084A - Reserved
+**/
+ UINT8 Reserved42[292];
+
+/** Offset 0x096E - Serial Io Uart Debug Mode
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartDebugMode;
+
+/** Offset 0x096F - Reserved
+**/
+ UINT8 Reserved43[185];
+
+/** Offset 0x0A28 - GPIO Override
+ Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
+ before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
+ configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
+**/
+ UINT8 GpioOverride;
+
+/** Offset 0x0A29 - Reserved
+**/
+ UINT8 Reserved44[23];
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPM_ARCH_UPD FspmArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_M_CONFIG FspmConfig;
+
+/** Offset 0x0A40
+**/
+ UINT8 UnusedUpdSpace25[6];
+
+/** Offset 0x0A46
+**/
+ UINT16 UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
index 8a92e001af..cb3c95838c 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
@@ -1,895 +1,895 @@
-/** @file
-
-Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
-
-/** Fsp S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Reserved
-**/
- UINT8 Reserved0[16];
-
-/** Offset 0x0050 - Graphics Configuration Ptr
- Points to VBT
-**/
- UINT32 GraphicsConfigPtr;
-
-/** Offset 0x0054 - Enable Device 4
- Enable/disable Device 4
- $EN_DIS
-**/
- UINT8 Device4Enable;
-
-/** Offset 0x0055 - Reserved
-**/
- UINT8 Reserved1[3];
-
-/** Offset 0x0058 - MicrocodeRegionBase
- Memory Base of Microcode Updates
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x005C - MicrocodeRegionSize
- Size of Microcode Updates
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0060 - Reserved
-**/
- UINT8 Reserved2;
-
-/** Offset 0x0061 - Enable SATA SALP Support
- Enable/disable SATA Aggressive Link Power Management.
- $EN_DIS
-**/
- UINT8 SataSalpSupport;
-
-/** Offset 0x0062 - Enable SATA ports
- Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
- and so on.
-**/
- UINT8 SataPortsEnable[8];
-
-/** Offset 0x006A - Enable SATA DEVSLP Feature
- Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
- port, byte0 for port0, byte1 for port1, and so on.
-**/
- UINT8 SataPortsDevSlp[8];
-
-/** Offset 0x0072 - Reserved
-**/
- UINT8 Reserved3[34];
-
-/** Offset 0x0094 - Enable USB2 ports
- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb20Enable[16];
-
-/** Offset 0x00A4 - Enable USB3 ports
- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb30Enable[10];
-
-/** Offset 0x00AE - Enable xDCI controller
- Enable/disable to xDCI controller.
- $EN_DIS
-**/
- UINT8 XdciEnable;
-
-/** Offset 0x00AF - Reserved
-**/
- UINT8 Reserved4[26];
-
-/** Offset 0x00C9 - Enable SATA
- Enable/disable SATA controller.
- $EN_DIS
-**/
- UINT8 SataEnable;
-
-/** Offset 0x00CA - SATA Mode
- Select SATA controller working mode.
- 0:AHCI, 1:RAID
-**/
- UINT8 SataMode;
-
-/** Offset 0x00CB - SPIn Device Mode
- Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
- modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
-**/
- UINT8 SerialIoSpiMode[7];
-
-/** Offset 0x00D2 - Reserved
-**/
- UINT8 Reserved5[35];
-
-/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW
- Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
- SPI1, ... Available options: 0:HW, 1:SW
-**/
- UINT8 SerialIoSpiCsMode[7];
-
-/** Offset 0x00FC - SPIn Default Chip Select State Low/High
- Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
- Available options: 0:Low, 1:High
-**/
- UINT8 SerialIoSpiCsState[7];
-
-/** Offset 0x0103 - UARTn Device Mode
- Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
- modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
- 4:SerialIoUartSkipInit
-**/
- UINT8 SerialIoUartMode[7];
-
-/** Offset 0x010A - Reserved
-**/
- UINT8 Reserved6[65];
-
-/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines
- Enables UART hardware flow control, CTS and RTS lines.
-**/
- UINT8 SerialIoUartAutoFlow[7];
-
-/** Offset 0x0152 - Reserved
-**/
- UINT8 Reserved7[2];
-
-/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
- Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
- for possible values.
-**/
- UINT32 SerialIoUartRtsPinMuxPolicy[7];
-
-/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy
- Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
- for possible values.
-**/
- UINT32 SerialIoUartCtsPinMuxPolicy[7];
-
-/** Offset 0x018C - SerialIoUartRxPinMuxPolicy
- Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
- possible values.
-**/
- UINT32 SerialIoUartRxPinMuxPolicy[7];
-
-/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy
- Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
- possible values.
-**/
- UINT32 SerialIoUartTxPinMuxPolicy[7];
-
-/** Offset 0x01C4 - UART Number For Debug Purpose
- UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
- 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
- for debug purpose.
- 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
-**/
- UINT8 SerialIoDebugUartNumber;
-
-/** Offset 0x01C5 - Reserved
-**/
- UINT8 Reserved8[7];
-
-/** Offset 0x01CC - I2Cn Device Mode
- Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
- modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
-**/
- UINT8 SerialIoI2cMode[8];
-
-/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing
- Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
- possible values.
-**/
- UINT32 PchSerialIoI2cSdaPinMux[8];
-
-/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing
- Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
- possible values.
-**/
- UINT32 PchSerialIoI2cSclPinMux[8];
-
-/** Offset 0x0214 - Reserved
-**/
- UINT8 Reserved9[192];
-
-/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias
- USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
-**/
- UINT8 Usb2PhyPetxiset[16];
-
-/** Offset 0x02E4 - USB Per Port HS Transmitter Bias
- USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
-**/
- UINT8 Usb2PhyTxiset[16];
-
-/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis
- USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
- 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
-**/
- UINT8 Usb2PhyPredeemp[16];
-
-/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis
- USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
- One byte for each port.
-**/
- UINT8 Usb2PhyPehalfbit[16];
-
-/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmphEnable[10];
-
-/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
- <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmph[10];
-
-/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-
-/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment
- USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
- = 00h</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmp[10];
-
-/** Offset 0x033C - Reserved
-**/
- UINT8 Reserved10[80];
-
-/** Offset 0x038C - Enable LAN
- Enable/disable LAN controller.
- $EN_DIS
-**/
- UINT8 PchLanEnable;
-
-/** Offset 0x038D - Reserved
-**/
- UINT8 Reserved11[11];
-
-/** Offset 0x0398 - PCIe PTM enable/disable
- Enable/disable Precision Time Measurement for PCIE Root Ports.
-**/
- UINT8 PciePtm[28];
-
-/** Offset 0x03B4 - Reserved
-**/
- UINT8 Reserved12[81];
-
-/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to low current mode voltage.
-**/
- UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
-
-/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
- This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
- to retention mode voltage.
-**/
- UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
-
-/** Offset 0x0407 - Reserved
-**/
- UINT8 Reserved13;
-
-/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
- This field has 1us resolution. When value is 0 Transition to 0V is disabled.
-**/
- UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
-
-/** Offset 0x040A - Reserved
-**/
- UINT8 Reserved14[50];
-
-/** Offset 0x043C - CNVi Configuration
- This option allows for automatic detection of Connectivity Solution. [Auto Detection]
- assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
- 0:Disable, 1:Auto
-**/
- UINT8 CnviMode;
-
-/** Offset 0x043D - Reserved
-**/
- UINT8 Reserved15;
-
-/** Offset 0x043E - CNVi BT Core
- Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
- $EN_DIS
-**/
- UINT8 CnviBtCore;
-
-/** Offset 0x043F - CNVi BT Audio Offload
- Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
- $EN_DIS
-**/
- UINT8 CnviBtAudioOffload;
-
-/** Offset 0x0440 - Reserved
-**/
- UINT8 Reserved16[4];
-
-/** Offset 0x0444 - CNVi RF_RESET pin muxing
- Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
- or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
-**/
- UINT32 CnviRfResetPinMux;
-
-/** Offset 0x0448 - CNVi CLKREQ pin muxing
- Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
- or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
- in GpioPins*.h.
-**/
- UINT32 CnviClkreqPinMux;
-
-/** Offset 0x044C - Reserved
-**/
- UINT8 Reserved17[172];
-
-/** Offset 0x04F8 - CdClock Frequency selection
- 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
- 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
- 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
- 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
-**/
- UINT8 CdClock;
-
-/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit
- <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
- Disable: FSP will NOT initialize the framebuffer.
- $EN_DIS
-**/
- UINT8 PeiGraphicsPeimInit;
-
-/** Offset 0x04FA - Enable D3 Hot in TCSS
- This policy will enable/disable D3 hot support in IOM
- $EN_DIS
-**/
- UINT8 D3HotEnable;
-
-/** Offset 0x04FB - Reserved
-**/
- UINT8 Reserved18;
-
-/** Offset 0x04FC - TypeC port GPIO setting
- GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
- in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
- = AlderLake)
-**/
- UINT32 IomTypeCPortPadCfg[8];
-
-/** Offset 0x051C - Reserved
-**/
- UINT8 Reserved19[8];
-
-/** Offset 0x0524 - Enable D3 Cold in TCSS
- This policy will enable/disable D3 cold support in IOM
- $EN_DIS
-**/
- UINT8 D3ColdEnable;
-
-/** Offset 0x0525 - Reserved
-**/
- UINT8 Reserved20[16];
-
-/** Offset 0x0535 - Enable VMD controller
- Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
- $EN_DIS
-**/
- UINT8 VmdEnable;
-
-/** Offset 0x0536 - Reserved
-**/
- UINT8 Reserved21[120];
-
-/** Offset 0x05AE - TCSS Aux Orientation Override Enable
- Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
-**/
- UINT16 TcssAuxOri;
-
-/** Offset 0x05B0 - TCSS HSL Orientation Override Enable
- Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
-**/
- UINT16 TcssHslOri;
-
-/** Offset 0x05B2 - Reserved
-**/
- UINT8 Reserved22;
-
-/** Offset 0x05B3 - ITBT Root Port Enable
- ITBT Root Port Enable, 0:Disable, 1:Enable
- 0:Disable, 1:Enable
-**/
- UINT8 ITbtPcieRootPortEn[4];
-
-/** Offset 0x05B7 - Reserved
-**/
- UINT8 Reserved23[3];
-
-/** Offset 0x05BA - ITbtConnectTopology Timeout value
- ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
- is 0-10000. 100 = 100 ms.
-**/
- UINT16 ITbtConnectTopologyTimeoutInMs;
-
-/** Offset 0x05BC - Reserved
-**/
- UINT8 Reserved24[7];
-
-/** Offset 0x05C3 - Enable/Disable PTM
- This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
- $EN_DIS
-**/
- UINT8 PtmEnabled[4];
-
-/** Offset 0x05C7 - Reserved
-**/
- UINT8 Reserved25[200];
-
-/** Offset 0x068F - Skip Multi-Processor Initialization
- When this is skipped, boot loader must initialize processors before SilicionInit
- API. </b>0: Initialize; <b>1: Skip
- $EN_DIS
-**/
- UINT8 SkipMpInit;
-
-/** Offset 0x0690 - Reserved
-**/
- UINT8 Reserved26[8];
-
-/** Offset 0x0698 - CpuMpPpi
- <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
- If not NULL, FSP will use the boot loader's implementation of multiprocessing.
- See section 5.1.4 of the FSP Integration Guide for more details.
-**/
- UINT32 CpuMpPpi;
-
-/** Offset 0x069C - Reserved
-**/
- UINT8 Reserved27[70];
-
-/** Offset 0x06E2 - Enable Power Optimizer
- Enable DMI Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 PchPwrOptEnable;
-
-/** Offset 0x06E3 - Reserved
-**/
- UINT8 Reserved28[33];
-
-/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
- Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshSpiCs0Enable[1];
-
-/** Offset 0x0705 - Reserved
-**/
- UINT8 Reserved29[2];
-
-/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
- Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshSpiEnable[1];
-
-/** Offset 0x0708 - Enable PCH ISH UART pins assigned
- Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshUartEnable[2];
-
-/** Offset 0x070A - Enable PCH ISH I2C pins assigned
- Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshI2cEnable[3];
-
-/** Offset 0x070D - Enable PCH ISH GP pins assigned
- Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
-**/
- UINT8 PchIshGpEnable[8];
-
-/** Offset 0x0715 - Reserved
-**/
- UINT8 Reserved30[2];
-
-/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
- Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
- protection.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosLock;
-
-/** Offset 0x0718 - Reserved
-**/
- UINT8 Reserved31[2];
-
-/** Offset 0x071A - RTC Cmos Memory Lock
- Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
- and and lower 128-byte bank of RTC RAM.
- $EN_DIS
-**/
- UINT8 RtcMemoryLock;
-
-/** Offset 0x071B - Enable PCIE RP HotPlug
- Indicate whether the root port is hot plug available.
-**/
- UINT8 PcieRpHotPlug[28];
-
-/** Offset 0x0737 - Reserved
-**/
- UINT8 Reserved32[56];
-
-/** Offset 0x076F - Enable PCIE RP Clk Req Detect
- Probe CLKREQ# signal before enabling CLKREQ# based power management.
-**/
- UINT8 PcieRpClkReqDetect[28];
-
-/** Offset 0x078B - PCIE RP Advanced Error Report
- Indicate whether the Advanced Error Reporting is enabled.
-**/
- UINT8 PcieRpAdvancedErrorReporting[28];
-
-/** Offset 0x07A7 - Reserved
-**/
- UINT8 Reserved33[196];
-
-/** Offset 0x086B - PCIE RP Max Payload
- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
-**/
- UINT8 PcieRpMaxPayload[28];
-
-/** Offset 0x0887 - Touch Host Controller Port 0 Assignment
- Assign THC Port 0
- 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
-**/
- UINT8 ThcPort0Assignment;
-
-/** Offset 0x0888 - Reserved
-**/
- UINT8 Reserved34[5];
-
-/** Offset 0x088D - Touch Host Controller Port 1 Assignment
- Assign THC Port 1
- 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
-**/
- UINT8 ThcPort1Assignment;
-
-/** Offset 0x088E - Reserved
-**/
- UINT8 Reserved35[91];
-
-/** Offset 0x08E9 - PCIE RP Aspm
- The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
- PchPcieAspmAutoConfig.
-**/
- UINT8 PcieRpAspm[28];
-
-/** Offset 0x0905 - PCIE RP L1 Substates
- The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
- Default is PchPcieL1SubstatesL1_1_2.
-**/
- UINT8 PcieRpL1Substates[28];
-
-/** Offset 0x0921 - Reserved
-**/
- UINT8 Reserved36[28];
-
-/** Offset 0x093D - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 PcieRpLtrEnable[28];
-
-/** Offset 0x0959 - Reserved
-**/
- UINT8 Reserved37[132];
-
-/** Offset 0x09DD - PCH Sata Pwr Opt Enable
- SATA Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 SataPwrOptEnable;
-
-/** Offset 0x09DE - Reserved
-**/
- UINT8 Reserved38[50];
-
-/** Offset 0x0A10 - Enable SATA Port DmVal
- DITO multiplier. Default is 15.
-**/
- UINT8 SataPortsDmVal[8];
-
-/** Offset 0x0A18 - Enable SATA Port DmVal
- DEVSLP Idle Timeout (DITO), Default is 625.
-**/
- UINT16 SataPortsDitoVal[8];
-
-/** Offset 0x0A28 - Reserved
-**/
- UINT8 Reserved39[62];
-
-/** Offset 0x0A66 - USB2 Port Over Current Pin
- Describe the specific over current pin number of USB 2.0 Port N.
-**/
- UINT8 Usb2OverCurrentPin[16];
-
-/** Offset 0x0A76 - USB3 Port Over Current Pin
- Describe the specific over current pin number of USB 3.0 Port N.
-**/
- UINT8 Usb3OverCurrentPin[10];
-
-/** Offset 0x0A80 - Reserved
-**/
- UINT8 Reserved40[16];
-
-/** Offset 0x0A90 - Enable 8254 Static Clock Gating
- Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
- might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
- legacy OS using 8254 timer. Also enable this while S0ix is enabled.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGating;
-
-/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3
- This is only applicable when Enable8254ClockGating is disabled. FSP will do the
- 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
- avoids the SMI requirement for the programming.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGatingOnS3;
-
-/** Offset 0x0A92 - Reserved
-**/
- UINT8 Reserved41;
-
-/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
- Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
- Default is 0: Disabled
- 0: Disabled, 1: Dynamic Configuration
-**/
- UINT8 HybridStorageMode;
-
-/** Offset 0x0A94 - Reserved
-**/
- UINT8 Reserved42[93];
-
-/** Offset 0x0AF1 - Enable PS_ON.
- PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
- target that will be required by the California Energy Commission (CEC). When FALSE,
- PS_ON is to be disabled.
- $EN_DIS
-**/
- UINT8 PsOnEnable;
-
-/** Offset 0x0AF2 - Reserved
-**/
- UINT8 Reserved43[318];
-
-/** Offset 0x0C30 - RpPtmBytes
-**/
- UINT8 RpPtmBytes[4];
-
-/** Offset 0x0C34 - Reserved
-**/
- UINT8 Reserved44[95];
-
-/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
- Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
- $EN_DIS
-**/
- UINT8 PmSupport;
-
-/** Offset 0x0C94 - Reserved
-**/
- UINT8 Reserved45;
-
-/** Offset 0x0C95 - GT Frequency Limit
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
-**/
- UINT8 GtFreqMax;
-
-/** Offset 0x0C96 - Reserved
-**/
- UINT8 Reserved46[24];
-
-/** Offset 0x0CAE - Enable or Disable HWP
- Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
- 2-3:Reserved
- $EN_DIS
-**/
- UINT8 Hwp;
-
-/** Offset 0x0CAF - Reserved
-**/
- UINT8 Reserved47[8];
-
-/** Offset 0x0CB7 - TCC Activation Offset
- TCC Activation Offset. Offset from factory set TCC activation temperature at which
- the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
- Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
- <b>10</b>, For all other SKUs the recommended default are <b>0</b>
-**/
- UINT8 TccActivationOffset;
-
-/** Offset 0x0CB8 - Reserved
-**/
- UINT8 Reserved48[34];
-
-/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
- Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Cx;
-
-/** Offset 0x0CDB - Reserved
-**/
- UINT8 Reserved49[196];
-
-/** Offset 0x0D9F - Enable LOCKDOWN SMI
- Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
- $EN_DIS
-**/
- UINT8 PchLockDownGlobalSmi;
-
-/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface
- Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosInterface;
-
-/** Offset 0x0DA1 - Unlock all GPIO pads
- Force all GPIO pads to be unlocked for debug purpose.
- $EN_DIS
-**/
- UINT8 PchUnlockGpioPads;
-
-/** Offset 0x0DA2 - Reserved
-**/
- UINT8 Reserved50[2];
-
-/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
- Latency Tolerance Reporting, Max Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxSnoopLatency[28];
-
-/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxNoSnoopLatency[28];
-
-/** Offset 0x0E14 - Reserved
-**/
- UINT8 Reserved51[313];
-
-/** Offset 0x0F4D - LpmStateEnableMask
-**/
- UINT8 LpmStateEnableMask;
-
-/** Offset 0x0F4E - Reserved
-**/
- UINT8 Reserved52[122];
-} FSP_S_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPS_ARCH_UPD FspsArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_S_CONFIG FspsConfig;
-
-/** Offset 0x0FC8
-**/
- UINT8 UnusedUpdSpace43[6];
-
-/** Offset 0x0FCE
-**/
- UINT16 UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
+/** @file
+
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+ SiPchNoInt, ///< No Interrupt Pin
+ SiPchIntA,
+ SiPchIntB,
+ SiPchIntC,
+ SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - Reserved
+**/
+ UINT8 Reserved0[16];
+
+/** Offset 0x0050 - Graphics Configuration Ptr
+ Points to VBT
+**/
+ UINT32 GraphicsConfigPtr;
+
+/** Offset 0x0054 - Enable Device 4
+ Enable/disable Device 4
+ $EN_DIS
+**/
+ UINT8 Device4Enable;
+
+/** Offset 0x0055 - Reserved
+**/
+ UINT8 Reserved1[3];
+
+/** Offset 0x0058 - MicrocodeRegionBase
+ Memory Base of Microcode Updates
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x005C - MicrocodeRegionSize
+ Size of Microcode Updates
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0060 - Reserved
+**/
+ UINT8 Reserved2;
+
+/** Offset 0x0061 - Enable SATA SALP Support
+ Enable/disable SATA Aggressive Link Power Management.
+ $EN_DIS
+**/
+ UINT8 SataSalpSupport;
+
+/** Offset 0x0062 - Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
+ and so on.
+**/
+ UINT8 SataPortsEnable[8];
+
+/** Offset 0x006A - Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
+ port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlp[8];
+
+/** Offset 0x0072 - Reserved
+**/
+ UINT8 Reserved3[34];
+
+/** Offset 0x0094 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb20Enable[16];
+
+/** Offset 0x00A4 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb30Enable[10];
+
+/** Offset 0x00AE - Enable xDCI controller
+ Enable/disable to xDCI controller.
+ $EN_DIS
+**/
+ UINT8 XdciEnable;
+
+/** Offset 0x00AF - Reserved
+**/
+ UINT8 Reserved4[26];
+
+/** Offset 0x00C9 - Enable SATA
+ Enable/disable SATA controller.
+ $EN_DIS
+**/
+ UINT8 SataEnable;
+
+/** Offset 0x00CA - SATA Mode
+ Select SATA controller working mode.
+ 0:AHCI, 1:RAID
+**/
+ UINT8 SataMode;
+
+/** Offset 0x00CB - SPIn Device Mode
+ Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+ modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
+**/
+ UINT8 SerialIoSpiMode[7];
+
+/** Offset 0x00D2 - Reserved
+**/
+ UINT8 Reserved5[35];
+
+/** Offset 0x00F5 - SPIn Default Chip Select Mode HW/SW
+ Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
+ SPI1, ... Available options: 0:HW, 1:SW
+**/
+ UINT8 SerialIoSpiCsMode[7];
+
+/** Offset 0x00FC - SPIn Default Chip Select State Low/High
+ Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
+ Available options: 0:Low, 1:High
+**/
+ UINT8 SerialIoSpiCsState[7];
+
+/** Offset 0x0103 - UARTn Device Mode
+ Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+ modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartMode[7];
+
+/** Offset 0x010A - Reserved
+**/
+ UINT8 Reserved6[65];
+
+/** Offset 0x014B - Enables UART hardware flow control, CTS and RTS lines
+ Enables UART hardware flow control, CTS and RTS lines.
+**/
+ UINT8 SerialIoUartAutoFlow[7];
+
+/** Offset 0x0152 - Reserved
+**/
+ UINT8 Reserved7[2];
+
+/** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartRtsPinMuxPolicy[7];
+
+/** Offset 0x0170 - SerialIoUartCtsPinMuxPolicy
+ Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartCtsPinMuxPolicy[7];
+
+/** Offset 0x018C - SerialIoUartRxPinMuxPolicy
+ Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
+ possible values.
+**/
+ UINT32 SerialIoUartRxPinMuxPolicy[7];
+
+/** Offset 0x01A8 - SerialIoUartTxPinMuxPolicy
+ Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
+ possible values.
+**/
+ UINT32 SerialIoUartTxPinMuxPolicy[7];
+
+/** Offset 0x01C4 - UART Number For Debug Purpose
+ UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
+ 6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
+ for debug purpose.
+ 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
+**/
+ UINT8 SerialIoDebugUartNumber;
+
+/** Offset 0x01C5 - Reserved
+**/
+ UINT8 Reserved8[7];
+
+/** Offset 0x01CC - I2Cn Device Mode
+ Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+ modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+ UINT8 SerialIoI2cMode[8];
+
+/** Offset 0x01D4 - Serial IO I2C SDA Pin Muxing
+ Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSdaPinMux[8];
+
+/** Offset 0x01F4 - Serial IO I2C SCL Pin Muxing
+ Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSclPinMux[8];
+
+/** Offset 0x0214 - Reserved
+**/
+ UINT8 Reserved9[192];
+
+/** Offset 0x02D4 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+ UINT8 Usb2PhyPetxiset[16];
+
+/** Offset 0x02E4 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+ UINT8 Usb2PhyTxiset[16];
+
+/** Offset 0x02F4 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2PhyPredeemp[16];
+
+/** Offset 0x0304 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2PhyPehalfbit[16];
+
+/** Offset 0x0314 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x031E - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmph[10];
+
+/** Offset 0x0328 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x0332 - USB 3.0 TX Output Downscale Amplitude Adjustment
+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
+ = 00h</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x033C - Reserved
+**/
+ UINT8 Reserved10[80];
+
+/** Offset 0x038C - Enable LAN
+ Enable/disable LAN controller.
+ $EN_DIS
+**/
+ UINT8 PchLanEnable;
+
+/** Offset 0x038D - Reserved
+**/
+ UINT8 Reserved11[11];
+
+/** Offset 0x0398 - PCIe PTM enable/disable
+ Enable/disable Precision Time Measurement for PCIE Root Ports.
+**/
+ UINT8 PciePtm[28];
+
+/** Offset 0x03B4 - Reserved
+**/
+ UINT8 Reserved12[81];
+
+/** Offset 0x0405 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to low current mode voltage.
+**/
+ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
+
+/** Offset 0x0406 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
+
+/** Offset 0x0407 - Reserved
+**/
+ UINT8 Reserved13;
+
+/** Offset 0x0408 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 Transition to 0V is disabled.
+**/
+ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
+
+/** Offset 0x040A - Reserved
+**/
+ UINT8 Reserved14[50];
+
+/** Offset 0x043C - CNVi Configuration
+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+ 0:Disable, 1:Auto
+**/
+ UINT8 CnviMode;
+
+/** Offset 0x043D - Reserved
+**/
+ UINT8 Reserved15;
+
+/** Offset 0x043E - CNVi BT Core
+ Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtCore;
+
+/** Offset 0x043F - CNVi BT Audio Offload
+ Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtAudioOffload;
+
+/** Offset 0x0440 - Reserved
+**/
+ UINT8 Reserved16[4];
+
+/** Offset 0x0444 - CNVi RF_RESET pin muxing
+ Select CNVi RF_RESET# pin depending on board routing. ADP-P/M: GPP_A8 = 0x2942E408(default)
+ or GPP_F4 = 0x194CE404. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
+**/
+ UINT32 CnviRfResetPinMux;
+
+/** Offset 0x0448 - CNVi CLKREQ pin muxing
+ Select CNVi CLKREQ pin depending on board routing. ADP-P/M: GPP_A9 = 0x3942E609(default)
+ or GPP_F5 = 0x394CE605. ADP-S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_*
+ in GpioPins*.h.
+**/
+ UINT32 CnviClkreqPinMux;
+
+/** Offset 0x044C - Reserved
+**/
+ UINT8 Reserved17[172];
+
+/** Offset 0x04F8 - CdClock Frequency selection
+ 0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
+ 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+ 0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
+ 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+**/
+ UINT8 CdClock;
+
+/** Offset 0x04F9 - Enable/Disable PeiGraphicsPeimInit
+ <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
+ Disable: FSP will NOT initialize the framebuffer.
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x04FA - Enable D3 Hot in TCSS
+ This policy will enable/disable D3 hot support in IOM
+ $EN_DIS
+**/
+ UINT8 D3HotEnable;
+
+/** Offset 0x04FB - Reserved
+**/
+ UINT8 Reserved18;
+
+/** Offset 0x04FC - TypeC port GPIO setting
+ GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
+ in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Adl
+ = AlderLake)
+**/
+ UINT32 IomTypeCPortPadCfg[8];
+
+/** Offset 0x051C - Reserved
+**/
+ UINT8 Reserved19[8];
+
+/** Offset 0x0524 - Enable D3 Cold in TCSS
+ This policy will enable/disable D3 cold support in IOM
+ $EN_DIS
+**/
+ UINT8 D3ColdEnable;
+
+/** Offset 0x0525 - Reserved
+**/
+ UINT8 Reserved20[16];
+
+/** Offset 0x0535 - Enable VMD controller
+ Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
+ $EN_DIS
+**/
+ UINT8 VmdEnable;
+
+/** Offset 0x0536 - Reserved
+**/
+ UINT8 Reserved21[120];
+
+/** Offset 0x05AE - TCSS Aux Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssAuxOri;
+
+/** Offset 0x05B0 - TCSS HSL Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssHslOri;
+
+/** Offset 0x05B2 - Reserved
+**/
+ UINT8 Reserved22;
+
+/** Offset 0x05B3 - ITBT Root Port Enable
+ ITBT Root Port Enable, 0:Disable, 1:Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 ITbtPcieRootPortEn[4];
+
+/** Offset 0x05B7 - Reserved
+**/
+ UINT8 Reserved23[3];
+
+/** Offset 0x05BA - ITbtConnectTopology Timeout value
+ ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
+ is 0-10000. 100 = 100 ms.
+**/
+ UINT16 ITbtConnectTopologyTimeoutInMs;
+
+/** Offset 0x05BC - Reserved
+**/
+ UINT8 Reserved24[7];
+
+/** Offset 0x05C3 - Enable/Disable PTM
+ This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
+ $EN_DIS
+**/
+ UINT8 PtmEnabled[4];
+
+/** Offset 0x05C7 - Reserved
+**/
+ UINT8 Reserved25[200];
+
+/** Offset 0x068F - Skip Multi-Processor Initialization
+ When this is skipped, boot loader must initialize processors before SilicionInit
+ API. </b>0: Initialize; <b>1: Skip
+ $EN_DIS
+**/
+ UINT8 SkipMpInit;
+
+/** Offset 0x0690 - Reserved
+**/
+ UINT8 Reserved26[8];
+
+/** Offset 0x0698 - CpuMpPpi
+ <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+ If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+ See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+ UINT32 CpuMpPpi;
+
+/** Offset 0x069C - Reserved
+**/
+ UINT8 Reserved27[70];
+
+/** Offset 0x06E2 - Enable Power Optimizer
+ Enable DMI Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 PchPwrOptEnable;
+
+/** Offset 0x06E3 - Reserved
+**/
+ UINT8 Reserved28[33];
+
+/** Offset 0x0704 - Enable PCH ISH SPI Cs0 pins assigned
+ Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiCs0Enable[1];
+
+/** Offset 0x0705 - Reserved
+**/
+ UINT8 Reserved29[2];
+
+/** Offset 0x0707 - Enable PCH ISH SPI pins assigned
+ Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiEnable[1];
+
+/** Offset 0x0708 - Enable PCH ISH UART pins assigned
+ Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshUartEnable[2];
+
+/** Offset 0x070A - Enable PCH ISH I2C pins assigned
+ Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshI2cEnable[3];
+
+/** Offset 0x070D - Enable PCH ISH GP pins assigned
+ Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshGpEnable[8];
+
+/** Offset 0x0715 - Reserved
+**/
+ UINT8 Reserved30[2];
+
+/** Offset 0x0717 - Enable LOCKDOWN BIOS LOCK
+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+ protection.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosLock;
+
+/** Offset 0x0718 - Reserved
+**/
+ UINT8 Reserved31[2];
+
+/** Offset 0x071A - RTC Cmos Memory Lock
+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and and lower 128-byte bank of RTC RAM.
+ $EN_DIS
+**/
+ UINT8 RtcMemoryLock;
+
+/** Offset 0x071B - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 PcieRpHotPlug[28];
+
+/** Offset 0x0737 - Reserved
+**/
+ UINT8 Reserved32[56];
+
+/** Offset 0x076F - Enable PCIE RP Clk Req Detect
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+ UINT8 PcieRpClkReqDetect[28];
+
+/** Offset 0x078B - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 PcieRpAdvancedErrorReporting[28];
+
+/** Offset 0x07A7 - Reserved
+**/
+ UINT8 Reserved33[196];
+
+/** Offset 0x086B - PCIE RP Max Payload
+ Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 PcieRpMaxPayload[28];
+
+/** Offset 0x0887 - Touch Host Controller Port 0 Assignment
+ Assign THC Port 0
+ 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0
+**/
+ UINT8 ThcPort0Assignment;
+
+/** Offset 0x0888 - Reserved
+**/
+ UINT8 Reserved34[5];
+
+/** Offset 0x088D - Touch Host Controller Port 1 Assignment
+ Assign THC Port 1
+ 0x0:ThcAssignmentNone, 0x1:ThcPort1AssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+ UINT8 ThcPort1Assignment;
+
+/** Offset 0x088E - Reserved
+**/
+ UINT8 Reserved35[91];
+
+/** Offset 0x08E9 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+ PchPcieAspmAutoConfig.
+**/
+ UINT8 PcieRpAspm[28];
+
+/** Offset 0x0905 - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+ Default is PchPcieL1SubstatesL1_1_2.
+**/
+ UINT8 PcieRpL1Substates[28];
+
+/** Offset 0x0921 - Reserved
+**/
+ UINT8 Reserved36[28];
+
+/** Offset 0x093D - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 PcieRpLtrEnable[28];
+
+/** Offset 0x0959 - Reserved
+**/
+ UINT8 Reserved37[132];
+
+/** Offset 0x09DD - PCH Sata Pwr Opt Enable
+ SATA Power Optimizer on PCH side.
+ $EN_DIS
+**/
+ UINT8 SataPwrOptEnable;
+
+/** Offset 0x09DE - Reserved
+**/
+ UINT8 Reserved38[50];
+
+/** Offset 0x0A10 - Enable SATA Port DmVal
+ DITO multiplier. Default is 15.
+**/
+ UINT8 SataPortsDmVal[8];
+
+/** Offset 0x0A18 - Enable SATA Port DmVal
+ DEVSLP Idle Timeout (DITO), Default is 625.
+**/
+ UINT16 SataPortsDitoVal[8];
+
+/** Offset 0x0A28 - Reserved
+**/
+ UINT8 Reserved39[62];
+
+/** Offset 0x0A66 - USB2 Port Over Current Pin
+ Describe the specific over current pin number of USB 2.0 Port N.
+**/
+ UINT8 Usb2OverCurrentPin[16];
+
+/** Offset 0x0A76 - USB3 Port Over Current Pin
+ Describe the specific over current pin number of USB 3.0 Port N.
+**/
+ UINT8 Usb3OverCurrentPin[10];
+
+/** Offset 0x0A80 - Reserved
+**/
+ UINT8 Reserved40[16];
+
+/** Offset 0x0A90 - Enable 8254 Static Clock Gating
+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+ legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGating;
+
+/** Offset 0x0A91 - Enable 8254 Static Clock Gating On S3
+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+ avoids the SMI requirement for the programming.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGatingOnS3;
+
+/** Offset 0x0A92 - Reserved
+**/
+ UINT8 Reserved41;
+
+/** Offset 0x0A93 - Hybrid Storage Detection and Configuration Mode
+ Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
+ Default is 0: Disabled
+ 0: Disabled, 1: Dynamic Configuration
+**/
+ UINT8 HybridStorageMode;
+
+/** Offset 0x0A94 - Reserved
+**/
+ UINT8 Reserved42[93];
+
+/** Offset 0x0AF1 - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
+**/
+ UINT8 PsOnEnable;
+
+/** Offset 0x0AF2 - Reserved
+**/
+ UINT8 Reserved43[318];
+
+/** Offset 0x0C30 - RpPtmBytes
+**/
+ UINT8 RpPtmBytes[4];
+
+/** Offset 0x0C34 - Reserved
+**/
+ UINT8 Reserved44[95];
+
+/** Offset 0x0C93 - Enable/Disable IGFX PmSupport
+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+ $EN_DIS
+**/
+ UINT8 PmSupport;
+
+/** Offset 0x0C94 - Reserved
+**/
+ UINT8 Reserved45;
+
+/** Offset 0x0C95 - GT Frequency Limit
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+ 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
+ 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
+ 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
+ 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
+ 0x18: 1200 Mhz
+**/
+ UINT8 GtFreqMax;
+
+/** Offset 0x0C96 - Reserved
+**/
+ UINT8 Reserved46[24];
+
+/** Offset 0x0CAE - Enable or Disable HWP
+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
+ 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x0CAF - Reserved
+**/
+ UINT8 Reserved47[8];
+
+/** Offset 0x0CB7 - TCC Activation Offset
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+ Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
+ <b>10</b>, For all other SKUs the recommended default are <b>0</b>
+**/
+ UINT8 TccActivationOffset;
+
+/** Offset 0x0CB8 - Reserved
+**/
+ UINT8 Reserved48[34];
+
+/** Offset 0x0CDA - Enable or Disable CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x0CDB - Reserved
+**/
+ UINT8 Reserved49[196];
+
+/** Offset 0x0D9F - Enable LOCKDOWN SMI
+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+ $EN_DIS
+**/
+ UINT8 PchLockDownGlobalSmi;
+
+/** Offset 0x0DA0 - Enable LOCKDOWN BIOS Interface
+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosInterface;
+
+/** Offset 0x0DA1 - Unlock all GPIO pads
+ Force all GPIO pads to be unlocked for debug purpose.
+ $EN_DIS
+**/
+ UINT8 PchUnlockGpioPads;
+
+/** Offset 0x0DA2 - Reserved
+**/
+ UINT8 Reserved50[2];
+
+/** Offset 0x0DA4 - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[28];
+
+/** Offset 0x0DDC - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxNoSnoopLatency[28];
+
+/** Offset 0x0E14 - Reserved
+**/
+ UINT8 Reserved51[313];
+
+/** Offset 0x0F4D - LpmStateEnableMask
+**/
+ UINT8 LpmStateEnableMask;
+
+/** Offset 0x0F4E - Reserved
+**/
+ UINT8 Reserved52[122];
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** Offset 0x0020
+**/
+ FSPS_ARCH_UPD FspsArchUpd;
+
+/** Offset 0x0040
+**/
+ FSP_S_CONFIG FspsConfig;
+
+/** Offset 0x0FC8
+**/
+ UINT8 UnusedUpdSpace43[6];
+
+/** Offset 0x0FCE
+**/
+ UINT16 UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-24 04:32:05 +0000