diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-01-25 10:50:39 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-01-31 05:56:07 +0000 |
| commit | 8b9f28994a1b5702ce33e62e55d1595b1a056892 (patch) | |
| tree | 6aad0300cdc18139fcdb2e15feb8b21e7cb404d2 /src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h | |
| parent | bb1e539f1440bc805dd6350ffba9646454334b2f (diff) | |
vendorcode/intel: Add UDK2017 support
This patch includes (edk2/UDK2017) all required headers for UDK2017
from EDK2 github project using below command
>> git clone https://github.com/tianocore/edk2.git vUDK2017
commit hash: 66833b2a87d98be8d81d1337c193bcbf0de47d47
Change-Id: If0d5a3fef016c67e9eed6aed9b698b3b13b930c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h')
| -rw-r--r-- | src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h new file mode 100644 index 0000000000..ef9970dc1a --- /dev/null +++ b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/CacheLib.h @@ -0,0 +1,62 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CACHE_LIB_H_ +#define _CACHE_LIB_H_ + +// +// EFI_MEMORY_CACHE_TYPE +// +typedef INT32 EFI_MEMORY_CACHE_TYPE; + +#define EFI_CACHE_UNCACHEABLE 0 +#define EFI_CACHE_WRITECOMBINING 1 +#define EFI_CACHE_WRITETHROUGH 4 +#define EFI_CACHE_WRITEPROTECTED 5 +#define EFI_CACHE_WRITEBACK 6 + +/** + Reset all the MTRRs to a known state. + + @retval EFI_SUCCESS All MTRRs have been reset successfully. + +**/ +EFI_STATUS +EFIAPI +ResetCacheAttributes ( + VOID + ); + +/** + Given the memory range and cache type, programs the MTRRs. + + @param[in] MemoryAddress Base Address of Memory to program MTRR. + @param[in] MemoryLength Length of Memory to program MTRR. + @param[in] MemoryCacheType Cache Type. + + @retval EFI_SUCCESS Mtrr are set successfully. + @retval EFI_LOAD_ERROR No empty MTRRs to use. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. + @retval others An error occurs when setting MTTR. + +**/ +EFI_STATUS +EFIAPI +SetCacheAttributes ( + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +#endif + |