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authorJon Murphy <jpmurphy@google.com>2023-09-05 10:37:05 -0600
committerKarthik Ramasubramanian <kramasub@google.com>2023-09-18 16:20:09 +0000
commit24604810252c8af7b7f350485f57a646718a5157 (patch)
treef4a1607df0a43278c5bd7166b02fed36d1affddb /src/vendorcode/google
parent277db94ebbb635f93cce426af2450ad0581485d4 (diff)
drivers/tpm: Make temp test value naming consistent
Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/vendorcode/google')
-rw-r--r--src/vendorcode/google/chromeos/cr50_enable_update.c32
-rw-r--r--src/vendorcode/google/chromeos/cse_board_reset.c8
-rw-r--r--src/vendorcode/google/chromeos/tpm2.c14
3 files changed, 27 insertions, 27 deletions
diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c
index 551c56a915..155769f545 100644
--- a/src/vendorcode/google/chromeos/cr50_enable_update.c
+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c
@@ -25,27 +25,27 @@ void __weak mainboard_prepare_cr50_reset(void) {}
*/
static int cr50_is_reset_needed(void)
{
- int ret;
+ int rc;
uint8_t tpm_mode;
- ret = tlcl_cr50_get_tpm_mode(&tpm_mode);
+ rc = tlcl_cr50_get_tpm_mode(&tpm_mode);
- if (ret == TPM_E_NO_SUCH_COMMAND) {
+ if (rc == TPM_E_NO_SUCH_COMMAND) {
printk(BIOS_INFO,
"Cr50 does not support TPM mode command\n");
/* Older Cr50 firmware, assume no Cr50 reset is required */
return 0;
}
- if (ret == TPM_E_MUST_REBOOT) {
+ if (rc == TPM_E_MUST_REBOOT) {
/*
* Cr50 indicated a reboot is required to restore TPM
* functionality.
*/
return 1;
- } else if (ret != TPM_SUCCESS) {
+ } else if (rc != TPM_SUCCESS) {
/* TPM command failed, continue booting. */
- printk(BIOS_ERR, "Attempt to get CR50 TPM mode failed: %x\n", ret);
+ printk(BIOS_ERR, "Attempt to get CR50 TPM mode failed: %x\n", rc);
return 0;
}
@@ -70,7 +70,7 @@ static int cr50_is_reset_needed(void)
static void enable_update(void *unused)
{
- int ret;
+ int rc;
int cr50_reset_reqd = 0;
uint8_t num_restored_headers;
@@ -82,23 +82,23 @@ static void enable_update(void *unused)
if (vboot_get_context()->flags & VB2_CONTEXT_FORCE_RECOVERY_MODE)
return;
- ret = tlcl_lib_init();
+ rc = tlcl_lib_init();
- if (ret != VB2_SUCCESS) {
+ if (rc != VB2_SUCCESS) {
printk(BIOS_ERR, "tlcl_lib_init() failed for CR50 update: %x\n",
- ret);
+ rc);
return;
}
timestamp_add_now(TS_TPM_ENABLE_UPDATE_START);
/* Reboot in 1000 ms if necessary. */
- ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
+ rc = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS,
&num_restored_headers);
- if (ret != TPM_SUCCESS) {
+ if (rc != TPM_SUCCESS) {
printk(BIOS_ERR, "Attempt to enable CR50 update failed: %x\n",
- ret);
+ rc);
return;
}
@@ -142,16 +142,16 @@ static void enable_update(void *unused)
* the mainboard specific code runs.
*/
if (cr50_reset_reqd) {
- ret = tlcl_cr50_immediate_reset(CR50_RESET_DELAY_MS);
+ rc = tlcl_cr50_immediate_reset(CR50_RESET_DELAY_MS);
- if (ret != TPM_SUCCESS) {
+ if (rc != TPM_SUCCESS) {
/*
* Reset request failed due to TPM error, continue
* booting but the current boot will likely end up at
* the recovery screen.
*/
printk(BIOS_ERR, "Attempt to reset CR50 failed: %x\n",
- ret);
+ rc);
return;
}
}
diff --git a/src/vendorcode/google/chromeos/cse_board_reset.c b/src/vendorcode/google/chromeos/cse_board_reset.c
index 9efc4e61f6..7d19408726 100644
--- a/src/vendorcode/google/chromeos/cse_board_reset.c
+++ b/src/vendorcode/google/chromeos/cse_board_reset.c
@@ -13,7 +13,7 @@
void cse_board_reset(void)
{
- int ret;
+ int rc;
struct cr50_firmware_version version;
if (CONFIG(CSE_RESET_CLEAR_EC_AP_IDLE_FLAG))
@@ -21,9 +21,9 @@ void cse_board_reset(void)
if (CONFIG(TPM2) && CONFIG(TPM_GOOGLE_CR50)) {
/* Initialize TPM and get the cr50 firmware version. */
- ret = tlcl_lib_init();
- if (ret != VB2_SUCCESS) {
- printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+ rc = tlcl_lib_init();
+ if (rc != VB2_SUCCESS) {
+ printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", rc);
return;
}
diff --git a/src/vendorcode/google/chromeos/tpm2.c b/src/vendorcode/google/chromeos/tpm2.c
index 98fd81522b..a28b02eeaf 100644
--- a/src/vendorcode/google/chromeos/tpm2.c
+++ b/src/vendorcode/google/chromeos/tpm2.c
@@ -7,7 +7,7 @@
static void disable_platform_hierarchy(void *unused)
{
- int ret;
+ int rc;
if (!CONFIG(TPM2))
return;
@@ -15,17 +15,17 @@ static void disable_platform_hierarchy(void *unused)
if (!CONFIG(RESUME_PATH_SAME_AS_BOOT))
return;
- ret = tlcl_lib_init();
+ rc = tlcl_lib_init();
- if (ret != VB2_SUCCESS) {
- printk(BIOS_ERR, "tlcl_lib_init() failed: %x\n", ret);
+ if (rc != VB2_SUCCESS) {
+ printk(BIOS_ERR, "tlcl_lib_init() failed: %x\n", rc);
return;
}
- ret = tlcl_disable_platform_hierarchy();
- if (ret != TPM_SUCCESS)
+ rc = tlcl_disable_platform_hierarchy();
+ if (rc != TPM_SUCCESS)
printk(BIOS_ERR, "Platform hierarchy disablement failed: %x\n",
- ret);
+ rc);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, disable_platform_hierarchy,