diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-03-01 15:11:30 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-04 14:04:46 +0000 |
| commit | cf8094cabbe517b2cced84e22a37ca3a8bcc7910 (patch) | |
| tree | 15638a4da34e6af23dd7476b473209f1cfc89496 /src/vendorcode/google/chromeos/acpi | |
| parent | e0a0c63e098db215e73d20307fe1b3190ef32891 (diff) | |
vendorcode/google/chromeos: Save VPD region into GNVS
Store the memory address of VPD region start and length for the memory
mapped RO_VPD and RW_VPD into GNVS so they can be used by ACPI code.
BUG=b:123925776
TEST=boot on sarien and verify VPD start/length in GNVS
Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/vendorcode/google/chromeos/acpi')
| -rw-r--r-- | src/vendorcode/google/chromeos/acpi/gnvs.asl | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index 52d3a0d563..69e848a1aa 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -32,4 +32,8 @@ VBTA, 32, // 0xd9a - pointer to smbios FWID MEHH, 256, // 0xd9e - Management Engine Hash RMOB, 32, // 0xdbe - RAM oops base address RMOL, 32, // 0xdc2 - RAM oops length - // 0xdc6 +ROVP, 32, // 0xdc6 - pointer to RO_VPD +ROVL, 32, // 0xdca - size of RO_VPD +RWVP, 32, // 0xdce - pointer to RW_VPD +RWVL, 32, // 0xdd2 - size of RW_VPD + // 0xdd6 |