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authorMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-08-08 12:28:03 -0500
committerFelix Held <felix-coreboot@felixheld.de>2023-08-09 19:08:33 +0000
commit66ff4fb1a565fe5f040e893bd02e52fed3ad2771 (patch)
tree3ed0fe8c1b0d4837300cca53d5648a575cf7ef13 /src/vendorcode/cavium
parentd59c79987df0498de7ee847f41782457a5320141 (diff)
soc/amd/stoneyridge: use SoC common uart ops
Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI _STA in asl since now handled by common SSDT generator. Implement wait_for_aoac_enabled() since required by SoC common code, and ensure compiled during all stages necessary. TEST=build/boot google/liara, verify console UART still functional. Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/cavium')
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