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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-09-15 16:35:56 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:31:58 +0000 |
| commit | 46ef53621265feeeebca475a0078f6bd301fcb35 (patch) | |
| tree | 97f7d3e1de612b3767da1948cabfc303cd35e104 /src/vendorcode/cavium | |
| parent | 85610d8d86de10cdb8c82b61290501ee0b3cf742 (diff) | |
soc/intel/icelake: correct wrong gpio SMI register base offsets
Reference: Intel doc# 341081-002.
Change-Id: If6e0503cc042c26c4077b8b32bb447d4e3a9bb6a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/cavium')
0 files changed, 0 insertions, 0 deletions