diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-08-30 13:51:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-01 03:06:04 +0000 |
| commit | 8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch) | |
| tree | 1550c8877877a7a9b197da65bcff76f878bee560 /src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h | |
| parent | b7a68d5b05259a07a84a546e6a7e40948ba705ac (diff) | |
{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h')
| -rw-r--r-- | src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h index fc28b58067..949a56008f 100644 --- a/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h +++ b/src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-csrs-usbdrd.h @@ -9446,7 +9446,7 @@ union bdk_usbdrdx_uctl_ctl [REF_SSP_EN] is asserted. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -9814,7 +9814,7 @@ union bdk_usbdrdx_uctl_ctl 0x07 is the only legal value. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -10106,7 +10106,7 @@ union bdk_usbdrdx_uctl_ctl [REF_SSP_EN] is asserted. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: @@ -10458,7 +10458,7 @@ union bdk_usbdrdx_uctl_ctl 0x07 is the only legal value. */ uint64_t ref_clk_div2 : 1; /**< [ 38: 38](R/W) Divides the reference clock by two before feeding it into the REF_CLK_FSEL divider. - If [REF_CLK_SEL] = 0x0, 0x1 or 0X2 then the legal values are: + If [REF_CLK_SEL] = 0x0, 0x1 or 0x2 then the legal values are: all DLMC_REF_CLK* frequencies: 0x0 is the only legal value. If [REF_CLK_SEL] = 0x4, 0x5 or 0x6 then the legal values are: |