vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments

Also document the maximum nuber of lanes for the different platforms.

Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 10 insertions, 1 deletions

diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
index 9c0e3e93ac..d5977efc6a 100644
--- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
+++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h
@@ -123,7 +123,16 @@ typedef struct __packed {
  * GPP[5:4] |  [1:0]  | PCIe, XGBE
  * GPP[7:6] |  [3:2]  | PCIe, SATA
  *
- * Dali has less DXIO connectivity than Picasso:
+ * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port
+ * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1
+ * ports. The ports can only start at logical lane numbers that are integer multiples of the
+ * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12.
+ * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the
+ * same width the one with a higher start logical lane number needs to be assigned to a higher
+ * PCIe root port number; ports of the same size don't have to be assigned to consecutive PCIe
+ * root ports though.
+ *
+ * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso:
  *
  * physical | logical | protocol
  * ---------|---------|-----------