diff options
| author | Justin TerAvest <teravest@chromium.org> | 2017-12-22 15:15:02 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-05 01:16:31 +0000 |
| commit | 922619512def4ef62c13c97b78321c6e6e610153 (patch) | |
| tree | 316f955f91a723d5c5db697bd14ae4407e76e5f8 /src/vendorcode/amd | |
| parent | a71c66a52e9ec53fed4c795c7f7409c7074363d6 (diff) | |
soc/amd/common: Allow AGESA file split for pre- and post-memory
By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).
This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.
BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.
Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/pi/00670F00/Makefile.inc | 23 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/Kconfig | 32 |
2 files changed, 54 insertions, 1 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index f1e340e751..22f3e16a56 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -123,8 +123,27 @@ ramstage-libs += $(agesa_output_path)/libagesa.a ####################################################################### +ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y) +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME) +$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_PRE_MEMORY_BINARY_PI_FILE) +$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-type := stage +$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options := --xip +# 4KiB alignment to handle any interior alignment. Current AGESA only has +# 64 byte alignment. +$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-align := 4096 + +cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME) +$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_POST_MEMORY_BINARY_PI_FILE) +$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage +$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-options := --xip +# 4KiB alignment to handle any interior alignment. Current AGESA only has +# 64 byte alignment. +$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-align := 4096 +else + cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME) $(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) + ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y) $(CONFIG_AGESA_CBFS_NAME)-type := stage $(CONFIG_AGESA_CBFS_NAME)-options := --xip @@ -134,6 +153,8 @@ $(CONFIG_AGESA_CBFS_NAME)-align := 4096 else $(CONFIG_AGESA_CBFS_NAME)-type := raw $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) -endif +endif # CONFIG_AGESA_BINARY_PI_AS_STAGE + +endif # CONFIG_AGESA_SPLIT_MEMORY_FILES endif diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 8c38a790ea..f463b7d2e9 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -58,10 +58,42 @@ config AGESA_BINARY_PI_AS_STAGE cpu address space. It's required that the file be in ELF format containing the relocations necessary for relocating at runtime. +config AGESA_SPLIT_MEMORY_FILES + bool "Split AGESA Binary PI into pre- and post-memory files." + depends on AGESA_BINARY_PI_AS_STAGE + default n + help + Specifies that AGESA is split into two binaries for pre- and + post-memory. + +config AGESA_PRE_MEMORY_BINARY_PI_FILE + string + depends on AGESA_SPLIT_MEMORY_FILES + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4 + help + Specify the binary file to use for pre-memory AMD platform + initialization. + +config AGESA_POST_MEMORY_BINARY_PI_FILE + string + depends on AGESA_SPLIT_MEMORY_FILES + default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4 + help + Specify the binary file to use for post-memory AMD platform + initialization. + config AGESA_CBFS_NAME string default "AGESA" +config AGESA_PRE_MEMORY_CBFS_NAME + string + default "AGESA_PRE_MEM" + +config AGESA_POST_MEMORY_CBFS_NAME + string + default "AGESA_POST_MEM" + config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" default 0xFFE00000 |