diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-25 05:46:56 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-27 17:00:27 +0000 |
| commit | 8e6bb80e9a71cf07be8310fc8ce582e700f69c6d (patch) | |
| tree | 7a1216eee31525493a6411dfb8d8852f5aa18ad7 /src/vendorcode/amd | |
| parent | c02b5e22a38dba429b1f058b305b6ddfdd7246b0 (diff) | |
vendorcode/amd: Satisfy clang's bracing requirements
src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error:
suggest braces around initialization of subobject
Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/vendorcode/amd')
5 files changed, 10 insertions, 10 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h index 4fd5354d05..0fd8232ead 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h @@ -4089,7 +4089,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - 0 + { 0 } }; #endif #if OPTION_DDR3 @@ -4097,7 +4097,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - 0 + { 0 } }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h index f97caa9bb2..283a972463 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h @@ -3921,7 +3921,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - 0 + { 0 } }; #endif #if OPTION_DDR3 @@ -3929,7 +3929,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - 0 + { 0 } }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h index a4d834699e..254e22e923 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h @@ -3677,7 +3677,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - 0 + { 0 } }; #endif #if OPTION_DDR3 @@ -3685,7 +3685,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - 0 + { 0 } }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h index 0cb25b8767..457c51e475 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemoryInstall.h @@ -4747,7 +4747,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - 0 + { 0 } }; #endif #if OPTION_DDR3 @@ -4755,7 +4755,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - 0 + { 0 } }; #endif /*--------------------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h index 8269742315..e2d4e03bf9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h @@ -1584,7 +1584,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - 0 + { 0 } }; #endif #if OPTION_DDR3 @@ -1592,7 +1592,7 @@ BOOLEAN MemFS3DefConstructorRet ( 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - 0 + { 0 } }; #endif /*--------------------------------------------------------------------------------------------------- |