diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-15 21:38:12 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-04-20 15:50:15 +0000 |
| commit | 4b6773a652cceee9e338614499343844d677b6b8 (patch) | |
| tree | 471d192589367e2bb3d20be93c07e180ed51022a /src/vendorcode/amd | |
| parent | 8f3e1192dfe5e3008524b587de4f06a0f289b646 (diff) | |
vc/amd/fsp/cezanne: update SMU setting section of FspmUpd.h
There was a bug in the UPDs for STAPM settings that required one UPD
field to be extended from 8 to 32 bits, so this patch is a breaking
change to the binary layout, but since the UPD struct fields for the SMU
SoC power and performance tuning parameters aren't populated by the
coreboot code yet and we added some padding after each logical section
in the UPD, this isn't expected to cause too much trouble; the only
thing that is required is that a very recent build of the FSP binaries
need to be used in combination with the new coreboot code that will
populate the struct fields in follow-up patches.
BUG=b:182297189
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39aaf64e8e1b4c0426f22ce8ed07707c2a31e61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index e51cbef143..66c8ab81b4 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -51,21 +51,21 @@ typedef struct __packed { /** Offset 0x03E8**/ uint16_t stt_skin_temp_hs2; /** Offset 0x03EA**/ uint16_t stt_error_coeff; /** Offset 0x03EC**/ uint16_t stt_error_rate_coefficient; - /** Offset 0x03EE**/ uint8_t stapm_control; - /** Offset 0x03EF**/ uint8_t stapm_boost; - /** Offset 0x03F0**/ uint8_t smartshift_enable; - /** Offset 0x03F1**/ uint32_t apu_only_sppt_limit; - /** Offset 0x03F5**/ uint32_t sustained_power_limit; - /** Offset 0x03F9**/ uint32_t fast_ppt_limit; - /** Offset 0x03FD**/ uint32_t slow_ppt_limit; - /** Offset 0x0401**/ uint8_t system_configuration; - /** Offset 0x0402**/ uint8_t cppc_ctrl; - /** Offset 0x0403**/ uint8_t cppc_perf_limit_max_range; - /** Offset 0x0404**/ uint8_t cppc_perf_limit_min_range; - /** Offset 0x0405**/ uint8_t cppc_epp_max_range; - /** Offset 0x0406**/ uint8_t cppc_epp_min_range; - /** Offset 0x0407**/ uint8_t cppc_preferred_cores; - /** Offset 0x0408**/ uint8_t smu_soc_tuning_reserved[20]; + /** Offset 0x03EE**/ uint8_t smartshift_enable; + /** Offset 0x03EF**/ uint32_t apu_only_sppt_limit; + /** Offset 0x03F3**/ uint32_t sustained_power_limit; + /** Offset 0x03F7**/ uint32_t fast_ppt_limit; + /** Offset 0x03FB**/ uint32_t slow_ppt_limit; + /** Offset 0x03FF**/ uint8_t system_configuration; + /** Offset 0x0400**/ uint8_t cppc_ctrl; + /** Offset 0x0401**/ uint8_t cppc_perf_limit_max_range; + /** Offset 0x0402**/ uint8_t cppc_perf_limit_min_range; + /** Offset 0x0403**/ uint8_t cppc_epp_max_range; + /** Offset 0x0404**/ uint8_t cppc_epp_min_range; + /** Offset 0x0405**/ uint8_t cppc_preferred_cores; + /** Offset 0x0406**/ uint8_t stapm_boost; + /** Offset 0x0407**/ uint32_t stapm_time_constant; + /** Offset 0x040B**/ uint8_t smu_soc_tuning_reserved[17]; /** Offset 0x041C**/ uint8_t iommu_support; /** Offset 0x041D**/ uint8_t pspp_policy; /** Offset 0x041E**/ uint8_t enable_nb_azalia; |