vendorcode/amd: Copy 00670F00 files from PI package

Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions.  Change the license text and fix
up misc. whitespace.

This will facilitate the review of binaryPI changes in the
vendorcode directory.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)

Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

21 files changed, 888 insertions, 91 deletions

diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h
index 62ef892eda..4883434002 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Family/cpuFamRegisters.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 309899 $   @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h
index 3ee71cd624..87077ce805 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h
index 7efbc523e4..418fb2f6d2 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h
index 7cef71d4c3..04bd01334d 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
index 889be764a1..3ef723cd4f 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 309899 $   @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -429,8 +429,9 @@ typedef struct {
 #define CPUID_EXT_FAMILY_MASK    0x0FF00000ul
 
 #define CZ_SOCKET_FP4       0
+#define CZ_SOCKET_AM4       2
 #define ST_SOCKET_FP4       0
-#define ST_SOCKET_FT4       3
+#define ST_SOCKET_FT4       4
 #define SOCKET_IGNORE       0xF
 
 #define LAPIC_BASE_ADDR_MASK    0x0000FFFFFFFFF000ull
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h
index 915144f8f9..c5f9529204 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/heapManager.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  CPU
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h b/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h
index f75f881601..57bfabbd03 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Common/AmdFch.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h
index 6f87842a30..fe1803d88a 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/AcpiLib.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h
index a694d11543..84cd94c64c 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchBiosRamUsage.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h
index 35a76d20fd..46fa1a9bdb 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchCommonCfg.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 311507 $   @e \$Date: 2015-01-22 06:57:51 +0800 (Thu, 22 Jan 2015) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -98,7 +98,9 @@ typedef struct {
   UINT32                XHCI_PMx08_xHCI_Firmware_Addr_1_Ram;       ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram
   UINT8                 SataDevSlpPort0S5Pin;                      ///< SataDevSlpPort0S5Pin - Reserved
   UINT8                 SataDevSlpPort1S5Pin;                      ///< SataDevSlpPort1S5Pin - Reserved
-  UINT16                Dummy16;                                   ///< Dummy16 - Reserved
+  UINT16                FchFlag16;                                 ///< Dummy16 - Reserved
+  UINT32                FchFlag32;                                 ///< Dummy32 - Reserved
+                                                                   ///    @li <b>0</b> - Carrizo
   UINT32                SdMmioBase;                                ///< Sd Mmio Base - Reserved
   UINT32                EhciMmioBase;                              ///< Ehci Mmio Base - Reserved
   UINT32                XhciMmioBase;                              ///< Xhci Mmio Base - Reserved
@@ -525,6 +527,7 @@ typedef struct {
 //  UINT8                 SataDevSlpPort1S5Pin;           /// SataDevSlpPort1S5Pin - Reserved
   UINT8                 SataDbgTX_DRV_STR ;           /// TX_DRV_STR - Reserved
   UINT8                 SataDbgTX_DE_EMPH_STR ;           /// TX_DE_EMPH_STR - Reserved
+  BOOLEAN               SataLongTrace[2];                /// Long Trace - Reserved
   UINT32                TempMmio;                       /// TempMmio - Reserved
 } FCH_SATA;
 
@@ -545,6 +548,8 @@ typedef struct {
 #define Fun_87                        0x87
 #define Fun_88                        0x88
 #define Fun_89                        0x89
+#define Fun_8B                        0x8B
+#define Fun_8C                        0x8C
 #define Fun_90                        0x90
 #define MSG_IMC_TO_SYS                0x81
 #define MSG_REG0                      0x82
@@ -789,9 +794,37 @@ typedef struct _FCH_EC {
   UINT8                 MsgFun89Zone3MsgReg9;           ///<Ct DWORD bit 31-24
   UINT8                 MsgFun89Zone3MsgRegA;           ///<Mode bit 0-7
 //
-// FLAG for Fun83/85/89 support
+//EC LDN9 function 8C Startup PWM channel 0
 //
-  UINT16                IMCFUNSupportBitMap;            ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
+  UINT8                 MsgFun8CZone0MsgReg0;           ///<Reture 0xFA stands for success
+  UINT8                 MsgFun8CZone0MsgReg1;           ///<Bit 2-0 Thermal zone number
+  UINT8                 MsgFun8CZone0MsgReg2;           ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
+  UINT8                 MsgFun8CZone0MsgReg3;           ///<Startup PWM (effective range 1~100)
+//
+//EC LDN9 function 8C Startup PWM channel 1
+//
+  UINT8                 MsgFun8CZone1MsgReg0;           ///<Reture 0xFA stands for success
+  UINT8                 MsgFun8CZone1MsgReg1;           ///<Bit 2-0 Thermal zone number
+  UINT8                 MsgFun8CZone1MsgReg2;           ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
+  UINT8                 MsgFun8CZone1MsgReg3;           ///<Startup PWM (effective range 1~100)
+//
+//EC LDN9 function 8C Startup PWM channel 2
+//
+  UINT8                 MsgFun8CZone2MsgReg0;           ///<Reture 0xFA stands for success
+  UINT8                 MsgFun8CZone2MsgReg1;           ///<Bit 2-0 Thermal zone number
+  UINT8                 MsgFun8CZone2MsgReg2;           ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
+  UINT8                 MsgFun8CZone2MsgReg3;           ///<Startup PWM (effective range 1~100)
+//
+//EC LDN9 function 8C Startup PWM channel 3
+//
+  UINT8                 MsgFun8CZone3MsgReg0;           ///<Reture 0xFA stands for success
+  UINT8                 MsgFun8CZone3MsgReg1;           ///<Bit 2-0 Thermal zone number
+  UINT8                 MsgFun8CZone3MsgReg2;           ///<Startup PWM flags; bit0: enable/disable current zone, bit1/2/3: 1 if values in reg3/4/5 are valid.
+  UINT8                 MsgFun8CZone3MsgReg3;           ///<Startup PWM (effective range 1~100)
+//
+// FLAG for Fun83/85/89/8C support
+//
+  UINT32                IMCFUNSupportBitMap;            ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
 } FCH_EC;
 
 ///
@@ -1284,8 +1317,126 @@ typedef struct {
   BOOLEAN               UsbBatteryChargeEnable;         ///< USB Battery Charge Enable
   BOOLEAN               ReduceUSB3PortToLastTwo;        ///< Reduce USB3.0 ports to last 2
   UINT8                 USB30PortInit;                  ///< USB 3.0 Port Init
+  UINT8                 USB30RxLfpsDetTh;               ///< USB 3.0 Rx Lfps Detect Threshhold
 } FCH_USB;
 
+//++++++++++++++++++++++++++++++++++ Promontory param structure
+///PTXhciStructure
+typedef struct {
+  UINT8         PTXhciGen1;                     ///< PTXhciGen1
+  UINT8         PTXhciGen2;                     ///< PTXhciGen2
+  UINT8         PTAOAC;                         ///< PTAOAC
+  UINT8         PTHW_LPM ;                      ///< PTHW_LPM
+  UINT8         PTDbC;                          ///< PTDbC
+  UINT8         PTXHC_PME;                      ///< PTXHC_PME
+  UINT8         PTSystemSpreadSpectrum;         ///< PTSystemSpreadSpectrum
+  UINT8         Equalization4;                  ///< Enable/Disable Equalization 4
+  UINT8         Redriver;                       ///< Enable/Disable Redriver Setting
+} PT_USB;
+///PTSataStructure
+typedef struct {
+  UINT8         PTSataPortEnable;               ///< PTSataEnable
+  UINT8         PTSataMode;                     ///< PTSataMode
+  UINT8         PTSataAggresiveDevSlpP0;        ///< PTSataAggresiveDevSlpP0
+  UINT8         PTSataAggresiveDevSlpP1;        ///< PTSataAggresiveDevSlpP1
+  UINT8         PTSataAggrLinkPmCap;            ///< PTSataAggrLinkPmCap
+  UINT8         PTSataPscCap;                   ///< PTSataPscCap
+  UINT8         PTSataSscCap;                   ///< PTSataSscCap
+  UINT8         PTSataMsiCapability;            ///< PTSataPscCap
+  UINT8         PTSataPortMdPort0;              ///< PTSataPortMdPort0
+  UINT8         PTSataPortMdPort1;              ///< PTSataPortMdPort1
+  UINT8         PTSataHotPlug;                  ///< PTSataHotPlug
+} PT_SATA;
+///PTPcieStructure
+typedef struct {
+  UINT8         PromontoryPCIeEnable;                   ///< PCIeEnable
+  UINT8         PromontoryPCIeASPM;                     ///< PCIeASPM
+} PT_PCIE;
+///PTAddressStructure
+typedef struct {
+  UINT8         GppNumber;                             ///< GppNumber
+  UINT32        XhciID;                                ///< XhciDIDVID
+  UINT32        SataID;                                ///< SataDIDVID
+  UINT32        GpioID;                                ///< GpioDIDVID
+  UINT64        FwVersion;                                ///< FwVersion
+} PT_ADDR;
+///PTUSBPortStructure
+typedef struct {
+  UINT8         PTUsb31P0;                    ///< PTUsb31Port0 Enable/Disable
+  UINT8         PTUsb31P1;                    ///< PTUsb31Port0 Enable/Disable
+  UINT8         PTUsb30P0;                    ///< PTUsb30Port0 Enable/Disable
+  UINT8         PTUsb30P1;                    ///< PTUsb30Port1 Enable/Disable
+  UINT8         PTUsb30P2;                    ///< PTUsb30Port2 Enable/Disable
+  UINT8 		PTUsb30P3;					  ///< PTUsb30Port3 Enable/Disable
+  UINT8		    PTUsb30P4; 					  ///< PTUsb30Port4 Enable/Disable
+  UINT8		    PTUsb30P5;					  ///< PTUsb30Port5 Enable/Disable
+  UINT8         PTUsb20P0;                    ///< PTUsb20Port0 Enable/Disable
+  UINT8         PTUsb20P1;                    ///< PTUsb20Port1 Enable/Disable
+  UINT8         PTUsb20P2;                    ///< PTUsb20Port2 Enable/Disable
+  UINT8 		PTUsb20P3;					  ///< PTUsb20Port3 Enable/Disable
+  UINT8		    PTUsb20P4; 					  ///< PTUsb20Port4 Enable/Disable
+  UINT8		    PTUsb20P5;					  ///< PTUsb20Port5 Enable/Disable
+} PT_USBPort;
+///PTUSB31TxStructure
+typedef struct {
+UINT8		  USB31Gen1Swing; 			///< PTUSB31PCS_B1 genI swing
+UINT8		  USB31Gen2Swing; 			///< PTUSB31PCS_B1 genI swing
+UINT8		  USB31Gen1PreEmEn;			///< PTUSB31PCS_B1 genI pre-emphasis enable
+UINT8		  USB31Gen2PreEmEn;			///< PTUSB31PCS_B1 genII pre-emphasis enable
+UINT8		  USB31Gen1PreEmLe;			///< PTUSB31PCS_B1 genI pre-emphasis level
+UINT8		  USB31Gen2PreEmLe;			///< PTUSB31PCS_B1 genII pre-emphasis level
+UINT8		  USB31Gen1PreShEn;			///< PTUSB31PCS_B1 genI pre-shoot enable
+UINT8		  USB31Gen2PreShEn;			///< PTUSB31PCS_B1 genII pre-shoot enable
+UINT8		  USB31Gen1PreShLe;			///< PTUSB31PCS_B1 genI pre-shoot level
+UINT8		  USB31Gen2PreShLe;			///< PTUSB31PCS_B1 genII pre-shoot level
+} PT_USB31Tx;
+
+///PTUSB30TxStructure
+typedef struct {
+UINT8		  USB30Gen1Swing; 			///< PTUSB30PCS_B3 genI swing
+UINT8		  USB30Gen1PreEmEn;			///< PTUSB30PCS_B3 genI pre-emphasis enable
+UINT8		  USB30Gen1PreEmLe;			///< PTUSB30PCS_B3 genI pre-emphasis level
+} PT_USB30Tx;
+
+
+///PTUSBTxStructure
+typedef struct {
+PT_USB31Tx    USB31Tx[2];                   ///< USB31Tx setting
+PT_USB30Tx    USB30Tx[3];                   ///< USB30Tx setting
+UINT8		  USB20B2Tx00;			        ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[0]
+UINT8		  USB20B2Tx05;			        ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[5]
+UINT8		  USB20B3Tx1113;			    ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[13][11]
+UINT8		  USB20B3Tx1012;			    ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[12][10]
+UINT8		  USB20B4Tx0206;			    ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[2][6]
+UINT8		  USB20B4Tx0307;			    ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[3][7]
+UINT8		  USB20B5Tx0408;			    ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[4][8]
+UINT8		  USB20B5Tx0109;			    ///< USB2.0 TX driving current, 7: largest By USB_HSDP/N[1][9]
+} PT_USBTx;
+
+///PTSataTxStructure
+typedef struct {
+UINT8		  SATAGen1Swing; 			///< genI swing
+UINT8		  SATAGen2Swing; 			///< genII swing
+UINT8		  SATAGen3Swing; 			///< genIII swing
+UINT8		  SATAGen1PreEmEn;			///< genI pre-emphasis enable
+UINT8		  SATAGen2PreEmEn;			///< genII pre-emphasis enable
+UINT8		  SATAGen3PreEmEn;			///< genIII pre-emphasis enable
+UINT8		  SATAGen1PreEmLevel;		///< genI pre-emphasis level
+UINT8		  SATAGen2PreEmLevel;		///< genII pre-emphasis level
+UINT8		  SATAGen3PreEmLevel;		///< genIII pre-emphasis level
+} PT_SATATx;
+///PTDataStructure
+typedef struct _FCH_PT {
+  PT_USB       PromontoryUSB;                     ///<PTXhciStructure
+  PT_SATA      PromontorySATA;                    ///<PTSataStructure
+  PT_PCIE      PromontoryPCIE;                    ///<PTPcieStructure
+  PT_ADDR      PromontoryAddr;                    ///<PTAddressStructure
+  PT_USBPort   PromontoryUSBPort;                 ///<PTUSBPortStructure
+  PT_USBTx     PTUSBTX;                   ///<PTUSBTX
+  PT_SATATx    PTSATATX[8];                  ///<PTSATATX
+} FCH_PT;
+
+//-------------------------------------------- Promontory param structure
 
 /// Private: FCH_DATA_BLOCK_RESET
 typedef struct _FCH_RESET_DATA_BLOCK {
@@ -1323,15 +1474,16 @@ typedef struct _FCH_RESET_DATA_BLOCK {
   BOOLEAN               QeEnabled;                      /// Quad Mode Enabled
   BOOLEAN               FchOscout1ClkContinous;         ///< FCH OSCOUT1_CLK Continous
   UINT8                 LpcClockDriveStrength;          ///< Lpc Clock Drive Strength
-  const VOID*           EarlyOemGpioTable;              /// Pointer of Early OEM GPIO table
+  FCH_PT                Promontory;                     ///< Promontory structure
+  VOID*                 EarlyOemGpioTable;              /// Pointer of Early OEM GPIO table
 //  VOID*                 OemSpiDeviceTable;              /// Pointer of OEM Spi Device table
 } FCH_RESET_DATA_BLOCK;
 
 
 /// Private: FCH_DATA_BLOCK
 typedef struct _FCH_DATA_BLOCK {
-  AMD_CONFIG_PARAMS     *StdHeader;                     ///< Header structure
   FCH_RUNTIME           FchRunTime;                     ///< FCH Run Time Parameters
+  AMD_CONFIG_PARAMS     *StdHeader;                     ///< Header structure
 
   FCH_ACPI              HwAcpi;                         ///< ACPI structure
   FCH_AB                Ab;                             ///< AB structure
@@ -1352,6 +1504,7 @@ typedef struct _FCH_DATA_BLOCK {
   FCH_IMC               Imc;                            ///< IMC structure
   FCH_MISC              Misc;                           ///< MISC structure
   FCH_IOMUX             IoMux;                          ///< MISC structure
+  FCH_PT                Promontory;                     ///< Promontory structure
   VOID*                 PostOemGpioTable;              /// Pointer of Post OEM GPIO table
 } FCH_DATA_BLOCK;
 
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h
index 41f103bd25..e1d0def2ef 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchDef.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -72,6 +72,12 @@ VOID          GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS
 VOID          GetFchAcpiPmBase (OUT  UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
 UINT8         ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
 UINT8         ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN       FchCheckBR_ST (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN       FchCheckBR (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN       FchCheckST (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN       FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN       FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader);
+UINT64        FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader);
 
 ///
 /// Fch Ab Routines
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
index dfdab59f08..5836e5c176 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchLib.c
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -375,7 +375,7 @@ RwAlink (
     WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
     Index = FCH_AX_DATAP_REG3C | AccessType;
   }
-  WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader);
+  WriteAlink (Index, ReadAlink (Index, StdHeader) & AndMask | OrMask, StdHeader);
 }
 
 
@@ -669,4 +669,4 @@ ClearAllSmiStatus (
   for ( Index = 0; Index < 20; Index++ ) {
     ACPIMMIO8 (0xfed80280 + Index) |= 0;
   }
-}
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
index 171ea0f3d0..9cd0e29557 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/FchPeLib.c
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -40,7 +40,13 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  ***************************************************************************/
+
 #include "FchPlatform.h"
+#include  "cpuFamilyTranslation.h"
+//#include  "Porting.h"
+//#include  "AMD.h"
+//#include  "amdlib.h"
+#include  "heapManager.h"
 #define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
 
 /*----------------------------------------------------------------------------------------*/
@@ -179,8 +185,8 @@ ProgramFchGpioTbl (
 {
   if (pGpioTbl != NULL) {
     while (pGpioTbl->GpioPin != 0xFF) {
-      ACPIMMIO8 (ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction);
-      ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + ((UINT32)pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte);
+      ACPIMMIO8 (ACPI_MMIO_BASE + IOMUX_BASE + pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction);
+      ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + (pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte);
       pGpioTbl++;
     }
   }
@@ -308,3 +314,359 @@ SbSleepTrapControl (
     ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
   }
 }
+
+/**
+ * FchUsb3D3ColdCallback - Fch Usb3 D3Cold Callback
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+FchUsb3D3ColdCallback (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+  UINT8 Value8;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+  //FCH_DEADLOOP ();
+  ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) |= FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown;
+  do {
+  } while ((ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) & FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown) == 0);
+
+  ACPIMMIO32 (FCH_XHC_PMx00_Configure0) |= FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN;
+
+  ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= ~ (AOAC_PWR_ON_DEV);
+  do {
+  } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 0);
+
+  ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= 3;
+
+  ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn;
+
+  if ((ACPIMMIO8 (FCH_AOACx64_EHCI_D3_CONTROL) & 0x03) == 3) {
+    ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown);
+    ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) |= FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn;
+  }
+
+  ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) &= ~ (FCH_AOACxA0_PwrGood_Control_XhcPwrGood + FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown);
+  Value8 = ACPIMMIO8 (0xFED803EE);
+  Value8 &= 0xFC;
+  Value8 |= 0x01;
+  ACPIMMIO8 (0xFED803EE) = Value8;
+}
+
+/**
+ * FchUsb3D0Callback - Fch Usb3 D0 Callback
+ *
+ *
+ * @param[in] FchDataPtr
+ *
+ */
+VOID
+FchUsb3D0Callback (
+  IN  VOID     *FchDataPtr
+  )
+{
+  FCH_DATA_BLOCK         *LocalCfgPtr;
+  AMD_CONFIG_PARAMS      *StdHeader;
+  UINT32 Dword32;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  ACPIMMIO8 (0xFED803EE) &= 0xFC;
+
+  ACPIMMIO8 (FCH_AOACxA0_PwrGood_Control) |= (FCH_AOACxA0_PwrGood_Control_XhcPwrGood);
+  ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn);
+  ACPIMMIO32 (FCH_MISCx28_ClkDrvStr2) &= ~ (FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn);
+  Dword32 = ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control);
+  Dword32 &= ~(FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown);
+  ACPIMMIO32 (FCH_AOACxA0_PwrGood_Control) =  ((FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB | Dword32) & (~ BIT29));
+
+  ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) &= 0xFC;
+  ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) |= (AOAC_PWR_ON_DEV);
+  do {
+  } while ((ACPIMMIO8 (FCH_AOACx6F_USB3_D3_STATE) & 0x07) != 7);
+
+  do {
+  } while ((ACPIMMIO32 (FCH_XHC_PMx00_Configure0) & BIT7) != BIT7);
+
+  ACPIMMIO32 (FCH_XHC_PMx00_Configure0) &= ~ (BIT16);
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Checks Bristol or Stoney
+ *
+ *   NOTE:
+ *
+ * @param[in] StdHeader
+ *
+ */
+BOOLEAN
+FchCheckBR_ST (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  // Only initialize on CZ processors, otherwise exit.
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) {
+    return TRUE;
+  }
+  if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Checks Bristol
+ *
+ *   NOTE:
+ *
+ * @param[in] StdHeader
+ *
+ */
+BOOLEAN
+FchCheckBR (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  // Only initialize on CZ processors, otherwise exit.
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F15_BR_ALL) != 0) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Checks Stoney
+ *
+ *   NOTE:
+ *
+ * @param[in] StdHeader
+ *
+ */
+BOOLEAN
+FchCheckST (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  // Only initialize on CZ processors, otherwise exit.
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F15_ST_ALL) != 0) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Checks Carrizo
+ *
+ *   NOTE:
+ *
+ * @param[in] StdHeader
+ *
+ */
+BOOLEAN
+FchCheckCZ (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  // Only initialize on CZ processors, otherwise exit.
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F15_CZ_ALL) != 0) {
+    return TRUE;
+  }
+
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Checks Package AM4
+ *
+ *   NOTE:
+ *
+ * @param[in] StdHeader
+ *
+ */
+BOOLEAN
+FchCheckPackageAM4 (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  CPUID_DATA CpuId;
+  UINT8 RegValue;
+
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+  RegValue = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+  ///@todo - update the PkgType once it is reflected in BKDG
+  if (RegValue == 2) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function Get Scratch Fuse
+ *
+ *   NOTE:
+ *
+ * @param[in] StdHeader
+ *
+ */
+UINT64
+FchGetScratchFuse (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PCI_ADDR D0F0xB8_SMU_Index_Address;
+  PCI_ADDR D0F0xBC_SMU_Index_Data;
+  UINT64  TempData64;
+  UINT32  TempData32;
+
+  D0F0xB8_SMU_Index_Address.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xB8));
+  D0F0xBC_SMU_Index_Data.AddressValue = (MAKE_SBDFO (0, 0, 0, 0, 0xBC));
+  TempData64 = 0;
+  TempData32 = 0xC0016028;
+  LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader);
+  LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader);
+  TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) >> 9;
+  TempData32 = 0xC001602C;
+  LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader);
+  LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader);
+  TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (32 - 9);
+  TempData32 = 0xC0016030;
+  LibAmdPciWrite (AccessWidth32, D0F0xB8_SMU_Index_Address, &TempData32, StdHeader);
+  LibAmdPciRead (AccessWidth32, D0F0xBC_SMU_Index_Data, &TempData32, StdHeader);
+  TempData64 |= (((UINT64) TempData32) & 0xFFFFFFFF) << (64 - 9);
+
+  return TempData64;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      Length            Buffer length
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer allocation fail
+ *
+ */
+
+VOID *
+FchAllocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = (UINT32) Length;
+  AllocHeapParams.BufferHandle = Handle;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return NULL;
+  }
+  return AllocHeapParams.BufferPtr;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap and clear it
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      Length            Buffer length
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer allocation fail
+ *
+ */
+
+VOID *
+FchAllocateHeapBufferAndClear (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  VOID  *Buffer;
+  Buffer = FchAllocateHeapBuffer (Handle, Length, StdHeader);
+  if (Buffer != NULL) {
+    LibAmdMemFill (Buffer, 0x00, Length, StdHeader);
+  }
+  return Buffer;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locates a previously allocated buffer on the heap.
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer handle not found
+ *
+ */
+
+VOID *
+MemLocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  LOCATE_HEAP_PTR       LocHeapParams;
+  LocHeapParams.BufferHandle = Handle;
+  Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return NULL;
+  }
+  return LocHeapParams.BufferPtr;
+}
+
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c
index 656f7689bb..8313d81ded 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/MemLib.c
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c
index ed8bb81869..7c55c4e7ef 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Common/PciLib.c
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h
index 92201b8a49..4413e2ec04 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 314274 $   @e \$Date: 2015-03-08 03:53:49 -0500 (Sun, 08 Mar 2015) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -347,7 +347,7 @@
 #define FCH_IDE_VID                  AMD_FCH_VID      // Dev 20 Func 1
 #define FCH_IDE_DID                  0x780C
 #define FCH_AZALIA_VID               AMD_FCH_VID      // Dev 20 Func 2
-#define FCH_AZALIA_DID               0x157a
+#define FCH_AZALIA_DID               0x780D
 #define FCH_LPC_VID                  AMD_FCH_VID      // Dev 20 Func 3
 #define FCH_LPC_DID                  0x780E
 #define FCH_PCIB_VID                 AMD_FCH_VID      // Dev 20 Func 4
@@ -415,6 +415,7 @@
 #define FCH_OHCI3_BUS        0
 #define FCH_OHCI3_DEV        22
 #define FCH_OHCI3_FUNC       0
+#define EHCI_BUS_DEV_FUN       ((0x12 << 3) + 0)    // PORT 0-3
 #define USB1_EHCI_BUS_DEV_FUN       ((0x12 << 3) + 2)    // PORT 0-4
 #define FCH_EHCI1_BUS        0
 #define FCH_EHCI1_DEV        18
@@ -435,9 +436,9 @@
 #define FCH_IDE_BUS          0
 #define FCH_IDE_DEV          20
 #define FCH_IDE_FUNC         1
-#define AZALIA_BUS_DEV_FUN          ((0x9 << 3) + 2)
+#define AZALIA_BUS_DEV_FUN          ((0x14 << 3) + 2)
 #define FCH_AZALIA_BUS       0
-#define FCH_AZALIA_DEV       9
+#define FCH_AZALIA_DEV       20
 #define FCH_AZALIA_FUNC      2
 #define LPC_BUS_DEV_FUN             ((0x14 << 3) + 3)
 #define FCH_LPC_BUS          0
@@ -856,7 +857,7 @@
 
 
 // USB ports
-#define NUM_USB1_PORTS           5
+#define NUM_USB1_PORTS           4
 #define NUM_USB2_PORTS           5
 #define NUM_USB3_PORTS           4
 #define NUM_USB4_PORTS           2
@@ -2041,8 +2042,10 @@ FCH_MISC_REGF0                   EQU     0F0h
 //    offset : 0x1C00
 //
 #define FCH_XHC_PMx00_Configure0             0xFED81C00ul        //
+#define FCH_XHC_PMx00_Configure0_U3pPllReset     BIT8
 #define FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN     BIT15
 #define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN          BIT21
+
 #define FCH_XHC_PMx10_Xhc_Memory_Configure             0xFED81C10ul        //
 #define FCH_XHC_PMx18_Usb20_Link_Status             0xFED81C18ul        //
 #define FCH_XHC_PMx20_Usb20_Wake_Control             0xFED81C20ul        //
@@ -2052,6 +2055,7 @@ FCH_MISC_REGF0                   EQU     0F0h
 #define FCH_XHC_PMx30_Xhci10_Enable             0xFED81C30ul        //
 #define FCH_XHC_PMx60_xHC_Battery_Charger_Enable             0xFED81C60ul        //
 
+#define FCH_XHC_PMx88_SSPHY_Common_Clock_Control_Status             0xFED81C88ul        //
 
 
 
@@ -2506,6 +2510,7 @@ FCH_AOAC_REG4X-7x State field
 #define FCH_XHCI_IND_REG100           0x100 //
 #define FCH_XHCI_IND_REG120           0x120 //
 #define FCH_XHCI_IND_REG128           0x128 //
+#define FCH_XHCI_IND_REG140           0x140 //
 #define FCH_XHCI_IND_REG200           0x200 //
 #define FCH_XHCI_IND_REG240           0x240 //
 #define FCH_XHCI_IND_REG280           0x280 //
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h
index ca2a8d89a5..e7fff2320b 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/FchPlatform.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h
index a20ec19f55..bca7b5bd59 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: FCH
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
index 20a359ad0e..5c2410d7d4 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  PSP
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,10 +48,11 @@
  */
 #include "AGESA.h"
 #include "Filecode.h"
+#include "Fch.h"
 #include "PspBaseLib.h"
 
 #define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE
-#define PSP_BAR1_TMP_BASE 0xFEA00000ul
+#define PSP_BAR_TMP_BASE 0xFEA00000ul
 
 #define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF)
 #define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F)
@@ -74,6 +75,13 @@
 #define PSP_SECURE_PART                 (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE)      ///< Secure Part
 #define PSP_FRA_MODE                    (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE)  ///< FRA Part
 
+#define PSP_MUTEX_REG0_OFFSET     (24 * 4)       ///< PSP Mutex0 register offset
+#define PSP_MUTEX_REG1_OFFSET     (25 * 4)       ///< PSP Mutex1 register offset
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
 /*----------------------------------------------------------------------------------------
  *                   D E F I N I T I O N S    A N D    M A C R O S
  *----------------------------------------------------------------------------------------
@@ -139,6 +147,37 @@ PspLibPciWritePspConfig (
   PspLibPciWriteConfig  ((UINT32) (PSP_PCI_BDA  + Offset), Value);
 }
 
+/// Structure for Program ID
+typedef enum {
+  CZ_PROGRAM = 0x00,            ///< Program ID for CZ
+  BR_PROGRAM = 0x01,            ///< Program ID for BR
+  ST_PROGRAM = 0x02,            ///< Program ID for ST
+  UNSUPPORTED_PROGRAM = 0xFF,   ///< Program ID for unsupported
+} PROGRAM_ID;
+
+PROGRAM_ID
+PspGetProgarmId (
+  VOID
+  )
+{
+  CPUID_DATA          Cpuid;
+
+  LibAmdCpuidRead (0x00000001, &Cpuid, NULL);
+  //Stoney CPUID 0x00670F00 or 0x00670F01
+  if ((Cpuid.EAX_Reg >> 16) == 0x67) {
+    return ST_PROGRAM;
+  } else if ((Cpuid.EAX_Reg >> 16) == 0x66) {
+    if ((Cpuid.EAX_Reg & 0xF0) == 0x50) {
+      //Bristol CPUID 0x00660F51
+      return BR_PROGRAM;
+    } else if ((Cpuid.EAX_Reg & 0xF0) == 0x00) {
+      //Carrizo CPUID 0x00660F00 or 0x00660F01
+      return CZ_PROGRAM;
+    }
+  }
+  return UNSUPPORTED_PROGRAM;
+}
+
 BOOLEAN
 GetPspDirBase (
   IN OUT   UINT32     *Address
@@ -146,6 +185,7 @@ GetPspDirBase (
 {
   UINTN                     i;
   FIRMWARE_ENTRY_TABLE      *FirmwareTableBase;
+  PROGRAM_ID                ProgramId;
   CONST UINT32 RomSigAddrTable[] =
   {
     0xFFFA0000, //  --> 512KB base
@@ -156,32 +196,66 @@ GetPspDirBase (
     0xFF020000  //  --> 16MB base
   };
 
+  ProgramId = PspGetProgarmId ();
+
   for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) {
     FirmwareTableBase  = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i];
     // Search flash for unique signature 0x55AA55AA
     if (FirmwareTableBase->Signature  == FIRMWARE_TABLE_SIGNATURE) {
-      *Address = FirmwareTableBase->PspDirBase;
+      switch (ProgramId) {
+      case BR_PROGRAM:
+      case CZ_PROGRAM:
+        *Address = FirmwareTableBase->PspDirBase;
+        break;
+      case ST_PROGRAM:
+        *Address = FirmwareTableBase->NewPspDirBase;
+        break;
+      default:
+        *Address = FirmwareTableBase->PspDirBase;
+        break;
+      }
       return TRUE;
     }
   }
-
   return (FALSE);
 }
 
+/**
+ * Get specific PSP Entry information, this routine will auto detect the processor for loading
+ * correct PSP Directory
+ *
+ *
+ *
+ * @param[in] EntryType               PSP DIR Entry Type
+ * @param[in,out] EntryAddress        Address of the specific PSP Entry
+ * @param[in,out] EntrySize           Size of the specific PSP Entry
+ */
+
 BOOLEAN
 PSPEntryInfo (
   IN       PSP_DIRECTORY_ENTRY_TYPE    EntryType,
   IN OUT   UINT64                      *EntryAddress,
-  IN       UINT32                      *EntrySize
+  IN OUT   UINT32                      *EntrySize
   )
 {
   PSP_DIRECTORY         *PspDir;
   UINTN                 i;
+  PROGRAM_ID                ProgramId;
 
+  PspDir = NULL;
   if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
     return FALSE;
   }
 
+  ProgramId = PspGetProgarmId ();
+  //Append BR Program ID
+  if ((ProgramId == BR_PROGRAM) &&
+      ((EntryType == SMU_OFFCHIP_FW) ||
+       (EntryType == SMU_OFF_CHIP_FW_2) ||
+       (EntryType == AMD_SCS_BINARY))) {
+    EntryType |= (PSP_ENTRY_BR_PROGRAM_ID << 8);
+  }
+
   for (i = 0; i < PspDir->Header.TotalEntries; i++) {
     if (PspDir->PspEntry[i].Type == EntryType) {
       *EntryAddress = PspDir->PspEntry[i].Location;
@@ -193,6 +267,66 @@ PSPEntryInfo (
   return (FALSE);
 }
 
+BOOLEAN
+PspSoftWareFuseInfo (
+  IN OUT   UINTN                       *FuseSpiAddress,
+  IN OUT   UINT64                      *FuseValue
+  )
+{
+  PSP_DIRECTORY         *PspDir;
+  UINTN                 i;
+
+  PspDir = NULL;
+  if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
+    return FALSE;
+  }
+
+  for (i = 0; i < PspDir->Header.TotalEntries; i++) {
+    if (PspDir->PspEntry[i].Type == AMD_SOFT_FUSE_CHAIN_01) {
+      *FuseSpiAddress = (UINT32) (UINTN) &PspDir->PspEntry[i].Location;
+      *FuseValue = PspDir->PspEntry[i].Location;
+      return (TRUE);
+    }
+  }
+  return (FALSE);
+}
+
+UINT32 Fletcher32 (
+  IN OUT   UINT16  *data,
+  IN       UINTN   words
+  )
+{
+  UINT32 sum1;
+  UINT32 sum2;
+  UINTN tlen;
+
+  sum1 = 0xffff;
+  sum2 = 0xffff;
+
+  while (words) {
+    tlen = words >= 359 ? 359 : words;
+    words -= tlen;
+    do {
+      sum2 += sum1 += *data++;
+    } while (--tlen);
+    sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+    sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+  }
+  // Second reduction step to reduce sums to 16 bits
+  sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+  sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+  return sum2 << 16 | sum1;
+}
+
+VOID
+UpdataPspDirCheckSum (
+  IN OUT   PSP_DIRECTORY         *PspDir
+  )
+{
+    PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \
+      (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2);
+}
+
 /**
   Check if PSP device is present
 
@@ -273,7 +407,7 @@ GetPspMboxStatus (
 {
   UINT32 PspMmio;
 
-  if (GetPspBar1Addr (&PspMmio) == FALSE) {
+  if (GetPspBar3Addr (&PspMmio) == FALSE) {
     return (FALSE);
   }
 
@@ -283,7 +417,7 @@ GetPspMboxStatus (
 }
 
 BOOLEAN
-PspBarInitEarly (void)
+PspBarInitEarly ()
 {
   UINT32 PspMmioSize;
   UINT32 Value32;
@@ -293,18 +427,18 @@ PspBarInitEarly (void)
   }
 
   //Check if PSP BAR has been assigned, if not do the PSP BAR initialation
-  if (PspLibPciReadPspConfig (PSP_PCI_BAR1_REG) == 0) {
+  if (PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) == 0) {
     /// Get PSP BAR1 Size
-    PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, 0xFFFFFFFF);
-    PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
+    PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, 0xFFFFFFFF);
+    PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG);
     PspMmioSize = ~PspMmioSize + 1;
-    /// Assign BAR1 Temporary Address
-    PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, PSP_BAR1_TMP_BASE);
+    /// Assign BAR3 Temporary Address
+    PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, PSP_BAR_TMP_BASE);
     PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06);
 
     /// Enable GNB redirection to this space @todo use equate & also find proper fix
-    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR1_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF);
-    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR1_TMP_BASE >> 8) | 3);
+    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF);
+    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR_TMP_BASE >> 8) | 3);
     /// Enable MsixBarEn, Bar1En, Bar3En
     PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34);
     /// Capability chain update
@@ -354,11 +488,21 @@ GetPspBar3Addr (
   IN OUT   UINT32 *PspMmio
   )
 {
+  UINT32 PciReg48;
+  UINT64 MsrPspAddr;
+
   if (CheckPspDevicePresent () == FALSE) {
     return (FALSE);
   }
 
-  *PspMmio = PspLibPciReadPspConfig  (PSP_PCI_BAR3_REG);
+  PciReg48 = PspLibPciReadPspConfig (PSP_PCI_EXTRAPCIHDR_REG);
+  if (PciReg48 & BIT12) {
+  // D8F0x48[12] Bar3Hide
+    LibAmdMsrRead (PSP_MSR_PRIVATE_BLOCK_BAR, &MsrPspAddr, NULL);
+    *PspMmio = (UINT32)MsrPspAddr;
+  } else {
+    *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) & 0xFFF00000;
+  }
 
   if ((*PspMmio) == 0xffffffff) {
     return (FALSE);
@@ -366,6 +510,51 @@ GetPspBar3Addr (
 
   return (TRUE);
 }
+/**
+ * Acquire the Mutex for access PSP,X86 co-accessed register
+ * Call this routine before access SMIx98 & SMIxA8
+ *
+ */
+VOID
+AcquirePspSmiRegMutex (
+  VOID
+  )
+{
+  UINT32 PspBarAddr;
+  UINT32 MutexReg0;
+  UINT32 MutexReg1;
+
+  PspBarAddr = 0;
+  if (GetPspBar3Addr (&PspBarAddr)) {
+    MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
+    MutexReg1 = PspBarAddr + PSP_MUTEX_REG1_OFFSET;
+    *(volatile UINT32*)(UINTN)(MutexReg0) |= BIT0;
+    *(volatile UINT32*)(UINTN)(MutexReg1) |= BIT0;
+    //Wait till PSP FW release the mutex
+    while ((*(volatile UINT32*)(UINTN)(MutexReg0)& BIT1) && (*(volatile UINT32*)(UINTN)(MutexReg1) & BIT0)) {
+      ;
+    }
+  }
+}
+/**
+ * Release the Mutex for access PSP,X86 co-accessed register
+ * Call this routine after access SMIx98 & SMIxA8
+ *
+ */
+VOID
+ReleasePspSmiRegMutex (
+  VOID
+  )
+{
+  UINT32 PspBarAddr;
+  UINT32 MutexReg0;
+
+  PspBarAddr = 0;
+  if (GetPspBar3Addr (&PspBarAddr)) {
+    MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
+    *(volatile UINT32*)(UINTN)(MutexReg0) &= ~BIT0;
+  }
+}
 
 /*---------------------------------------------------------------------------------------*/
 /**
@@ -461,4 +650,30 @@ PspLibPciIndirectWrite (
   LibAmdPciWrite (Width, Address, Value, NULL);
 }
 
+BOOLEAN
+IsS3Resume (
+  )
+{
+  UINT16                  AcpiPm1CntBlk;
+  UINT16                  SleepType;
+  UINT8                   PmioAddr;
+
+  AcpiPm1CntBlk = 0;
+  //Get AcpiPm1CntBlk address
+  //PMIO register can only allow 8bits access
+  PmioAddr = PMIO_REG62;
+  LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
+  LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, &AcpiPm1CntBlk, NULL);
+
+  PmioAddr++;
+  LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
+  LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, ((UINT8 *) &AcpiPm1CntBlk) + 1, NULL);
+
+  //Get Sleep type
+  LibAmdIoRead (AccessWidth16, AcpiPm1CntBlk, &SleepType, NULL);
+  SleepType = SleepType & 0x1C00;
+  SleepType = ((SleepType >> 10) & 7);
+
+  return ((SleepType == 3) ? TRUE : FALSE);
+}
 
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h
index 611539644f..e7f5a47d8d 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  PSP
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -53,7 +53,7 @@
 #define PSP_PCI_DEV        0x08    ///< PSP Device address
 #define PSP_PCI_FN         0x00    ///< PSP Fn address
 #define PSP_PCI_BDA        ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8))
-#define GET_PSP_PCI_ADDR (Offset)    MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)
+#define GET_PSP_PCI_ADDR(Offset)    MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)
 
 #define PSP_PCI_DEVID_REG           0x00    ///< DevId
 #define PSP_PCI_CMD_REG             0x04    ///< CmdReg
@@ -63,7 +63,7 @@
 #define PSP_PCI_EXTRAPCIHDR_REG     0x48    ///< Extra PCI Header Ctr
 #define PSP_PCI_HTMSICAP_REG        0x5C    ///<  HT MSI Capability
 
-#define PSP_MSR_PRIVATE_BLOCK_BAR   0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR)
+#define PSP_MSR_PRIVATE_BLOCK_BAR   0xC00110A2ul ///< PSP Private Block Base Address (PSP_ADDR)
 
 #define D8F0x44_PmNxtPtrW_MASK                                  0xff
 
@@ -102,6 +102,28 @@ typedef struct {
 
 
 
+#define PSP_SMM_COMMUNICATION_TYPE_S3SCRIPT       0x1     ///< PspCommunicationType for S3 script
+
+/// PSP communication structure for S3SCRIPT
+typedef struct {
+  UINT64    PspBar3PciAddr;       /// PCI address for PSP BAR3
+  UINT32    PspBar3Val;           /// PCI register value  for PSP BAR3
+  UINT64    Pspx48PciAddr;        /// PCI address for PSP Register 48
+  UINT32    Pspx48Val;            /// PCI register value  for PSP Register 48
+} PSP_SMM_COMMUNICATION_S3SCRIPT;
+
+/// Union for PSP_SMM_COMMUNICATE_DATA
+typedef union _PSP_SMM_COMMUNICATE_DATA {
+  PSP_SMM_COMMUNICATION_S3SCRIPT S3Script;      ///< S3Script
+} PSP_SMM_COMMUNICATE_DATA;
+
+/// PSP communication header
+typedef struct {
+  UINT32                       PspCommunicationType;         ///< Type of smm communication buffer
+  PSP_SMM_COMMUNICATE_DATA     Data;                      ///< Communication buffer
+} PSP_SMM_COMMUNICATION_BUFFER;
+
+
 UINT32
 PspLibPciReadConfig (
   IN  UINT32 Register
@@ -131,9 +153,20 @@ GetPspDirBase (
 
 BOOLEAN
 PSPEntryInfo (
-  IN      PSP_DIRECTORY_ENTRY_TYPE    EntryType,
-  IN OUT  UINT64                      *EntryAddress,
-  IN      UINT32                      *EntrySize
+  IN       PSP_DIRECTORY_ENTRY_TYPE    EntryType,
+  IN OUT   UINT64                      *EntryAddress,
+  IN OUT   UINT32                      *EntrySize
+  );
+
+BOOLEAN
+PspSoftWareFuseInfo (
+  IN OUT   UINTN                       *FuseSpiAddress,
+  IN OUT   UINT64                      *FuseValue
+  );
+
+VOID
+UpdataPspDirCheckSum (
+  IN OUT   PSP_DIRECTORY         *PspDir
   );
 
 BOOLEAN
@@ -161,6 +194,15 @@ GetPspBar3Addr (
   IN OUT   UINT32 *PspMmio
   );
 
+VOID
+AcquirePspSmiRegMutex (
+  VOID
+  );
+
+VOID
+ReleasePspSmiRegMutex (
+  VOID
+  );
 
 BOOLEAN
 GetPspMboxStatus (
@@ -169,7 +211,7 @@ GetPspMboxStatus (
 
 
 BOOLEAN
-PspBarInitEarly (VOID);
+PspBarInitEarly ();
 
 VOID
 PspLibPciIndirectRead (
@@ -187,12 +229,8 @@ PspLibPciIndirectWrite (
   IN      VOID          *Value
   );
 
-UINT8
-PspLibAccessWidth (
-  IN       ACCESS_WIDTH AccessWidth
-  );
-
 BOOLEAN
-IsS3Resume (VOID);
+IsS3Resume ();
+
 
 #endif // _AMD_LIB_H_
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h
index 193cc6506c..e3fdd8d115 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h
@@ -8,11 +8,11 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  PSP
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -51,6 +51,7 @@ typedef struct _FIRMWARE_ENTRY_TABLE {
   UINT32  GecRomBase;   ///< Base Address for Gmc Firmware
   UINT32  XHCRomBase;   ///< Base Address for XHCI Firmware
   UINT32  PspDirBase;   ///< Base Address for PSP directory
+  UINT32  NewPspDirBase;   ///< Base Address of PSP directory from program start from ST
 } FIRMWARE_ENTRY_TABLE;
 
 /// Define structure for PSP directory
@@ -64,16 +65,32 @@ typedef struct {
 
 /// define various enum type for PSP entry type
 enum _PSP_DIRECTORY_ENTRY_TYPE {
-  AMD_PUBLIC_KEY                  = 0,    ///< PSP entry pointer to AMD public key
-  PSP_FW_BOOT_LOADER              = 1,    ///< PSP entry points to PSP boot loader in SPI space
-  PSP_FW_TRUSTED_OS               = 2,    ///< PSP entry points to PSP Firmware region in SPI space
-  PSP_FW_RECOVERY_BOOT_LOADER     = 3,    ///< PSP entry point to PSP recovery region.
-  PSP_NV_DATA                     = 4,    ///< PSP entry points to PSP data region in SPI space
-  BIOS_PUBLIC_KEY                 = 5,    ///< PSP entry points to BIOS public key stored in SPI space
-  BIOS_RTM_FIRMWARE               = 6,    ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space
-  BIOS_RTM_SIGNATURE              = 7,    ///< PSP entry points to signed BIOS RTM hash stored  in SPI space
-  SMU_OFFCHIP_FW                  = 8     ///< PSP entry points to SMU image
+  AMD_PUBLIC_KEY                  = 0x00,           ///< PSP entry pointer to AMD public key
+  PSP_FW_BOOT_LOADER              = 0x01,           ///< PSP entry points to PSP boot loader in SPI space
+  PSP_FW_TRUSTED_OS               = 0x02,           ///< PSP entry points to PSP Firmware region in SPI space
+  PSP_FW_RECOVERY_BOOT_LOADER     = 0x03,           ///< PSP entry point to PSP recovery region.
+  PSP_NV_DATA                     = 0x04,           ///< PSP entry points to PSP data region in SPI space
+  BIOS_PUBLIC_KEY                 = 0x05,           ///< PSP entry points to BIOS public key stored in SPI space
+  BIOS_RTM_FIRMWARE               = 0x06,           ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space
+  BIOS_RTM_SIGNATURE              = 0x07,           ///< PSP entry points to signed BIOS RTM hash stored  in SPI space
+  SMU_OFFCHIP_FW                  = 0x08,           ///< PSP entry points to SMU image
+  AMD_SEC_DBG_PUBLIC_KEY          = 0x09,           ///< PSP entry pointer to Secure Unlock Public key
+  OEM_PSP_FW_PUBLIC_KEY           = 0x0A,           ///< PSP entry pointer to an optional public part of the OEM PSP Firmware Signing Key Token
+  AMD_SOFT_FUSE_CHAIN_01          = 0x0B,           ///< PSP entry pointer to 64bit PSP Soft Fuse Chain
+  PSP_BOOT_TIME_TRUSTLETS         = 0x0C,           ///< PSP entry points to boot-loaded trustlet binaries
+  PSP_BOOT_TIME_TRUSTLETS_KEY     = 0x0D,           ///< PSP entry points to key of the boot-loaded trustlet binaries
+  PSP_AGESA_RESUME_FW             = 0x10,           ///< PSP Entry points to PSP Agesa-Resume-Firmware
+  SMU_OFF_CHIP_FW_2               = 0x12,           ///< PSP entry points to secondary SMU image
+  PSP_S3_NV_DATA                  = 0x1A,           ///< PSP entry pointer to S3 Data Blob
+  AMD_SCS_BINARY                  = 0x5F,           ///< Software Configuration Settings Data Block
 };
+
+#define PSP_ENTRY_PROGRAM_ID_0             0                  ///< Program identifier 0, used when two programs share the same root key
+#define PSP_ENTRY_PROGRAM_ID_1             1                  ///< Program identifier 1, used when two programs share the same root key
+
+#define PSP_ENTRY_CZ_PROGRAM_ID            PSP_ENTRY_PROGRAM_ID_0       ///< CZ Program identifier
+#define PSP_ENTRY_BR_PROGRAM_ID            PSP_ENTRY_PROGRAM_ID_1       ///< BR Program identifier
+
 typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE;
 
 /// Structure for PSP Entry