diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-08-30 13:51:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-01 03:06:04 +0000 |
| commit | 8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch) | |
| tree | 1550c8877877a7a9b197da65bcff76f878bee560 /src/vendorcode/amd/pi/00660F01 | |
| parent | b7a68d5b05259a07a84a546e6a7e40948ba705ac (diff) | |
{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/pi/00660F01')
| -rw-r--r-- | src/vendorcode/amd/pi/00660F01/Include/Filecode.h | 162 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/00660F01/Include/Ids.h | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h | 12 | ||||
| -rw-r--r-- | src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc | 2 |
5 files changed, 90 insertions, 90 deletions
diff --git a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h index 0e01812626..e17ac02516 100644 --- a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h +++ b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h @@ -545,15 +545,15 @@ #define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119) #define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) +#define PROC_MEM_NB_MN_FILECODE (0xF27C) +#define PROC_MEM_NB_MNDCT_FILECODE (0xF27D) +#define PROC_MEM_NB_MNPHY_FILECODE (0xF27E) +#define PROC_MEM_NB_MNMCT_FILECODE (0xF27F) +#define PROC_MEM_NB_MNS3_FILECODE (0xF280) +#define PROC_MEM_NB_MNFLOW_FILECODE (0xF281) +#define PROC_MEM_NB_MNFEAT_FILECODE (0xF282) +#define PROC_MEM_NB_MNTRAIN3_FILECODE (0xF284) +#define PROC_MEM_NB_MNREG_FILECODE (0xF285) #define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7) #define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8) #define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9) @@ -565,82 +565,82 @@ #define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF) #define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0) #define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1) -#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3) - - -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_MPS2D_FILECODE (0XF436) -#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437) -#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C) -#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D) -#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445) -#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446) -#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447) -#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A) -#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B) - - -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) -#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0xF2E3) + + +#define PROC_MEM_PS_MP_FILECODE (0xF401) +#define PROC_MEM_PS_MPRTT_FILECODE (0xF422) +#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0xF423) +#define PROC_MEM_PS_MPODTPAT_FILECODE (0xF424) +#define PROC_MEM_PS_MPSAO_FILECODE (0xF425) +#define PROC_MEM_PS_MPMR0_FILECODE (0xF426) +#define PROC_MEM_PS_MPRC2IBT_FILECODE (0xF427) +#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0xF428) +#define PROC_MEM_PS_MPLRIBT_FILECODE (0xF429) +#define PROC_MEM_PS_MPLRNPR_FILECODE (0xF42A) +#define PROC_MEM_PS_MPLRNLR_FILECODE (0xF42B) +#define PROC_MEM_PS_MPS2D_FILECODE (0xF436) +#define PROC_MEM_PS_MPSEEDS_FILECODE (0xF437) +#define PROC_MEM_PS_MPCADCFG_FILECODE (0xF43C) +#define PROC_MEM_PS_MPDATACFG_FILECODE (0xF43D) +#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0xF445) +#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0xF446) +#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0xF447) +#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0xF44A) +#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0xF44B) + + +#define PROC_MEM_TECH_MT_FILECODE (0xF501) +#define PROC_MEM_TECH_MTHDI_FILECODE (0xF502) +#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0xF504) +#define PROC_MEM_TECH_MTTECC_FILECODE (0xF505) +#define PROC_MEM_TECH_MTTHRC_FILECODE (0xF506) +#define PROC_MEM_TECH_MTTML_FILECODE (0xF507) +#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0xF509) +#define PROC_MEM_TECH_MTTSRC_FILECODE (0xF50B) +#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0xF50C) +#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0xF581) +#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0xF583) +#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0xF584) +#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0xF585) +#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0xF586) +#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0xF587) +#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0xF588) +#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0xF589) +#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0xF58A) +#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0xF58B) +#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0xF58C) #define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590) #define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591) -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA) +#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0xF801) +#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0xF802) +#define PROC_RECOVERY_MEM_MRM_FILECODE (0xF803) +#define PROC_RECOVERY_MEM_MRUC_FILECODE (0xF804) +#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0xF8C1) +#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0xF8C2) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0xF8C3) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0xF8C4) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0xF8C5) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0xF8C6) +#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0xF8C7) +#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0xF8C8) +#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0xF8C9) +#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0xF8CA) +#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0xF8CB) +#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0xF8CC) +#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0xF8E0) +#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0xF8E1) +#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0xF8E2) +#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0xF8E3) +#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0xF8E4) +#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0xF8E5) +#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0xF8E6) +#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0xF8E7) +#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0xF8E8) +#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0xF8E9) +#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0xF8FA) //Psp #define PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE (0xFA20) diff --git a/src/vendorcode/amd/pi/00660F01/Include/Ids.h b/src/vendorcode/amd/pi/00660F01/Include/Ids.h index cb101869e3..b711345892 100644 --- a/src/vendorcode/amd/pi/00660F01/Include/Ids.h +++ b/src/vendorcode/amd/pi/00660F01/Include/Ids.h @@ -1081,7 +1081,7 @@ typedef enum { TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea TpProcS3Init, ///< 56 Entry point S3Init - TpProcCpuProcessRegisterTables = 0X58, ///< 58 .. Register table processing + TpProcCpuProcessRegisterTables = 0x58, ///< 58 .. Register table processing TpProcCpuSetBrandID, ///< 59 .. Set brand ID TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC TpProcCpuLoadUcode, ///< 5B .. Load microcode patch diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h index 889be764a1..c16371f0a8 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -332,7 +332,7 @@ typedef struct { #define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register #define MSR_CPUID_NAME_STRING1 0xC0010031ul -#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING2 0xC0010032ul #define MSR_CPUID_NAME_STRING3 0xC0010033ul #define MSR_CPUID_NAME_STRING4 0xC0010034ul #define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h index 92201b8a49..d061b5bb96 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -2545,12 +2545,12 @@ FCH_AOAC_REG4X-7x State field #define SBTSI_REG10 0x10 #define SBTSI_READORDER BIT5 -#define FCH_EC_ENTER_CONFIG 0X5A -#define FCH_EC_EXIT_CONFIG 0XA5 -#define FCH_EC_REG07 0X07 -#define FCH_EC_REG30 0X30 -#define FCH_EC_REG60 0X60 -#define FCH_EC_REG61 0X61 +#define FCH_EC_ENTER_CONFIG 0x5A +#define FCH_EC_EXIT_CONFIG 0xA5 +#define FCH_EC_REG07 0x07 +#define FCH_EC_REG30 0x30 +#define FCH_EC_REG60 0x60 +#define FCH_EC_REG61 0x61 #define FCH_IMC_ROMSIG 0x55aa55aaul diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc index 88e1a7d1be..87aeb4fc7b 100644 --- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc @@ -161,7 +161,7 @@ CR0_PG = 31 # Paging Enable CPUID_MODEL = 1 AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */ +AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */ AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */ |