diff options
author | Marc Jones <marc.jones@se-eng.com> | 2015-07-19 15:20:17 -0600 |
---|---|---|
committer | Marc Jones <marc.jones@se-eng.com> | 2015-08-07 17:59:48 +0200 |
commit | 0b11bd0d028089288e52f9f08cdcfafc9910511b (patch) | |
tree | e561ef6110713f774cc71f95e5ad0f26302de85c /src/vendorcode/amd/pi/00630F01/Proc/CPU/Family | |
parent | 9b9400dc90906fddadc0303994422ec011a8f6e7 (diff) |
vendorcode: Move AMD sources from blobs to vendorcode
The AMD AGESA binaryPI sources were incorrectly committed to
3rdparty/blobs. Move them from blobs to vendorcode and fix
Kconfig and Makefile.inc to match.
Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10982
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/pi/00630F01/Proc/CPU/Family')
-rw-r--r-- | src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h new file mode 100644 index 0000000000..b93d396747 --- /dev/null +++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ + +#ifndef _CPU_FAM_REGISTERS_H_ +#define _CPU_FAM_REGISTERS_H_ + +/* + *-------------------------------------------------------------- + * + * M O D U L E S U S E D + * + *--------------------------------------------------------------- + */ + +/* + *-------------------------------------------------------------- + * + * D E F I N I T I O N S / M A C R O S + * + *--------------------------------------------------------------- + */ + +// This define should be equal to the total number of families +// in the cpuFamily enum. +#define MAX_CPU_FAMILIES 64 +#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family + +// CPU_LOGICAL_ID.Family equates +// Family 15h equates +#define AMD_FAMILY_15_TN 0x0000000000000200ull +#define AMD_FAMILY_TN (AMD_FAMILY_15_TN) +#define AMD_FAMILY_15_RL (AMD_FAMILY_15_TN) +#define AMD_FAMILY_RL (AMD_FAMILY_15_TN) +#define AMD_FAMILY_15_KV 0x0000000000000400ull +#define AMD_FAMILY_KV (AMD_FAMILY_15_KV) +#define AMD_FAMILY_15 (AMD_FAMILY_15_TN | AMD_FAMILY_15_KV) + +// Family Unknown +#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull + + +// Family 15h CPU_LOGICAL_ID.Revision equates +// ------------------------------------- + + // Family 15h TN steppings +#define AMD_F15_TN_A0 0x0000000000000100ull +#define AMD_F15_TN_A1 0x0000000000000200ull +#define AMD_F15_RL_A1 0x0000000000000400ull + // Family 15h KV steppings +#define AMD_F15_KV_A0 0x0000000000100000ull +#define AMD_F15_KV_A1 0x0000000000200000ull + // Family 15h Unknown stepping +#define AMD_F15_UNKNOWN 0x8000000000000000ull + +#define AMD_F15_RL_Ax (AMD_F15_RL_A1) +#define AMD_F15_RL_ALL (AMD_F15_RL_Ax) + +#define AMD_F15_TN_Ax (AMD_F15_TN_A0 | AMD_F15_TN_A1) +#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0) +#define AMD_F15_TN_ONLY (AMD_F15_TN_Ax) +#define AMD_F15_TN_ALL (AMD_F15_TN_Ax | AMD_F15_RL_ALL) + +#define AMD_F15_KV_Ax (AMD_F15_KV_A0 | AMD_F15_KV_A1) +#define AMD_F15_KV_ALL (AMD_F15_KV_Ax) + +#define AMD_F15_ALL (AMD_F15_TN_ALL | AMD_F15_KV_ALL) + +#endif // _CPU_FAM_REGISTERS_H_ + |