diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2022-01-31 15:29:04 -0700 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2022-02-02 22:56:43 +0000 |
| commit | 21fdd44db037e4751f9793a2fcf4a3646a70fd88 (patch) | |
| tree | 82633d2aa238cb0dbdba5d6578e0c63dbaea9661 /src/vendorcode/amd/fsp | |
| parent | 8a576f60ffa0f5d0599033304e6e7e34ea9c8ef6 (diff) | |
soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode
This will allow verstage to write post codes.
BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214 03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/fsp')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h index ff2144d159..4cf9e70686 100644 --- a/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h @@ -51,6 +51,7 @@ #define SVC_SHA 0x69 #define SVC_CCP_DMA 0x6A #define SVC_SET_PLATFORM_BOOT_MODE 0x6C +#define SVC_WRITE_POSTCODE 0x6D struct mod_exp_params { char *pExponent; // Exponent address |