diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-02-02 13:04:33 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-03 17:27:30 +0000 |
| commit | 4c4a360018315b3bd60d3cfc3506137a631ee7ba (patch) | |
| tree | 76c93db60b686ea263ff0af6a0a87ed9e72f4617 /src/vendorcode/amd/fsp/picasso | |
| parent | 275440edf1107143865413631efc3f6aace4e7a5 (diff) | |
soc/amd/picasso: clean up and re-sort UPD table
Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.
remove:
EDpPhySel
EDpVersion
rename:
DpPhyOverride -> edp_phy_override
EDpPhySel -> edp_physel
DpVsPemphLevel -> edp_dp_vs_pemph_level
MarginDeemPh -> edp_margin_deemph
Deemph6db4 -> edp_deemph_6db_4
BoostAdj -> edp_boost_adj
eDP phy setting:
DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004b
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd/fsp/picasso')
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/FspsUpd.h | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8482..aac6fdbcfb 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,26 +39,22 @@ typedef struct __packed { /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; |