diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2020-01-21 20:57:44 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-28 22:50:24 +0000 |
| commit | a57240687f56dcadecc318bba3e89ab8108596bc (patch) | |
| tree | c2108b724a4eb5e6de1a319b8a78fb915dcbe904 /src/vendorcode/amd/fsp/picasso/FspsUpd.h | |
| parent | c97bb64aadee241189f3c3ffae91115cbe33e58d (diff) | |
vc/amd/fsp/picasso: Update UPD files to version 0.0.1-r38
Include a more recent set of files from a current FSP build. These
are automatically generated.
BUG=b:153675909
TEST=Trembyle builds and boots to payload
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I6428f618afc2a1cf1c35e93e00f905f90b2cd86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38696
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/fsp/picasso/FspsUpd.h')
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/FspsUpd.h | 48 |
1 files changed, 32 insertions, 16 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index 5a154358d9..66ea60bb7b 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -13,22 +13,38 @@ typedef struct { - /** Offset 0x0020**/ uint32_t pcie_port0_topology; - /** Offset 0x0024**/ uint32_t pcie_port1_topology; - /** Offset 0x0028**/ uint32_t pcie_port2_topology; - /** Offset 0x002C**/ uint32_t pcie_port3_topology; - /** Offset 0x0030**/ uint32_t pcie_port4_topology; - /** Offset 0x0034**/ uint32_t pcie_port5_topology; - /** Offset 0x0038**/ uint32_t pcie_port6_topology; - /** Offset 0x003C**/ uint32_t pcie_sata_topology; - /** Offset 0x0040**/ uint32_t pcie_xgbe1_topology; - /** Offset 0x0044**/ uint32_t pcie_xgbe2_topology; - /** Offset 0x0048**/ uint32_t dp0_connector_type; - /** Offset 0x004C**/ uint32_t dp1_connector_type; - /** Offset 0x0050**/ uint32_t dp2_connector_type; - /** Offset 0x0054**/ uint32_t dp3_connector_type; - /** Offset 0x0058**/ uint32_t emmc0_mode; - /** Offset 0x005C**/ uint8_t UnusedUpdSpace0[196]; + /** Offset 0x0020**/ uint32_t emmc0_mode; + /** Offset 0x0024**/ uint8_t unused0[12]; + /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; + /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; + /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; + /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; + /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; + /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; + /** Offset 0x0090**/ uint32_t ddi_descriptor0; + /** Offset 0x0094**/ uint32_t ddi_descriptor1; + /** Offset 0x0098**/ uint32_t ddi_descriptor2; + /** Offset 0x009C**/ uint32_t ddi_descriptor3; + /** Offset 0x00A0**/ uint32_t unused1; + /** Offset 0x00A4**/ uint32_t unused2; + /** Offset 0x00A8**/ uint32_t unused3; + /** Offset 0x00AC**/ uint32_t unused4; + /** Offset 0x00B0**/ uint8_t fch_usb_version_major; + /** Offset 0x00B1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00B2**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x00BB**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x00C4**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x00CD**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x00D6**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x00DF**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x00E8**/ uint8_t fch_usb_device_removable; + /** Offset 0x00E9**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x00EA**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x00EB**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x00EC**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x00ED**/ uint8_t unused8; + /** Offset 0x00EE**/ uint32_t xhci_oc_pin_select; + /** Offset 0x00F2**/ uint8_t UnusedUpdSpace0[46]; /** Offset 0x0120**/ uint16_t UpdTerminator; } FSP_S_CONFIG; |