diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2015-07-29 23:54:38 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-10-30 18:24:39 +0100 |
| commit | 5fa4cb6d32b469ef8312de0c12ec648c085b9a1f (patch) | |
| tree | 7d25078fb59f9861880a4aaf1d9f807531e36637 /src/vendorcode/amd/cimx/sb900 | |
| parent | d91ddc8d3181b8ab23726c8e744093f39473c202 (diff) | |
cpu/amd: Fix cbtypes.h to match UINTN convention
There are some inconsistencies in AMDs APIs between the coreboot
code and the vendorcode code. Unify the API.
UINTN maps to uintptr_t in UEFI land. Do the same
here. Also switch the other UEFI types to map to
fixed size types.
Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb900')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/AmdSbLib.h | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/SbDef.h | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/SbMain.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/SbSubFun.h | 5 |
4 files changed, 7 insertions, 6 deletions
diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h index cf9589bfbf..47a7048560 100644 --- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h +++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h @@ -69,10 +69,10 @@ unsigned char getEfuseByte (IN unsigned char Index); AGESA_STATUS AmdSbDispatcher (IN void *pConfig); /**< AmdSbCopyMem - Reserved */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /**< GetRomSigPtr - Reserved */ -void* GetRomSigPtr (IN unsigned int* RomSigPtr); +void* GetRomSigPtr (IN UINTN * RomSigPtr); /**< RWXhciIndReg - Reserved */ void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask); diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h index 91fec4aa21..b600627e09 100644 --- a/src/vendorcode/amd/cimx/sb900/SbDef.h +++ b/src/vendorcode/amd/cimx/sb900/SbDef.h @@ -71,7 +71,7 @@ void MemoryCopy ( IN unsigned char *Dest, IN unsigned char *Source, - IN unsigned int Size + IN unsigned long Size ); //AMD Library Routines (PCILIB.C) diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c index 958e44b35e..7c9dbbdff6 100644 --- a/src/vendorcode/amd/cimx/sb900/SbMain.c +++ b/src/vendorcode/amd/cimx/sb900/SbMain.c @@ -278,7 +278,7 @@ sbSmmAcpiOn ( UINTN CallBackToOEM ( IN UINT32 Func, - IN UINT32 Data, + IN UINTN Data, IN AMDSBCFG* pConfig ) { diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h index 447f5c9603..68574a77dc 100644 --- a/src/vendorcode/amd/cimx/sb900/SbSubFun.h +++ b/src/vendorcode/amd/cimx/sb900/SbSubFun.h @@ -40,6 +40,7 @@ ; ;*********************************************************************************/ +#include <cpu/amd/common/cbtypes.h> // Southbridge SBMAIN Routines /** @@ -127,7 +128,7 @@ void sbSmmAcpiOn (IN AMDSBCFG* pConfig); * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig); +UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig); // Southbridge SBPOR Routines @@ -605,4 +606,4 @@ void TurnOffCG2 (OUT void); */ void BackUpCG2 (OUT void); -void XhciA12Fix (OUT void);
\ No newline at end of file +void XhciA12Fix (OUT void); |