diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-15 21:23:51 +1000 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-05-19 22:39:01 +0200 |
| commit | b2d68976c830c3b4eddf78ea788f02cfa6d25ffc (patch) | |
| tree | afae4f535d4e64456bc7bb003489251b6bc4a2e0 /src/vendorcode/amd/agesa | |
| parent | e1845b38c7cd4c6e18b07d82d2ba6aebd9b8170f (diff) | |
amd/agesa: Implicit assigment between enum without cast
Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5760
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa')
| -rw-r--r-- | src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c index 2ad6e1255b..942fe1f58c 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c @@ -206,7 +206,7 @@ MemNSyncTargetSpeedNb ( ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? ((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) : ((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY)); - MemClkFreq = ChnlTmgMod[1]; + MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; } } diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c index eac35b7593..3664dc59ce 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c @@ -178,7 +178,7 @@ MemNSyncTargetSpeedNb ( // ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? // (ChnlTmgMod[1] >= DDR667_FREQUENCY) : // (ChnlTmgMod[1] <= DDR1066_FREQUENCY)); - MemClkFreq = ChnlTmgMod[1]; + MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c index 613aadd936..9ff66f210d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c @@ -186,7 +186,7 @@ MemNSyncTargetSpeedNb ( ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) : ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY)); - MemClkFreq = ChnlTmgMod[1]; + MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; } } |