diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-21 15:24:42 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-05-26 11:46:47 +0000 |
| commit | 7ee8e7f12969f3141fd0b1c814c3b648268156b8 (patch) | |
| tree | 6daa19823a068acb12d5eb1e7acbacea6c88213c /src/vendorcode/amd/agesa | |
| parent | 7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344 (diff) | |
AGESA f15tn: Factor out default MTRR settings
All AGESA f15tn boards use the same MTRR values. Factor them out,
while still allowing a board to override them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index d769220dd2..1bca388000 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -62,6 +62,22 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; +/* The default fixed MTRR values to be set after memory initialization */ +static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL }, +}; /* Process solution defined socket / family installations * @@ -2425,7 +2441,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) + #define CFG_AP_MTRR_SETTINGS_LIST (TrinityApMtrrSettingsList) #endif #ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST |