diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2014-01-25 15:59:31 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-07 17:40:45 +0100 |
| commit | 2e0d9447db22183e2d3393d84e221e8bb1613d45 (patch) | |
| tree | d481c26efa3b5501505f116226d747dd36d730a3 /src/vendorcode/amd/agesa/f16kb/Proc | |
| parent | f8532b16bec1743b0528a215c71f67c8845e2a0c (diff) | |
src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc')
5 files changed, 7 insertions, 7 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c index b5a38b8021..d8243ad0ea 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S index 97f6f16dc3..5803c26e26 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S @@ -179,7 +179,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c index 24ee886c98..7f573a4cff 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c @@ -191,7 +191,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c index a568f9ec68..832e807647 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c @@ -64,7 +64,7 @@ CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE +#define FILECODE PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c index 0fc13f92d8..08c773080c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c @@ -70,7 +70,7 @@ CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE +#define FILECODE PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * |