diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2021-02-12 13:49:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-15 11:30:40 +0000 |
| commit | 6b688f5329e560ef432f6ea281b2fe3d905ef297 (patch) | |
| tree | 831ff654f7477b293421e38b8ed880f2cc740386 /src/vendorcode/amd/agesa/f16kb/Proc/Mem | |
| parent | 036d66be051c4aeeac3b6220974e93645489c27d (diff) | |
src: use ARRAY_SIZE where possible
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/Mem')
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c | 8 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c index 6ca3859b8e..95a464ae82 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c @@ -242,7 +242,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = { CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = { 0, - (sizeof (S3PciPreSelfRefDescriptorKB) / sizeof (PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3PciPreSelfRefDescriptorKB), S3PciPreSelfRefDescriptorKB, PciSpecialCaseFuncKB }; @@ -414,7 +414,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorKB[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefKB = { 0, - (sizeof (S3CPciPreSelfDescriptorKB) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPreSelfDescriptorKB), S3CPciPreSelfDescriptorKB, PciSpecialCaseFuncKB }; @@ -608,7 +608,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = { CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefKB = { 0, - (sizeof (S3CPciPostSelfDescriptorKB) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + ARRAY_SIZE(S3CPciPostSelfDescriptorKB), S3CPciPostSelfDescriptorKB, PciSpecialCaseFuncKB }; @@ -638,7 +638,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorKB[] = { CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefKB = { 0, - (sizeof (S3MSRPreSelfRefDescriptorKB) / sizeof (MSR_REG_DESCRIPTOR)), + ARRAY_SIZE(S3MSRPreSelfRefDescriptorKB), S3MSRPreSelfRefDescriptorKB, MsrSpecialCaseFuncKB }; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c index 113386e20b..f632337a3b 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mt3.c @@ -207,12 +207,12 @@ MemConstructTechBlock3 ( // // Initialize the SPD pointers for each Dimm // - for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) { + for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) { ChannelPtr->DimmSpdPtr[i] = NULL; } for (i = 0 ; i < DimmSlots; i++) { ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]); - if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) { + if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) { if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) { if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) { ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]); |