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authorWANG Siyuan <wangsiyuanbuaa@gmail.com>2013-07-31 16:55:26 +0800
committerBruce Griffith <Bruce.Griffith@se-eng.com>2013-10-15 05:01:11 +0200
commit7b6d412dbc4e5c11d3dd7890abf0edf279b3f504 (patch)
tree9d41c0b6299cab6a90616fdbc3e31d6ef67797c6 /src/vendorcode/amd/agesa/f16kb/Proc/Mem
parentf8bf5a10c599ef071998bbc3f16e9e3d7fcdb6eb (diff)
vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7
The platform initialization (PI) code v1.0.0.7 for Kabini has some enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH bug fix (RTC) and so on. Use the name Kabini instead of Kerala everywhere. Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0 as used in `AGESA_VERSION_STRING`. Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3935 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/Mem')
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c4
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c9
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c1
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c8
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c106
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c1
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c40
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c77
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c30
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c106
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h19
11 files changed, 284 insertions, 117 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
index af7bdaf357..57cc491e56 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
@@ -392,8 +392,8 @@ MemFDMISupport3 (
FormFactor = (UINT8) SpdDataStructure->Data[3];
if (((FormFactor & 0x0F) == 0x01) || ((FormFactor & 0x0F) == 0x02) || ((FormFactor & 0x0F) == 0x0B)) {
DmiPhysicalDimmInfoTable->FormFactor = 0x09; // RDIMM or UDIMM or LRDIMM
- } else if ((FormFactor & 0x0F) == 0x03) {
- DmiPhysicalDimmInfoTable->FormFactor = 0x0D; // SO-DIMM
+ } else if (((FormFactor & 0x0F) == 0x03) || ((FormFactor & 0x0F) == 0x08) || ((FormFactor & 0x0F) == 0x09) || ((FormFactor & 0x0F) == 0x0A)) {
+ DmiPhysicalDimmInfoTable->FormFactor = 0x0D; // SO-DIMM, SO-UDIMM, SO-RDIMM and SO-CDIMM
} else {
DmiPhysicalDimmInfoTable->FormFactor = 0x02; // UNKNOWN
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
index 2cba133a66..3d80bafded 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
@@ -59,6 +59,7 @@
#include "S3.h"
#include "mfs3.h"
#include "heapManager.h"
+#include "cpuFeatures.h"
#include "cpuRegisters.h"
#include "cpuPostInit.h"
#include "cpuApicUtilities.h"
@@ -491,6 +492,14 @@ MemMContextRestore (
MemFeatMain.MemClr (MemMainPtr);
}
}
+ // Set LockDramCfg, which must be done after Memory Clear
+ for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
+ if (IsFeatureEnabled (C6Cstate, MemMainPtr->MemPtr->PlatFormConfig, &(MemMainPtr->MemPtr->StdHeader))) {
+ IDS_SKIP_HOOK (IDS_LOCK_DRAM_CFG, &NBArray[Node], &MemMainPtr->MemPtr->StdHeader) {
+ NBArray[Node].SetBitField (&NBArray[Node], BFLockDramCfg, 1);
+ }
+ }
+ }
} else {
RefPtr->MemRestoreCtl = FALSE;
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
index dbc2de3ce6..b76d9e8a07 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
@@ -451,6 +451,7 @@ MemNInitNBDataKB (
NBPtr->FamilySpecificHook[DisableMemHoleMapping] = MemNDisableMemHoleMappingKB;
NBPtr->FamilySpecificHook[RestoreMemHoleMapping] = MemNRestoreMemHoleMappingKB;
NBPtr->FamilySpecificHook[PhyInitVref] = MemNPhyInitVrefKB;
+ NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] = MemNIntermediateMemclkFreqValUnb;
IEM_INSERT_CODE (IEM_NBBLOCK_INIT, IemInitNBDataOverrideKB, (NBPtr));
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
index 17a3779878..be956bcc1c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
@@ -938,6 +938,8 @@ MemNPhyPowerSavingMPstateKB (
UINT8 WrDqDqsEarly;
UINT8 i;
UINT8 j;
+ UINT16 MemClkSpeed;
+ MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) );
// 3. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][PwrDn] to disable the ECC lane if
// D18F2x90_dct[0][DimmEccEn]==0.
@@ -966,11 +968,11 @@ MemNPhyPowerSavingMPstateKB (
}
// 11. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
// (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
- MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+ MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
// 12. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
// If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
// else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
- if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
+ if (MemClkSpeed <= DDR1600_FREQUENCY) {
MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
} else {
@@ -994,7 +996,7 @@ MemNPhyPowerSavingMPstateKB (
DllPower[i] = 0x8080;
}
// 13. If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
- DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
+ DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0;
// Let MaxRxStggrDly = ((Tcl-1)*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 6.
MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
index 7c433ad033..6ca3859b8e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
@@ -185,6 +185,14 @@ MemS3ResumeConstructNBBlockKB (
IN UINT8 NodeID
);
+VOID
+MemNS3SetMemClkFreqValKB (
+ IN ACCESS_WIDTH AccessWidth,
+ IN PCI_ADDR Address,
+ IN OUT VOID *Value,
+ IN OUT VOID *ConfigPtr
+ );
+
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
@@ -201,7 +209,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = {
{MemNS3SaveNBRegisterUnb, MemNS3RestoreNBRegisterUnb},
{MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb},
{ (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegKB},
- { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb},
+ { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValKB},
{MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb},
{MemNS3GetBitFieldNb, MemNS3SetPhyFenceKB},
{ (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb},
@@ -218,8 +226,8 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
{{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703},
{{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707},
{{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00001FFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x00001FFF},
+ {{0, 0, 0}, FUNC_1, 0x120, 0x001FFFFF},
+ {{0, 0, 0}, FUNC_1, 0x124, 0x001FFFFF},
{{0, 0, 0}, FUNC_1, 0x200, 0x00FFF87B},
{{0, 0, 0}, FUNC_1, 0x204, 0x00FFF800},
{{0, 0, 0}, FUNC_2, 0x114, 0x00000200},
@@ -229,11 +237,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
{{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F},
{{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF},
{{0, 0, 0}, FUNC_2, 0x1BC, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900},
- {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1},
- {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF},
- {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0},
- {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF}
+ {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900}
};
CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = {
@@ -421,12 +425,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MASK, ANY_DIMM_MASK},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04},
@@ -437,12 +445,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04},
@@ -453,12 +465,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MASK, 0x01},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MASK, 0x04},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MASK, 0x10},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MASK, 0x40},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MASK, 0x04},
@@ -493,12 +509,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
+ {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
@@ -509,12 +529,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04},
@@ -525,12 +549,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
+ {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
@@ -562,6 +590,10 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{1, 1, 1}, DCT0, BFVrefSel, 0x00000007, DCT0_MASK, ANY_DIMM_MASK},
{{1, 2, 1}, DCT0, BFVrefDAC, 0x000001F8, DCT0_MASK, ANY_DIMM_MASK},
+ {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1, ANY_DIMM_MASK, ANY_DIMM_MASK},
+ {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
+ {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0, ANY_DIMM_MASK, ANY_DIMM_MASK},
+ {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_2, 0x1B4, 0x08000000, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_3, 0x180, 0x02000000, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_3, 0x58, 0x0000001F, ANY_DIMM_MASK, ANY_DIMM_MASK},
@@ -569,7 +601,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 0}, FUNC_3, 0x44, 0x00400004, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK},
+ {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK, S3_RESUME_MODE},
{{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK}
};
@@ -1256,3 +1288,59 @@ MemNS3SetPhyFenceKB (
MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg);
}
}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ * This function sets MemClkFreqVal bit, adding an intermediate frequency hop
+ * to 333Mhz before changing to the target DDR rate. This sequence is
+ * intended to mimic the initial boot frequency ramp.
+ *
+ * @param[in] AccessWidth - Access width of the register.
+ * @param[in] Address - address in PCI_ADDR format.
+ * @param[in, out] *Value - Pointer to the value to be written.
+ * @param[in, out] *ConfigPtr - Pointer to Config handle.
+ * @return none
+ */
+VOID
+MemNS3SetMemClkFreqValKB (
+ IN ACCESS_WIDTH AccessWidth,
+ IN PCI_ADDR Address,
+ IN OUT VOID *Value,
+ IN OUT VOID *ConfigPtr
+ )
+{
+ UINT32 TempValue;
+ UINT32 TempMemClk;
+
+ // 1. Save the current MemClkFreq
+ MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+ TempMemClk = TempValue;
+
+ // 2. Program MemClkFreq = 200MHz, MemClkFreqVal = 1;
+ TempValue &= 0xFFFFFF00;
+ TempValue |= 0x82;
+ MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+
+ // 3. Wait for FreqChgInPrg == 0
+ MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+ while ((TempValue & 0x200000) != 0) {
+ MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+ }
+
+ // 4. Program MemClkFreqVal = 0, Restore MemClkFreq
+ TempValue &= 0xFFFFFFEF;
+ MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempMemClk, ConfigPtr);
+
+ // 5. Program MemClkFreqVal = 1
+ MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+ TempValue |= 0x80;
+ MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+
+ // 6. Wait for FreqChgInPrg = 0
+ MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+ while ((TempValue & 0x200000) != 0) {
+ MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+ }
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
index cefa8dbc83..9499278b84 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
@@ -367,6 +367,7 @@ MemNStartupDCTUnb (
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
MemNSwitchDCTNb (NBPtr, Dct);
if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
+ NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] (NBPtr, NULL);
MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
index 773e7b2d61..356d4e3918 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
@@ -1152,6 +1152,8 @@ MemNPhyPowerSavingMPstateUnb (
UINT8 MaxTxStggrDly;
UINT8 Tcwl;
UINT8 i;
+ UINT16 MemClkSpeed;
+ MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) );
IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate);
// 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b.
@@ -1172,11 +1174,11 @@ MemNPhyPowerSavingMPstateUnb (
}
// 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
// (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
- MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+ MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
// 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
// If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
// else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
- if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
+ if (MemClkSpeed <= DDR1600_FREQUENCY) {
MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
} else {
@@ -1199,7 +1201,7 @@ MemNPhyPowerSavingMPstateUnb (
DllPower[i] = 0x8080;
}
// If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
- DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
+ DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0;
// Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4.
MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4);
@@ -1343,3 +1345,35 @@ MemN2DRdDQSEyeRimSearchUnb (
{
return MemT2DRdDQSEyeRimSearch (NBPtr->TechPtr);
}
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ * Hook for some families which need an intermediate Mem Clk Frequency Valid
+ * before changing to the initial startup training frequency.
+ *
+ *
+ * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
+ * @param[in,out] *OptParam - Optional parameter
+ *
+ * @return TRUE - always
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNIntermediateMemclkFreqValUnb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *OptParam
+ )
+{
+ // 1. Program MemClkFreq = 200MHz
+ MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DDR400_FREQUENCY));
+ // 2. MemClkFreqVal = 1;
+ MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
+ // 3. Wait for FreqChgInPrg == 0
+ MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+ // 4. Program MemClkFreqVal = 0
+ MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 0);
+ // 5. Retore MemClkFreq to startup value.
+ MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+ return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c
index f04c4a3e43..7503417237 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c
@@ -66,7 +66,6 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
#define SOCKET_FT3_KB 0
-
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
@@ -84,12 +83,80 @@ RDATA_GROUP (G2_PEI)
*
*-----------------------------------------------------------------------------
*/
+// Slow mode, POdtOff, Address timing and Output drive compensation for FT3
+// Format :
+// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC, POdtOff
+//
+STATIC CONST PSCFG_SAO_ENTRY KBUDdr3SAOFT3[] = {
+ {_1DIMM, DDR667 + DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222, 0},
+ {_1DIMM, DDR1066, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222, 0},
+ {_1DIMM, DDR1066, V1_5 + V1_35, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222, 0},
+ {_1DIMM, DDR1333, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20112222, 0},
+ {_1DIMM, DDR1333, V1_5 + V1_35, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0},
+ {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
+ {_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
+ {_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
+ {_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
+ {_2DIMM, DDR667 + DDR800, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0},
+ {_2DIMM, DDR667, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0},
+ {_2DIMM, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0},
+ {_2DIMM, DDR1066, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0},
+ {_2DIMM, DDR1066, V1_5 + V1_35, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0},
+ {_2DIMM, DDR1066 + DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
+ {_2DIMM, DDR1333, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0},
+ {_2DIMM, DDR1333, V1_5 + V1_35, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0},
+ {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
+ {_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
+ {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
+ {_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0},
+ {_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
+ {_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
+};
+CONST PSC_TBL_ENTRY KBSAOTblEntU3FT3 = {
+ {PSCFG_SAO, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
+ sizeof (KBUDdr3SAOFT3) / sizeof (PSCFG_SAO_ENTRY),
+ (VOID *)&KBUDdr3SAOFT3
+};
+
+// Dram Term and Dynamic Dram Term for FT3
+// Format :
+// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
+//
+// RttNom:
+// 0 On die termination disabled
+// 1 60ohms
+// 2 120ohms
+// 3 40ohms
+// 4 20ohms
+// 5 30ohms
+// RttWr:
+// 0 Dynamic termination for writes disabled.
+// 1 60ohms
+// 2 120ohms
+STATIC CONST PSCFG_RTT_ENTRY DramTermKBUDIMMFT3[] = {
+ {_1DIMM, DDR667 + DDR800 + DDR1066, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+ {_1DIMM, DDR1333 + DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+ {_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+ {_2DIMM, DDR667 + DDR800 + DDR1066, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
+ {_2DIMM, DDR667 + DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
+ {_2DIMM, DDR1066 + DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
+ {_2DIMM, DDR1333 + DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+ {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
+ {_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
+ {_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
+};
+CONST PSC_TBL_ENTRY KBDramTermTblEntUFT3 = {
+ {PSCFG_RTT, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
+ sizeof (DramTermKBUDIMMFT3) / sizeof (PSCFG_RTT_ENTRY),
+ (VOID *)&DramTermKBUDIMMFT3
+};
+
//
// MemClkDis
//
STATIC CONST UINT8 ROMDATA KBSODdr3CLKDisFT3[] = {0xFF, 0xFF, 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00};
CONST PSC_TBL_ENTRY KBClkDisMapEntSOFT3 = {
- {PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
+ {PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBSODdr3CLKDisFT3) / sizeof (UINT8),
(VOID *)&KBSODdr3CLKDisFT3
};
@@ -99,7 +166,7 @@ CONST PSC_TBL_ENTRY KBClkDisMapEntSOFT3 = {
//
STATIC CONST UINT8 ROMDATA KBSODdr3ODTTriFT3[] = {0xFF, 0xFF, 0x00, 0x00};
CONST PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3 = {
- {PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
+ {PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBSODdr3ODTTriFT3) / sizeof (UINT8),
(VOID *)&KBSODdr3ODTTriFT3
};
@@ -109,7 +176,7 @@ CONST PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3 = {
//
STATIC CONST UINT8 ROMDATA KBSODdr3CSTriFT3[] = {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
CONST PSC_TBL_ENTRY KBSODdr3CSTriEntFT3 = {
- {PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
+ {PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBSODdr3CSTriFT3) / sizeof (UINT8),
(VOID *)&KBSODdr3CSTriFT3
};
@@ -124,7 +191,7 @@ STATIC CONST PSCFG_S2D_ENTRY KBUDdr3S2DFT3[] = {
{2, ANY_SPEED, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, NP, 1}
};
CONST PSC_TBL_ENTRY S2DTblEntUFT3 = {
- {PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE + SODWN_SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
+ {PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE + SODWN_SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBUDdr3S2DFT3) / sizeof (PSCFG_S2D_ENTRY),
(VOID *)&KBUDdr3S2DFT3
};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c
index 76b85e5420..9074629749 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c
@@ -95,24 +95,18 @@ STATIC CONST PSCFG_SAO_ENTRY KBSODdr3SAO[] = {
{_1DIMM, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0},
{_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
- {_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
- {_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0},
{_2DIMM, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0},
{_2DIMM, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0},
{_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0},
{_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0},
- {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
+ {_2DIMM, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0},
{_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0},
- {_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
- {_2DIMM, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0},
- {_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
- {_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
};
CONST PSC_TBL_ENTRY KBSAOTblEntSO3 = {
{PSCFG_SAO, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -155,8 +149,6 @@ STATIC CONST PSCFG_SAO_ENTRY KBSoDwnDdr3SAO[] = {
{_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20110000, 0},
{_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30110000, 0},
{_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30110000, 0},
- {_DIMM_NONE, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30110000, 0},
- {_DIMM_NONE, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30110000, 0},
};
CONST PSC_TBL_ENTRY KBSAOTblEntSoDwn3 = {
{PSCFG_SAO, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -186,14 +178,11 @@ STATIC CONST PSCFG_RTT_ENTRY KBDramTermSODIMM3[] = {
{_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_2DIMM, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
- {_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
+ {_2DIMM, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
- {_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
- {_2DIMM, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
{_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
- {_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
};
CONST PSC_TBL_ENTRY KBDramTermTblEntSO3 = {
{PSCFG_RTT, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -250,7 +239,6 @@ STATIC CONST PSCFG_RTT_ENTRY KBDramTermSoDwn3[] = {
{_DIMM_NONE, DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
- {_DIMM_NONE, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
};
CONST PSC_TBL_ENTRY KBDramTermTblEntSoDwn3 = {
{PSCFG_RTT, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -267,9 +255,9 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSODIMM6L[] = {
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
- {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
- {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
- {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
+ {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+ {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
+ {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntSO6L = {
{PSCFG_MAXFREQ, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -304,8 +292,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSoDwnPlusSODIMM6L[] = {
{{_1DIMM, 1, 1, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
- {{_1DIMM, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
- {{_1DIMM, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
+ {{_1DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
+ {{_1DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM6L = {
{PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _1DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -335,8 +323,8 @@ CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM4L = {
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSoDwn[] = {
- {{_DIMM_NONE, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1066_FREQUENCY}},
- {{_DIMM_NONE, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1066_FREQUENCY}},
+ {{_DIMM_NONE, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
+ {{_DIMM_NONE, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn = {
{PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c
index c18af0a6c7..7e9b64eab1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c
@@ -82,77 +82,18 @@ RDATA_GROUP (G2_PEI)
*
*-----------------------------------------------------------------------------
*/
-// Slow mode, POdtOff, Address timing and Output drive compensation
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC, POdtOff
-//
-STATIC CONST PSCFG_SAO_ENTRY KBUDdr3SAO[] = {
- {_1DIMM, DDR667 + DDR800, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222, 0},
- {_1DIMM, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222, 0},
- {_1DIMM, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222, 0},
- {_1DIMM, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20112222, 0},
- {_1DIMM, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0},
- {_1DIMM, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
- {_1DIMM, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
- {_2DIMM, DDR667 + DDR800, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0},
- {_2DIMM, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0},
- {_2DIMM, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0},
- {_2DIMM, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0},
- {_2DIMM, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0},
- {_2DIMM, DDR1066 + DDR1333 + DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
- {_2DIMM, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0},
- {_2DIMM, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0},
- {_2DIMM, DDR1600 + DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
- {_2DIMM, DDR1600 + DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
-};
-CONST PSC_TBL_ENTRY KBSAOTblEntU3 = {
- {PSCFG_SAO, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
- sizeof (KBUDdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
- (VOID *)&KBUDdr3SAO
-};
-
-// Dram Term and Dynamic Dram Term
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
-//
-// RttNom:
-// 0 On die termination disabled
-// 1 60ohms
-// 2 120ohms
-// 3 40ohms
-// 4 20ohms
-// 5 30ohms
-// RttWr:
-// 0 Dynamic termination for writes disabled.
-// 1 60ohms
-// 2 120ohms
-STATIC CONST PSCFG_RTT_ENTRY DramTermKBUDIMM[] = {
- {_1DIMM, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
- {_1DIMM, DDR1333 + DDR1600 + DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
- {_2DIMM, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
- {_2DIMM, DDR667 + DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
- {_2DIMM, DDR1066 + DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
- {_2DIMM, DDR1333 + DDR1600 + DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
- {_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
-};
-CONST PSC_TBL_ENTRY KBDramTermTblEntU = {
- {PSCFG_RTT, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
- sizeof (DramTermKBUDIMM) / sizeof (PSCFG_RTT_ENTRY),
- (VOID *)&DramTermKBUDIMM
-};
-
// Max Freq. for UDIMM <6-layer Motherboard Design> configuration
// Format :
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM6L[] = {
- {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@@ -160,18 +101,37 @@ CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = {
(VOID *)&MaxFreqKBUDIMM6L
};
+// Max Freq. for UDIMM <6-layer Motherboard Design> configuration for microserver
+// Format :
+// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
+//
+STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = {
+ {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+};
+CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = {
+ {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
+ sizeof (MaxFreqKBMicroSrvUDIMM6L) / sizeof (PSCFG_MAXFREQ_ENTRY),
+ (VOID *)&MaxFreqKBMicroSrvUDIMM6L
+};
+
// Max Freq. for UDIMM <4-layer Motherboard Design> configuration
// Format :
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM4L[] = {
- {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
- {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
+ {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
index 4783cd3e0d..feddf9f541 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
@@ -364,6 +364,8 @@ typedef struct _MEM_PS_BLOCK {
UINT8 NumOfDimmSlots; ///< See enum type NOD_SUPPORTED
UINT8 DimmType; ///< See enum type DIMM_TYPE
UINT16 RankType; ///< Rank type of all populated DIMMs. See MemPGetPsRankType.
+ UINT8 MotherboardLayer; ///< See enum type MB_LAYER_TYPE
+ UINT8 MotherboardPower; ///< See enum type MB_POWER_TYPE
} MEM_PS_BLOCK;
/// Structure parameters needed in frequency change of client NB.
@@ -445,7 +447,8 @@ typedef enum {
AMPIsEnabled, ///< Check to detemine if AMP is exactly enabled.
ScrubberEn, ///< Check to determine if DRAM scrubber is already enabled
SwitchRdDqsDlyForMaxRdLatency, ///< Use the different RdDqsDly value for MaxRdLatency calculation before/after DQS training
-
+ SelectMotherboardLayer, ///< Check to determine if multiple motherboard layer design applies
+ SelectMotherboardPower, ///< Check to determine if multiple motherboard power design applies
EnumSize ///< Size of list
} NB_SUPPORTED;
@@ -548,6 +551,7 @@ typedef enum {
DisableMemHoleMapping, ///< Disable Memory Hole Settings
RestoreMemHoleMapping, ///< Enable Memory Hole Settings
PhyInitVref, ///< Program VrefSel during phy init
+ IntermediateMemclkFreqVal, ///< Workaround for some families needing intermediate frequency valid
NumberOfHooks ///< Size of list
} FAMILY_SPECIFIC_FUNC_INDEX;
@@ -629,6 +633,7 @@ typedef struct _MEM_NB_BLOCK {
BOOLEAN OrigDisAutoRefreshState; ///< Original state of Dis Auto Refresh
BOOLEAN Execute1dMaxRdLatTraining; ///< Indicates if 1D training should be executed
BOOLEAN Override2DTraining; ///< 2D training has been overriden
+ UINT8 PmuFirmwareImage; ///< PMU firmware image to be use.
MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE.
MEM_DCT_CACHE *DctCachePtr; ///< pointer to current Node's Node struct
@@ -1575,5 +1580,17 @@ VOID
MemNSetEccExclusionRangeUnb (
IN OUT MEM_NB_BLOCK *NBPtr
);
+
+UINT32
+MemNGetNbClkFreqByPstateUnb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN UINT32 NBPstate
+ );
+
+BOOLEAN
+MemNIntermediateMemclkFreqValUnb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *OptParam
+ );
#endif /* _MN_H_ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-25 15:34:23 +0000