diff options
author | Mike Banon <mikebdp2@gmail.com> | 2020-04-17 14:35:20 +0300 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-12-02 17:05:39 +0000 |
commit | 3ee9935f6342b224e46a16d9148d0eedc43fff90 (patch) | |
tree | db5625017ae2c32504e7196f1896b28ebd6a8239 /src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3 | |
parent | 03a339126b35341b3b1baa85e596602a7facb1ed (diff) |
vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
Add XMP memory profiles support that has been tested on f15tn (A88XM-E)
and f16kb (AM1I-A) with two Crucial BLT8G3D1869DT1TX0, XMP 1 profile.
Added using the datasheets from https://github.com/mikebdp2/ddr3spd :
JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40488
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3')
-rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h | 83 |
1 files changed, 73 insertions, 10 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f13c..bc608a5052 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,82 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 +#define SPD_TWR 17 #define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ #define SPD_TRAS 22 -#define SPD_TWR 17 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +188,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38 -#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *----------------------------- |