vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7

The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.

Use the name Kabini instead of Kerala everywhere.

Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.

Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

5 files changed, 141 insertions, 15 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
index dbc2de3ce6..b76d9e8a07 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
@@ -451,6 +451,7 @@ MemNInitNBDataKB (
   NBPtr->FamilySpecificHook[DisableMemHoleMapping] = MemNDisableMemHoleMappingKB;
   NBPtr->FamilySpecificHook[RestoreMemHoleMapping] = MemNRestoreMemHoleMappingKB;
   NBPtr->FamilySpecificHook[PhyInitVref] = MemNPhyInitVrefKB;
+  NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] = MemNIntermediateMemclkFreqValUnb;
 
   IEM_INSERT_CODE (IEM_NBBLOCK_INIT, IemInitNBDataOverrideKB, (NBPtr));
 }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
index 17a3779878..be956bcc1c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
@@ -938,6 +938,8 @@ MemNPhyPowerSavingMPstateKB (
   UINT8 WrDqDqsEarly;
   UINT8 i;
   UINT8 j;
+  UINT16 MemClkSpeed;
+  MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) );
 
   // 3. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][PwrDn] to disable the ECC lane if
   // D18F2x90_dct[0][DimmEccEn]==0.
@@ -966,11 +968,11 @@ MemNPhyPowerSavingMPstateKB (
   }
   // 11. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
   // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
-  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
   // 12. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
   // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
   // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
-  if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
+  if (MemClkSpeed <= DDR1600_FREQUENCY) {
     MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
     MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
   } else {
@@ -994,7 +996,7 @@ MemNPhyPowerSavingMPstateKB (
       DllPower[i] = 0x8080;
     }
     // 13. If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
-    DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
+    DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0;
     // Let MaxRxStggrDly = ((Tcl-1)*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 6.
     MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
     Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
index 7c433ad033..6ca3859b8e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
@@ -185,6 +185,14 @@ MemS3ResumeConstructNBBlockKB (
   IN       UINT8 NodeID
   );
 
+VOID
+MemNS3SetMemClkFreqValKB (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                          DEFINITIONS AND MACROS
  *
@@ -201,7 +209,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = {
   {MemNS3SaveNBRegisterUnb, MemNS3RestoreNBRegisterUnb},
   {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb},
   { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegKB},
-  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb},
+  { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValKB},
   {MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb},
   {MemNS3GetBitFieldNb, MemNS3SetPhyFenceKB},
   { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb},
@@ -218,8 +226,8 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
   {{0, 0, 0}, FUNC_1, 0x40,  0xFFFF0703},
   {{0, 0, 0}, FUNC_1, 0x44,  0xFFFF0707},
   {{0, 0, 0}, FUNC_1, 0xF0,  0xFF00FF83},
-  {{0, 0, 0}, FUNC_1, 0x120, 0x00001FFF},
-  {{0, 0, 0}, FUNC_1, 0x124, 0x00001FFF},
+  {{0, 0, 0}, FUNC_1, 0x120, 0x001FFFFF},
+  {{0, 0, 0}, FUNC_1, 0x124, 0x001FFFFF},
   {{0, 0, 0}, FUNC_1, 0x200, 0x00FFF87B},
   {{0, 0, 0}, FUNC_1, 0x204, 0x00FFF800},
   {{0, 0, 0}, FUNC_2, 0x114, 0x00000200},
@@ -229,11 +237,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
   {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F},
   {{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF},
   {{0, 0, 0}, FUNC_2, 0x1BC, 0xFFFFFFFF},
-  {{0, 0, 0}, FUNC_2, 0xA4,  0x00F07900},
-  {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1},
-  {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF},
-  {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0},
-  {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF}
+  {{0, 0, 0}, FUNC_2, 0xA4,  0x00F07900}
 };
 
 CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = {
@@ -421,12 +425,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{1, 2, 1}, DCT0,   BFRxDqInsDly, 0, DCT0_MASK, ANY_DIMM_MASK},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x03FF03FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x03FF03FF, DCT0_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000003FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x03FF03FF, DCT0_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x03FF03FF, DCT0_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000003FF, DCT0_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x03FF03FF, DCT0_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x03FF03FF, DCT0_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000003FF, DCT0_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x03FF03FF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x03FF03FF, DCT0_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000003FF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x03FF03FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x03FF03FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x03FF03FF, DCT0_MASK, 0x04},
@@ -437,12 +445,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x03FF03FF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0xFFFFFFFF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0xFFFFFFFF, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x000000FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3E3E3E3E, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3E3E3E3E, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04},
@@ -453,12 +465,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_MASK, 0x04},
@@ -493,12 +509,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{1, 2, 1}, DCT0,   BFRxDqInsDly, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12),  0x000003FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15),  0x000003FF, DCT0_MEMPSTATE_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18),  0x000003FF, DCT0_MEMPSTATE_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B),  0x000003FF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
@@ -509,12 +529,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A),  0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01),  0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02),  0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03),  0x000000FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05),  0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06),  0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04},
@@ -525,12 +549,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32),  0x000000FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35),  0x000000FF, DCT0_MEMPSTATE_MASK, 0x04},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38),  0x000000FF, DCT0_MEMPSTATE_MASK, 0x10},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
+  {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B),  0x000000FF, DCT0_MEMPSTATE_MASK, 0x40},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
   {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43),  0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
@@ -562,6 +590,10 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{1, 1, 1}, DCT0,   BFVrefSel, 0x00000007, DCT0_MASK, ANY_DIMM_MASK},
   {{1, 2, 1}, DCT0,   BFVrefDAC, 0x000001F8, DCT0_MASK, ANY_DIMM_MASK},
 
+  {{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
   {{0, 0, 0}, FUNC_2, 0x1B4, 0x08000000, ANY_DIMM_MASK, ANY_DIMM_MASK},
   {{0, 0, 0}, FUNC_3, 0x180, 0x02000000, ANY_DIMM_MASK, ANY_DIMM_MASK},
   {{0, 0, 0}, FUNC_3, 0x58,  0x0000001F, ANY_DIMM_MASK, ANY_DIMM_MASK},
@@ -569,7 +601,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
   {{0, 0, 0}, FUNC_3, 0x44,  0x00400004, ANY_DIMM_MASK, ANY_DIMM_MASK},
 
   {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK},
-  {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK},
+  {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK, S3_RESUME_MODE},
 
   {{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK}
 };
@@ -1256,3 +1288,59 @@ MemNS3SetPhyFenceKB (
     MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg);
   }
 }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function sets MemClkFreqVal bit, adding an intermediate frequency hop
+ *     to 333Mhz before changing to the target DDR rate. This sequence is
+ *     intended to mimic the initial boot frequency ramp.
+ *
+ *     @param[in]   AccessWidth - Access width of the register.
+ *     @param[in]   Address - address in PCI_ADDR format.
+ *     @param[in, out]  *Value - Pointer to the value to be written.
+ *     @param[in, out]  *ConfigPtr - Pointer to Config handle.
+ *     @return         none
+ */
+VOID
+MemNS3SetMemClkFreqValKB (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR Address,
+  IN OUT   VOID *Value,
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  UINT32 TempValue;
+  UINT32 TempMemClk;
+
+  // 1. Save the current MemClkFreq
+  MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  TempMemClk = TempValue;
+
+  // 2. Program MemClkFreq = 200MHz, MemClkFreqVal = 1;
+  TempValue &= 0xFFFFFF00;
+  TempValue |= 0x82;
+  MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+
+  // 3. Wait for FreqChgInPrg == 0
+  MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  while ((TempValue & 0x200000) != 0) {
+    MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  }
+
+  // 4. Program MemClkFreqVal = 0, Restore MemClkFreq
+  TempValue &= 0xFFFFFFEF;
+  MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempMemClk, ConfigPtr);
+
+  // 5. Program MemClkFreqVal = 1
+  MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  TempValue |= 0x80;
+  MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+
+  // 6. Wait for FreqChgInPrg = 0
+  MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  while ((TempValue & 0x200000) != 0) {
+    MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
index cefa8dbc83..9499278b84 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
@@ -367,6 +367,7 @@ MemNStartupDCTUnb (
     for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
       MemNSwitchDCTNb (NBPtr, Dct);
       if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
+        NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] (NBPtr, NULL);
         MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
         MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
       }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
index 773e7b2d61..356d4e3918 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
@@ -1152,6 +1152,8 @@ MemNPhyPowerSavingMPstateUnb (
   UINT8 MaxTxStggrDly;
   UINT8 Tcwl;
   UINT8 i;
+  UINT16 MemClkSpeed;
+  MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) );
 
   IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate);
   // 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b.
@@ -1172,11 +1174,11 @@ MemNPhyPowerSavingMPstateUnb (
   }
   // 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
   // (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
-  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
+  MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
   // 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
   // If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
   // else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
-  if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
+  if (MemClkSpeed <= DDR1600_FREQUENCY) {
     MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
     MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
   } else {
@@ -1199,7 +1201,7 @@ MemNPhyPowerSavingMPstateUnb (
       DllPower[i] = 0x8080;
     }
     // If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
-    DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
+    DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0;
     // Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4.
     MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
     ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4);
@@ -1343,3 +1345,35 @@ MemN2DRdDQSEyeRimSearchUnb (
 {
   return MemT2DRdDQSEyeRimSearch (NBPtr->TechPtr);
 }
+
+/*-----------------------------------------------------------------------------
+ *
+ *
+ *     Hook for some families which need an intermediate Mem Clk Frequency Valid
+ *       before changing to the initial startup training frequency.
+ *
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  *OptParam   - Optional parameter
+ *
+ *     @return  TRUE - always
+ * ----------------------------------------------------------------------------
+ */
+BOOLEAN
+MemNIntermediateMemclkFreqValUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  // 1. Program MemClkFreq = 200MHz
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DDR400_FREQUENCY));
+  // 2. MemClkFreqVal = 1;
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
+  // 3. Wait for FreqChgInPrg == 0
+  MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
+  // 4. Program MemClkFreqVal = 0
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 0);
+  // 5. Retore MemClkFreq to startup value.
+  MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, NBPtr->DCTPtr->Timings.Speed));
+  return TRUE;
+}