diff options
| author | Konstantin Aladyshev <aladyshev22@gmail.com> | 2017-08-01 14:29:20 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-02 05:29:03 +0000 |
| commit | 8656914cda9a43df8abd9aa56f73cb179da0570d (patch) | |
| tree | 9aa36105c8c5d817464f5c589ee6ab1fc67150fb /src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c | |
| parent | 14c8f71b0b24058ce7f7b44ca958d5a8ad96ba1c (diff) | |
AGESA: Correct PCI function number for MEM_GET(SET)REG outputs
PCI function number takes only 3 bits, therefore
correct bitmask for it is 0x7.
Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c index df810d0df1..f8b70b877a 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c @@ -234,7 +234,7 @@ MemNCmnGetSetFieldKB ( if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Value); + (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -265,7 +265,7 @@ MemNCmnGetSetFieldKB ( if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { ASSERT (!NBPtr->IsSupported[ScrubberEn]); // Phy CSR write is not allowed after scrubber is enabled |