AMD Kabini: Add AGESA/PI code for new processor family

Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Nick Dill <nick.dill@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>

2 files changed, 431 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
new file mode 100644
index 0000000000..edf877264b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c
@@ -0,0 +1,376 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Configure Max Payload
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision:
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "PcieMaxPayload.h"
+#include  "OptionGnb.h"
+#include  "GnbFamServices.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  UINT8                   MaxPayload;
+} PCIE_MAX_PAYLOAD_DATA;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+SCAN_STATUS
+PcieGetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+SCAN_STATUS
+PcieSetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+AGESA_STATUS
+PciePayloadBlackListFeature (
+  IN       PCI_ADDR               Device,
+  IN       UINT8                  *MaxPayload,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+PcieMaxPayloadInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine maximum payload size for PCIe segment
+ *
+ *  Scan through all link in segment to determine maximum payload by EPs.
+ *
+ * @param[in]   DownstreamPort    PCI address of PCIe port
+ * @param[in]   EngineMaxPayload  MaxPayload supported by the engine
+ * @param[in]   StdHeader         Standard configuration header
+ *
+ */
+
+VOID
+PcieSetMaxPayload (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       UINT8                   EngineMaxPayload,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_MAX_PAYLOAD_DATA  PcieMaxPayloadData;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayload for Device = %d:%d:%d\n",
+    DownstreamPort.Address.Bus,
+    DownstreamPort.Address.Device,
+    DownstreamPort.Address.Function
+    );
+  PcieMaxPayloadData.MaxPayload = EngineMaxPayload;
+  PcieMaxPayloadData.ScanData.StdHeader = StdHeader;
+  PcieMaxPayloadData.ScanData.GnbScanCallback = PcieGetMaxPayloadCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData);
+  PcieMaxPayloadData.ScanData.GnbScanCallback = PcieSetMaxPayloadCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayloadExit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieGetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_MAX_PAYLOAD_DATA   *PcieMaxPayloadData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT32                  Value;
+  UINT8                   PcieCapPtr;
+  UINT8                   DeviceMaxPayload;
+
+  PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieGetMaxPayloadCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (
+      Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER),
+      AccessWidth32,
+      &Value,
+      ScanData->StdHeader
+    );
+    DeviceMaxPayload = (UINT8) (Value & 0x7);
+    PciePayloadBlackListFeature (Device, &DeviceMaxPayload, ScanData->StdHeader);
+    IDS_HDT_CONSOLE (GNB_TRACE, "  Found DeviceMaxPayload as %d (Value = %x\n", DeviceMaxPayload, Value);
+    if (DeviceMaxPayload < PcieMaxPayloadData->MaxPayload) {
+      PcieMaxPayloadData->MaxPayload = DeviceMaxPayload;
+    }
+  }
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure the Max Payload setting to all devices in the PCIe Segment
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieSetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_MAX_PAYLOAD_DATA   *PcieMaxPayloadData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT8                   PcieCapPtr;
+
+  PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayloadCallback for Device = %d:%d:%d to %d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function,
+    PcieMaxPayloadData->MaxPayload
+    );
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CTRL_REGISTER),
+      AccessWidth32,
+      ~(UINT32) (0x7 << 5),
+      ((UINT32)PcieMaxPayloadData->MaxPayload << 5),
+      ScanData->StdHeader
+    );
+  }
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
+UINT16  PayloadBlacklistDeviceTable[] = {
+  0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Max_Payload_Size Black List
+ *
+ *
+ *
+ * @param[in] Device              PCI_ADDR of PCIe Device to evaluate
+ * @param[in] MaxPayload          Pointer to Max_Payload_Size value
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PciePayloadBlackListFeature (
+  IN       PCI_ADDR               Device,
+  IN       UINT8                  *MaxPayload,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  TargetDeviceId;
+  UINTN   i;
+  UINT32  DeviceId;
+  UINT32  VendorId;
+
+  GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader);
+  for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    VendorId = PayloadBlacklistDeviceTable[i];
+    DeviceId = PayloadBlacklistDeviceTable[i + 1];
+    if (VendorId == (UINT16)TargetDeviceId) {
+      if (DeviceId == 0xFFFF || DeviceId == (TargetDeviceId >> 16)) {
+        *MaxPayload = (UINT8) PayloadBlacklistDeviceTable[i + 2];
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieMaxPayloadInitCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_MAXPAYLOAD_SERVICE   *PcieMaxPayloadProtocol;
+  UINT8                     EngineMaxPayload;
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+
+
+
+  if ((GnbBuildOptions.CfgMaxPayloadEnable != 0) &&
+      (!PcieConfigIsSbPcieEngine (Engine)) &&
+      (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS))) {
+    EngineMaxPayload =  MAX_PAYLOAD;
+    Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+    Status = GnbLibLocateService (GnbPcieMaxPayloadService, Complex->SocketId, (VOID **)&PcieMaxPayloadProtocol, GnbLibGetHeader (Pcie));
+    if (Status ==  AGESA_SUCCESS) {
+      EngineMaxPayload = PcieMaxPayloadProtocol->SetMaxPayload (Engine);
+    }
+    PcieSetMaxPayload (Engine->Type.Port.Address, EngineMaxPayload, GnbLibGetHeader (Pcie));
+  }
+}
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Interface to configure MaxPayloadSize on PCIE interface
+ *
+ *
+ *
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    AGESA_STATUS
+ */
+ /*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieMaxPayloadInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadInterface Enter\n");
+  AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieMaxPayloadInitCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadInterface Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h
new file mode 100644
index 0000000000..d36724400e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Configure Max Payload
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEMAXPAYLOAD_H_
+#define _PCIEMAXPAYLOAD_H_
+
+VOID
+PcieSetMaxPayload (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       UINT8                   EngineMaxPayload,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+#endif