AMD Kabini: Add AGESA/PI code for new processor family

Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Nick Dill <nick.dill@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>

7 files changed, 1202 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h
new file mode 100644
index 0000000000..f2bdf75d24
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/GnbPcieInitLibV5.h
@@ -0,0 +1,141 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Init Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 87271 $   @e \$Date: 2013-01-31 10:11:23 -0600 (Thu, 31 Jan 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIEINITLIBV5_H_
+#define _GNBPCIEINITLIBV5_H_
+
+VOID
+PciePifApplyGangingV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerDownV5 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyApplyLaneMuxV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+BOOLEAN
+PcieTopologyIsGen3SupportedV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  );
+
+VOID
+PciePwrPowerDownUnusedLanesV5 (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePwrClockGatingV5 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PciePortsVisibilityControlV5 (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PcieLinkInitHotplugV5 (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieEnableSlotPowerLimitV5 (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PciePhyApplyGangingV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyChannelCharacteristicV5 (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyLaneControlV5 (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyReduceLinkWidthV5 (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyExecuteReconfigV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetLs2ExitTimeV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c
new file mode 100644
index 0000000000..bc5023431e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c
@@ -0,0 +1,111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersCommonV2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+PciePhyApplyGangingV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyChannelCharacteristicV5 (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PHY channel characteristic
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyChannelCharacteristicV5 (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  /// @todo
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c
new file mode 100644
index 0000000000..1f7dc6545d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c
@@ -0,0 +1,269 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 88079 $   @e \$Date: 2013-02-15 15:28:53 -0600 (Fri, 15 Feb 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersCommonV2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+PciePifApplyGangingV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerDownV5 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetLs2ExitTimeV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply PIF ganging for all lanes for given wrapper
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifApplyGangingV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG      *EngineList;
+  UINT32                  LaneBitmap;
+  D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011;
+  D0F0xE4_PIF_0011.Value = 0;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGangingV5 Enter\n");
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList);
+      switch (LaneBitmap) {
+      case  0x0003:
+        D0F0xE4_PIF_0011.Field.X2Lane10 = 0x1;
+        break;
+      case  0x000c:
+        D0F0xE4_PIF_0011.Field.X2Lane32 = 0x1;
+        break;
+      case  0x0030:
+        D0F0xE4_PIF_0011.Field.X2Lane54 = 0x1;
+        break;
+      case  0x00c0:
+        D0F0xE4_PIF_0011.Field.X2Lane76 = 0x1;
+        break;
+      case  0x000f:
+        D0F0xE4_PIF_0011.Field.X4Lane30 = 0x1;
+        break;
+      case  0x00f0:
+        D0F0xE4_PIF_0011.Field.X4Lane74 = 0x1;
+        break;
+      case  0x00ff:
+        D0F0xE4_PIF_0011.Field.X8Lane70 = 0x1;
+        break;
+      case  0x0300:
+        D0F0xE4_PIF_0011.Field.X2Lane98 = 0x1;
+        break;
+      case  0x0c00:
+        D0F0xE4_PIF_0011.Field.X2Lane1110 = 0x1;
+        break;
+      case  0x3000:
+        D0F0xE4_PIF_0011.Field.X2Lane1312 = 0x1;
+        break;
+      case  0xc000:
+        D0F0xE4_PIF_0011.Field.X2Lane1514 = 0x1;
+        break;
+      case  0x0f00:
+        D0F0xE4_PIF_0011.Field.X4Lane118 = 0x1;
+        break;
+      case  0xf000:
+        D0F0xE4_PIF_0011.Field.X4Lane1512 = 0x1;
+        break;
+      case  0xff00:
+        D0F0xE4_PIF_0011.Field.X8Lane158 = 0x1;
+        break;
+      case  0xffff:
+        D0F0xE4_PIF_0011.Field.X16Lane150 = 0x1;
+        break;
+      default:
+        break;
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0011_ADDRESS),
+    D0F0xE4_PIF_0011.Value,
+    FALSE,
+    Pcie
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGangingV5 Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL powerdown
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllPowerDownV5 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT16                  NibbleBitmap;
+  UINT16                  PifRegAffress;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDownV5 Enter\n");
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    NibbleBitmap = (0xF << (Nibble * 4));
+    if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) {
+      PifRegAffress = ((Nibble < 2) ? D0F0xE4_PIF_0012_ADDRESS : D0F0xE4_PIF_0017_ADDRESS) + (Nibble & 0x1);
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, 0, PifRegAffress),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, 0, PifRegAffress),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDownV5 Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program LS2 exit time
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetLs2ExitTimeV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTimeV5 Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET,
+        D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH,
+        0x5,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTimeV5 Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c
new file mode 100644
index 0000000000..803d134dd1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV5.h"
+#include  "GnbRegistersCommonV2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init hotplug port
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkInitHotplugV5 (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  PcieLinkInitHotplug (Engine, Pcie);
+  if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) {
+    Value = 1;
+  } else {
+    Value = 0;
+  }
+  PciePortRegisterWriteField (
+    Engine,
+    0x10,
+    3,
+    1,
+    Value,
+    TRUE,
+    Pcie
+    );
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set slot power limit
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @param[in]  Pcie                Pointer to PCIe configuration
+ */
+
+
+VOID
+PcieEnableSlotPowerLimitV5 (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG   *Silicon;
+  if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "   Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
+    Silicon = PcieConfigGetParentSilicon (Engine);
+    GnbLibPciIndirectRMW (
+      Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
+      D0F0xCC_x01_ADDRESS | ((Engine->Type.Port.PortData.DeviceNumber << 3 | Engine->Type.Port.PortData.FunctionNumber)  << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << D0F0xCC_x01_SetPowEn_OFFSET,
+      GnbLibGetHeader (Pcie)
+    );
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
new file mode 100644
index 0000000000..0b2be80970
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c
@@ -0,0 +1,198 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe complex initialization services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV5.h"
+#include  "GnbRegistersCommonV2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+PcieSiliconControlPortsV5 (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_SILICON_CONFIG     *Silicon,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+STATIC
+PcieSiliconEnablePortsV5 (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Control port visibility in PCI config space
+ *
+ *
+ * @param[in]  Control         Control Hide/Unhide ports
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PciePortsVisibilityControlV5 (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG *SiliconList;
+  SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  while (SiliconList != NULL) {
+    switch (Control) {
+    case UnhidePorts:
+      PcieSiliconControlPortsV5 (UnhidePorts, SiliconList, Pcie);
+      break;
+    case HidePorts:
+      PcieSiliconControlPortsV5 (HidePorts, SiliconList, Pcie);
+      PcieSiliconEnablePortsV5 (SiliconList, Pcie);
+      break;
+    default:
+      ASSERT (FALSE);
+    }
+    SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (SiliconList, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Hide/Unhide all ports
+ *
+ *
+ * @param[in]  Control             Control Hide/Unhide ports
+ * @param[in]  Silicon             Pointer to silicon configuration descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+STATIC
+PcieSiliconControlPortsV5 (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_SILICON_CONFIG     *Silicon,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT32              Value;
+  Value = (Control == HidePorts) ? ((1 << D0F0xCC_x01_BridgeDis_OFFSET) | (1 << D0F0xCC_x01_CfgDis_OFFSET)) : 0;
+  EngineList = PcieConfigGetChildEngine (Silicon);
+  while (EngineList != NULL) {
+    if (PcieConfigIsPcieEngine (EngineList)) {
+      GnbLibPciIndirectRMW (
+        Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
+        D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.NativeDevNumber << 3 | EngineList->Type.Port.NativeFunNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
+        AccessS3SaveWidth32,
+        (UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
+        Value,
+        GnbLibGetHeader (Pcie)
+        );
+    }
+    EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Hide unused ports
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configuration data area
+ * @param[in]  Pcie                Pointer to data area up to 256 byte
+ */
+
+VOID
+STATIC
+PcieSiliconEnablePortsV5 (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  EngineList = PcieConfigGetChildEngine (Silicon);
+  while (EngineList != NULL) {
+    if (PcieConfigIsPcieEngine (EngineList)) {
+      if (!PcieConfigIsSbPcieEngine (EngineList) &&
+        (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+        ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) &&
+        (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard)))) {
+        GnbLibPciIndirectRMW (
+          Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
+          D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.PortData.DeviceNumber << 3 | EngineList->Type.Port.PortData.FunctionNumber)  << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
+          AccessS3SaveWidth32,
+          (UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
+          ((1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET)),
+          GnbLibGetHeader (Pcie)
+        );
+      }
+    }
+    EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c
new file mode 100644
index 0000000000..9c602e1442
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV5.h"
+#include  "GnbRegistersCommonV2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lanes enable/disable control
+ *
+ * @param[in]   Control             Lane control action
+ * @param[in]   LaneBitMap          Core lanes bitmap
+ * @param[in]   Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyLaneControlV5 (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+    )
+{
+  D0F0xE4_WRAP_8029_STRUCT  D0F0xE4_WRAP_8029;
+  D0F0xE4_WRAP_8029.Value = PcieRegisterRead (
+                            Wrapper,
+                            WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8029_ADDRESS),
+                            Pcie
+                            );
+
+  if (Control == EnableLanes) {
+    D0F0xE4_WRAP_8029.Value |= LaneBitMap;
+  } else if (Control == DisableLanes) {
+    D0F0xE4_WRAP_8029.Value &= (~LaneBitMap);
+  }
+  D0F0xE4_WRAP_8029.Value &= ((1 << Wrapper->NumberOfLanes) - 1);
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8029_ADDRESS),
+    D0F0xE4_WRAP_8029.Value,
+    TRUE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Reduce link width
+ *
+ *
+ * @param[in]  LinkWidth           Link width
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyReduceLinkWidthV5 (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG       *Wrapper;
+  UINT32                    LinkReversed;
+  UINT8                     DeltaLinkWidthBitmap;
+  UINT32                    LanesToDisable;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
+
+  DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
+  LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane +  LinkWidth)));
+
+  PcieTopologyLaneControlV5 (
+    DisableLanes,
+    LanesToDisable,
+    Wrapper,
+    Pcie
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c
new file mode 100644
index 0000000000..89547bfd95
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c
@@ -0,0 +1,184 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV5.h"
+#include  "GnbRegistersCommonV2.h"
+#include  "GnbSmuInitLibV7.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+UINT8 LaneMuxSelectorArrayV5[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if lane topology supports Gen3
+ *
+ *  Check if more that one link mapped to single PIF slice
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ */
+
+BOOLEAN
+PcieTopologyIsGen3SupportedV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  )
+{
+  UINT8                 LaneNibbleArray [4];
+  UINT32                LaneBitmap;
+  UINT8                 Nibble;
+  UINT8                 NibbleBitmap;
+  PCIe_ENGINE_CONFIG    *Engine;
+
+
+  LibAmdMemFill (&LaneNibbleArray[0], 0x00, sizeof (LaneNibbleArray), PcieConfigGetStdHeader (Wrapper));
+  Engine = PcieConfigGetChildEngine (Wrapper);
+  while (Engine != NULL) {
+    LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Engine);
+    for (Nibble = 0; Nibble < 4; Nibble++) {
+      NibbleBitmap = (0xF << (Nibble * 4));
+      if ((LaneBitmap & NibbleBitmap) != 0) {
+        if (++LaneNibbleArray [Nibble] > 1) {
+          return FALSE;
+        }
+      }
+    }
+    Engine = PcieLibGetNextDescriptor (Engine);
+  }
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute/clean up reconfiguration
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyExecuteReconfigV5 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  PCIe_SILICON_CONFIG       *Silicon;
+  DEV_OBJECT                DevObject;
+
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Enter\n");
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
+    D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x2;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+
+    Silicon = PcieConfigGetParentSilicon (Wrapper);
+    DevObject.StdHeader = GnbLibGetHeader (Pcie);
+    DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
+    DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue;
+    GnbSmuServiceRequestV7 (
+      &DevObject,
+      25,
+      0,
+      0
+      );
+
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV5 Exit\n");
+  }
+}