AMD Kabini: Add AGESA/PI code for new processor family

Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Nick Dill <nick.dill@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>

21 files changed, 4411 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
new file mode 100644
index 0000000000..01cd3530a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
@@ -0,0 +1,60 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Init Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEINITLIBV1_H_
+#define _PCIEINITLIBV1_H_
+
+#include "PciePifServices.h"
+#include "PciePortRegAcc.h"
+#include "PciePowerMgmt.h"
+#include "PcieTimer.h"
+#include "PcieTopologyServices.h"
+#include "PcieUtilityLib.h"
+#include "PcieWrapperRegAcc.h"
+#include "PcieAspmExitLatency.h"
+#include "PcieSiliconServices.h"
+#include "PciePortServices.h"
+#include "PcieAspm.h"
+#include "PciePhyServices.h"
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
new file mode 100644
index 0000000000..64e7cb36fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -0,0 +1,173 @@
+/**
+ * @file
+ *
+ * PCIe link ASPM Black List
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "PcieAspmBlackList.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+UINT16  AspmBrDeviceTable[] = {
+ 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x168C, 0xFFFF, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x9123, (UINT16) ~(AspmL0s),
+ 0x1969, 0x1083, (UINT16) ~(AspmL0s),
+ 0x1033, 0x0194, (UINT16) ~(AspmL0s),
+ 0x1180, 0xE832, (UINT16) ~(AspmL0s),
+ 0x1180, 0xE823, (UINT16) ~(AspmL0s)
+};
+
+UINT16  Aspm168cL0sEnabled[] = {
+  0x002B,
+  0x002C,
+  0x002E,
+  0x002A,
+  0x002D,
+  0x0024,
+  0x001B,
+  0x0030,
+  0x0032
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie ASPM Black List
+ *
+ *
+ *
+ * @param[in] LinkAspm            PCie ASPM black list
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieAspmBlackListFeature (
+  IN       PCIe_LINK_ASPM         *LinkAspm,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  UpstreamDeviceId;
+  UINT32  DownstreamDeviceId;
+  UINTN   i;
+  UINT32  DeviceId;
+  UINT32  VendorId;
+
+  GnbLibPciRead (LinkAspm->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader);
+  GnbLibPciRead (LinkAspm->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader);
+  LinkAspm->BlackList = FALSE;
+  for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    VendorId = AspmBrDeviceTable[i];
+    DeviceId = AspmBrDeviceTable[i + 1];
+    if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) {
+      if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) {
+        LinkAspm->UpstreamAspm &= AspmBrDeviceTable[i + 2];
+        LinkAspm->DownstreamAspm &= AspmBrDeviceTable[i + 2];
+        LinkAspm->BlackList = TRUE;
+      }
+    }
+  }
+  if ((UINT16)UpstreamDeviceId == 0x168c) {
+    // Atheros (Ignore dev capability enable L1 if requested)
+    LinkAspm->UpstreamAspm = LinkAspm->RequestedAspm & AspmL1;
+    LinkAspm->DownstreamAspm = LinkAspm->UpstreamAspm;
+    GnbLibPciRMW (LinkAspm->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader);
+
+    DeviceId = UpstreamDeviceId >> 16;
+    for (i = 0; i < (sizeof (Aspm168cL0sEnabled) / sizeof (UINT16)); i++) {
+      if (DeviceId == Aspm168cL0sEnabled[i]) {
+        LinkAspm->UpstreamAspm = LinkAspm->RequestedAspm & AspmL0sL1;
+        LinkAspm->DownstreamAspm = LinkAspm->UpstreamAspm & AspmL1;
+      }
+    }
+
+  }
+  if (UpstreamDeviceId == 0x10831969) {
+    GnbLibPciRMW (LinkAspm->UpstreamPort.AddressValue | 0x12F8, AccessS3SaveWidth32, 0xFFF7F7FF, 0, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
new file mode 100644
index 0000000000..3ae175da73
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
@@ -0,0 +1,55 @@
+/**
+ * @file
+ *
+ * PCIe ASPM Black List
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPMBLACKLIST_H_
+#define _PCIEASPMBLACKLIST_H_
+
+///PCIe ASPM Black List
+
+AGESA_STATUS
+PcieAspmBlackListFeature (
+  IN       PCIe_LINK_ASPM         *LinkAspm,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
new file mode 100644
index 0000000000..a6aff55594
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to calculate PCIe topology segment maximum exit latency
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPMEXITLATENCY_H_
+#define _PCIEASPMEXITLATENCY_H_
+
+VOID
+PcieAspmGetMaxExitLatency (
+  IN       PCI_ADDR                DownstreamPort,
+     OUT   PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
new file mode 100644
index 0000000000..9b8156b563
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
@@ -0,0 +1,73 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PHY initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEPHYSERVICES_H_
+#define _PCIEPHYSERVICES_H_
+
+VOID
+PciePhyApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyAvertClockPickers (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyChannelCharacteristic (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PciePhyForceDccRecalibration (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
new file mode 100644
index 0000000000..2c9d1ce304
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -0,0 +1,622 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersCommon.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PIF_GANG_0to1  0x1
+#define PIF_GANG_2to3  (0x1 << 1)
+#define PIF_GANG_4to5  (0x1 << 2)
+#define PIF_GANG_6to7  (0x1 << 3)
+#define PIF_GANG_0to3  (0x1 << 4)
+#define PIF_GANG_4to7  (0x1 << 8)
+#define PIF_GANG_0to7  (0x1 << 9)
+#define PIF_GANG_ALL   (0x1 << 25)
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply PIF ganging for all lanes for given wrapper
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG      *EngineList;
+  UINT32                  LaneBitmap;
+  UINT8                   Pif;
+  D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2];
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n");
+  LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie));
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, EngineList);
+      switch (LaneBitmap) {
+      case  0x0003:
+        D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1;
+        break;
+      case  0x000c:
+        D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1;
+        break;
+      case  0x0030:
+        D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1;
+        break;
+      case  0x00c0:
+        D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1;
+        break;
+      case  0x000f:
+        D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1;
+        break;
+      case  0x00f0:
+        D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1;
+        break;
+      case  0x00ff:
+        D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1;
+        break;
+      case  0x0300:
+        D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1;
+        break;
+      case  0x0c00:
+        D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1;
+        break;
+      case  0x3000:
+        D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1;
+        break;
+      case  0xc000:
+        D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1;
+        break;
+      case  0x0f00:
+        D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1;
+        break;
+      case  0xf000:
+        D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1;
+        break;
+      case  0xff00:
+        D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1;
+        break;
+      case  0xffff:
+        D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1;
+        D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1;
+        break;
+      default:
+        break;
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS),
+        D0F0xE4_PIF_0011[Pif].Value,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL powerdown
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllPowerDown (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT16                  NibbleBitmap;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n");
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    NibbleBitmap = (0xF << (Nibble * 4));
+    if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL init for DDI
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllInitForDdi (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT32                  LaneBitmap;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n");
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (LaneBitmap & (0xF << (Nibble * 4))) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for on PIF to indicate action completion
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollPifForCompeletion (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Pif;
+  UINT32                  Value;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    do {
+      Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, Pif, 0x15),
+                                 Pcie
+                                 );
+    } while ((Value & 0xff) != 0xff);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable fifo reset
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifDisableFifoReset (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET,
+      D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program LS2 exit time
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetLs2ExitTime (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET,
+        D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH,
+        0x0,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PLL mode for L1
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifSetPllModeForL1 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (LaneBitmap & (0xF << (Nibble * 4))) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program receiver detection power mode
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetRxDetectPowerMode (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET,
+        D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH,
+        0x1,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pll ramp up time
+ *
+ *
+ *
+ * @param[in]  Rampup              Ramp up time
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifSetPllRampTime (
+  IN      PCIE_PLL_RAMPUP_TIME  Rampup,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Pif;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
+  D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0013.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0010.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+                               Pcie
+                               );
+    if (Rampup == NormalRampup) {
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
+      D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1;
+      D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0;
+    } else {
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3;
+      D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3;
+      D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010.Value,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down PIFs
+ *
+ *
+ *
+ * @param[in]  Control             Power up or Power down control
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifPllPowerControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8   Pif;
+  UINT8   PllPowerStateInOff;
+  PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET,
+      D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH,
+      PllPowerStateInOff,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET,
+      D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH,
+      PllPowerStateInOff,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down PIFs
+ *
+ *
+ *
+ * @param[in]  Control             Power up/Down control
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifFullPowerStateControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8                   Pif;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0013.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+                               Pcie
+                               );
+    if (Control == PowerDownPifs) {
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+    } else {
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013.Value,
+      FALSE,
+      Pcie
+      );
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
new file mode 100644
index 0000000000..50dca90570
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEPIFSERVICES_H_
+#define _PCIEPIFSERVICES_H_
+
+VOID
+PciePifApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerDown (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllInitForDdi (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollPifForCompeletion (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifDisableFifoReset (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetLs2ExitTime (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetPllModeForL1 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetRxDetectPowerMode (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetPllRampTime (
+  IN      PCIE_PLL_RAMPUP_TIME  Rampup,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PciePifFullPowerStateControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
new file mode 100644
index 0000000000..3fc8561c02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -0,0 +1,273 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe port indirect register
+ * space.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe port indirect register.
+ *
+ * Support for unify register access through index/data pair on PCIe port
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Register Value
+ */
+
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  Value       New register value
+ * @param[in]  S3Save      Save for S3 flag
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ */
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ASSERT (S3Save == TRUE || S3Save == FALSE);
+
+  IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, "    *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n",
+    Engine->Type.Port.Address.Address.Bus,
+    Engine->Type.Port.Address.Address.Device,
+    Engine->Type.Port.Address.Address.Function,
+    Address,
+    Value
+    );
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  S3Save      Save for S3 flag
+ * @param[in]  Value       New register value
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ */
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Data;
+  UINT32  Mask;
+  Data = PciePortRegisterRead (Engine, Address, Pcie);
+  Mask = (1 << FieldWidth) - 1;
+  Value &= Mask;
+  Data &= (~(Mask << FieldOffset));
+  PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Register Field Value.
+ */
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PciePortRegisterRead (Engine, Address, Pcie);
+  Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1);
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe port register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PciePortRegisterRead (Engine, Address, Pcie);
+  Value = (Value & (~AndMask)) | OrMask;
+  PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
new file mode 100644
index 0000000000..a6195485e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe port indirect register space.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTREGACC_H_
+#define _PCIEPORTREGACC_H_
+
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
new file mode 100644
index 0000000000..c6688ebe96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -0,0 +1,396 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersCommon.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8 L1State = 0x1b;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set completion timeout
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | 0x80,
+    AccessWidth32,
+    0xffffffff,
+    0x6 << 0,
+    GnbLibGetHeader (Pcie)
+    );
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    PciePortRegisterWriteField (
+      Engine,
+      0x20,
+      15,
+      1,
+      0x0,
+      TRUE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init hotplug port
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 Value;
+  if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
+    Value = PciePortRegisterRead (Engine, 0xb5, Pcie);
+    Value |= 3 << 12;
+    Value |= 3 << 14;
+    Value |= 1 << 10;
+    PciePortRegisterWrite (
+      Engine,
+      0xb5,
+      Value,
+      TRUE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
+      D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
+      D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
+      0x5,
+      TRUE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
+      D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET,
+      D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH,
+      0x1,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | 0x6c,
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << 6,
+      GnbLibGetHeader (Pcie)
+      );
+    PciePortRegisterWriteField (
+      Engine,
+      0x20,
+      15,
+      1,
+      0x0,
+      TRUE,
+      Pcie
+      );
+    PciePortRegisterWriteField (
+      Engine,
+      0x70,
+      19,
+      1,
+      0x1,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set misc slot capability
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | 0x58,
+    AccessWidth32,
+    0xffffffff,
+    1 << 24,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | 0x3c,
+    AccessWidth32,
+    0xffffffff,
+    1 << 8,
+    GnbLibGetHeader (Pcie)
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Safe mode to force link advertize Gen1 only capability in TS
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieFmSetLinkSpeedCap (PcieGen1, Engine, Pcie);
+  PciePortRegisterRMW (
+    Engine,
+    0xa2,
+    0x2000,
+    (1 << 13),
+    FALSE,
+    Pcie
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterRMW (
+    Engine,
+    0xa2,
+    0x2000,
+    0,
+    FALSE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Force compliance
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) {
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | 0x88,
+      AccessWidth32,
+      0xffffffff,
+      0x1 << 4,
+      GnbLibGetHeader (Pcie)
+      );
+  } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) {
+    PciePortRegisterWriteField (
+      Engine,
+      0xc0,
+      13,
+      1,
+      0x1,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable ASPM on SB link
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) {
+    if (PcieConfigIsSbPcieEngine (Engine)) {
+      SbPcieLinkAspmControl (Engine, Pcie);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for link to get into L1
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkHwStateHistory[8];
+  do {
+    PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie);
+  } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for link to get into L0
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkHwStateHistory[4];
+  do {
+    PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie);
+  } while (LinkHwStateHistory[0] != 0x10);
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
new file mode 100644
index 0000000000..67c66bb6fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTSERVICES_H_
+#define _PCIEPORTSERVICES_H_
+
+
+VOID
+PcieSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieEnableSlotPowerLimit (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
new file mode 100644
index 0000000000..0eeee7979a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERSAVINGFEATURES_H_
+#define _PCIEPOWERSAVINGFEATURES_H_
+
+
+VOID
+PciePwrPowerDownUnusedLanes (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieLanesToPowerDownPllInL1 (
+  IN       UINT8                  PllPowerUpLatency,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PciePwrAutoPowerDownElectricalIdleDetector (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePwrClockGating (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
new file mode 100644
index 0000000000..66e59f41ea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
@@ -0,0 +1,72 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Complex Services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIESILICONSERVICES_H_
+#define _PCIESILICONSERVICES_H_
+
+UINT8
+PcieSiliconGetGen1VoltageIndex (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+PcieSiliconRequestVoltage (
+  IN      UINT8                 VidIndex,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+PcieSiliconUnHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
new file mode 100644
index 0000000000..2a7a0db50c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -0,0 +1,95 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe timer access procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 86079 $   @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbTimerLib.h"
+#include  "GnbRegistersCommon.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCIe timer timestamp
+ *
+ *
+ *
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Time stamp value
+ */
+
+UINT32
+PcieTimerGetTimeStamp (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  return GnbFmTimeStamp (GnbLibGetHeader (Pcie));
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
new file mode 100644
index 0000000000..c68d214602
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
@@ -0,0 +1,55 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe timer access procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETIMER_H_
+#define _PCIETIMER_H_
+
+UINT32
+PcieTimerGetTimeStamp (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2))
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
new file mode 100644
index 0000000000..5151fb445d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -0,0 +1,722 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersCommon.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Cleanup reconfig
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyCleanUpReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062_ConfigXferMode_MASK,
+      1 << D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare for reconfiguration
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyPrepareForReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  UINT8                     CoreId;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
+        D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
+        D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
+        0xf,
+        FALSE,
+        Pcie
+        );
+    }
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                 Pcie
+                                 );
+
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
+    D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate mux array index
+ *
+ *
+ *
+ * @param[in, out]  LaneMuxSelectorArrayPtr     Pointer to mux selector array
+ * @param[in]       LaneMuxValue                The value that match to array
+ * @retval          Index                       Index successfully mapped
+ */
+STATIC UINT8
+PcieTopologyLocateMuxIndex (
+  IN OUT   UINT8 *LaneMuxSelectorArrayPtr,
+  IN       UINT8  LaneMuxValue
+  )
+{
+  UINT8  Index;
+  for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) {
+    if (LaneMuxSelectorArrayPtr [Index] ==  LaneMuxValue) {
+      return Index;
+    }
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply lane mux
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieTopologyApplyLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT8               CurrentPhyLane;
+  UINT8               CurrentCoreLane;
+  UINT8               CoreLaneIndex;
+  UINT8               PhyLaneIndex;
+  UINT8               NumberOfPhyLane;
+  UINT8               TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
+  UINT8               RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
+  UINT8               Index;
+  UINT32              TxMaxSelectorValue;
+  UINT32              RxMaxSelectorValue;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n");
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    EngineList = PcieConfigGetChildEngine (Wrapper);
+    LibAmdMemCopy (
+      &TxLaneMuxSelectorArray[0],
+      &LaneMuxSelectorTable[0],
+      sizeof (LaneMuxSelectorTable),
+      GnbLibGetHeader (Pcie)
+      );
+    LibAmdMemCopy (
+      &RxLaneMuxSelectorArray[0],
+      &LaneMuxSelectorTable[0],
+      sizeof (LaneMuxSelectorTable),
+      GnbLibGetHeader (Pcie)
+      );
+    while (EngineList != NULL) {
+      if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
+        CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
+        NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
+        CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
+        if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
+          CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane;
+        }
+        for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) {
+          CoreLaneIndex = (CurrentCoreLane + Index) / 2;
+          PhyLaneIndex = (CurrentPhyLane + Index) / 2;
+
+          if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) {
+            RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex];
+            RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex;
+          }
+          if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) {
+            TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] =  TxLaneMuxSelectorArray [PhyLaneIndex];
+            TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex;
+          }
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    RxMaxSelectorValue = 0;
+    TxMaxSelectorValue = 0;
+    for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) {
+      RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4));
+      TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4));
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS),
+      TxMaxSelectorValue,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS),
+      RxMaxSelectorValue,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Select master PLL
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[out] ConfigChanged       Pointer to boolean indicator that configuration was changed
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieTopologySelectMasterPll (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  UINT16                    MasterLane;
+  UINT16                    MasterHotplugLane;
+  D0F0xE4_WRAP_8013_STRUCT  D0F0xE4_WRAP_8013;
+  D0F0xE4_WRAP_8013_STRUCT  D0F0xE4_WRAP_8013_BASE;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
+  MasterLane = 0xFFFF;
+  MasterHotplugLane = 0xFFFF;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) {
+      if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+        MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList);
+      } else {
+        MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList);
+        if (PcieConfigIsSbPcieEngine (EngineList)) {
+          break;
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+
+  if (MasterLane == 0xffff) {
+    if (MasterHotplugLane != 0xffff) {
+      MasterLane = MasterHotplugLane;
+    } else {
+      MasterLane = 0x0;
+    }
+  }
+
+  D0F0xE4_WRAP_8013.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value;
+  if ( MasterLane <= 3 ) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xA;
+  } else if (MasterLane <= 7) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xB;
+  } else if (MasterLane <= 11) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xC;
+  } else {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1;
+    Wrapper->MasterPll = 0xD;
+  }
+  if (ConfigChanged != NULL) {
+    *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
+    D0F0xE4_WRAP_8013.Value,
+    FALSE,
+    Pcie
+    );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute/clean up reconfiguration
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyExecuteReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  D0F0xE4_WRAP_8060_STRUCT  D0F0xE4_WRAP_8060;
+
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n");
+
+    PcieTopologyServices136_fun (FALSE, Wrapper, Pcie);
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+                                Pcie
+                                );
+
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+      D0F0xE4_WRAP_8060.Value,
+      FALSE,
+      Pcie
+      );
+    do {
+      D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
+                                  Wrapper,
+                                  WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+                                  Pcie
+                                  );
+
+    } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1);
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    PcieTopologyServices136_fun (TRUE, Wrapper, Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable lane reversal
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologySetLinkReversal (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n");
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (PcieLibIsPcieEngine (EngineList)) {
+        if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) {
+            PciePortRegisterWriteField (
+              EngineList,
+              0xc1,
+              4,
+              1,
+              0x1,
+              FALSE,
+              Pcie
+              );
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Reduce link width
+ *
+ *
+ * @param[in]  LinkWidth           Link width
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyReduceLinkWidth (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG       *Wrapper;
+  UINT32                    LinkReversed;
+  UINT8                     DeltaLinkWidthBitmap;
+  UINT32                    LanesToDisable;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
+
+  DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
+  LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane +  LinkWidth)));
+
+  PcieTopologyLaneControl (
+    DisableLanes,
+    LanesToDisable,
+    Wrapper,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lanes enable/disable control
+ *
+ * @param[in]   Control             Lane control action
+ * @param[in]   LaneBitMap          Core lanes bitmap
+ * @param[in]   Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyLaneControl (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+    )
+{
+  D0F0xE4_WRAP_8023_STRUCT  D0F0xE4_WRAP_8023;
+  D0F0xE4_WRAP_8023.Value = PcieRegisterRead (
+                            Wrapper,
+                            WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
+                            Pcie
+                            );
+
+  if (Control == EnableLanes) {
+    D0F0xE4_WRAP_8023.Value |= LaneBitMap;
+  } else if (Control == DisableLanes) {
+    D0F0xE4_WRAP_8023.Value &= (~LaneBitMap);
+  }
+  D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1);
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
+    D0F0xE4_WRAP_8023.Value,
+    TRUE,
+    Pcie
+    );
+}
+
+VOID
+PcieTopologyServices136_fun (
+  IN      BOOLEAN               fv0,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GNBREGCOMMON_STR1_STRUCT  GNBREGCOMMON_STR1;
+  GNBREGCOMMON_STR1.Value = PcieRegisterRead (
+                               Wrapper,
+                               WRAP_SPACE (Wrapper->WrapId, 0x8063),
+                               Pcie
+                               );
+  if (fv0) {
+    GNBREGCOMMON_STR1.Field.bit4 = 0x1;
+    GNBREGCOMMON_STR1.Field.bit5 = 0x1;
+    GNBREGCOMMON_STR1.Field.bit12 = 0x1;
+    GNBREGCOMMON_STR1.Field.bit13 = 0x1;
+    GNBREGCOMMON_STR1.Field.bit14 = 0x1;
+  } else {
+    GNBREGCOMMON_STR1.Field.bit4 = 0x0;
+    GNBREGCOMMON_STR1.Field.bit5 = 0x0;
+    GNBREGCOMMON_STR1.Field.bit12 = 0x0;
+    GNBREGCOMMON_STR1.Field.bit13 = 0x0;
+    GNBREGCOMMON_STR1.Field.bit14 = 0x0;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, 0x8063),
+    GNBREGCOMMON_STR1.Value,
+    FALSE,
+    Pcie
+    );
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set core configuration according to PCIe port topology
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[out] ConfigChanged       Pointer to boolean indicator that configuration was changed
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+PcieTopologySetCoreConfig (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                     CoreId;
+  AGESA_STATUS              Status;
+  D0F0xE4_WRAP_0080_STRUCT  D0F0xE4_WRAP_0080;
+
+  Status = AGESA_SUCCESS;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      UINT64  ConfigurationSignature;
+      UINT8   NewConfigurationValue;
+      ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
+      Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
+      if (Status == AGESA_SUCCESS) {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
+          PcieFmDebugGetWrapperNameString (Wrapper),
+          CoreId,
+          PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
+          );
+        D0F0xE4_WRAP_0080.Value = PcieRegisterRead (
+                                    Wrapper,
+                                    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
+                                    Pcie
+                                    );
+        if (ConfigChanged != NULL) {
+          if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) {
+            *ConfigChanged = TRUE;
+          }
+        }
+        D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue;
+        PcieRegisterWrite (
+          Wrapper,
+          WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
+          D0F0xE4_WRAP_0080.Value,
+          FALSE,
+          Pcie
+          );
+      } else {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
+          PcieFmDebugGetWrapperNameString (Wrapper),
+          ((UINT32*)&ConfigurationSignature)[1],
+          ((UINT32*)&ConfigurationSignature)[0]
+          );
+        PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+      }
+    }
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set TX control for PCIe lanes
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieWrapSetTxS1CtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8025_STRUCT  D0F0xE4_WRAP_8025;
+  UINT32                    LaneBitmap;
+  UINTN                     Index;
+  D0F0xE4_WRAP_8025.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+                              Pcie
+                              );
+  Index = 0;
+  LaneBitmap =  PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
+  while (LaneBitmap != 0) {
+    if ((LaneBitmap & 0xf) != 0) {
+      D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8)));
+      D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8));
+    }
+    LaneBitmap >>= 4;
+    ++Index;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+    D0F0xE4_WRAP_8025.Value,
+    FALSE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set TX control for lane muxes
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieWrapSetTxOffCtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+    0x1f1f1f1f,
+    FALSE,
+    Pcie
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
new file mode 100644
index 0000000000..00ffd58d9f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -0,0 +1,135 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETOPOLOGYSERVICES_H_
+#define _PCIETOPOLOGYSERVICES_H_
+
+VOID
+PcieTopologyCleanUpReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyPrepareForReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PcieTopologySetCoreConfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT  BOOLEAN               *ConfigChanged,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyApplyLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+ );
+
+VOID
+PcieTopologySelectMasterPll (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyExecuteReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologySetLinkReversal (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+
+VOID
+PcieTopologyReduceLinkWidth (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyLaneControl (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyServices136_fun (
+  IN      BOOLEAN               fv0,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetDdiOwnPhy (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieWrapSetTxS1CtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieWrapSetTxOffCtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
new file mode 100644
index 0000000000..6af26def32
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -0,0 +1,661 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe utility. Various supporting functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersCommon.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/// Lane type
+typedef enum {
+  LaneTypeCore,         ///< Core Lane
+  LaneTypePhy,          ///< Package Phy Lane
+  LaneTypeNativePhy     ///< Native Phy Lane
+} LANE_TYPE;
+
+/// Lane Property
+typedef enum {
+  LanePropertyConfig,   ///< Configuration
+  LanePropertyActive,   ///< Active
+  LanePropertyAllocated ///< Allocated
+} LANE_PROPERTY;
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct {
+  UINT32               Flags;
+  PCIE_LINK_SPEED_CAP  LinkSpeedCapability;
+} PCIE_GLOBAL_GEN_CAP_WORKSPACE;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link state history from HW state machine
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @param[out]  History             Buffer to save history
+ * @param[in]   Length              Buffer length
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieUtilGetLinkHwStateHistory (
+  IN       PCIe_ENGINE_CONFIG        *Engine,
+     OUT   UINT8                     *History,
+  IN       UINT8                     Length,
+  IN       PCIe_PLATFORM_CONFIG      *Pcie
+  )
+{
+  UINT8   ReadLength;
+  UINT32  LocalHistory [6];
+  UINT16  Index;
+  ASSERT (Length <= 16);
+  ASSERT (Length > 0);
+  if (Length > 6*4) {
+    Length = 6*4;
+  }
+  ReadLength = (Length + 3) / 4;
+  for (Index = 0; Index < ReadLength; Index++) {
+    LocalHistory[Index] = PciePortRegisterRead (
+                            Engine,
+                            0xa5 + Index,
+                            Pcie
+                            );
+  }
+  LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Search array for specific pattern
+ *
+ *
+ * @param[in]  Buf1           Pointer to source buffer which will be subject of search
+ * @param[in]  Buf1Length     Length of the source buffer
+ * @param[in]  Buf2           Pointer to pattern buffer
+ * @param[in]  Buf2Length     Length of the pattern buffer
+ * @retval     TRUE           Pattern found
+ * @retval     TRUE           Pattern not found
+ */
+
+BOOLEAN
+PcieUtilSearchArray (
+  IN      UINT8                         *Buf1,
+  IN      UINTN                         Buf1Length,
+  IN      UINT8                         *Buf2,
+  IN      UINTN                         Buf2Length
+  )
+{
+  UINT8 *CurrentBuf1Ptr;
+  CurrentBuf1Ptr = Buf1;
+  while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
+    UINT8 *SourceBufPtr;
+    UINT8 *PatternBufPtr;
+    UINTN PatternBufLength;
+    SourceBufPtr = CurrentBuf1Ptr;
+    PatternBufPtr = Buf2;
+    PatternBufLength = Buf2Length;
+    while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
+    if (PatternBufLength == 0) {
+      return TRUE;
+    }
+    CurrentBuf1Ptr++;
+  }
+  return FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link reversed
+ *
+ *
+ * @param[in]  HwLinkState  Check for HW auto link reversal
+ * @param[in]  Engine       Pointer to engine config descriptor
+ * @param[in]  Pcie         Pointer to PCIe config descriptor
+ * @retval                 TRUE if link reversed
+ */
+BOOLEAN
+PcieUtilIsLinkReversed (
+  IN      BOOLEAN               HwLinkState,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 LinkReversal;
+
+  LinkReversal  = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0;
+  if (HwLinkState)  {
+    UINT32 Value;
+    Value = PciePortRegisterRead (
+                          Engine,
+                          0x50,
+                          Pcie
+                          );
+    LinkReversal ^= (Value & 1);
+  }
+  return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link width detected during training
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ * @retval                          Link width
+ */
+UINT8
+PcieUtilGetLinkWidth (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8               LinkWidth;
+  UINT32              Value;
+  Value = PciePortRegisterRead (
+                        Engine,
+                        0xA2,
+                        Pcie
+                        );
+  switch ((Value & 7) >> 4) {
+  case 0x6:
+    LinkWidth = 16;
+    break;
+  case 0x5:
+    LinkWidth = 12;
+    break;
+  case 0x4:
+    LinkWidth = 8;
+    break;
+  case 0x3:
+    LinkWidth = 4;
+    break;
+  case 0x2:
+    LinkWidth = 2;
+    break;
+  case 0x1:
+    LinkWidth = 1;
+    break;
+  default:
+    LinkWidth = 0;
+  }
+  return LinkWidth;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of PCIE engine lane of requested type
+ *
+ *
+ * @param[in]   LaneType            Lane type
+ * @param[in]   LaneProperty        Lane Property
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetPcieEngineLaneBitMap (
+  IN      LANE_TYPE                      LaneType,
+  IN      LANE_PROPERTY                  LaneProperty,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32                LaneBitmap;
+  UINT8                 Width;
+  UINT16                Offset;
+  UINT16                LoPhylane;
+  UINT16                HiPhylane;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+
+  Width = 0;
+  Offset = 0;
+  LaneBitmap = 0;
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+
+  if (PcieConfigIsPcieEngine (Engine)) {
+    if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) {
+      Width = PcieConfigGetNumberOfCoreLane (Engine);
+      Offset = Engine->Type.Port.StartCoreLane;
+      LaneBitmap = ((1 << Width) - 1) << Offset;
+    } else if (PcieConfigIsEngineAllocated (Engine)) {
+      if (LaneType == LaneTypeNativePhy) {
+        LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
+        LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
+      } else {
+        if (LaneType == LaneTypeCore) {
+          if (LaneProperty == LanePropertyActive) {
+            Width = PcieUtilGetLinkWidth (Engine, Pcie);
+            Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
+          } else if (LaneProperty == LanePropertyAllocated) {
+            Width = PcieConfigGetNumberOfPhyLane (Engine);
+            Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
+          }
+        }
+        if (LaneType == LaneTypePhy) {
+          LoPhylane = PcieLibGetLoPhyLane (Engine);
+          HiPhylane = PcieLibGetHiPhyLane (Engine);
+          if (LaneProperty == LanePropertyActive) {
+            Width = PcieUtilGetLinkWidth (Engine, Pcie);
+            Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+          } else if (LaneProperty == LanePropertyAllocated) {
+            Width = PcieConfigGetNumberOfPhyLane (Engine);
+            Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+          }
+        }
+        LaneBitmap = ((1 << Width) - 1) << Offset;
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of PCIE engine lane of requested type
+ *
+ *
+ * @param[in]   LaneType            Lane type
+ * @param[in]   LaneProperty        Lane Property
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetDdiEngineLaneBitMap (
+  IN      LANE_TYPE                      LaneType,
+  IN      LANE_PROPERTY                  LaneProperty,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitmap;
+  UINT8   Width;
+  UINT16  Offset;
+  Width = 0;
+  Offset = 0;
+  LaneBitmap = 0;
+  if (PcieConfigIsDdiEngine (Engine)) {
+    if (PcieConfigIsEngineAllocated (Engine)) {
+      if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) {
+        Width = PcieConfigGetNumberOfPhyLane (Engine);
+        Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+        LaneBitmap = ((1 << Width) - 1) << Offset;
+      }
+      if (LaneType == LaneTypeNativePhy) {
+        LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
+        LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get  bitmap of engine lane of requested type
+ *
+ *
+ * @param[in]   IncludeLaneType     Include Lane type
+ * @param[in]   ExcludeLaneType     Exclude Lane type
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+UINT32
+PcieUtilGetEngineLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitmap;
+  LaneBitmap = 0;
+  if (IncludeLaneType & LANE_TYPE_PCIE_LANES) {
+    if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) {
+      if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
+        LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+      } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+        } else {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine);
+        }
+      }
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_PHY) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) {
+      if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
+        LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+      } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+        } else {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
+        }
+      }
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+  }
+  if (IncludeLaneType & LANE_TYPE_DDI_LANES) {
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
+    }
+  }
+  if (ExcludeLaneType != 0) {
+    LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine));
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of phy lane confugred for master pll
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @retval     Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetMasterPllLaneBitMap (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  if (Wrapper->MasterPll != 0) {
+    return 0xf << (Wrapper->MasterPll - 0xA) * 4;
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of Wrapper lane of requested type
+ *
+ *
+ * @param[in]  IncludeLaneType Include Lane type
+ * @param[in]  ExcludeLaneType Exclude Lane type
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @retval     Lane bitmap
+ */
+
+UINT32
+PcieUtilGetWrapperLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  UINT32                    LaneBitmap;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  LaneBitmap = 0;
+  if ((IncludeLaneType | ExcludeLaneType) != 0) {
+    if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) {
+      LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1;
+      if (ExcludeLaneType != 0) {
+        LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper));
+      }
+    } else {
+      while (EngineList != NULL) {
+        LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList);
+        EngineList = PcieLibGetNextDescriptor (EngineList);
+      }
+      if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
+        LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper);
+      }
+      if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
+        LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper));
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program port register table
+ *
+ *
+ *
+ * @param[in]  Table           Pointer to table
+ * @param[in]  Length          number of entries
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  S3Save          Save for S3 flag
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PciePortProgramRegisterTable (
+  IN      PCIE_PORT_REGISTER_ENTRY    *Table,
+  IN      UINTN                       Length,
+  IN      PCIe_ENGINE_CONFIG          *Engine,
+  IN      BOOLEAN                     S3Save,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  UINTN   Index;
+  UINT32  Value;
+  for (Index = 0; Index < Length; Index++) {
+    Value = PciePortRegisterRead (
+              Engine,
+              Table[Index].Reg,
+              Pcie
+              );
+    Value &= (~Table[Index].Mask);
+    Value |= Table[Index].Data;
+    PciePortRegisterWrite (
+      Engine,
+      Table[Index].Reg,
+      Value,
+      S3Save,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lock registers
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PcieLockRegisters (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT8   CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
+        D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
+        D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
+        0x1,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training state handling
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Indicate if engine in non final state
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieUtilGlobalGenCapabilityCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability;
+  PCIE_LINK_SPEED_CAP           LinkSpeedCapability;
+  PCIE_HOTPLUG_TYPE             HotPlugType;
+  UINT32                        Flags;
+
+  Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS;
+  GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer;
+  LinkSpeedCapability = PcieGen1;
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS;
+  }
+  HotPlugType = Engine->Type.Port.PortData.LinkHotplug;
+  if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) {
+    Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS;
+  }
+  if ((GlobalGenCapability->Flags & Flags) != 0) {
+    ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0);
+    LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine);
+    if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) {
+      GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine global GEN capability
+ *
+ *
+ * @param[in]  Flags           global GEN capability flags
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+PCIE_LINK_SPEED_CAP
+PcieUtilGlobalGenCapability (
+  IN      UINT32                         Flags,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP             GlobalCapability;
+  PCIE_GLOBAL_GEN_CAP_WORKSPACE   GlobalGenCap;
+
+  GlobalGenCap.LinkSpeedCapability = PcieGen1;
+  GlobalGenCap.Flags = Flags;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieUtilGlobalGenCapabilityCallback,
+    &GlobalGenCap,
+    Pcie
+    );
+
+  GlobalCapability = GlobalGenCap.LinkSpeedCapability;
+
+  return GlobalCapability;
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
new file mode 100644
index 0000000000..09f090329b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
@@ -0,0 +1,131 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe utility. Various supporting functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEUTILLIB_H_
+#define _PCIEUTILLIB_H_
+
+/// Core lanes
+typedef enum {
+  AllCoreLanes,           ///< All core lanes
+  AllocatedCoreLanes,     ///< Allocated core lanes
+  ActiveCoreLanes,        ///< Active core lanes
+  HotplugCoreLanes,       ///< Hot plug core lanes
+  SbCoreLanes,            ///< South bridge core lanes
+} CORE_LANES;
+
+/// DDI lanes
+typedef enum {
+  DdiAllLanes,            ///< All DDI Lanes
+  DdiActiveLanes          ///< Active DDI Lanes
+} DDI_LANES;
+
+BOOLEAN
+PcieUtilSearchArray (
+  IN      UINT8                         *Buf1,
+  IN      UINTN                         Buf1Length,
+  IN      UINT8                         *Buf2,
+  IN      UINTN                         Buf2Length
+  );
+
+VOID
+PcieUtilGetLinkHwStateHistory (
+  IN       PCIe_ENGINE_CONFIG            *Engine,
+     OUT   UINT8                         *History,
+  IN       UINT8                         Length,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+
+BOOLEAN
+PcieUtilIsLinkReversed (
+  IN      BOOLEAN                        HwLinkState,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+
+UINT8
+PcieUtilGetLinkWidth (
+  IN      PCIe_ENGINE_CONFIG            *Engine,
+  IN      PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+
+UINT32
+PcieUtilGetEngineLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+UINT32
+PcieUtilGetWrapperLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  );
+
+VOID
+PciePortProgramRegisterTable (
+  IN      PCIE_PORT_REGISTER_ENTRY       *Table,
+  IN      UINTN                          Length,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      BOOLEAN                        S3Save,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+VOID
+PcieLockRegisters (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+PCIE_LINK_SPEED_CAP
+PcieUtilGlobalGenCapability (
+  IN      UINT32                         Flags,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
new file mode 100644
index 0000000000..eed1d2fb77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -0,0 +1,300 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register Value
+ */
+UINT32
+PcieRegisterRead (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Silicon     Pointer to silicon descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register Value
+ */
+
+UINT32
+PcieSiliconRegisterRead (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32              Value;
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]   Wrapper     Pointer to wrapper descriptor
+ * @param[in]   Address     Register address
+ * @param[in]   Value       New register value
+ * @param[in]   S3Save      Save register for S3 (True/False)
+ * @param[in]   Pcie        Pointer to global PCIe configuration
+ */
+VOID
+PcieRegisterWrite (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  PcieSiliconRegisterWrite (
+     PcieConfigGetParentSilicon (Wrapper),
+     Address,
+     Value,
+     S3Save,
+     Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]   Silicon     Pointer to silicon descriptor
+ * @param[in]   Address     Register address
+ * @param[in]   Value       New register value
+ * @param[in]   S3Save      Save register for S3 (True/False)
+ * @param[in]   Pcie        Pointer to global PCIe configuration
+ */
+VOID
+PcieSiliconRegisterWrite (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, "    *WR %s (%d:%d:%d):0x%08x = 0x%08x\n",
+    PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)),
+    Silicon->Address.Address.Bus,
+    Silicon->Address.Address.Device,
+    Silicon->Address.Address.Function,
+    Address,
+    Value
+    );
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register field value
+ */
+
+UINT32
+PcieRegisterReadField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PcieRegisterRead (Wrapper, Address, Pcie);
+  Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth));
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Value       Value to write
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+
+VOID
+PcieRegisterWriteField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  TempValue;
+  UINT32  Mask;
+  TempValue = PcieRegisterRead (Wrapper, Address, Pcie);
+  Mask = (~(0xFFFFFFFF << FieldWidth));
+  Value &= Mask;
+  TempValue &= (~(Mask << FieldOffset));
+  PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PcieRegisterRMW (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  PcieSiliconRegisterRMW (
+    PcieConfigGetParentSilicon (Wrapper),
+    Address,
+    AndMask,
+    OrMask,
+    S3Save,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Silicon     Pointer to silicon descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PcieSiliconRegisterRMW (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PcieSiliconRegisterRead (Silicon, Address, Pcie);
+  Value = (Value & (~AndMask)) | OrMask;
+  PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
new file mode 100644
index 0000000000..9a7e9013ef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
@@ -0,0 +1,127 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEWRAPPERREGACC_H_
+#define _PCIEWRAPPERREGACC_H_
+
+//#define WRAP_SPACE(w, x)   (0x01300000ul | (w << 16) | (x))
+//#define CORE_SPACE(c, x)   (0x00010000ul | (c << 24) | (x))
+//#define PHY_SPACE(w, p, x) (0x00200000ul | ((p + 1) << 24) | (w << 16) | (x))
+//#define PIF_SPACE(w, p, x) (0x00100000ul | ((p + 1) << 24) | (w << 16) | (x))
+#define IMP_SPACE(x) (0x01080000ul | (x))
+
+UINT32
+PcieRegisterRead (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterWrite (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieRegisterReadField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterWriteField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterRMW (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieSiliconRegisterRead (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconRegisterWrite (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconRegisterRMW (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif