diff options
| author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2013-07-25 15:14:15 +0800 |
|---|---|---|
| committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-08-04 05:40:37 +0200 |
| commit | affe85fbc8a13d35960aa92ae87cbb6330ad253f (patch) | |
| tree | 9c1ace69f12b06b6544faf041994aa4288fb2e45 /src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB | |
| parent | ae8d06969bdde9b1250bc3c4ad93f5db408dae98 (diff) | |
AMD Kabini: Add AGESA/PI code for new processor family
Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Nick Dill <nick.dill@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB')
39 files changed, 48716 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c new file mode 100644 index 0000000000..30ec1b368a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibKB.c @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "AlibSsdtKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_ALIBKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID * +PcieAlibGetBaseTableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Get base SSDT table + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval pointer to SSTD table + */ +VOID * +PcieAlibGetBaseTableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return &AlibSsdtKB[0]; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h new file mode 100644 index 0000000000..eb3c21f80d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h @@ -0,0 +1,3230 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87932 $ @e \$Date: 2013-02-13 13:53:55 -0600 (Wed, 13 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _ALIBSSDTKB_H_ +#define _ALIBSSDTKB_H_ + +UINT8 AlibSsdtKB[] = { + 0x53, 0x53, 0x44, 0x54, 0x52, 0x63, 0x00, 0x00, + 0x02, 0x82, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x8D, 0x32, 0x06, + 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x47, + 0x52, 0x42, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x08, + 0x41, 0x44, 0x42, 0x47, 0x11, 0x04, 0x0B, 0x00, + 0x01, 0x08, 0x41, 0x44, 0x41, 0x54, 0x11, 0x45, + 0x20, 0x0B, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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"File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86586 $ @e \$Date: 2013-01-23 12:45:26 -0600 (Wed, 23 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxConfig.h" +#include "GnbGfxFamServices.h" +#include "GfxLibKB.h" +#include "GfxLibV3.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbHandleLib.h" +#include "cpuFamilyTranslation.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXENVINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GfxEnvInitTableKB[]; +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GfxEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GFX straps. + * + * + * @param[in] Gfx Pointer to global GFX configuration + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxStrapsEnvInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D0F0xD4_x010914E1_STRUCT D0F0xD4_x10914E1; + D0F0xD4_x010914E2_STRUCT D0F0xD4_x10914E2; + D0F0xD4_x01091507_STRUCT D0F0xD4_x1091507; + D0F0x64_x1D_STRUCT D0F0x64_x1D; + UINT32 D0F0xD4_x010914C3; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEnvInitKB Enter\n"); + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + + GnbRegisterReadKB (GnbHandle, D0F0xD4_x010914E1_TYPE, D0F0xD4_x010914E1_ADDRESS, &D0F0xD4_x10914E1.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, D0F0xD4_x010914E2_TYPE, D0F0xD4_x010914E2_ADDRESS, &D0F0xD4_x10914E2.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, D0F0xD4_x01091507_TYPE, D0F0xD4_x01091507_ADDRESS, &D0F0xD4_x1091507.Value, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, D0F0xD4_x010914C3_TYPE, D0F0xD4_x010914C3_ADDRESS, &D0F0xD4_x010914C3, 0, GnbLibGetHeader (Gfx)); + + GnbLibPciIndirectRead ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0x64_x1D.Field.VgaEn = 0x1; + + D0F0xD4_x10914E2.Field.bita = 0x0; + D0F0xD4_x10914E2.Field.bita = 0x0; + D0F0xD4_x1091507.Field.bit16 = Gfx->GnbHdAudio; + D0F0xD4_x10914E2.Field.bit13 = Gfx->GnbHdAudio; + + D0F0xD4_x10914E1.Field.StrapBifRegApSize = 0x2; + D0F0xD4_x10914E1.Field.StrapBifDoorbellBarDis = 0x0; + D0F0xD4_x10914E1.Field.Bitfield_13_13 = 0x0; + D0F0xD4_x10914E1.Field.Bitfield_15_14 = 0x3; + + if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) { + D0F0xD4_x10914E1.Field.StrapBifMemApSize = 0x1; + D0F0xD4_x1091507.Field.StrapBifMemApSizePin = 0x1; + } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) { + D0F0xD4_x10914E1.Field.StrapBifMemApSize = 0x0; + D0F0xD4_x1091507.Field.StrapBifMemApSizePin = 0x0; + } else { + D0F0xD4_x10914E1.Field.StrapBifMemApSize = 0x2; + D0F0xD4_x1091507.Field.StrapBifMemApSizePin = 0x2; + } + + GnbLibPciIndirectWrite ( + GNB_SBDFO | D0F0x60_ADDRESS, + D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + &D0F0x64_x1D.Value, + GnbLibGetHeader (Gfx) + ); + + D0F0xD4_x010914C3 |= BIT0; + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x010914E1_TYPE, D0F0xD4_x010914E1_ADDRESS, &D0F0xD4_x10914E1.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x010914E2_TYPE, D0F0xD4_x010914E2_ADDRESS, &D0F0xD4_x10914E2.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x01091507_TYPE, D0F0xD4_x01091507_ADDRESS, &D0F0xD4_x1091507.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, D0F0xD4_x010914C3_TYPE, D0F0xD4_x010914C3_ADDRESS, &D0F0xD4_x010914C3, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEnvInitKB Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Env Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + GNB_HANDLE *GnbHandle; + UINT32 Property; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Property = TABLE_PROPERTY_DEFAULT; + + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + // Power up iGPU + GfxRequestGPUPowerV3 (Gfx, 1); + Status = GfxStrapsEnvInitKB (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + } else { + GfxFmDisableController (StdHeader); + Property |= TABLE_PROPERTY_IGFX_DISABLED; + } + + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + Status = GnbProcessTable ( + GnbHandle, + GfxEnvInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceKB Exit [0x%x]\n", AgesaStatus); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c new file mode 100644 index 0000000000..234592bfb3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c @@ -0,0 +1,375 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87849 $ @e \$Date: 2013-02-11 15:37:58 -0600 (Mon, 11 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbRegisterAccKB.h" +#include "cpuFamilyTranslation.h" +#include "GnbRegistersKB.h" +#include "GfxLibKB.h" +#include "GfxGmcInitKB.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXGMCINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_TABLE ROMDATA GfxGmcFeature1DisableKB []; +extern GNB_TABLE ROMDATA GfxGmcInitTableKB []; +extern GNB_TABLE ROMDATA GfxGmcFeature1EnableKB []; + + +#define GNB_GFX_DRAM_CH_0_PRESENT 1 +#define GNB_GFX_DRAM_CH_1_PRESENT 2 + +#define DRAMTYPE_DDR3 1 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize Fb location + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeFbLocationKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 GMMx2024; + UINT32 GMMx2068; + UINT32 GMMx2C04; + UINT32 GMMx5428; + UINT64 FBBase; + UINT64 FBTop; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitializeFbLocationKB Enter\n"); + + FBBase = 0x0F00000000; + FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1; + GMMx2024 = 0; + GMMx2C04 = 0; + GMMx2024 |= (UINT16) (FBBase >> 24); + GMMx2024 |= (UINT32) ((FBTop >> 24) << 16); + GMMx2068 = (UINT32) (Gfx->UmaInfo.UmaBase >> 22); + GMMx2C04 = (UINT32) (FBBase >> 8); + GMMx5428 = Gfx->UmaInfo.UmaSize >> 20; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2024, &GMMx2024, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2068, &GMMx2068, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2C04, &GMMx2C04, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x5428, &GMMx5428, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitializeFbLocationKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize sequencer model + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeHubAndCitfSteeringKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 GMMx2004; + UINT32 GMMx2008; + + GMMx2004 = 0x2210; + GMMx2008 = 0; + + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2004, &GMMx2004, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2008, &GMMx2008, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Stutter Mode with/without power-gating + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcEnableStutterModePowerGatingKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 GMMx3508; + UINT32 GMMx350C; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcEnableStutterModePowerGatingKB Enter\n"); + + GnbRegisterReadKB (GnbHandle, 0x12, 0x3508, &GMMx3508, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, 0x12, 0x350C, &GMMx350C, 0, GnbLibGetHeader (Gfx)); + if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { + // Enabling power gating + if (Gfx->GmcPowerGating == GmcPowerGatingWithStutter) { + GMMx3508 |= 1; + GMMx350C |= 1 << 11; + GMMx350C &= ~(1 << 16); + } else { + GMMx3508 &= ~1; + GMMx350C &= ~(1 << 11); + GMMx350C |= 1 << 16; + } + GnbRegisterWriteKB (GnbHandle, 0x12, 0x3508, &GMMx3508, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x350C, &GMMx350C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } else { + // Disabling power gating + GMMx3508 &= ~1; + GMMx350C &= ~(1 << 11); + GMMx350C &= ~(1 << 16); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x3508, &GMMx3508, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x350C, &GMMx350C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcEnableStutterModePowerGatingKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + */ + +STATIC VOID +GfxGmcSecureGarlicAccessKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 v1; + UINT32 v2; + UINT32 v3; + + v1 = (UINT32) (Gfx->UmaInfo.UmaBase >> 20); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2868, &v1, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + v2 = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x286C, &v2, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + // Area FB - 32K reserved by VBIOS for SBIOS to use + v3 = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2878, &v3, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize C6 aperture location + * + * + * + * @param[in] GnbHandle Pointer to GNB_HANDLE + * @param[in] Gfx Pointer to global GFX configuration + * + */ +STATIC VOID +GfxGmcInitializeC6LocationKB ( + IN GNB_HANDLE *GnbHandle, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x118_STRUCT D18F2x118; + D18F1x44_STRUCT D18F1x44; + UINT32 GMMx2870; + UINT32 GMMx2874; + + // Check C6 enable, D18F2x118[CC6SaveEn] + GnbRegisterReadKB (GnbHandle, D18F2x118_TYPE, D18F2x118_ADDRESS, &D18F2x118.Value, 0, GnbLibGetHeader (Gfx)); + + if (D18F2x118.Field.CC6SaveEn) { + // From D18F1x[144:140,44:40] DRAM Base/Limit, + // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}. + GnbRegisterReadKB (GnbHandle, D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx)); + // + // base 39:20, base = Dram Limit + 1 + // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1) + // Node DRAM D18F1x[144:140,44:40] CC6DRAMRange D18F4x128 D18F1x120 D18F1x124 + // 0 256MB 0MB ~ 240 MB - 1 240 MB ~ 256 MB - 1 0 0 MB, 256 MB - 1 + // + + // base 39:20 + GMMx2870 = ((D18F1x44.Field.DramLimit_39_24 + 1) << 4); + // top 39:20 + GMMx2874 = (((D18F1x44.Field.DramLimit_39_24 + 1) << 24) + (16 * 0x100000) - 1) >> 20; + + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2870, &GMMx2870, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2874, &GMMx2874, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GMC + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ + +AGESA_STATUS +GfxGmcInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 v1; + UINT32 GMMx25E8; + D18F3x44_STRUCT D18F3x44; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitKB Enter\n"); +//2.1 Disable clock-gating + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GnbProcessTable ( + GnbHandle, + GfxGmcFeature1DisableKB, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); +//2.3 HUB & CITF channel steering + GfxGmcInitializeHubAndCitfSteeringKB (GnbHandle, Gfx); +//2.6 Frame buffer location + GfxGmcInitializeFbLocationKB (GnbHandle, Gfx); +//2.8 Securing GARLIC access +//2.8.1 GARLIC request disable + GfxGmcSecureGarlicAccessKB (GnbHandle, Gfx); +//2.8.2 C6 save aperture + GfxGmcInitializeC6LocationKB (GnbHandle, Gfx); +//2.2 System memory address translation +//2.4 Sequencer model programming +//2.5 Power Gating - PGFSM and RENG init +//2.7 Performance tuning +//2.10 Display latency +//2.11 Remove blackout + GnbProcessTable ( + GnbHandle, + GfxGmcInitTableKB, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); +//4. Power management + GnbProcessTable ( + GnbHandle, + GfxGmcFeature1EnableKB, + 0, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + GnbLibGetHeader (Gfx) + ); + +// SETUP or BLDCFG may override. + switch (Gfx->UmaSteering) { + case 0: + v1 = 0; + GnbRegisterReadKB (GnbHandle, D18F3x44_TYPE, D18F3x44_ADDRESS, &D18F3x44.Value, 0, GnbLibGetHeader (Gfx)); + if (D18F3x44.Field.DramEccEn == 1) { + v1 = SystemTrafficOnion; + } + break; + case SystemTrafficOnion: + v1 = SystemTrafficOnion; + break; + case Onion: + v1 = Onion; + break; + case 3: + v1 = 3; + break; + default: + v1 = 0; + ASSERT (FALSE); + break; + } + GnbRegisterWriteKB (GnbHandle, 0x12, 0x206C, &v1, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx)); + + GnbRegisterReadKB (GnbHandle, 0x12, 0x25E8, &GMMx25E8, 0, GnbLibGetHeader (Gfx)); + GMMx25E8 |= BIT14; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x25E8, &GMMx25E8, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) { + //4.2 Enabling stutter mode with or without power-gating + GfxGmcEnableStutterModePowerGatingKB (GnbHandle, Gfx); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitKB Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h new file mode 100644 index 0000000000..a6b63cafcf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXGMCINITKB_H_ +#define _GFXGMCINITKB_H_ + +#include "GnbRegistersKB.h" + +AGESA_STATUS +GfxGmcInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c new file mode 100644 index 0000000000..c81fd5ee3f --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c @@ -0,0 +1,526 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Integrated table info init + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87902 $ @e \$Date: 2013-02-12 15:59:48 -0600 (Tue, 12 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Gnb.h" +#include "GnbF1Table.h" +#include "GnbPcie.h" +#include "GnbGfx.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbGfxFamServices.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbNbInitLibV1.h" +#include "GfxConfigLib.h" +#include "GfxIntegratedInfoTable.h" +#include "GfxPwrPlayTable.h" +#include "GfxLibKB.h" +#include "GfxLibV3.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXINTEGRATEDINFOTABLEKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define GFX_REFCLK 100 // (in MHz) Reference clock is 100 MHz + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxMapEngineToDisplayPathKB ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ); + +AGESA_STATUS +GfxIntInfoTableInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +CONST UINT8 DdiLaneConfigArrayKB [][4] = { + {8, 11, 0, 0}, + {12, 15, 1, 1}, + {11, 8, 0, 0}, + {15, 12, 1, 1}, + {16, 19, 6, 6}, + {19, 16, 6, 6} +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize display path for given engine + * + * + * + * @param[in] Engine Engine configuration info + * @param[out] DisplayPathList Display path list + * @param[in] Gfx Pointer to global GFX configuration + */ + +AGESA_STATUS +GfxMapEngineToDisplayPathKB ( + IN PCIe_ENGINE_CONFIG *Engine, + OUT EXT_DISPLAY_PATH *DisplayPathList, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + UINT8 PrimaryDisplayPathId; + UINT8 SecondaryDisplayPathId; + UINTN DisplayPathIndex; + PrimaryDisplayPathId = 0xff; + SecondaryDisplayPathId = 0xff; + for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArrayKB) / 4); DisplayPathIndex++) { + if (DdiLaneConfigArrayKB[DisplayPathIndex][0] == Engine->EngineData.StartLane && + DdiLaneConfigArrayKB[DisplayPathIndex][1] == Engine->EngineData.EndLane) { + PrimaryDisplayPathId = DdiLaneConfigArrayKB[DisplayPathIndex][2]; + SecondaryDisplayPathId = DdiLaneConfigArrayKB[DisplayPathIndex][3]; + break; + } + } + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds && PrimaryDisplayPathId != 0)) { + // Display config invalid for KB + PrimaryDisplayPathId = 0xff; + } + + if (PrimaryDisplayPathId != 0xff) { + ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3); + IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId); + Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE; + GfxIntegratedCopyDisplayInfo ( + Engine, + &DisplayPathList[PrimaryDisplayPathId], + (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL, + Gfx + ); + + if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) { + LibAmdMemCopy (&DisplayPathList[6], &DisplayPathList[PrimaryDisplayPathId], sizeof (EXT_DISPLAY_PATH), GnbLibGetHeader (Gfx)); + DisplayPathList[6].usDeviceACPIEnum = 0x100; + DisplayPathList[6].usDeviceTag = ATOM_DEVICE_CRT1_SUPPORT; + } + + Status = AGESA_SUCCESS; + } else { + IDS_HDT_CONSOLE (GFX_MISC, " Error!!! Map DDI lanes %d - %d to display path failed\n", + Engine->EngineData.StartLane, + Engine->EngineData.EndLane + ); + PutEventLog ( + AGESA_ERROR, + GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION, + Engine->EngineData.StartLane, + Engine->EngineData.EndLane, + 0, + 0, + GnbLibGetHeader (Gfx) + ); + Status = AGESA_ERROR; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init KB Nb p-State MemclkFreq + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillNbPstateMemclkFreqKB ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F2x94_dct0_STRUCT D18F2x94; + D18F2x2E0_dct0_STRUCT D18F2x2E0; + D18F5x160_STRUCT NbPstate; + UINT8 i; + ULONG memps0_freq; + ULONG memps1_freq; + UINT8 last_valid_pstate; + GNB_HANDLE *GnbHandle; + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + + GnbRegisterReadKB ( + GnbHandle, + D18F2x94_dct0_TYPE, + D18F2x94_dct0_ADDRESS, + &D18F2x94.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + GnbRegisterReadKB ( + GnbHandle, + D18F2x2E0_dct0_TYPE, + D18F2x2E0_dct0_ADDRESS, + &D18F2x2E0.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + memps0_freq = 100 * GfxLibExtractDramFrequencyV3 ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx)); + memps1_freq = 100 * GfxLibExtractDramFrequencyV3 ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx)); + + last_valid_pstate = 0; + for (i = 0; i < 4; i++) { + NbPstate.Value = 0; + GnbRegisterReadKB ( + GnbHandle, + TYPE_D18F5, + (D18F5x160_ADDRESS + (i * 4)), + &NbPstate.Value, + 0, + GnbLibGetHeader (Gfx) + ); + if (NbPstate.Field.NbPstateEn == 1) { + last_valid_pstate = i; + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq; + } else { + IntegratedInfoTable->ulNbpStateMemclkFreq[i] = + IntegratedInfoTable->ulNbpStateMemclkFreq[last_valid_pstate]; + } + } + + for (i = 0; i < 4; i++) { + IDS_HDT_CONSOLE (GNB_TRACE, " Nclk[%d] = %08x\n", i, IntegratedInfoTable->ulNbpStateNClkFreq[i]); + IDS_HDT_CONSOLE (GNB_TRACE, " Mclk[%d] = %08x\n", i, IntegratedInfoTable->ulNbpStateMemclkFreq[i]); + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Calculate ulGMCRestoreResetTime + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + * @param[in] PpF1Array + * @retval AGESA_STATUS + */ +///@todo - this is currently based on TN +STATIC AGESA_STATUS +GfxCalculateRestoreResetTimeKB ( + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx, + IN PP_F1_ARRAY_V2 *PpF1Array + ) +{ + UINT8 MaxDid; + ULONG FreqSclk; + UINTN Index; + UINT32 TSclk; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeKB Enter\n"); + MaxDid = PpF1Array->PP_FUSE_ARRAY_V2_fld3; + for (Index = 0; Index < 4; Index++) { + MaxDid = MAX (MaxDid, PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index]); + } + IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid); + FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx)); + // FreqSclk is in 10KHz units - need calculations in nS + // For accuracy, do calculations in .01nS, then convert at the end + TSclk = (100 * (1000000000 / 10000)) / FreqSclk; + + IntegratedInfoTable->ulGMCRestoreResetTime = ((TSclk * 662) + 99) / 100; + IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeKB Exit\n"); + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init KB HTC Data + * + * + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxFillHtcDataKB ( + IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + D18F3x64_STRUCT D18F3x64; + GNB_HANDLE *GnbHandle; + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + + GnbRegisterReadKB ( + GnbHandle, + D18F3x64_TYPE, + D18F3x64_ADDRESS, + &D18F3x64.Value, + 0, + GnbLibGetHeader (Gfx) + ); + + if (D18F3x64.Field.HtcEn == 1) { + IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52); + IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2); + } else { + IntegratedInfoTable->ucHtcTmpLmt = 0; + IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = 0; + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + *Init Sclk <-> VID table + * + * + * @param[in] PpF1Array + * @param[in] IntegratedInfoTable Integrated info table pointer + * @param[in] Gfx Gfx configuration info + */ + +STATIC VOID +GfxIntInfoTableInitSclkTableKB ( + IN PP_F1_ARRAY_V2 *PpF1Array, + IN ATOM_INTEGRATED_SYSTEM_INFO_V1_8 *IntegratedInfoTable, + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT8 Index; + UINTN AvailSclkIndex; + GnbGfx275_STRUCT *AvailSclkList; + BOOLEAN Sorting; + AvailSclkList = &IntegratedInfoTable->ATOM_INTEGRATED_SYSTEM_INFO_V1_8[0]; + + AvailSclkIndex = 0; + for (Index = 0; Index < 5; Index++) { + if (PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index] != 0) { + AvailSclkList[AvailSclkIndex].GnbGfx275_STRUCT_fld0 = GfxFmCalculateClock (PpF1Array->PP_FUSE_ARRAY_V2_fld33[Index], GnbLibGetHeader (Gfx)); + AvailSclkList[AvailSclkIndex].GnbGfx275_STRUCT_fld1 = Index; + AvailSclkList[AvailSclkIndex].GnbGfx275_STRUCT_fld2 = PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index]; + AvailSclkIndex++; + } + } + //Sort by VoltageIndex & GnbGfx275_STRUCT_fld0 + if (AvailSclkIndex > 1) { + do { + Sorting = FALSE; + for (Index = 0; Index < (AvailSclkIndex - 1); Index++) { + GnbGfx275_STRUCT Temp; + BOOLEAN Exchange; + Exchange = FALSE; + if (AvailSclkList[Index].GnbGfx275_STRUCT_fld1 > AvailSclkList[Index + 1].GnbGfx275_STRUCT_fld1) { + Exchange = TRUE; + } + if ((AvailSclkList[Index].GnbGfx275_STRUCT_fld1 == AvailSclkList[Index + 1].GnbGfx275_STRUCT_fld1) && + (AvailSclkList[Index].GnbGfx275_STRUCT_fld0 > AvailSclkList[Index + 1].GnbGfx275_STRUCT_fld0)) { + Exchange = TRUE; + } + if (Exchange) { + Sorting = TRUE; + LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (GnbGfx275_STRUCT), GnbLibGetHeader (Gfx)); + } + } + } while (Sorting); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * + * + * + * @param[in] Gfx Gfx configuration info + * @retval AGESA_STATUS + */ +AGESA_STATUS +STATIC +GfxIntInfoTableInitKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + ATOM_FUSION_SYSTEM_INFO_V3 SystemInfoTableV3; + PP_F1_ARRAY_V2 *PpF1Array; + ATOM_PPLIB_POWERPLAYTABLE4 *PpTable; + D18F5x170_STRUCT D18F5x170; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInitKB Enter\n"); + + AgesaStatus = AGESA_SUCCESS; + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, GnbLibGetHeader (Gfx)); + if (PpF1Array != NULL) { + LibAmdMemFill (&SystemInfoTableV3, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V3), GnbLibGetHeader (Gfx)); + + // Use common initialization first + Status = GfxIntInfoTableInitV3 (Gfx, &SystemInfoTableV3, PpF1Array); + // Complete table with KB-specific fields + + // Build PP table + PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3.ulPowerplayTable; + Status = GfxPwrPlayBuildTable (PpTable, Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "KB Pplay done\n"); + + // Assign usFormatID to 0x0013 to represent Kabini + PpTable->usFormatID = 0x13; + + // Build Sclk info table + GfxIntInfoTableInitSclkTableKB (PpF1Array, &SystemInfoTableV3.sIntegratedSysInfo, Gfx); + + // Fill in Nb P-state MemclkFreq Data + GfxFillNbPstateMemclkFreqKB (&SystemInfoTableV3.sIntegratedSysInfo, Gfx); + // Fill in HTC Data + GfxFillHtcDataKB (&SystemInfoTableV3.sIntegratedSysInfo, Gfx); + + // Family specific data update + // Determine ulGMCRestoreResetTime + Status = GfxCalculateRestoreResetTimeKB (&SystemInfoTableV3.sIntegratedSysInfo, Gfx, PpF1Array); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); + SystemInfoTableV3.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; + SystemInfoTableV3.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; + + SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo = + GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE | + GPUCAPINFO_DP_USE_SINGLE_PLL_MODE | + GPUCAPINFO_DFS_BYPASS_DISABLE; + + // GPUCAPINFO_DFS_BYPASS_ENABLE should be enabled by default for MOBILE systems + if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) { + SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo |= GPUCAPINFO_DFS_BYPASS_ENABLE; + } + + // Check if NbPstate enable + GnbRegisterReadKB (GnbHandle, TYPE_D18F5, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx)); + if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) { + // If NbPstate enable, then enable NBDPM for driver + SystemInfoTableV3.sIntegratedSysInfo.ulSystemConfig |= BIT3; + } + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV3.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); + //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) + GfxIntInfoTablePostToFbV3 (&SystemInfoTableV3, Gfx); + + GNB_DEBUG_CODE ( + GfxIntInfoTableDebugDumpV3 (&SystemInfoTableV3, Gfx); + ); + } else { + Status = AGESA_ERROR; + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInitKB Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build integrated info table + * GMC FB access requred + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +GfxIntInfoTableInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + if (GfxLibIsControllerPresent (StdHeader)) { + Status = GfxLocateConfigData (StdHeader, &Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_FATAL) { + Status = GfxIntInfoTableInitKB (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntInfoTableInterfaceKB Exit[0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c new file mode 100644 index 0000000000..7523736eb3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.c @@ -0,0 +1,192 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific GFX library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "S3SaveState.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbGfx.h" +#include "GfxLibKB.h" +#include "GnbCommonLib.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXLIBKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GfxDisableControllerKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +GfxCalculateClockKB ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +GfxIsVbiosPostedKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Disable GFX controller + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +VOID +GfxDisableControllerKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbLibPciRMW ( + MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS), + AccessS3SaveWidth32, + 0xffffffff, + 1 << D0F0x7C_ForceIntGfxDisable_OFFSET, + StdHeader + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get system PLL COF + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval System PLL COF + */ +UINT32 +GfxLibGetSystemPllCofKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 v0; + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0500000, &v0, 0, StdHeader); + return 100 * (((v0 >> 1) & 0x3F) + 0x10); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Calculate COF for DFS out of Main PLL + * + * + * + * @param[in] Did Did + * @param[in] StdHeader Standard Configuration Header + * @retval COF in 10khz + */ + +UINT32 +GfxCalculateClockKB ( + IN UINT8 Did, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Divider; + UINT32 SystemPllCof; + SystemPllCof = GfxLibGetSystemPllCofKB (StdHeader) * 100; + if (Did >= 8 && Did <= 0x3F) { + Divider = Did * 25; + } else if (Did > 0x3F && Did <= 0x5F) { + Divider = (Did - 64) * 50 + 1600; + } else if (Did > 0x5F && Did <= 0x7E) { + Divider = (Did - 96) * 100 + 3200; + } else if (Did == 0x7f) { + Divider = 128 * 100; + } else { + ASSERT (FALSE); + return 200 * 100; + } + ASSERT (Divider != 0); + return (((SystemPllCof * 100) + (Divider - 1)) / Divider); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if Video BIOS has posted or not + * + * + * @param[in] Gfx Pointer to global GFX configuration + */ + +BOOLEAN +GfxIsVbiosPostedKB ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 D0F0xBC_xC0200000; + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Gfx)), 0x4, 0xC0200000, &D0F0xBC_xC0200000, 0, GnbLibGetHeader (Gfx)); + + return (((D0F0xBC_xC0200000 >> 16) & 1) == 0) ? TRUE : FALSE; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h new file mode 100644 index 0000000000..117a794fef --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxLibKB.h @@ -0,0 +1,53 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various GFX service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85947 $ @e \$Date: 2013-01-14 17:25:21 -0600 (Mon, 14 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GFXLIBKB_H_ +#define _GFXLIBKB_H_ + +UINT32 +GfxLibGetSystemPllCofKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c new file mode 100644 index 0000000000..b6cfe666a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c @@ -0,0 +1,161 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GFX mid post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88282 $ @e \$Date: 2013-02-19 11:20:56 -0600 (Tue, 19 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GnbGfxFamServices.h" +#include "GfxGmcInitKB.h" +#include "GfxLibKB.h" +#include "GfxLibV3.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "PcieConfigData.h" +#include "PcieConfigLib.h" +#include "cpuFamilyTranslation.h" +#include "GfxSamuInitKB.h" +#include "GnbHandleLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXMIDINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Mid Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GfxMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GFX_PLATFORM_CONFIG *Gfx; + UINT8 AudioEPCount; + UINT32 GMMx5F50; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_FATAL) { + GfxFmDisableController (StdHeader); + } else { + if (Gfx->UmaInfo.UmaMode != UMA_NONE) { + Status = GfxEnableGmmAccessV3 (Gfx); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_SUCCESS) { + // Can not initialize GMM registers going to disable GFX controller + IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n"); + Gfx->UmaInfo.UmaMode = UMA_NONE; + GfxFmDisableController (StdHeader); + } else { + Status = GfxGmcInitKB (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + //Status = GfxSamuInit (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GfxInitSsid (Gfx); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + AudioEPCount = 0; + Status = GfxIntAudioEPEnumV3 (Gfx, &AudioEPCount); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + if (AudioEPCount > 2) { + AudioEPCount = 2; + } + + AudioEPCount = 7 - AudioEPCount; + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x12, 0x5F50, &GMMx5F50, 0, StdHeader); + GMMx5F50 &= ~7; GMMx5F50 |= AudioEPCount & 7; + GMMx5F50 |= 1 << 4; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x12, 0x5F50, &GMMx5F50, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c new file mode 100644 index 0000000000..fa70f375fb --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c @@ -0,0 +1,153 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbF1Table.h" +#include "GnbGfxInitLibV1.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "GnbHandleLib.h" +#include "GfxLibV3.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXPOSTINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GfxPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Init GFX at Post. + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + + +AGESA_STATUS +GfxPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + GFX_CARD_CARD_INFO GfxDiscreteCardInfo; + AGESA_STATUS Status; + GFX_PLATFORM_CONFIG *Gfx; + UINT32 D0F0xBC_xC00C0000; + GnbRegistersKB7269_STRUCT var5; + GnbRegistersKB7314_STRUCT var6; + GNB_HANDLE *GnbHandle; + + PostParamsPtr = (AMD_POST_PARAMS *)StdHeader; + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + ASSERT (GnbHandle != NULL); + GnbRegisterReadKB (GnbHandle, 0x4, + 0xc00c0000, &D0F0xBC_xC00C0000, 0, StdHeader); + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + if (Status == AGESA_SUCCESS) { + if (((D0F0xBC_xC00C0000 >> 1) & 1) != 1) { + if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) { + LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader); + GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader); + if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || + (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) || + ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE) && + ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n"); + } + } + + if (PostParamsPtr->MemConfig.UmaMode == UMA_NONE) { + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &var5.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &var6.Value, 0, StdHeader); + var5.Field.bit16 = FALSE; + var6.Field.bit13 = FALSE; + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &var5.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &var6.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + } + + // Power down iGPU + GfxRequestGPUPowerV3 (Gfx, 0); + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + } + } else { + PostParamsPtr->MemConfig.UmaMode = UMA_NONE; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceKB Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c new file mode 100644 index 0000000000..66cf992243 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c @@ -0,0 +1,253 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86584 $ @e \$Date: 2013-01-23 12:34:28 -0600 (Wed, 23 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbRegisterAccKB.h" +#include "cpuFamilyTranslation.h" +#include "GnbRegistersKB.h" +#include "GfxLibKB.h" +#include "GfxSamuInitKB.h" +#include "GnbSamuPatchKB.h" +#include "OptionGnb.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GFXSAMUINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define LENGTH_1MBYTE 0x0100000ul +#define MASK_1MBYTE 0x0FFFFFul + +#define SAM_IND_INDEX 0x22000ul +#define SAM_IND_DATA 0x22004ul + +#define SAM_SAB_IND_INDEX 0x22008ul +#define SAM_SAB_IND_DATA 0x2200Cul + +#define SMU_TOOLS_INDEX 0x238ul +#define SMU_TOOLS_DATA 0x23Cul + +typedef struct { + UINT32 BootControl; ///< + UINT32 KeySelect; ///< + UINT32 KernelAddrLo; ///< + UINT32 KernelAddrHi; ///< + UINT32 TweakSelect; ///< +} SAMU_BOOT_CONTROL; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GMC + * + * + * + * @param[in] Gfx Pointer to global GFX configuration + * + */ + +AGESA_STATUS +GfxSamuInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ) +{ + UINT32 D0F0xBC_xC00C0000; + GNB_HANDLE *GnbHandle; + VOID *ControlXBuffer; + VOID *AlignedControlXBuffer; + VOID *PatchYBuffer; + VOID *AlignedPatchYBuffer; + SAMU_BOOT_CONTROL *SamuBootControl; + + UINT32 D0F0xBC_x800000A4; + UINT32 GMMx22000; + UINT32 GMMx22004; + UINT32 GMMx22008; + UINT32 GMMx2200C; + UINT32 LoopCount; + BOOLEAN SamuUseF1dPatch; + BOOLEAN SamuPatchEnabled; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSamuInit Enter\n"); + + GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx)); + ASSERT (GnbHandle != NULL); + GnbRegisterReadKB (GnbHandle, 0x4, 0xc00c0000, + &D0F0xBC_xC00C0000, 0, GnbLibGetHeader (Gfx)); + + SamuPatchEnabled = GnbBuildOptions.CfgSamuPatchEnabled; + IDS_OPTION_HOOK (IDS_GNB_LOAD_SAMU_PATCH, &SamuPatchEnabled, GnbLibGetHeader (Gfx)); + + if ((((D0F0xBC_xC00C0000) & BIT24) == 0) && + (SamuPatchEnabled == TRUE)) { + + // Decide which version of the patch to use + SamuUseF1dPatch = TRUE; + + GMMx22008 = 0x29; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, + &GMMx22008, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, 0x12, 0x2200C, + &GMMx2200C, 0, GnbLibGetHeader (Gfx)); + IDS_HDT_CONSOLE (GNB_TRACE, " SAMSAB:29=%08x\n", GMMx2200C); + + if (GMMx2200C == 0x80000001) { + SamuUseF1dPatch = FALSE; + } + + ControlXBuffer = GnbAllocateHeapBufferAndClear (AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + ASSERT (ControlXBuffer != NULL); + if (ControlXBuffer == NULL) { + return AGESA_ERROR; + } + AlignedControlXBuffer = (VOID *) (((UINTN)ControlXBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE)); + PatchYBuffer = GnbAllocateHeapBuffer (AMD_GNB_SAMU_PATCH_HANDLE, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + ASSERT (PatchYBuffer != NULL); + if (PatchYBuffer == NULL) { + return AGESA_ERROR; + } + AlignedPatchYBuffer = (VOID *) (((UINTN)PatchYBuffer + LENGTH_1MBYTE) & (~MASK_1MBYTE)); + + // Copy samu firmware patch to PatchYBuffer + if (SamuUseF1dPatch == TRUE) { + LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKB[0], + SamuPatchKBHeader[1], GnbLibGetHeader (Gfx)); + } else { + LibAmdMemCopy (AlignedPatchYBuffer, &SamuPatchKBUnf1[0], + SamuPatchKBHeaderUnf1[1], GnbLibGetHeader (Gfx)); + } + + // WBINVD + LibAmdWriteBackInvalidateCache (); + + // Load boot control structure + SamuBootControl = (SAMU_BOOT_CONTROL *)AlignedControlXBuffer; + SamuBootControl->BootControl = 0x3; + SamuBootControl->KernelAddrLo = (UINT32) (AlignedPatchYBuffer); + SamuBootControl->KernelAddrHi = 0; //(UINT32) ((((UINT64) AlignedPatchYBuffer) >> 32) & 0xFF); + if (SamuUseF1dPatch == TRUE) { + SamuBootControl->TweakSelect = 0xBB027E1F; + SamuBootControl->KeySelect = 0x8E174F83; + } else { + SamuBootControl->TweakSelect = 0x0; + SamuBootControl->KeySelect = 0x0; + } + + + // Write 0x0 to SAM_CGC_HOST_CTRL to release the clock-gating of SAMU + GMMx22000 = 0x3; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GMMx22004 = 0x0; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + + // Write (physical address of boot control structure)>>8 into SAM_SAB_INIT_TLB_CONFIG (Location X >> 8) + GMMx22008 = 0x4; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22008, &GMMx22008, 0, GnbLibGetHeader (Gfx)); + GMMx2200C = ((UINT32) ((UINT32) AlignedControlXBuffer)) >> 8; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x2200C, &GMMx2200C, 0, GnbLibGetHeader (Gfx)); + + // Write 0x0 to SAM_RST_HOST_SOFT_RESET + GMMx22000 = 0x1; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GMMx22004 = 0x0; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + + // Write 0x2 to SAM_SCRATCH_0 to start the firmware boot + GMMx22000 = 0x38; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GMMx22004 = 0x2; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + + // Poll SAM_RST_HOST_SOFT_RST_RDY and wait for HOST_RDY + do { + // Write 0x2 to SAM_SCRATCH_0 to start the firmware boot + GMMx22000 = 0x51; + GnbRegisterWriteKB (GnbHandle, 0x12, 0x22000, &GMMx22000, 0, GnbLibGetHeader (Gfx)); + GnbRegisterReadKB (GnbHandle, 0x12, 0x22004, &GMMx22004, 0, GnbLibGetHeader (Gfx)); + } while ((GMMx22004 & BIT0) == 0); + + // Clear the allocated memory ranges, locations X and Y (write 0), issue WBINVD + LibAmdMemFill (ControlXBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + LibAmdMemFill (PatchYBuffer, 0, 2 * LENGTH_1MBYTE, GnbLibGetHeader (Gfx)); + LibAmdWriteBackInvalidateCache (); + + // Confirm read of SMC_DRAM_ACCESS_CNTL is 0x1 + D0F0xBC_x800000A4 = 0; + for (LoopCount = 0; LoopCount < 0x00FFFFFF; LoopCount++) { + GnbRegisterReadKB (GnbHandle, 0x4, 0x800000A4, &D0F0xBC_x800000A4, 0, GnbLibGetHeader (Gfx)); + if ((D0F0xBC_x800000A4 & BIT0) != 0) { + break; + } + } + ASSERT ((D0F0xBC_x800000A4 & BIT0) != 0); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbSamuInit Exit\n"); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h new file mode 100644 index 0000000000..44dd8935e0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.h @@ -0,0 +1,53 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * various service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBSAMUINITKB_H_ +#define _GNBSAMUINITKB_H_ + +AGESA_STATUS +GfxSamuInit ( + IN GFX_PLATFORM_CONFIG *Gfx + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c new file mode 100644 index 0000000000..99e7f933a9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c @@ -0,0 +1,479 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GFx tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87698 $ @e \$Date: 2013-02-07 12:40:51 -0600 (Thu, 07 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersKB.h" +#include "cpuFamilyTranslation.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GfxGmcFeature1DisableKB [] = { + //2.1 Disable clock-gating + GNB_ENTRY_WR (0x12, 0x20C0, 0x00000C80), + GNB_ENTRY_WR (0x12, 0x2478, 0x00000400), + GNB_ENTRY_WR (0x12, 0x20B8, 0x00000400), + GNB_ENTRY_WR (0x12, 0x20BC, 0x00000400), + GNB_ENTRY_WR (0x12, 0x2648, 0x00000400), + GNB_ENTRY_WR (0x12, 0x264C, 0x00000400), + GNB_ENTRY_WR (0x12, 0x2650, 0x00000400), + GNB_ENTRY_WR (0x12, 0x15C0, 0x00000400), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxGmcInitTableKB [] = { + GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET), + //2.2 System memory address translation + GNB_ENTRY_COPY (0x12, 0x2814, 0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x281C, 0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x2824, 0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x282C, 0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x2834, 0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS, 0, 32), + GNB_ENTRY_COPY (0x12, 0x283C, 0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS, 0, 32), + // MC_FUS_DRAM0_BANK_ADDR_MAPPING + GNB_ENTRY_COPY (0x12, 0x2844, 0, 8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS, 0, 8), + GNB_ENTRY_COPY (0x12, 0x2844, 8, 1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22, 1), + GNB_ENTRY_COPY (0x12, 0x2844, 9, 1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20, 1), + // MC_FUS_DRAM0_CTL_BASE + GNB_ENTRY_COPY (0x12, 0x284C, 0, 3, D18F1x200_TYPE, D18F1x200_ADDRESS, 4, 3), + GNB_ENTRY_COPY (0x12, 0x284C, 3, 4, D18F1x204_TYPE, D18F1x204_ADDRESS, 0, 4), + GNB_ENTRY_COPY (0x12, 0x284C, 7, 21, D18F1x200_TYPE, D18F1x200_ADDRESS, 11, 21), + GNB_ENTRY_COPY (0x12, 0x284C, 28, 1, D18F1x200_TYPE, D18F1x200_ADDRESS, 3, 1), + GNB_ENTRY_COPY (0x12, 0x284C, 29, 1, D18F1x200_TYPE, D18F1x200_ADDRESS, 0, 1), + // MC_FUS_DRAM0_CTL_LIMIT + GNB_ENTRY_COPY (0x12, 0x2854, 0, 21, D18F1x204_TYPE, D18F1x204_ADDRESS, 11, 21), + GNB_ENTRY_COPY (0x12, 0x2854, 21, 1, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 1, 1), + // MC_FUS_DRAM_MODE + GNB_ENTRY_COPY (0x12, 0x2864, 3, 1, D18F2x78_dct0_TYPE, D18F2x78_dct0_ADDRESS, 8, 1), + GNB_ENTRY_COPY (0x12, 0x2864, 4, 9, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 7, 9), + GNB_ENTRY_COPY (0x12, 0x2864, 0, 2, D18F2x110_TYPE, D18F2x110_ADDRESS, 6, 2), + GNB_ENTRY_COPY (0x12, 0x2864, 2, 1, D18F2x114_TYPE, D18F2x114_ADDRESS, 9, 1), + // MC_FUS_DRAM_CTL_HIGH_01 + GNB_ENTRY_COPY (0x12, 0x285C, 0, 12, D18F1x240_TYPE, D18F1x240_ADDRESS, 11, 12), + + // 2.4 Sequencer model programming + GNB_ENTRY_WR (0x12, 0x276C, 0x000003ff), + + //--------------------------------------------------------------------------- + // 2.5 Power gating init + // Initializing PGFSMs + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x3538, 0x200010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x3538, 0x300010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x210000), + GNB_ENTRY_WR (0x12, 0x3538, 0xa00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x21003), + GNB_ENTRY_WR (0x12, 0x3538, 0xb00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x2b00), + GNB_ENTRY_WR (0x12, 0x3538, 0xc00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x3538, 0xd00010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x420000), + GNB_ENTRY_WR (0x12, 0x3538, 0x100010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x120202), + GNB_ENTRY_WR (0x12, 0x3538, 0x500010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x3e3e36), + GNB_ENTRY_WR (0x12, 0x3538, 0x600010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x373f3e), + GNB_ENTRY_WR (0x12, 0x3538, 0x700010ff), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x0), + GNB_ENTRY_WR (0x12, 0x353C, 0x3e1332), + GNB_ENTRY_WR (0x12, 0x3538, 0xe00010ff), +//--------------------------------------------------------------------------- +// Initializing register engine +// opcode=1, body_cnt=0, mask=0xf, const=0xf: MC_CONFIG (0x800) MC_CONFIG (0x800) + GNB_ENTRY_WR (0x12, 0x3500, 0x0), + GNB_ENTRY_WR (0x12, 0x3504, 0x10000800), + GNB_ENTRY_WR (0x12, 0x3504, 0xf), + GNB_ENTRY_WR (0x12, 0x3504, 0xf), +// opcode=1, body_cnt=0, mask=0x3f, const=0x3f: MC_CONFIG_MCD (0x828) MC_CONFIG_MCD (0x828) + GNB_ENTRY_WR (0x12, 0x3500, 0x4), + GNB_ENTRY_WR (0x12, 0x3504, 0x10000828), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f), +// opcode=1, body_cnt=0, mask=0xffff, const=0xffff: VM_INVALIDATE_REQUEST (0x51e) VM_INVALIDATE_REQUEST (0x51e) + GNB_ENTRY_WR (0x12, 0x3500, 0x8), + GNB_ENTRY_WR (0x12, 0x3504, 0x1000051e), + GNB_ENTRY_WR (0x12, 0x3504, 0xffff), + GNB_ENTRY_WR (0x12, 0x3504, 0xffff), +// opcode=0, body_cnt=2: VM_L2_CNTL (0x500) VM_L2_CNTL3 (0x502) + GNB_ENTRY_WR (0x12, 0x3500, 0xc), + GNB_ENTRY_WR (0x12, 0x3504, 0x20500), +// opcode=0, body_cnt=4: VM_CONTEXT0_CNTL (0x504) VM_SECURE_FAULT_CNTL (0x508) + GNB_ENTRY_WR (0x12, 0x3500, 0x10), + GNB_ENTRY_WR (0x12, 0x3504, 0x40504), +// opcode=0, body_cnt=9: VM_CONTEXT0_CNTL2 (0x50c) VM_CONTEXT15_PAGE_TABLE_BASE_ADDR (0x515) + GNB_ENTRY_WR (0x12, 0x3500, 0x16), + GNB_ENTRY_WR (0x12, 0x3504, 0x9050c), +// opcode=0, body_cnt=9: VM_PRT_APERTURE0_LOW_ADDR (0x52c) VM_CONTEXTS_DISABLE (0x535) + GNB_ENTRY_WR (0x12, 0x3500, 0x21), + GNB_ENTRY_WR (0x12, 0x3504, 0x9052c), +// opcode=0, body_cnt=1: VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR (0x546) VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR (0x547) + GNB_ENTRY_WR (0x12, 0x3500, 0x2c), + GNB_ENTRY_WR (0x12, 0x3504, 0x10546), +// opcode=0, body_cnt=10: VM_FAULT_CLIENT_ID (0x54e) VM_CONTEXT1_PAGE_TABLE_START_ADDR (0x558) + GNB_ENTRY_WR (0x12, 0x3500, 0x2f), + GNB_ENTRY_WR (0x12, 0x3504, 0xa054e), +// opcode=0, body_cnt=1: VM_CONTEXT0_PAGE_TABLE_END_ADDR (0x55f) VM_CONTEXT1_PAGE_TABLE_END_ADDR (0x560) + GNB_ENTRY_WR (0x12, 0x3500, 0x3b), + GNB_ENTRY_WR (0x12, 0x3504, 0x1055f), +// opcode=0, body_cnt=1: VM_DEBUG (0x56f) VM_L2_CG (0x570) + GNB_ENTRY_WR (0x12, 0x3500, 0x3e), + GNB_ENTRY_WR (0x12, 0x3504, 0x1056f), +// opcode=0, body_cnt=1: VM_L2_BANK_SELECT_MASKA (0x572) VM_L2_BANK_SELECT_MASKB (0x573) + GNB_ENTRY_WR (0x12, 0x3500, 0x41), + GNB_ENTRY_WR (0x12, 0x3504, 0x10572), +// opcode=0, body_cnt=2: VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR (0x575) VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET (0x577) + GNB_ENTRY_WR (0x12, 0x3500, 0x44), + GNB_ENTRY_WR (0x12, 0x3504, 0x20575), +// opcode=0, body_cnt=53: MC_CITF_PERFCOUNTER_LO (0x7a0) ATC_PERFCOUNTER_RSLT_CNTL (0x7d5) + GNB_ENTRY_WR (0x12, 0x3500, 0x48), + GNB_ENTRY_WR (0x12, 0x3504, 0x3507a0), +// opcode=0, body_cnt=0: MC_ARB_PERF_MON_CNTL0_ECC (0x7db) MC_ARB_PERF_MON_CNTL0_ECC (0x7db) + GNB_ENTRY_WR (0x12, 0x3500, 0x7f), + GNB_ENTRY_WR (0x12, 0x3504, 0x7db), +// opcode=0, body_cnt=26: MC_SHARED_CHMAP (0x801) MC_VM_STEERING (0x81b) + GNB_ENTRY_WR (0x12, 0x3500, 0x81), + GNB_ENTRY_WR (0x12, 0x3504, 0x1a0801), +// opcode=0, body_cnt=2: MC_CG_CONFIG_MCD (0x829) MC_SHARED_BLACKOUT_CNTL (0x82b) + GNB_ENTRY_WR (0x12, 0x3500, 0x9d), + GNB_ENTRY_WR (0x12, 0x3504, 0x20829), +// opcode=0, body_cnt=4: MC_HUB_MISC_POWER (0x82d) MC_HUB_MISC_DBG (0x831) + GNB_ENTRY_WR (0x12, 0x3500, 0xa1), + GNB_ENTRY_WR (0x12, 0x3504, 0x4082d), +// opcode=0, body_cnt=4: MC_HUB_MISC_OVERRIDE (0x833) MC_HUB_WDP_BP (0x837) + GNB_ENTRY_WR (0x12, 0x3500, 0xa7), + GNB_ENTRY_WR (0x12, 0x3504, 0x40833), +// opcode=0, body_cnt=11: MC_HUB_RDREQ_CNTL (0x83b) MC_HUB_SHARED_DAGB_DLY (0x846) + GNB_ENTRY_WR (0x12, 0x3500, 0xad), + GNB_ENTRY_WR (0x12, 0x3504, 0xb083b), +// opcode=0, body_cnt=1: MC_HUB_RDREQ_DMIF_LIMIT (0x848) MC_HUB_RDREQ_ACPG_LIMIT (0x849) + GNB_ENTRY_WR (0x12, 0x3500, 0xba), + GNB_ENTRY_WR (0x12, 0x3504, 0x10848), +// opcode=0, body_cnt=63: MC_HUB_WDP_SH2 (0x84d) MC_HUB_WDP_SAM (0x88c) + GNB_ENTRY_WR (0x12, 0x3500, 0xbd), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f084d), +// opcode=0, body_cnt=0: MC_VM_MB_L1_TLB0_DEBUG (0x891) MC_VM_MB_L1_TLB0_DEBUG (0x891) + GNB_ENTRY_WR (0x12, 0x3500, 0xfe), + GNB_ENTRY_WR (0x12, 0x3504, 0x891), +// opcode=0, body_cnt=0: MC_VM_MB_L1_TLB2_DEBUG (0x893) MC_VM_MB_L1_TLB2_DEBUG (0x893) + GNB_ENTRY_WR (0x12, 0x3500, 0x100), + GNB_ENTRY_WR (0x12, 0x3504, 0x893), +// opcode=0, body_cnt=0: MC_VM_MB_L2ARBITER_L2_CREDITS (0x8a1) MC_VM_MB_L2ARBITER_L2_CREDITS (0x8a1) + GNB_ENTRY_WR (0x12, 0x3500, 0x102), + GNB_ENTRY_WR (0x12, 0x3504, 0x8a1), +// opcode=0, body_cnt=0: MC_VM_MB_L1_TLB3_DEBUG (0x8a5) MC_VM_MB_L1_TLB3_DEBUG (0x8a5) + GNB_ENTRY_WR (0x12, 0x3500, 0x104), + GNB_ENTRY_WR (0x12, 0x3504, 0x8a5), +// opcode=0, body_cnt=51: MC_XPB_RTR_SRC_APRTR0 (0x8cd) MC_XPB_UNC_THRESH_SID (0x900) + GNB_ENTRY_WR (0x12, 0x3500, 0x106), + GNB_ENTRY_WR (0x12, 0x3504, 0x3308cd), +// opcode=0, body_cnt=1: MC_XPB_WCB_CFG (0x902) MC_XPB_P2P_BAR_CFG (0x903) + GNB_ENTRY_WR (0x12, 0x3500, 0x13b), + GNB_ENTRY_WR (0x12, 0x3504, 0x10902), +// opcode=0, body_cnt=19: MC_XPB_P2P_BAR_SETUP (0x90c) MC_XPB_INTF_CFG (0x91f) + GNB_ENTRY_WR (0x12, 0x3500, 0x13e), + GNB_ENTRY_WR (0x12, 0x3504, 0x13090c), +// opcode=0, body_cnt=0: MC_XPB_SUB_CTRL (0x922) MC_XPB_SUB_CTRL (0x922) + GNB_ENTRY_WR (0x12, 0x3500, 0x153), + GNB_ENTRY_WR (0x12, 0x3504, 0x922), +// opcode=0, body_cnt=0: MC_XPB_PERF_KNOBS (0x924) MC_XPB_PERF_KNOBS (0x924) + GNB_ENTRY_WR (0x12, 0x3500, 0x155), + GNB_ENTRY_WR (0x12, 0x3504, 0x924), +// opcode=0, body_cnt=20: MC_XPB_STICKY_W1C (0x926) MC_XPB_CLG_CFG36 (0x93a) + GNB_ENTRY_WR (0x12, 0x3500, 0x157), + GNB_ENTRY_WR (0x12, 0x3504, 0x140926), +// opcode=2, body_cnt=0: MC_RPB_CID_QUEUE_EX (0x95a) + GNB_ENTRY_WR (0x12, 0x3500, 0x16d), + GNB_ENTRY_WR (0x12, 0x3504, 0x2000095a), + GNB_ENTRY_WR (0x12, 0x3504, 0x1), +// opcode=3, body_cnt=31: MC_RPB_CID_QUEUE_EX_DATA (0x95b) + GNB_ENTRY_WR (0x12, 0x3500, 0x16f), + GNB_ENTRY_WR (0x12, 0x3504, 0x301f095b), +// opcode=0, body_cnt=12: MC_RPB_CONF (0x94d) MC_RPB_PERF_COUNTER_STATUS (0x959) + GNB_ENTRY_WR (0x12, 0x3500, 0x190), + GNB_ENTRY_WR (0x12, 0x3504, 0xc094d), +// opcode=0, body_cnt=16: MC_CITF_XTRA_ENABLE (0x96d) MC_CITF_INT_CREDITS_WR (0x97d) + GNB_ENTRY_WR (0x12, 0x3500, 0x19e), + GNB_ENTRY_WR (0x12, 0x3504, 0x10096d), +// opcode=0, body_cnt=12: MC_CITF_WTM_RD_CNTL (0x97f) MC_WR_GRP_LCL (0x98b) + GNB_ENTRY_WR (0x12, 0x3500, 0x1b0), + GNB_ENTRY_WR (0x12, 0x3504, 0xc097f), +// opcode=0, body_cnt=0: MC_CITF_PERF_MON_CNTL2 (0x98e) MC_CITF_PERF_MON_CNTL2 (0x98e) + GNB_ENTRY_WR (0x12, 0x3500, 0x1be), + GNB_ENTRY_WR (0x12, 0x3504, 0x98e), +// opcode=0, body_cnt=2: MC_CITF_MISC_RD_CG (0x992) MC_CITF_MISC_VM_CG (0x994) + GNB_ENTRY_WR (0x12, 0x3500, 0x1c0), + GNB_ENTRY_WR (0x12, 0x3504, 0x20992), +// opcode=0, body_cnt=2: MC_VM_MD_L1_TLB0_DEBUG (0x998) MC_VM_MD_L1_TLB2_DEBUG (0x99a) + GNB_ENTRY_WR (0x12, 0x3500, 0x1c4), + GNB_ENTRY_WR (0x12, 0x3504, 0x20998), +// opcode=0, body_cnt=0: MC_VM_MD_L2ARBITER_L2_CREDITS (0x9a4) MC_VM_MD_L2ARBITER_L2_CREDITS (0x9a4) + GNB_ENTRY_WR (0x12, 0x3500, 0x1c8), + GNB_ENTRY_WR (0x12, 0x3504, 0x9a4), +// opcode=0, body_cnt=0: MC_VM_MD_L1_TLB3_DEBUG (0x9a7) MC_VM_MD_L1_TLB3_DEBUG (0x9a7) + GNB_ENTRY_WR (0x12, 0x3500, 0x1ca), + GNB_ENTRY_WR (0x12, 0x3504, 0x9a7), +// opcode=0, body_cnt=6: MC_ARB_AGE_CNTL (0x9bf) MC_ARB_GECC2_DEBUG2 (0x9c5) + GNB_ENTRY_WR (0x12, 0x3500, 0x1cc), + GNB_ENTRY_WR (0x12, 0x3504, 0x609bf), +// opcode=0, body_cnt=45: MC_ARB_GECC2 (0x9c9) MC_ARB_MAX_LAT_CID (0x9f6) + GNB_ENTRY_WR (0x12, 0x3500, 0x1d4), + GNB_ENTRY_WR (0x12, 0x3504, 0x2d09c9), +// opcode=0, body_cnt=3: MC_ARB_SSM (0x9f9) MC_ARB_DRAM_TIMING_1 (0x9fc) + GNB_ENTRY_WR (0x12, 0x3500, 0x203), + GNB_ENTRY_WR (0x12, 0x3504, 0x309f9), +// opcode=0, body_cnt=0: MC_ARB_DRAM_TIMING2_1 (0x9ff) MC_ARB_DRAM_TIMING2_1 (0x9ff) + GNB_ENTRY_WR (0x12, 0x3500, 0x208), + GNB_ENTRY_WR (0x12, 0x3504, 0x9ff), +// opcode=0, body_cnt=2: MC_ARB_BURST_TIME (0xa02) MC_ARB_SCRAMBLE_KEY1 (0xa04) + GNB_ENTRY_WR (0x12, 0x3500, 0x20a), + GNB_ENTRY_WR (0x12, 0x3504, 0x20a02), +// opcode=0, body_cnt=6: MC_FUS_DRAM0_CTL_BASE (0xa13) MC_FUS_DRAM_MODE (0xa19) + GNB_ENTRY_WR (0x12, 0x3500, 0x20e), + GNB_ENTRY_WR (0x12, 0x3504, 0x60a13), +// opcode=0, body_cnt=3: MC_FUS_ARB_GARLIC_ISOC_PRI (0xa1f) MC_FUS_ARB_GARLIC_WR_PRI2 (0xa22) + GNB_ENTRY_WR (0x12, 0x3500, 0x216), + GNB_ENTRY_WR (0x12, 0x3504, 0x30a1f), +// opcode=1, body_cnt=0, mask=0x3f, const=0x0: ATC_ATS_FAULT_CNTL (0xccd) ATC_ATS_FAULT_CNTL (0xccd) + GNB_ENTRY_WR (0x12, 0x3500, 0x21b), + GNB_ENTRY_WR (0x12, 0x3504, 0x10000ccd), + GNB_ENTRY_WR (0x12, 0x3504, 0x3f), + GNB_ENTRY_WR (0x12, 0x3504, 0x0), +// opcode=0, body_cnt=7: ATC_VM_APERTURE0_LOW_ADDR (0xcc0) ATC_VM_APERTURE1_CNTL2 (0xcc7) + GNB_ENTRY_WR (0x12, 0x3500, 0x21f), + GNB_ENTRY_WR (0x12, 0x3504, 0x70cc0), +// opcode=0, body_cnt=2: ATC_ATS_CNTL (0xcc9) ATC_ATS_FAULT_DEBUG (0xccb) + GNB_ENTRY_WR (0x12, 0x3500, 0x228), + GNB_ENTRY_WR (0x12, 0x3504, 0x20cc9), +// opcode=0, body_cnt=1: ATC_ATS_DEFAULT_PAGE_LOW (0xcd0) ATC_ATS_DEFAULT_PAGE_CNTL (0xcd1) + GNB_ENTRY_WR (0x12, 0x3500, 0x22c), + GNB_ENTRY_WR (0x12, 0x3504, 0x10cd0), +// opcode=0, body_cnt=4: ATC_MISC_CG (0xcd4) ATC_L2_DEBUG2 (0xcd8) + GNB_ENTRY_WR (0x12, 0x3500, 0x22f), + GNB_ENTRY_WR (0x12, 0x3504, 0x40cd4), +// opcode=0, body_cnt=5: ATC_L1_CNTL (0xcdc) ATC_L1WR_STATUS (0xce1) + GNB_ENTRY_WR (0x12, 0x3500, 0x235), + GNB_ENTRY_WR (0x12, 0x3504, 0x50cdc), +// opcode=0, body_cnt=16: ATC_VMID_PASID_MAPPING_UPDATE_STATUS (0xce6) ATC_VMID15_PASID_MAPPING (0xcf6) + GNB_ENTRY_WR (0x12, 0x3500, 0x23c), + GNB_ENTRY_WR (0x12, 0x3504, 0x100ce6), +// opcode=0, body_cnt=0: ATC_ATS_FAULT_CNTL (0xccd) ATC_ATS_FAULT_CNTL (0xccd) + GNB_ENTRY_WR (0x12, 0x3500, 0x24e), + GNB_ENTRY_WR (0x12, 0x3504, 0xccd), +// opcode=0, body_cnt=23: MC_ARB_HARSH_EN_RD (0xdc0) MC_ARB_HARSH_CTL_WR (0xdd7) + GNB_ENTRY_WR (0x12, 0x3500, 0x250), + GNB_ENTRY_WR (0x12, 0x3504, 0x170dc0), +// opcode=0, body_cnt=0: MC_CONFIG (0x800) MC_CONFIG (0x800) + GNB_ENTRY_WR (0x12, 0x3500, 0x269), + GNB_ENTRY_WR (0x12, 0x3504, 0x800), +// opcode=0, body_cnt=0: MC_CONFIG_MCD (0x828) MC_CONFIG_MCD (0x828) + GNB_ENTRY_WR (0x12, 0x3500, 0x26b), + GNB_ENTRY_WR (0x12, 0x3504, 0x828), +//--------------------------------------------------------------------------- +// Setting up end pointers + GNB_ENTRY_RMW (0x12, 0x3508, 0xfffff000, 0x9b26c000), +//--------------------------------------------------------------------------- +// Enabling light sleep + GNB_ENTRY_RMW (0x12, 0x3544, 0x6000000, 0x2000000), + + // 2.7 Performance tuning + GNB_ENTRY_WR (0x12, 0x27D0, 0x10724847), + GNB_ENTRY_WR (0x12, 0x27C0, 0x00C32008), + GNB_ENTRY_WR (0x12, 0x27C4, 0x00C32006), + GNB_ENTRY_WR (0x12, 0x277C, 0x00000007), + GNB_ENTRY_WR (0x12, 0x218C, 0x000021b1), + GNB_ENTRY_WR (0x12, 0x201C, 0x47773337), + GNB_ENTRY_WR (0x12, 0x2020, 0x73773337), + GNB_ENTRY_WR (0x12, 0x2018, 0x66334303), + GNB_ENTRY_WR (0x12, 0x2014, 0x66300333), + GNB_ENTRY_WR (0x12, 0x2794, 0xfcfcfdfc), + GNB_ENTRY_WR (0x12, 0x2798, 0xfcfcfdfc), + GNB_ENTRY_WR (0x12, 0x27A4, 0x00ffffff), + GNB_ENTRY_WR (0x12, 0x27A8, 0x00ffffff), + GNB_ENTRY_WR (0x12, 0x278C, 0x00000008), + GNB_ENTRY_WR (0x12, 0x2790, 0x00000008), + GNB_ENTRY_WR (0x12, 0x2628, 0x55111000), + GNB_ENTRY_WR (0x12, 0x25E0, 0x00000025), + GNB_ENTRY_WR (0x12, 0x262C, 0x10555111), + GNB_ENTRY_WR (0x12, 0x25E4, 0x00000025), + GNB_ENTRY_WR (0x12, 0x25C8, 0x0080685F), + GNB_ENTRY_WR (0x12, 0x25CC, 0x0000807F), + GNB_ENTRY_WR (0x12, 0x2144, 0x50A1421D), + GNB_ENTRY_WR (0x12, 0x20EC, 0x0000001C), + GNB_ENTRY_WR (0x12, 0x2184, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x21E0, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x217C, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x21C0, 0x0000A1F1), + GNB_ENTRY_WR (0x12, 0x2214, 0x000021B1), + GNB_ENTRY_WR (0x12, 0x2220, 0x000021B1), + GNB_ENTRY_WR (0x12, 0x3758, 0x00000800), + GNB_ENTRY_WR (0x12, 0x375C, 0x00000800), + GNB_ENTRY_WR (0x12, 0x3700, 0xD1000000), + GNB_ENTRY_WR (0x12, 0x3704, 0xD0000000), + GNB_ENTRY_WR (0x12, 0x3748, 0x0000007F), + GNB_ENTRY_WR (0x12, 0x3750, 0x18201015), + GNB_ENTRY_WR (0x12, 0x3754, 0x18201015), + GNB_ENTRY_WR (0x12, 0x253C, 0x000000B4), + GNB_ENTRY_WR (0x12, 0x2550, 0x000000A3), + GNB_ENTRY_WR (0x12, 0x2558, 0x00002077), + GNB_ENTRY_WR (0x12, 0x2558, 0x000020B7), + GNB_ENTRY_WR (0x12, 0x2558, 0x00002A3D), + + GNB_ENTRY_WR (0x12, 0x287C, 0x0c000911), + + //2.9 Display latency + GNB_ENTRY_WR (0x12, 0x2114, 0x00000015), + + GNB_ENTRY_WR (0x12, 0x2880, 0xFCFE8000), + + //2.12 Remove blackout + GNB_ENTRY_WR (0x12, 0x20AC, 0x00000000), + + // VCE Optimization + GNB_ENTRY_RMW (0x12, 0x2108, 0xff00, (1 << 8)), + GNB_ENTRY_WR (0x12, 0x21fc, 0xA1F1), + GNB_ENTRY_WR (0x12, 0x2198, 0xA1F1), + + // STCTRL_IGNORE_PROTECTION_FAULT + GNB_ENTRY_RMW (0x12, 0x350C, 0x01000000, (1 << 24)), + + GNB_ENTRY_RMW (0x12, 0x5490, 0x2 | 0x1, (1 << 0) | (1 << 1)), + + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxGmcFeature1EnableKB [] = { + GNB_ENTRY_WR (0x12, 0x20C0, 0x000c0c80), + GNB_ENTRY_WR (0x12, 0x2478, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x20B8, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x20BC, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x2648, 0x00080400), + GNB_ENTRY_WR (0x12, 0x264C, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x2650, 0x000c0400), + GNB_ENTRY_WR (0x12, 0x15C0, 0x000c0400), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GfxEnvInitTableKB [] = { + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c new file mode 100644 index 0000000000..288884b0cf --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c @@ -0,0 +1,459 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84838 $ @e \$Date: 2012-12-20 10:04:21 -0600 (Thu, 20 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "OptionGnb.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbTable.h" +#include "GnbSmuInitLibV7.h" +#include "GnbSmuFirmwareKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "cpuF16PowerMgmt.h" +#include "excel925.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBEARLYINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB []; +extern GNB_TABLE ROMDATA GnbEarlyInitTableKB []; +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern BUILD_OPT_CFG UserOptions; + +#define CFG_DISP_PHY_TDP_LIMIT 0 +#define CFG_FCH_PWR_CREDIT 0 + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbEarlierInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbScsInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +OptionGnbInstall581 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +STATIC VOID +GnbEarlyInitKB129_fun ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_EARLY_PARAMS *EarlyParams; + UINT32 v0; + UINT32 v1; + D18F4x110_STRUCT D18F4x110; + D18F5xE0_STRUCT D18F5xE0; + UINT32 v4; + UINT32 Data; + + EarlyParams = (AMD_EARLY_PARAMS *) StdHeader; + + v0 = ((EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10) & 0xFFFF) | + (((EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10) & 0xFFFF) << 16); + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3FA04, &v0, 0, StdHeader); + + v1 = ((EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10) & 0xFFFF) | + (((EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10) & 0xFFFF) << 16); + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3f994, &v1, 0, StdHeader); + + GnbRegisterReadKB (GnbGetHandle (StdHeader), + D18F4x110_TYPE, D18F4x110_ADDRESS, &D18F4x110, 0, StdHeader); + GnbRegisterReadKB (GnbGetHandle (StdHeader), + D18F5xE0_TYPE, D18F5xE0_ADDRESS, &D18F5xE0, 0, StdHeader); + + // Period = (2^(RunAvgRange + 1)*CSampleTimer*5.12)us - round down to nearest 10uS + Data = D18F5xE0.Field.RunAvgRange + 1; + Data = 1 << Data; + Data *= D18F4x110.Field.CSampleTimer; + Data = ((Data * 512) / 1000) * 10; + + IDS_HDT_CONSOLE (GNB_TRACE, "VPC period = %d\n", Data); + + v4 = Data; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), + 0x4, 0x3F830, &v4, 0, StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +STATIC VOID +GnbEarlyInitKB180_fun ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F3xA8_STRUCT D18F3xA8; + UINT32 D0F0xBC_x3F9D8; + UINT64 MsrData; + + GnbRegisterReadKB (GnbGetHandle (StdHeader), D18F3xA8_TYPE, D18F3xA8_ADDRESS, &D18F3xA8, 0, StdHeader); + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0x3F9D8, &D0F0xBC_x3F9D8, 0, StdHeader); + D0F0xBC_x3F9D8 &= ~(0xF << 24); + D0F0xBC_x3F9D8 |= (D18F3xA8.Field.PopDownPstate & 0x7) << 24; + LibAmdMsrRead ((PS_REG_BASE + D18F3xA8.Field.PopDownPstate), &MsrData, StdHeader); + D0F0xBC_x3F9D8 |= (((MsrData & (1 << 22)) == 0) ? (1 << 27) :0); + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3F9D8, &D0F0xBC_x3F9D8, 0, StdHeader); + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init Package Power Support + * + * + * + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GnbInitPkgPowerKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 D0F0xBC_x3F834; + UINT32 D0F0xBC_x3F838; + UINT32 D0F0xBC_x3F844; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbInitPkgPowerKB Enter\n"); + + D0F0xBC_x3F834 = CFG_DISP_PHY_TDP_LIMIT; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), TYPE_D0F0xBC, 0x3F834, + &D0F0xBC_x3F834, 0, StdHeader); + + D0F0xBC_x3F838 = CFG_FCH_PWR_CREDIT; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), TYPE_D0F0xBC, 0x3F838, + &D0F0xBC_x3F838, 0, StdHeader); + + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0x3f844, + &D0F0xBC_x3F844, 0, StdHeader); + D0F0xBC_x3F844 &= 0xe0000000; + GnbRegisterWriteKB (GnbGetHandle (StdHeader), 0x4, 0x3f844, + &D0F0xBC_x3F844, 0, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbInitPkgPowerKB Exit\n"); + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Request VDDB Pmin + * + * + * + * @param[in] GnbHandle GNB_HANDLE + * @param[in] StdHeader Standard configuration header + */ + +STATIC VOID +GnbRequestVddNbPminKB ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + D18F5x170_STRUCT D18F5x170; + D18F5x160_STRUCT D18F5x160; + UINT32 Millivolt; + UINT32 NbVid; + DEV_OBJECT DevObject; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbRequestVddNbPminKB Enter\n"); + // 1) Read F5x170[NbPstateMaxVal] to find NB Pmin. + GnbRegisterReadKB (GnbHandle, D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170, 0, StdHeader); + // 2) Determine voltage associated with NB Pmin. Read F5x(160+4*NbPstateMaxVal)[NbVid]. (For example, NBP0 is F5x160, NBP1 is F5x164, etc) + GnbRegisterReadKB (GnbHandle, D18F5x160_TYPE, (D18F5x160_ADDRESS + (4 * D18F5x170.Field.NbPstateMaxVal)), &D18F5x160, 0, StdHeader); + NbVid = (D18F5x160.Field.NbVid_7_ << 7) | (D18F5x160.Field.NbVid_6_0_); + // 3) Make voltage request (via BIOSSMC_MSG_VDDNB_REQUEST) for voltage determined by Step 2. Note that message requires encoding in voltage, not VID. + // Use the following equation to decode SVI2 VIDs: + // Voltage = 1.55 - (0.00625*VID) + // Furthermore, VDDNB requests to SMU should be encoded in 0.25mV steps. + // Therefore, voltage should be translated into mV and then multiplied by 4, to be encoded as 0.25mV steps. + // Or... ( 1.55 * 1000 * 4) - (.00625 * 1000 * 4) * VID) = (1550 * 4) - (25 * VID) + Millivolt = (1550 * 4) - (25 * NbVid); + + IDS_HDT_CONSOLE (GNB_TRACE, " Set Voltage for NbPstateMaxVal = 0x%x, Vid code 0x%x = %d mV\n", D18F5x170.Field.NbPstateMaxVal, NbVid, Millivolt); + DevObject.StdHeader = StdHeader; + DevObject.GnbHandle = GnbHandle; + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_VDDNB_REQUEST, + Millivolt, + 0 + ); + IDS_HDT_CONSOLE (GNB_TRACE, "GnbRequestVddNbPminKB Exit\n"); + return; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Initialize GFX straps. + * + * + * @param[in] StdHeader Standard configuration header + */ +STATIC VOID +GfxStrapsEarlyInitKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbRegistersKB7236_STRUCT v0; + GnbRegistersKB7269_STRUCT v1; + GnbRegistersKB7314_STRUCT v2; + GnbRegistersKB7341_STRUCT v3; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitKB Enter\n"); + + GnbHandle = GnbGetHandle (StdHeader); + + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014AB, &v0.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &v1.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &v2.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x013014BE, &v3.Value, 0, StdHeader); + + v0.Field.bit17 = 1; + + v2.Field.bita = 0x0; + v2.Field.StrapBifF0LegacyDeviceTypeDis = 0x0; + + v1.Field.bit16 = UserOptions.CfgGnbHdAudio; + v2.Field.bit13 = UserOptions.CfgGnbHdAudio; + + // Enable PCI Vendor Specific Capabilities + v3.Field.bit_20 = 1; + + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014AB, &v0.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014AC, &v1.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x13014B6, &v2.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x013014BE, &v3.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsEarlyInitKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable Gfx gBIF + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GfxGBifEnableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + GnbRegistersKB7208_STRUCT var0; + GnbRegistersKB7514_STRUCT var1; + UINT32 D0F0xBC_xC00C0000; + GNB_HANDLE *GnbHandle; + + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGBifEnableKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, 0xc00c0000, &D0F0xBC_xC00C0000, 0, StdHeader); + if (((D0F0xBC_xC00C0000 >> 1) & 1 )!= 1) { + GfxStrapsEarlyInitKB (StdHeader); + } + + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x1301486, &var0.Value, 0, StdHeader); + GnbRegisterReadKB (GnbHandle, TYPE_D0F0xD4, 0x1091518, &var1.Value, 0, StdHeader); + var0.Field.bit2 = 0x1; + var1.Field.bit0 = 0x1; + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x1091518, &var1.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + GnbRegisterWriteKB (GnbHandle, TYPE_D0F0xD4, 0x1301486, &var0.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "GfxGBifEnableKB Exit\n"); + + return AGESA_SUCCESS; +} +/*----------------------------------------------------------------------------------------*/ +/** + * GNB init at early post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + UINT32 Property; + + AgesaStatus = AGESA_SUCCESS; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + + Property = TABLE_PROPERTY_DEFAULT; + Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? 0x00000400ul : 0; + Property |= GnbBuildOptions.CfgSviRevision == 2 ? TABLE_PROPERTY_SVI2 : 0; + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + while (GnbHandle != NULL) { + GnbEarlyInitKB129_fun (StdHeader); + GnbEarlyInitKB180_fun (StdHeader); + GnbInitPkgPowerKB (StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbEarlyInitTableKB, + Property, + 0, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbRequestVddNbPminKB (GnbHandle, StdHeader); + Status = GfxGBifEnableKB (StdHeader); + ASSERT (Status == AGESA_SUCCESS); + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * GNB init at earlier post + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEarlierInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + + AgesaStatus = AGESA_SUCCESS; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceKB Enter\n"); + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + Status = GnbProcessTable ( + GnbHandle, + GnbEarlierInitTableBeforeSmuKB, + 0, + 0, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + Status = GnbSmuFirmwareLoadV7 (GnbHandle, (FIRMWARE_HEADER_V7*) &FirmwareKB[0], StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceKB Exit [0x%x]\n", Status); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +AGESA_STATUS +OptionGnbInstall581 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + + AgesaStatus = AGESA_SUCCESS; + Status = AGESA_SUCCESS; + GnbHandle = GnbGetHandle (StdHeader); + + while (GnbHandle != NULL) { + Status = GnbSmuInitLibV7139_fun0 (GnbHandle, &excel925[0], StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c new file mode 100644 index 0000000000..e9f41de52e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c @@ -0,0 +1,302 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB env post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85506 $ @e \$Date: 2013-01-08 15:38:33 -0600 (Tue, 08 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbPcieConfig.h" +#include "GnbSmuInitLibV7.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV4.h" +#include "GnbNbInitLibV5.h" +#include "GnbF1TableKB.h" +#include "GnbF1Table.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBENVINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbEnvInitTableKB []; +extern GNB_TABLE ROMDATA GnbIommuInitTableKB []; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * NB Dynamic Wake + * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller + * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high). + * + * @param[in] NbPciAddress Gnb PCI address + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +GnbOrbDynamicWakeKB ( + IN PCI_ADDR NbPciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + D0F0x98_x2C_STRUCT D0F0x98_x2C; + + GnbLibPciIndirectRead ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x2C_ADDRESS, + AccessWidth32, + &D0F0x98_x2C.Value, + StdHeader + ); + + // Enable Dynamic wake + // Wake Hysteresis timer value. Specifies the number of SMU pulses to count. + if (GnbBuildOptions.CfgOrbDynWakeEnable) { + D0F0x98_x2C.Field.DynWakeEn = 1; + } else { + D0F0x98_x2C.Field.DynWakeEn = 0; + } + D0F0x98_x2C.Field.WakeHysteresis = 0x19; + + IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &D0F0x98_x2C, StdHeader); + + GnbLibPciIndirectWrite ( + NbPciAddress.AddressValue | D0F0x94_ADDRESS, + D0F0x98_x2C_ADDRESS, + AccessS3SaveWidth32, + &D0F0x98_x2C.Value, + StdHeader + ); +} +/*----------------------------------------------------------------------------------------*/ +/** + * HTC Data + * + * @param[in] GnbHandle Gnb Header + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +GnbFillHtcData ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT32 D0F0xBC_x3FDD4; + D18F3x64_STRUCT D18F3x64; + UINT16 *p = (UINT16 *)&D0F0xBC_x3FDD4; + GnbRegisterReadKB (GnbHandle, D18F3x64_TYPE, D18F3x64_ADDRESS, + &D18F3x64.Value, 0, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, 0x3fdd4, + &D0F0xBC_x3FDD4, 0, StdHeader); + + if (D18F3x64.Field.HtcEn == 1) { + + p[1] = D18F3x64.Field.HtcTmpLmt / 2 + 52; + p[0] = + p[1] - (D18F3x64.Field.HtcHystLmt / 2); + + p[1] = + (p[1] + 49) << 3; + p[0] = + (p[0] + 49) << 3; + + } else { + + p[0] = 0; + p[1] = 0; + + } + + + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdd4, &D0F0xBC_x3FDD4, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * LHTC Data + * + * @param[in] GnbHandle Gnb Header + * @param[in] StdHeader Standard Configuration Header + */ + +VOID +STATIC +GnbUpdateLhtcData ( + IN GNB_HANDLE *GnbHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AMD_ENV_PARAMS *EnvParams; + UINT32 LhtcParameter; + D18F3x64_STRUCT D18F3x64; + UINT32 D0F0xBC_xC0104090; + DEV_OBJECT DevObject; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbUpdateLhtcData Enter\n"); + EnvParams = (AMD_ENV_PARAMS *) StdHeader; + + // Make sure both config values are valid + if ((EnvParams->PlatformConfig.LhtcTemperatureLimit >= 520) && (EnvParams->PlatformConfig.HtcTemperatureLimit >= 520)) { + // Platform config value is in .1 degrees + LhtcParameter = (EnvParams->PlatformConfig.LhtcTemperatureLimit - 520) / 5; + // Read HtcTmpLmt field from D18F3 + GnbRegisterReadKB (GnbGetHandle (StdHeader), D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader); + GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0104090, &D0F0xBC_xC0104090, 0, StdHeader); + if ((D18F3x64.Field.HtcEn == 1) && (LhtcParameter < D18F3x64.Field.HtcTmpLmt) && (LhtcParameter < ((D0F0xBC_xC0104090 >> 23) & 0xFF))) { + // All values are valid, so we can send the service to the SMU + DevObject.StdHeader = StdHeader; + DevObject.GnbHandle = GnbGetHandle (StdHeader); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_LHTC_LIMIT_SetLimit, + LhtcParameter, + GNB_REG_ACC_FLAG_S3SAVE + ); + } + } + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbUpdateLhtcData Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * GNB init at env + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + UINT32 Property; + GNB_HANDLE *GnbHandle; + PCI_ADDR GnbPciAddress; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceKB Enter\n"); + Property = TABLE_PROPERTY_DEFAULT; + Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0; + Property |= GnbBuildOptions.CfgLhtcSupport ? TABLE_PROPERTY_LHTC : 0; + Property |= GnbBuildOptions.CfgTdcSupport ? 0x00040000ul : 0; + Property |= 0x00080000ul; + AgesaStatus = AGESA_SUCCESS; + GnbLoadF1TableKB (StdHeader); + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Status = GnbSetTomV5 (GnbPciAddress, StdHeader); + GnbOrbDynamicWakeKB (GnbPciAddress, StdHeader); + GnbFillHtcData (GnbHandle, StdHeader); + if (GnbIsGnbConnectedToSb (GnbHandle)) { + GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader); + } + + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + + Status = GnbProcessTable ( + GnbHandle, + GnbEnvInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + if ((Property & TABLE_PROPERTY_LHTC) != 0) { + GnbUpdateLhtcData (GnbHandle, StdHeader); + } + + Status = GnbProcessTable ( + GnbHandle, + GnbIommuInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c new file mode 100644 index 0000000000..41b7b176f2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c @@ -0,0 +1,1022 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Gnb f1 table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84159 $ @e \$Date: 2011-12-21 14:49:48 -0600 (Wed, 21 Dec 2011) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbF1Table.h" +#include "GnbF1TableKB.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbHandleLib.h" +#include "OptionGnb.h" +#include "Filecode.h" +//#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBFUSETABLEKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +PP_F1_ARRAY_V2 DefaultPpF1ArrayKB = { + 0, + {0x40, 0, 0, 0, 0}, + {0x40, 0, 0, 0, 0}, + 8, + {0, 0, 0, 0, 0, 0}, + {0x40, 0x40, 0x40, 0, 0}, + {0, 0, 0, 0, 0}, + 3, + 0x10, + 0, + 0, + 0, + 0, + TRUE, + {0x3, 0xC, 0x30, 0xC0}, + 0, + {0, 0, 0, 0}, + {0x40, 0x40, 0x40, 0x40, 0}, + 0, + 0, + 0, + 0, + { 1, 1, 1, 1}, + { 0, 0, 0, 0}, + { 2, 2, 2, 2}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 0, 0, 0, 0}, + { 1, 1, 1, 1}, + { 0x24, 0x24, 0x24, 0x24, 0x24 }, + { 0x17, 0x18, 0x20, 0x22, 0x24 }, + { 0x17, 0x18, 0x20, 0x22, 0x24 }, + { 0x1, 0x2, 0x3, 0x4, 0x5 }, + 0x1E, + 0x3 +}; + + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104007_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104008_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[1]) + }, + { + 13, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[2]) + }, + { + 21, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[3]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010400C_TABLE [] = { + { + 25, + 6, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld21) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010407C_TABLE [] = { + { + 20, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld32[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104080_TABLE [] = { + { + 21, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104083_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104084_TABLE [] = { + { + 5, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[2]) + }, + { + 13, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceFlags[3]) + }, + { + 29, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0104088_TABLE [] = { + { + 0, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[1]) + }, + { + 3, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[2]) + }, + { + 6, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld16[3]) + }, + { + 12, + 5, + (UINT16) offsetof (PP_F1_ARRAY_V2, VceMclk) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC01040A8_TABLE [] = { + { + 16, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[0]) + }, + { + 24, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC01040AC_TABLE [] = { + { + 0, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[2]) + }, + { + 8, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[3]) + }, + { + 16, + 8, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld35[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107044_TABLE [] = { + { + 16, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld36) + }, +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107064_TABLE [] = { + { + 0, + 4, + (UINT16) offsetof (PP_F1_ARRAY_V2, PPlayTableRev) + }, + { + 4, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld3) + }, + { + 11, + 3, + (UINT16) offsetof (PP_F1_ARRAY_V2, PcieGen2Vid) + }, + { + 17, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[0]) + }, + { + 24, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107067_TABLE [] = { + { + 7, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[2]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107068_TABLE [] = { + { + 6, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[3]) + }, + { + 13, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld33[4]) + }, + { + 20, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010706B_TABLE [] = { + { + 3, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010706C_TABLE [] = { + { + 2, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[2]) + }, + { + 9, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[3]) + }, + { + 16, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, excel841_fld6[4]) + }, + { + 23, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010706F_TABLE [] = { + { + 6, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107070_TABLE [] = { + { + 5, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[2]) + }, + { + 12, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[3]) + }, + { + 19, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld5[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107073_TABLE [] = { + { + 2, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107074_TABLE [] = { + { + 1, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[1]) + }, + { + 8, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[2]) + }, + { + 15, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[3]) + }, + { + 22, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld2[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107077_TABLE [] = { + { + 5, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[0]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107078_TABLE [] = { + { + 4, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[1]) + }, + { + 11, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[2]) + }, + { + 18, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[3]) + }, + { + 25, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld1[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010707C_TABLE [] = { + { + 0, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[0]) + }, + { + 7, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[1]) + }, + { + 14, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[2]) + }, + { + 21, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[3]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC010707F_TABLE [] = { + { + 4, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, EclkDid[4]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107080_TABLE [] = { + { + 3, + 5, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld37) + }, + { + 8, + 5, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld38) + }, + { + 13, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[0]) + }, + { + 20, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[1]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107083_TABLE [] = { + { + 3, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[2]) + } +}; + +F1_REGISTER_ENTRY_KB D0F0xBC_xC0107084_TABLE [] = { + { + 2, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[3]) + }, + { + 9, + 7, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld34[4]) + } +}; + +F1_REGISTER_ENTRY_KB D18F3x64_TABLE [] = { + { + D18F3x64_HtcEn_OFFSET, + D18F3x64_HtcEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, HtcEn) + }, + { + D18F3x64_HtcTmpLmt_OFFSET, + D18F3x64_HtcTmpLmt_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, HtcTmpLmt) + }, + { + D18F3x64_HtcHystLmt_OFFSET, + D18F3x64_HtcHystLmt_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld20) + } +}; + +F1_REGISTER_ENTRY_KB GnbFuseTableKB565_TABLE [] = { + { + 1, + 6, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld21) + } +}; + +F1_REGISTER_ENTRY_KB D18F2x90_dct0_TABLE [] = { + { + D18F2x90_dct0_DisDllShutdownSR_OFFSET, + D18F2x90_dct0_DisDllShutdownSR_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, DisDllShutdownSR[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F2x94_dct0_TABLE [] = { + { + D18F2x94_dct0_MemClkFreq_OFFSET, + D18F2x94_dct0_MemClkFreq_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, MemClkFreq[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F2xA8_dct0_TABLE [] = { + { + D18F2xA8_dct0_MemPhyPllPdMode_OFFSET, + D18F2xA8_dct0_MemPhyPllPdMode_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, MemPhyPllPdMode[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F2x2E0_dct0_TABLE [] = { + { + D18F2x2E0_dct0_M1MemClkFreq_OFFSET, + D18F2x2E0_dct0_M1MemClkFreq_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, M1MemClkFreq[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x160_TABLE [] = { + { + D18F5x160_NbPstateEn_OFFSET, + D18F5x160_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[0]) + }, + { + D18F5x160_MemPstate_OFFSET, + D18F5x160_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[0]) + }, + { + D18F5x160_NbFid_OFFSET, + D18F5x160_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[0]) + }, + { + D18F5x160_NbDid_OFFSET, + D18F5x160_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[0]) + }, + { + D18F5x160_NbVid_6_0_OFFSET, + D18F5x160_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[0]) + }, + { + D18F5x160_NbVid_7_OFFSET, + D18F5x160_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[0]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x164_TABLE [] = { + { + D18F5x164_NbPstateEn_OFFSET, + D18F5x164_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[1]) + }, + { + D18F5x164_MemPstate_OFFSET, + D18F5x164_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[1]) + }, + { + D18F5x164_NbFid_OFFSET, + D18F5x164_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[1]) + }, + { + D18F5x164_NbDid_OFFSET, + D18F5x164_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[1]) + }, + { + D18F5x164_NbVid_6_0_OFFSET, + D18F5x164_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[1]) + }, + { + D18F5x164_NbVid_7_OFFSET, + D18F5x164_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[1]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x168_TABLE [] = { + { + D18F5x168_NbPstateEn_OFFSET, + D18F5x168_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[2]) + }, + { + D18F5x168_MemPstate_OFFSET, + D18F5x168_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[2]) + }, + { + D18F5x168_NbFid_OFFSET, + D18F5x168_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[2]) + }, + { + D18F5x168_NbDid_OFFSET, + D18F5x168_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[2]) + }, + { + D18F5x168_NbVid_6_0_OFFSET, + D18F5x168_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[2]) + }, + { + D18F5x168_NbVid_7_OFFSET, + D18F5x168_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[2]) + } +}; + +F1_REGISTER_ENTRY_KB D18F5x16C_TABLE [] = { + { + D18F5x16C_NbPstateEn_OFFSET, + D18F5x16C_NbPstateEn_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld26[3]) + }, + { + D18F5x16C_MemPstate_OFFSET, + D18F5x16C_MemPstate_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld29[3]) + }, + { + D18F5x16C_NbFid_OFFSET, + D18F5x16C_NbFid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld30[3]) + }, + { + D18F5x16C_NbDid_OFFSET, + D18F5x16C_NbDid_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld31[3]) + }, + { + D18F5x16C_NbVid_6_0_OFFSET, + D18F5x16C_NbVid_6_0_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld27[3]) + }, + { + D18F5x16C_NbVid_7_OFFSET, + D18F5x16C_NbVid_7_WIDTH, + (UINT16) offsetof (PP_F1_ARRAY_V2, PP_FUSE_ARRAY_V2_fld28[3]) + } +}; + + +F1_TABLE_ENTRY_KB F1RegisterTableKB [] = { + + { + 0x4, + 0xC0104007, + sizeof (D0F0xBC_xC0104007_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104007_TABLE + }, + { + 0x4, + 0xC0104008, + sizeof (D0F0xBC_xC0104008_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104008_TABLE + }, + { + 0x4, + 0xC010400c, + sizeof (D0F0xBC_xC010400C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010400C_TABLE + }, + { + 0x4, + 0xC010407c, + sizeof (D0F0xBC_xC010407C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010407C_TABLE + }, + { + 0x4, + 0xC0104080, + sizeof (D0F0xBC_xC0104080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104080_TABLE + }, + { + 0x4, + 0xC0104083, + sizeof (D0F0xBC_xC0104083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104083_TABLE + }, + { + 0x4, + 0xC0104084, + sizeof (D0F0xBC_xC0104084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104084_TABLE + }, + { + 0x4, + 0xC0104088, + sizeof (D0F0xBC_xC0104088_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0104088_TABLE + }, + { + 0x4, + 0xC01040a8, + sizeof (D0F0xBC_xC01040A8_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC01040A8_TABLE + }, + { + 0x4, + 0xC01040ac, + sizeof (D0F0xBC_xC01040AC_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC01040AC_TABLE + }, + { + 0x4, + 0xC0107044, + sizeof (D0F0xBC_xC0107044_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107044_TABLE + }, + { + 0x4, + 0xC0107064, + sizeof (D0F0xBC_xC0107064_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107064_TABLE + }, + { + 0x4, + 0xC0107067, + sizeof (D0F0xBC_xC0107067_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107067_TABLE + }, + { + 0x4, + 0xC0107068, + sizeof (D0F0xBC_xC0107068_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107068_TABLE + }, + { + 0x4, + 0xC010706b, + sizeof (D0F0xBC_xC010706B_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010706B_TABLE + }, + { + 0x4, + 0xC010706c, + sizeof (D0F0xBC_xC010706C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010706C_TABLE + }, + { + 0x4, + 0xC010706f, + sizeof (D0F0xBC_xC010706F_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010706F_TABLE + }, + { + 0x4, + 0xC0107070, + sizeof (D0F0xBC_xC0107070_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107070_TABLE + }, + { + 0x4, + 0xC0107073, + sizeof (D0F0xBC_xC0107073_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107073_TABLE + }, + { + 0x4, + 0xC0107074, + sizeof (D0F0xBC_xC0107074_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107074_TABLE + }, + { + 0x4, + 0xC0107077, + sizeof (D0F0xBC_xC0107077_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107077_TABLE + }, + { + 0x4, + 0xC0107078, + sizeof (D0F0xBC_xC0107078_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107078_TABLE + }, + { + 0x4, + 0xC010707c, + sizeof (D0F0xBC_xC010707C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC010707C_TABLE + }, + { + 0x4, + 0xC0107080, + sizeof (D0F0xBC_xC0107080_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107080_TABLE + }, + { + 0x4, + 0xC0107083, + sizeof (D0F0xBC_xC0107083_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107083_TABLE + }, + { + 0x4, + 0xC0107084, + sizeof (D0F0xBC_xC0107084_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D0F0xBC_xC0107084_TABLE + } +}; + +F1_TABLE_ENTRY_KB PPRegisterTableKB [] = { + { + D18F3x64_TYPE, + D18F3x64_ADDRESS, + sizeof (D18F3x64_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F3x64_TABLE + }, + { + 0x4, + 0xC0500000, + sizeof (GnbFuseTableKB565_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + GnbFuseTableKB565_TABLE + }, + { + D18F2x90_dct0_TYPE, + D18F2x90_dct0_ADDRESS, + sizeof (D18F2x90_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F2x90_dct0_TABLE + }, + { + D18F2x94_dct0_TYPE, + D18F2x94_dct0_ADDRESS, + sizeof (D18F2x94_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F2x94_dct0_TABLE + }, + { + D18F2xA8_dct0_TYPE, + D18F2xA8_dct0_ADDRESS, + sizeof (D18F2xA8_dct0_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F2xA8_dct0_TABLE + }, + { + D18F5x160_TYPE, + D18F5x160_ADDRESS, + sizeof (D18F5x160_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x160_TABLE + }, + { + D18F5x164_TYPE, + D18F5x164_ADDRESS, + sizeof (D18F5x164_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x164_TABLE + }, + { + D18F5x168_TYPE, + D18F5x168_ADDRESS, + sizeof (D18F5x168_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x168_TABLE + }, + { + D18F5x16C_TYPE, + D18F5x16C_ADDRESS, + sizeof (D18F5x16C_TABLE) / sizeof (F1_REGISTER_ENTRY_KB), + D18F5x16C_TABLE + } +}; + + +F1_TABLE_KB F1TableKB = { + sizeof (F1RegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + F1RegisterTableKB +}; + +F1_TABLE_KB PPTableKB = { + sizeof (PPRegisterTableKB) / sizeof (F1_TABLE_ENTRY_KB), + PPRegisterTableKB +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Load F1 Table KB + * + * + * param[out] PpF1Array Pointer to save f1 table + * param[in] StdHeader Pointer to Standard configuration + * retval AGESA_STATUS + */ + +STATIC VOID +NbF1LoadF1TableKB ( + IN F1_TABLE_KB *F1Table, + OUT PP_F1_ARRAY_V2 *PpF1Array, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN RegisterIndex; + + for (RegisterIndex = 0; RegisterIndex < F1Table->F1TableLength; RegisterIndex++ ) { + UINTN FieldIndex; + UINTN F1RegisterTableLength; + UINT32 F1Value; + F1RegisterTableLength = F1Table->F1Table[RegisterIndex].F1RegisterTableLength; + + GnbRegisterReadKB ( + GnbGetHandle (StdHeader), + F1Table->F1Table[RegisterIndex].RegisterSpaceType, + F1Table->F1Table[RegisterIndex].Register, + &F1Value, + 0, + StdHeader + ); + for (FieldIndex = 0; FieldIndex < F1RegisterTableLength; FieldIndex++) { + F1_REGISTER_ENTRY_KB RegisterEntry; + RegisterEntry = F1Table->F1Table[RegisterIndex].F1RegisterTable[FieldIndex]; + *((UINT8 *) PpF1Array + RegisterEntry.F1Offset) = (UINT8) ((F1Value >> RegisterEntry.FieldOffset) & + ((1 << RegisterEntry.FieldWidth) - 1)); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb load f1 table + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbLoadF1TableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PP_F1_ARRAY_V2 *PpF1Array; + AGESA_STATUS Status; + D18F3xA0_STRUCT D18F3xA0; + + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadF1TableKB Enter\n"); + + PpF1Array = (PP_F1_ARRAY_V2 *) GnbAllocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, sizeof (PP_F1_ARRAY_V2), StdHeader); + ASSERT (PpF1Array != NULL); + if (PpF1Array != NULL) { + //Support for real f1 table + GnbRegisterReadKB (GnbGetHandle (StdHeader), D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader); + + if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealF1Table)) { + NbF1LoadF1TableKB (&F1TableKB, PpF1Array, StdHeader); + PpF1Array->PP_FUSE_ARRAY_V2_fld13 = TRUE; + IDS_HDT_CONSOLE (NB_MISC, " Processor F1d\n"); + } else { + LibAmdMemCopy (PpF1Array, &DefaultPpF1ArrayKB, sizeof (PP_F1_ARRAY_V2), StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Processor Unf1d\n"); + } + NbF1LoadF1TableKB (&PPTableKB, PpF1Array, StdHeader); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPF1_OVERRIDE, PpF1Array, StdHeader); + } else { + Status = AGESA_ERROR; + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadF1TableKB Exit [0x%x]\n", Status); + return Status; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h new file mode 100644 index 0000000000..8ea51d0c0d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.h @@ -0,0 +1,78 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * F1 table initialization + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBF1TABLEKB_H_ +#define _GNBF1TABLEKB_H_ + +#pragma pack (push, 1) + +/// F1 field entry +typedef struct { + UINT8 FieldOffset; ///< Field offset in f1 register + UINT8 FieldWidth; ///< Width of field + UINT16 F1Offset; ///< destination offset in translation table +} F1_REGISTER_ENTRY_KB; + +/// F1 register entry +typedef struct { + UINT8 RegisterSpaceType; ///< Register type + UINT32 Register; ///< FCR register address + UINT8 F1RegisterTableLength; ///< Length of field table for this register + F1_REGISTER_ENTRY_KB *F1RegisterTable; ///< Pointer to field table +} F1_TABLE_ENTRY_KB; + +/// F1 translation table +typedef struct { + UINT8 F1TableLength; ///< Length of translation table + F1_TABLE_ENTRY_KB *F1Table; ///< Pointer to register table +} F1_TABLE_KB; + +#pragma pack (pop) + +AGESA_STATUS +GnbLoadF1TableKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h new file mode 100644 index 0000000000..47b8fd51a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbInitKBInstall.h @@ -0,0 +1,234 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * KB service installation file + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86079 $ @e \$Date: 2013-01-16 00:59:04 -0600 (Wed, 16 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNB_INIT_KB_INSTALL_H_ +#define _GNB_INIT_KB_INSTALL_H_ + +//----------------------------------------------------------------------- +// Specify definition used by module services +//----------------------------------------------------------------------- + +#include "GnbPcie.h" +#include "GnbUraServices.h" +#include "GnbPcieFamServices.h" +#include "GnbFamServices.h" +#include "GnbGfxFamServices.h" + +//----------------------------------------------------------------------- +// Export services +//----------------------------------------------------------------------- + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) + + extern F_PCIEFMGETSBCONFIGINFO PcieGetSbConfigInfoKB; + extern F_PCIEFMGETCOMPLEXDATALENGTH PcieGetComplexDataLengthKB; + extern F_PCIEFMBUILDCOMPLEXCONFIGURATION PcieBuildComplexConfigurationKB; + extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION PcieConfigureEnginesLaneAllocationKB; + extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING PcieCheckPortPciDeviceMappingKB; + extern F_PCIEFMMAPPORTPCIADDRESS PcieMapPortPciAddressKB; + extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED PcieCheckPortPcieLaneCanBeMuxedKB; + + + PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolKB = { + PcieGetComplexDataLengthKB, + PcieBuildComplexConfigurationKB, + PcieConfigureEnginesLaneAllocationKB, + PcieCheckPortPciDeviceMappingKB, + PcieMapPortPciAddressKB, + PcieCheckPortPcieLaneCanBeMuxedKB, + PcieGetSbConfigInfoKB + }; + + GNB_SERVICE GnbPcieCongigServicesKB = { + GnbPcieFamConfigService, + AMD_FAMILY_KB, + &GnbPcieConfigProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieCongigServicesKB +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + extern F_PCIEFMGETCORECONFIGURATIONVALUE PcieGetCoreConfigurationValueKB; + extern F_PCIEFMGETLINKSPEEDCAP PcieGetLinkSpeedCapKB; + extern F_PCIEFMGETNATIVEPHYLANEBITMAP PcieGetNativePhyLaneBitmapKB; + extern F_PCIEFMSETLINKSPEEDCAP PcieSetLinkSpeedCapV4; + + PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolKB = { + PcieGetCoreConfigurationValueKB, + PcieGetLinkSpeedCapKB, + PcieGetNativePhyLaneBitmapKB, + PcieSetLinkSpeedCapV4 + }; + + GNB_SERVICE GnbPcieInitServicesKB = { + GnbPcieFamInitService, + AMD_FAMILY_KB, + &GnbPcieInitProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieInitServicesKB +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) + #if IDSOPT_IDS_ENABLED == TRUE + #if IDSOPT_TRACING_ENABLED == TRUE + extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING PcieDebugGetHostRegAddressSpaceStringKB; + extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING PcieDebugGetWrapperNameStringKB; + extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING PcieDebugGetCoreConfigurationStringKB; + + PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolKB = { + PcieDebugGetHostRegAddressSpaceStringKB, + PcieDebugGetWrapperNameStringKB, + PcieDebugGetCoreConfigurationStringKB + }; + + GNB_SERVICE GnbPcieDebugServicesKB = { + GnbPcieFamDebugService, + AMD_FAMILY_KB, + &GnbPcieDebugProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbPcieDebugServicesKB + #endif + #endif +#endif + +#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) + extern F_GNB_REGISTER_ACCESS GnbRegisterReadKB; + extern F_GNB_REGISTER_ACCESS GnbRegisterWriteKB; + + GNB_REGISTER_SERVICE GnbRegisterAccessProtocolKB = { + GnbRegisterReadKB, + GnbRegisterWriteKB + }; + + GNB_SERVICE GnbRegisterAccessServicesKB = { + GnbRegisterAccessService, + AMD_FAMILY_KB, + &GnbRegisterAccessProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbRegisterAccessServicesKB + + extern F_GNBURASERVICELOCATEREGTBL GnbUraLocateRegTblKB; + extern F_GNBURASERVICEGET GnbUraGetKB; + extern F_GNBURASERVICESET GnbUraSetKB; + extern F_GNBURASERVICESTREAMSET GnbUraStreamSetKB; + + GNB_URA_SERVICE GnbUraProtocolKB = { + GnbUraLocateRegTblKB, + GnbUraGetKB, + GnbUraSetKB, + GnbUraStreamSetKB + }; + + GNB_SERVICE GnbUraServicesKB = { + GnbUraService, + AMD_FAMILY_KB, + &GnbUraProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbUraServicesKB + + extern F_GFXMAPENGINETODISPLAYPATH GfxMapEngineToDisplayPathKB; + extern F_GFXDISABLECONTROLLER GfxDisableControllerKB; + extern F_GFXCALCULATECLOCK GfxCalculateClockKB; + extern F_GFXISVBIOSPOSTED GfxIsVbiosPostedKB; + + GFX_FAM_SERVICES GfxFamilyServiceProtocolKB = { + GfxMapEngineToDisplayPathKB, + GfxDisableControllerKB, + GfxCalculateClockKB, + GfxIsVbiosPostedKB + }; + + GNB_SERVICE GfxFamilyServicesKB = { + GfxFamService, + AMD_FAMILY_KB, + &GfxFamilyServiceProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GfxFamilyServicesKB + + extern F_GNBTIMESTAMP GnbTimeStampKB; + + GNB_FAM_TS_SERVICES GnbFamTsProtocolKB = { + GnbTimeStampKB, + }; + + GNB_SERVICE GnbFamTsServicesKB = { + GnbFamTsService, + AMD_FAMILY_KB, + &GnbFamTsProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &GnbFamTsServicesKB + + + extern F_PCIE_MAXPAYLOAD_SETTING PcieMaxPayloadKB; + + PCIE_MAXPAYLOAD_SERVICE PcieMaxPayloadProtocolKB = { + PcieMaxPayloadKB + }; + + GNB_SERVICE PcieMaxPayloadServicesKB = { + GnbPcieMaxPayloadService, + AMD_FAMILY_KB, + &PcieMaxPayloadProtocolKB, + SERVICES_POINTER + }; + #undef SERVICES_POINTER + #define SERVICES_POINTER &PcieMaxPayloadServicesKB + +#endif +#endif // _GNB_INIT_KB_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c new file mode 100644 index 0000000000..82f32dd62e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c @@ -0,0 +1,165 @@ +/** + * @file + * + * GNB init tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersKB.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GnbIommuInitTableKB [] = { + + // 1. Program D0F0x64_x0D[PciDev0Fn2RegEn] = 1h + GNB_ENTRY_RMW ( + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET) + ), + // 2. Program credits for the BIF client as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_BIF << 16) | 0x32), + 0x10000 | 0x3F0 | 0xFC00, + (0x1 << 16) | (0x8 << 4) | (0x8 << 10) + ), + // 3. Program credits for the PPD client as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_PPD << 16) | 0x32), + 0x3F0 | 0xFC00, + (0x8 << 4) | (0x7 << 10) + ), + // 4. Program credits for the INTGEN client as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_INTGEN << 16) | 0x32), + 0x3F0 | 0xFC00, + (0x4 << 4) | (0x4 << 10) + ), + // 5. Program clock gating as follows + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_PPD << 16) | 0x33), + 0x10 | 0x20 | + 0x40 | 0x80 | + 0x100 | 0x200 | + 0x400 | 0x80000000 | + 0x800, + (0x1 << 4) | (0x1 << 5) | + (0x1 << 6) | (0x1 << 7) | + (0x1 << 8) | (0x1 << 9) | + (0x1 << 10) | (0x1 << 31) | + (0x1 << 11) + ), + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_BIF << 16) | 0x33), + 0x10 | 0x20 | + 0x40 | 0x80 | + 0x100 | 0x200 | + 0x400 | 0x80000000 | + 0x800, + (0x1 << 4) | (0x1 << 5) | + (0x1 << 6) | (0x1 << 7) | + (0x1 << 8) | (0x1 << 9) | + (0x1 << 10) | (0x1 << 31) | + (0x1 << 11) + ), + GNB_ENTRY_RMW ( + 0xa, + ((L1_SEL_INTGEN << 16) | 0x33), + 0x10 | 0x20 | + 0x40 | 0x80 | + 0x100 | 0x200 | + 0x400 | 0x80000000 | + 0x800, + (0x1 << 4) | (0x1 << 5) | + (0x1 << 6) | (0x1 << 7) | + (0x1 << 8) | (0x1 << 9) | + (0x1 << 10) | (0x1 << 31) | + (0x1 << 11) + ), + // 6. Program D0F0x64_x0D[PciDev0Fn2RegEn] = 0h + GNB_ENTRY_RMW ( + D0F0x64_x0D_TYPE, + D0F0x64_x0D_ADDRESS, + D0F0x64_x0D_PciDev0Fn2RegEn_MASK, + 0 + ), + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c new file mode 100644 index 0000000000..b9ba10de20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c @@ -0,0 +1,429 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * GNB mid post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "GnbPcieConfig.h" +#include "GnbF1Table.h" +#include "heapManager.h" +#include "GnbGfxFamServices.h" +#include "GnbCommonLib.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GnbGfxInitLibV1.h" +#include "GnbSmuInitLibV7.h" +#include "GnbTable.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "GnbFamServices.h" +#include "OptionGnb.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBMIDINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern GNB_TABLE ROMDATA GnbMidInitTableKB[]; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +GnbMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * + * + * @param[out] Index State index + * @param[in] PpF1s + * @retval TRUE State is valid + */ +STATIC BOOLEAN +GnbIsF1dStateValid ( + IN UINT8 Index, + IN PP_F1_ARRAY_V2 *PpF1s + ) +{ + BOOLEAN Result; + Result = FALSE; + + if (Index >= 5) { + Result = FALSE; + } else if ((PpF1s->PP_FUSE_ARRAY_V2_fld37 & (1 << Index)) || + (PpF1s->PP_FUSE_ARRAY_V2_fld38 & (1 << Index))) { + Result = TRUE; + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * LCLK DPM Initialization + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +STATIC AGESA_STATUS +GnbLclkDpmInitKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + PP_F1_ARRAY_V2 *PpF1Array; + PCI_ADDR GnbPciAddress; + UINT8 Index; + UINT8 LclkDpmMode; + + UINT32 D0F0xBC_x3FD00[8]; + UINT32 D0F0xBC_x3FD04[8]; + UINT32 D0F0xBC_x3FD08[8]; + UINT32 D0F0xBC_x3FD0C[8]; + UINT32 D0F0xBC_x3FD10[8]; + UINT32 D0F0xBC_x3FDC8; + UINT32 D0F0xBC_x3F820; + UINT32 D0F0xBC_x3FDC4; + UINT32 D0F0xBC_xC0200110; + + GNB_HANDLE *GnbHandle; + DEV_OBJECT DevObject; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitKB Enter\n"); + Status = AGESA_SUCCESS; + + GnbHandle = GnbGetHandle (StdHeader); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + DevObject.GnbHandle = GnbHandle; + DevObject.StdHeader = StdHeader; + + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, 0, StdHeader); + D0F0xBC_x3F820 &= ~0xFF; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; + IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); + if (LclkDpmMode == LclkDpmRcActivity) { + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, StdHeader); + if (PpF1Array != NULL) { + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + if (Status == AGESA_SUCCESS) { + GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + //Clear DPM_EN bit in LCLK_DPM_CNTL register + //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, 0, StdHeader); + D0F0xBC_x3FDC8 &= 0x00FFFFFF; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + //Initialize LCLK states + LibAmdMemFill (D0F0xBC_x3FD00, 0x00, sizeof (D0F0xBC_x3FD00), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD04, 0x00, sizeof (D0F0xBC_x3FD04), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD08, 0x00, sizeof (D0F0xBC_x3FD08), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD0C, 0x00, sizeof (D0F0xBC_x3FD0C), StdHeader); + LibAmdMemFill (D0F0xBC_x3FD10, 0x00, sizeof (D0F0xBC_x3FD10), StdHeader); + + for (Index = 0; Index < 8; ++Index) { + + if (GnbIsF1dStateValid (Index, PpF1Array)) { + + ASSERT (Index < 5); + IDS_HDT_CONSOLE (GNB_TRACE, " Valid Lclk state: %d\n", Index); + + // CNTL0 + D0F0xBC_x3FD00[Index] = 0; + D0F0xBC_x3FD00[Index] |= (PpF1Array->PP_FUSE_ARRAY_V2_fld5[Index] & 0xFF) << 16; + D0F0xBC_x3FD00[Index] |= 1 << 24; + + // CNTL1 + D0F0xBC_x3FD04[Index] = GnbTranslateVidCodeToMillivoltV5 ( + PpF1Array->PP_FUSE_ARRAY_V2_fld32[Index], StdHeader + ) * 4 / 100; + + // CNTL2 + // D0F0xBC_x3FD08 defined as zero and is already zeroed above + D0F0xBC_x3FD08[Index] = 0; + + // CNTL3 + D0F0xBC_x3FD0C[Index] = + GfxFmCalculateClock (PpF1Array->PP_FUSE_ARRAY_V2_fld5[Index], StdHeader); + D0F0xBC_x3FD10[Index] &= ~(0xFF << 8); + switch (D0F0xBC_x3FD0C[Index]) { + case 20000: + D0F0xBC_x3FD10[Index] |= 0x7 << 8; + break; + case 30000: + D0F0xBC_x3FD10[Index] |= 0x2 << 8; + break; + case 40000: + D0F0xBC_x3FD10[Index] |= 0x3 << 8; + break; + case 15000: + D0F0xBC_x3FD10[Index] |= 0x6 << 8; + break; + case 10000: + D0F0xBC_x3FD10[Index] |= 0x8 << 8; + break; + default: + break; + } + + // Activity Threshold + D0F0xBC_x3FD10[Index] &= ~0xFFFF0000; + D0F0xBC_x3FD10[Index] |= 50 << 24; + } else { + + IDS_HDT_CONSOLE (GNB_TRACE, " Invalid Lclk state: %d\n", Index); + + // CNTL0 + D0F0xBC_x3FD00[Index] = 0xF800; + + // CNTL1 + D0F0xBC_x3FD04[Index] = 0x0; + + // CNTL2 + // D0F0xBC_x3FD08 defined as zero and is already zeroed above + D0F0xBC_x3FD08[Index] = 0; + + // CNTL3 + D0F0xBC_x3FD0C[Index] = 0; + + // Activity Threshold + D0F0xBC_x3FD10[Index] &= ~0xFFFF0000; + D0F0xBC_x3FD10[Index] |= 50 << 24; + } + + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd00 + Index * 0x14, + &D0F0xBC_x3FD00[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd04 + Index * 0x14, + &D0F0xBC_x3FD04[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd08 + Index * 0x14, + &D0F0xBC_x3FD08[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd0c + Index * 0x14, + &D0F0xBC_x3FD0C[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + GnbRegisterWriteKB ( + GnbHandle, + 0x4, + 0x3fd10 + Index * 0x14, + &D0F0xBC_x3FD10[Index], + GNB_REG_ACC_FLAG_S3SAVE, + StdHeader + ); + } + //Enable LCLK DPM Voltage Scaling + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, 0, StdHeader); + D0F0xBC_x3FDC8 &= 0xFF; + D0F0xBC_x3FDC8 |= 1 << 16 | 1 << 24; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdc8, &D0F0xBC_x3FDC8, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3fdc4, &D0F0xBC_x3FDC4, 0, StdHeader); + D0F0xBC_x3FDC4 = 5; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3fdc4, &D0F0xBC_x3FDC4, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, 0, StdHeader); + D0F0xBC_x3F820 &= ~0xFF; D0F0xBC_x3F820 |= 1; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0x3f820, &D0F0xBC_x3F820, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + GnbRegisterReadKB (GnbHandle, 0x4, + 0xc0200110, &D0F0xBC_xC0200110, 0, StdHeader); + D0F0xBC_xC0200110 &= ~(1 << 2 | 7 << 5 | 0xfffff800); + D0F0xBC_xC0200110 &= ~(1 << 0 | 1 << 1 | 1 << 8); + D0F0xBC_xC0200110 |= 3<<3 | 1 << 9 | 1 << 10; //.Field.BusyCntSel = 3; + GnbRegisterWriteKB (GnbHandle, 0x4, + 0xc0200110, &D0F0xBC_xC0200110, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); + + + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_LCLK_DPM_ENABLE, + 0, + GNB_REG_ACC_FLAG_S3SAVE + ); + + } + } else { + Status = AGESA_ERROR; + } + + GnbSmuServiceRequestV7 ( + &DevObject, + SMC_MSG_ENABLE_ALLCLK_MONITOR, + 0, + GNB_REG_ACC_FLAG_S3SAVE + ); + + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitKB Exit [0x%x]\n", Status); + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + UINT32 Property; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + PCI_ADDR GnbPciAddress; + + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceKB Enter\n"); + + Property = TABLE_PROPERTY_DEFAULT; + Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED; + Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0; + Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? 0x00000008ul : 0; + Property |= 0x00000010ul; + Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? 0x00000020ul : 0; + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); + Status = GnbProcessTable ( + GnbHandle, + GnbMidInitTableKB, + Property, + GNB_TABLE_FLAGS_FORCE_S3_SAVE, + StdHeader + ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbHandle = GnbGetNextHandle (GnbHandle); + } + + GnbPciAddress = GnbGetHostPciAddress (GnbGetHandle (StdHeader)); + GnbLibPciIndirectWriteField ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x0F_ADDRESS, + D0F0xFC_x0F_GBIFExtIntrGrp_OFFSET, + D0F0xFC_x0F_GBIFExtIntrGrp_WIDTH, + 5, + AccessS3SaveWidth32, + StdHeader + ); + + GnbLibPciIndirectWriteField ( + GnbPciAddress.AddressValue | D0F0xF8_ADDRESS, + D0F0xFC_x0F_ADDRESS, + D0F0xFC_x0F_GBIFExtIntrSwz_OFFSET, + D0F0xFC_x0F_GBIFExtIntrSwz_WIDTH, + 0, + AccessS3SaveWidth32, + StdHeader + ); + + Status = GnbLclkDpmInitKB (StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c new file mode 100644 index 0000000000..ce6eda2b09 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c @@ -0,0 +1,120 @@ +/** + * @file + * + * GNB post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbGfxConfig.h" +#include "GnbGfxInitLibV1.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "GnbPcieConfig.h" +#include "GfxLibV3.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBPOSTINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +GnbPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +GnbPostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + GNB_HANDLE *GnbHandle; + PCI_ADDR GnbPciAddress; + GFX_PLATFORM_CONFIG *Gfx; + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + + Status = GfxLocateConfigData (StdHeader, &Gfx); + ASSERT (Status == AGESA_SUCCESS); + + GnbHandle = GnbGetHandle (StdHeader); + while (GnbHandle != NULL) { + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Status = GnbSetTomV5 (GnbPciAddress, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + GnbHandle = GnbGetNextHandle (GnbHandle); + } + IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c new file mode 100644 index 0000000000..499275bb00 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c @@ -0,0 +1,585 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "GnbSmuInitLibV7.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBREGISTERACCKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define GNB_IGNORED_PARAM 0xFF +#define ORB_WRITE_ENABLE 0x100 +#define IOMMU_L1_WRITE_ENABLE 0x80000000ul +#define IOMMU_L2_WRITE_ENABLE 0x100 + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbRegisterWriteKBDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ); + + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to read all register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value Return value + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterReadKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + PCI_ADDR GnbPciAddress; + + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + + switch (RegisterSpaceType) { + case 0x1: + GnbLibPciRead ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x8: + GnbPciAddress.Address.Function = 2; + GnbLibPciRead ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x6: ///@todo has to be DxFx + GnbLibPciRead ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + case TYPE_D18F2_dct0: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciRead ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case 0x2: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x3: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x4: + { + UINT64 TempData; + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + (Address & (~0x3ull)), + Width, + &TempData, + StdHeader + ); + if ((Address & 0x3) != 0) { + //Non aligned access allowed to fuse block + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + (Address & (~0x3ull)) + 4, + Width, + ((UINT32 *) &TempData) + 1, + StdHeader + ); + } + * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8)); + break; + } + case 0x22: + // D0F0xD0 Link Index Address, access D0F0xD4_x[0130_14BF:0109_0000] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | 0xD0, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x5: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | D0F0xE0_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x9: + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | 0xF0, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0xa: + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectRead ( + GnbPciAddress.AddressValue | 0xF8, + Address, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrRead (Address, Value, StdHeader); + break; + + case 0x12: + ASSERT (Address < 0x40000); + // SRBM + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + break; + + default: + ASSERT (FALSE); + break; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to write all register spaces. + * + * + * @param[in] GnbHandle GnbHandle + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset, but PortDevice + * @param[out] Value The value to write + * @param[in] Flags Flags - BIT0 indicates S3 save/restore + * @param[in] StdHeader Standard configuration header + */ +AGESA_STATUS +GnbRegisterWriteKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + ACCESS_WIDTH Width; + UINT32 TempValue; + UINT32 TempAddress; + PCI_ADDR GnbPciAddress; + DEV_OBJECT DevObject; + + GnbPciAddress = GnbGetHostPciAddress (GnbHandle); + Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + TempAddress = 0; + TempValue = 0; + + GNB_DEBUG_CODE ( + GnbRegisterWriteKBDump (RegisterSpaceType, Address, Value); + ); + + switch (RegisterSpaceType) { + case 0x1: + GnbLibPciWrite ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x8: + GnbPciAddress.Address.Function = 2; + GnbLibPciWrite ( + GnbPciAddress.AddressValue | Address, + Width, + Value, + StdHeader + ); + break; + case 0x6: /// @todo needs to be DxFx + GnbLibPciWrite ( + Address, + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 0, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F1: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 1, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F2: + case TYPE_D18F2_dct0: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 2, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F3: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 3, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F4: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 4, Address), + Width, + Value, + StdHeader + ); + break; + case TYPE_D18F5: + GnbLibPciWrite ( + MAKE_SBDFO (0, 0, 0x18, 5, Address), + Width, + Value, + StdHeader + ); + break; + + case 0x2: + // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0x60_ADDRESS, + Address | IOC_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case 0x3: + // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0x94_ADDRESS, + Address | ORB_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case 0x4: + //SMU, access D0F0xBC_x[FFFFFFFF:00000000] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x22: + // D0F0xD0 Link Index Address, access D0F0xD4_x[0130_14BF:0109_0000] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | 0xD0, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x5: + // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000] + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | D0F0xE0_ADDRESS, + Address, + Width, + Value, + StdHeader + ); + break; + + case 0x9: + // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00]. + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | 0xF0, + Address | IOMMU_L2_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case 0xa: + GnbPciAddress.Address.Function = 2; + GnbLibPciIndirectWrite ( + GnbPciAddress.AddressValue | 0xF8, + Address | IOMMU_L1_WRITE_ENABLE, + Width, + Value, + StdHeader + ); + break; + + case TYPE_MSR: + LibAmdMsrWrite (Address, Value, StdHeader); + break; + + case 0x12: + ASSERT (Address < 0x40000); + // SRBM + GnbLibPciIndirectWrite ( + MAKE_SBDFO (0, 0, 0, 0, 0xB8), + (0x80080000 | (Address & 0x3FFFF)), + Width, + Value, + StdHeader + ); + break; + + case TYPE_SMU_MSG: + DevObject.StdHeader = StdHeader; + DevObject.GnbHandle = GnbGetHandle (StdHeader); + DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); + GnbSmuServiceRequestV7 (&DevObject, (UINT8) Address, *((UINT32 *)Value), Flags); + break; + + default: + ASSERT (FALSE); + break; + } + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/* + * Routine to dump all write register spaces. + * + * + * + * @param[in] RegisterSpaceType Register space type + * @param[in] Address Register offset + * @param[in] Value The value to write + */ +VOID +GnbRegisterWriteKBDump ( + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value + ) +{ + IDS_HDT_CONSOLE (NB_MISC, " R WRITE Space %s Address 0x%04x, Value 0x%04x\n", + (RegisterSpaceType == 0x1) ? "0x1" : ( + (RegisterSpaceType == 0x2) ? "0x2" : ( + (RegisterSpaceType == 0x3) ? "0x3" : ( + (RegisterSpaceType == 0x4) ? "0x4" : ( + (RegisterSpaceType == 0x22) ? "0x22" : ( + (RegisterSpaceType == 0x5) ? "0x5" : ( + (RegisterSpaceType == 0x6) ? "0x6" : ( + (RegisterSpaceType == TYPE_D18F0) ? "TYPE_D18F0" : ( + (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : ( + (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : ( + (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : ( + (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : ( + (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : ( + (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : ( + (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : ( + (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : ( + (RegisterSpaceType == 0x12) ? "0x12" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : ( + (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : ( + (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : ( + (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : ( + (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))), + Address, + *((UINT32*)Value) + ); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h new file mode 100644 index 0000000000..326c0b32f5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.h @@ -0,0 +1,68 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Various register access service procedures + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _GNBREGISTERACCKB_H_ +#define _GNBREGISTERACCKB_H_ + +AGESA_STATUS +GnbRegisterWriteKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + IN VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +GnbRegisterReadKB ( + IN GNB_HANDLE *GnbHandle, + IN UINT8 RegisterSpaceType, + IN UINT32 Address, + OUT VOID *Value, + IN UINT32 Flags, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h new file mode 100644 index 0000000000..bed59c0d32 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h @@ -0,0 +1,2103 @@ +/** + * @file + * + * SAMU firmware + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBSAMUPATCHKB_H_ +#define _GNBSAMUPATCHKB_H_ + +UINT8 SamuPatchKB[] = { + 0x9d, + 0xaf, + 0x50, + 0x9, + 0x10, + 0x3, + 0xf6, + 0x5f, + 0x7b, + 0x29, + 0x2d, + 0xe0, + 0x33, + 0xbd, + 0x76, + 0x53, + 0x0, + 0x4, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x83, + 0x4f, + 0x17, + 0x8e, + 0x1f, + 0x7e, + 0x2, + 0xbb, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3, + 0x0, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x4, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x80, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0xf7, + 0x11, + 0xbd, + 0x4f, + 0x87, + 0x69, + 0x32, + 0x50, + 0x1, + 0x9, + 0x10, + 0x0, + 0x1, + 0x0, + 0x0, + 0x0, + 0x8a, + 0x38, + 0x2f, + 0xed, + 0x4d, + 0x1c, + 0x95, + 0x9f, + 0xe2, + 0x0, + 0xc0, + 0x45, + 0x50, + 0xe2, + 0x8, + 0xd2, + 0x9a, + 0xe1, + 0xca, + 0x4d, + 0xd0, + 0xb3, + 0xf1, + 0x3f, + 0x43, + 0x6a, + 0x12, + 0x54, + 0xfb, + 0x99, + 0x99, + 0xf9, + 0x4e, + 0x63, + 0xae, + 0x61, + 0x75, + 0x6a, + 0x90, + 0xf6, + 0x43, + 0xab, + 0xf8, + 0xd4, + 0x69, + 0x4d, + 0xe1, + 0x54, + 0x8e, + 0x68, + 0x9f, + 0x7, + 0x39, + 0x67, + 0xf4, + 0xdc, + 0x25, + 0xcb, + 0x0, + 0x66, + 0x28, + 0x4b, + 0xe5, + 0xdc, + 0x62, + 0x5a, + 0xa6, + 0xd6, + 0x1e, + 0xcd, + 0x48, + 0x15, + 0xde, + 0x62, + 0x53, + 0x7a, + 0xf, + 0xdf, + 0x44, + 0x4e, + 0x95, + 0xa6, + 0x82, + 0xa1, + 0x47, + 0x11, + 0x50, + 0x5f, + 0x18, + 0x8c, + 0x94, + 0x13, + 0xb8, + 0x14, + 0x21, + 0x4c, + 0xba, + 0x7b, + 0x4f, + 0x5e, + 0xe2, + 0x9, + 0x74, + 0x7e, + 0x71, + 0x21, + 0x74, + 0xd2, + 0xb2, + 0xc3, + 0xa8, + 0xa6, + 0x41, + 0x83, + 0x30, + 0xaa, + 0xf3, + 0x88, + 0x7b, + 0x16, + 0xfc, + 0xe5, + 0xe9, + 0x6f, + 0x9a, + 0xdf, + 0x7b, + 0x86, + 0x91, + 0xf5, + 0xb6, + 0x4, + 0x9e, + 0x7a, + 0x5, + 0xea, + 0x18, + 0x2e, + 0x7, + 0xc6, + 0x9, + 0x10, + 0xc5, + 0x1e, + 0xf, + 0x51, + 0x84, + 0x27, + 0x80, + 0x8d, + 0xa3, + 0x0, + 0x2d, + 0x53, + 0x6a, + 0xaa, + 0xad, + 0x2e, + 0x1e, + 0x33, + 0x6a, + 0x3d, + 0x72, + 0x16, + 0x34, + 0x9f, + 0x5f, + 0x33, + 0x70, + 0xe2, + 0x85, + 0xb7, + 0xbe, + 0xdf, + 0x59, + 0xd0, + 0xbc, + 0x7b, + 0xc0, + 0x1f, + 0x8e, + 0xc4, + 0x25, + 0xb5, + 0xe3, + 0x88, + 0x60, + 0x20, + 0x73, + 0x44, + 0x17, + 0x2f, + 0x0, + 0x2b, + 0xa5, + 0xea, + 0x4d, + 0x9, + 0xa5, + 0x42, + 0x95, + 0x23, + 0xb9, + 0x1e, + 0x1, + 0xe8, + 0xf7, + 0x7c, + 0x9f, + 0xbe, + 0xb0, + 0x85, + 0xf4, + 0x18, + 0xa9, + 0xf2, + 0x87, + 0x84, + 0x73, + 0xc2, + 0xfe, + 0x9a, + 0x8c, + 0xbb, + 0x9d, + 0x36, + 0x8d, + 0x2e, + 0x94, + 0xc1, + 0x6c, + 0x5f, + 0xc4, + 0x3, + 0x77, + 0x60, + 0x64, + 0x70, + 0x65, + 0x45, + 0x8, + 0x89, + 0xf9, + 0x4f, + 0x76, + 0x25, + 0x79, + 0x1b, + 0x2a, + 0x46, + 0x4b, + 0xfb, + 0x1b, + 0xed, + 0x32, + 0x16, + 0x6d, + 0x3c, + 0x65, + 0xbb, + 0xc4, + 0xe7, + 0xdd, + 0xf2, + 0xd1, + 0x13, + 0x84, + 0x9a, + 0x5f, + 0x71, + 0x15, + 0x6d, + 0x46, + 0x3, + 0x14, + 0xbc, + 0x54, + 0x17, + 0x3a, + 0x12, + 0x3a, + 0x8, + 0xe6, + 0x9c, + 0xff, + 0xb3, + 0x13, + 0xfd, + 0x37, + 0x17, + 0xb6, + 0x79, + 0x6, + 0x56, + 0x9d, + 0xd1, + 0xb7, + 0x57, + 0x33, + 0x3a, + 0x85, + 0xbc, + 0xb2, + 0xd6, + 0x47, + 0x71, + 0x79, + 0xa1, + 0xf8, + 0xf4, + 0x97, + 0xc6, + 0x67, + 0x6e, + 0xe6, + 0xa7, + 0x7e, + 0xfe, + 0x81, + 0xb5, + 0x6a, + 0x97, + 0xd0, + 0x3e, + 0x4e, + 0x7c, + 0x20, + 0xac, + 0xb, + 0x28, + 0xde, + 0x5e, + 0x73, + 0x9c, + 0xb3, + 0x28, + 0xd6, + 0xa0, + 0xd, + 0x6e, + 0x41, + 0x2b, + 0x82, + 0xa8, + 0xb9, + 0x45, + 0x3d, + 0x5d, + 0xd7, + 0xa, + 0xa6, + 0x16, + 0xcd, + 0xfb, + 0x6a, + 0x63, + 0xab, + 0x50, + 0x4c, + 0x2, + 0xce, + 0x4b, + 0xbf, + 0xac, + 0x68, + 0x24, + 0x5b, + 0x56, + 0xc0, + 0x72, + 0xe6, + 0x63, + 0x0, + 0xff, + 0x71, + 0xbd, + 0x4a, + 0x0, + 0x8b, + 0xff, + 0xff, + 0x2b, + 0xe1, + 0x89, + 0xb0, + 0xd1, + 0x8c, + 0x15, + 0x74, + 0xe9, + 0xef, + 0x5b, + 0x88, + 0xe4, + 0x6e, + 0x94, + 0x52, + 0x66, + 0xcb, + 0xcf, + 0x77, + 0x7f, + 0xb, + 0xc0, + 0x88, + 0x99, + 0x9f, + 0xce, + 0xbe, + 0xf3, + 0xf0, + 0x9d, + 0x42, + 0xe, + 0x8f, + 0x63, + 0x7c, + 0x2, + 0x6f, + 0x7, + 0x2, + 0xb1, + 0x91, + 0xbe, + 0xdc, + 0x28, + 0xc8, + 0x1d, + 0x1c, + 0xfb, + 0xb, + 0xcf, + 0x96, + 0x73, + 0x56, + 0x70, + 0x10, + 0xdc, + 0x41, + 0xad, + 0x15, + 0x70, + 0xab, + 0x4d, + 0x81, + 0x7, + 0x1c, + 0x9a, + 0x31, + 0x1, + 0x2a, + 0xd3, + 0x9e, + 0x3d, + 0x3f, + 0x8c, + 0x88, + 0x38, + 0xc9, + 0xb5, + 0xbe, + 0xaa, + 0x3f, + 0x83, + 0x14, + 0xdc, + 0xc2, + 0x90, + 0x37, + 0x7, + 0xc5, + 0x49, + 0xf3, + 0x3a, + 0xe8, + 0x2d, + 0xc5, + 0xd8, + 0xa9, + 0x4, + 0x54, + 0x21, + 0x32, + 0x76, + 0xd2, + 0x13, + 0x42, + 0x58, + 0x9e, + 0xa7, + 0x36, + 0xfd, + 0xf3, + 0xd1, + 0x42, + 0x69, + 0xe1, + 0x58, + 0x9b, + 0xec, + 0xe9, + 0x4e, + 0x3e, + 0xdf, + 0x3b, + 0x9b, + 0x72, + 0x82, + 0xfc, + 0x7e, + 0xdf, + 0x74, + 0x14, + 0xa7, + 0x2a, + 0xbf, + 0x75, + 0xa5, + 0xb0, + 0xee, + 0x79, + 0xd0, + 0xc4, + 0x3e, + 0xbc, + 0xdc, + 0xc6, + 0xb, + 0xeb, + 0xf6, + 0x6e, + 0x95, + 0xda, + 0x9e, + 0x57, + 0xb5, + 0xc6, + 0xa8, + 0x8d, + 0x79, + 0xf8, + 0xbf, + 0xa9, + 0x79, + 0x96, + 0x2c, + 0x29, + 0x64, + 0x2c, + 0x32, + 0x94, + 0x89, + 0x17, + 0x30, + 0x1a, + 0x4e, + 0x7e, + 0x8d, + 0xfc, + 0x40, + 0xee, + 0x39, + 0x9e, + 0x13, + 0x56, + 0x25, + 0xe1, + 0xd3, + 0x3, + 0x95, + 0x6a, + 0x69, + 0x48, + 0x47, + 0xf8, + 0x5e, + 0x2f, + 0x9f, + 0xcd, + 0x1f, + 0xcb, + 0x35, + 0xbf, + 0x90, + 0x70, + 0x75, + 0xff, + 0x7d, + 0x4e, + 0xa8, + 0x0, + 0xed, + 0x3, + 0xee, + 0xce, + 0x83, + 0x2d, + 0xca, + 0x75, + 0xad, + 0x82, + 0x94, + 0x86, + 0xec, + 0x58, + 0x4, + 0x8f, + 0x6c, + 0x34, + 0x89, + 0x8, + 0xac, + 0x53, + 0x74, + 0x8c, + 0xf1, + 0x8a, + 0xf9, + 0x55, + 0x31, + 0xaf, + 0xb7, + 0x9, + 0xd8, + 0x66, + 0x5, + 0xa0, + 0xe2, + 0x84, + 0x8e, + 0x21, + 0x35, + 0xb0, + 0x66, + 0x87, + 0x40, + 0xd0, + 0xbd, + 0xf3, + 0x6e, + 0x57, + 0xf5, + 0x7e, + 0x3a, + 0xe4, + 0x6f, + 0x8d, + 0x8c, + 0xfb, + 0x45, + 0x36, + 0x53, + 0xd3, + 0xf7, + 0x32, + 0xd5, + 0x21, + 0xb, + 0x81, + 0xe0, + 0x7, + 0xc9, + 0x68, + 0xc4, + 0x93, + 0x59, + 0x7a, + 0xcb, + 0xad, + 0x65, + 0xb7, + 0x66, + 0x84, + 0x2f, + 0x3b, + 0x9f, + 0xe7, + 0x43, + 0x11, + 0x36, + 0xa5, + 0x36, + 0x77, + 0x32, + 0xbd, + 0x1d, + 0x7d, + 0x49, + 0x61, + 0x79, + 0x88, + 0x2d, + 0x8e, + 0x41, + 0xec, + 0x14, + 0x31, + 0xf9, + 0xaa, + 0x97, + 0x1a, + 0x39, + 0x6a, + 0xb3, + 0xe8, + 0xdb, + 0x57, + 0xd4, + 0x6d, + 0xed, + 0xa6, + 0x2a, + 0x3c, + 0xba, + 0x7, + 0x8a, + 0x22, + 0x5f, + 0xa7, + 0xc3, + 0xa1, + 0x3, + 0x86, + 0xa8, + 0xa, + 0x12, + 0x0, + 0x1f, + 0xd0, + 0x1a, + 0xc7, + 0x5d, + 0xdf, + 0x51, + 0xad, + 0x2e, + 0xf6, + 0x1e, + 0xb7, + 0xb2, + 0x1f, + 0x40, + 0x76, + 0x72, + 0xf0, + 0x6, + 0x4a, + 0x1f, + 0x69, + 0x3, + 0xc5, + 0x7f, + 0x93, + 0x5c, + 0x31, + 0x6e, + 0x8b, + 0x3a, + 0xc7, + 0x46, + 0xc5, + 0xe3, + 0x8b, + 0x9d, + 0xf4, + 0x79, + 0x6d, + 0x2e, + 0x7f, + 0x45, + 0x5c, + 0x9e, + 0x2d, + 0xec, + 0xe8, + 0x91, + 0xd0, + 0x37, + 0xc7, + 0xba, + 0x73, + 0x87, + 0x79, + 0x8a, +}; + +UINT32 SamuPatchKBHeader[] = { + 0x53414d55, + 0x410 +}; + +UINT8 SamuPatchKBUnf1[] = { + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0xe8, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 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0x0, + 0x1, + 0x34, + 0xb0, + 0x0, + 0x20, + 0xd0, + 0x3, + 0x0, + 0x81, + 0x7c, + 0x8, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x12, + 0x58, + 0xbc, + 0xff, + 0x0, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x9, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0x41, + 0xb8, + 0xf0, + 0x2, + 0x60, + 0xd0, + 0x18, + 0x0, + 0x0, + 0xe0, + 0x2, + 0x0, + 0x81, + 0x7c, + 0x8, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x12, + 0x50, + 0xbc, + 0x0, + 0xff, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x9, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0x41, + 0xb8, + 0xd0, + 0x2, + 0x60, + 0xd0, + 0xf, + 0x0, + 0x0, + 0xe0, + 0x1, + 0x0, + 0x81, + 0x7c, + 0x8, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x12, + 0x48, + 0xbc, + 0xff, + 0xff, + 0x1, + 0x78, + 0xff, + 0x0, + 0x21, + 0x38, + 0x80, + 0x9, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0x41, + 0xb8, + 0xb0, + 0x2, + 0x60, + 0xd0, + 0x6, + 0x0, + 0x0, + 0xe0, + 0x5, + 0x0, + 0x80, + 0x5c, + 0x0, + 0xff, + 0x1, + 0x34, + 0x80, + 0x29, + 0xa1, + 0xa0, + 0x0, + 0x28, + 0xa2, + 0xb8, + 0x90, + 0x2, + 0x60, + 0xd0, + 0xb0, + 0x0, + 0xa0, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x10, + 0x20, + 0xb8, + 0x3, + 0x0, + 0x21, + 0x7c, + 0x4, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x0, + 0x1, + 0x34, + 0xf0, + 0x2, + 0x20, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x41, + 0x7c, + 0x4, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x0, + 0x1, + 0x34, + 0xd0, + 0x2, + 0x20, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x1, + 0x0, + 0x41, + 0x7c, + 0x4, + 0x0, + 0x20, + 0x5c, + 0x0, + 0x0, + 0x1, + 0x34, + 0xb0, + 0x2, + 0x20, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x40, + 0x5c, + 0x90, + 0x2, + 0x40, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x10, + 0x20, + 0xb8, + 0xb0, + 0x0, + 0x60, + 0x90, + 0x3, + 0x0, + 0x21, + 0x7c, + 0x6, + 0x0, + 0x20, + 0x5c, + 0xff, + 0x0, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x41, + 0x7c, + 0x6, + 0x0, + 0x20, + 0x5c, + 0x0, + 0xff, + 0x1, + 0x78, + 0xff, + 0xff, + 0x21, + 0x38, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x1, + 0x0, + 0x41, + 0x7c, + 0x6, + 0x0, + 0x20, + 0x5c, + 0xff, + 0xff, + 0x1, + 0x78, + 0xff, + 0x0, + 0x21, + 0x38, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x4, + 0x0, + 0x40, + 0x5c, + 0x0, + 0xff, + 0x1, + 0x34, + 0x80, + 0x19, + 0x61, + 0xa0, + 0xb0, + 0x0, + 0x60, + 0xd0, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x8, + 0xa0, + 0xbb, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x0, + 0x10, + 0x20, + 0xb8, + 0xff, + 0xff, + 0x42, + 0x34, + 0xff, + 0xff, + 0x41, + 0x64, + 0xfe, + 0xff, + 0x20, + 0x44, + 0x0, + 0x0, + 0xa0, + 0xc3, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x41, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x1, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0xd8, + 0x20, + 0x21, + 0x38, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0xd8, + 0x20, + 0x21, + 0x38, + 0x2, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x74, + 0x20, + 0x21, + 0x38, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x38, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x0, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x41, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x0, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x1, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0xff, + 0x1, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x0, + 0x20, + 0x21, + 0x38, + 0x25, + 0x1, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x2, + 0x0, + 0x1, + 0x78, + 0x4, + 0x20, + 0x21, + 0x38, + 0x1, + 0x0, + 0x2, + 0x34, + 0x3, + 0x0, + 0x41, + 0xcc, + 0x0, + 0x0, + 0x0, + 0xe0, +}; + +UINT32 SamuPatchKBHeaderUnf1[] = { + 0x53414d55, + 0x3e8 +}; +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h new file mode 100644 index 0000000000..62736a3a20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h @@ -0,0 +1,32414 @@ +/** + * @file + * + * SMU firmware + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87932 $ @e \$Date: 2013-02-13 13:53:55 -0600 (Wed, 13 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBSMUFIRMWAREKB_H_ +#define _GNBSMUFIRMWAREKB_H_ + +UINT32 FirmwareKBHeader [] = { + 0x554D535F, + 0x554D535F, + 0x0001F984, + 0x00002000, + 0x00010000, + 0xECE28940, + 0x0000424B, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +UINT32 FirmwareKB[] = { + 0x63c00f17, + 0xb9cfd803, + 0x196410db, + 0x8c378d8b, + 0xa8f232ce, + 0x000c0d00, + 0x00000100, + 0x00000000, + 0x00020100, + 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0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00002710, + 0x000003e8, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K + SMU_FIRMWARE_PADS_1K +}; +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c new file mode 100644 index 0000000000..5c1fef2c20 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c @@ -0,0 +1,499 @@ +/** + * @file + * + * GNB init tables + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 86714 $ @e \$Date: 2013-01-24 17:51:46 -0600 (Thu, 24 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbCommonLib.h" +#include "GnbTable.h" +#include "GnbRegistersKB.h" +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuKB [] = { + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_SMUCsrIsocEn_MASK, + (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x1E_TYPE, + D0F0x98_x1E_ADDRESS, + D0F0x98_x1E_HiPriEn_MASK, + (1 << D0F0x98_x1E_HiPriEn_OFFSET) + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEarlyInitTableKB [] = { + // Set SVI2 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_SVI2, + 0x4, + 0x3F9D8, + 0x20000000, + (1 << 29) + ), + GNB_ENTRY_WR ( + D0F0x04_TYPE, + D0F0x04_ADDRESS, + (0x1 << D0F0x04_MemAccessEn_WIDTH) + ), + GNB_ENTRY_RMW ( + D0F0x64_x16_TYPE, + D0F0x64_x16_ADDRESS, + D0F0x64_x16_AerUrMsgEn_MASK, + 0x0 << D0F0x64_x16_AerUrMsgEn_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK, + (1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + ), + + GNB_ENTRY_RMW ( + D0F0x98_x0C_TYPE, + D0F0x98_x0C_ADDRESS, + D0F0x98_x0C_GcmWrrLenA_MASK | D0F0x98_x0C_GcmWrrLenB_MASK, + (0x8 << D0F0x98_x0C_GcmWrrLenA_OFFSET) | (0x8 << D0F0x98_x0C_GcmWrrLenB_OFFSET) + ), + + // Enable voltage controller + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + SMC_MSG_VOLTAGE_CNTL_ENABLE, + 0 + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_COPY ( + 0x9, + 0x49, + 0, + 32, + D0F0x64_x1F_TYPE, + D0F0x64_x1F_ADDRESS, + 0, + 32 + ), + // Enable VPC + // CSR_GNB_1.SviTrimValueVdd = Vdd Trim + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F4, + 16, 8, + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH + ), + // CSR_GNB_1.SviTrimValueVddNB = VddNB Trim + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F4, + 24, 8, + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH + ), + // CSR_GNB_3.SviLoadLineOffsetVdd = Vdd Offset + + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F8, + 0, 8, + D18F5x12C_TYPE, + D18F5x12C_ADDRESS, + D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH + ), + // CSR_GNB_3.SviLoadLineOffsetVddNB = VddNB Offset + GNB_ENTRY_COPY ( + 0x4, + 0x3F9F8, + 8, 8, + D18F5x188_TYPE, + D18F5x188_ADDRESS, + D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH + ), + + // Set SRBM time out + GNB_ENTRY_RMW ( + 0x12, + 0xE40, + 0x1FFF, + (0x1FFF << 0) + ), + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbEnvInitTableKB [] = { + //--------------------------------------------------------------------------- + + // SMU Enable Thermal Controller + GNB_ENTRY_WR ( + SMU_MSG_TYPE, + 56, + 0 + ), + // Enable VPC + GNB_ENTRY_PROPERTY_RMW ( + 0x00040000ul, + 0x4, + 0x3F9D8, + 0x1, + (1 << 0) + ), + // Enable LHTC + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_LHTC, + SMU_MSG_TYPE, + 70, + 0 + ), + GNB_ENTRY_PROPERTY_WR ( + 0x00040000ul, + SMU_MSG_TYPE, + SMC_MSG_CONFIG_VPC_ACCUMULATOR, + 0 + ), + + // PM_CONFIG.f.enable_tdc_limit = 1; + GNB_ENTRY_PROPERTY_RMW ( + 0x00040000ul, + 0x4, + 0x3F9D8, + 0x4, + (1 << 2) + ), + GNB_ENTRY_PROPERTY_WR ( + 0x00040000ul, + SMU_MSG_TYPE, + 46, + 0 + ), + + // Enable Package Power Limit + GNB_ENTRY_PROPERTY_WR ( + 0x00080000ul, + SMU_MSG_TYPE, + SMC_MSG_ENABLE_PKGPWRLIMIT, + 0 + ), + + // Enable BAPM + // PM_CONFIG.f.enable_bapm = 1; + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_BAPM, + 0x4, + 0x3F9D8, + 0x2, + (1 << 1) + ), + GNB_ENTRY_PROPERTY_WR ( + TABLE_PROPERTY_BAPM, + SMU_MSG_TYPE, + 48, + 0 + ), +//--------------------------------------------------------------------------- +// ORB Init + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK, + (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x07_TYPE, + D0F0x98_x07_ADDRESS, + D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK | D0F0x98_x07_DmaReqRespPassPWMode_MASK, + (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) | (0 << D0F0x98_x07_DmaReqRespPassPWMode_OFFSET) + ), + GNB_ENTRY_RMW ( + D0F0x98_x08_TYPE, + D0F0x98_x08_ADDRESS, + D0F0x98_x08_NpWrrLenC_MASK, + 0x1 << D0F0x98_x08_NpWrrLenC_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x28_TYPE, + D0F0x98_x28_ADDRESS, + D0F0x98_x28_ForceCoherentIntr_MASK, + 0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET + ), + GNB_ENTRY_RMW ( + D0F0x98_x2C_TYPE, + D0F0x98_x2C_ADDRESS, + D0F0x98_x2C_SBDmaActiveMask_MASK | D0F0x98_x2C_CgttLclkOverride_MASK, + (1 << D0F0x98_x2C_SBDmaActiveMask_OFFSET) | (1 << D0F0x98_x2C_CgttLclkOverride_OFFSET) + ), + // Enable gBIF UID Clumping [BIT 23:21 = 011b] + GNB_ENTRY_RMW ( + D0F0x98_x3A_TYPE, + D0F0x98_x3A_ADDRESS, + 0x00E00000, + 0x00600000 + ), + GNB_ENTRY_RMW ( + D18F0x110_TYPE, + D18F0x110_ADDRESS, + 0x00E00000, + 0x00600000 + ), + //NB P-state Configuration for Runtime + GNB_ENTRY_RMW ( + 0x4, + 0x3F9E8, + 0xFF | 0xFF00 | + 0xFF0000 | 0xFF000000, + (3 << 0) | (0 << 8) | + (2 << 16) | (1 << 24) + ), + // Programming a conservative watermark for NBP states + GNB_ENTRY_RMW ( + 0x12, + 0x6cd8, + 0x10 | + 0x100 | + 0xffff0000, + (1 << 4) | + (1 << 8) | + (0x7FFF << 16) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cc8, + 0x3 | + 0x30000, + (0x3 << 0) | + (0x3 << 16) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cd4, + 0xffff0000, + (0x7FFF << 16) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cd4, + 0x1, + (1 << 0) + ), + + GNB_ENTRY_RMW ( + 0x12, + 0x6cd8, + 0x1, + (1 << 0) + ), + + GNB_ENTRY_TERMINATE +}; + +GNB_TABLE ROMDATA GnbMidInitTableKB [] = { +//--------------------------------------------------------------------------- +// ORB clock gating + GNB_ENTRY_PROPERTY_RMW ( + 0x00000008ul, + D0F0x98_x49_TYPE, + D0F0x98_x49_ADDRESS, + D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000008ul, + D0F0x98_x4A_TYPE, + D0F0x98_x4A_ADDRESS, + D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000008ul, + D0F0x98_x2C_TYPE, + D0F0x98_x2C_ADDRESS, + D0F0x98_x2C_CgttLclkOverride_MASK, + 0x0 + ), +//--------------------------------------------------------------------------- +// IOC clock gating + GNB_ENTRY_PROPERTY_RMW ( + 0x00000010ul, + D0F0x64_x22_TYPE, + D0F0x64_x22_ADDRESS, + 0x4000000 | 0x8000000 | 0x10000000 | 0x20000000 | 0x40000000, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000010ul, + D0F0x64_x23_TYPE, + D0F0x64_x23_ADDRESS, + 0x4000000 | 0x8000000 | 0x10000000 | 0x20000000 | 0x40000000, + 0x0 + ), + GNB_ENTRY_PROPERTY_RMW ( + 0x00000010ul, + D0F0x64_x46_TYPE, + D0F0x64_x46_ADDRESS, + 0x10000, + 0x0 + ), + //--------------------------------------------------------------------------- + GNB_ENTRY_RMW ( + 0x4, + 0xc0200110, + 0x18 | 0x1 | + 0x2 | 0x200 | + 0x400, + (0x3 << 3) | + (0 << 0) | + (0x0 << 1) | + (0x1 << 9) | + (0x1 << 10) + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + 0x4, + 0xc0200310, + 0x20 | + 0x40 | + 0x80 | + 0x100 | + 0x200 | + 0x400 | + 0x800 | + 0x1000 | + 0x2000 | + 0x4000 | + 0x8000 | + 0x10000 | + 0x20000 | + 0x40000 | + 0x80000 | + 0x100000 | + 0x1 | + 0x2 | + 0x4, + ( 1 << 5) | + ( 0 << 6) | + ( 0 << 7) | + ( 0 << 8) | + ( 0 << 9) | + ( 1 << 10) | + ( 1 << 11) | + ( 1 << 12) | + ( 1 << 13) | + ( 1 << 14) | + ( 1 << 15) | + ( 1 << 16) | + ( 1 << 17) | + ( 1 << 18) | + ( 1 << 19) | + ( 1 << 20) | + ( 1 << 0) | + ( 1 << 1) | + ( 1 << 2) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + 0x4, + 0xc020008c, + 0x7 | + 0x8 | + 0xfff0, + ( 5 << 0) | + ( 0 << 3) | + ( 0xF << 4) + ), + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_IGFX_DISABLED, + 0x4, + 0xc0200310, + 0x200000, + 0x0 + ), +// Reset : 0, Enable : 1 + GNB_ENTRY_PROPERTY_RMW ( + TABLE_PROPERTY_LCLK_DEEP_SLEEP, + 0x4, + 0xc020008c, + 0x80000000, + (0x1 << 31) + ), +//--------------------------------------------------------------------------- + GNB_ENTRY_TERMINATE +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c new file mode 100644 index 0000000000..c5eb8a1dc0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraKB.c @@ -0,0 +1,260 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize PP/DPM fuse table. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcieConfig.h" +#include "GnbCommonLib.h" +#include "GnbUra.h" +#include "GnbUraToken.h" +#include "GnbRegisterAccKB.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBURAKB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GnbUraGetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +VOID +GnbUraSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ); + +VOID +GnbUraStreamSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Pointer to Device object + * @param[in] UraTokenInfo Pointer to URA_TOKEN_INFO structure + * @param[in, out] Value Pointer to Context + */ +VOID +GnbUraGetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ) +{ + ACCESS_WIDTH Width; + UINT32 RegValue; + UINT32 FieldMask; + UINT32 TargetAddress; + + RegValue = 0; + Width = (UraTokenInfo->Flags == GNB_URA_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + switch (UraTokenInfo->MethodType) { + case TYPE_GNB_INDIRECT_ACCESS: + TargetAddress = Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType; + GnbLibPciIndirectRead ( TargetAddress, UraTokenInfo->RegAddress, Width, &RegValue, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura GET: RegDomainType = 0x%x IndirectAddress = 0x%08x, Value = 0x%08x\n", UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, RegValue); + break; + + case TYPE_GNB_PROTOCOL_ACCESS: + TargetAddress = UraTokenInfo->RegDomainType; + GnbRegisterReadKB (Device->GnbHandle, (UINT8)TargetAddress, UraTokenInfo->RegAddress, &RegValue, UraTokenInfo->Flags, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura GET: RegDomainType = %d, Address = 0x%08x, Value = 0x%08x\n", TargetAddress, UraTokenInfo->RegAddress, RegValue); + break; + + default: + ASSERT (FALSE); + return; + } + + if (UraTokenInfo->WholeRegAccess == TRUE) { + *(UINT32 *)Value = RegValue; + } else { + RegValue = RegValue >> UraTokenInfo->BfOffset; + FieldMask = (((UINT32)1 << UraTokenInfo->BfWidth) - 1); + *(UINT32 *)Value = RegValue & FieldMask; + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Pointer to Device object + * @param[in] UraTokenInfo Pointer to URA_TOKEN_INFO structure + * @param[in, out] Value Pointer to Context + */ +VOID +GnbUraSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT VOID *Value + ) +{ + ACCESS_WIDTH Width; + UINT32 RegValue; + UINT32 TargetValue; + UINT32 FieldMask; + UINT32 TempValue; + + Width = (UraTokenInfo->Flags == GNB_URA_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + FieldMask = 0; + TempValue = *(UINT32 *)Value; + + switch (UraTokenInfo->MethodType) { + case TYPE_GNB_INDIRECT_ACCESS: + if (UraTokenInfo->WholeRegAccess == TRUE) { + TargetValue = TempValue; + } else { + GnbLibPciIndirectRead ( Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, Width, &RegValue, Device->StdHeader); + FieldMask = (((UINT32)1 << UraTokenInfo->BfWidth) - 1); + TargetValue = RegValue & (~(FieldMask << UraTokenInfo->BfOffset)); + TargetValue |= (TempValue & FieldMask) << UraTokenInfo->BfOffset; + } + GnbLibPciIndirectWrite ( Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, Width, &TargetValue, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura SET: RegDomainType = 0x%x IndirectAddress = 0x%08x, Value = 0x%08x\n", UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, TargetValue); + break; + + case TYPE_GNB_PROTOCOL_ACCESS: + if (UraTokenInfo->WholeRegAccess == TRUE) { + TargetValue = TempValue; + } else { + GnbRegisterReadKB (Device->GnbHandle, UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, &RegValue, UraTokenInfo->Flags, Device->StdHeader); + FieldMask = (((UINT32)1 << UraTokenInfo->BfWidth) - 1); + TargetValue = RegValue & (~(FieldMask << UraTokenInfo->BfOffset)); + TargetValue |= (TempValue & FieldMask) << UraTokenInfo->BfOffset; + } + GnbRegisterWriteKB (Device->GnbHandle, UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, &TargetValue, UraTokenInfo->Flags, Device->StdHeader); + IDS_HDT_CONSOLE (NB_MISC, " Ura SET: RegDomainType = %d, Address = 0x%08x, Value = 0x%08x\n", UraTokenInfo->RegDomainType, UraTokenInfo->RegAddress, TargetValue); + break; + + default: + ASSERT (FALSE); + break; + } + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method + * + * + * @param[in] Device Pointer to device object + * @param[in] UraTokenInfo Pointer to URA_TOKEN_INFO structure + * @param[in, out] UraTuple Pointer to structure URA_TUPLE + * @param[in] CombinedCount Token count + */ +VOID +GnbUraStreamSetKB ( + IN DEV_OBJECT *Device, + IN URA_TOKEN_INFO *UraTokenInfo, + IN OUT URA_TUPLE *UraTuple, + IN UINT32 CombinedCount + ) +{ + ACCESS_WIDTH Width; + UINT32 RegValue; + UINT32 Index; + UINT32 StreamSetAddress; + UINT32 StepLength; + UINT32 TargetAddress; + + Width = (UraTokenInfo->Flags == GNB_URA_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32; + StreamSetAddress = UraTokenInfo->RegAddress; + StepLength = UraTuple->StepLength; + for (Index = 0; Index < CombinedCount; Index++) { + RegValue = *(((UINT32 *) ((UINTN)UraTuple->Value)) + Index); + switch (UraTokenInfo->MethodType) { + case TYPE_GNB_INDIRECT_ACCESS: + TargetAddress = Device->DevPciAddress.AddressValue | UraTokenInfo->RegDomainType; + //IDS_HDT_CONSOLE (NB_MISC, "0x%08x:0x%08x, \n", StreamSetAddress, RegValue); + GnbLibPciIndirectWrite (TargetAddress, StreamSetAddress, Width, &RegValue, Device->StdHeader); + break; + + case TYPE_GNB_PROTOCOL_ACCESS: + TargetAddress = UraTokenInfo->RegDomainType; + GnbRegisterWriteKB (Device->GnbHandle, (UINT8)TargetAddress, StreamSetAddress, &RegValue, UraTokenInfo->Flags, Device->StdHeader); + break; + + default: + ASSERT (FALSE); + return; + } + StreamSetAddress += StepLength; + } +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c new file mode 100644 index 0000000000..2d75fcee51 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c @@ -0,0 +1,122 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AGESA gnb file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbUra.h" +#include "GnbUraToken.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_GNBURATOKENMAPKB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +VOID +GnbUraLocateRegTblKB ( + IN DEV_OBJECT *Device, + IN OUT UINT32 *UraTableAddress + ); +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +REG_FIELD_TABLE_STRUCT UraTableKB = { + {0xC2100000, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuIntReq ,BfxSmuIntToggle)}, + {1, 16, FIELD_OFFSET(RxSmuIntReq ,BfxSmuServiceIndex)}, + {0xC2100004, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuIntSts ,BfxSmuIntAck)}, + {1, 1, FIELD_OFFSET(RxSmuIntSts ,BfxSmuIntDone)}, + {0xE0003088, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuAuthSts ,BfxSmuAuthDone)}, + {1, 1, FIELD_OFFSET(RxSmuAuthSts ,BfxSmuAuthPass)}, + {0xE00030A4, 0x4, 0}, + {16, 1, FIELD_OFFSET(RxSmuFwAuth ,BfxSmuProtectedMode)}, + {0xC0000004, 0x4, 0}, + {7, 1, FIELD_OFFSET(REG_FIELD_TABLE_STRUCT_fld11 ,BfxSmuBootSeqDone)}, + {0x3F800, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuFwFlags ,BfxSmuInterruptsEnabled)}, + {0x80000000, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuResetCntl ,BfxSmuRstReg)}, + {0x80000004, 0x4, 0}, + {0, 1, FIELD_OFFSET(RxSmuClkCntl ,BfxSmuCkDisable)}, + {0x80008000, 0x4, 0}, + {D0F0xBC_x20000_ADDRESS, D0F0xBC_x20000_TYPE, 0}, + {D0F0xBC_x0_ADDRESS, D0F0xBC_x0_TYPE, 0}, + {D0F0xBC_xC210003C_ADDRESS, D0F0xBC_xC210003C_TYPE, 0}, + +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Gnb Unified Register Access method to locate register table. + * + * + * @param[in] Device Standard configuration header + * @param[in, out] UraTableAddress Ura register table address + */ +VOID +GnbUraLocateRegTblKB ( + IN DEV_OBJECT *Device, + IN OUT UINT32 *UraTableAddress + ) +{ + *UraTableAddress = (UINT32)((UINTN)(&UraTableKB)); + return; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c new file mode 100644 index 0000000000..5fd3cca0eb --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c @@ -0,0 +1,447 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe configuration data + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PcieComplexDataKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIECOMPLEXDATAKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieGetComplexDataLengthKB ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PcieBuildComplexConfigurationKB ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +PcieGetNativePhyLaneBitmapKB ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ); +// +// Complex configuration +// + +KB_COMPLEX_CONFIG ComplexDataKB = { + //Silicon + { + { + DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + 0, + 0, + offsetof (KB_COMPLEX_CONFIG, GppWrapper) - offsetof (KB_COMPLEX_CONFIG, Silicon) + }, + 0, + 0xFF, + 0xFF + }, + //Gpp Wrapper + { + { + DESCRIPTOR_PCIE_WRAPPER, + offsetof (KB_COMPLEX_CONFIG, GppWrapper) - offsetof (KB_COMPLEX_CONFIG, Silicon), + offsetof (KB_COMPLEX_CONFIG, DdiWrapper) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR4) - offsetof (KB_COMPLEX_CONFIG, GppWrapper) + }, + GPP_WRAP_ID, + GPP_NUMBER_OF_PIFs, + GPP_START_PHY_LANE, + GPP_END_PHY_LANE, + GPP_CORE_ID, + GPP_CORE_ID, + GPP_END_PHY_LANE - GPP_START_PHY_LANE + 1, + { + 1, + 1, + 1, + 1, + 1, + 1, + 1 + }, + }, + //Virtual DDI Wrapper + { + { + DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (KB_COMPLEX_CONFIG, DdiWrapper) - offsetof (KB_COMPLEX_CONFIG, Silicon), + 0, + offsetof (KB_COMPLEX_CONFIG, Ddi1) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper) + }, + DDI_WRAP_ID, + 0, + DDI_START_PHY_LANE, + DDI_END_PHY_LANE, + -1, + 0, + 0, + { + 1, + 1, + 1, + 1, + 1, + 0, + 1 + }, + }, +//------------------------------ GPP WRAPPER START------------------------------------- + //Port PBR4 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR4) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR3) - offsetof (KB_COMPLEX_CONFIG, PortPBR4), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 7, + 7, + PBR4_NATIVE_PCI_DEV, + PBR4_NATIVE_PCI_FUN, + PBR4_CORE_ID, + PBR4_PORT_ID, + {(UINT32)PBR4_PCI_ADDRESS}, + LinkStateResetExit, + PBR4, + PBR4_UNIT_ID, + PBR4_NUM_UNIT_IDs + }, + }, + }, + //Port PBR3 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR3) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR2) - offsetof (KB_COMPLEX_CONFIG, PortPBR3), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 6, + 6, + PBR3_NATIVE_PCI_DEV, + PBR3_NATIVE_PCI_FUN, + PBR3_CORE_ID, + PBR3_PORT_ID, + {(UINT32)PBR3_PCI_ADDRESS}, + LinkStateResetExit, + PBR3, + PBR3_UNIT_ID, + PBR3_NUM_UNIT_IDs + }, + }, + }, + //Port PBR2 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR2) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR1) - offsetof (KB_COMPLEX_CONFIG, PortPBR2), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 5, + 5, + PBR2_NATIVE_PCI_DEV, + PBR2_NATIVE_PCI_FUN, + PBR2_CORE_ID, + PBR2_PORT_ID, + {(UINT32)PBR2_PCI_ADDRESS}, + LinkStateResetExit, + PBR2, + PBR2_UNIT_ID, + PBR2_NUM_UNIT_IDs + }, + }, + }, + //Port PBR1 + { + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (KB_COMPLEX_CONFIG, PortPBR1) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, PortPBR0) - offsetof (KB_COMPLEX_CONFIG, PortPBR1), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 4, + 4, + PBR1_NATIVE_PCI_DEV, + PBR1_NATIVE_PCI_FUN, + PBR1_CORE_ID, + PBR1_PORT_ID, + {(UINT32)PBR1_PCI_ADDRESS}, + LinkStateResetExit, + PBR1, + PBR1_UNIT_ID, + PBR1_NUM_UNIT_IDs + }, + }, + }, + //Port PBR0 + { + { + DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (KB_COMPLEX_CONFIG, PortPBR0) - offsetof (KB_COMPLEX_CONFIG, GppWrapper), + offsetof (KB_COMPLEX_CONFIG, Ddi1) - offsetof (KB_COMPLEX_CONFIG, PortPBR0), + 0 + }, + { PciePortEngine, GPP_START_PHY_LANE, GPP_END_PHY_LANE }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 0, + 3, + PBR0_NATIVE_PCI_DEV, + PBR0_NATIVE_PCI_FUN, + PBR0_CORE_ID, + PBR0_PORT_ID, + {(UINT32)PBR0_PCI_ADDRESS}, + LinkStateResetExit, + PBR0, + PBR0_UNIT_ID, + PBR0_NUM_UNIT_IDs + }, + }, + }, +//------------------------------ GPP WRAPPER END ------------------------------------- +//------------------------------ DDI WRAPPER START---------------------------------- + //Ddi1 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + offsetof (KB_COMPLEX_CONFIG, Ddi1) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper), + offsetof (KB_COMPLEX_CONFIG, Ddi2) - offsetof (KB_COMPLEX_CONFIG, Ddi1), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //Ddi2 + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + offsetof (KB_COMPLEX_CONFIG, Ddi2) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper), + offsetof (KB_COMPLEX_CONFIG, Vga) - offsetof (KB_COMPLEX_CONFIG, Ddi2), + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + //Vga + { + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, + offsetof (KB_COMPLEX_CONFIG, Vga) - offsetof (KB_COMPLEX_CONFIG, DdiWrapper), + 0, + 0 + }, + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF //Scratch + }, + { + {0, 0, 0, 0, 0} + } +}; + +// +// PCIe lane allocation GPP +// +UINT8 ROMDATA GppPortLaneConfigurationTableKB [] = { + UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 4, 7, 0, 3, + UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, 4, 5, 0, 3, + UNUSED_LANE_ID, UNUSED_LANE_ID, 7, 7, 6, 6, 4, 5, 0, 3, + 7, 7, 6, 6, 5, 5, 4, 4, 0, 3 +}; + +// +// DDI lane allocation DDI +// +UINT8 ROMDATA DdiLaneConfigurationTableKB [] = { + 0, 3, 4, 7, 8, 11 +}; + +// +// PCIe lane allocation desfriptors +// +PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[] = { + { + 0, + GPP_WRAP_ID, + PciePortEngine, + NUMBER_OF_GPP_PORTS, + sizeof (GppPortLaneConfigurationTableKB) / (NUMBER_OF_GPP_PORTS * 2), + &GppPortLaneConfigurationTableKB[0] + }, + { + DESCRIPTOR_TERMINATE_LIST, + DDI_WRAP_ID, + PcieDdiEngine, + NUMBER_OF_DDI_DDIS, + sizeof (DdiLaneConfigurationTableKB) / (NUMBER_OF_DDI_DDIS * 2), + &DdiLaneConfigurationTableKB[0] + } +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get length of data block for complex + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @param[out] StdHeader Standard configuration header + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieGetComplexDataLengthKB ( + IN UINT8 SocketId, + OUT UINTN *Length, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Length = sizeof (KB_COMPLEX_CONFIG); + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * + * @param[in] SocketId Socket ID. + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieBuildComplexConfigurationKB ( + IN UINT8 SocketId, + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemCopy (Buffer, &ComplexDataKB, sizeof (KB_COMPLEX_CONFIG), StdHeader); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * get native PHY lane bitmap + * + * + * @param[in] PhyLaneBitmap Package PHY lane bitmap + * @param[in] Engine Standard configuration header. + * @retval Native PHY lane bitmap + */ +UINT32 +PcieGetNativePhyLaneBitmapKB ( + IN UINT32 PhyLaneBitmap, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + + return PhyLaneBitmap; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h new file mode 100644 index 0000000000..6663031ec4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.h @@ -0,0 +1,157 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +#ifndef _PCIECOMPLEXDATAKB_H_ +#define _PCIECOMPLEXDATAKB_H_ + +#define MAX_NUM_PHYs 2 +#define MAX_NUM_LANE_PER_PHY 8 + +#define NUMBER_OF_GPP_PORTS 5 +#define NUMBER_OF_DDI_DDIS 3 + +#define NON_INITIALIZED_PCI_ADDRESS 0 + +#define GPP_WRAP_ID 0 +#define GPP_START_PHY_LANE 0 +#define GPP_END_PHY_LANE 7 +#define GPP_CORE_ID 0 +#define GPP_NUMBER_OF_PIFs 1 + +#define DDI_WRAP_ID 3 +#define DDI_START_PHY_LANE 8 +#define DDI_END_PHY_LANE 19 +#define DDI_NUMBER_OF_PIFs 1 + +// PBR0 +#define PBR0 0 +#define PBR0_NATIVE_PCI_DEV 2 +#define PBR0_NATIVE_PCI_FUN 1 +#define PBR0_CORE_ID GPP_CORE_ID +#define PBR0_PORT_ID 0 +#define PBR0_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR0_UNIT_ID 0x4 +#define PBR0_NUM_UNIT_IDs 0x1 + +// PBR1 +#define PBR1 1 +#define PBR1_NATIVE_PCI_DEV 2 +#define PBR1_NATIVE_PCI_FUN 2 +#define PBR1_CORE_ID GPP_CORE_ID +#define PBR1_PORT_ID 1 +#define PBR1_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR1_UNIT_ID 0x5 +#define PBR1_NUM_UNIT_IDs 0x1 + +// PBR2 +#define PBR2 2 +#define PBR2_NATIVE_PCI_DEV 2 +#define PBR2_NATIVE_PCI_FUN 3 +#define PBR2_CORE_ID GPP_CORE_ID +#define PBR2_PORT_ID 2 +#define PBR2_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR2_UNIT_ID 0x6 +#define PBR2_NUM_UNIT_IDs 0x1 + +// PBR3 +#define PBR3 3 +#define PBR3_NATIVE_PCI_DEV 2 +#define PBR3_NATIVE_PCI_FUN 4 +#define PBR3_CORE_ID GPP_CORE_ID +#define PBR3_PORT_ID 3 +#define PBR3_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR3_UNIT_ID 0x7 +#define PBR3_NUM_UNIT_IDs 0x1 + +// PBR4 +#define PBR4 4 +#define PBR4_NATIVE_PCI_DEV 2 +#define PBR4_NATIVE_PCI_FUN 5 +#define PBR4_CORE_ID GPP_CORE_ID +#define PBR4_PORT_ID 4 +#define PBR4_PCI_ADDRESS NON_INITIALIZED_PCI_ADDRESS +#define PBR4_UNIT_ID 0x8 +#define PBR4_NUM_UNIT_IDs 0x1 + +#define MaxDevNum 4 +#define MaxDevFunc 5 + +#define GPP_CORE_x4x4 ((4ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2 ((2ull << 16) | (2ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1 ((1ull << 24) | (1ull << 16) | (2ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) + +///Family specific silicon configuration +typedef struct { + UINT8 PortDevMap [5]; ///< Device number that has beed allocated already +} KB_PCIe_SILICON_CONFIG; + + +/// Complex Configuration for silicon module +typedef struct { + PCIe_SILICON_CONFIG Silicon; ///< Silicon + + PCIe_WRAPPER_CONFIG GppWrapper; ///< GPP Wrapper + PCIe_WRAPPER_CONFIG DdiWrapper; ///< DDI Wrapper + + // GPP + PCIe_ENGINE_CONFIG PortPBR4; ///< Port PBR6 + PCIe_ENGINE_CONFIG PortPBR3; ///< Port PBR5 + PCIe_ENGINE_CONFIG PortPBR2; ///< Port PBR4 + PCIe_ENGINE_CONFIG PortPBR1; ///< Port PBR3 + PCIe_ENGINE_CONFIG PortPBR0; ///< Port PBR2 + + // DDI + PCIe_ENGINE_CONFIG Ddi1; ///< Ddi1 + PCIe_ENGINE_CONFIG Ddi2; ///< Ddi2 + PCIe_ENGINE_CONFIG Vga; ///< Vga + KB_PCIe_SILICON_CONFIG FmSilicon; ///< Fm silicon config +} KB_COMPLEX_CONFIG; + + +VOID +PcieSetPortPciAddressMapKB ( + IN PCIe_SILICON_CONFIG *Silicon + ); +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c new file mode 100644 index 0000000000..bc87ddef3d --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c @@ -0,0 +1,626 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe wrapper configuration services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "PcieComplexDataKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIECONFIGKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define DEVFUNC(d, f) ((((UINT8) d) << 3) | ((UINT8) f)) + +extern PCIe_LANE_ALLOC_DESCRIPTOR ROMDATA PcieLaneAllocConfigurationKB[]; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8* +PcieDebugGetCoreConfigurationStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ); + +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringKB ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ); + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieMapPortPciAddressKB ( + IN PCIe_ENGINE_CONFIG *Engine + ); + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8* +PcieDebugGetWrapperNameStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ); + +AGESA_STATUS +PcieConfigureEnginesLaneAllocationKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +PcieGetCoreConfigurationValueKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ); + +BOOLEAN +PcieCheckPortPciDeviceMappingKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ); + +AGESA_STATUS +PcieGetSbConfigInfoKB ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +// +// Default port dev map +// +UINT8 ROMDATA DefaultPortDevMap [] = { + DEVFUNC (2, 1), + DEVFUNC (2, 2), + DEVFUNC (2, 3), + DEVFUNC (2, 4), + DEVFUNC (2, 5) +}; + +// +// Default apic config +// +APIC_DEVICE_INFO ROMDATA DefaultIoapicConfig [] = { + {0, 0, 0x18}, + {1, 0, 0x19}, + {2, 0, 0x1A}, + {3, 0, 0x1B}, + {4, 0, 0x18} +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] PcieLaneConfig Lane configuration descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ +STATIC AGESA_STATUS +PcieConfigurePcieEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_LANE_ALLOC_DESCRIPTOR *PcieLaneConfig, + IN UINT8 ConfigurationId + ) +{ + UINT8 CoreLaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + + if (ConfigurationId >= PcieLaneConfig->NumberOfConfigurations) { + return AGESA_ERROR; + } + EnginesList = PcieConfigGetChildEngine (Wrapper); + CoreLaneIndex = ConfigurationId * PcieLaneConfig->NumberOfEngines * 2; + + while (EnginesList != NULL) { + if (PcieLibIsPcieEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->Type.Port.StartCoreLane = PcieLaneConfig->ConfigTable[CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = PcieLaneConfig->ConfigTable[CoreLaneIndex++]; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] DdiLaneConfig Lane configuration descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ +STATIC AGESA_STATUS +PcieConfigureDdiEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_LANE_ALLOC_DESCRIPTOR *DdiLaneConfig, + IN UINT8 ConfigurationId + ) +{ + UINTN LaneIndex; + PCIe_ENGINE_CONFIG *EnginesList; + if (ConfigurationId >= DdiLaneConfig->NumberOfConfigurations) { + return AGESA_ERROR; + } + LaneIndex = ConfigurationId * DdiLaneConfig->NumberOfEngines * 2; + EnginesList = PcieConfigGetChildEngine (Wrapper); + while (EnginesList != NULL) { + if (PcieLibIsDdiEngine (EnginesList)) { + PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED); + EnginesList->EngineData.StartLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = DdiLaneConfig->ConfigTable[LaneIndex++] + Wrapper->StartPhyLane; + } + EnginesList = PcieLibGetNextDescriptor (EnginesList); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieConfigureEnginesLaneAllocationKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + PCIe_LANE_ALLOC_DESCRIPTOR *LaneConfigDescriptor; + + Status = AGESA_ERROR; + LaneConfigDescriptor = PcieLaneAllocConfigurationKB; + while (LaneConfigDescriptor != NULL) { + if (LaneConfigDescriptor->WrapId == Wrapper->WrapId && LaneConfigDescriptor->EngineType == EngineType) { + switch (EngineType) { + case PciePortEngine: + Status = PcieConfigurePcieEnginesLaneAllocation (Wrapper, LaneConfigDescriptor, ConfigurationId); + break; + case PcieDdiEngine: + Status = PcieConfigureDdiEnginesLaneAllocation (Wrapper, LaneConfigDescriptor, ConfigurationId); + break; + default: + ASSERT (FALSE); + } + break; + } + LaneConfigDescriptor = PcieConfigGetNextDataDescriptor (LaneConfigDescriptor); + } + return Status; +} + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieGetCoreConfigurationValueKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + switch (ConfigurationSignature) { + case GPP_CORE_x4x1x1x1x1: + *ConfigurationValue = 0x4; + break; + case GPP_CORE_x4x2x1x1: + *ConfigurationValue = 0x3; + break; + case GPP_CORE_x4x2x2: + *ConfigurationValue = 0x2; + break; + case GPP_CORE_x4x4: + *ConfigurationValue = 0x1; + break; + default: + IDS_HDT_CONSOLE (PCIE_MISC, "ERROR!!![%s Wrapper] Unknown core config signature 0x%08x%08x\n", + PcieDebugGetWrapperNameStringKB (Wrapper), + ((UINT32 *) &ConfigurationSignature)[1], + ((UINT32 *) &ConfigurationSignature)[0] + ); + ASSERT (FALSE); + Status = AGESA_ERROR; + } + return Status; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieCheckPortPciDeviceMappingKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 DevFunc; + UINT8 Index; + DevFunc = DEVFUNC (PortDescriptor->Port.DeviceNumber, PortDescriptor->Port.FunctionNumber); + if (DevFunc == 0) { + return TRUE; + } + for (Index = 0; Index < (sizeof (DefaultPortDevMap) / sizeof (DefaultPortDevMap[0])); Index++) { + if (DefaultPortDevMap[Index] == DevFunc) { + return TRUE; + } + } + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieDebugGetCoreConfigurationStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + switch (ConfigurationValue) { + case 0x4: + return "4:1:1:1:1"; + case 0x3: + return "4:2:1:1"; + case 0x2: + return "4:2:2"; + case 0x1: + return "4:4"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieDebugGetWrapperNameStringKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + switch (Wrapper->WrapId) { + case GPP_WRAP_ID: + return "GPP"; + case DDI_WRAP_ID: + return "Virtual DDI"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] Silicon Silicon config descriptor + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieDebugGetHostRegAddressSpaceStringKB ( + IN PCIe_SILICON_CONFIG *Silicon, + IN UINT16 AddressFrame + ) +{ + switch (AddressFrame) { + case 0x130: + return "GPP WRAP"; + case 0x110: + return "GPP PIF0"; + case 0x120: + return "GPP PHY0"; + case 0x140: + return "GPP CORE"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE Lane can NOT be muxed + */ + +BOOLEAN +PcieCheckPortPcieLaneCanBeMuxedKB ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + PCIe_WRAPPER_CONFIG *Wrapper; + UINT16 NormalizedLoPhyLane; + BOOLEAN Result; + + Result = FALSE; + Wrapper = PcieConfigGetParentWrapper (Engine); + DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; + + if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { + Result = TRUE; + } else { + if (NormalizedLoPhyLane == 0) { + Result = TRUE; + } else { + if ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0) { + Result = TRUE; + } + } + } + return Result; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieMapPortPciAddressKB ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + AGESA_STATUS Status; + KB_COMPLEX_CONFIG *ComplexConfig; + PCIe_COMPLEX_CONFIG *Complex; + PCIe_PLATFORM_CONFIG *Pcie; + UINT8 DevFunc; + UINT8 Index; + Status = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressKB Enter\n"); + Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); + if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { + Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; + Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; + } + ComplexConfig = (KB_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Engine); + IDS_OPTION_HOOK (IDS_GNB_PCIE_PORT_REMAP, &Engine->Type.Port, GnbLibGetHeader (Pcie)); + DevFunc = (Engine->Type.Port.PortData.DeviceNumber << 3) | Engine->Type.Port.PortData.FunctionNumber; + for (Index = 0; Index < sizeof (ComplexConfig->FmSilicon.PortDevMap); ++Index) { + if (ComplexConfig->FmSilicon.PortDevMap[Index] == DevFunc) { + Status = AGESA_ERROR; + break; + } + } + if (Status == AGESA_SUCCESS) { + ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.PcieBridgeId] = DevFunc; + } + for (Index = 0; Index < sizeof (DefaultPortDevMap); ++Index) { + if (DevFunc == DefaultPortDevMap[Index]) { + Engine->Type.Port.LogicalBridgeId = Index; + // Get the configuration from the table or from "auto settings" + if (Engine->Type.Port.PortData.ApicDeviceInfo.GroupMap == 0x00) { + // If Group is 0, use "Auto" settings + Engine->Type.Port.PortData.ApicDeviceInfo = DefaultIoapicConfig[Index]; + } + break; + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressKB Exit [0x%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * @param[in] Silicon Silicon config descriptor + */ + +VOID +PcieSetPortPciAddressMapKB ( + IN PCIe_SILICON_CONFIG *Silicon + ) +{ + UINT8 Index; + UINT8 DevFuncIndex; + UINT8 PortDevMap [sizeof (DefaultPortDevMap)]; + PCIe_PLATFORM_CONFIG *Pcie; + D0F0x64_x30_STRUCT D0F0x64_x30; + + Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Silicon->Header); + LibAmdMemCopy (&PortDevMap[0], &DefaultPortDevMap[0], sizeof (DefaultPortDevMap), GnbLibGetHeader (Pcie)); + for (Index = 0; Index < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++Index) { + if (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] != 0) { + for (DevFuncIndex = 0; DevFuncIndex < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++DevFuncIndex) { + if (PortDevMap[DevFuncIndex] == ((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index]) { + PortDevMap[DevFuncIndex] = 0; + break; + } + } + } + } + for (Index = 0; Index < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++Index) { + if (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] == 0) { + for (DevFuncIndex = 0; DevFuncIndex < sizeof (((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++DevFuncIndex) { + if (PortDevMap[DevFuncIndex] != 0) { + ((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] = PortDevMap[DevFuncIndex]; + PortDevMap[DevFuncIndex] = 0; + break; + } + } + } + GnbRegisterReadKB ((GNB_HANDLE *) Silicon, D0F0x64_x30_TYPE, D0F0x64_x30_ADDRESS + Index, &D0F0x64_x30.Value, 0, GnbLibGetHeader (Pcie)); + D0F0x64_x30.Field.DevFnMap = ((KB_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index]; + GnbRegisterWriteKB ((GNB_HANDLE *) Silicon, D0F0x64_x30_TYPE, D0F0x64_x30_ADDRESS + Index, &D0F0x64_x30.Value, 0, GnbLibGetHeader (Pcie)); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Build default SB configuration descriptor + * + * + * @param[in] SocketId Socket Id + * @param[out] SbPort Pointer to SB configuration descriptor + * @param[in] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieGetSbConfigInfoKB ( + IN UINT8 SocketId, + OUT PCIe_PORT_DESCRIPTOR *SbPort, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return AGESA_UNSUPPORTED; +} + + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c new file mode 100644 index 0000000000..2199796fd8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c @@ -0,0 +1,938 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87701 $ @e \$Date: 2013-02-07 12:58:51 -0600 (Thu, 07 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbUra.h" +#include "GnbCommonLib.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbPcieInitLibV5.h" +#include "PcieLibKB.h" +#include "PcieComplexDataKB.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "OptionGnb.h" +#include "GnbSmuInitLibV7.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEEARLYINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern GNB_BUILD_OPTIONS GnbBuildOptions; +extern BUILD_OPT_CFG UserOptions; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB; +extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB; +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Set port device/function mapping + * + * + * + * @param[in] Descriptor Silicon descriptor + * @param[in] Buffer Pointer to buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC AGESA_STATUS +PciePortMapInitCallbackKB ( + IN PCIe_DESCRIPTOR_HEADER *Descriptor, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieSetPortPciAddressMapKB ((PCIe_SILICON_CONFIG *) Descriptor); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Static init for various registers. + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyStaticInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINTN Index; + + for (Index = 0; Index < PcieInitEarlyTableKB.Length; Index++) { + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS), + PcieInitEarlyTableKB.Table[Index].Reg, + AccessS3SaveWidth32, + (UINT32)~PcieInitEarlyTableKB.Table[Index].Mask, + PcieInitEarlyTableKB.Table[Index].Data, + GnbLibGetHeader (Pcie) + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Init core registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PcieEarlyCoreInitKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + UINTN Index; + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitKB Enter\n"); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + for (Index = 0; Index < CoreInitTableKB.Length; Index++) { + UINT32 Value; + Value = PcieRegisterRead ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableKB.Table[Index].Reg), + Pcie + ); + Value &= (~CoreInitTableKB.Table[Index].Mask); + Value |= CoreInitTableKB.Table[Index].Data; + PcieRegisterWrite ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTableKB.Table[Index].Reg), + Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitKB Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set Pcie Phy Isolation + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +STATIC +PciePhyIsolationKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 ActiveLaneBitmap; + UINT32 PhyRxIsoDis; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; + UINT32 D0F0xE4_WRAP_8021; + UINT32 D0F0xE4_WRAP_8022; + UINT32 D0F0xE4_WRAP_8025; + UINT32 D0F0xE4_WRAP_8026; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Enter\n"); + + // Apply lane mux + D0F0xE4_WRAP_8021 = 0x07060504; + D0F0xE4_WRAP_8022 = 0x03020100; + D0F0xE4_WRAP_8025 = 0x07060504; + D0F0xE4_WRAP_8026 = 0x03020100; + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS), + D0F0xE4_WRAP_8021, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS), + D0F0xE4_WRAP_8022, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS), + D0F0xE4_WRAP_8025, + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8026_ADDRESS), + D0F0xE4_WRAP_8026, + FALSE, + Pcie + ); + + PhyRxIsoDis = GnbBuildOptions.CfgPciePhyIsolationEnable ? 0 : 3; + ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, Wrapper); + if ((ActiveLaneBitmap & 0xF0) != 0) { + PhyRxIsoDis = 3; + } + + IDS_OPTION_HOOK (IDS_GNB_PCIE_PHY_ISOLATION, &PhyRxIsoDis, GnbLibGetHeader (Pcie)); + + D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8013.Field.PhyRxIsoDis = 3; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + D0F0xE4_WRAP_8013.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Exit\n"); +} + +UINT8 LaneMuxSelectorArrayKB[] = { 7, 6, 5, 4, 3, 2, 1, 0 }; + +/*----------------------------------------------------------------------------------------*/ +/** + * Locate mux array index + * + * + * + * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array + * @param[in] LaneMuxValue The value that match to array + * @retval Index Index successfully mapped + */ +STATIC UINT8 +PcieTopologyLocateMuxIndexKB ( + IN OUT UINT8 *LaneMuxSelectorArrayPtr, + IN UINT8 LaneMuxValue + ) +{ + UINT8 Index; + for (Index = 0; Index < sizeof (LaneMuxSelectorArrayKB); Index++ ) { + if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) { + return Index; + } + } + return 0; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply lane mux + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC VOID +PcieTopologyApplyLaneMuxKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT32 Index; + UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayKB)]; + UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorArrayKB)]; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxKB Enter\n"); + if (PcieLibIsPcieWrapper (Wrapper)) { + LibAmdMemCopy ( + &TxLaneMuxSelectorArray[0], + &LaneMuxSelectorArrayKB[0], + sizeof (LaneMuxSelectorArrayKB), + GnbLibGetHeader (Pcie) + ); + LibAmdMemCopy ( + &RxLaneMuxSelectorArray[0], + &LaneMuxSelectorArrayKB[0], + sizeof (LaneMuxSelectorArrayKB), + GnbLibGetHeader (Pcie) + ); + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) { + UINT32 CoreLaneBitmap; + UINT32 PifLaneBitmap; + UINT8 CurrentCoreLane; + UINT8 CurrentPifLane; + + CoreLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_CORE_ALLOC, 0, EngineList); + PifLaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, EngineList); + + while (CoreLaneBitmap != 0) { + CurrentCoreLane = LibAmdBitScanForward (CoreLaneBitmap); + CurrentPifLane = LibAmdBitScanForward (PifLaneBitmap); + + if (TxLaneMuxSelectorArray[CurrentPifLane] != CurrentCoreLane) { + TxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexKB (TxLaneMuxSelectorArray, CurrentCoreLane)] = TxLaneMuxSelectorArray[CurrentPifLane]; + TxLaneMuxSelectorArray[CurrentPifLane] = CurrentCoreLane; + } + + if (RxLaneMuxSelectorArray[CurrentCoreLane] != CurrentPifLane) { + RxLaneMuxSelectorArray[PcieTopologyLocateMuxIndexKB (RxLaneMuxSelectorArray, CurrentPifLane)] = RxLaneMuxSelectorArray[CurrentCoreLane]; + RxLaneMuxSelectorArray[CurrentCoreLane] = CurrentPifLane; + } + + CoreLaneBitmap &= (~ (1 << CurrentCoreLane)); + PifLaneBitmap &= (~ (1 << CurrentPifLane)); + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + for (Index = 0; Index < 2; ++Index) { + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS + Index), + ((UINT32 *) TxLaneMuxSelectorArray) [Index], + FALSE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS + Index), + ((UINT32 *) RxLaneMuxSelectorArray) [Index], + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMuxKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +STATIC VOID +PcieTopologyExecuteReconfigKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; + PCIe_SILICON_CONFIG *Silicon; + DEV_OBJECT DevObject; + + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigKB Enter\n"); + + D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; + D0F0xE4_WRAP_8062.Field.ResetPeriod = 0x2; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + Silicon = PcieConfigGetParentSilicon (Wrapper); + + GnbLibPciIndirectRMW ( + Silicon->Address.AddressValue | D0F0xB8_ADDRESS, + 0x3f81c, + AccessWidth32, + (UINT32) ~0xff00, + Wrapper->WrapId << 8, + GnbLibGetHeader (Pcie) + ); + + DevObject.StdHeader = GnbLibGetHeader (Pcie); + DevObject.GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie)); + DevObject.DevPciAddress.AddressValue = Silicon->Address.AddressValue; + GnbSmuServiceRequestV7 ( + &DevObject, + 25, //SMC_MSG_RECONFIGURE, + 0, + 0 + ); + + D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; + D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), + D0F0xE4_WRAP_8062.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigKB Exit\n"); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Apply Misc settings for given wrapper + * + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ +STATIC VOID +PcieMiscInitKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; + GnbRegistersKB4915_STRUCT GnbRegistersKB4915; + GnbRegistersKB4940_STRUCT GnbRegistersKB4940; + GnbRegistersKB4965_STRUCT GnbRegistersKB4965; + GnbRegistersKB4990_STRUCT GnbRegistersKB4990; + GnbRegistersKB5015_STRUCT GnbRegistersKB5015; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMiscInitKB Enter\n"); + D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8011.Field.Bitfield_23_23 = 0; + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + D0F0xE4_WRAP_8011.Value, + TRUE, + Pcie + ); + + GnbRegistersKB4915.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x805), + Pcie + ); + + GnbRegistersKB4940.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x905), + Pcie + ); + + GnbRegistersKB4965.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0A05), + Pcie + ); + GnbRegistersKB4990.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0B05), + Pcie + ); + + GnbRegistersKB5015.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0C05), + Pcie + ); + + GnbRegistersKB4915.Field.bit_31_24 = 0x40; + GnbRegistersKB4940.Field.bit_31_24 = 0x40; + GnbRegistersKB4965.Field.bit_31_24 = 0x40; + GnbRegistersKB4990.Field.bit_31_24 = 0x40; + GnbRegistersKB5015.Field.bit_31_24 = 0x40; + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x805), + GnbRegistersKB4915.Value, + TRUE, + Pcie + ); + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x905), + GnbRegistersKB4940.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0A05), + GnbRegistersKB4965.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0B05), + GnbRegistersKB4990.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x0C05), + GnbRegistersKB5015.Value, + TRUE, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMiscInitKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Switch to PCIe Native Gen1 PLL. + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieNativeGen1PLLSwitchKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + UINT32 ParamValue; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieNativeGen1PLLSwitchKB Enter\n"); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + ParamValue = 0; + if (GlobalSpeedCap == PcieGen1) { + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, 87, &ParamValue, 0, GnbLibGetHeader (Pcie)); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieNativeGen1PLLSwitchKB Exit\n"); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init prior training. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieEarlyInitCallbackKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + BOOLEAN CoreConfigChanged; + BOOLEAN PllConfigChanged; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackKB Enter\n"); + CoreConfigChanged = FALSE; + PllConfigChanged = FALSE; + IDS_OPTION_HOOK (IDS_BEFORE_RECONFIGURATION, Pcie, GnbLibGetHeader (Pcie)); + PcieTopologyPrepareForReconfig (Wrapper, Pcie); + Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie); + ASSERT (Status == AGESA_SUCCESS); + PciePhyIsolationKB (Wrapper, Pcie); + PcieTopologyApplyLaneMuxKB (Wrapper, Pcie); + PciePifSetRxDetectPowerMode (Wrapper, Pcie); + PciePifSetLs2ExitTimeV5 (Wrapper, Pcie); + PciePifApplyGanging (Wrapper, Pcie); + PcieTopologySelectMasterPllKB (Wrapper, &PllConfigChanged, Pcie); + PcieMiscInitKB (Wrapper, Pcie); + PcieTopologyExecuteReconfigKB (Wrapper, Pcie); + PcieTopologyCleanUpReconfig (Wrapper, Pcie); + PcieTopologySetLinkReversalV4 (Wrapper, Pcie); + PciePifPllConfigureKB (Wrapper, Pcie); + PcieTopologyLaneControlV5 ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), + Wrapper, + Pcie + ); + + PciePollPifForCompeletion (Wrapper, Pcie); + PcieEarlyCoreInitKB (Wrapper, Pcie); + PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackKB Exit [%x]\n", Status); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieEarlyInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + BOOLEAN NativeGen1PLL; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + NativeGen1PLL = GnbBuildOptions.CfgNativeGen1PLL; + + Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, PciePortMapInitCallbackKB, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_OPTION_HOOK (IDS_GNB_PMM_NATIVEGEN1PLL, &NativeGen1PLL, GnbLibGetHeader (Pcie)); + + if (NativeGen1PLL == TRUE) { + Status = PcieNativeGen1PLLSwitchKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + } + + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackKB, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieEarlyStaticInitKB (Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitKB Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set misc slot capability + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +PcieLinkSetSlotCapKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 IntPin; + PCIe_WRAPPER_CONFIG *Wrapper; + + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS, + AccessWidth32, + 0xffffffff, + 1 << DxF0x58_SlotImplemented_OFFSET, + GnbLibGetHeader (Pcie) + ); + + if (Engine->Type.Port.Address.Address.Function < 5) { + IntPin = Engine->Type.Port.Address.Address.Function; + } else { + IntPin = Engine->Type.Port.Address.Address.Function - 4; + } + + GnbLibPciRMW ( + Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS, + AccessWidth32, + 0xffffffff, + IntPin << DxF0x3C_IntPin_OFFSET, + GnbLibGetHeader (Pcie) + ); + + // Set MaxPayload straps for port + if (Engine->EngineData.StartLane == Engine->EngineData.EndLane) { + IDS_HDT_CONSOLE (GNB_TRACE, "Set MaxPayload strap for StartLane = %d and EndLane = %d\n", Engine->EngineData.StartLane, Engine->EngineData.EndLane); + Wrapper = PcieConfigGetParentWrapper (Engine); + PcieRegisterRMW ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, 0x804 + (Engine->Type.Port.PortId) * 0x100), + 0xe, + MAX_PAYLOAD_256 << 1, + FALSE, + Pcie + ); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieEarlyPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackKB Enter\n"); + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + PciePortProgramRegisterTable (PortInitEarlyTableKB.Table, PortInitEarlyTableKB.Length, Engine, FALSE, Pcie); + PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie); + PcieSetLinkWidthCap (Engine, Pcie); + PcieCompletionTimeout (Engine, Pcie); + PcieLinkSetSlotCapKB (Engine, Pcie); + PcieLinkInitHotplugV5 (Engine, Pcie); + PciePhyChannelCharacteristicV5 (Engine, Pcie); + if (Engine->Type.Port.PortData.PortPresent == PortDisabled || + (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent && + Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced && + Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) { + ASSERT (!PcieConfigIsSbPcieEngine (Engine)); + // + // Pass endpoint status in scratch + // + PciePortRegisterRMW ( + Engine, + 0x1, + 0x1, + 0x1, + FALSE, + Pcie + ); + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + if (PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +STATIC +DdiEarlyPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 GMMx6464; + UINT32 GMMx5C6C; + UINT32 GMMx5C90; + + IDS_HDT_CONSOLE (GNB_TRACE, "DdiEarlyPortInitCallbackKB Enter\n"); + if ((Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDpToLvds) || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) || + (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvdsSwInit)) { + + IDS_HDT_CONSOLE (GNB_TRACE, "Found eDP/LVDS Connector\n"); + + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x6464, &GMMx6464, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c90, &GMMx5C90, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c6c, &GMMx5C6C, 0, GnbLibGetHeader (Pcie)); + GMMx6464 |= 1; + GMMx6464 |= 1 << 4; + GMMx6464 |= 1 << 25; + GMMx5C90 &= ~0x3f00; GMMx5C90 |= 1 << 8; + GMMx5C6C &= ~0x1800; GMMx5C6C |= 1 << 13; + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x6464, &GMMx6464, 0, GnbLibGetHeader (Pcie)); + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c90, &GMMx5C90, 0, GnbLibGetHeader (Pcie)); + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x12, 0x5c6c, &GMMx5C6C, 0, GnbLibGetHeader (Pcie)); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "DdiEarlyPortInitCallbackKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ +AGESA_STATUS +STATIC +PcieEarlyPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateResetExit; + } + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieEarlyPortInitCallbackKB, + NULL, + Pcie + ); + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + DdiEarlyPortInitCallbackKB, + NULL, + Pcie + ); + + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + PCIe_PLATFORM_CONFIG *Pcie; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceKB Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PcieEarlyInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieEarlyPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c new file mode 100644 index 0000000000..9656f26d9e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe env post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEENVINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Env Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieEnvInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreKBS3Script_ID, 0, NULL); + return AGESA_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c new file mode 100644 index 0000000000..61b07250a6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.c @@ -0,0 +1,463 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * KB specific PCIe services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 87645 $ @e \$Date: 2013-02-06 13:08:17 -0600 (Wed, 06 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "heapManager.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbSbLib.h" +#include "GnbCommonLib.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV5.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbNbInitLibV4.h" +#include "GnbNbInitLibV1.h" +#include "GnbNbInitLibV5.h" +#include "PcieComplexDataKB.h" +#include "PcieLibKB.h" +#include "GnbRegistersKB.h" +#include "GnbRegisterAccKB.h" +#include "GnbF1Table.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIELIBKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapKB ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ); + +UINT32 +GnbTimeStampKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +PcieMaxPayloadKB ( + IN PCIe_ENGINE_CONFIG *Engine + ); +/*----------------------------------------------------------------------------------------*/ +/** + * PLL powerdown + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ + +VOID +PciePifPllConfigureKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureKB Enter\n"); + D0F0xE4_PIF_0012.Value = PcieRegisterRead ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), + Pcie + ); + + D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0; + + if (Wrapper->Features.PowerOffUnusedPlls != 0) { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; + } else { + D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0; + D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0; + } + + if (Wrapper->Features.PllOffInL1 != 0) { + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; + } else { + D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; + D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; + } + + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + 1), + D0F0xE4_PIF_0012.Value, + TRUE, + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllConfigureKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down unused lanes and plls + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrPowerDownUnusedLanesKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 UnusedLanes; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanesKB Enter\n"); + if (Wrapper->Features.PowerOffUnusedLanes != 0) { + UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper); + PcieTopologyLaneControlV5 ( + DisableLanes, + UnusedLanes, + Wrapper, + Pcie + ); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanesKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Request boot up voltage + * + * + * + * @param[in] LinkCap Global GEN capability + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +PcieSetVoltageKB ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 TargetVid; + UINT8 MinVidIndex; + UINT8 PP_FUSE_ARRAY_V2_fld32[5]; + UINT8 Index; + PP_F1_ARRAY_V2 *PpF1Array; + UINT32 Millivolt; + UINT32 D0F0xBC_xC0104007; + UINT32 D0F0xBC_xC0104008; + UINT32 D0F0xBC_xC010407C; + UINT32 D0F0xBC_xC0107064; + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageKB Enter\n"); + PpF1Array = GnbLocateHeapBuffer (AMD_PP_F1_TABLE_HANDLE, GnbLibGetHeader (Pcie)); + if (PpF1Array == NULL) { + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC0104007, &D0F0xBC_xC0104007, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC0104008, &D0F0xBC_xC0104008, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC010407C, &D0F0xBC_xC010407C, 0, GnbLibGetHeader (Pcie)); + GnbRegisterReadKB (GnbGetHandle (GnbLibGetHeader (Pcie)), 0x4, 0xC0107064, &D0F0xBC_xC0107064, 0, GnbLibGetHeader (Pcie)); + PP_FUSE_ARRAY_V2_fld32[0] = (UINT8) ((D0F0xBC_xC0104007 >> 5) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[1] = (UINT8) ((D0F0xBC_xC0104008 >> 5) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[2] = (UINT8) ((D0F0xBC_xC0104008 >> 13) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[3] = (UINT8) ((D0F0xBC_xC0104008 >> 21) & 0xFF); + PP_FUSE_ARRAY_V2_fld32[4] = (UINT8) ((D0F0xBC_xC010407C >> 20) & 0xFF); + Index = (UINT8) ((D0F0xBC_xC0107064 >> 11) & 7); + } else { + PP_FUSE_ARRAY_V2_fld32[0] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[0]; + PP_FUSE_ARRAY_V2_fld32[1] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[1]; + PP_FUSE_ARRAY_V2_fld32[2] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[2]; + PP_FUSE_ARRAY_V2_fld32[3] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[3]; + PP_FUSE_ARRAY_V2_fld32[4] = PpF1Array->PP_FUSE_ARRAY_V2_fld32[4]; + Index = PpF1Array->PcieGen2Vid; + } + if (LinkCap > PcieGen1) { + ASSERT (PP_FUSE_ARRAY_V2_fld32[Index] != 0); + TargetVid = PP_FUSE_ARRAY_V2_fld32[Index]; + } else { + + MinVidIndex = 0; + for (Index = 0; Index < 5; Index++) { + if (PP_FUSE_ARRAY_V2_fld32[Index] > PP_FUSE_ARRAY_V2_fld32[MinVidIndex]) { + MinVidIndex = (UINT8) Index; + } + } + ASSERT (PP_FUSE_ARRAY_V2_fld32[MinVidIndex] != 0); + TargetVid = PP_FUSE_ARRAY_V2_fld32[MinVidIndex]; + } + + IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid); + Millivolt = GnbTranslateVidCodeToMillivoltV5 (TargetVid, GnbLibGetHeader (Pcie)) * 4 / 100; + GnbRegisterWriteKB (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, SMC_MSG_VDDNB_REQUEST, &Millivolt, 0, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL power up latency + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + * @retval Pll wake up latency in us + */ +UINT8 +PciePifGetPllPowerUpLatencyKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return 35; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieGetLinkSpeedCapKB ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIe_WRAPPER_CONFIG *Wrapper; + PCIe_PLATFORM_CONFIG *Pcie; + + Wrapper = PcieConfigGetParentWrapper (Engine); + Pcie = PcieConfigGetPlatform (Wrapper); + + LinkSpeedCapability = PcieGen2; + + if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { + Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; + } + if (Pcie->PsppPolicy == PsppPowerSaving) { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { + LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; + } + if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { + + if (( Pcie->PsppPolicy == PsppBalanceLow || + Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) + && !PcieConfigIsSbPcieEngine (Engine)) { + + LinkSpeedCapability = PcieGen1; + } + } + return LinkSpeedCapability; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Family specific time stamp function + * + * + * @param[in] StdHeader Standard configuration header + * @retval Count + */ +UINT32 +GnbTimeStampKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TimeStamp; + + TimeStamp = 0; + + GnbLibPciIndirectRead ( + MAKE_SBDFO (0, 0, 0, 0, 0xE0), + 0x13080F0, + AccessWidth32, + &TimeStamp, + StdHeader + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "GnbTsKb: %08x\n", TimeStamp); + return TimeStamp; + +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Limit MaxPayload to 256 for x1 ports + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @retval MaxPayload MaxPayloadSupport + */ +UINT8 +PcieMaxPayloadKB ( + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT8 MaxPayload; + + MaxPayload = MAX_PAYLOAD_512; + if (Engine->EngineData.StartLane == Engine->EngineData.EndLane) { + MaxPayload = MAX_PAYLOAD_256; + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMaxPayloadKB Exit with MaxPayload = %d for StartLane = %d and EndLane = %d\n", MaxPayload, Engine->EngineData.StartLane, Engine->EngineData.EndLane); + return MaxPayload; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Select master PLL + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[out] ConfigChanged Pointer to boolean indicator that configuration was changed + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieTopologySelectMasterPllKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_ENGINE_CONFIG *EngineList; + UINT16 MasterLane; + UINT16 MasterHotplugLane; + UINT16 EngineMasterLane; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013; + D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n"); + MasterLane = 0xFFFF; + MasterHotplugLane = 0xFFFF; + EngineList = PcieConfigGetChildEngine (Wrapper); + while (EngineList != NULL) { + if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) { + EngineMasterLane = PcieConfigGetPcieEngineMasterLane (EngineList); + if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + MasterHotplugLane = (EngineMasterLane < MasterHotplugLane) ? EngineMasterLane : MasterHotplugLane; + } else { + MasterLane = (EngineMasterLane < MasterLane) ? EngineMasterLane : MasterLane; + if (PcieConfigIsSbPcieEngine (EngineList)) { + break; + } + } + } + EngineList = PcieLibGetNextDescriptor (EngineList); + } + + if (MasterLane == 0xffff) { + if (MasterHotplugLane != 0xffff) { + MasterLane = MasterHotplugLane; + } else { + MasterLane = 0x0; + } + } + + D0F0xE4_WRAP_8013.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value; + + if (MasterLane <= 3 ) { + Wrapper->MasterPll = GNB_PCIE_MASTERPLL_A; + } else { + Wrapper->MasterPll = GNB_PCIE_MASTERPLL_B; + } + + IDS_OPTION_HOOK (IDS_GNB_PCIE_MASTERPLL_SELECTION, &(Wrapper->MasterPll), GnbLibGetHeader (Pcie)); + + if (Wrapper->MasterPll == GNB_PCIE_MASTERPLL_A) { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0; + } else { + D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0; + D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1; + } + + if (ConfigChanged != NULL) { + *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE; + } + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS), + D0F0xE4_WRAP_8013.Value, + FALSE, + Pcie + ); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n"); +} + diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h new file mode 100644 index 0000000000..0434b7886e --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieLibKB.h @@ -0,0 +1,80 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * KB specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84519 $ @e \$Date: 2012-12-17 11:20:40 -0600 (Mon, 17 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _PCIELIBKB_H_ +#define _PCIELIBKB_H_ + +VOID +PciePifPllConfigureKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePwrPowerDownUnusedLanesKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieSetVoltageKB ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PciePifGetPllPowerUpLatencyKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieTopologySelectMasterPllKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + OUT BOOLEAN *ConfigChanged, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c new file mode 100644 index 0000000000..ef076477ea --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c @@ -0,0 +1,392 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe mid post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 88079 $ @e \$Date: 2013-02-15 15:28:53 -0600 (Fri, 15 Feb 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieConfig.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbPcieInitLibV5.h" +#include "GnbFamServices.h" +#include "PcieLibKB.h" +#include "PciePortServicesV4.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEMIDINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PcieMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieMidPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortProgramRegisterTable (PortInitMidTableKB.Table, PortInitMidTableKB.Length, Engine, TRUE, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PcieEnableSlotPowerLimitV5 (Engine, Pcie); + } + // If StartLane == 4/7 and EndLane == 7/4, this is GFX port + if (!(((Engine->EngineData.StartLane == 4) && (Engine->EngineData.EndLane == 7)) || + ((Engine->EngineData.StartLane == 7) && (Engine->EngineData.EndLane == 4)))) { + // For GPP ports only set STRAP_MED_yTSx_COUNT=2 + PciePortRegisterRMW ( + Engine, + 0xC0, + 0x30, + 0x2 << 4, + TRUE, + Pcie + ); + } + PcieEnableAspm (Engine, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PcieMidPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + Status = AGESA_SUCCESS; + + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieMidPortInitCallbackKB, + NULL, + Pcie + ); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageKB (GlobalSpeedCap, Pcie); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Clock gating + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +STATIC VOID +PciePwrClockGatingKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011; + D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012; + D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014; + D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015; + D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016; + UINT8 CoreId; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingKB Enter\n"); + D0F0xE4_WRAP_8014.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8015.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8012.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + Pcie + ); + + D0F0xE4_WRAP_8011.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + Pcie + ); + + if (Wrapper->Features.ClkGating == 0x1) { + D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0; + D0F0xE4_WRAP_8011.Field.Reserved_16_16 = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkPermStop = 0; + D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0; + D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1; + D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0; + D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1; + + D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1; + D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0; + + D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1; + D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1; + D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1; + + } + + if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) { + D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1; + } + + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS), + D0F0xE4_WRAP_8014.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS), + D0F0xE4_WRAP_8015.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS), + D0F0xE4_WRAP_8012.Value, + TRUE, + Pcie + ); + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS), + D0F0xE4_WRAP_8011.Value, + TRUE, + Pcie + ); + + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + PcieRegisterWriteField ( + Wrapper, + CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS), + D0F0xE4_CORE_0011_DynClkLatency_OFFSET, + D0F0xE4_CORE_0011_DynClkLatency_WIDTH, + 0xf, + TRUE, + Pcie + ); + } + + if (Wrapper->Features.LclkGating == 0x1) { + D0F0xE4_WRAP_8016.Value = PcieRegisterRead ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), + Pcie + ); + D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1; + D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1; + D0F0xE4_WRAP_8016.Field.LclkDynGateLatency = 0x3F; + PcieRegisterWrite ( + Wrapper, + WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS), + D0F0xE4_WRAP_8016.Value, + TRUE, + Pcie + ); + } + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingKB Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Late Init. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +STATIC +PcieMidInitCallbackKB ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePwrPowerDownUnusedLanesKB (Wrapper, Pcie); + PciePwrClockGatingKB (Wrapper, Pcie); + PcieLockRegisters (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Late Init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PcieMidInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackKB, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieMidInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PcieMidPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieMidInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c new file mode 100644 index 0000000000..77fb825982 --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c @@ -0,0 +1,470 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "GnbPcieConfig.h" +#include "GnbPcieTrainingV2.h" +#include "GnbPcieInitLibV1.h" +#include "GnbPcieInitLibV4.h" +#include "GnbPcieInitLibV5.h" +#include "PcieLibKB.h" +#include "GnbRegistersKB.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_MODULES_GNBINITKB_PCIEPOSTINITKB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +AGESA_STATUS +PciePostEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +PciePostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreInitKBS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostPortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) { + PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePostS3PortInitCallbackKB ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_LINK_TRAINING_STATE State; + + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine); + PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie); + + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + + if (!PcieConfigIsSbPcieEngine (Engine)) { + // + // General Port + // + State = LinkStateDeviceNotPresent; + if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) { + // + // Non hotplug device: we only check status from previous boot + // + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + State = LinkStateResetExit; + } + } else { + UINT32 PcieScratch; + // + // Get endpoint staus from scratch + // + PcieScratch = PciePortRegisterRead (Engine, 0x1, Pcie); + // + // Hotplug device: we check ep status if reported + // + if ((PcieScratch & 0x1) == 0) { + State = LinkStateResetExit; + } + } + // + // For compliance we always leave link in enabled state + // + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) { + State = LinkStateResetExit; + } + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } else { + // + // SB port + // + State = LinkStateTrainingSuccess; + } + PcieTrainingSetPortState (Engine, State, FALSE, Pcie); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostEarlyPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + // Distributed Training started at PciePortInit complete it now to get access to PCIe devices + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Pcie->TrainingExitState = LinkStateTrainingCompleted; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostPortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostPortInitCallbackKB, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +STATIC +PciePostS3PortInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePostS3PortInitCallbackKB, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +STATIC +PciePostInitKB ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + + PcieSetVoltageKB (GlobalSpeedCap, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostEarlyInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + IDS_OPTION_HOOK (IDS_BEFORE_GPP_TRAINING, Pcie, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PciePostEarlyPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PciePostInterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PciePostInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PciePostPortInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +STATIC AGESA_STATUS +PciePostS3InterfaceKB ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceKB Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControlV5 (UnhidePorts, Pcie); + + Status = PciePostInitKB (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) { + Status = PciePostS3PortInitKB (Pcie); + } else { + Status = PciePostPortInitKB (Pcie); + } + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControlV5 (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceKB Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe S3 restore + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context Context pointer (not used) + */ +VOID +PcieLateRestoreInitKBS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + PciePostS3InterfaceKB (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c new file mode 100644 index 0000000000..10f882808a --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c @@ -0,0 +1,225 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe init tables. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85361 $ @e \$Date: 2013-01-07 11:15:28 -0600 (Mon, 07 Jan 2013) $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbRegistersKB.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ + +STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { + { + PHY_SPACE (0, 0, D0F0xE4_PHY_4440_ADDRESS), + D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_MASK, + 0x2 << D0F0xE4_PHY_4440_PllDbgRoIPFDResetCntrl_OFFSET + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_4450_ADDRESS), + D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_MASK | + D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_MASK, + (0x0 << D0F0xE4_PHY_4450_PllCfgROVTOIBiasCntrlOvrdVal0_OFFSET) | (0x90 << D0F0xE4_PHY_4450_PllCfgROBWCntrlOvrdVal0_OFFSET) + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_0004_ADDRESS), + D0F0xE4_PHY_0004_CfgIdleDetTh_MASK, + 0x0 << D0F0xE4_PHY_0004_CfgIdleDetTh_OFFSET + } + }; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableKB = { + &PcieInitEarlyTable[0], + sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + +STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { + { + D0F0xE4_CORE_0020_ADDRESS, + D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | + D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, + (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) + }, + { + D0F0xE4_CORE_0010_ADDRESS, + D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK, + (0x4 << D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET) + }, + { + D0F0xE4_CORE_001C_ADDRESS, + D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | + D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | + D0F0xE4_CORE_001C_TxArbMstLimit_MASK, + (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) + }, + { + D0F0xE4_CORE_0040_ADDRESS, + D0F0xE4_CORE_0040_PElecIdleMode_MASK, + (0x1 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) + }, + { + D0F0xE4_CORE_0002_ADDRESS, + D0F0xE4_CORE_0002_HwDebug_0_MASK, + (0x1 << D0F0xE4_CORE_0002_HwDebug_0_OFFSET) + }, + { + D0F0xE4_CORE_00C1_ADDRESS, + D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | + D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, + (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | + (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) + }, + { + D0F0xE4_CORE_00B0_ADDRESS, + D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK | + D0F0xE4_CORE_00B0_StrapF0AerEn_MASK, + (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) | (0x0 << D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET) + } +}; + +CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableKB = { + &CoreInitTable[0], + sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { + { + DxFxxE4_x70_ADDRESS, + DxFxxE4_x70_RxRcbCplTimeoutMode_MASK, + (0x1 << DxFxxE4_x70_RxRcbCplTimeoutMode_OFFSET) + }, + { + DxFxxE4_xA0_ADDRESS, + DxFxxE4_xA0_Lc16xClearTxPipe_MASK | DxFxxE4_xA0_LcL1ImmediateAck_MASK | DxFxxE4_xA0_LcL0sInactivity_MASK, + (0x1 << DxFxxE4_xA0_Lc16xClearTxPipe_OFFSET) | + (0x1 << DxFxxE4_xA0_LcL1ImmediateAck_OFFSET) | + (0x6 << DxFxxE4_xA0_LcL0sInactivity_OFFSET) + }, + { + DxFxxE4_xA1_ADDRESS, + DxFxxE4_xA1_LcDontGotoL0sifL1Armed_MASK, + (0x1 << DxFxxE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) + }, + { + DxFxxE4_xA2_ADDRESS, + DxFxxE4_xA2_LcRenegotiateEn_MASK | DxFxxE4_xA2_LcUpconfigureSupport_MASK, + (0x1 << DxFxxE4_xA2_LcRenegotiateEn_OFFSET) | + (0x1 << DxFxxE4_xA2_LcUpconfigureSupport_OFFSET) + }, + { + DxFxxE4_xA3_ADDRESS, + DxFxxE4_xA3_LcXmitFtsBeforeRecovery_MASK, + (0x1 << DxFxxE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) + }, + { + DxFxxE4_xB1_ADDRESS, + DxFxxE4_xB1_LcElecIdleMode_MASK | + DxFxxE4_xB1_LcDeassertRxEnInL0s_MASK | + DxFxxE4_xB1_LcBlockElIdleinL0_MASK, + (0x1 << DxFxxE4_xB1_LcElecIdleMode_OFFSET) | + (0x1 << DxFxxE4_xB1_LcDeassertRxEnInL0s_OFFSET) | + (0x1 << DxFxxE4_xB1_LcBlockElIdleinL0_OFFSET) + }, + { + 0xC0, + 0x70000, + (0x1 << 16) + } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableKB = { + &PortInitEarlyTable[0], + sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; + + +STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = { + { + DxFxxE4_xA2_ADDRESS, + DxFxxE4_xA2_LcDynLanesPwrState_MASK, + (0x3 << DxFxxE4_xA2_LcDynLanesPwrState_OFFSET) + }, + { + DxFxxE4_x6A_ADDRESS, + DxFxxE4_x6A_ErrReportingDis_MASK, + (0x1 << DxFxxE4_x6A_ErrReportingDis_OFFSET) + }, +// { +// 0xC0, +// DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, +// (0x1 << DxFxxE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) +// } +}; + +CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableKB = { + &PortInitMidTable[0], + sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY) +}; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h new file mode 100644 index 0000000000..1d9fc9fe5c --- /dev/null +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * SCS Binary + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 85201 $ @e \$Date: 2013-01-03 14:13:50 -0600 (Thu, 03 Jan 2013) $ + * + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _EXCEL925_H_ +#define _EXCEL925_H_ + +UINT8 excel925[] = { + 0x21, 0x53, 0x43, 0x53, 0x4B, 0x41, 0x42, 0x49, 0x4E, 0x49, 0x20, 0x20, 0x56, 0x30, 0x2E, 0x30, + 0x2E, 0x30, 0x2E, 0x31, 0x1 , 0x00, 0x00, 0x4 , 0x00, 0x3 , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x16, 0x2 , 0x1 , 0xA5, 0xF7, 0x2D, 0x83, 0x4E, 0xC3, 0xC3, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0x3F, 0x2 , 0x1 , 0x80, 0x00, 0xCA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xB8, 0x59, 0x00, 0x00, 0x92, 0x00, 0x96, 0xB8, 0x00, 0xC3, 0x00, 0xB5, 0x54, 0xB4, 0x8B, 0x62, + 0xB5, 0x00, 0xC4, 0xC1, 0x00, 0xA6, 0x55, 0x00, 0x00, 0xC7, 0x00, 0x38, 0x3C, 0x71, 0x4C, 0xB0, + 0x00, 0x00, 0xB7, 0xC4, 0x00, 0xB5, 0x86, 0xA4, 0x00, 0xC4, 0x00, 0x9B, 0xCB, 0x9D, 0x85, 0xC2, + 0xFF, 0x86, 0xD4, 0xC0, 0x00, 0x00, 0xB0, 0xBD, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x3 , 0x1 , 0xC7, 0x50, 0x7A, 0x3F, + 0x4A, 0xBE, 0x9E, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x3F, 0x2 , 0x1 , 0x80, 0x00, + 0x00, 0x91, 0x00, 0x70, 0x00, 0x00, 0x98, 0x98, 0x9F, 0x9F, 0x00, 0x00, 0x43, 0x43, 0x43, 0x43, + 0x97, 0x00, 0xB4, 0x00, 0x00, 0x00, 0xAE, 0x00, 0x00, 0x00, 0x9E, 0x93, 0x00, 0x00, 0x00, 0x77, + 0x00, 0x00, 0xA5, 0xA5, 0x00, 0x00, 0x00, 0x00, 0xA2, 0xA2, 0xA2, 0xA2, 0x00, 0x90, 0xDA, 0x96, + 0x8D, 0x8D, 0x8D, 0x8D, 0x90, 0x00, 0xFF, 0x00, 0xE6, 0x00, 0xDA, 0x4E, 0x00, 0x89, 0x89, 0x00, + 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x99, 0xA9, 0x91, 0x98, 0xC9, 0x00, 0x00, + 0x00, 0x16, 0x4 , 0x1 , 0xCC, 0xBF, 0x86, 0xAD, 0x43, 0x3A, 0x9D, 0x40, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0x3F, 0x2 , 0x1 , 0x80, 0x00, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB2, 0xB2, + 0x7E, 0x7E, 0x00, 0x00, 0x97, 0x97, 0x97, 0x97, 0xA0, 0x00, 0xBE, 0x00, 0x00, 0x00, 0xBA, 0x00, + 0x00, 0x00, 0x9D, 0x57, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0xA8, 0xA8, 0x00, 0x00, 0x4 , 0x4 , + 0xAB, 0xAB, 0xAB, 0xAB, 0x00, 0x00, 0xDE, 0x00, 0x75, 0x75, 0x75, 0x75, 0x64, 0x91, 0xFF, 0x00, + 0xE0, 0xE4, 0x95, 0x00, 0x00, 0x80, 0x80, 0xE9, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x95, 0xA5, 0xB5, 0xDE, 0x00, 0xB9, 0xCF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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