vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7

The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.

Use the name Kabini instead of Kerala everywhere.

Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.

Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

13 files changed, 202 insertions, 43 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h
index 7376a965df..9009f6bdb6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h
@@ -370,11 +370,15 @@ typedef struct _SATA_ST {
                                                         ///   @li <b>0</b> - disable
                                                         ///   @li <b>1</b> - enable
                                                         ///
-  BOOLEAN               IdeEnable;                      ///< IdeEnable - Ide Controller Mode
+  BOOLEAN               IdeEnable;                      ///< IdeEnable - Hidden IDE
                                                         ///  @par
-                                                        /// Sata IDE Controller set to Combined Mode
-                                                        ///  @li <b>0</b> - disable
-                                                        ///  @li <b>1</b> - enable
+                                                        /// Sata IDE Controller Combined Mode
+                                                        ///   Enable -  SATA controller has control over Port0 through Port3,
+                                                        ///     IDE controller has control over Port4 and Port7.
+                                                        ///   Disable - SATA controller has full control of all 8 Ports
+                                                        ///     when operating in non-IDE mode.
+                                                        ///  @li <b>0</b> - enable
+                                                        ///  @li <b>1</b> - disable
                                                         ///
   UINT8                 SataClkMode;                    /// SataClkMode - Reserved
 } SATA_ST;
@@ -843,6 +847,7 @@ typedef struct {
   TIMER_SMI             LongTimer;                      ///< Long Timer SMI
   TIMER_SMI             ShortTimer;                     ///< Short Timer SMI
   UINT32                FchCpuId;                       ///< Saving CpuId for FCH Module.
+  BOOLEAN               NoneSioKbcSupport;              ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
 } FCH_MISC;
 
 
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
index 1d717e47c2..42a9bef643 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
@@ -245,6 +245,7 @@ VOID    ImcWakeup                  (IN VOID  *FchDataPtr);
 VOID    ImcIdle                    (IN VOID  *FchDataPtr);
 BOOLEAN ValidateImcFirmware        (IN VOID  *FchDataPtr);
 VOID    SoftwareToggleImcStrapping (IN VOID  *FchDataPtr);
+VOID    SoftwareDisableImc         (IN VOID  *FchDataPtr);
 
 
 ///
@@ -355,7 +356,7 @@ VOID  FchXhciInitBeforePciInit   (IN FCH_DATA_BLOCK* FchDataPtr);
 VOID  FchXhciInitIndirectReg     (IN FCH_DATA_BLOCK* FchDataPtr);
 VOID  FchInitLateUsbXhciProgram  (IN VOID  *FchDataPtr);
 VOID  FchXhciUsbPhyCalibrated    (IN FCH_DATA_BLOCK* FchDataPtr);
-
+UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
 
 ///
 /// Fch Sd Routines
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
index a67439a68a..c370d4c9cf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
@@ -1617,8 +1617,13 @@ FCH_MISC_REGF0                   EQU     0F0h
 #define KABINI_OSC_OUT_CLOCK_SEL_48MHz  0x02
 #define KABINI_OSC_OUT_CLOCK_SEL_25MHz  0x01
 
+#define RTC_WORKAROUND_SECOND           0x00
+#define RTC_VALID_SECOND_VALUE          0x59
+#define RTC_SECOND_RESET_VALUE          0x30
+#define RTC_SECOND_LOWER_NIBBLE         0x0F
+#define RTC_VALID_SECOND_VALUE_LN       0x09
+
 #ifndef FCH_DEADLOOP
   #define FCH_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
 #endif
 
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
index a035a722c3..57ca222710 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
@@ -77,21 +77,19 @@ ACPI_REG_WRITE FchYangtzeInitEnvHwAcpiMmioTable[] =
   //
   // HPET workaround
   //
-  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
-  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
+  {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
+  {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0x3D},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x0, 0x04},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC2, (UINT8)~(BIT4), BIT4},
-  {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x07},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x03},
   {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
   {PMIO_BASE >> 8, 0x74 + 3, (UINT8)~BIT5, 0},
   {PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3},
-  {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6},
   {PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1},
-  {PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0},
   {PMIO_BASE >> 8, 0xDC, 0x7C, BIT1},
 
   {SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1},
@@ -190,6 +188,11 @@ ProgramFchEnvHwAcpiPciReg (
   if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
     RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
   }
+  if ( LocalCfgPtr->Misc.NoneSioKbcSupport ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2 + BIT1);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2);
+  }
   ProgramPcieNativeMode (FchDataPtr);
 }
 
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
index 3db2cbeae1..68c9be79ce 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
@@ -116,6 +116,7 @@ ProgramFchHwAcpiResetP (
   LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
   StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
 
+  RwPmio (FCH_PMIOA_REGC8, AccessWidth8, 0xEF, 0x0, StdHeader);
   RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader);
   RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
   RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
index 5a3833e252..c9b5ffccf6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
@@ -135,7 +135,18 @@ FchInitResetHwAcpi (
   if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) {
     ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr);
   }
-
+  //
+  // RTC Workaround for Daylight saving time enable bit
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 );   // Enable DltSavEnable
+  Value = 0x0B;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
+  LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+  Value &= 0xFE;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 );      // Disable DltSavEnable
   //
   // Prevent RTC error
   //
@@ -148,6 +159,7 @@ FchInitResetHwAcpi (
   Value = 0x08;
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
   LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
+
   if ( !LocalCfgPtr->EcKbd ) {
     //
     // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
@@ -156,6 +168,23 @@ FchInitResetHwAcpi (
   }
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
 
+  if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) {
+    Value = RTC_WORKAROUND_SECOND;
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    if ( Value > RTC_VALID_SECOND_VALUE ) {
+      Value = RTC_SECOND_RESET_VALUE;
+      LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    }
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    Value &= RTC_SECOND_LOWER_NIBBLE;
+    if ( Value > RTC_VALID_SECOND_VALUE_LN ) {
+      LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+      Value = RTC_SECOND_RESET_VALUE;
+      LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    }
+  }
+
   Value = 0x09;
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
   LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
@@ -189,14 +218,14 @@ FchInitResetHwAcpi (
   //
   // PciExpWakeStatus workaround
   //
+  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
+  AsfPort++;
   ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits);
   ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue);
   if ( (GeventValue & GeventEnableBits) != 0 ) {
     Value = 0x40;
     LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
   }
-  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
-  AsfPort++;
   LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader);
   if ((Value & (BIT2 + BIT0)) != 0) {
     Value = 0x40;
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c
index 44fe2cd99d..05f57278da 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c
@@ -176,6 +176,43 @@ ImcSleep (
   WaitForEcLDN9MailboxCmdAck (StdHeader);
 }
 
+/**
+ * SoftwareDisableImc - Software disable IMC strap
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SoftwareDisableImc (
+  IN  VOID     *FchDataPtr
+  )
+{
+  UINT8    ValueByte;
+  UINT8    PortStatusByte;
+  UINT32   AbValue;
+  UINT32   ABStrapOverrideReg;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
+  GetChipSysMode (&PortStatusByte, StdHeader);
+
+  RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
+  ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader);
+
+  ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
+  ABStrapOverrideReg = AbValue;
+  ABStrapOverrideReg &= ~BIT2;                           // bit2=0 EcEnableStrap
+  WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg);
+
+  ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
+  ValueByte |= BIT1;
+  WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
+
+  ValueByte = 06;
+  LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
+  FchStall (0xffffffff, StdHeader);
+}
 
 /**
  * ImcEnableSurebootTimer - IMC Enable Sureboot Timer.
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
index 8abcac0f8a..0ae09932cf 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
@@ -210,12 +210,12 @@ FchProgramSataPhy (
   SquelchValue[0] = (0x07 << 9);
   SquelchValue[1] = (0x07 << 9);
   for (PortNum = 0; PortNum < 2; PortNum ++) {
-    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x130 + PortNum), StdHeader);
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader);
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader);
-    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x120 + PortNum), StdHeader);
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader);
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
-    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x110 + PortNum), StdHeader);
+    RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader);
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader);
   }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
index ab3bbab37a..9f526d8837 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
@@ -165,13 +165,22 @@ FchInitMidProgramSataRegs (
     FchSataMsiCapability = 0;
   }
   //
+  // Disable SATA FLR Capability
+  //
+  RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0, StdHeader);
+  //
   // Enabled SATA MSI capability
   // SATA MSI and D3 Power State Capability MMC 0x2
   //
-  if ( !FchSataMsiCapability ) {
-    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x70 + 1), AccessWidth8, 0, 0, StdHeader);
+  if ( FchSataMsiCapability ) {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x50, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x06, StdHeader);
+  } else {
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x00, StdHeader);
+    RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x00, StdHeader);
   }
-
   //
   // Sata Target Support 8 devices function
   //
@@ -286,8 +295,8 @@ FchInitLateProgramSataRegs (
     RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00);
   }
   if ( LocalCfgPtr->Sata.SataDevSlpPort0 ) {
-    RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x3E);
-    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x01);
+    RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x0E);
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x02);
     RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFEEF, BIT4 + BIT8);
   } else {
     RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x00);
@@ -297,8 +306,8 @@ FchInitLateProgramSataRegs (
     }
   }
   if ( LocalCfgPtr->Sata.SataDevSlpPort1 ) {
-    RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x3E);
-    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x01);
+    RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x0E);
+    RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x02);
     RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFDEF, BIT4 + BIT9);
   } else {
     RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x00);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c
index e9ded685a3..577d8cf8c4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c
@@ -71,6 +71,7 @@ FchInitEnvSdProgram (
   // SD Configuration
   //
   if ( LocalCfgPtr->Sd.SdConfig != SdDisable) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x40);
     RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE8, AccessWidth8, 0xFE, BIT0);
     Sd30Control = 0;
     SdData32 = 0x30FE00B2;
@@ -83,8 +84,7 @@ FchInitEnvSdProgram (
     } else if ( LocalCfgPtr->Sd.SdConfig == SdPio) {
       SdData32 &=  ~(BIT20 + BIT22 + BIT19);       ///PIO
     }
-    SdData32 |= (LocalCfgPtr->Sd.SdSpeed << 21) + (LocalCfgPtr->Sd.SdBitWidth << 28);
-    SdData32 |= BIT24;
+    SdData32 |= BIT24 + BIT21;
     if ( LocalCfgPtr->Sd.SdHostControllerVersion == 1) {
       SdData32 |= 0x3200;
       if ( (ApuStepping & 0x0F) == 0) {
@@ -109,12 +109,13 @@ FchInitEnvSdProgram (
       Sd30Control |= (BIT16 + BIT17);
     }
     Sd30Control &= ~(BIT0 + BIT1);
-    Sd30Control |= LocalCfgPtr->Sd.SdrCapabilities;
+    // Sd30Control |= LocalCfgPtr->Sd.SdrCapabilities;
     Sd30Control |= LocalCfgPtr->Sd.SdReTuningMode << 14;
     if ( LocalCfgPtr->Sd.SdHostControllerVersion == 2) {
       Sd30Control &= 0xFFFF00FF;
-      Sd30Control |= ( BIT4 + BIT5 + BIT6 + BIT8 + BIT10 + BIT13 );
+      Sd30Control |= ( BIT0 + BIT1 + BIT8 + BIT10 + BIT13 );
     }
+    Sd30Control |= ( BIT4 + BIT5 + BIT6 );
     RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGD0 + 1, AccessWidth8, 0xFD, BIT1, StdHeader);
     RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA8, AccessWidth32, 0x3FFC, Sd30Control, StdHeader);
     RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0 + 3, AccessWidth8, 0, LocalCfgPtr->Sd.SdHostControllerVersion, StdHeader);
@@ -124,6 +125,7 @@ FchInitEnvSdProgram (
     RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGF8, AccessWidth32, 0, 0x00010002, StdHeader);
     RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGFC, AccessWidth32, 0, 0x00014000, StdHeader);
   } else {
-    RwMem (ACPI_MMIO_BASE + PMIO_BASE +  FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00);
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE8, AccessWidth8, 0xFE, 0x00);
   }
 }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
index eb0f54f473..1a02218e67 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
@@ -471,7 +471,7 @@ FchInitResetSpi (
 
   SpiModeByte = LocalCfgPtr->Mode;
   if (LocalCfgPtr->Mode) {
-    if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144)) {
+    if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144) || (SpiModeByte == FCH_SPI_MODE_QUAL_112) || (SpiModeByte == FCH_SPI_MODE_QUAL_122) || (SpiModeByte == FCH_SPI_MODE_FAST)) {
       if (FchPlatformSpiQe (FchDataPtr)) {
         FchSetQualMode (SpiModeByte, StdHeader);
       }
@@ -671,6 +671,7 @@ FchConfigureSpiDeviceDummyCycle (
 {
   UINT16     Mode16;
   UINT16     Value16;
+  UINT8      Value8;
   UINT16     DummyValue16;
   UINT16     CurrentDummyValue16;
   UINT16     CurrentMode16;
@@ -681,7 +682,8 @@ FchConfigureSpiDeviceDummyCycle (
   DummyValue16 = 8;
 
   switch (DeviceID) {
-  case 0x17BA20:
+  case 0x17BA20://N25Q064
+  case 0x16BA20://N25Q032
 
     FchSpiTransfer (
       0, //IN       UINT8    PrefixCode,
@@ -740,8 +742,34 @@ FchConfigureSpiDeviceDummyCycle (
         TRUE,//IN       BOOLEAN  DataFlag,
         TRUE //IN       BOOLEAN  FinishedFlag
       );
-      FchStall (1000, StdHeader);
-      WriteIo8 ((UINT16) (0xCF9), 0x0E);
+
+      FchSpiTransfer (
+        0, //IN       UINT8    PrefixCode,
+        0x85,//IN       UINT8    Opcode,
+        (UINT8 *)(&Value8),//IN  OUT   UINT8    *DataPtr,
+        NULL,//IN       UINT8    *AddressPtr,
+        0,//IN       UINT8    Length,
+        FALSE,//IN       BOOLEAN  WriteFlag,
+        FALSE,//IN       BOOLEAN  AddressFlag,
+        TRUE,//IN       BOOLEAN  DataFlag,
+        FALSE //IN       BOOLEAN  FinishedFlag
+      );
+
+      Value8 &= ~ (0xf << 4);
+      Value8 |= (UINT8) (DummyValue16 << 4);
+      FchSpiTransfer (
+        0x06, //IN       UINT8    PrefixCode,
+        0x81,//IN       UINT8    Opcode,
+        (UINT8 *)(&Value8),//IN  OUT   UINT8    *DataPtr,
+        NULL,//IN       UINT8    *AddressPtr,
+        0,//IN       UINT8    Length,
+        TRUE,//IN       BOOLEAN  WriteFlag,
+        FALSE,//IN       BOOLEAN  AddressFlag,
+        TRUE,//IN       BOOLEAN  DataFlag,
+        TRUE //IN       BOOLEAN  FinishedFlag
+      );
+      //      FchStall (1000, StdHeader);
+//      WriteIo8 ((UINT16) (0xCF9), 0x0E);
     }
     return TRUE;
   default:
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
index 977ee0e27a..8959420c8c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
@@ -66,6 +66,8 @@ FchEhciInitAfterPciInit (
   AMD_CONFIG_PARAMS      *StdHeader;
   UINT32                 PortNum;
   UINT32                 DrivingStrength;
+  UINT8                  RetEfuseValue;
+  UINT32                 UsbFuseCommonCalibrationValue;
 
   LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
   StdHeader = LocalCfgPtr->StdHeader;
@@ -122,8 +124,13 @@ FchEhciInitAfterPciInit (
     RwMem (BarAddress + FCH_EHCI_BAR_REGD4, AccessWidth32, ~((UINT32) (0x02)), (UINT32) (0x02));
     FchStall (400, StdHeader);
     RwMem (BarAddress + FCH_EHCI_BAR_REGD4, AccessWidth32, ~((UINT32) (0x02)), (UINT32) (0x0));
-    RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x00010000), BIT16);
-
+    RetEfuseValue = FchUsbCommonPhyCalibration ( FchDataPtr );
+    if ( RetEfuseValue == 0 ) {
+      RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x00030000), BIT16);
+    } else {
+      UsbFuseCommonCalibrationValue = RetEfuseValue << 11;
+      RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0003FF00), UsbFuseCommonCalibrationValue);
+    }
     RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader);
     RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader);
     RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader);
@@ -170,12 +177,6 @@ FchEhciInitAfterPciInit (
       RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~((UINT32) (1 << 12)), 0);
       RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~((UINT32) (1 << 12)), (UINT32) (0x1 << 12));
     }
-  } else {
-    BarAddress = FCH_FAKE_USB_BAR_ADDRESS;
-    WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
-    RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader);
-    RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), BIT12 + BIT14);
-    RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, StdHeader);
   }
 
   ReadPmio (FCH_PMIOA_REGF0, AccessWidth8, &UsbS3WakeResumeOnlyDisable, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c
index 67fcaf6408..c34a280532 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c
@@ -47,8 +47,36 @@
 // Declaration of local functions
 //
 
+#define PRODUCT_INFO_REG1           0x1FC     // Product Information Register 1
+#define AMD_CPU_DEV_FUN             ((0x18 << 3) + 3)
+
 
 /**
+ * FchUsbCommonPhyCalibration - Config USB Common PHY
+ * Calibration
+ *
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+UINT8
+FchUsbCommonPhyCalibration (
+  IN  FCH_DATA_BLOCK     *FchDataPtr
+  )
+{
+  UINT8                 RetEfuseValue;
+  FCH_DATA_BLOCK        *LocalCfgPtr;
+  AMD_CONFIG_PARAMS     *StdHeader;
+
+  LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
+  StdHeader = LocalCfgPtr->StdHeader;
+
+  ReadPci ((AMD_CPU_DEV_FUN << 16) + PRODUCT_INFO_REG1, AccessWidth8, &RetEfuseValue, StdHeader);
+  RetEfuseValue = ((RetEfuseValue & 0x1E) >> 1);
+  return RetEfuseValue;
+}
+/**
  * FchXhciUsbPhyCalibrated - Config XHCI Phy
  *
  *
@@ -133,11 +161,15 @@ FchXhciInitIndirectReg (
   UINT32                RegValue;
   FCH_DATA_BLOCK        *LocalCfgPtr;
   AMD_CONFIG_PARAMS     *StdHeader;
+  UINT8                 RetEfuseValue;
+  UINT32                UsbFuseCommonCalibrationValue;
 
   LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
   StdHeader = LocalCfgPtr->StdHeader;
   DrivingStrength = 0;
 
+  FchXhciUsbPhyCalibrated (LocalCfgPtr);
+
   RwXhci0IndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
   RwXhci0IndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
 
@@ -150,10 +182,16 @@ FchXhciInitIndirectReg (
   }
 
 
-  RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader);
+  RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x06)), StdHeader);
   RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader);
   RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
-  RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader); // For BTS
+  RetEfuseValue = FchUsbCommonPhyCalibration ( FchDataPtr );
+  if ( RetEfuseValue == 0) {
+    RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FD00FF, (UINT32) BIT16 , StdHeader);
+  } else {
+    UsbFuseCommonCalibrationValue = RetEfuseValue << 11;
+    RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, UsbFuseCommonCalibrationValue , StdHeader);
+  }
 
   for (Port = 0; Port < 2; Port ++) {
     DrivingStrength = 0x1E4;