AMD Kabini: Add AGESA/PI code for new processor family

Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-by: Nick Dill <nick.dill@se-eng.com> Tested-by: Bruce Griffith <bruce.griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3836 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com>
author: Siyuan Wang <wangsiyuanbuaa@gmail.com> 2013-07-25 15:14:15 +0800
committer: Bruce Griffith <Bruce.Griffith@se-eng.com> 2013-08-04 05:40:37 +0200
commit: affe85fbc8a13d35960aa92ae87cbb6330ad253f (patch)
tree: 9c1ace69f12b06b6544faf041994aa4288fb2e45 /src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family
parent: ae8d06969bdde9b1250bc3c4ad93f5db408dae98 (diff)
41 files changed, 17286 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c
new file mode 100644
index 0000000000..b923fec5bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbC6State.c
@@ -0,0 +1,198 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini C6 C-state feature support functions.
+ *
+ * Provides the functions necessary to initialize the C6 feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#include "cpuApicUtilities.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBC6STATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+F16KbIsC6Supported (
+  IN       C6_FAMILY_SERVICES      *C6Services,
+  IN       UINT32                  Socket,
+  IN       PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+STATIC
+F16KbInitializeC6 (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Is C6 supported on this CPU
+ *
+ * @param[in]    C6Services         Pointer to this CPU's C6 family services.
+ * @param[in]    Socket             This core's zero-based socket number.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 state is supported.
+ * @retval       FALSE              C6 state is not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F16KbIsC6Supported (
+  IN       C6_FAMILY_SERVICES      *C6Services,
+  IN       UINT32                  Socket,
+  IN       PLATFORM_CONFIGURATION  *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable C6 on a family 16h Kabini CPU.
+ *
+ * @param[in]    C6Services         Pointer to this CPU's C6 family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F16KbInitializeC6 (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR                PciAddress;
+  CSTATE_CTRL1_REGISTER   CstateCtrl1;
+  POPUP_PSTATE_REGISTER   PopDownPstate;
+  CLK_PWR_TIMING_CTRL2_REGISTER   ClkPwrTimingCtrl2;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
+    // Initialize F4x118
+    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+    // Set C-state Action Field 0
+    // bits[8]       PwrGateEnCstAct0    = 0x1
+    // bits[9]       PwrOffEnCstAct0     = 0x1
+    CstateCtrl1.PwrGateEnCstAct0 = 1;
+    CstateCtrl1.PwrOffEnCstAct0 = 1;
+    // Set C-state Action Field 1
+    // bits[24]      PwrGateEnCstAct1    = 0x1
+    // bits[25]      PwrOffEnCstAct1     = 0x1
+    CstateCtrl1.PwrGateEnCstAct1 = 1;
+    CstateCtrl1.PwrOffEnCstAct1 = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+
+    // Initialize F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
+    PciAddress.AddressValue = CPTC2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+    PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
+    PopDownPstate.PopDownPstate = ClkPwrTimingCtrl2.HwPstateMaxVal;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PopDownPstate, StdHeader);
+  } else if ((EntryPoint & (CPU_FEAT_AFTER_RESUME_MTRR_SYNC | CPU_FEAT_BEFORE_RELINQUISH_AP)) != 0) {
+    // Initialize F4x118
+    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+    // Set C-state Action Field 0
+    // bits[1]       CacheFlushEnCstAct0 = 0x1
+    CstateCtrl1.CacheFlushEnCstAct0 = 1;
+    // Set C-state Action Field 1
+    // bits[17]      CacheFlushEnCstAct1 = 0x1
+    CstateCtrl1.CacheFlushEnCstAct1 = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
+CONST C6_FAMILY_SERVICES ROMDATA F16KbC6Support =
+{
+  0,
+  F16KbIsC6Supported,
+  F16KbInitializeC6,
+  ReloadMicrocodePatchAfterMemInit
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c
new file mode 100644
index 0000000000..95c3a5ab96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c
@@ -0,0 +1,150 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function for Family 16h Kabini.
+ *
+ * Contains code to initialize Cache Flush On Halt feature for Family 16h Kabini.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCACHEFLUSHONHALT_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+SetF16KbCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in]       EntryPoint               Timepoint designator.
+ *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
+ *    @param[in]       StdHeader                Config Handle for library, services.
+ */
+VOID
+SetF16KbCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  PCI_ADDR                              PciAddress;
+  CSTATE_CTRL1_REGISTER                 CstateCtrl1;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    // Set F4x118
+    PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+    // Set C-state Action Field 0
+    // bits[11]      NbClkGate0          = 0x1
+    // bits[12]      SelfRefr0           = 0x1
+    CstateCtrl1.NbClkGate0 = 1;
+    CstateCtrl1.SelfRefr0 = 1;
+    // Set C-state Action Field 1
+    // bits[27]      NbClkGate1          = 0x1
+    // bits[28]      SelfRefr1           = 0x1
+    CstateCtrl1.NbClkGate1 = 1;
+    CstateCtrl1.SelfRefr1 = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader);
+
+    //Override the default setting
+    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader);
+  }
+
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F16KbCacheFlushOnHalt =
+{
+  0,
+  SetF16KbCacheFlushOnHaltRegister
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
new file mode 100644
index 0000000000..0ae46c605e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
@@ -0,0 +1,250 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini after warm reset sequence for core P-states
+ *
+ * Performs the "Core Minimum P-State Transition Sequence After Warm Reset"
+ * as described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "F16KbCoreAfterReset.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCOREAFTERRESET_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F16KbPmCoreAfterResetPhase1OnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F16KbPmCoreAfterResetPhase2OnCore (
+  IN       VOID              *HwPsMaxVal,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 16h Kabini core 0 entry point for performing the necessary steps for core
+ * P-states after a warm reset has occurred.
+ *
+ * The steps are as follows:
+ *    1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
+ *    2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+ *       MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
+ *    3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
+ *       cores in the processor.
+ *    4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+ *       MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal].
+ *    5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
+ *       MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
+ *       MSRC001_0061[PstateMaxVal].
+ *    6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F16KbPmCoreAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32       Core;
+  UINT32       HwPsMaxVal;
+  PCI_ADDR     PciAddress;
+  AP_TASK      TaskPtr;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbPmCoreAfterReset\n");
+
+  GetCurrentCore (&Core, StdHeader);
+  ASSERT (Core == 0);
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_3, CPTC2_REG);
+  LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
+  HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->HwPstateMaxVal;
+
+  // Launch each local core to perform steps 1 through 3.
+  TaskPtr.FuncAddress.PfApTask = F16KbPmCoreAfterResetPhase1OnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+  // Launch each local core to perform steps 4 through 6.
+  TaskPtr.FuncAddress.PfApTaskI = F16KbPmCoreAfterResetPhase2OnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 1;
+  TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F16KbPmCoreAfterReset to perform MSR initialization on all
+ * cores of a family 16h socket.
+ *
+ * This function implements steps 1 - 3 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F16KbPmCoreAfterResetPhase1OnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 CofvidSts;
+  UINT64 LocalMsrRegister;
+  UINT64 PstateCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbPmCoreAfterResetPhase1OnCore\n");
+
+  // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
+  PstateCtrl = 0;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
+
+  // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+  //    MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
+  do {
+    LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
+    LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader);
+  } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) ||
+           (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid));
+
+  // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
+  //    cores in the processor.
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+  ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F16KbPmCoreAfterReset to perform MSR initialization on all
+ * cores of a family 16h socket.
+ *
+ * This function implements steps 4 - 6 on each core.
+ *
+ * @param[in]  HwPsMaxVal         Index of the highest enabled HW P-state.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F16KbPmCoreAfterResetPhase2OnCore (
+  IN       VOID              *HwPsMaxVal,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 TargetPsMsr;
+  UINT64 LocalMsrRegister;
+  UINT64 PstateCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbPmCoreAfterResetPhase2OnCore\n");
+
+  // 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
+  //    MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal].
+  LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader);
+  do {
+    LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+  } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
+           (((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
+
+  // 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for
+  //    MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by
+  //    MSRC001_0061[PstateMaxVal].
+  if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) {
+    do {
+      LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+    } while (GetF16KbCurCpuVid (&LocalMsrRegister) != GetF16KbCpuVid (&TargetPsMsr));
+  }
+
+  // 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd].
+  LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
+  do {
+    LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+  } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd);
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h
new file mode 100644
index 0000000000..2f986286ad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini after warm reset sequence for core P-states
+ *
+ * Contains code that provide power management functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _F16_KB_CORE_AFTER_RESET_H_
+#define _F16_KB_CORE_AFTER_RESET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F16KbPmCoreAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _F16_KB_CORE_AFTER_RESET_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
new file mode 100644
index 0000000000..db00c58e95
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
@@ -0,0 +1,195 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 CPB Initialization
+ *
+ * Enables core performance boost.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "cpuCpb.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBCPB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+F16KbIsCpbSupported (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+STATIC
+F16KbInitializeCpb (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT64                 EntryPoint,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for checking whether or not CPB is supported.
+ *
+ * @param[in]  CpbServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  Socket                  Zero based socket number to check.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     TRUE                    CPB is supported.
+ * @retval     FALSE                   CPB is not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F16KbIsCpbSupported (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64                MsrData;
+  BOOLEAN               CpbSupported;
+  CPB_CTRL_REGISTER     CpbControl;
+  PCI_ADDR              PciAddress;
+
+  CpbSupported = FALSE;
+
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+  if (CpbControl.NumBoostStates != 0) {
+    LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
+    if (((PSTATE_MSR *) &MsrData)->PsEnable == 1) {
+      CpbSupported = TRUE;
+    }
+  }
+  return CpbSupported;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for for enabling Core Performance Boost.
+ *
+ * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
+ *
+ * @param[in]  CpbServices             The current CPU's family services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  EntryPoint              Current CPU feature dispatch point.
+ * @param[in]  Socket                  Zero based socket number to check.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F16KbInitializeCpb (
+  IN       CPB_FAMILY_SERVICES    *CpbServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       UINT64                 EntryPoint,
+  IN       UINT32                 Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPB_CTRL_REGISTER     CpbControl;
+  PCI_ADDR              PciAddress;
+  F16_PSTATE_MSR        PstateMsrData;
+  UINT32                Pbx;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+    if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) {
+      // If any boosted P-state is still enabled, set BoostSrc = 1.
+      for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
+        LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
+        if (PstateMsrData.PsEnable == 1) {
+          CpbControl.BoostSrc = 1;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+          break;
+        }
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+CONST CPB_FAMILY_SERVICES ROMDATA F16KbCpbSupport =
+{
+  0,
+  F16KbIsCpbSupported,
+  F16KbInitializeCpb
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
new file mode 100644
index 0000000000..37d0aa0ea3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
@@ -0,0 +1,369 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions for Family16h Kabini.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 87400 $   @e \$Date: 2013-02-01 12:14:44 -0600 (Fri, 01 Feb 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuLateInit.h"
+#include "cpuF16Dmi.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBDMI_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * Processor Family Table
+ *
+ *-------------------------------------------------------------------------------------*/
+CONST CHAR8 ROMDATA str_A6[] = "AMD A6-";
+CONST CHAR8 ROMDATA str_A4[] = "AMD A4-";
+CONST CHAR8 ROMDATA str_E2[] = "AMD E2-";
+CONST CHAR8 ROMDATA str_E1[] = "AMD E1-";
+CONST CHAR8 ROMDATA str_GX[] = "AMD GX-";
+/*---------------------------------------------------------------------------------------
+ * Processor Family Table
+ *
+ *       047h = "E-Series"
+ *       048h = "A-Series"
+ *       049h = "GX-Series"
+ *-------------------------------------------------------------------------------------*/
+CONST CPU_T4_PROC_FAMILY ROMDATA F16KbFT3T4ProcFamily[] =
+{
+  {str_A6, 0x48},
+  {str_A4, 0x48},
+  {str_E2, 0x47},
+  {str_E1, 0x47},
+  {str_GX, 0x49},
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+DmiF16KbGetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+DmiF16KbGetT4ProcFamily (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT8
+DmiF16KbGetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+DmiF16KbGetMemInfo (
+  IN OUT   CPU_GET_MEM_INFO  *CpuGetMemInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+UINT16
+DmiF16KbGetExtClock (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF16KbGetInfo
+ *
+ *    Get CPU type information
+ *
+ *    @param[in,out]  CpuInfoPtr     Pointer to CPU_TYPE_INFO struct.
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ */
+VOID
+DmiF16KbGetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CPUID_DATA CpuId;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+  CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
+  CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
+  CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
+  CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4)  & 0xF; // bit 7:4
+  CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
+
+  CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber--;
+
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
+  CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
+
+  switch (CpuInfoPtr->PackageType) {
+  case KB_SOCKET_FT3:
+    /// Use 'NONE' for BGA package
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
+    break;
+  default:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
+    break;
+  }
+
+  // L1 Size & Associativity
+  LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader);
+  CpuInfoPtr->CacheInfo.L1CacheSize = (UINT32) (((CpuId.ECX_Reg >> 24) + (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->TotalCoreNumber + 1));
+
+  CpuInfoPtr->CacheInfo.L1CacheAssoc = DMI_ASSOCIATIVE_2_WAY; // Per the BKDG, this is hard-coded to 2-Way.
+
+  // L2 Size & Associativity
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader);
+  CpuInfoPtr->CacheInfo.L2CacheSize = (UINT32) (CpuId.ECX_Reg >> 16);
+
+  CpuInfoPtr->CacheInfo.L2CacheAssoc = DMI_ASSOCIATIVE_16_WAY; // Per the BKDG, this is hard-coded to 16-Way.
+
+  // L3 Size & Associativity
+  CpuInfoPtr->CacheInfo.L3CacheSize = 0;
+  CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN;
+  }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF16KbGetT4ProcFamily
+ *
+ *    Get type 4 processor family information
+ *
+ *    @param[in,out]  T4ProcFamily   Pointer to type 4 processor family information.
+ *    @param[in]      *CpuDmiProcFamilyTable  Pointer to DMI family special service
+ *    @param[in]      *CpuInfo       Pointer to CPU_TYPE_INFO struct
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ */
+VOID
+DmiF16KbGetT4ProcFamily (
+  IN OUT   UINT8 *T4ProcFamily,
+  IN       PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+  IN       CPU_TYPE_INFO *CpuInfo,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CHAR8 NameString[49];
+  CONST CHAR8 *DmiString;
+  CONST VOID  *DmiStringTable;
+  UINT8 NumberOfDmiString;
+  UINT8 i;
+
+  // Get name string from MSR_C001_00[30:35]
+  GetNameString (NameString, StdHeader);
+  // Get DMI String
+  DmiStringTable = NULL;
+  switch (CpuInfo->PackageType) {
+  case KB_SOCKET_FT3:
+    DmiStringTable = (CONST VOID *) &F16KbFT3T4ProcFamily[0];
+    NumberOfDmiString = sizeof (F16KbFT3T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY);
+    break;
+  default:
+    DmiStringTable = NULL;
+    NumberOfDmiString = 0;
+    break;
+  }
+
+  // Find out which DMI string matches current processor's name string
+  *T4ProcFamily = P_FAMILY_UNKNOWN;
+  if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) {
+    for (i = 0; i < NumberOfDmiString; i++) {
+      DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart;
+      if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) {
+        *T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting;
+        break;
+      }
+    }
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF16KbGetVoltage
+ *
+ *    Get the voltage value according to SMBIOS SPEC's requirement.
+ *
+ *    @param[in]       StdHeader      Standard Head Pointer
+ *
+ *    @retval  Voltage   - CPU Voltage.
+ *
+ */
+UINT8
+DmiF16KbGetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8     MaxVid;
+  UINT8     Voltage;
+  UINT8     NumberBoostStates;
+  UINT64    MsrData;
+  PCI_ADDR  TempAddr;
+  CPB_CTRL_REGISTER CpbCtrl;
+
+  // Voltage = 0x80 + (voltage at boot time * 10)
+  TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader);  // F4x15C
+  NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+
+  LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
+  MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+
+  if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) {
+    Voltage = 0;
+  } else {
+    Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000);
+  }
+
+  Voltage += 0x80;
+  return (Voltage);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF16KbGetMemInfo
+ *
+ *    Get memory information.
+ *
+ *    @param[in,out]  CpuGetMemInfoPtr      Pointer to CPU_GET_MEM_INFO struct.
+ *    @param[in]      StdHeader             Standard Head Pointer
+ *
+ */
+VOID
+DmiF16KbGetMemInfo (
+  IN OUT   CPU_GET_MEM_INFO  *CpuGetMemInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32 PciData;
+  PCI_ADDR PciAddress;
+
+  CpuGetMemInfoPtr->EccCapable = FALSE;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+  // Check if F2x90[DimmEccEn] is set
+  if ((PciData & 0x00080000) != 0) {
+    CpuGetMemInfoPtr->EccCapable = TRUE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF16KbGetExtClock
+ *
+ *    Get the external clock Speed
+ *
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ *    @retval  ExtClock   - CPU external clock Speed.
+ *
+ */
+UINT16
+DmiF16KbGetExtClock (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  return (EXTERNAL_CLOCK_DFLT);
+}
+
+/* -----------------------------------------------------------------------------*/
+CONST PROC_FAMILY_TABLE ROMDATA ProcFamily16KbDmiTable =
+{
+// This table is for Processor family 16h Kabini
+  AMD_FAMILY_16_KB,               // ID for Family 16h Kabini
+  DmiF16KbGetInfo,                // Transfer vectors for family
+  DmiF16KbGetT4ProcFamily,        // Get type 4 processor family information
+  DmiF16KbGetVoltage,             //   specific routines (above)
+  DmiF16GetMaxSpeed,
+  DmiF16KbGetExtClock,
+  DmiF16KbGetMemInfo,             // Get memory information
+  0,
+  NULL
+};
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
new file mode 100644
index 0000000000..02e5df92af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBEQUIVALENCETABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF16KbMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **KbEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST UINT16 ROMDATA stu1[] =
+{
+  0x7001, 0x7001,
+  0x7000, 0x7000
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  KbEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF16KbMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **KbEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrDeCfg;
+
+  LibAmdMsrRead (0xC0011029, &MsrDeCfg, StdHeader);
+  if ((MsrDeCfg & BIT12) == 0) {
+  } else {
+    *NumberOfElements = ((sizeof (stu1) / sizeof (UINT16)) / 2);
+    *KbEquivalenceTablePtr = stu1;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c
new file mode 100644
index 0000000000..9b93e4512d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbHtc.c
@@ -0,0 +1,178 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini thermal initialization
+ *
+ * Performs processor thermal initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 85817 $   @e \$Date: 2013-01-11 16:58:12 -0600 (Fri, 11 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "CommonReturns.h"
+#include "cpuFeatures.h"
+#include "cpuHtc.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "Gnb.h"
+#include "GnbPcie.h"
+#include "GnbRegistersKB.h"
+#include "GnbRegisterAccKB.h"
+#include "GnbHandleLib.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBHTC_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+STATIC
+F16KbInitializeHtc (
+  IN       HTC_FAMILY_SERVICES    *HtcServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *    Main entry point for initializing the Thermal Control
+ *    safety net feature.
+ *
+ *    This must be run by all Family 16h Kabini core 0s in the system.
+ *
+ * @param[in]  HtcServices             The current CPU's family services.
+ * @param[in]  EntryPoint              Timepoint designator.
+ * @param[in]  PlatformConfig          Platform profile/build option config structure.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F16KbInitializeHtc (
+  IN       HTC_FAMILY_SERVICES    *HtcServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                         HtcTempLimit;
+  NB_CAPS_REGISTER               NbCaps;
+  HTC_REGISTER                   HtcReg;
+  CLK_PWR_TIMING_CTRL2_REGISTER  Cptc2;
+  POPUP_PSTATE_REGISTER          PopUpPstate;
+  PCI_ADDR                       PciAddress;
+  UINT32                         D0F0xBC_xC0107097;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+    if (NbCaps.HtcCapable == 1) {
+      // Enable HTC
+      PciAddress.Address.Register = HTC_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
+      GnbRegisterReadKB (GnbGetHandle (StdHeader), 0x4, 0xC0107097, &D0F0xBC_xC0107097, 0, StdHeader);
+      HtcReg.HtcTmpLmt = (D0F0xBC_xC0107097 >> 3) & 0x7F;
+      if (HtcReg.HtcTmpLmt != 0) {
+        // Enable HTC
+        HtcReg.HtcEn = 1;
+        PciAddress.Address.Register = CPTC2_REG;
+        LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2, StdHeader);
+        if (HtcReg.HtcPstateLimit > Cptc2.HwPstateMaxVal) {
+          // F3xDC[HwPstateMaxVal] = F3x64[HtcPstateLimit]
+          Cptc2.HwPstateMaxVal = HtcReg.HtcPstateLimit;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2, StdHeader);
+          // F3xA8[PopDownPstate] = F3xDC[HwPstateMaxVal]
+          PciAddress.Address.Register = POPUP_PSTATE_REG;
+          LibAmdPciRead (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
+          PopUpPstate.PopDownPstate = Cptc2.HwPstateMaxVal;
+          LibAmdPciWrite (AccessWidth32, PciAddress, &PopUpPstate, StdHeader);
+        }
+        if ((PlatformConfig->HtcTemperatureLimit >= 520) && (PlatformConfig->LhtcTemperatureLimit != 0)) {
+          HtcTempLimit = ((PlatformConfig->HtcTemperatureLimit - 520) / 5);
+          if (HtcTempLimit < HtcReg.HtcTmpLmt) {
+            HtcReg.HtcTmpLmt = HtcTempLimit;
+          }
+        }
+      } else {
+        // Disable HTC
+        HtcReg.HtcEn = 0;
+      }
+      PciAddress.Address.Register = HTC_REG;
+      IDS_OPTION_HOOK (IDS_HTC_CTRL, &HtcReg, StdHeader);
+      LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader);
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+CONST HTC_FAMILY_SERVICES ROMDATA F16KbHtcSupport =
+{
+  0,
+  (PF_HTC_IS_SUPPORTED) CommonReturnTrue,
+  F16KbInitializeHtc
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
new file mode 100644
index 0000000000..9c0e54baca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
@@ -0,0 +1,143 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize the Family 16h Kabini specific way of running early initialization.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x16/KB
+ * @e \$Revision: 86705 $   @e \$Date: 2013-01-24 17:34:21 -0600 (Thu, 24 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[];
+extern CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitAfterApLaunchOnCoreTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GetF16KbEarlyInitBeforeApLaunchOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+
+VOID
+GetF16KbEarlyInitAfterApLaunchOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly (Before AP launch) to return the steps that a
+ * processor that uses the standard initialization steps should take.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetF16KbEarlyInitBeforeApLaunchOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  *Table = F16KbEarlyInitBeforeApLaunchOnCoreTable;
+}
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly (After AP launch) to return the steps that a
+ * processor that uses the standard initialization steps should take.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetF16KbEarlyInitAfterApLaunchOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  *Table = F16KbEarlyInitAfterApLaunchOnCoreTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c
new file mode 100644
index 0000000000..d3923d6a75
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbIoCstate.c
@@ -0,0 +1,371 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini IO C-state feature support functions.
+ *
+ * Provides the functions necessary to initialize the IO C-state feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "cpuIoCstate.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBIOCSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F16KbInitializeIoCstateOnCore (
+  IN       VOID *CstateBaseMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F16KbIsCsdObjGenerated (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            IoCstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable IO Cstate on a family 16h Kabini CPU.
+ *  Implement BIOS Requirements for Initialization of C-states
+ *
+ * @param[in]    IoCstateServices   Pointer to this CPU's IO Cstate family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F16KbInitializeIoCstate (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT64                    EntryPoint,
+  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64                              LocalMsrRegister;
+  AP_TASK                             TaskPtr;
+  PCI_ADDR                            PciAddress;
+  CSTATE_POLICY_CTRL1_REGISTER        CstatePolicyCtrl1;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
+    // Initialize F4x128
+    // bit[4:2] HaltCstateIndex = 0
+    PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
+    CstatePolicyCtrl1.HaltCstateIndex = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader);
+
+    // Initialize MSRC001_0073[CstateAddr] on each core to a region of
+    // the IO address map with 8 consecutive available addresses.
+    LocalMsrRegister = 0;
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "    Init IO C-state Base at 0x%x\n", PlatformConfig->CStateIoBaseAddress);
+    ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+
+    TaskPtr.FuncAddress.PfApTaskI = F16KbInitializeIoCstateOnCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable CState on a family 16h Kabini core.
+ *
+ * @param[in]    CstateBaseMsr      MSR value to write to C001_0073 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F16KbInitializeIoCstateOnCore (
+  IN       VOID *CstateBaseMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // Initialize MSRC001_0073[CstateAddr] on each core
+  LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the size of CST object
+ *
+ * @param[in]    IoCstateServices   IO Cstate services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       CstObjSize         Size of CST Object
+ *
+ */
+UINT32
+STATIC
+F16KbGetAcpiCstObj (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  BOOLEAN                   GenerateCsdObj;
+  UINT32                    CStateAcpiObjSize;
+  IO_CSTATE_FAMILY_SERVICES *FamilyServices;
+  ACPI_CST_GET_INPUT CstGetInput;
+
+  CstGetInput.IoCstateServices = IoCstateServices;
+  CstGetInput.PlatformConfig = PlatformConfig;
+  CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize;
+
+  IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) {
+    CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE;
+
+    // If CSD Object is generated, add the size of CSD Object to the total size of
+    // CState ACPI Object size
+    GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
+
+    if (GenerateCsdObj) {
+      CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE;
+    }
+  }
+  return CStateAcpiObjSize;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Routine to generate the C-State ACPI objects
+ *
+ * @param[in]      IoCstateServices       IO Cstate services.
+ * @param[in]      LocalApicId            Local Apic Id for each core.
+ * @param[in, out] **PstateAcpiBufferPtr  Pointer to the Acpi Buffer Pointer.
+ * @param[in]      StdHeader              Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F16KbCreateAcpiCstObj (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT8                     LocalApicId,
+  IN OUT   VOID                      **PstateAcpiBufferPtr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64                MsrData;
+  BOOLEAN               GenerateCsdObj;
+  CST_HEADER_STRUCT     *CstHeaderPtr;
+  CST_BODY_STRUCT       *CstBodyPtr;
+  CSD_HEADER_STRUCT     *CsdHeaderPtr;
+  CSD_BODY_STRUCT       *CsdBodyPtr;
+  IO_CSTATE_FAMILY_SERVICES    *FamilyServices;
+  ACPI_CST_CREATE_INPUT  CstInput;
+
+  CstInput.IoCstateServices = IoCstateServices;
+  CstInput.LocalApicId = LocalApicId;
+  CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr;
+
+  IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) {
+    // Read from MSR C0010073 to obtain CstateAddr
+    LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
+
+    // Typecast the pointer
+    CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
+
+    // Set CST Header
+    CstHeaderPtr->NameOpcode  = NAME_OPCODE;
+    CstHeaderPtr->CstName_a__ = CST_NAME__;
+    CstHeaderPtr->CstName_a_C = CST_NAME_C;
+    CstHeaderPtr->CstName_a_S = CST_NAME_S;
+    CstHeaderPtr->CstName_a_T = CST_NAME_T;
+
+    // Typecast the pointer
+    CstHeaderPtr++;
+    CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
+
+    // Set CST Body
+    CstBodyPtr->PkgOpcode      = PACKAGE_OPCODE;
+    CstBodyPtr->PkgLength      = CST_LENGTH;
+    CstBodyPtr->PkgElements    = CST_NUM_OF_ELEMENTS;
+    CstBodyPtr->BytePrefix     = BYTE_PREFIX_OPCODE;
+    CstBodyPtr->Count          = CST_COUNT;
+    CstBodyPtr->PkgOpcode2     = PACKAGE_OPCODE;
+    CstBodyPtr->PkgLength2     = CST_PKG_LENGTH;
+    CstBodyPtr->PkgElements2   = CST_PKG_ELEMENTS;
+    CstBodyPtr->BufferOpcode   = BUFFER_OPCODE;
+    CstBodyPtr->BufferLength   = CST_SUBPKG_LENGTH;
+    CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
+    CstBodyPtr->BufferOpcode2  = BUFFER_OPCODE;
+    CstBodyPtr->GdrOpcode      = GENERIC_REG_DESCRIPTION;
+    CstBodyPtr->GdrLength      = CST_GDR_LENGTH;
+    CstBodyPtr->AddrSpaceId    = GDR_ASI_SYSTEM_IO;
+    CstBodyPtr->RegBitWidth    = 0x08;
+    CstBodyPtr->RegBitOffset   = 0x00;
+    CstBodyPtr->AddressSize    = GDR_ASZ_BYTE_ACCESS;
+    CstBodyPtr->RegisterAddr   = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
+    CstBodyPtr->EndTag         = 0x0079;
+    CstBodyPtr->BytePrefix2    = BYTE_PREFIX_OPCODE;
+    CstBodyPtr->Type           = CST_C2_TYPE;
+    CstBodyPtr->WordPrefix     = WORD_PREFIX_OPCODE;
+    CstBodyPtr->Latency        = 400;
+    CstBodyPtr->DWordPrefix    = DWORD_PREFIX_OPCODE;
+    CstBodyPtr->Power          = 0;
+
+    CstBodyPtr++;
+    //Update the pointer
+    *PstateAcpiBufferPtr = CstBodyPtr;
+
+
+  // Check whether CSD object should be generated
+    GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader);
+
+    if (GenerateCsdObj) {
+      CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr;
+
+      // Set CSD Header
+      CsdHeaderPtr->NameOpcode  = NAME_OPCODE;
+      CsdHeaderPtr->CsdName_a__ = CST_NAME__;
+      CsdHeaderPtr->CsdName_a_C = CST_NAME_C;
+      CsdHeaderPtr->CsdName_a_S = CST_NAME_S;
+      CsdHeaderPtr->CsdName_a_D = CSD_NAME_D;
+
+      CsdHeaderPtr++;
+      CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr;
+
+      // Set CSD Body
+      CsdBodyPtr->PkgOpcode         = PACKAGE_OPCODE;
+      CsdBodyPtr->PkgLength         = CSD_BODY_SIZE - 1;
+      CsdBodyPtr->PkgElements       = 1;
+      CsdBodyPtr->PkgOpcode2        = PACKAGE_OPCODE;
+      CsdBodyPtr->PkgLength2        = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode
+      CsdBodyPtr->PkgElements2      = 6;
+      CsdBodyPtr->BytePrefix        = BYTE_PREFIX_OPCODE;
+      CsdBodyPtr->NumEntries        = 6;
+      CsdBodyPtr->BytePrefix2       = BYTE_PREFIX_OPCODE;
+      CsdBodyPtr->Revision          = 0;
+      CsdBodyPtr->DWordPrefix       = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->Domain            = (LocalApicId & 0xFE) >> 1;
+      CsdBodyPtr->DWordPrefix2      = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->CoordType         = CSD_COORD_TYPE_HW_ALL;
+      CsdBodyPtr->DWordPrefix3      = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->NumProcessors     = 0x2;
+      CsdBodyPtr->DWordPrefix4      = DWORD_PREFIX_OPCODE;
+      CsdBodyPtr->Index             = 0x0;
+
+      CsdBodyPtr++;
+
+      // Update the pointer
+      *PstateAcpiBufferPtr = CsdBodyPtr;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Routine to check whether CSD object should be created.
+ *
+ * @param[in]      IoCstateServices      IO Cstate services.
+ * @param[in]      StdHeader             Config Handle for library, services.
+ *
+ * @retval         TRUE                  CSD Object should be created.
+ * @retval         FALSE                 CSD Object should not be created.
+ *
+ */
+BOOLEAN
+F16KbIsCsdObjGenerated (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  // CSD Object should only be created when there are two cores per compute unit
+  if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F16KbIoCstateSupport =
+{
+  0,
+  (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
+  F16KbInitializeIoCstate,
+  F16KbGetAcpiCstObj,
+  F16KbCreateAcpiCstObj,
+  F16KbIsCsdObjGenerated
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c
new file mode 100644
index 0000000000..97affa017c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBLOGICALIDTABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF16KbLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **KbIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF16KbLogicalIdAndRevArray[] =
+{
+  {
+    0x7001,
+    AMD_F16_KB_A1
+  },
+  {
+    0x7000,
+    AMD_F16_KB_A0
+  },
+};
+
+VOID
+GetF16KbLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **KbIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF16KbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *KbIdPtr = CpuF16KbLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_16_KB;
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c
new file mode 100644
index 0000000000..5a010ae1a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c
@@ -0,0 +1,3539 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD F16Kb Microcode patch.
+ *
+ * F16Kb Microcode Patch rev 0700002A for 7000 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84798 $   @e \$Date: 2012-12-19 21:26:23 -0600 (Wed, 19 Dec 2012) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// Encrypt Patch code 0700002A for 7000 and equivalent
+
+CONST UINT8 ROMDATA arr1 [IDS_PAD_4K] =
+{
+  0x12,
+  0x20,
+  0x18,
+  0x12,
+  0x2a,
+  0x00,
+  0x00,
+  0x07,
+  0x03,
+  0x80,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x70,
+  0x00,
+  0x00,
+  0x00,
+  0xaa,
+  0xaa,
+  0xaa,
+  0x49,
+  0x98,
+  0x47,
+  0x92,
+  0x9e,
+  0x94,
+  0x1c,
+  0x90,
+  0x43,
+  0x82,
+  0xfb,
+  0x61,
+  0x5c,
+  0xc3,
+  0x8a,
+  0xb1,
+  0xd7,
+  0x77,
+  0xc5,
+  0x2f,
+  0xe2,
+  0x32,
+  0x8e,
+  0xa2,
+  0xfe,
+  0x17,
+  0x86,
+  0x8b,
+  0xea,
+  0xf8,
+  0x9c,
+  0x9a,
+  0xdb,
+  0x75,
+  0x44,
+  0x1c,
+  0x12,
+  0xd5,
+  0x0f,
+  0x64,
+  0x9f,
+  0x29,
+  0x38,
+  0x9c,
+  0xec,
+  0xfd,
+  0x20,
+  0xb9,
+  0x5c,
+  0x11,
+  0xfa,
+  0xac,
+  0xde,
+  0xa7,
+  0xaf,
+  0xb2,
+  0x71,
+  0x1b,
+  0x5d,
+  0x8d,
+  0x0a,
+  0x84,
+  0xff,
+  0xae,
+  0x77,
+  0xef,
+  0xee,
+  0xe8,
+  0xb9,
+  0xe4,
+  0x4c,
+  0xcf,
+  0x43,
+  0x69,
+  0xda,
+  0x62,
+  0x85,
+  0x56,
+  0x75,
+  0xf4,
+  0xa9,
+  0x9e,
+  0x2a,
+  0x63,
+  0x6d,
+  0xdd,
+  0xcb,
+  0x04,
+  0x18,
+  0xeb,
+  0xa5,
+  0xab,
+  0x8d,
+  0xd7,
+  0x03,
+  0x48,
+  0x71,
+  0x18,
+  0x18,
+  0x3e,
+  0xff,
+  0x33,
+  0x60,
+  0xb0,
+  0x43,
+  0x6c,
+  0xa3,
+  0xc6,
+  0x78,
+  0x0a,
+  0xc8,
+  0x88,
+  0x0b,
+  0x85,
+  0x34,
+  0x41,
+  0x72,
+  0xe7,
+  0x2f,
+  0xac,
+  0x22,
+  0x75,
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+  0xbf,
+  0x97,
+  0x5b,
+  0x02,
+  0x00,
+  0x57,
+  0xdc,
+  0x38,
+  0x00,
+  0xc0,
+  0xdf,
+  0xdb,
+  0xeb,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0x9b,
+  0x5b,
+  0x06,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xbc,
+  0xa8,
+  0x3e,
+  0x11,
+  0x69,
+  0xce,
+  0x06,
+  0x3f,
+  0xb9,
+  0x87,
+  0xd7,
+  0xdd,
+  0xc6,
+  0x12,
+  0xb6,
+  0xe2,
+  0xc2,
+  0x53,
+  0x20,
+  0xfb,
+  0xea,
+  0x71,
+  0x72,
+  0xb5,
+  0xe1,
+  0xa6,
+  0xd8,
+  0xee,
+  0x9d,
+  0x97,
+  0xe6,
+  0x72,
+  0x3f,
+  0x73,
+  0x88,
+  0xed,
+  0x14,
+  0x8c,
+  0xdf,
+  0x5d,
+  0x8f,
+  0x0d,
+  0xd0,
+  0x70,
+  0x64,
+  0x1c,
+  0x06,
+  0x7f,
+  0x59,
+  0x93,
+  0x32,
+  0x55,
+  0x2a,
+  0x10,
+  0x61,
+  0xde,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c
new file mode 100644
index 0000000000..85bdc4e582
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c
@@ -0,0 +1,3539 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD F16Kb Microcode patch.
+ *
+ * F16Kb Microcode Patch rev 07000106 for 7001 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 86822 $   @e \$Date: 2013-01-28 00:17:14 -0500 (Mon, 28 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// Encrypt Patch code 07000106 for 7001 and equivalent
+
+CONST UINT8 ROMDATA arr2 [IDS_PAD_4K] =
+{
+  0x13,
+  0x20,
+  0x22,
+  0x01,
+  0x06,
+  0x01,
+  0x00,
+  0x07,
+  0x03,
+  0x80,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x01,
+  0x70,
+  0x00,
+  0x00,
+  0x00,
+  0xaa,
+  0xaa,
+  0xaa,
+  0x49,
+  0x66,
+  0xa8,
+  0x8e,
+  0x7a,
+  0x20,
+  0xc7,
+  0xae,
+  0xe4,
+  0xf4,
+  0xb4,
+  0x4a,
+  0x32,
+  0x58,
+  0xbb,
+  0x8b,
+  0x60,
+  0x57,
+  0x0e,
+  0x35,
+  0x36,
+  0xda,
+  0x53,
+  0x69,
+  0xb7,
+  0xaf,
+  0x84,
+  0xe0,
+  0x66,
+  0x54,
+  0x71,
+  0x2a,
+  0xef,
+  0x0f,
+  0xf0,
+  0x0e,
+  0x9d,
+  0x5a,
+  0xbe,
+  0xbe,
+  0x19,
+  0x2a,
+  0xe1,
+  0x53,
+  0xdf,
+  0x30,
+  0x15,
+  0xe9,
+  0x9e,
+  0xa2,
+  0xb4,
+  0x74,
+  0x0f,
+  0xfa,
+  0x38,
+  0x6e,
+  0x5c,
+  0x08,
+  0xa5,
+  0xe5,
+  0xd7,
+  0xc3,
+  0x24,
+  0x04,
+  0x5c,
+  0x6e,
+  0xf5,
+  0x57,
+  0xb6,
+  0x2e,
+  0x41,
+  0x1d,
+  0x5d,
+  0xa2,
+  0x62,
+  0x9c,
+  0xce,
+  0x79,
+  0xfb,
+  0xd8,
+  0xda,
+  0x01,
+  0x36,
+  0xfe,
+  0xcf,
+  0x18,
+  0x78,
+  0xcd,
+  0x8b,
+  0x49,
+  0x92,
+  0x0a,
+  0x59,
+  0x40,
+  0x8f,
+  0xc9,
+  0x3e,
+  0xf6,
+  0xd7,
+  0xea,
+  0x78,
+  0x89,
+  0xc1,
+  0xea,
+  0xf8,
+  0x2e,
+  0x35,
+  0xf8,
+  0xfb,
+  0x15,
+  0x48,
+  0x8f,
+  0x07,
+  0xd4,
+  0x3f,
+  0x1f,
+  0x85,
+  0x38,
+  0x87,
+  0x17,
+  0x38,
+  0x23,
+  0x9b,
+  0xcc,
+  0x4a,
+  0xea,
+  0xfd,
+  0x49,
+  0x5a,
+  0xfe,
+  0xb6,
+  0x11,
+  0x21,
+  0xa6,
+  0x5d,
+  0x26,
+  0x5a,
+  0x2e,
+  0xc9,
+  0x49,
+  0x4a,
+  0x2a,
+  0x5b,
+  0xc7,
+  0x8f,
+  0xde,
+  0x65,
+  0x27,
+  0xfd,
+  0x9d,
+  0x59,
+  0x02,
+  0xf9,
+  0xad,
+  0x13,
+  0x4a,
+  0x19,
+  0xb9,
+  0x63,
+  0x1b,
+  0x94,
+  0xd8,
+  0x24,
+  0x87,
+  0xd2,
+  0xfc,
+  0x1d,
+  0x4f,
+  0xa2,
+  0xf1,
+  0xf1,
+  0x4e,
+  0x1a,
+  0x8e,
+  0x7a,
+  0xbd,
+  0xaf,
+  0xd4,
+  0x24,
+  0x07,
+  0x3b,
+  0x43,
+  0x2d,
+  0xe3,
+  0xbf,
+  0xc3,
+  0x03,
+  0x4c,
+  0x81,
+  0x9b,
+  0xec,
+  0x8a,
+  0x91,
+  0x7b,
+  0x1c,
+  0xe0,
+  0x70,
+  0xa4,
+  0x3f,
+  0x83,
+  0x4d,
+  0xa5,
+  0x4b,
+  0x9d,
+  0xbe,
+  0xfe,
+  0xdf,
+  0xed,
+  0xb8,
+  0xa9,
+  0x0e,
+  0xe1,
+  0x11,
+  0x71,
+  0x4d,
+  0xfa,
+  0x27,
+  0x32,
+  0x5c,
+  0xd1,
+  0xe9,
+  0x84,
+  0xbb,
+  0xeb,
+  0x65,
+  0x19,
+  0x09,
+  0xc9,
+  0x2f,
+  0x0c,
+  0x80,
+  0x14,
+  0x3f,
+  0x94,
+  0x1f,
+  0xcd,
+  0xaf,
+  0x29,
+  0x51,
+  0x7c,
+  0x88,
+  0x36,
+  0xf3,
+  0xcb,
+  0x41,
+  0x20,
+  0xcb,
+  0x4c,
+  0x1c,
+  0x4b,
+  0xb2,
+  0xaa,
+  0x6c,
+  0x2c,
+  0xab,
+  0x37,
+  0x5b,
+  0x2a,
+  0x58,
+  0x44,
+  0x53,
+  0xdf,
+  0x59,
+  0xbc,
+  0x14,
+  0xe3,
+  0x7f,
+  0xd6,
+  0x4a,
+  0xd6,
+  0x98,
+  0x59,
+  0x8c,
+  0xbb,
+  0xce,
+  0xe6,
+  0x86,
+  0xdb,
+  0x66,
+  0xbd,
+  0xeb,
+  0x51,
+  0xf1,
+  0xce,
+  0x80,
+  0x0f,
+  0xd9,
+  0x83,
+  0x86,
+  0x17,
+  0xed,
+  0x78,
+  0x3e,
+  0x5d,
+  0xac,
+  0xd1,
+  0x13,
+  0xfa,
+  0x01,
+  0x58,
+  0x35,
+  0xe9,
+  0x66,
+  0x16,
+  0x5d,
+  0xa8,
+  0x70,
+  0x08,
+  0x0e,
+  0xa3,
+  0xab,
+  0x3b,
+  0xd1,
+  0x75,
+  0xbf,
+  0x2f,
+  0xb2,
+  0x9a,
+  0x7c,
+  0xd8,
+  0x84,
+  0x66,
+  0x1a,
+  0x07,
+  0x00,
+  0xe0,
+  0x04,
+  0xbf,
+  0x0e,
+  0x04,
+  0xaa,
+  0x0e,
+  0x91,
+  0x6f,
+  0xb4,
+  0xb8,
+  0xff,
+  0xfa,
+  0xad,
+  0xb0,
+  0xd8,
+  0x41,
+  0x65,
+  0xf5,
+  0xd5,
+  0x0d,
+  0x12,
+  0x15,
+  0xbf,
+  0x40,
+  0x5b,
+  0xed,
+  0xeb,
+  0x81,
+  0x2a,
+  0x1f,
+  0x48,
+  0x00,
+  0x5b,
+  0xf7,
+  0x08,
+  0x35,
+  0x86,
+  0x8d,
+  0xe4,
+  0x15,
+  0x52,
+  0x40,
+  0x1b,
+  0x88,
+  0x5a,
+  0x8f,
+  0xd0,
+  0x4f,
+  0xb5,
+  0xbc,
+  0xdb,
+  0x45,
+  0x30,
+  0xc5,
+  0x89,
+  0x32,
+  0x98,
+  0xf9,
+  0xa7,
+  0x18,
+  0x27,
+  0xf1,
+  0x0b,
+  0xc7,
+  0x6d,
+  0xeb,
+  0x7f,
+  0x39,
+  0xd2,
+  0x25,
+  0x99,
+  0x6d,
+  0x3a,
+  0x1b,
+  0x24,
+  0xa4,
+  0xc5,
+  0x7c,
+  0xdf,
+  0x33,
+  0x3d,
+  0x7c,
+  0x43,
+  0x40,
+  0x5b,
+  0x8d,
+  0xd1,
+  0xec,
+  0x0c,
+  0xca,
+  0x76,
+  0xd9,
+  0x1a,
+  0x32,
+  0xee,
+  0x45,
+  0xee,
+  0xb6,
+  0x30,
+  0x21,
+  0xf8,
+  0x66,
+  0xb5,
+  0xbf,
+  0xfb,
+  0x66,
+  0x13,
+  0x9c,
+  0xf0,
+  0xcf,
+  0xae,
+  0xca,
+  0x54,
+  0xbc,
+  0xf1,
+  0xce,
+  0x76,
+  0x57,
+  0x8d,
+  0xf5,
+  0xee,
+  0x02,
+  0x14,
+  0xc0,
+  0x62,
+  0x3f,
+  0xa1,
+  0xad,
+  0x9d,
+  0xbb,
+  0x83,
+  0x3d,
+  0x8f,
+  0xf2,
+  0xe9,
+  0x41,
+  0x42,
+  0xca,
+  0x04,
+  0xf9,
+  0xf7,
+  0x4f,
+  0xf7,
+  0xc6,
+  0x77,
+  0xf0,
+  0x0e,
+  0x8c,
+  0xea,
+  0xb6,
+  0x6c,
+  0x47,
+  0xae,
+  0xd1,
+  0x1b,
+  0x2c,
+  0x89,
+  0xbf,
+  0x4b,
+  0x61,
+  0xdc,
+  0x2d,
+  0x06,
+  0x6d,
+  0x79,
+  0x5c,
+  0x5e,
+  0x82,
+  0xc0,
+  0x4f,
+  0x54,
+  0x5d,
+  0x68,
+  0x55,
+  0x5b,
+  0x1c,
+  0x75,
+  0xb6,
+  0xcc,
+  0x4b,
+  0xb6,
+  0x3e,
+  0x2b,
+  0xec,
+  0x30,
+  0xa7,
+  0x90,
+  0xd8,
+  0x99,
+  0x44,
+  0x85,
+  0xe7,
+  0x21,
+  0x33,
+  0x00,
+  0x48,
+  0xf3,
+  0xbb,
+  0x92,
+  0xe9,
+  0x48,
+  0x99,
+  0x45,
+  0x66,
+  0xd5,
+  0xe6,
+  0xd9,
+  0x9e,
+  0x92,
+  0x8b,
+  0x42,
+  0x94,
+  0xa3,
+  0x2f,
+  0x44,
+  0xb1,
+  0x5e,
+  0x07,
+  0xd7,
+  0x0a,
+  0xb4,
+  0x7b,
+  0x49,
+  0x7e,
+  0x15,
+  0xab,
+  0x34,
+  0x6b,
+  0xff,
+  0x1f,
+  0xcf,
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+  0xff,
+  0xbf,
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+  0xff,
+  0xbf,
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+  0x00,
+  0xe1,
+  0x1f,
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+  0xbf,
+  0xff,
+  0x81,
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+  0x00,
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+  0x1f,
+  0xc0,
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+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
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+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
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+  0x00,
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+  0x1f,
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+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
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+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
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+  0x1f,
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+  0x1f,
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+  0xbf,
+  0xff,
+  0xbf,
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+  0xff,
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+  0xff,
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+  0x00,
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+  0x81,
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+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0x81,
+  0x7f,
+  0x00,
+  0xe1,
+  0x1f,
+  0xc0,
+  0xbf,
+  0xff,
+  0xbf,
+  0x07,
+  0x00,
+  0x13,
+  0x42,
+  0x99,
+  0xf4,
+  0x9c,
+  0x43,
+  0x10,
+  0xb9,
+  0x93,
+  0x17,
+  0x40,
+  0x75,
+  0x1b,
+  0x3d,
+  0x9e,
+  0xa9,
+  0x4f,
+  0xbf,
+  0xac,
+  0x60,
+  0x92,
+  0x6b,
+  0xbb,
+  0x51,
+  0x50,
+  0x1a,
+  0x56,
+  0xc0,
+  0x34,
+  0x59,
+  0xb6,
+  0x4a,
+  0x30,
+  0x0a,
+  0x21,
+  0xa2,
+  0x14,
+  0x1f,
+  0x8d,
+  0x89,
+  0xc4,
+  0x82,
+  0xb0,
+  0x5c,
+  0x8d,
+  0x49,
+  0x3d,
+  0xb8,
+  0x34,
+  0x7a,
+  0x54,
+  0xb2,
+  0xc2,
+  0x0e,
+  0x5b,
+  0xbc,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+  0x00,
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
new file mode 100644
index 0000000000..4790709618
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c
@@ -0,0 +1,111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini microcode patches
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBMICROCODEPATCHTABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF16KbMicroCodePatchArray[];
+extern CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF16KbMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **KbUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  KbUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF16KbMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **KbUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = CpuF16KbNumberOfMicrocodePatches;
+  *KbUcodePtr = &CpuF16KbMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c
new file mode 100644
index 0000000000..12dd300f70
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMsrTables.c
@@ -0,0 +1,264 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 KB MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x16/KB
+ * @e \$Revision: 87267 $   @e \$Date: 2013-01-31 09:34:00 -0600 (Thu, 31 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "F16KbPowerMgmt.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP  (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+NbMcaLock (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//   M S R   T a b l e s
+// ----------------------
+
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F16KbMsrRegisters[] =
+{
+// MSR_TOM2 (0xC001001D)
+// bits[39:23]   TOP_MEM2            = 0x0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                             // PlatformFeatures
+    {{
+      MSR_TOM2,                             // Address
+      0x0000000000000000,                   // RegData
+      0xFFFFFFFFFF800000,                   // RegMask
+    }}
+  },
+
+// MSR_SYS_CFG (0xC0010010)
+// bits[21]      MtrrTom2En          = 0x1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                             // PlatformFeatures
+    {{
+      MSR_SYS_CFG,                          // Address
+      (1 << 21),                            // RegData
+      (1 << 21),                            // RegMask
+    }}
+  },
+// MC4_MISC_1 (0xC0000408)
+// Clear to 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                             // PlatformFeatures
+    {{
+      0xC0000408,                           // Address
+      0x0000000000000000,                   // RegData
+      0xFF0FFFFFFFFFFFFF,                   // RegMask
+    }}
+  },
+// MSR_LS_CFG (C0011020)
+// bits[26]                          = 0x1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MSR_LS_CFG,                           // Address
+      0x0000000004000000,                   // RegData
+      0x0000000004000000,                   // RegMask
+    }}
+  },
+// MSR_IC_CFG (C0011021)
+// bits[26]      DIS_WIDEREAD_PWR_SAVE = 0x1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MSR_IC_CFG,                           // Address
+      0x0000000004000000,                   // RegData
+      0x0000000004000000,                   // RegMask
+    }}
+  },
+// Processor Feedback Constants 0 (C0011090)
+// bits[15:8]    RefCountScale = 0x64
+// bits[7:0]     ActualCountScale = 0xA5
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      0xC0011090,                           // Address
+      0x00000000000064A5,                   // RegData
+      0x000000000000FFFF,                   // RegMask
+    }}
+  },
+// MSR_L2I_CFG (C00110A0)
+// bits[56:45]   L2ScrubberInterval  = 0x100
+// bits[44]      PbDisObeysThrottleNb = 0x1
+// bits[43:40]   ThrottleNbInterface = 0x0
+// bits[19]      McaToMstCoreEn      = 0x1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MSR_L2I_CFG,                          // Address
+      0x0020100000080000,                   // RegData
+      0x01FFFF0000080000,                   // RegMask
+    }}
+  },
+};
+
+//   MSR with Special Programming Requirements Table
+// ----------------------
+
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F16KbMsrWorkarounds[] =
+{
+// MSR_0000_0413
+  {
+    FamSpecificWorkaround,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      NbMcaLock,                            // Function call
+      0x00000000,                           // Data
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F16KbMsrRegisterTable = {
+  AllCores,
+  PERFORM_TP_AFTER_AP_LAUNCH,
+  (sizeof (F16KbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F16KbMsrRegisters,
+};
+
+CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable = {
+  AllCores,
+  PERFORM_TP_AFTER_AP_LAUNCH,
+  (sizeof (F16KbMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F16KbMsrWorkarounds,
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  MSR special programming requirements for MSR_0000_0413
+ *
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+NbMcaLock (
+  IN       UINT32            Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  MC4_MISC0_MSR Mc4Misc0;
+
+  LibAmdMsrRead (MSR_MC4_MISC, (UINT64 *) &Mc4Misc0, StdHeader);
+
+  if (Mc4Misc0.IntType == 0x2) {
+    Mc4Misc0.Locked = 1;
+  } else {
+    Mc4Misc0.Locked = 0;
+  }
+  LibAmdMsrWrite (MSR_MC4_MISC, (UINT64 *) &Mc4Misc0, StdHeader);
+
+  return;
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c
new file mode 100644
index 0000000000..0ab9896db4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c
@@ -0,0 +1,365 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini after warm reset sequence for NB P-states
+ *
+ * Performs the "NB COF and VID Transition Sequence After Warm Reset"
+ * as described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "F16KbNbAfterReset.h"
+#include "Gnb.h"
+#include "GnbPcie.h"
+#include "GnbHandleLib.h"
+#include "GnbRegisterAccKB.h"
+#include "GnbRegistersKB.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBNBAFTERRESET_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F16KbPmNbAfterResetOnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+TransitionToNbLow (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+STATIC
+TransitionToNbHigh (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+STATIC
+WaitForNbTransitionToComplete (
+  IN       PCI_ADDR           PciAddress,
+  IN       UINT32             PstateIndex,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 16h Kabini core 0 entry point for performing the necessary steps after
+ * a warm reset has occurred.
+ *
+ * The steps are as follows:
+ *
+ *   1.    Temp1=D18F5x170[SwNbPstateLoDis].
+ *   2.    Temp2=D18F5x170[NbPstateDisOnP0].
+ *   3.    Temp3=D18F5x170[NbPstateThreshold].
+ *   4.    Temp4=D18F5x170[NbPstateGnbSlowDis].
+ *   5.    If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11.
+ *   6.    Write 1 to D18F5x170[NbPstateGnbSlowDis].
+ *   7.    Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+ *   8.    Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+ *   9.    Set D18F5x170[SwNbPstateLoDis]=1.
+ *   10.   Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15.
+ *   11.   Write 1 to D18F5x170[SwNbPstateLoDis].
+ *   12.   Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+ *   13.   Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+ *   14.   Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
+ *         Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+ *   15.   Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
+ *         stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F16KbPmNbAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Core;
+  UINT32    TaskedCore;
+  UINT32    Ignored;
+  AP_TASK   TaskPtr;
+  AGESA_STATUS IgnoredSts;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbPmNbAfterReset\n");
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+
+  ASSERT (Core == 0);
+
+  // Launch one core per node.
+  TaskPtr.FuncAddress.PfApTask = F16KbPmNbAfterResetOnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) {
+      if (TaskedCore != 0) {
+        ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader);
+      }
+    }
+  }
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F16KbPmNbAfterReset to perform MSR initialization on one
+ * core of each die in a family 16h socket.
+ *
+ * This function implements steps 1 - 15 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F16KbPmNbAfterResetOnCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    NbPsCtrlOnEntry;
+  UINT32    NbPsCtrlOnExit;
+  UINT64    LocalMsrRegister;
+  PCI_ADDR  PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbPmNbAfterResetOnCore\n");
+
+  // 1. Temp1 = D18F5x170[SwNbPstateLoDis].
+  // 2. Temp2 = D18F5x170[NbPstateDisOnP0].
+  // 3. Temp3 = D18F5x170[NbPstateThreshold].
+  // 4. Temp4 = D18F5x170[NbPstateGnbSlowDis].
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader);
+
+  // Check if NB P-states were disabled, and if so, prevent any changes from occurring.
+  if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) {
+    // 5. If MSRC001_0070[NbPstate] = 1, go to step 11
+    LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader);
+    if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) {
+      // 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
+      PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+      ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+
+      // 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+      // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
+      //    CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+      TransitionToNbLow (PciAddress, StdHeader);
+
+      // 9. Set D18F5x170[SwNbPstateLoDis] = 1.
+      // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
+      //     CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+      //     Go to step 15.
+      TransitionToNbHigh (PciAddress, StdHeader);
+    } else {
+      // 11. Set D18F5x170[SwNbPstateLoDis] = 1.
+      // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
+      //     CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+      TransitionToNbHigh (PciAddress, StdHeader);
+
+      // 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+      // 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
+      //     CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+      TransitionToNbLow (PciAddress, StdHeader);
+    }
+
+    // 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
+    //     stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F16KbPmNbAfterResetOnCore to transition to the low NB P-state.
+ *
+ * This function implements steps 7, 8, 13, and 14 as needed.
+ *
+ * @param[in]  PciAddress         Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+TransitionToNbLow (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  TransitionToNbLow\n");
+
+  // 7/13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+  NbPsCtrl.SwNbPstateLoDis = 0;
+  NbPsCtrl.NbPstateDisOnP0 = 0;
+  NbPsCtrl.NbPstateThreshold = 0;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+  // 8/14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid,
+  //       CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
+  WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F16KbPmNbAfterResetOnCore to transition to the high NB P-state.
+ *
+ * This function implements steps 9, 10, 11, and 12 as needed.
+ *
+ * @param[in]  PciAddress         Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+TransitionToNbHigh (
+  IN       PCI_ADDR           PciAddress,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  NB_PSTATE_CTRL_REGISTER   NbPsCtrl;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  TransitionToNbHigh\n");
+
+  // 9/10. Set D18F5x170[SwNbPstateLoDis] = 1.
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+  NbPsCtrl.SwNbPstateLoDis = 1;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+  // 11/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid,
+  //       CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
+  WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F16KbPmAfterResetCore to wait for NB FID and DID to
+ * match a specific P-state.
+ *
+ * This function implements steps 8, 10, 12, and 14 as needed.
+ *
+ * @param[in]  PciAddress         Segment, bus, device number of the node to transition.
+ * @param[in]  PstateIndex        P-state settings to match.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+WaitForNbTransitionToComplete (
+  IN       PCI_ADDR           PciAddress,
+  IN       UINT32             PstateIndex,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  NB_PSTATE_REGISTER       TargetNbPs;
+  NB_PSTATE_STS_REGISTER   NbPsSts;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  WaitForNbTransitionToComplete\n");
+
+  PciAddress.Address.Function = FUNC_5;
+  PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2);
+  LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader);
+  PciAddress.Address.Register = NB_PSTATE_STATUS;
+  do {
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader);
+  } while ((NbPsSts.CurNbPstate != PstateIndex ||
+           (NbPsSts.CurNbFid != TargetNbPs.NbFid)) ||
+           (NbPsSts.CurNbDid != TargetNbPs.NbDid));
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h
new file mode 100644
index 0000000000..0d2c7bcd72
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini after warm reset sequence for NB P-states
+ *
+ * Contains code that provide power management functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F16_KB_NB_AFTER_RESET_H_
+#define _CPU_F16_KB_NB_AFTER_RESET_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F16KbPmNbAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F16_KB_NB_AFTER_RESET_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
new file mode 100644
index 0000000000..4cd445e349
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
@@ -0,0 +1,1147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 KB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x16/KB
+ * @e \$Revision: 86705 $   @e \$Date: 2013-01-24 17:34:21 -0600 (Thu, 24 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "F16KbPowerMgmt.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP  (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+SetDisCstateBoostBlockPstateUp (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+ScalingApmParamBaseOnCSampleTimer (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+SetTdpLimitDis (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//   P C I   T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16KbPciRegistersAfterApLaunch[] =
+{
+// D18F0x6C - Link Initialization Control
+// bits[0]       RouteTblDis         = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
+      0x00000000,                           // RegData
+      0x00000001,                           // RegMask
+    }}
+  },
+// D18F0x84 - Link Control
+// bits[12]       IsocEn             = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x84),  // Address
+      0x00001000,                           // RegData
+      0x00001000,                           // RegMask
+    }}
+  },
+// D18F0x90 - Link Base Channel Buffer Count
+// bits[30]      PReq[3]             = 0x0
+// bits[29:28]   NpReqData[3:2]      = 0x0
+// bits[27:25]   FreeData            = 0x0
+// bits[24:20]   FreeCmd             = 0x0
+// bits[19:18]   RspData             = 0x1
+// bits[17:16]   NpReqData[1:0]      = 0x1
+// bits[15:12]   ProbeCmd            = 0x0
+// bits[11:8]    RspCmd              = 0x1
+// bits[7:5]     PReq[2:0]           = 0x5
+// bits[4:0]     NpReqCmd            = 0x5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90),  // Address
+      0x000501A5,                           // RegData
+      0x7FFFFFFF,                           // RegMask
+    }}
+  },
+// D18F0x94 - Link Isochronous Channel Buffer Count
+// bits[28:27]   IsocRspData         = 0x0
+// bits[26:25]   IsocNpReqData       = 0x1
+// bits[24:22]   IsocRspCmd          = 0x0
+// bits[21:19]   IsocPReq            = 0x0
+// bits[18:16]   IsocNpReqCmd        = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94),  // Address
+      0x02010000,                           // RegData
+      0x1FFF0000,
+    }}
+  },
+// D18F0x90 - Link Base Channel Buffer Count
+// bit [31]      LockBc              = 0x1
+//
+// NOTE: The entry is intended to be programmed after other bits of D18F0x[90, 94] is programmed.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90),  // Address
+      0x80000000,                           // regData
+      0x80000000,                           // regMask
+    }}
+  },
+// D18F0x110 - Link Clumping Enable
+// bits [31:1]   ClumpEn             = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x110), // Address
+      0x00000002,                           // regData
+      0xFFFFFFFE,                           // regMask
+    }}
+  },
+// D18F0x168 - Extended Link Transaction Control
+// bits[20]                          = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x168), // Address
+      0x00100000,                           // RegData
+      0x00100000,                           // RegMask
+    }}
+  },
+
+// D18F2x118 - Memory Controller Configuration Low
+// bits[31:28]   MctVarPriCntLmt     = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
+      0x10000000,                           // RegData
+      0xF0000000,                           // RegMask
+    }}
+  },
+// D18F3x44 - MCA NB Configuration
+// bits[30]      SyncFloodOnDramAdrParErr = 0x1
+// bits[27]      NbMcaToMstCpuEn     = 0x1
+// bits[21]      SyncFloodOnAnyUcErr = 0x1
+// bits[20]      SyncFloodOnWDT      = 0x1
+// bits[6]       CpuErrDis           = 0x1
+// bits[4]       SyncPktPropDis      = 0x0
+// bits[3]       SyncPktGenDis       = 0x0
+// bits[2]       SyncFloodOnDramUcEcc = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
+      0x48300044,                           // RegData
+      0x4830005C,                           // RegMask
+    }}
+  },
+// D18F3x6C - Data Buffer Count
+// bits[30:28]   IsocRspDBC          = 0x1
+// bits[18:16]   UpRspDBC            = 0x1
+// bits[7:6]     DnRspDBC            = 0x1
+// bits[5:4]     DnReqDBC            = 0x1
+// bits[2:0]     UpReqDBC            = 0x2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10010052,                           // RegData
+      0x700700F7,                           // RegMask
+    }}
+  },
+// D18F3x70 - SRI to XBAR Command Buffer Count
+// bits[30:28]   IsocRspCBC          = 0x1
+// bits[26:24]   IsocPreqCBC         = 0x0
+// bits[22:20]   IsocReqCBC          = 0x1
+// bits[18:16]   UpRspCBC            = 0x3
+// bits[14:12]   DnPreqCBC           = 0x1
+// bits[10:8]    UpPreqCBC           = 0x1
+// bits[7:6]     DnRspCBC            = 0x1
+// bits[5:4]     DnReqCBC            = 0x1
+// bits[2:0]     UpReqCBC            = 0x3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x10131153,                           // RegData
+      0x777777F7,                           // RegMask
+    }}
+  },
+// D18F3x74 - XBAR to SRI Command Buffer Count
+// bits[31:28]   DRReqCBC            = 0x0
+// bits[26:24]   IsocPreqCBC         = 0x1
+// bits[23:20]   IsocReqCBC          = 0x1
+// bits[19:16]   ProbeCBC            = 0xC
+// bits[14:12]   DnPreqCBC           = 0x0
+// bits[10:8]    UpPreqCBC           = 0x1
+// bits[6:4]     DnReqCBC            = 0x0
+// bits[2:0]     UpReqCBC            = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x011C0101,                           // RegData
+      0xF7FF7777,                           // RegMask
+    }}
+  },
+// D18F3x78 - MCT to XBAR Buffer Count
+// bits[12:8]    ProbeCBC            = 0x8
+// bits[5:0]     RspCBC              = 0x10
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x78),  // Address
+      0x00000810,                           // RegData
+      0x00001F3F,                           // RegMask
+    }}
+  },
+
+// D18F3x7C - Free List Buffer Count
+// bits[22:20]   Sri2XbarFreeRspDBC  = 0x0
+// bits[19:16]   Sri2XbarFreeXreqDBC = 0x5
+// bits[15:12]   Sri2XbarFreeRspCBC  = 0x0
+// bits[11:8]    Sri2XbarFreeXreqCBC = 0x6
+// bits[5:0]     Xbar2SriFreeListCBC = 0x1B
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0005061B,                           // RegData
+      0x007FFF3F,                           // RegMask
+    }}
+  },
+// D18F3x84 - ACPI Power State Control High
+// bits[1]       NbLowPwrEnSmafAct4  = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
+      0x00000002,                           // RegData
+      0x00000002,                           // RegMask
+    }}
+  },
+// D18F3xA0 - Power Control Miscellaneous
+// bits[13:11]   PllLockTime         = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00000800,                           // RegData
+      0x00003800,                           // RegMask
+    }}
+  },
+// D18F3xA0 - Power Control Miscellaneous
+// bits[14]      Svi2HighFreqSel     = 0x1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00004000,                           // regData
+      0x00004000,                           // regMask
+    }}
+  },
+// D18F3xA4 - Reported Temperature Control
+// bits[12:8]    PerStepTimeDn       = 0xF
+// bits[7]       TmpSlewDnEn         = 0x1
+// bits[6:5]     TmpMaxDiffUp        = 0x3
+// bits[4:0]     PerStepTimeUp       = 0xF
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),  // Address
+      0x00000FEF,                           // RegData
+      0x00001FFF,                           // RegMask
+    }}
+  },
+// D18F3xD4 - Clock Power/Timing Control 0
+// bits[31]      NbClkDivApplyAll    = 0x1
+// bits[30:28]   NbClkDiv            = 0x1
+// bits[27:24]   PowerStepUp         = 0x8
+// bits[23:20]   PowerStepDown       = 0x8
+// bits[11:8]    ClkRampHystSel      = 0xF
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0x98800F00,                           // RegData
+      0xFFF00F00,                           // RegMask
+    }}
+  },
+// D18F3xD8 - Clock Power/Timing Control 1
+// bits[6:4]     VSRampSlamTime      = 0x4
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8),  // Address
+      0x00000040,                           // RegData
+      0x00000070,                           // RegMask
+    }}
+  },
+// D18F3xDC - Clock Power/Timing Control 2
+// bits[29:27]   NbsynPtrAdjLo       = 0x5
+// bits[26]      IgnCpuPrbEn         = 0x0
+// bits[25:19]   CacheFlushOnHaltTmr = 0xF
+// bits[18:16]   CacheFlushOnHaltCtl = 0x0
+// bits[14:12]   NbsynPtrAdj         = 0x6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x28786000,                           // RegData
+      0x3FFF7000,                           // RegMask
+    }}
+  },
+// D18F3x140 - SRI to XCS Token Count
+// bits[24:20]   FreeTok             = 0xF
+// bits[17:16]   IsocRspTok          = 0x1
+// bits[15:14]   IsocPreqTok         = 0x0
+// bits[13:12]   IsocReqTok          = 0x1
+// bits[11:10]   DnRspTok            = 0x1
+// bits[9:8]     UpRspTok            = 0x1
+// bits[7:6]     DnPreqTok           = 0x1
+// bits[5:4]     UpPreqTok           = 0x2
+// bits[3:2]     DnReqTok            = 0x1
+// bits[1:0]     UpReqTok            = 0x2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00F11566,                           // RegData
+      0x01F3FFFF,                           // RegMask
+    }}
+  },
+// D18F3x144 - MCT to XCS Token Count
+// bits[7:4]     ProbeTok            = 0x4
+// bits[3:0]     RspTok              = 0x7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000047,                           // RegData
+      0x000000FF,                           // RegMask
+    }}
+  },
+// D18F3x148 - Link to XCS Token Count - Link 0
+// bits[31:30]   FreeTok[3:2]        = 0x0
+// bits[28]      IsocRspTok1         = 0x0
+// bits[26]      IsocPreqTok1        = 0x0
+// bits[24]      IsocReqTok1         = 0x0
+// bits[23:22]   ProbeTok1           = 0x0
+// bits[21:20]   RspTok1             = 0x0
+// bits[19:18]   PReqTok1            = 0x0
+// bits[17:16]   ReqTok1             = 0x0
+// bits[15:14]   FreeTok[1:0]        = 0x0
+// bits[13:12]   IsocRspTok0         = 0x0
+// bits[11:10]   IsocPreqTok0        = 0x1
+// bits[9:8]     IsocReqTok0         = 0x1
+// bits[7:6]     ProbeTok0           = 0x0
+// bits[5:4]     RspTok0             = 0x2
+// bits[3:2]     PReqTok0            = 0x2
+// bits[1:0]     ReqTok0             = 0x2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000052A,                           // RegData
+      0xD5FFFFFF,                           // RegMask
+    }}
+  },
+// D18F3x160 - NB Machine Check Misc (DRAM Thresholding) 0 (MC4_MISC0)
+// bits[23:20]   LvtOffset           = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x160), // Address
+      0x00100000,                           // RegData
+      0x00F00000,                           // RegMask
+    }}
+  },
+// D18F3x168 - NB Machine Check Misc (Link Thresholding) 1 (MC4_MISC1)
+// bits[23:20]   LvtOffset           = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x168), // Address
+      0x00100000,                           // RegData
+      0x00F00000,                           // RegMask
+    }}
+  },
+// D18F3x17C - Extended Freelist Buffer Count
+// bits[3:0]     SPQPrbFreeCBC       = 0x8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address
+      0x00000008,                           // RegData
+      0x0000000F,                           // RegMask
+    }}
+  },
+// D18F3x180 - Extended NB MCA Configuration
+// bits[28]      SyncFloodOnCC6DramUcErr = 0x1
+// bits[24]      McaLogErrAddrWdtErr = 0x1
+// bits[21]      SyncFloodOnCpuLeakErr = 0x1
+// bits[17]      SyncFloodOnDeferErrToIO = 0x1
+// bits[9]       SyncFloodOnUCNbAry  = 0x1
+// bits[8]       SyncFloodOnProtErr  = 0x1
+// bits[7]       SyncFloodOnTgtAbortErr = 0x1
+// bits[6]       SyncFloodOnDatErr   = 0x1
+// bits[5]       DisPciCfgCpuMstAbortRsp = 0x1
+// bits[1]       SyncFloodOnUsPwDatErr = 0x1
+// bits[0]       McaLogUsPwDatErrEn  = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x112203E3,                           // RegData
+      0x112203E3,                           // RegMask
+    }}
+  },
+// bits[9]                           = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00000200,                           // RegData
+      0x00000200,                           // RegMask
+    }}
+  },
+// D18F3x1A0 - Core Interface Buffer Count
+// bits[18:16]   CpuToNbFreeBufCnt   = 0x3
+// bits[2:0]     CpuCmdBufCnt        = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
+      0x00030001,                           // RegData
+      0x00070007,                           // RegMask
+    }}
+  },
+// D18F3x1CC - IBS Control
+// bits[8]       LvtOffsetVal        = 0x1
+// bits[3:0]     LvtOffset           = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
+      0x00000100,                           // RegData
+      0x0000010F,                           // RegMask
+    }}
+  },
+// D18F3x1E4 - SBI Control
+// bits[11:8]    LvtOffset           = 0x3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1E4), // Address
+      0x00000300,                           // RegData
+      0x00000F00,                           // RegMask
+    }}
+  },
+// D18F0x6C - Link Initialization Control
+// bit [30]      RlsLnkFullTokCntImm = 0x1
+// bit [28]      RlsIntFullTokCntImm = 0x1
+//
+// NOTE: The entry is intended to be after D18F0x[90, 94] and D18F3x[6C, 70, 74, 78, 7C, 140, 144, 148, 14C, 17C, 1A0] are programmed.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
+      0x50000000,                           // RegData
+      0x50000000,                           // RegMask
+    }}
+  },
+// D18F0x6C - Link Initialization Control
+// bits[27]      ApplyIsocModeEnNow  = 0x1
+//
+// NOTE: The entry is intended to be after RlsLnkFullTokCntImm and RlsIntFullTokCntImm have been set.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),  // Address
+      0x08000000,                           // RegData
+      0x08000000,                           // RegMask
+    }}
+  },
+// D18F3x200 - Performance Mode Control Register
+// bits[3]       EnMcqPrbPickThrottle = 0x1
+// bits[2]       EnDctOddToNcLnkDatXfr = 0x1
+// bits[1]       EnDctEvnToNcLnkDatXfr = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x200), // Address
+      0x0000000E,                           // RegData
+      0x0000000E,                           // RegMask
+    }}
+  },
+// D18F4x118 - C-state Control 1
+// bits[23:21]   ClkDivisorCstAct1   = 0x0
+// bits[19:18]   CacheFlushTmrSelCstAct1 = 0x2
+// bits[16]      CpuPrbEnCstAct1     = 0x1
+// bits[7:5]     ClkDivisorCstAct0   = 0x0
+// bits[3:2]     CacheFlushTmrSelCstAct0 = 0x2
+// bits[0]       CpuPrbEnCstAct0     = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
+      0x00090009,                           // RegData
+      0x00ED00ED,                           // RegMask
+    }}
+  },
+// D18F4x128 - C-state Policy Control 1
+// bits[24:23]   CacheFlushSucMonMispredictAct = 0x1
+// bits[22:21]   CacheFlushSucMonTmrSel = 0x1
+// bits[20:18]   CacheFlushSucMonThreshold = 0x4
+// bits[11:5]    CacheFlushTmr       = 0x7F
+// bits[4:2]     HaltCstateIndex     = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x128), // Address
+      0x00B00FE0,                           // RegData
+      0x01FC0FFC,                           // RegMask
+    }}
+  },
+// D18F4x15C - Core Performance Boost Control
+// bits[8]       CstatePowerEn       = 0x1
+// bits[1:0]     BoostSrc            = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
+      0x00000100,                           // RegData
+      0x00000103,                           // RegMask
+    }}
+  },
+// D18F4x16C - APM TDP Control
+// bits[14]      CacUpC1             = 0x0
+// bits[4]       ApmTdpLimitIntEn    = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address
+      0x00000010,                           // RegData
+      0x00004010,                           // RegMask
+    }}
+  },
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x210), // Address
+      0x0000B41F,                           // RegData
+      0x0000F7FF,                           // RegMask
+    }}
+  },
+// D18F5x88 - NB Configuration 4 (NB_CFG4)
+// bits[24]      DisHbNpReqBusLock   = 0x1
+// bits[0]       CC6PstateWakeUpDis  = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88),  // Address
+      0x01000001,                           // RegData
+      0x01000001,                           // RegMask
+    }}
+  },
+// D18F5x8C
+// bits[15]                          = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x8C),  // Address
+      0x00008000,                           // RegData
+      0x00008000,                           // RegMask
+    }}
+  },
+// D18F5xE0 - Processor TDP Running Average
+// bits[3:0]     RunAvgRange         = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0),  // Address
+      0x00000001,                           // RegData
+      0x0000000F,                           // RegMask
+    }}
+  },
+// D18F5x128 - Clock Power/Timing Control 3
+// bits[13:12]   PwrGateTmr          = 0x0
+// bits[9]       FastSlamTimeDown    = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x128), // Address
+      0x00000200,                           // RegData
+      0x00003200,                           // RegMask
+    }}
+  },
+// D18F5x12C - Clock Power/Timing Control 4
+// bits[5]       CorePsi1En          = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x12C), // Address
+      0x00000020,                           // RegData
+      0x00000020,                           // RegMask
+    }}
+  },
+// D18F5x170 - Northbridge P-state Control
+// bits[12:9]    NbPstateThreshold   = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x170), // Address
+      0x00000200,                           // RegData
+      0x00001E00,                           // RegMask
+    }}
+  },
+// D18F5x178 - Northbridge Fusion Configuration
+// bits[18]      CstateFusionHsDis   = 0x1
+// bits[17]                          = 0x1
+// bits[16]      ProcHotToGnbEn      = 0x1
+// bits[11]                          = 0x1
+// bits[10]                          = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_5, 0x178), // Address
+      0x00070C00,                           // RegData
+      0x00070C00,                           // RegMask
+    }}
+  },
+};
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16KbPciRegistersBeforeApLaunch[] =
+{
+// D18F0x68 - Link Transaction Control
+// bits[22:21]   DsNpReqLmt          = 0x2
+// bits[19]      ApicExtSpur         = 0x1
+// bits[18]      ApicExtId           = 0x1
+// bits[17]      ApicExtBrdCst       = 0x1
+// bits[15]      LimitCldtCfg        = 0x1
+// bits[11]      RespPassPW          = 0x1
+// bits[10]      DisFillP            = 0x0
+// bits[4]       DisMTS              = 0x1
+// bits[3]       DisWrDwP            = 0x1
+// bits[2]       DisWrBP             = 0x1
+// bits[1]       DisRdDwP            = 0x1
+// bits[0]       DisRdBP             = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x004E881F,                           // RegData
+      0x006E8C1F,                           // RegMask
+    }}
+  },
+// D18F3x8C - NB Configuration 1 High (NB_CFG1_HI)
+// bits[30]      MSRC001_001F[DisStpClkAbortFlush] = 0x1
+// bits[23]      MSRC001_001F[EnaDiv1CpuLowPwr] = 0x1
+// bits[22]      MSRC001_001F[InitApicIdCpuIdLo] = 0x1
+// bits[19]      MSRC001_001F[DisDatFwdVic] = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
+      0x40C80000,                           // RegData
+      0x40C80000,                           // RegMask
+    }}
+  },
+};
+
+//   PCI with Special Programming Requirements Table
+// ----------------------
+
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F16KbPciWorkarounds[] =
+{
+// D18F3x88
+  {
+    FamSpecificWorkaround,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      SetDisCstateBoostBlockPstateUp,       // function call
+      0x00000000,                           // data
+    }}
+  },
+// D18F4x110
+  {
+    FamSpecificWorkaround,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      ScalingApmParamBaseOnCSampleTimer,    // function call
+      0x00000000,                           // data
+    }}
+  },
+// D18F4x16C
+  {
+    FamSpecificWorkaround,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_KB_ALL                        // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      SetTdpLimitDis,                       // function call
+      0x00000000,                           // data
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableAfterApLaunch = {
+  PrimaryCores,
+  PERFORM_TP_AFTER_AP_LAUNCH,
+  (sizeof (F16KbPciRegistersAfterApLaunch) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F16KbPciRegistersAfterApLaunch,
+};
+
+CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableBeforeApLaunch = {
+  PrimaryCores,
+  PERFORM_TP_BEFORE_AP_LAUNCH,
+  (sizeof (F16KbPciRegistersBeforeApLaunch) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F16KbPciRegistersBeforeApLaunch,
+};
+
+CONST REGISTER_TABLE ROMDATA F16KbPciWorkaroundTable = {
+  PrimaryCores,
+  PERFORM_TP_AFTER_AP_LAUNCH,
+  (sizeof (F16KbPciWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) F16KbPciWorkarounds,
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Workaround for Kabini processors.
+ *
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+SetDisCstateBoostBlockPstateUp (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR PciAddress;
+  NB_CFG1_LOW_REG_REGISTER NbCfg1Low;
+  NB_CFG_4_REGISTER NbCfg4;
+
+  PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
+
+  PciAddress.AddressValue = NB_CFG1_LOW_REG_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg1Low, StdHeader);
+
+  NbCfg1Low.DisCstateBoostBlockPstateUp = NbCfg4.EnCstateBoostBlockCC6Exit;
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg1Low, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Workaround for Kabini processors.
+ *
+ *  AGESA should program F4x110[11:0][CSampleTimer] to 2, and update below registers as:
+ *  The following should be ROUNDED-NEAREST:
+ *
+ *  @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ *  @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+ScalingApmParamBaseOnCSampleTimer (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR PciAddress;
+  pmgmt_str0 var0;
+  pmgmt_str1 var1;
+  SAMPLE_RESIDENCY_TIMER_REGISTER SampleResidencyTimer;
+
+  PciAddress.AddressValue = SAMPLE_RESIDENCY_TIMER_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&SampleResidencyTimer, StdHeader);
+
+  SampleResidencyTimer.CSampleTimer = 20;
+  IDS_OPTION_HOOK (IDS_CSAMPLE_TIMER, (VOID *) (&SampleResidencyTimer), StdHeader);
+  ASSERT (SampleResidencyTimer.CSampleTimer != 0);
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&SampleResidencyTimer, StdHeader);
+
+  // The following should be ROUNDED-NEAREST:
+  // F5xB8[19:0] = F5xB8[19:0] * 2 / F4x110[CSampleTimer]
+  // F5xBC[19:0] = F5xBC[19:0] * 2 / F4x110[CSampleTimer]
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, FUNC_5, 0xB8);
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&var0, StdHeader);
+  var0.Bits_19_0 = ((var0.Bits_19_0 * 2) + (SampleResidencyTimer.CSampleTimer / 2)) / SampleResidencyTimer.CSampleTimer;
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&var0, StdHeader);
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, FUNC_5, 0xBC);
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&var1, StdHeader);
+  var1.Bits_19_0 = ((var1.Bits_19_0 * 2) + (SampleResidencyTimer.CSampleTimer / 2)) / SampleResidencyTimer.CSampleTimer;
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&var1, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Workaround for Kabini processors.
+ *
+ *  AGESA should program F4x16C[TdpLimitDis] in some case
+ *
+ * @param[in]   Data         The table data value, for example to indicate which CPU and Platform types matched.
+ * @param[in]   StdHeader    Config handle for library and services.
+ *
+ */
+VOID
+SetTdpLimitDis (
+  IN       UINT32              Data,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PciData;
+  PCI_ADDR PciAddress;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, FUNC_0, 0xB8);
+  PciData = 0xC010408C;
+  LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&PciData, StdHeader);
+  PciAddress.Address.Register = 0xBC;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&PciData, StdHeader);
+
+  if ((PciData & BIT2) == BIT2) {
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, FUNC_4, 0x16C);
+    LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&PciData, StdHeader);
+    PciData |= BIT3;
+    LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&PciData, StdHeader);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c
new file mode 100644
index 0000000000..2017f8b548
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c
@@ -0,0 +1,500 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 P-State power check
+ *
+ * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 86879 $   @e \$Date: 2013-01-28 11:11:12 -0600 (Mon, 28 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF16PowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "F16KbPowerCheck.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPOWERCHECK_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F16KbPmPwrCheckErrorHandler (
+  IN     VOID *ErrorData,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F16KbPmPwrChkCopyPstate (
+  IN     UINT8 Dest,
+  IN     UINT8 Src,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F16KbTransitionPstateCore (
+  IN       VOID *StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 16h Kabini core 0 entry point for performing the family 16h Processor-
+ * Systemboard Power Delivery Check.
+ *
+ * The steps are as follows:
+ *    1. Starting with P0, loop through all P-states until a passing state is
+ *       found.  A passing state is one in which the current required by the
+ *       CPU is less than the maximum amount of current that the system can
+ *       provide to the CPU.  If P0 is under the limit, no further action is
+ *       necessary.
+ *    2. If at least one P-State is under the limit & at least one P-State is
+ *       over the limit, the BIOS must:
+ *       a. If the processor's current P-State is disabled by the power check,
+ *          then the BIOS must request a transition to an enabled P-state
+ *          using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
+ *          to reflect the new value.
+ *       b. Copy the contents of the enabled P-state MSRs to the highest
+ *          performance P-state locations.
+ *       c. Request a P-state transition to the P-state MSR containing the
+ *          COF/VID values currently applied.
+ *       d. If a subset of boosted P-states are disabled, then copy the contents
+ *          of the highest performance boosted P-state still enabled to the
+ *          boosted P-states that have been disabled.
+ *       e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc]
+ *          to zero.
+ *       f. Adjust the following P-state parameters affected by the P-state
+ *          MSR copy by subtracting the number of P-states that are disabled
+ *          by the power check.
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[SwPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *    3. If all P-States are over the limit, the BIOS must:
+ *       a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
+ *          write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
+ *          MSRC001_0063[CurPstate] to reflect the new value.
+ *       b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state
+ *          MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR.
+ *          Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
+ *          [CurPstate] to reflect the new value.
+ *       c. Adjust the following P-state parameters to zero:
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[SwPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *       d. Program D18F4x15C[BoostSrc] to zero.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F16KbPmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8       DisPsNum;
+  UINT8       PsMaxVal;
+  UINT8       Pstate;
+  UINT32      ProcIddMax;
+  UINT32      LocalPciRegister;
+  UINT32      PstateLimit;
+  UINT32      SwPstateAdjust;
+  PCI_ADDR    PciAddress;
+  UINT64      LocalMsrRegister;
+  PWRCHK_ERROR_DATA ErrorData;
+
+  ErrorData.SocketNumber = 0;
+  // get the Max P-state value
+  for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
+    if (((F16_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+
+  ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
+
+ // Starting with P0, loop through all P-states until a passing state is
+ // found.  A passing state is one in which the current required by the
+ // CPU is less than the maximum amount of current that the system can
+ // provide to the CPU.  If P0 is under the limit, no further action is
+ // necessary.
+  DisPsNum = 0;
+  for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
+    if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
+      if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].MaximumCurrentLimit) {
+        // Add to event log the Pstate that exceeded the current limit
+        PutEventLog (AGESA_WARNING,
+                     CPU_EVENT_PM_PSTATE_OVERCURRENT,
+                     0, Pstate, 0, 0, StdHeader);
+        DisPsNum++;
+      } else {
+        break;
+      }
+    }
+  }
+
+  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+
+  if (ErrorData.AllowablePstateNumber == 0) {
+    PutEventLog (AGESA_FATAL,
+                 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
+                 0, 0, 0, 0, StdHeader);
+  }
+
+  if (DisPsNum != 0) {
+    PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+    ErrorData.NumberOfBoostStates = (UINT8) ((F16_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+
+    if (DisPsNum >= ErrorData.NumberOfBoostStates) {
+      // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero.
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((F16_CPB_CTRL_REGISTER *) (&LocalPciRegister))->BoostSrc = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      // Update the result of isFeatureEnabled in heap.
+      UpdateFeatureStatusInHeap (CoreBoost, FALSE, StdHeader);
+
+      ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates;
+    } else {
+      ErrorData.NumberOfSwPstatesDisabled = 0;
+    }
+
+    PciAddress.AddressValue = HTC_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
+    ErrorData.HtcPstate = (UINT8) (((HTC_REGISTER *) (&LocalPciRegister))->HtcPstateLimit);
+
+    F16KbPmPwrCheckErrorHandler (&ErrorData, StdHeader);
+
+    // Final Step
+    //    F3x64[HtcPstatelimit] -= disPsNum
+    //    F3x68[SwPstateLimit] -= disPsNum
+    //    F3xDC[HwPstateMaxVal] -= disPsNum
+    if (ErrorData.NumberOfSwPstatesDisabled != 0) {
+      PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
+      if (PstateLimit > PsMaxVal) {
+        SwPstateAdjust = PstateLimit - PsMaxVal;
+      } else {
+        SwPstateAdjust = 0;
+      }
+      if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+        PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      } else {
+        PstateLimit = ErrorData.NumberOfBoostStates;
+      }
+      if (PstateLimit <= ErrorData.NumberOfBoostStates) {
+        PstateLimit = ErrorData.NumberOfBoostStates + SwPstateAdjust;
+      }
+      ((HTC_REGISTER *) (&LocalPciRegister))->HtcPstateLimit = PstateLimit;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      PciAddress.Address.Register = SW_PS_LIMIT_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
+      PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit;
+      if (PstateLimit > PsMaxVal) {
+        SwPstateAdjust = PstateLimit - PsMaxVal;
+      } else {
+        SwPstateAdjust = 0;
+      }
+      if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+        PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      } else {
+        PstateLimit = ErrorData.NumberOfBoostStates;
+      }
+      if (PstateLimit <= ErrorData.NumberOfBoostStates) {
+        PstateLimit = ErrorData.NumberOfBoostStates + SwPstateAdjust;
+      }
+      ((SW_PS_LIMIT_REGISTER *) (&LocalPciRegister))->SwPstateLimit = PstateLimit;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      PciAddress.Address.Register = CPTC2_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
+      PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->HwPstateMaxVal;
+      if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
+        PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
+      } else {
+        PstateLimit = ErrorData.NumberOfBoostStates;
+      }
+      if (PstateLimit < ErrorData.NumberOfBoostStates) {
+        PstateLimit = ErrorData.NumberOfBoostStates;
+      }
+
+      ((CLK_PWR_TIMING_CTRL2_REGISTER *) (&LocalPciRegister))->HwPstateMaxVal = PstateLimit;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Error handler called if any p-states were determined to be out
+ * of range for the mother board.
+ *
+ * This function implements steps 2a-c and 3a-c on each core.
+ *
+ * @param[in]  ErrorData            Details about the error condition.
+ * @param[in]  StdHeader            Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F16KbPmPwrCheckErrorHandler (
+  IN       VOID *ErrorData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  i;
+  UINT8  HwPsMaxVal;
+  UINT8  SwPsMaxVal;
+  UINT8  HwDisPsNum;
+  UINT8  CurrentSwPs;
+  UINT8  ShiftIndex;
+  UINT8  PsDisableCount;
+  UINT8  NewSwP0;
+  UINT8  StateNumber;
+  UINT8  Core;
+  UINT32 ActiveCores;
+  UINT64 LocalMsrRegister;
+  BOOLEAN DisableAllBoostPstates;
+  AP_TASK      ApTask;
+  AGESA_STATUS IgnoreStatus;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  if (IsBsp (StdHeader, &IgnoreStatus)) {
+    // P-state MSRs are shared, so only BSC needs to perform this
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
+
+    HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+    HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+                  ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
+
+    LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+    CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
+    LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+    SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal);
+    PsDisableCount = 0;
+    if (((PWRCHK_ERROR_DATA *) ErrorData)->HtcPstate > HwPsMaxVal) {
+      ShiftIndex = ((PWRCHK_ERROR_DATA *) ErrorData)->HtcPstate;
+    } else {
+      ShiftIndex = HwPsMaxVal;
+    }
+
+    DisableAllBoostPstates = FALSE;
+
+    // Prepare ApTask
+    ApTask.FuncAddress.PfApTaskI = F16KbTransitionPstateCore;
+    ApTask.DataTransfer.DataSizeInDwords = 1;
+    ApTask.DataTransfer.DataPtr = &StateNumber;
+    ApTask.DataTransfer.DataTransferFlags = 0;
+    ApTask.ExeFlags = 0;
+    if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+      // All P-States are over the limit.
+
+      // Step 1
+      // Transition to Pstate Max if not there already
+      if (CurrentSwPs != SwPsMaxVal) {
+        StateNumber = SwPsMaxVal;
+        for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+          ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
+        }
+        ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
+      }
+
+      // Step 2
+      // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+      // to P0.
+      for (i = 0; i <= (ShiftIndex - HwPsMaxVal); i++) {
+        F16KbPmPwrChkCopyPstate ((((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates + i), (HwPsMaxVal + i), StdHeader);
+      }
+      StateNumber = 0;
+      for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+        ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
+      }
+      ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
+
+
+      // Disable all SW P-states except P0
+      PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1;
+
+      // Set a flag to disable all boost P-states
+      DisableAllBoostPstates = TRUE;
+    } else {
+      // At least one P-State is under the limit & at least one P-State is
+      // over the limit.
+      if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) {
+        // A subset of boosted P-states are disabled.  Copy the contents of the
+        // highest performance boosted P-state still enabled to the boosted
+        // P-states that have been disabled.
+        for (i = 0; i < HwDisPsNum; i++) {
+          F16KbPmPwrChkCopyPstate (i, HwDisPsNum, StdHeader);
+        }
+      } else {
+        // Set a flag to disable all boost P-states
+        DisableAllBoostPstates = TRUE;
+
+        if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) {
+          // Move remaining P-state register(s) up
+          // Step 1
+          // Transition to a valid Pstate if current Pstate has been disabled
+          if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) {
+            StateNumber = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+            for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+              ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
+            }
+            ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
+
+            CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+          }
+
+          // Step 2
+          // Move enabled Pstates up and disable the remainder
+          NewSwP0 = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+          for (i = 0; i <= (ShiftIndex - NewSwP0); i++) {
+            F16KbPmPwrChkCopyPstate ((i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates), (i + NewSwP0), StdHeader);
+          }
+
+          // Step 3
+          // Transition to current COF/VID at shifted location
+          CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled);
+          StateNumber = CurrentSwPs;
+          for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+            ApUtilRunCodeOnSocketCore (0, Core, &ApTask, StdHeader);
+          }
+          ApUtilTaskOnExecutingCore (&ApTask, StdHeader, (VOID *) NULL);
+
+          // Disable the appropriate number of P-states
+          PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled;
+        }
+      }
+    }
+    // Disable all boost P-states
+    if (DisableAllBoostPstates) {
+      for (i = 0; i < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; i++) {
+        FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
+      }
+    }
+    // Disable the appropriate P-states if any, starting from HW Pmin
+    for (i = 0; i < PsDisableCount; i++) {
+      FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copies the contents of one P-State MSR to another.
+ *
+ * @param[in]  Dest              Destination p-state number
+ * @param[in]  Src               Source p-state number
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+F16KbPmPwrChkCopyPstate (
+  IN       UINT8 Dest,
+  IN       UINT8 Src,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Core-level transition Pstate
+ *
+ * Transitions the executing core to the desired P-state.
+ *
+ * @param[in]  StateNumber          The new P-State to make effective.
+ * @param[in]  StdHeader            Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F16KbTransitionPstateCore (
+  IN       VOID *StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, *((UINT8 *) StateNumber), (BOOLEAN) TRUE, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h
new file mode 100644
index 0000000000..078a539226
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerCheck.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini Power related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _F16_KB_POWER_CHECK_H_
+#define _F16_KB_POWER_CHECK_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Power Check Error Data
+typedef struct {
+  UINT8 SocketNumber;                 ///< Socket Number
+  UINT8 HwPstateNumber;               ///< Number of hardware P-states
+  UINT8 AllowablePstateNumber;        ///< Number of allowable P-states
+  UINT8 NumberOfBoostStates;          ///< Number of boosted P-states
+  UINT8 NumberOfSwPstatesDisabled;    ///< Number of software P-states disabled
+  UINT8 HtcPstate;                    ///< HTC Pstate Limit Pstate
+} PWRCHK_ERROR_DATA;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F16KbPmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _F16_KB_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h
new file mode 100644
index 0000000000..497b4d4fdb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmt.h
@@ -0,0 +1,535 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini Power Management related registers defination
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F16_KB_POWERMGMT_H_
+#define _CPU_F16_KB_POWERMGMT_H_
+
+/*
+ * Family 16h Kabini CPU Power Management MSR definitions
+ *
+ */
+
+
+/* NB Machine Check Misc 4 MSR Register 0x00000413 */
+#define MC4_MISC0 0x00000413ul
+
+/// Interrupt Pending and CMP-Halt MSR Register
+typedef struct {
+  UINT64 :24;                        ///< Reserved
+  UINT64 BlkPtr:8;                   ///< Block pointer for additional MISC registers
+  UINT64 ErrCnt:12;                  ///< Error counter
+  UINT64 :4;                         ///< Reserved
+  UINT64 Ovrflw:1;                   ///< Overflow
+  UINT64 IntType:2;                  ///< Interrupt type
+  UINT64 CntEn:1;                    ///< Counter enable
+  UINT64 LvtOffset:4;                ///< LVT offset
+  UINT64 :5;                         ///< Reserved
+  UINT64 Locked:1;                   ///< Locked
+  UINT64 CntP:1;                     ///< Counter present
+  UINT64 Valid:1;                    ///< Valid
+} MC4_MISC0_MSR;
+
+/* P-state Registers 0xC00100[6B:64] */
+
+/// P-state MSR
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid:8;                   ///< CpuVid
+  UINT64 :5;                         ///< Reserved
+  UINT64 NbPstate:1;                 ///< NbPstate
+  UINT64 :9;                         ///< Reserved
+  UINT64 IddValue:8;                 ///< IddValue
+  UINT64 IddDiv:2;                   ///< IddDiv
+  UINT64 :21;                        ///< Reserved
+  UINT64 PsEnable:1;                 ///< Pstate Enable
+} PSTATE_MSR;
+
+#define GetF16KbCpuVid(PstateMsr) (((PSTATE_MSR *) PstateMsr)->CpuVid)
+
+
+/* VID operation related macros */
+#define ConvertVidInuV(Vid)   (1550000 - (6250 * Vid)) ///< Convert VID in uV.
+
+/* COFVID Control Register 0xC0010070 */
+#define MSR_COFVID_CTL 0xC0010070ul
+
+/// COFVID Control MSR Register
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid_6_0:7;               ///< CpuVid[6:0]
+  UINT64 PstateId:3;                 ///< Pstate ID
+  UINT64 :1;                         ///< Reserved
+  UINT64 CpuVid_7:1;                 ///< CpuVid[7]
+  UINT64 :1;                         ///< Reserved
+  UINT64 NbPstate:1;                 ///< Northbridge P-state
+  UINT64 :1;                         ///< Reserved
+  UINT64 NbVid:8;                    ///< NbVid
+  UINT64 :32;                        ///< Reserved
+} COFVID_CTRL_MSR;
+
+#define COFVID_CTRL_MSR_CurCpuVid_6_0_OFFSET       9
+#define COFVID_CTRL_MSR_CurCpuVid_6_0_WIDTH        7
+#define COFVID_CTRL_MSR_CurCpuVid_6_0_MASK         0xfe00
+#define COFVID_CTRL_MSR_CurCpuVid_7_OFFSET         20
+#define COFVID_CTRL_MSR_CurCpuVid_7_WIDTH          1
+#define COFVID_CTRL_MSR_CurCpuVid_7_MASK           0x100000ul
+
+/* SVI VID Encoding */
+
+///< Union structure of VID in SVI1/SVI2 modes
+typedef union {
+  UINT32     RawVid;                 ///< Raw VID value
+  struct {                           ///< SVI2 mode VID structure
+    UINT32   Vid_6_0:7;              ///< Vid[6:0] of SVI2 mode
+    UINT32   Vid_7:1;                ///< Vid[7] of SVI2 mode
+  } SVI2;
+  struct {                           ///< SVI1 mode VID structure
+    UINT32   Vid_LSB_Ignore:1;       ///< Ignored LSB of 8bit VID encoding in SVI1 mode
+    UINT32   Vid_6_0:1;              ///< Vid[6:0] of SVI mode
+  } SVI1;
+} SVI_VID;
+
+
+#define SetF16KbCpuVid(CofVidStsMsr, NewCpuVid) ( \
+  ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_6_0) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_6_0; \
+  ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_7) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_7; \
+)
+
+
+/* COFVID Status Register 0xC0010071 */
+#define MSR_COFVID_STS 0xC0010071ul
+
+/// COFVID Status MSR Register
+typedef struct {
+  UINT64 CurCpuFid:6;                ///< Current CpuFid
+  UINT64 CurCpuDid:3;                ///< Current CpuDid
+  UINT64 CurCpuVid_6_0:7;            ///< Current CpuVid[6:0]
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :1;                         ///< Reserved
+  UINT64 CurCpuVid_7:1;              ///< Current CpuVid[7]
+  UINT64 :2;                         ///< Reserved
+  UINT64 NbPstateDis:1;              ///< NbPstate Disable
+  UINT64 :8;
+  UINT64 StartupPstate:3;            ///< Startup Pstate
+  UINT64 :14;                        ///< Reserved
+  UINT64 MaxCpuCof:6;                ///< MaxCpuCof
+  UINT64 :1;                         ///< Reserved
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 MaxNbCof:5;                 ///< MaxNbCof
+} COFVID_STS_MSR;
+
+#define COFVID_STS_MSR_CurCpuVid_6_0_OFFSET       9
+#define COFVID_STS_MSR_CurCpuVid_6_0_WIDTH        7
+#define COFVID_STS_MSR_CurCpuVid_6_0_MASK         0xfe00
+#define COFVID_STS_MSR_CurCpuVid_7_OFFSET         20
+#define COFVID_STS_MSR_CurCpuVid_7_WIDTH          1
+#define COFVID_STS_MSR_CurCpuVid_7_MASK           0x100000ul
+
+#define GetF16KbCurCpuVid(CofVidStsMsr) ( \
+  (((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_7 << COFVID_STS_MSR_CurCpuVid_6_0_WIDTH) \
+  | ((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_6_0)
+
+
+/*
+ * Family 16h Kabini CPU Power Management PCI definitions
+ *
+ */
+/* Link Initialization Status D18F0x1A0 */
+#define LINK_INIT_STATUS_REG 0x1A0
+#define LINK_INIT_STATUS_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_0, LINK_INIT_STATUS_REG))
+
+/// Link Initialization Status
+typedef struct {
+  UINT32 InitComplete0:2;            ///< Initialization complete for link 0
+  UINT32 InitComplete1:2;            ///< Initialization complete for link 1
+  UINT32 :20;                        ///< Reserved
+  UINT32 IntNbExtCap:4;              ///< Internal NB extneded capability
+  UINT32 :3;                         ///< Reserved
+  UINT32 InitStatusValid:1;          ///< Initialization status valid
+} LINK_INIT_STATUS_REGISTER;
+
+/* NB Configuration 1 Low F3x88 */
+#define NB_CFG1_LOW_REG 0x88
+#define NB_CFG1_LOW_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CFG1_LOW_REG))
+
+/// Power Control Miscellaneous PCI Register
+typedef struct {
+  UINT32 :18;                        ///< Reserved
+  UINT32 DisCstateBoostBlockPstateUp:1; ///< DisCstateBoostBlockPstateUp
+  UINT32 :12;                        ///< Reserved
+  UINT32 DisCohLdtCfg:1;             ///< Disable coherent link configuration accesses
+} NB_CFG1_LOW_REG_REGISTER;
+
+/* Power Control Miscellaneous Register F3xA0 */
+#define PW_CTL_MISC_REG 0xA0
+#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
+
+/// Power Control Miscellaneous PCI Register
+typedef struct {
+  UINT32 PsiVid:7;                   ///< PSI_L VID threshold VID[6:0]
+  UINT32 PsiVidEn:1;                 ///< PSI_L VID enable
+  UINT32 PsiVid_7:1;                 ///< PSI_L VID threshold VID[7]
+  UINT32 :1;                         ///< Reserved
+  UINT32 IdleExitEn:1;               ///< Idle exit enable
+  UINT32 PllLockTime:3;              ///< PLL synchronization lock time
+  UINT32 Svi2HighFreqSel:1;          ///< SVI2 high frequency select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ConfigId:12;                ///< Configuration ID
+  UINT32 :3;                         ///< Reserved
+  UINT32 CofVidProg:1;               ///< COF and VID of Pstate programmed
+} POWER_CTRL_MISC_REGISTER;
+
+
+/* Clock Power/Timing Control 0 Register F3xD4 */
+#define CPTC0_REG 0xD4
+#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
+
+/// Clock Power Timing Control PCI Register
+typedef struct {
+  UINT32 MaxSwPstateCpuCof:6;        ///< Maximum software P-state core COF
+  UINT32 :2;                         ///< Reserved
+  UINT32 ClkRampHystSel:4;           ///< Clock Ramp Hysteresis Select
+  UINT32 ClkRampHystCtl:1;           ///< Clock Ramp Hysteresis Control
+  UINT32 :1;                         ///< Reserved
+  UINT32 CacheFlushImmOnAllHalt:1;   ///< Cache Flush Immediate on All Halt
+  UINT32 :5;                         ///< Reserved
+  UINT32 PowerStepDown:4;            ///< Power Step Down
+  UINT32 PowerStepUp:4;              ///< Power Step Up
+  UINT32 NbClkDiv:3;                 ///< NbClkDiv
+  UINT32 NbClkDivApplyAll:1;         ///< NbClkDivApplyAll
+} CLK_PWR_TIMING_CTRL_REGISTER;
+
+
+/* Clock Power/Timing Control 1 Register F3xD8 */
+#define CPTC1_REG 0xD8
+#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
+
+/// Clock Power Timing Control 1 PCI Register
+typedef struct {
+  UINT32 :4;                         ///< Reserved
+  UINT32 VSRampSlamTime:3;           ///< Voltage stabilization ramp time
+  UINT32 :25;                        ///< Reserved
+} CLK_PWR_TIMING_CTRL1_REGISTER;
+
+
+/* Northbridge Capabilities Register F3xE8 */
+#define NB_CAPS_REG 0xE8
+#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
+
+/// Northbridge Capabilities PCI Register
+typedef struct {
+  UINT32 :1;                         ///< Reserved
+  UINT32 DualNode:1;                 ///< Dual-node multi-processor capable
+  UINT32 EightNode:1;                ///< Eight-node multi-processor capable
+  UINT32 Ecc:1;                      ///< ECC capable
+  UINT32 Chipkill:1;                 ///< Chipkill ECC capable
+  UINT32 :3;                         ///< Reserved
+  UINT32 MctCap:1;                   ///< Memory controller capable
+  UINT32 SvmCapable:1;               ///< SVM capable
+  UINT32 HtcCapable:1;               ///< HTC capable
+  UINT32 :3;                         ///< Reserved
+  UINT32 MultVidPlane:1;             ///< Multiple VID plane capable
+  UINT32 :4;                         ///< Reserved
+  UINT32 x2Apic:1;                   ///< x2Apic capability
+  UINT32 :4;                         ///< Reserved
+  UINT32 MemPstateCap:1;             ///< Memory P-state capable
+  UINT32 :3;                         ///< Reserved
+  UINT32 Succor:1;                   ///< SUCCOR
+  UINT32 :3;                         ///< Reserved
+} NB_CAPS_REGISTER;
+
+/* Sample and Residency Timers Register D18F4x110 */
+#define SAMPLE_RESIDENCY_TIMER_REG 0x110
+#define SAMPLE_RESIDENCY_TIMER_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, SAMPLE_RESIDENCY_TIMER_REG))
+
+/// Sample and Residency Timers Register
+typedef struct {
+  UINT32 CSampleTimer:12;            ///< CSampleTimer
+  UINT32 FastCSampleTimer:1;         ///< FastCSampleTimer
+  UINT32 MinResTmr:8;                ///< Minimum residency timer
+  UINT32 :11;                        ///< Reserved
+} SAMPLE_RESIDENCY_TIMER_REGISTER;
+
+/* C-state Control 1 Register D18F4x118 */
+#define CSTATE_CTRL1_REG 0x118
+#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
+
+/// C-state Control 1 Register
+typedef struct {
+  UINT32 CpuPrbEnCstAct0:1;          ///< Core direct probe enable
+  UINT32 CacheFlushEnCstAct0:1;      ///< Cache flush enable
+  UINT32 CacheFlushTmrSelCstAct0:2;  ///< Cache flush timer select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ClkDivisorCstAct0:3;        ///< Clock divisor
+  UINT32 PwrGateEnCstAct0:1;         ///< Power gate enable
+  UINT32 PwrOffEnCstAct0:1;          ///< C-state action field 3
+  UINT32 NbPwrGate0:1;               ///< NB power-gating 0
+  UINT32 NbClkGate0:1;               ///< NB clock-gating 0
+  UINT32 SelfRefr0:1;                ///< Self-refresh 0
+  UINT32 SelfRefrEarly0:1;           ///< Allow early self-refresh 0
+  UINT32 :2;                         ///< Reserved
+  UINT32 CpuPrbEnCstAct1:1;          ///< Core direct probe enable
+  UINT32 CacheFlushEnCstAct1:1;      ///< Cache flush eable
+  UINT32 CacheFlushTmrSelCstAct1:2;  ///< Cache flush timer select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ClkDivisorCstAct1:3;        ///< Clock divisor
+  UINT32 PwrGateEnCstAct1:1;         ///< Power gate enable
+  UINT32 PwrOffEnCstAct1:1;          ///< C-state action field 3
+  UINT32 NbPwrGate1:1;               ///< NB power-gating 1
+  UINT32 NbClkGate1:1;               ///< NB clock-gating 1
+  UINT32 SelfRefr1:1;                ///< Self-refresh 1
+  UINT32 SelfRefrEarly1:1;           ///< Allow early self-refresh 1
+  UINT32 :2;                         ///< Reserved
+} CSTATE_CTRL1_REGISTER;
+
+
+/* C-state Control 2 Register D18F4x11C */
+#define CSTATE_CTRL2_REG 0x11C
+#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
+
+/// C-state Control 2 Register
+typedef struct {
+  UINT32 CpuPrbEnCstAct2:1;          ///< Core direct probe enable
+  UINT32 CacheFlushEnCstAct2:1;      ///< Cache flush eable
+  UINT32 CacheFlushTmrSelCstAct2:2;  ///< Cache flush timer select
+  UINT32 :1;                         ///< Reserved
+  UINT32 ClkDivisorCstAct2:3;        ///< Clock divisor
+  UINT32 PwrGateEnCstAct2:1;         ///< Power gate enable
+  UINT32 PwrOffEnCstAct2:1;          ///< C-state action field 3
+  UINT32 NbPwrGate2:1;               ///< NB power-gating 2
+  UINT32 NbClkGate2:1;               ///< NB clock-gating 2
+  UINT32 SelfRefr2:1;                ///< Self-refresh 2
+  UINT32 SelfRefrEarly2:1;           ///< Allow early self-refresh 2
+  UINT32 :18;                        ///< Reserved
+} CSTATE_CTRL2_REGISTER;
+
+
+/* Cstate Policy Control 1 Register D18F4x128 */
+#define CSTATE_POLICY_CTRL1_REG 0x128
+#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG))
+
+/// Cstate Policy Control 1 Register
+typedef struct {
+  UINT32 :2;                          ///< Reserved
+  UINT32 HaltCstateIndex:3;           ///< Specifies the IO-based C-state that is invoked by a HLT instruction
+  UINT32 CacheFlushTmr:7;             ///< Cache flush timer
+  UINT32 :6;                          ///< Reserved
+  UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold
+  UINT32 CacheFlushSucMonTmrSel:2;    ///< Cache flush success monitor timer select
+  UINT32 CacheFlushSucMonMispredictAct:2; ///< Cache flush success monitor mispredict action
+  UINT32 :6;                          ///< Reserved
+  UINT32 CstateMsgDis:1;              ///< C-state messaging disable
+} CSTATE_POLICY_CTRL1_REGISTER;
+
+
+/* Core Performance Boost Control Register D18F4x15C */
+
+/// Core Performance Boost Control Register
+typedef struct {
+  UINT32 BoostSrc:2;                 ///< Boost source
+  UINT32 NumBoostStates:3;           ///< Number of boosted states
+  UINT32 :2;                         ///< Reserved
+  UINT32 ApmMasterEn:1;              ///< APM master enable
+  UINT32 CstatePowerEn:1;            ///< C-state Power Enable
+  UINT32 :22;                        ///< Reserved
+  UINT32 BoostLock:1;                ///<
+} CPB_CTRL_REGISTER;
+
+
+/* Northbridge Capabilities 2  F5x84*/
+#define NB_CAPS_REG2 0x84
+#define NB_CAPS_REG2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CAPS_REG2))
+
+/// Northbridge Capabilities 2 PCI Register
+typedef struct {
+  UINT32 CmpCap:8;                   ///< CMP capable
+  UINT32 :4;                         ///< Reserved
+  UINT32 DctEn:4;                    ///< DCT enabled
+  UINT32 DdrMaxRate:5;               ///< maximum DDR rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 DdrMaxRateEnf:5;            ///< enforced maximum DDR rate:
+  UINT32 :3;                         ///< Reserved
+} NB_CAPS_2_REGISTER;
+
+/* Northbridge Configuration 4  F5x88*/
+#define NB_CFG_REG4 0x88
+#define NB_CFG_REG4_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CFG_REG4))
+
+/// Northbridge Configuration 4 PCI Register
+typedef struct {
+  UINT32 CC6PstateWakeUpDis:1;       ///< CC6PstateWakeUpDis
+  UINT32 :17;                        ///< Reserved
+  UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit
+  UINT32 :5;                         ///< Reserved
+  UINT32 DisHbNpReqBusLock:1;        ///< DisHbNpReqBusLock
+  UINT32 :7;                         ///< Reserved
+} NB_CFG_4_REGISTER;
+
+typedef struct {
+  UINT32 Bits_19_0:20;               ///< Bits[19:0]
+  UINT32 Bits_31_20:12;              ///< Reserved
+} pmgmt_str0;
+
+typedef struct {
+  UINT32 Bits_19_0:20;               ///< Bits[19:0]
+  UINT32 Bits_31_20:12;              ///< Reserved
+} pmgmt_str1;
+
+/* Northbridge P-state [3:0] F5x1[6C:60]  */
+
+/// Northbridge P-state Register
+typedef struct {
+  UINT32 NbPstateEn:1;               ///< NB P-state enable
+  UINT32 NbFid:6;                    ///< NB frequency ID
+  UINT32 NbDid:1;                    ///< NB divisor ID
+  UINT32 :2;                         ///< Reserved
+  UINT32 NbVid_6_0:7;                ///< NB VID[6:0]
+  UINT32 :1;                         ///< Reserved
+  UINT32 MemPstate:1;                ///< Memory P-State
+  UINT32 :2;                         ///< Reserved
+  UINT32 NbVid_7:1;                  ///< NB VID[7]
+  UINT32 NbIddDiv:2;                 ///< northbridge current divisor
+  UINT32 NbIddValue:8;               ///< northbridge current value
+} NB_PSTATE_REGISTER;
+
+#define NB_PSTATE_REGISTER_NbVid_6_0_OFFSET      10
+#define NB_PSTATE_REGISTER_NbVid_6_0_WIDTH       7
+#define NB_PSTATE_REGISTER_NbVid_6_0_MASK        0x0001FC00ul
+#define NB_PSTATE_REGISTER_NbVid_7_OFFSET        21
+#define NB_PSTATE_REGISTER_NbVid_7_WIDTH         1
+#define NB_PSTATE_REGISTER_NbVid_7_MASK          0x00200000ul
+
+#define GetF16KbNbVid(NbPstateRegister) ( \
+  (((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 << NB_PSTATE_REGISTER_NbVid_6_0_WIDTH) \
+  | ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0)
+
+#define SetF16KbNbVid(NbPstateRegister, NewNbVid) { \
+  ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0 = ((SVI_VID *) NewNbVid)->SVI2.Vid_6_0; \
+  ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 = ((SVI_VID *) NewNbVid)->SVI2.Vid_7; \
+}
+
+/* Northbridge P-state Status */
+#define NB_PSTATE_CTRL 0x170
+#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL))
+
+/// Northbridge P-state Control Register
+typedef struct {
+  UINT32 NbPstateMaxVal:2;           ///< NB P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateLo:2;               ///< NB P-state low
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateHi:2;               ///< NB P-state high
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateThreshold:4;        ///< NB P-state threshold
+  UINT32 NbPstateDisOnP0:1;          ///< NB P-state disable on P0
+  UINT32 SwNbPstateLoDis:1;          ///< Software NB P-state low disable
+  UINT32 :8;                         ///< Reserved
+  UINT32 NbPstateGnbSlowDis:1;       ///< NbPstateGnbSlowDis
+  UINT32 NbPstateLoRes:3;            ///< NB P-state low residency timer
+  UINT32 NbPstateHiRes:3;            ///< NB P-state high residency timer
+  UINT32 NbPstateFidVidSbcEn:1;      ///< NbPstateFidVidSbcEn
+  UINT32 MemPstateDis:1;             ///< Memory P-state disable
+} NB_PSTATE_CTRL_REGISTER;
+
+
+/* Northbridge P-state Status */
+#define NB_PSTATE_STATUS 0x174
+#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS))
+
+/// Northbridge P-state Status Register
+typedef struct {
+  UINT32 NbPstateDis:1;              ///< Nb pstate disable
+  UINT32 StartupNbPstate:2;          ///< startup northbridge Pstate number
+  UINT32 CurNbFid:6;                 ///< Current NB FID
+  UINT32 CurNbDid:1;                 ///< Current NB DID
+  UINT32 :2;                         ///< Reserved
+  UINT32 CurNbVid_6_0:7;             ///< Current NB VID[6:0]
+  UINT32 CurNbPstate:2;              ///< Current NB Pstate
+  UINT32 :1;                         ///< Reserved
+  UINT32 CurNbPstateLo:1;            ///< Current NB Pstate maps to Lo or Hi
+  UINT32 CurNbVid_7:1;               ///< Current NB VID[7]
+  UINT32 CurMemPstate:1;             ///< Current memory P-state
+  UINT32 :7;                         ///< Reserved
+} NB_PSTATE_STS_REGISTER;
+
+#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_OFFSET      12
+#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH       7
+#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_MASK        0x0007F000ul
+#define NB_PSTATE_STS_REGISTER_CurNbVid_7_OFFSET        23
+#define NB_PSTATE_STS_REGISTER_CurNbVid_7_WIDTH         1
+#define NB_PSTATE_STS_REGISTER_CurNbVid_7_MASK          0x00800000ul
+
+#define GetF16KbCurNbVid(NbPstateStsRegister) ( \
+  (((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_7 << NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH) \
+  | ((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_6_0)
+
+/* Miscellaneous Voltages */
+#define MISC_VOLTAGES 0x17C
+#define MISC_VOLTAGES_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, MISC_VOLTAGES))
+
+/// Miscellaneous Voltages Register
+typedef struct {
+  UINT32 MaxVid:8;                   ///< Maximum Voltage
+  UINT32 :2;                         ///< Reserved
+  UINT32 MinVid:8;                   ///< Minimum Voltage
+  UINT32 :5;                         ///< Reserved
+  UINT32 NbPsi0Vid:8;                ///< Northbridge PSI0_L VID threshold
+  UINT32 NbPsi0VidEn:1;              ///< Northbridge PSI0_L VID enable
+} MISC_VOLTAGE_REGISTER;
+
+
+/* Clock Power/Timing Control 5 Register F5x188 */
+#define CPTC5_REG 0x188
+#define CPTC5_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, CPTC5_REG))
+
+/// Clock Power Timing Control 5 Register
+typedef struct {
+  UINT32 NbOffsetTrim:2;             ///< Northbridge offset trim
+  UINT32 NbLoadLineTrim:3;           ///< Northbridge load line trim
+  UINT32 NbPsi1:1;                   ///< Northbridge PSI1_L
+  UINT32 :1;                    ///< Northbridge telemetry functionality.
+  UINT32 :25;                        ///< Reserved
+} CLK_PWR_TIMING_CTRL_5_REGISTER;
+
+#endif /* _CPU_F16_KB_POWERMGMT_H_ */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c
new file mode 100644
index 0000000000..fac228848f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c
@@ -0,0 +1,153 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Models 0x00 - 0x0F Kabini Power Management related initialization table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "F16KbUtilities.h"
+#include "F16KbCoreAfterReset.h"
+#include "F16KbNbAfterReset.h"
+#include "F16KbPowerCheck.h"
+#include "IdsF16KbAllService.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPOWERMGMTSYSTEMTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF16KbSysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*  Family 16h Kabini Only Table */
+/* ---------------------- */
+CONST SYS_PM_TBL_STEP ROMDATA CpuF16KbSysPmTableArray[] =
+{
+  /// @todo
+  IDS_INITIAL_F16_KB_PM_STEP
+  // Step 1 - Configure F3x[84:80].  Handled by PCI register table.
+
+  // Step 2 - Disable NB Pstate, if required
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F16KbNbPstateDis                                  // Function Pointer
+  },
+
+  // Step 3 - Core Minimum P-state Transition Sequence After Warm Reset
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F16KbPmCoreAfterReset                             // Function Pointer
+  },
+
+  // Step 4 - NB P-state COF and VID Synchronization After Warm Reset
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F16KbPmNbAfterReset                               // Function Pointer
+  },
+
+  // Step 5 - Power Check
+  //   Execute only after warm reset
+  {
+    0,                                                // ExeFlags
+    F16KbPmPwrCheck                                   // Function Pointer
+  },
+
+  IDS_F16_KB_PM_CUSTOM_STEP
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate table of steps to perform to initialize the power management
+ *  subsystem.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  SysPmTblPtr              Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF16KbSysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF16KbSysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
+  *SysPmTblPtr = CpuF16KbSysPmTableArray;
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c
new file mode 100644
index 0000000000..7d9d4d2a96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPsi.c
@@ -0,0 +1,278 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini PSI Initialization
+ *
+ * Enables Power Status Indicator (PSI) feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuFeatures.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "CommonReturns.h"
+#include "cpuPsi.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPSI_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+F16KbPmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES    *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION   *PlatformConfig,
+  IN       PCI_ADDR                 PciAddress,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Entry point for enabling Power Status Indicator
+ *
+ * This function must be run after all P-State routines have been executed
+ *
+ * @param[in]  PsiServices             The current CPU's family services.
+ * @param[in]  EntryPoint              Timepoint designator.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F16KbInitializePsi (
+  IN       PSI_FAMILY_SERVICES    *PsiServices,
+  IN       UINT64                  EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR                  PciAddress;
+  CPU_SPECIFIC_SERVICES     *FamilySpecificServices;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
+    // Configure PsiVid
+    F16KbPmVrmLowPowerModeEnable (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Sets up PSI_L operation.
+ *
+ * This function implements the LowPowerThreshold parameter.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  PlatformConfig          Contains the runtime modifiable feature input data.
+ * @param[in]  PciAddress              Segment, bus, device number of the node to transition.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F16KbPmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES    *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION   *PlatformConfig,
+  IN       PCI_ADDR                 PciAddress,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PSTATE_MSR                     PstateMsr;
+  CLK_PWR_TIMING_CTRL2_REGISTER  ClkPwrTimingCtrl2;
+  POWER_CTRL_MISC_REGISTER       PwrCtrlMisc;
+  UINT32                         CoreVrmLowPowerThreshold;
+  UINT32                         Pstate;
+  UINT32                         HwPstateMaxVal;
+  UINT32                         PstateCurrent;
+  UINT32                         NextPstateCurrent;
+  UINT32                         PreviousVid;
+  UINT32                         CurrentVid;
+
+  NB_PSTATE_REGISTER             NbPstateReg;
+  NB_PSTATE_CTRL_REGISTER        NbPsCtrl;
+  MISC_VOLTAGE_REGISTER          MiscVoltageReg;
+  UINT32                         NbVrmLowPowerThreshold;
+  UINT32                         NbPstate;
+  UINT32                         NbPstateMaxVal;
+  UINT32                         NbPstateCurrent;
+  UINT32                         NextNbPstateCurrent;
+  UINT32                         PreviousNbVid;
+  UINT32                         CurrentNbVid;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbPmVrmLowPowerModeEnable\n");
+
+  if (PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold != 0) {
+    // Set up PSI0_L for VDD
+    CoreVrmLowPowerThreshold = PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold;
+    IDS_HDT_CONSOLE (CPU_TRACE, "    Core VRM - LowPowerThreshold: %d\n", CoreVrmLowPowerThreshold);
+    PreviousVid = 0xFF;
+    CurrentVid = 0xFF;
+
+    PciAddress.AddressValue = CPTC2_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+    HwPstateMaxVal = ClkPwrTimingCtrl2.HwPstateMaxVal;
+    ASSERT (HwPstateMaxVal < NM_PS_REG);
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "    HwPstateMaxVal %d\n", HwPstateMaxVal);
+    // Check P-state from P0 to HwPstateMaxVal
+    for (Pstate = 0; Pstate <= HwPstateMaxVal; Pstate++) {
+      FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader);
+
+      LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), (UINT64 *) &PstateMsr, StdHeader);
+      CurrentVid = (UINT32) PstateMsr.CpuVid;
+
+      if (Pstate == HwPstateMaxVal) {
+        NextPstateCurrent = 0;
+      } else {
+        // Check P-state from P1 to HwPstateMaxVal
+        FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader);
+      }
+
+      if ((PstateCurrent <= CoreVrmLowPowerThreshold) &&
+          (NextPstateCurrent <= CoreVrmLowPowerThreshold) &&
+          (CurrentVid != PreviousVid)) {
+        // Program PsiVid and PsiVidEn if PSI state is found and stop searching.
+        PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
+        LibAmdPciRead (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader);
+        PwrCtrlMisc.PsiVid = CurrentVid;
+        PwrCtrlMisc.PsiVidEn = 1;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader);
+        IDS_HDT_CONSOLE (CPU_TRACE, "    PsiVid is enabled at P-state %d. PsiVid: %d\n", Pstate, CurrentVid);
+        break;
+      } else {
+        PstateCurrent = NextPstateCurrent;
+        PreviousVid = CurrentVid;
+      }
+    }
+  }
+
+  if (PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold != 0) {
+    // Set up NBPSI0_L for VDDNB
+    NbVrmLowPowerThreshold = PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold;
+    IDS_HDT_CONSOLE (CPU_TRACE, "    NB VRM - LowPowerThreshold: %d\n", NbVrmLowPowerThreshold);
+    PreviousNbVid = 0xFF;
+    CurrentNbVid = 0xFF;
+
+    PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    NbPstateMaxVal = NbPsCtrl.NbPstateMaxVal;
+    ASSERT (NbPstateMaxVal < NM_NB_PS_REG);
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "    NbPstateMaxVal %d\n", NbPstateMaxVal);
+    for (NbPstate = 0; NbPstate <= NbPstateMaxVal; NbPstate++) {
+      // Check only valid NB P-state
+      if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) NbPstate, &NbPstateCurrent, StdHeader) != TRUE) {
+        continue;
+      }
+
+      PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
+      LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader);
+      CurrentNbVid = (UINT32) GetF16KbNbVid (&NbPstateReg);
+
+      if (NbPstate == NbPstateMaxVal) {
+        NextNbPstateCurrent = 0;
+      } else {
+        // Check only valid NB P-state
+        if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) (NbPstate + 1), &NextNbPstateCurrent, StdHeader) != TRUE) {
+          continue;
+        }
+      }
+
+      if ((NbPstateCurrent <= NbVrmLowPowerThreshold) &&
+          (NextNbPstateCurrent <= NbVrmLowPowerThreshold) &&
+          (CurrentNbVid != PreviousNbVid)) {
+        // Program NbPsi0Vid and NbPsi0VidEn if PSI state is found and stop searching.
+        PciAddress.AddressValue = MISC_VOLTAGES_PCI_ADDR;
+        LibAmdPciRead (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader);
+        MiscVoltageReg.NbPsi0Vid = CurrentNbVid;
+        MiscVoltageReg.NbPsi0VidEn = 1;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader);
+        IDS_HDT_CONSOLE (CPU_TRACE, "    NbPsi0Vid is enabled at NB P-state %d. NbPsi0Vid: %d\n", NbPstate, CurrentNbVid);
+        break;
+      } else {
+        PreviousNbVid = CurrentNbVid;
+      }
+    }
+  }
+}
+
+
+CONST PSI_FAMILY_SERVICES ROMDATA F16KbPsiSupport =
+{
+  0,
+  (PF_PSI_IS_SUPPORTED) CommonReturnTrue,
+  F16KbInitializePsi
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
new file mode 100644
index 0000000000..38913c1d7a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPstate.c
@@ -0,0 +1,613 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini Pstate feature support functions.
+ *
+ * Provides the functions necessary to initialize the Pstate feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuPstateTables.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+#include "cpuF16Utilities.h"
+#include "F16KbUtilities.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBPSTATE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F16KbGetPowerStepValueInTime (
+  IN OUT   UINT32  *PowerStepPtr
+  );
+
+VOID
+STATIC
+F16KbGetPllValueInTime (
+  IN OUT   UINT32  *PllLockTimePtr
+  );
+
+
+AGESA_STATUS
+F16KbGetPstateTransLatency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F16KbGetPstateFrequency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F16KbGetPstatePower (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F16KbGetPstateMaxState (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+     OUT   UINT32              *MaxPStateNumber,
+     OUT   UINT8               *NumberOfBoostStates,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F16KbGetPstateRegisterInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+     OUT   UINT32              *SwPstateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+BOOLEAN
+STATIC
+F16KbIsPstatePsdDependent (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbIsPstatePsdDependent\n");
+  // Family 16h KB defaults to independent PSD
+  IDS_HDT_CONSOLE (CPU_TRACE, "    P-state PSD is independent.\n");
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to get Pstate Transition Latency.
+ *
+ *  Calculate TransitionLatency by power step value and pll value.
+ *
+ *  @param[in]     PstateCpuServices                 Pstate CPU services.
+ *  @param[in]     PStateLevelingBufferStructPtr     Pstate row data buffer pointer
+ *  @param[in]     PciAddress                        Pci address
+ *  @param[out]    TransitionLatency                 The transition latency.
+ *  @param[in]     StdHeader                         Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F16KbGetPstateTransLatency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32               CpuFid;
+  UINT32               HwP0CpuFid;
+  UINT32               PowerStepDown;
+  UINT32               PowerStepUp;
+  UINT32               PllLockTime;
+  UINT32               LocalPciRegister;
+  UINT32               k;
+  UINT32               PStateMaxValueOnCurrentCore;
+  UINT32               TransAndBusMastLatency;
+  UINT64               MsrData;
+  BOOLEAN              CpuFidSameFlag;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPstateTransLatency\n");
+
+  CpuFidSameFlag = TRUE;
+  HwP0CpuFid = 0;
+
+  // Get PStateMaxValue
+  PciAddress->Address.Register = CPTC2_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+  PStateMaxValueOnCurrentCore = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->HwPstateMaxVal;
+
+  //
+  //Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states
+  //
+  for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+    LibAmdMsrRead ((MSR_PSTATE_0 + k), &MsrData, StdHeader);
+    CpuFid = (UINT32) (((PSTATE_MSR *) &MsrData)->CpuFid);
+    if (k == 0) {
+      HwP0CpuFid = CpuFid;
+    }
+    if (HwP0CpuFid != CpuFid) {
+      CpuFidSameFlag = FALSE;
+      break;
+    }
+  }
+
+  PciAddress->Address.Register = CPTC0_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+
+  // PowerStepDown - Bits 20:23
+  PowerStepDown = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown;
+
+  // PowerStepUp   - Bits 24:27
+  PowerStepUp = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp;
+
+  // Convert the raw numbers in TempVar8_a and TempVar8_b into time
+  F16KbGetPowerStepValueInTime (&PowerStepDown);
+  F16KbGetPowerStepValueInTime (&PowerStepUp);
+
+  //
+  //(15 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us
+  //
+  TransAndBusMastLatency =
+  (15 * (PowerStepDown + PowerStepUp) + 999) / 1000;
+
+  if (!CpuFidSameFlag) {
+    //
+    //+ F3xA0[PllLockTime]
+    //
+    PciAddress->Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+
+    PllLockTime = ((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PllLockTime;
+    F16KbGetPllValueInTime (&PllLockTime);
+    TransAndBusMastLatency += PllLockTime;
+  }
+
+  *TransitionLatency = TransAndBusMastLatency;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to calculates the frequency in megahertz of the desired P-state.
+ *
+ *  @param[in]   PstateCpuServices        Pstate CPU services.
+ *  @param[in]   StateNumber              The P-State to analyze.
+ *  @param[out]  FrequencyInMHz           The P-State's frequency in MegaHertz
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS   Always Succeeds.
+ */
+AGESA_STATUS
+F16KbGetPstateFrequency (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempValue;
+  UINT32 CpuDid;
+  UINT32 CpuFid;
+  UINT64 LocalMsrRegister;
+  PCI_ADDR PciAddress;
+  HTC_REGISTER HtcReg;
+  CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
+
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPstateFrequency - P%d\n", StateNumber);
+
+  PciAddress.AddressValue = CPTC2_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader);
+
+  PciAddress.AddressValue = HTC_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader);
+
+  ASSERT ((StateNumber <= ClkPwrTimingCtrl2.HwPstateMaxVal) || ((StateNumber == HtcReg.HtcPstateLimit)));
+
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+
+  CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid);
+  CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid);
+
+  switch (CpuDid) {
+  case 0:
+    TempValue = 1;
+    break;
+  case 1:
+    TempValue = 2;
+    break;
+  case 2:
+    TempValue = 4;
+    break;
+  case 3:
+    TempValue = 8;
+    break;
+  case 4:
+    TempValue  =  16;
+    break;
+  default:
+    // CpuDid is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    TempValue = 1;
+    break;
+  }
+  *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FrequencyInMHz=%d, CpuFid=%d, CpuDid=%d\n", *FrequencyInMHz, CpuFid, CpuDid);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to calculates the power in milliWatts of the desired P-state.
+ *
+ *  @param[in]     PstateCpuServices      Pstate CPU services.
+ *  @param[in]   StateNumber              Which P-state to analyze
+ *  @param[out]  PowerInMw                The Power in milliWatts of that P-State
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F16KbGetPstatePower (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  CpuVid;
+  UINT32  IddValue;
+  UINT32  IddDiv;
+  UINT32  V_x100000;
+  UINT32  Power;
+  UINT64  LocalMsrRegister;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPstatePower - P%d\n", StateNumber);
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1);
+  CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid);
+  IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue);
+  IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv);
+
+  if (CpuVid >= 0xF8) {
+    V_x100000 = 0;
+  } else {
+    V_x100000 = 155000L - (625L * CpuVid);
+  }
+
+  Power = V_x100000 * IddValue;
+
+  switch (IddDiv) {
+  case 0:
+    *PowerInMw = Power / 100L;
+    break;
+  case 1:
+    *PowerInMw = Power / 1000L;
+    break;
+  case 2:
+    *PowerInMw = Power / 10000L;
+    break;
+  default:
+    // IddDiv is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    *PowerInMw = 0;
+    break;
+  }
+  IDS_HDT_CONSOLE (CPU_TRACE, "  PowerInMw=%d, CpuVid=%d, IddValue=%d, IddDiv=%d\n", *PowerInMw, CpuVid, IddValue, IddDiv);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to get CPU pstate max state.
+ *
+ *  @param[in]     PstateCpuServices      Pstate CPU services.
+ *  @param[out]    MaxPStateNumber        The max hw pstate value on the current socket.
+ *  @param[out]    NumberOfBoostStates    The number of boosted P-states on the current socket.
+ *  @param[in]     StdHeader              Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F16KbGetPstateMaxState (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+     OUT   UINT32              *MaxPStateNumber,
+     OUT   UINT8               *NumberOfBoostStates,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32               NumBoostStates;
+  UINT64               MsrValue;
+  UINT32               LocalPciRegister;
+  PCI_ADDR             PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPstateMaxState\n");
+
+  LocalPciRegister = 0;
+
+  // For F16 Kabini CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+
+  NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+  *NumberOfBoostStates = (UINT8) NumBoostStates;
+
+  //
+  // Read PstateMaxVal [6:4] from MSR C001_0061
+  // So, we will know the max pstate state in this socket.
+  //
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
+  *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    MaxPStateNumber=%d, NumBoostStates=%d\n", *MaxPStateNumber, NumBoostStates);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to get CPU pstate register information.
+ *
+ *  @param[in]     PstateCpuServices         Pstate CPU services.
+ *  @param[in]     PState                    Input Pstate number for query.
+ *  @param[out]    PStateEnabled             Boolean flag return pstate enable.
+ *  @param[in,out] IddVal                    Pstate current value.
+ *  @param[in,out] IddDiv                    Pstate current divisor.
+ *  @param[out]    SwPstateNumber            Software P-state number.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F16KbGetPstateRegisterInfo (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+     OUT   UINT32              *SwPstateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32    LocalPciRegister;
+  UINT64    LocalMsrRegister;
+  PCI_ADDR  PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPstateRegisterInfo - P%d\n", PState);
+
+  ASSERT (PState < NM_PS_REG);
+
+  // For F16 Kabini CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
+
+  // Read PSTATE MSRs
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader);
+
+  *SwPstateNumber = PState;
+
+  if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+    // PState enable = bit 63
+    *PStateEnabled = TRUE;
+    //
+    // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
+    //
+    if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) {
+      *PStateEnabled = FALSE;
+    } else {
+      *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+    }
+    IDS_HDT_CONSOLE (CPU_TRACE, "  Pstate %d is enabled. SwPstateNumber=%d\n", PState, *SwPstateNumber);
+  } else {
+    *PStateEnabled = FALSE;
+  }
+
+  // Bits 39:32 (high 32 bits [7:0])
+  *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue;
+  // Bits 41:40 (high 32 bits [9:8])
+  *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    IddVal=%d, IddDiv=%d\n", *IddVal, *IddDiv);
+  return (AGESA_SUCCESS);
+}
+
+
+CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F16KbPstateServices =
+{
+  0,
+  (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
+  F16KbIsPstatePsdDependent,
+  F16KbGetPstateTransLatency,
+  F16KbGetPstateFrequency,
+  (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
+  F16KbGetPstatePower,
+  F16KbGetPstateMaxState,
+  F16KbGetPstateRegisterInfo
+};
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F16KbGetPowerStepValueInTime
+ *
+ *  Description:
+ *    Convert power step value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PowerStepPtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+F16KbGetPowerStepValueInTime (
+  IN OUT   UINT32  *PowerStepPtr
+  )
+{
+  UINT32 TempVar_a;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPowerStepValueInTime\n");
+
+  TempVar_a = *PowerStepPtr;
+
+  if (TempVar_a < 0x4) {
+    *PowerStepPtr = 400 - (TempVar_a * 100);
+  } else if (TempVar_a <  0x9) {
+    *PowerStepPtr = 130 - (TempVar_a * 10);
+  } else {
+    *PowerStepPtr = 90 - (TempVar_a * 5);
+  }
+  IDS_HDT_CONSOLE (CPU_TRACE, "  PowerStepPtr=%d\n", *PowerStepPtr);
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F16KbGetPllValueInTime
+ *
+ *  Description:
+ *    Convert PLL Value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PllLockTimePtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+F16KbGetPllValueInTime (
+  IN OUT   UINT32  *PllLockTimePtr
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetPllValueInTime\n");
+
+  if (*PllLockTimePtr < 4) {
+    *PllLockTimePtr = *PllLockTimePtr + 1;
+  } else if (*PllLockTimePtr == 4) {
+    *PllLockTimePtr = 8;
+  } else if (*PllLockTimePtr == 5) {
+    *PllLockTimePtr = 16;
+  } else
+    *PllLockTimePtr = 0;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    PllLockTimePtr=%d\n", *PllLockTimePtr);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c
new file mode 100644
index 0000000000..a953793c3d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c
@@ -0,0 +1,112 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini Shared MSR table with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 86705 $   @e \$Date: 2013-01-24 17:34:21 -0600 (Thu, 24 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBSHAREDMSRTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+//   M S R   T a b l e s
+// ----------------------
+
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F16KbSharedMsrRegisters[] =
+{
+  // When there's a entry, change the number of entries below from 0 to (sizeof (F16KbSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS))
+  {0},
+};
+
+//   Shared MSRs with Special Programming Requirements Table
+// ----------------------
+STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F16KbSharedMsrWorkarounds[] =
+{
+  // When there's a entry, change the number of entries below from 0 to (sizeof (F16KbSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS))
+  {0},
+};
+
+
+CONST REGISTER_TABLE ROMDATA F16KbSharedMsrRegisterTable = {
+  ComputeUnitPrimary,
+  PERFORM_TP_AFTER_AP_LAUNCH,
+  0,
+  //(sizeof (F16KbSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F16KbSharedMsrRegisters,
+};
+
+CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable = {
+  ComputeUnitPrimary,
+  PERFORM_TP_AFTER_AP_LAUNCH,
+  0,
+  //(sizeof (F16KbSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F16KbSharedMsrWorkarounds,
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
new file mode 100644
index 0000000000..ed94e79f78
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.c
@@ -0,0 +1,1015 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 models 00h - 0Fh Kabini specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 16h Kabini.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF16PowerMgmt.h"
+#include "F16KbPowerMgmt.h"
+#include "cpuEarlyInit.h"
+#include "GeneralServices.h"
+#include "F16KbUtilities.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+F16KbNbPstateDisCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F16KbGetNbFreqNumeratorInMHz (
+  IN       UINT32                NbFid,
+     OUT   UINT32                *FreqNumeratorInMHz,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+F16KbGetNbFreqDivisor (
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FreqDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+STATIC
+F16KbCalculateNbFrequencyInMHz (
+  IN       UINT32                NbFid,
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F16KbCovertVidInuV (
+  IN       UINT32                Vid,
+     OUT   UINT32                *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+F16KbCmnGetIddDivisor (
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *IddDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+F16KbCmnCalculateCurrentInmA (
+  IN       UINT32                IddValue,
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *CurrentInmA,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+BOOLEAN
+F16KbSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F16KbGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       MsrAddress;
+  PSTATE_MSR   PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+  NB_CAPS_2_REGISTER  NbCap2;
+  UINT32       ProcIddMaxPerCore;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetProcIddMax - P%d\n", Pstate);
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, (UINT64 *) &PstateMsr, StdHeader);
+  F16KbCmnCalculateCurrentInmA ((UINT32) PstateMsr.IddValue, (UINT32) PstateMsr.IddDiv, &ProcIddMaxPerCore, StdHeader);
+  PciAddress.AddressValue = NB_CAPS_REG2_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbCap2, StdHeader);
+  *ProcIddMax = (UINT32) ProcIddMaxPerCore * (NbCap2.CmpCap + 1);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Pstate %d ProcIddMax %d CmpCap %d\n", Pstate, *ProcIddMax, NbCap2.CmpCap);
+
+  if (PstateMsr.PsEnable == 1) {
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on Kabini
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   CoreLevelMode            Core level mode.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ * @retval      TRUE                     Down Core register is updated.
+ * @retval      FALSE                    Down Core register is not updated.
+ */
+BOOLEAN
+F16KbSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     NumOfComputeUnit;
+  UINT8     CoresPerComputeUnit;
+  UINT32    LocalPciRegister;
+  UINT32    CoreDisableBits;
+  UINT32    TempVar32_a;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   IsUpdated;
+  AGESA_STATUS AgesaStatus;
+
+  IsUpdated = FALSE;
+  CoreDisableBits = 0;
+  TempVar32_a = 1;
+  CoresPerComputeUnit = 1;
+
+  switch (CoreLevelMode) {
+  // There's no 'break' except 'case CORE_LEVEL_COMPUTE_UNIT'.
+  // It's for generating CoreDisableBits and CoresPerComputeUnit
+  case CORE_LEVEL_COMPUTE_UNIT_THREE:
+    TempVar32_a = TempVar32_a << 1;
+    CoresPerComputeUnit++;
+  case CORE_LEVEL_COMPUTE_UNIT_TWO:
+    TempVar32_a = TempVar32_a << 1;
+    CoresPerComputeUnit++;
+  case CORE_LEVEL_COMPUTE_UNIT:
+    TempVar32_a = (TempVar32_a << 1) - 1;
+    TempVar32_a = FOUR_CORE_COMPUTE_UNIT_BITMAP & (~TempVar32_a);
+    NumOfComputeUnit = (UINT8) ((*LeveledCores) / CoresPerComputeUnit);
+    for (CoreDisableBits = 0; NumOfComputeUnit > 0; NumOfComputeUnit--) {
+      CoreDisableBits <<= FOUR_CORE_COMPUTE_UNIT_BITWIDTH;
+      CoreDisableBits |= TempVar32_a;
+    }
+    break;
+  default:
+    TempVar32_a = *LeveledCores;
+    if (TempVar32_a == 1) {
+      CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    } else {
+      CoreDisableBits = ALL_CORES_DISABLE_BITMAP;
+      TempVar32_a = ((1 << TempVar32_a) - 1);
+      CoreDisableBits &= ~TempVar32_a;
+    }
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_5;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      LocalPciRegister = (LocalPciRegister & 0xFF) + 1;
+      LocalPciRegister = (1 << LocalPciRegister) - 1;
+      CoreDisableBits &= LocalPciRegister;
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      if ((LocalPciRegister | CoreDisableBits) != LocalPciRegister) {
+        LocalPciRegister |= CoreDisableBits;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+        IsUpdated = TRUE;
+      }
+    }
+  }
+
+  return IsUpdated;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F16KbCoreLeveling =
+{
+  0,
+  F16KbSetDownCoreRegister
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ *  @return      AGESA_SUCCESS            FrequencyInMHz is valid.
+ */
+AGESA_STATUS
+F16KbGetCurrentNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  NB_PSTATE_STS_REGISTER NbPstateStsReg;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS ReturnCode;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetCurrentNbFrequency\n");
+
+  PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateStsReg, StdHeader);
+  ReturnCode = F16KbCalculateNbFrequencyInMHz (
+                 NbPstateStsReg.CurNbFid,
+                 NbPstateStsReg.CurNbDid,
+                 FrequencyInMHz,
+                 StdHeader
+                 );
+  return ReturnCode;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the node's minimum and maximum northbridge frequency.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[out]    MaxFreqInMHz            The node's maximum northbridge frequency.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        AGESA_SUCCESS           Northbridge frequency is valid
+ */
+AGESA_STATUS
+F16KbGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *var3,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  INT8         NbPsMaxVal;
+  UINT8        i;
+  UINT32       LocalPciRegister;
+  AGESA_STATUS AgesaStatus;
+
+  AgesaStatus = AGESA_ERROR;
+
+  // Obtain the max NB frequency on the node
+  PciAddress->Address.Function = FUNC_5;
+  PciAddress->Address.Register = NB_PSTATE_CTRL;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+  NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal;
+
+  // Starting from NB Pmax
+  for (i = 0; i <= NbPsMaxVal; i++) {
+    PciAddress->Address.Function = FUNC_5;
+    PciAddress->Address.Register = (NB_PSTATE_0 + (4 * i));
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+
+    // Ensure that the NB Pstate is enabled
+    if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) {
+      AgesaStatus = F16KbCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid,
+                                                    ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid,
+                                                    MaxFreqInMHz,
+                                                    StdHeader);
+      break;
+    }
+  }
+  // If all of NbPstates are disabled, get MaxFreqInMHz from CurNbPstate
+  if (i > NbPsMaxVal) {
+    PciAddress->Address.Register = NB_PSTATE_STATUS;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+    F16KbCalculateNbFrequencyInMHz (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid,
+                                      ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid,
+                                      MaxFreqInMHz,
+                                      StdHeader);
+    *var3 = *MaxFreqInMHz;
+    ASSERT (FALSE);
+  } else {
+    // If platform configuration disable NB P-states, return the NB P0 frequency
+    // as both the min and max frequency on the node.
+    if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) {
+      *var3 = *MaxFreqInMHz;
+    } else {
+      PciAddress->Address.Function = FUNC_5;
+      PciAddress->Address.Register = NB_PSTATE_CTRL;
+      LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+      NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal;
+
+      // Obtain the min NB frequency on the node, starting from NB Pmin
+      for (; NbPsMaxVal >= 0; NbPsMaxVal--) {
+        PciAddress->Address.Function = FUNC_5;
+        PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPsMaxVal));
+        LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+
+        // Ensure that the NB Pstate is enabled
+        if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) {
+          AgesaStatus = F16KbCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid,
+                                                        ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid,
+                                                        var3,
+                                                        StdHeader);
+          break;
+        }
+      }
+    }
+  }
+  IDS_OPTION_HOOK (IDS_NBPS_MIN_FREQ, var3, StdHeader);
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[in]     NbPstate                The NB P-state number to check.
+ *  @param[out]    FreqNumeratorInMHz      The desired node's frequency numerator in megahertz.
+ *  @param[out]    FreqDivisor             The desired node's frequency divisor.
+ *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    NbPstate is valid
+ *  @retval        FALSE                   NbPstate is disabled or invalid
+ */
+BOOLEAN
+F16KbGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   NbVid;
+  BOOLEAN  PstateIsValid;
+  NB_PSTATE_CTRL_REGISTER   NbPstateCtrlReg;
+  NB_PSTATE_REGISTER        NbPstateReg;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetNbPstateInfo - NB P%d\n", NbPstate);
+
+  ASSERT ((PciAddress->Address.Segment == 0) && (PciAddress->Address.Bus == 0) && (PciAddress->Address.Device == 0x18));
+
+  PstateIsValid = FALSE;
+
+  // If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled
+  if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) {
+    PciAddress->AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateCtrlReg, StdHeader);
+
+    ASSERT ((NbPstate < NM_NB_PS_REG) && (NbPstateCtrlReg.NbPstateMaxVal < NM_NB_PS_REG));
+    if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) {
+      PciAddress->Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
+      LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateReg, StdHeader);
+      IDS_HDT_CONSOLE (CPU_TRACE, "    En:%d Fid:%x Did:%x Vid:%x\n", NbPstateReg.NbPstateEn, NbPstateReg.NbFid, NbPstateReg.NbDid, GetF16KbNbVid (&NbPstateReg));
+
+      // Check if at least NB P0 is enabled.
+      ASSERT ((NbPstate == 0) ? (NbPstateReg.NbPstateEn == 1) : TRUE);
+      // Ensure that requested NbPstate is enabled
+      if (NbPstateReg.NbPstateEn == 1) {
+        F16KbGetNbFreqNumeratorInMHz (NbPstateReg.NbFid, FreqNumeratorInMHz, StdHeader);
+        F16KbGetNbFreqDivisor (NbPstateReg.NbDid, FreqDivisor, StdHeader);
+
+        NbVid = GetF16KbNbVid (&NbPstateReg);
+        F16KbCovertVidInuV  (NbVid, VoltageInuV, StdHeader);
+        PstateIsValid = TRUE;
+      }
+    }
+  }
+  return PstateIsValid;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get NB pstate current.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_IDD_MAX}.
+ *
+ *    This function returns the NbIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     NbPstate                  The NB P-state to check.
+ *  @param[out]    NbIddMax                  NB P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      NB P-state is enabled, and NbIddMax is valid.
+ *  @retval        FALSE                     NB P-state is disabled
+ */
+BOOLEAN
+F16KbGetNbIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  NbPstate,
+     OUT   UINT32                 *NbIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN      IsNbPsEnabled;
+  PCI_ADDR     PciAddress;
+  NB_PSTATE_CTRL_REGISTER   NbPstateCtrlReg;
+  NB_PSTATE_REGISTER        NbPstateReg;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetNbIddMax - NB P%d\n", NbPstate);
+
+  IsNbPsEnabled = FALSE;
+
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateCtrlReg, StdHeader);
+
+  ASSERT (NbPstate < NM_NB_PS_REG);
+  if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) {
+    PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate));
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader);
+
+    // Ensure that requested NbPstate is enabled
+    if (NbPstateReg.NbPstateEn == 1) {
+      F16KbCmnCalculateCurrentInmA (NbPstateReg.NbIddValue, NbPstateReg.NbIddDiv, NbIddMax, StdHeader);
+      IsNbPsEnabled = TRUE;
+      IDS_HDT_CONSOLE (CPU_TRACE, "  NB Pstate %d is Valid. NbIddMax %d\n", NbPstate, *NbIddMax);
+    }
+  }
+  return IsNbPsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the number of physical cores of current processor.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of physical cores.
+ */
+UINT8
+F16KbGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPUID_DATA    CpuId;
+
+  //
+  //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc.
+  //
+  LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader);
+  return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Use the Mailbox Register to get the Ap Mailbox info for the current core.
+ *
+ *  @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
+ *
+ *  Access the mailbox register used with this NB family.  This is valid until the
+ *  point that some init code initializes the mailbox register for its normal use.
+ *  The Machine Check Misc (Thresholding) register is available as both a PCI config
+ *  register and a MSR, so it can be used as a mailbox from HT to other functions.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    ApMailboxInfo           The AP Mailbox info
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F16KbGetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  // For Family 16h Kabini, we will return socket 0, node 0, module 0, module type 0, and 0 for
+  // the system degree
+  ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000;
+  ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get this AP's system core number from hardware.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
+ *
+ *  Returns the system core number from the scratch MSR, where
+ *  it was saved at heap initialization.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+UINT32
+F16KbGetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CPUID_DATA Cpuid;
+
+  LibAmdCpuidRead (0x1, &Cpuid, StdHeader);
+  return ((Cpuid.EBX_Reg >> 24) & 0xFF);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      PlatformConfig                 Platform profile/build option config structure.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F16KbIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR PciAddress;
+  BOOLEAN  NbPstatesSupported;
+  BOOLEAN  SkipHwCfg;
+  NB_PSTATE_STS_REGISTER   NbPstateSts;
+  NB_PSTATE_CTRL_REGISTER  NbPstateCtrl;
+
+
+  PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateSts, StdHeader);
+  if (NbPstateSts.NbPstateDis == 1) {
+    return FALSE;
+  }
+
+  SkipHwCfg = FALSE;
+  IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader);
+
+  // NbPstates is supported by default
+  NbPstatesSupported = TRUE;
+
+  // Get user options
+  if (!PlatformConfig->PlatformProfile.NbPstatesSupported) {
+    NbPstatesSupported = FALSE;
+  }
+
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateCtrl, StdHeader);
+  if (((NbPstateCtrl.NbPstateMaxVal != 0) || SkipHwCfg) && (NbPstatesSupported)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Disable NB P-state.
+ *   - clear F5x1[6C:64]
+ *   - clear F5x170[NbPstateMaxVal]
+ *   - set   F5x170[SwNbPstateLoDis]
+ *   - clear MSRC001_00[6B:64][NbPstate]
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services
+ * @param[in]     CpuEarlyParamsPtr       Service Parameters
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+F16KbNbPstateDis (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS   *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       i;
+  UINT32       PciData;
+  UINT32       NbPsCtrl;
+  UINT32       NbPsCtrlOrg;
+  BOOLEAN      SkipNbPsLoPart;
+  PCI_ADDR     PciAddress;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbNbPstateDis\n");
+
+  // D18F5x170[30, NbPstateFidVidSbcEn] = 1
+  PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+  ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateFidVidSbcEn = 1;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+  // Check whether NB P-state is disabled
+  if (!FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
+
+    IDS_HDT_CONSOLE (CPU_TRACE, "  NB Pstates disabled\n");
+
+    PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    NbPsCtrlOrg = NbPsCtrl;
+
+    // If CurNbPstate is not NB P0, get the Pstate pointed to by CurNbPstate and copy it's value to NB P0 to P3 and clear NbPstateHi
+    PciAddress.Address.Register = NB_PSTATE_STATUS;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+    SkipNbPsLoPart = FALSE;
+    if ((((NB_PSTATE_STS_REGISTER *) &PciData)->StartupNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi) &&
+        (((NB_PSTATE_STS_REGISTER *) &PciData)->StartupNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo)) {
+      SkipNbPsLoPart = TRUE;
+    }
+
+    if (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0) {
+      PciAddress.Address.Register = NB_PSTATE_0 + (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate * 4);
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+      for (i = 1; i < NM_NB_PS_REG; i++) {
+        PciAddress.Address.Register = NB_PSTATE_0 + (i * 4);
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+      }
+
+      if (!SkipNbPsLoPart) {
+        // Program D18F5x170 to transition the NB P-state:
+        // 1) NbPstateLo = NbPstateMaxVal.
+        // 2) SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0.
+
+        PciAddress.Address.Register = NB_PSTATE_CTRL;
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 0;
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateDisOnP0 = 0;
+        ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateThreshold = 0;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+        // Wait for D18F5x174[CurNbPstate] to equal NbPstateLo.
+        PciAddress.Address.Register = NB_PSTATE_STATUS;
+        do {
+          LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+        } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo);
+      }
+    }
+
+    // Program D18F5x170 to force the NB P-state:
+    // 1) NbPstateHi = target NB P-state.
+    // 2) SwNbPstateLoDis = 1
+    // And clear F5x170[NbPstateMaxVal]
+    PciAddress.Address.Register = NB_PSTATE_CTRL;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi = 0;
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader);
+
+    // Wait for D18F5x174[CurNbPstate] to equal the target NB P-state.
+    PciAddress.Address.Register = NB_PSTATE_STATUS;
+    do {
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0);
+
+    // Clear F5x1[6C:64]
+    PciData = 0x00000000;
+    for (i = 1; i < NM_NB_PS_REG; i++) {
+      PciAddress.Address.Register = NB_PSTATE_0 + (i * 4);
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+    }
+
+    // Clear MSRC001_00[6B:64][NbPstate] on cores
+    F16KbNbPstateDisCore (StdHeader);
+
+    // BIOS performs the following to release the NB P-state force:
+    // 1. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateLo] values.
+    // 2. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values.
+    PciAddress.Address.Register = NB_PSTATE_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateLo = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->SwNbPstateLoDis;
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateDisOnP0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi = 0;
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateMaxVal = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+    ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateThreshold;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Disable NB P-state on core.
+ *   - clear MSRC001_00[6B:64][NbPstate].
+ *
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F16KbNbPstateDisCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 i;
+  UINT64 MsrData;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbNbPstateDisCore\n");
+
+  // Only one core per compute unit needs to clear NbPstate in P-state MSRs
+  if (IsCoreComputeUnitPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
+    for (i = MSR_PSTATE_0; i <= MSR_PSTATE_7; i++) {
+      LibAmdMsrRead (i, &MsrData, StdHeader);
+      ((PSTATE_MSR *) &MsrData)->NbPstate = 0;
+      LibAmdMsrWrite (i, &MsrData, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get NB Frequency Numerator in MHz
+ *
+ * @param[in]     NbFid                   NB Frequency ID to convert
+ * @param[out]    FreqNumeratorInMHz      The desire NB FID's frequency numerator in megahertz.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F16KbGetNbFreqNumeratorInMHz (
+  IN       UINT32                NbFid,
+     OUT   UINT32                *FreqNumeratorInMHz,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetNbFreqNumeratorInMHz - NbFid=%d\n", NbFid);
+  *FreqNumeratorInMHz = (NbFid + 4) * 100;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FreqNumeratorInMHz=%d\n", *FreqNumeratorInMHz);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get NB Frequency Divisor
+ *
+ * @param[in]     NbDid                   NB Divisor ID to convert.
+ * @param[out]    FreqDivisor             The desire NB DID's frequency divisor.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F16KbGetNbFreqDivisor (
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FreqDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbGetNbFreqDivisor - NbDid=%d\n", NbDid);
+  *FreqDivisor = (1 << NbDid);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FreqDivisor=%d\n", *FreqDivisor);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate NB Frequency in MHz
+ *
+ * @param[in]     NbFid                   NB Frequency ID to convert
+ * @param[in]     NbDid                   NB Divisor ID to convert.
+ * @param[out]    FrequencyInMHz          The Northbridge clock frequency in megahertz.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @return        AGESA_SUCCESS           FrequencyInMHz is valid.
+ */
+AGESA_STATUS
+STATIC
+F16KbCalculateNbFrequencyInMHz (
+  IN       UINT32                NbFid,
+  IN       UINT32                NbDid,
+     OUT   UINT32                *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32        FreqNumeratorInMHz;
+  UINT32        FreqDivisor;
+  AGESA_STATUS  ReturnStatus;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbCalculateNbFrequencyInMHz - NbFid=%x, NbDid=%x\n", NbFid, NbDid);
+
+  ReturnStatus = AGESA_SUCCESS;
+  F16KbGetNbFreqNumeratorInMHz (NbFid, &FreqNumeratorInMHz, StdHeader);
+  F16KbGetNbFreqDivisor (NbDid, &FreqDivisor, StdHeader);
+  *FrequencyInMHz = FreqNumeratorInMHz / FreqDivisor;
+  IDS_HDT_CONSOLE (CPU_TRACE, "    FrequencyInMHz=%d\n", *FrequencyInMHz);
+
+  return ReturnStatus;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Convert VID to microvolts(uV)
+ *
+ * @param[in]     Vid                     The voltage ID of SVI2 encoding to be converted.
+ * @param[out]    VoltageInuV             The voltage in microvolts.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ */
+VOID
+STATIC
+F16KbCovertVidInuV (
+  IN       UINT32                Vid,
+     OUT   UINT32                *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbCovertVidInuV\n");
+  // Maximum 1.55V, 6.25mV per stpe
+  *VoltageInuV = ConvertVidInuV(Vid);
+  IDS_HDT_CONSOLE (CPU_TRACE, "    Vid=%x, VoltageInuV=%d\n", Vid, *VoltageInuV);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get Core/NB Idd Divisor
+ *
+ * @param[in]     IddDiv                  Core/NB current divisor to convert.
+ * @param[out]    IddDivisor              The desire Core/NB current divisor.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+STATIC
+F16KbCmnGetIddDivisor (
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *IddDivisor,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbCmnGetIddDivisor - IddDiv=%d\n", IddDiv);
+
+  switch (IddDiv) {
+  case 0:
+    *IddDivisor = 1000;
+    break;
+  case 1:
+    *IddDivisor = 100;
+    break;
+  case 2:
+    *IddDivisor = 10;
+    break;
+  default:  // IddDiv = 3 is reserved. Use 10
+    *IddDivisor = 10;
+    ASSERT (FALSE);
+    break;
+  }
+  IDS_HDT_CONSOLE (CPU_TRACE, "    IddDivisor=%d\n", *IddDivisor);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate Core/NB current in mA
+ *
+ * @param[in]     IddValue                Core/NB current value.
+ * @param[in]     IddDiv                  Core/NB current divisor.
+ * @param[out]    CurrentInmA             The Core/NB current in milliampere.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+STATIC
+F16KbCmnCalculateCurrentInmA (
+  IN       UINT32                IddValue,
+  IN       UINT32                IddDiv,
+     OUT   UINT32                *CurrentInmA,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32        IddDivisor;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "  F16KbCmnCalculateCurrentInmA - IddValue=%x, IddDiv=%x\n", IddValue, IddDiv);
+
+  F16KbCmnGetIddDivisor (IddDiv, &IddDivisor, StdHeader);
+  *CurrentInmA = IddValue * IddDivisor;
+
+  IDS_HDT_CONSOLE (CPU_TRACE, "    CurrentInmA=%d\n", *CurrentInmA);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h
new file mode 100644
index 0000000000..4565ccef0d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbUtilities.h
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Kabini specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 16h Kabini.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16/KB
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _F16_KB_UTILITES_H_
+#define _F16_KB_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+#define FOUR_CORE_COMPUTE_UNIT_BITMAP    0xF
+#define FOUR_CORE_COMPUTE_UNIT_BITWIDTH  0x4
+#define ALL_CORES_DISABLE_BITMAP         0xFFFFFFFFul
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT8
+F16KbGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F16KbGetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F16KbIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F16KbNbPstateDis (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+BOOLEAN
+F16KbGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F16KbGetNbIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  NbPstate,
+     OUT   UINT32                 *NbIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F16KbGetCurrentNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F16KbGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *var3,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F16KbGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+F16KbGetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif  // _F16_KB_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
new file mode 100644
index 0000000000..2330f18309
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Apm.c
@@ -0,0 +1,124 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 APM Initialization
+ *
+ * Enables Application Power Management feature
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF16PowerMgmt.h"
+#include "CommonReturns.h"
+#include "cpuApm.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16APM_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Entry point for enabling Application Power Management
+ *
+ * This function must be run after all P-State routines have been executed
+ *
+ * @param[in]  ApmServices             The current CPU's family services.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ * @retval     AGESA_SUCCESS           Always succeeds.
+ *
+ */
+STATIC AGESA_STATUS
+F16InitializeApm (
+  IN       APM_FAMILY_SERVICES    *ApmServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  F16_CPB_CTRL_REGISTER  CpbControl;
+  PCI_ADDR               PciAddress;
+
+  PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+  if (CpbControl.NumBoostStates == 0) {
+    CpbControl.ApmMasterEn = 0;
+  } else {
+    CpbControl.ApmMasterEn = 1;
+  }
+  LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+
+
+CONST APM_FAMILY_SERVICES ROMDATA F16ApmSupport =
+{
+  0,
+  (PF_APM_IS_SUPPORTED) CommonReturnTrue,
+  F16InitializeApm
+};
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
new file mode 100644
index 0000000000..444315ac9e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16BrandId.c
@@ -0,0 +1,166 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuEarlyInit.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16BRANDID_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NAME_STRING_ADDRESS_PORT 0x194
+#define NAME_STRING_DATA_PORT 0x198
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// FAM16_BRAND_STRING_MSR
+typedef struct _PROCESSOR_NAME_STRING {
+  UINT32 lo;                 ///< lower 32-bits of 64-bit value
+  UINT32 hi;                 ///< highest 32-bits of 64-bit value
+} PROCESSOR_NAME_STRING;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+F16SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+CONST CHAR8 ROMDATA str_Unprogrammed_Sample[48] = "AMD Unprogrammed Engineering Sample";
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the Processor Name String register based on F5x194/198
+ *
+ * This function copies F5x198_x[B:0] to MSR_C001_00[35:30]
+ *
+ *  @param[in]   FamilyServices      The current Family Specific Services.
+ *  @param[in]   EarlyParams         Service parameters.
+ *  @param[in]   StdHeader           Config handle for library and services.
+ *
+ */
+VOID
+F16SetBrandIdRegistersAtEarly (
+  IN       CPU_SPECIFIC_SERVICES  *FamilyServices,
+  IN       AMD_CPU_EARLY_PARAMS   *EarlyParams,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 PciData;
+  UINT32 MsrIndex;
+  UINT64 MsrData;
+  UINT64 *MsrNameStringPtrPtr;
+  PCI_ADDR PciAddress;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_5, 0);
+  PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
+  // check if D18F5x198_x0 is 00000000h.
+  PciData = 0;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+  PciAddress.Address.Register = NAME_STRING_DATA_PORT;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+  if (PciData != 0) {
+    for (MsrIndex = 0; MsrIndex <= (MSR_CPUID_NAME_STRING5 - MSR_CPUID_NAME_STRING0); MsrIndex++) {
+      PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
+      PciData = MsrIndex * 2;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+      PciAddress.Address.Register = NAME_STRING_DATA_PORT;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+      ((PROCESSOR_NAME_STRING *) (&MsrData))->lo = PciData;
+
+      PciAddress.Address.Register = NAME_STRING_ADDRESS_PORT;
+      PciData = (MsrIndex * 2) + 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+      PciAddress.Address.Register = NAME_STRING_DATA_PORT;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+      ((PROCESSOR_NAME_STRING *) (&MsrData))->hi = PciData;
+
+      LibAmdMsrWrite ((MsrIndex + MSR_CPUID_NAME_STRING0), &MsrData, StdHeader);
+    }
+  } else {
+    // It is unprogrammed (unfused) parts and use a name string of "AMD Unprogrammed Engineering Sample"
+    MsrNameStringPtrPtr = (UINT64 *) str_Unprogrammed_Sample;
+    // Put values into name MSRs,  Always write the full 48 bytes
+    for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
+      LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
+      MsrNameStringPtrPtr++;
+    }
+  }
+  return;
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
new file mode 100644
index 0000000000..b89daaabdb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16CacheDefaults.c
@@ -0,0 +1,129 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 ROM Execution Cache Defaults
+ *
+ * Contains default values for ROM execution cache setup
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16CACHEDEFAULTS_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF16CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+#define MEM_TRAINING_BUFFER_SIZE  16384
+#define VAR_MTRR_MASK             0x000000FFFFFFFFFFul
+
+#define HEAP_BASE_MASK            0x000000FFFFFFFFFFul
+
+#define SHARED_MEM_SIZE       0
+
+CONST CACHE_INFO ROMDATA CpuF16CacheInfo =
+{
+  BSP_STACK_SIZE_64K,
+  CORE0_STACK_SIZE,
+  CORE1_STACK_SIZE,
+  MEM_TRAINING_BUFFER_SIZE,
+  SHARED_MEM_SIZE,
+  VAR_MTRR_MASK,
+  VAR_MTRR_MASK,
+  HEAP_BASE_MASK,
+  InfiniteExe
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific properties of the cache, and its usage.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  CacheInfoPtr             Points to the cache info properties on exit.
+ *  @param[out]  NumberOfElements         Will be one to indicate one entry.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF16CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *CacheInfoPtr = &CpuF16CacheInfo;
+}
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c
new file mode 100644
index 0000000000..df81dcd255
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.c
@@ -0,0 +1,123 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions for Family 16h.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuLateInit.h"
+#include "cpuF16PowerMgmt.h"
+#include "cpuServices.h"
+#include "cpuF16Dmi.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16DMI_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF16GetMaxSpeed
+ *
+ *    Get the Max Speed
+ *
+ *    @param[in]      StdHeader      Standard Head Pointer
+ *
+ *    @retval  MaxSpeed   - CPU Max Speed.
+ *
+ */
+UINT16
+DmiF16GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 PP_FUSE_ARRAY_V2_fld36;
+  UINT32 P0Frequency;
+  UINT32 PciData;
+  PCI_ADDR PciAddress;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+
+  FamilyServices = NULL;
+  GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  ASSERT (FamilyServices != NULL);
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+  PP_FUSE_ARRAY_V2_fld36 = (UINT8) ((PciData >> 2) & 7);
+
+  FamilyServices->GetPstateFrequency (FamilyServices, PP_FUSE_ARRAY_V2_fld36, &P0Frequency, StdHeader);
+  return ((UINT16) P0Frequency);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.h
new file mode 100644
index 0000000000..c687c3b38e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Dmi.h
@@ -0,0 +1,76 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions for Family 16h.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F16_DMI_H_
+#define _CPU_F16_DMI_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT16
+DmiF16GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#endif  // _CPU_F16_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
new file mode 100644
index 0000000000..cf1d0d8ee9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
@@ -0,0 +1,473 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 MMIO map manager
+ *
+ * manage MMIO base/limit registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "mmioMapManager.h"
+#include "cpuF16MmioMap.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16MMIOMAP_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST UINT16 ROMDATA MmioBaseLowRegOffset[MMIO_REG_PAIR_NUM] = {0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0, 0xB8, 0x1A0, 0x1A8, 0x1B0, 0x1B8};
+STATIC CONST UINT16 ROMDATA MmioLimitLowRegOffset[MMIO_REG_PAIR_NUM] = {0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0x1A4, 0x1AC, 0x1B4, 0x1BC};
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+#define F16_MMIO_ALIGN 0x10000l
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for for adding MMIO map
+ *
+ * program MMIO base/limit registers
+ *
+ * @param[in]    MmioMapServices    MMIO map manager services.
+ * @param[in]    AmdAddMmioParams   Pointer to a data structure containing the parameter information.
+ *
+ * @retval       AGESA_STATUS       AGESA_ERROR       - The requested range could not be added because there are not
+ *                                                      enough mapping resources.
+ *                                  AGESA_BOUNDS_CHK  - One or more input parameters are invalid. For example, the
+ *                                                      TargetAddress does not correspond to any device in the system.
+ *                                  AGESA_SUCCESS     - Adding MMIO map succeeds
+ */
+AGESA_STATUS
+STATIC
+cpuF16AddingMmioMap (
+  IN       MMIO_MAP_FAMILY_SERVICES *MmioMapServices,
+  IN       AMD_ADD_MMIO_PARAMS AmdAddMmioParams
+  )
+{
+  UINT8               i;
+  UINT8               j;
+  UINT8               UnusedMmioPair;
+  UINT8               Socket;
+  UINT8               Module;
+  UINT8               MmioPair;
+  AGESA_STATUS        IgnoredSts;
+  PCI_ADDR            PciAddress;
+  MMIO_BASE_LOW       MmioBaseLow;
+  MMIO_LIMIT_LOW      MmioLimitLow;
+  MMIO_RANGE          MmioRange[MMIO_REG_PAIR_NUM];
+  MMIO_RANGE          MmioRangeTemp;
+  MMIO_RANGE          NewMmioRange;
+  MMIO_RANGE          FragmentMmioRange;
+  BOOLEAN             Overlap;
+  BOOLEAN             NewMmioIncluded;
+
+  UnusedMmioPair = 0;
+  // FragmentMMioRange is used for record the MMIO range which is splitted by overriding.
+  FragmentMmioRange.Attribute.MmioReadableRange = 0;
+  FragmentMmioRange.Attribute.MmioWritableRange = 0;
+  FragmentMmioRange.Base = 0;
+  FragmentMmioRange.Limit = F16_MMIO_ALIGN;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, FUNC_1, MmioBaseLowRegOffset[0]);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "MMIO map configuration before merging:\n");
+  IDS_HDT_CONSOLE (MAIN_FLOW, "    Base                 Limit               NP RE WE Lock DstNode DstLink DstSubLink\n");
+  for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+    // MMIO base low
+    PciAddress.Address.Register = MmioBaseLowRegOffset[MmioPair];
+    LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+    // MMIO limit low
+    PciAddress.Address.Register = MmioLimitLowRegOffset[MmioPair];
+    LibAmdPciRead (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader));
+    // get MMIO info
+    MmioRange[MmioPair].Base = (MmioBaseLow.MmioBase << 16);
+    MmioRange[MmioPair].Limit = (MmioLimitLow.MmioLimit << 16) + F16_MMIO_ALIGN;
+    MmioRange[MmioPair].Attribute.MmioPostedRange =  (UINT8) MmioLimitLow.NP;
+    MmioRange[MmioPair].Attribute.MmioReadableRange = (UINT8) MmioBaseLow.RE;
+    MmioRange[MmioPair].Attribute.MmioWritableRange =  (UINT8) MmioBaseLow.WE;
+    MmioRange[MmioPair].Attribute.MmioSecuredRange =  (UINT8) MmioBaseLow.Lock;
+    MmioRange[MmioPair].Destination.DstNode = MmioLimitLow.DstNode;
+    MmioRange[MmioPair].Destination.DstLink = MmioLimitLow.DstLink;
+    MmioRange[MmioPair].Destination.DstSubLink = MmioLimitLow.DstSubLink;
+    MmioRange[MmioPair].RangeNum = MmioPair;
+    MmioRange[MmioPair].Modified = FALSE;
+    if ((MmioRange[MmioPair].Attribute.MmioReadableRange == 0) && (MmioRange[MmioPair].Attribute.MmioWritableRange == 0)) {
+      UnusedMmioPair++;
+    }
+    IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
+    IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x    %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
+                                                         MmioRange[MmioPair].Base & 0xFFFFFFFF,
+                                                        (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
+                                                         MmioRange[MmioPair].Limit & 0xFFFFFFFF);
+    IDS_HDT_CONSOLE (MAIN_FLOW, "    %s  %s  %s  %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N",
+                                                      MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N",
+                                                      MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N",
+                                                      MmioRange[MmioPair].Attribute.MmioSecuredRange ? "Y" : "N");
+    IDS_HDT_CONSOLE (MAIN_FLOW, "    %02d      %02d      %02d\n", MmioRange[MmioPair].Destination.DstNode,
+                                                                  MmioRange[MmioPair].Destination.DstLink,
+                                                                  MmioRange[MmioPair].Destination.DstSubLink);
+  }
+
+  // parse requirement
+  NewMmioRange.Base = AmdAddMmioParams.BaseAddress;
+  NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length;
+  NewMmioRange.Attribute = AmdAddMmioParams.Attributes;
+  IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x    %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF,
+                                                         NewMmioRange.Base & 0xFFFFFFFF,
+                                                        (NewMmioRange.Limit >> 32) & 0xFFFFFFFF,
+                                                         NewMmioRange.Limit & 0xFFFFFFFF);
+
+
+  // sort by base address
+  //    range0, range1, range2, non used, non used...
+  for (i = 0; i < (MMIO_REG_PAIR_NUM - 1); i++) {
+    for (j = 0; j < (MMIO_REG_PAIR_NUM - i - 1); j++) {
+      if (((MmioRange[j].Base > MmioRange[j + 1].Base) && ((MmioRange[j + 1].Attribute.MmioReadableRange != 0) || (MmioRange[j + 1].Attribute.MmioWritableRange != 0))) ||
+          (((MmioRange[j].Attribute.MmioReadableRange == 0) && (MmioRange[j].Attribute.MmioWritableRange == 0)) &&
+          ((MmioRange[j + 1].Attribute.MmioReadableRange != 0) || (MmioRange[j + 1].Attribute.MmioWritableRange != 0)))) {
+        MmioRangeTemp = MmioRange[j];
+        MmioRange[j] = MmioRange[j + 1];
+        MmioRange[j + 1] = MmioRangeTemp;
+      }
+    }
+  }
+
+  // merge the request to current setting
+  Overlap = FALSE;
+  NewMmioIncluded = FALSE;
+  for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+    if (MmioRange[MmioPair].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair].Attribute.MmioWritableRange != 0) {
+      if (((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Base)) ||
+          ((MmioRange[MmioPair].Base <= NewMmioRange.Base) && (MmioRange[MmioPair].Limit > NewMmioRange.Base))) {
+        if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair].Attribute.MmioPostedRange) &&
+            (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair].Attribute.MmioReadableRange) &&
+            (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair].Attribute.MmioWritableRange) &&
+            (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair].Attribute.MmioSecuredRange)) {
+
+//  Original sorted MMIO register pair defined ranges:
+//                                          ____________            ________          ____________
+//                                          |          |            |      |          |          |
+//                                        base0      limit0       base1  limit1     base2      limit2
+//  Requested MMIO range:
+//    case 1:
+//     ((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Base))
+//                                                              __________
+//                                                              |        |
+//                                                         new base   new limit
+//                                                              ____________________
+//                                                              |                  |
+//                                                         new base             new limit
+//    case 2:
+//    ((MmioRange[MmioPair].Base <= NewMmioRange.Base) && (MmioRange[MmioPair].Limit >= NewMmioRange.Base))
+//                                                                                       ____________
+//                                                                                       |          |
+//                                                                                   new base   new limit
+
+          MmioRange[MmioPair].Base = (MmioRange[MmioPair].Base <= NewMmioRange.Base) ? MmioRange[MmioPair].Base : NewMmioRange.Base;
+          MmioRange[MmioPair].Modified = TRUE;
+          for (i = 1; NewMmioRange.Limit >= MmioRange[MmioPair + i].Base; i++) {
+            if ((NewMmioRange.Attribute.MmioPostedRange == MmioRange[MmioPair + i].Attribute.MmioPostedRange) &&
+                (NewMmioRange.Attribute.MmioReadableRange == MmioRange[MmioPair + i].Attribute.MmioReadableRange) &&
+                (NewMmioRange.Attribute.MmioWritableRange == MmioRange[MmioPair + i].Attribute.MmioWritableRange) &&
+                (NewMmioRange.Attribute.MmioSecuredRange == MmioRange[MmioPair + i].Attribute.MmioSecuredRange)) {
+              MmioRange[MmioPair].Limit = MmioRange[MmioPair + i].Limit;
+              MmioRange[MmioPair + i].Base = 0;
+              MmioRange[MmioPair + i].Limit = F16_MMIO_ALIGN;
+              MmioRange[MmioPair + i].Attribute.MmioReadableRange = 0;
+              MmioRange[MmioPair + i].Attribute.MmioWritableRange = 0;
+              MmioRange[MmioPair + i].Modified = TRUE;
+              UnusedMmioPair++;
+            } else if (MmioRange[MmioPair + i].Attribute.MmioReadableRange != 0 || MmioRange[MmioPair + i].Attribute.MmioWritableRange != 0) {
+              // Overlapped MMIO regions with different attributes
+              MmioRange[MmioPair].Limit = (MmioRange[MmioPair].Limit >= NewMmioRange.Limit) ? MmioRange[MmioPair].Limit : NewMmioRange.Limit;
+              NewMmioIncluded = TRUE;
+              Overlap = TRUE;
+              break;
+            }
+          }
+          MmioRange[MmioPair].Limit = (MmioRange[MmioPair + i - 1].Limit >= NewMmioRange.Limit) ? MmioRange[MmioPair + i - 1].Limit : NewMmioRange.Limit;
+          break;
+        } else {
+          // Overlapped MMIO regions with different attributes
+          Overlap = TRUE;
+          break;
+        }
+      }
+    } else {
+
+//  Original sorted MMIO register pair defined ranges:
+//                                          ____________            ________          ____________
+//                                          |          |            |      |          |          |
+//                                        base0      limit0       base1  limit1     base2      limit2
+//  Requested MMIO range:
+//    case 3:
+//     No overlapping area with the original ranges
+//                    ____________
+//                    |          |
+//                new base   new limit
+//                                                                                                        ______________
+//                                                                                                        |            |
+//                                                                                                    new base     new limit
+
+      MmioRange[MmioPair].Base = NewMmioRange.Base;
+      MmioRange[MmioPair].Limit = NewMmioRange.Limit;
+      MmioRange[MmioPair].Attribute = NewMmioRange.Attribute;
+      MmioRange[MmioPair].Modified = TRUE;
+
+      break;
+    }
+  }
+
+  if (MmioPair == MMIO_REG_PAIR_NUM) {
+    IDS_HDT_CONSOLE (MAIN_FLOW, " [ERROR] Not enough MMIO register pairs to hold the request.\n");
+    return AGESA_ERROR;
+  }
+
+  if (Overlap) {
+    if (NewMmioRange.Attribute.OverrideExisting) {
+      // First loop, to see which existing MMIO range should be overrided
+      for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+        if ((MmioRange[MmioPair].Modified == TRUE) || (NewMmioRange.Limit < MmioRange[MmioPair].Base) || (NewMmioRange.Base > MmioRange[MmioPair].Limit)) {
+          continue;
+        } else {
+          // There's an overlap between NewMmio and MmioRange[MmioPair]
+
+          //                  ____________________
+          //                  |                  |
+          //                base0              limit0
+          //                       __________
+          //                       |        |
+          //                   new base   new limit
+          if ((NewMmioRange.Base >= MmioRange[MmioPair].Base) && (NewMmioRange.Limit <= MmioRange[MmioPair].Limit)) {
+            if ((MmioRange[MmioPair].Limit - NewMmioRange.Limit) >= F16_MMIO_ALIGN) {
+              FragmentMmioRange.Base = NewMmioRange.Limit;
+              FragmentMmioRange.Limit = MmioRange[MmioPair].Limit;
+              FragmentMmioRange.Attribute = MmioRange[MmioPair].Attribute;
+              FragmentMmioRange.Destination = MmioRange[MmioPair].Destination;
+            }
+            if ((NewMmioRange.Base -  MmioRange[MmioPair].Base) < F16_MMIO_ALIGN) {
+              MmioRange[MmioPair].Attribute.MmioReadableRange = 0;
+              MmioRange[MmioPair].Attribute.MmioWritableRange = 0;
+              UnusedMmioPair++;
+            }
+            MmioRange[MmioPair].Limit = NewMmioRange.Base;
+            MmioRange[MmioPair].Modified = TRUE;
+          }
+          //                  ____________________
+          //                  |                  |
+          //                base0              limit0
+          //            ______________
+          //            |            |
+          //         new base    new limit
+          if ((NewMmioRange.Base < MmioRange[MmioPair].Base) && (NewMmioRange.Limit <= MmioRange[MmioPair].Limit) && (NewMmioRange.Limit > MmioRange[MmioPair].Base)) {
+            MmioRange[MmioPair].Base = NewMmioRange.Limit;
+            MmioRange[MmioPair].Modified = TRUE;
+            if ((MmioRange[MmioPair].Limit - NewMmioRange.Limit) < F16_MMIO_ALIGN) {
+              MmioRange[MmioPair].Attribute.MmioReadableRange = 0;
+              MmioRange[MmioPair].Attribute.MmioWritableRange = 0;
+              UnusedMmioPair++;
+            }
+          }
+          //                  ____________________
+          //                  |                  |
+          //                base0              limit0
+          //                                 ______________
+          //                                 |            |
+          //                              new base    new limit
+          if ((NewMmioRange.Base >= MmioRange[MmioPair].Base) && (NewMmioRange.Base < MmioRange[MmioPair].Limit) && (NewMmioRange.Limit > MmioRange[MmioPair].Limit)) {
+            MmioRange[MmioPair].Limit = NewMmioRange.Base;
+            MmioRange[MmioPair].Modified = TRUE;
+            if ((NewMmioRange.Base - MmioRange[MmioPair].Base) < F16_MMIO_ALIGN) {
+              MmioRange[MmioPair].Attribute.MmioReadableRange = 0;
+              MmioRange[MmioPair].Attribute.MmioWritableRange = 0;
+              UnusedMmioPair++;
+            }
+          }
+          //                  _________
+          //                  |       |
+          //                base0   limit0
+          //             ___________________
+          //             |                 |
+          //          new base         new limit
+          if ((NewMmioRange.Base <= MmioRange[MmioPair].Base) && (NewMmioRange.Limit >= MmioRange[MmioPair].Limit)) {
+            MmioRange[MmioPair].Base = 0;
+            MmioRange[MmioPair].Limit = F16_MMIO_ALIGN;
+            MmioRange[MmioPair].Attribute.MmioReadableRange = 0;
+            MmioRange[MmioPair].Attribute.MmioWritableRange = 0;
+            MmioRange[MmioPair].Attribute.MmioPostedRange = 0;
+            MmioRange[MmioPair].Attribute.MmioSecuredRange = 0;
+            MmioRange[MmioPair].Modified = TRUE;
+            UnusedMmioPair++;
+          }
+        }
+      }
+      // Let's see if there's enough MMIO registers for NewMmioRange and FragmentMmioRange
+      if (!NewMmioIncluded) {
+        UnusedMmioPair--;
+      }
+      if ((FragmentMmioRange.Attribute.MmioReadableRange != 0) && (FragmentMmioRange.Attribute.MmioWritableRange != 0)) {
+        UnusedMmioPair--;
+      }
+
+      if ((UnusedMmioPair != 0) && (UnusedMmioPair <= MMIO_REG_PAIR_NUM)) {
+        // Set MMIO for NewMmioRange and FragmentMmioRange
+        for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+          if ((MmioRange[MmioPair].Attribute.MmioReadableRange == 0) && (MmioRange[MmioPair].Attribute.MmioWritableRange == 0)) {
+            if (!NewMmioIncluded) {
+              MmioRange[MmioPair].Base = NewMmioRange.Base;
+              MmioRange[MmioPair].Limit = NewMmioRange.Limit;
+              MmioRange[MmioPair].Attribute = NewMmioRange.Attribute;
+              MmioRange[MmioPair].Modified = TRUE;
+              NewMmioIncluded = TRUE;
+            } else if ((FragmentMmioRange.Attribute.MmioReadableRange != 0) && (FragmentMmioRange.Attribute.MmioWritableRange != 0)) {
+              MmioRange[MmioPair].Base = FragmentMmioRange.Base;
+              MmioRange[MmioPair].Limit = FragmentMmioRange.Limit;
+              MmioRange[MmioPair].Attribute = FragmentMmioRange.Attribute;
+              MmioRange[MmioPair].Destination = FragmentMmioRange.Destination;
+              MmioRange[MmioPair].Modified = TRUE;
+              FragmentMmioRange.Attribute.MmioReadableRange = 0;
+              FragmentMmioRange.Attribute.MmioWritableRange = 0;
+            } else {
+              break;
+            }
+          }
+        }
+      } else {
+        // We don't have enough MMIO registers.
+        IDS_HDT_CONSOLE (MAIN_FLOW, " [ERROR] Not enough MMIO register pairs to hold the request.\n");
+        return AGESA_ERROR;
+      }
+    } else {
+      // Overlapped MMIO regions with different attributes
+      // and the caller doesn't want to override existing MMIO setting.
+      IDS_HDT_CONSOLE (MAIN_FLOW, " [ERROR] Overlapped MMIO regions with different attributes.\n");
+      return AGESA_ERROR;
+    }
+  }
+  // write back MMIO base/limit
+  IDS_HDT_CONSOLE (MAIN_FLOW, "MMIO map configuration after merging:\n");
+  IDS_HDT_CONSOLE (MAIN_FLOW, "    Base                 Limit               NP RE WE Lock DstNode DstLink DstSubLink\n");
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, &(AmdAddMmioParams.StdHeader))) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (&(AmdAddMmioParams.StdHeader), Socket, Module, &PciAddress, &IgnoredSts)) {
+          PciAddress.Address.Function = FUNC_1;
+          for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
+            IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
+            IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x    %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
+                                                                 MmioRange[MmioPair].Base & 0xFFFFFFFF,
+                                                                (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
+                                                                 MmioRange[MmioPair].Limit & 0xFFFFFFFF);
+            IDS_HDT_CONSOLE (MAIN_FLOW, "    %s  %s  %s  %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N",
+                                                              MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N",
+                                                              MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N",
+                                                              MmioRange[MmioPair].Attribute.MmioSecuredRange ? "Y" : "N");
+            IDS_HDT_CONSOLE (MAIN_FLOW, "    %02d      %02d      %02d\n", MmioRange[MmioPair].Destination.DstNode,
+                                                                          MmioRange[MmioPair].Destination.DstLink,
+                                                                          MmioRange[MmioPair].Destination.DstSubLink);
+            if (MmioRange[MmioPair].Modified) {
+              // MMIO base low
+              PciAddress.Address.Register = MmioBaseLowRegOffset[MmioRange[MmioPair].RangeNum];
+              LibAmdPciRead (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+              if (MmioBaseLow.Lock == 1) {
+                IDS_HDT_CONSOLE (MAIN_FLOW, " [ERROR] MMIO register pair locked.\n");
+                return AGESA_ERROR;
+              }
+              // Disable RE/WE before changing the address range
+              MmioBaseLow.RE = 0;
+              MmioBaseLow.WE = 0;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLow);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+
+              IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioBaseLowRegOffset[MmioRange[MmioPair].RangeNum]);
+              MmioBaseLow.MmioBase = (UINT32) (MmioRange[MmioPair].Base >> 16) & 0xFFFFFFul;
+              MmioBaseLow.RE = MmioRange[MmioPair].Attribute.MmioReadableRange;
+              MmioBaseLow.WE = MmioRange[MmioPair].Attribute.MmioWritableRange;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioBaseLow);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioBaseLow, &(AmdAddMmioParams.StdHeader));
+
+              // MMIO limit low
+              IDS_HDT_CONSOLE (MAIN_FLOW, " Reconfiguring offset %X\n", MmioLimitLowRegOffset[MmioRange[MmioPair].RangeNum]);
+              PciAddress.Address.Register = MmioLimitLowRegOffset[MmioRange[MmioPair].RangeNum];
+              LibAmdPciRead (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader));
+              MmioLimitLow.MmioLimit = (UINT32) ((MmioRange[MmioPair].Limit - 1) >> 16) & 0xFFFFFFul;
+              MmioLimitLow.NP = MmioRange[MmioPair].Attribute.MmioPostedRange;
+              MmioLimitLow.DstNode = MmioRange[MmioPair].Destination.DstNode;
+              MmioLimitLow.DstLink = MmioRange[MmioPair].Destination.DstLink;
+              MmioLimitLow.DstSubLink = MmioRange[MmioPair].Destination.DstSubLink;
+              S3_SAVE_PCI_WRITE (&(AmdAddMmioParams.StdHeader), PciAddress, AccessWidth32, &MmioLimitLow);
+              LibAmdPciWrite (AccessWidth32, PciAddress, &MmioLimitLow, &(AmdAddMmioParams.StdHeader));
+            }
+          }
+        }
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F16MmioMapSupport =
+{
+  0,
+  cpuF16AddingMmioMap
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.h
new file mode 100644
index 0000000000..d202dfbaa0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 MMIO map manager
+ *
+ * manage MMIO base/limit registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F16_MMIO_MAP_H_
+#define _CPU_F16_MMIO_MAP_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define MMIO_REG_PAIR_NUM     12
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// MMIO base low
+typedef struct {
+  UINT32 RE:1;          ///< Read enable
+  UINT32 WE:1;          ///< Write enable
+  UINT32 :1;            ///< Reserved
+  UINT32 Lock:1;        ///< Lock
+  UINT32 :4;            ///< Reserved
+  UINT32 MmioBase:24;   ///< MMIO base address register bits[39:16]
+} MMIO_BASE_LOW;
+
+/// MMIO limit low
+typedef struct {
+  UINT32 DstNode:3;     ///< Destination node ID bits
+  UINT32 :1;            ///< Reserved
+  UINT32 DstLink:2;     ///< Destination link ID
+  UINT32 DstSubLink:1;  ///< Destination sublink
+  UINT32 NP:1;          ///< Non-posted
+  UINT32 MmioLimit:24;  ///< MMIO limit address register bits[39:16]
+} MMIO_LIMIT_LOW;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_F16_MMIO_MAP_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c
new file mode 100644
index 0000000000..5299228dcd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 MSR tables for unknown processor
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 85962 $   @e \$Date: 2013-01-14 20:12:29 -0600 (Mon, 14 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16MSRUNKNOWNTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F16MsrUnknownRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_NB_CFG1 (C001001F)
+// bits[54]      InitApicIdCpuIdLo   = 0x1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MSR_NB_CFG,                          // Address
+      0x0040000000000000,                   // RegData
+      0x0040000000000000,                   // RegMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable = {
+  AllCores,
+  PERFORM_TP_BEFORE_AP_LAUNCH,
+  (sizeof (F16MsrUnknownRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *)F16MsrUnknownRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c
new file mode 100644
index 0000000000..f4bd703d69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c
@@ -0,0 +1,250 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 PCI tables for unknown processor
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 85962 $   @e \$Date: 2013-01-14 20:12:29 -0600 (Mon, 14 Jan 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16PCIUNKNOWNTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16PciUnknownRegisters[] =
+{
+// D18F0x68 - Link Transaction Control
+// bits[22:21]   DsNpReqLmt          = 0x2
+// bits[19]      ApicExtSpur         = 0x1
+// bits[18]      ApicExtId           = 0x1
+// bits[17]      ApicExtBrdCst       = 0x1
+// bits[15]      LimitCldtCfg        = 0x1
+// bits[11]      RespPassPW          = 0x1
+// bits[10]      DisFillP            = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x004E8800,                           // RegData
+      0x006E8C00,                           // RegMask
+    }}
+  },
+// D18F0x6C - Link Initialization Control
+// bits[0]       RouteTblDis         = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C),    // Address
+      0x00000000,                           // RegData
+      0x00000001,                           // RegMask
+    }}
+  },
+// D18F0x90 - Upstream Base Channel Buffer Count
+// bits[27:25]   FreeData            = 0x0
+// bits[24:20]   FreeCmd             = 0x0
+// bits[19:18]   RspData             = 0x1
+// bits[17:16]   NpReqData           = 0x1
+// bits[15:12]   ProbeCmd            = 0x0
+// bits[11:8]    RspCmd              = 0x2
+// bits[7:5]     PReq                = 0x5
+// bits[4:0]     NpReqCmd            = 0x8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90),    // Address
+      0x000502A8,                           // RegData
+      0x0FFFFFFF,                           // RegMask
+    }}
+  },
+// D18F0x94 - Link Isochronous Channel Buffer Count
+// bits[28:27]   IsocRspData         = 0x0
+// bits[26:25]   IsocNpReqData       = 0x1
+// bits[24:22]   IsocRspCmd          = 0x0
+// bits[21:19]   IsocPReq            = 0x0
+// bits[18:16]   IsocNpReqCmd        = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94),    // Address
+      0x02010000,                           // RegData
+      0x1FFF0000,                           // RegMask
+    }}
+  },
+// D18F3x6C - Data Buffer Count
+// bits[30:28]   IsocRspDBC          = 0x1
+// bits[18:16]   UpRspDBC            = 0x1
+// bits[7:6]     DnRspDBC            = 0x1
+// bits[5:4]     DnReqDBC            = 0x1
+// bits[2:0]     UpReqDBC            = 0x2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),    // Address
+      0x10010052,                           // RegData
+      0x700700F7,                           // RegMask
+    }}
+  },
+// D18F3xA0 - Power Control Miscellaneous
+// bits[13:11]   PllLockTime         = 0x1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),    // Address
+      0x00000800,                           // RegData
+      0x00003800,                           // RegMask
+    }}
+  },
+// D18F3xA4 - Reported Temperature Control
+// bits[20]      TcenPwrDnCc6En      = 0x1
+// bits[12:8]    PerStepTimeDn       = 0xF
+// bits[7]       TmpSlewDnEn         = 0x1
+// bits[6:5]     TmpMaxDiffUp        = 0x3
+// bits[4:0]     PerStepTimeUp       = 0xF
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),    // Address
+      0x00100FEF,                           // RegData
+      0x00101FFF,                           // RegMask
+    }}
+  },
+// D18F3x1CC - IBS Control
+// bits[8]       LvtOffsetVal        = 0x1
+// bits[3:0]     LvtOffset           = 0x0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC),   // Address
+      0x00000100,                           // RegData
+      0x0000010F,                           // RegMask
+    }}
+  },
+// D18F4x15C - Core Performance Boost Control
+// bits[1:0]     BoostSrc            = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_16,                        // CpuFamily
+      AMD_F16_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // PlatformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C),   // Address
+      0x00000000,                           // RegData
+      0x00000003,                           // RegMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable = {
+  PrimaryCores,
+  PERFORM_TP_BEFORE_AP_LAUNCH,
+  (sizeof (F16PciUnknownRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F16PciUnknownRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PowerMgmt.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PowerMgmt.h
new file mode 100644
index 0000000000..72ca5b84d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16PowerMgmt.h
@@ -0,0 +1,294 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 Power Management related registers defination
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPUF16POWERMGMT_H_
+#define _CPUF16POWERMGMT_H_
+
+/*
+ * Family 16h CPU Power Management MSR definitions
+ *
+ */
+
+
+/* Last Branch From IP Register 0x000001DB */
+#define MSR_BR_FROM                 0x000001DBul
+
+/* P-state Current Limit Register 0xC0010061 */
+#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061ul // F16 Shared
+
+/// Pstate Current Limit MSR Register
+typedef struct {
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 :1;                         ///< Reserved
+  UINT64 PstateMaxVal:3;             ///< Pstate Max Value
+  UINT64 :57;                        ///< Reserved
+} PSTATE_CURLIM_MSR;
+
+
+/* P-state Control Register 0xC0010062 */
+#define MSR_PSTATE_CTL 0xC0010062ul    // F16 Shared
+
+/// Pstate Control MSR Register
+typedef struct {
+  UINT64 PstateCmd:3;                ///< Pstate change command
+  UINT64 :61;                        ///< Reserved
+} PSTATE_CTRL_MSR;
+
+
+/* P-state Status Register 0xC0010063 */
+#define MSR_PSTATE_STS 0xC0010063ul
+
+/// Pstate Status MSR Register
+typedef struct {
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :61;                        ///< Reserved
+} PSTATE_STS_MSR;
+
+
+/* P-state Registers 0xC001006[B:4] */
+#define MSR_PSTATE_0 0xC0010064ul
+#define MSR_PSTATE_1 0xC0010065ul
+#define MSR_PSTATE_2 0xC0010066ul
+#define MSR_PSTATE_3 0xC0010067ul
+#define MSR_PSTATE_4 0xC0010068ul
+#define MSR_PSTATE_5 0xC0010069ul
+#define MSR_PSTATE_6 0xC001006Aul
+#define MSR_PSTATE_7 0xC001006Bul
+
+#define PS_REG_BASE MSR_PSTATE_0     /* P-state Register base */
+#define PS_MAX_REG  MSR_PSTATE_7     /* Maximum P-State Register */
+#define PS_MIN_REG  MSR_PSTATE_0     /* Minimum P-State Register */
+#define NM_PS_REG 8                  /* number of P-state MSR registers */
+
+/// P-state MSR with common field
+typedef struct {
+  UINT64 :63;                        ///< CpuFid
+  UINT64 PsEnable:1;                 ///< Pstate Enable
+} F16_PSTATE_MSR;
+
+
+/* C-state Address Register 0xC0010073 */
+#define MSR_CSTATE_ADDRESS 0xC0010073ul
+
+/// C-state Address MSR Register
+typedef struct {
+  UINT64 CstateAddr:16;              ///< C-state address
+  UINT64 :48;                        ///< Reserved
+} CSTATE_ADDRESS_MSR;
+
+
+/*
+ * Family 16h CPU Power Management PCI definitions
+ *
+ */
+
+/* Extended Memory Controller Configuration Low Register F2x1B0 */
+#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0
+
+/// Extended Memory Controller Configuration Low PCI Register
+typedef struct {
+  UINT32 AdapPrefMissRatio:2;        ///< Adaptive prefetch miss ratio
+  UINT32 AdapPrefPositiveStep:2;     ///< Adaptive prefetch positive step
+  UINT32 AdapPrefNegativeStep:2;     ///< Adaptive prefetch negative step
+  UINT32 :2;                         ///< Reserved
+  UINT32 CohPrefPrbLmt:3;            ///< Coherent prefetch probe limit
+  UINT32 DisIoCohPref:1;             ///< Disable coherent prefetched for IO
+  UINT32 EnSplitDctLimits:1;         ///< Split DCT write limits enable
+  UINT32 :7;                         ///< Reserved
+  UINT32 DblPrefEn:1;                ///< Double prefetch enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 PrefFourConf:3;             ///< Prefetch four-ahead confidence
+  UINT32 PrefFiveConf:3;             ///< Prefetch five-ahead confidence
+  UINT32 DcqBwThrotWm:4;             ///< Dcq bandwidth throttle watermark
+} EXT_MEMCTRL_CFG_LOW_REGISTER;
+
+
+/* Hardware thermal control register F3x64 */
+#define HTC_REG 0x64
+#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
+
+/// Hardware Thermal Control PCI Register
+typedef struct {
+  UINT32 HtcEn:1;                    ///< HTC Enable
+  UINT32 :3;                         ///< Reserved
+  UINT32 HtcAct:1;                   ///< HTC Active State
+  UINT32 HtcActSts:1;                ///< HTC Active Status
+  UINT32 PslApicHiEn:1;              ///< P-state limit higher APIC interrupt enable
+  UINT32 PslApicLoEn:1;              ///< P-state limit lower APIC interrupt enable
+  UINT32 :8;                         ///< Reserved
+  UINT32 HtcTmpLmt:7;                ///< HTC temperature limit
+  UINT32 HtcSlewSel:1;               ///< HTC slew-controlled temp select
+  UINT32 HtcHystLmt:4;               ///< HTC hysteresis
+  UINT32 HtcPstateLimit:3;           ///< HTC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} HTC_REGISTER;
+
+
+/* Software P-state limit register F3x68 */
+#define SW_PS_LIMIT_REG 0x68
+
+/// Software P-state Limit PCI Register
+typedef struct {
+  UINT32 :5;                         ///< Reserved
+  UINT32 SwPstateLimitEn:1;          ///< Software P-state limit enable
+  UINT32 :22;                        ///< Reserved
+  UINT32 SwPstateLimit:3;            ///< HTC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} SW_PS_LIMIT_REGISTER;
+
+/* ACPI Power State Control Registers F3x84:80 */
+
+/// System Management Action Field (SMAF) Register
+typedef struct {
+  UINT8 CpuPrbEn:1;                  ///< CPU direct probe enable
+  UINT8 NbLowPwrEn:1;                ///< Northbridge low-power enable
+  UINT8 NbGateEn:1;                  ///< Northbridge gate enable
+  UINT8 Reserved:2;                  ///< Reserved
+  UINT8 ClkDivisor:3;                ///< Clock divisor
+} SMAF_REGISTER;
+
+/// union type for ACPI State SMAF setting
+typedef union {
+  UINT8 SMAFValue;                   ///< SMAF raw value
+  SMAF_REGISTER SMAF;                ///< SMAF structure
+} ACPI_STATE_SMAF;
+
+/// ACPI Power State Control Register F3x80
+typedef struct {
+  ACPI_STATE_SMAF C2;                ///< [7:0]   SMAF Code 000b - C2
+  ACPI_STATE_SMAF C1eLinkInit;       ///< [15:8]  SMAF Code 001b - C1e or Link init
+  ACPI_STATE_SMAF SmafAct2;          ///< [23:16] SMAF Code 010b
+  ACPI_STATE_SMAF S1;                ///< [31:24] SMAF Code 011b - S1
+} ACPI_PSC_0_REGISTER;
+
+/// ACPI Power State Control Register F3x84
+typedef struct {
+  ACPI_STATE_SMAF S3;                 ///< [7:0]   SMAF Code 100b - S3
+  ACPI_STATE_SMAF Throttling;         ///< [15:8]  SMAF Code 101b - Throttling
+  ACPI_STATE_SMAF S4S5;               ///< [23:16] SMAF Code 110b - S4/S5
+  ACPI_STATE_SMAF C1;                 ///< [31:24] SMAF Code 111b - C1
+} ACPI_PSC_4_REGISTER;
+
+
+/* Popup P-state Register F3xA8 */
+#define POPUP_PSTATE_REG 0xA8
+#define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG))
+
+/// Popup P-state Register
+typedef struct {
+  UINT32 :29;                        ///< Reserved
+  UINT32 PopDownPstate:3;            ///< PopDownPstate
+} POPUP_PSTATE_REGISTER;
+
+
+/* Clock Power/Timing Control 2 Register F3xDC */
+#define CPTC2_REG 0xDC
+#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
+
+/// Clock Power Timing Control 2 PCI Register
+typedef struct {
+  UINT32 :8;                         ///< Reserved
+  UINT32 HwPstateMaxVal:3;           ///< P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbsynPtrAdj:3;              ///< NB/Core sync FIFO ptr adjust
+  UINT32 NbSynPtrAdjPstate_0:1;      ///< NB/Core synchronization FIFO pointer adjust P-state[0]
+  UINT32 CacheFlushOnHaltCtl:3;      ///< Cache flush on halt control
+  UINT32 CacheFlushOnHaltTmr:7;      ///< Cache flush on halt timer
+  UINT32 IgnCpuPrbEn:1;              ///< ignore CPU probe enable
+  UINT32 NbSynPtrAdjLo:3;            ///< NB/core synchronization FIFO pointer adjust low
+  UINT32 NbsynPtrAdjPstate2_1:2;     ///< NB/core synchronization FIFO pointer adjust P-state[2:1]
+} CLK_PWR_TIMING_CTRL2_REGISTER;
+
+
+/* Core Performance Boost Control Register D18F4x15C */
+#define CPB_CTRL_REG 0x15C
+#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
+
+/// Core Performance Boost Control Register of Family 16h common aceess
+typedef struct {
+  UINT32 BoostSrc:2;                 ///< Boost source
+  UINT32 NumBoostStates:3;           ///< Number of boosted states
+  UINT32 :2;                         ///< Reserved
+  UINT32 ApmMasterEn:1;              ///< APM master enable
+  UINT32 CstatePowerEn:1;            ///< C-state power enable
+  UINT32 :22;                        ///< Reserved
+  UINT32 BoostLock:1;                ///< Boost source
+} F16_CPB_CTRL_REGISTER;
+
+
+#define NM_NB_PS_REG 4               /* Number of NB P-state registers */
+
+/* Northbridge P-state */
+#define NB_PSTATE_0 0x160
+#define NB_PSTATE_0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_0))
+
+#define NB_PSTATE_1 0x164
+#define NB_PSTATE_1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_1))
+
+#define NB_PSTATE_2 0x168
+#define NB_PSTATE_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_2))
+
+#define NB_PSTATE_3 0x16C
+#define NB_PSTATE_3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_3))
+
+
+/* Northbridge P-state Status */
+#define F16_NB_PSTATE_CTRL 0x170
+#define F16_NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, F16_NB_PSTATE_CTRL))
+
+/// Northbridge P-state Control Register
+typedef struct {
+  UINT32 NbPstateMaxVal:2;           ///< NB P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateLo:2;               ///< NB P-state low
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateHi:2;               ///< NB P-state high
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateThreshold:3;        ///< NB P-state threshold
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbPstateDisOnP0:1;          ///< NB P-state disable on P0
+  UINT32 SwNbPstateLoDis:1;          ///< Software NB P-state low disable
+  UINT32 :17;                        ///< Reserved
+} F16_NB_PSTATE_CTRL_REGISTER;
+
+
+#endif /* _CPUF16POWERMGMT_H */
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
new file mode 100644
index 0000000000..87748240c7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.c
@@ -0,0 +1,417 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 16h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPstateTables.h"
+#include "cpuF16PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuF16Utilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuPostInit.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16UTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Disables the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The P-State to disable.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F16DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  ((F16_PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 0;
+  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Transitions the executing core to the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The new P-State to make effective.
+ *  @param[in]   WaitForTransition        True if the caller wants the transition completed upon return.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS       Always Succeeds
+ */
+AGESA_STATUS
+F16TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64       LocalMsrRegister;
+
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
+  ASSERT (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal >= StateNumber);
+  LibAmdMsrRead (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader);
+  ((PSTATE_CTRL_MSR *) &LocalMsrRegister)->PstateCmd = (UINT64) StateNumber;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &LocalMsrRegister, StdHeader);
+  if (WaitForTransition) {
+    do {
+      LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+    } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != (UINT64) StateNumber);
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the rate at which the executing core's time stamp counter is
+ *  incrementing.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  FrequencyInMHz           TSC actual frequency.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ *  @return      The most severe status of all called services
+ */
+AGESA_STATUS
+F16GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8        NumBoostStates;
+  UINT32       LocalPciRegister;
+  UINT64       LocalMsrRegister;
+  PCI_ADDR     PciAddress;
+  PSTATE_CPU_FAMILY_SERVICES  *FamilyServices;
+
+  LibAmdMsrRead (0xC0010015, &LocalMsrRegister, StdHeader);
+  if ((LocalMsrRegister & 0x01000000) != 0) {
+    FamilyServices = NULL;
+    GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    ASSERT (FamilyServices != NULL);
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_4, CPB_CTRL_REG);
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    NumBoostStates = (UINT8) ((F16_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+    return (FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, FrequencyInMHz, StdHeader));
+  } else {
+    return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initially launches the desired core to run from the reset vector.
+ *
+ * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   SocketNum                The Processor on which the core is to be launched
+ * @param[in]   ModuleNum                The Module in that processor containing that core
+ * @param[in]   CoreNum                  The Core to launch
+ * @param[in]   PrimaryCoreNum           The id of the module's primary core.
+ * @param[in]   StdHeader                Header for library and services
+ *
+ * @retval      TRUE          The core was launched
+ * @retval      FALSE         The core was previously launched
+ */
+BOOLEAN
+F16LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    NodeRelativeCoreNum;
+  UINT32    LocalPciRegister;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   LaunchFlag;
+
+  NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = 0x18;
+  PciAddress.Address.Function = FUNC_0;
+  PciAddress.Address.Register = CORE_CTRL;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+  GetGivenModuleCoreRange (0, 0, &LowCore, &HighCore, StdHeader);
+  ASSERT ((NodeRelativeCoreNum != 0) || (NodeRelativeCoreNum <= HighCore))
+
+  if ((LocalPciRegister & (1 << NodeRelativeCoreNum)) == 0) {
+    LocalPciRegister |= (1 << NodeRelativeCoreNum);
+    LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    LaunchFlag = TRUE;
+  } else {
+    LaunchFlag = FALSE;
+  }
+
+  return (LaunchFlag);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F16GetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NbVidUpdateAll = FALSE;
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      PlatformConfig                 Platform profile/build option config structure.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F16IsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   LocalPciRegister;
+  PCI_ADDR PciAddress;
+  BOOLEAN  PowerMode;
+  BOOLEAN  SkipHwCfg;
+
+  SkipHwCfg = FALSE;
+
+  IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader);
+
+  // Defaults to Power Optimized Mode
+  PowerMode = TRUE;
+
+  // If system is optimized for performance, disable NB P-States
+  if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) {
+    PowerMode = FALSE;
+  }
+
+  PciAddress.AddressValue = F16_NB_PSTATE_CTRL_PCI_ADDR;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  if ((((((F16_NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal != 0) &&
+      (!IsNonCoherentHt1 (StdHeader))) || SkipHwCfg) && (PowerMode)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
+ *
+ *  This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Handle of Header for calling lib functions and services.
+ *  @param[in]  Request                  Indicate warm reset status
+ *
+ */
+VOID
+F16SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  PciData &= ~(HT_INIT_BIOS_RST_DET_0);
+  PciData = PciData | (Request->RequestBit << 5);
+
+  // bit[10,9] - indicate warm reset status and count
+  PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
+  PciData |= Request->StateBits << 9;
+
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
+ *
+ *  This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Config handle for library and services
+ *  @param[out] Request                  Indicate warm reset status
+ *
+ */
+VOID
+F16GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
+  // bit[10,9] - indicate warm reset status and count
+  Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Return a number zero or one, based on the Core ID position in the initial APIC Id.
+ *
+ * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @retval        CoreIdPositionZero      Core Id is not low
+ * @retval        CoreIdPositionOne       Core Id is low
+ */
+CORE_ID_POSITION
+F16CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64 InitApicIdCpuIdLo;
+
+  //  Check bit_54 [InitApicIdCpuIdLo] to find core id position.
+  LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
+  InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
+  return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h
new file mode 100644
index 0000000000..e635fb0938
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16Utilities.h
@@ -0,0 +1,144 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 16h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F16_UTILITES_H_
+#define _CPU_F16_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// The structure for Software Initiated NB Voltage Transitions
+typedef struct {
+  UINT32  VidCode;          ///< VID code to transition to
+  BOOLEAN SlamMode;         ///< Whether voltage is to be slammed, or stepped
+} SW_VOLT_TRANS_NB;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+F16DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F16TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F16GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F16LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F16GetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F16IsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+CORE_ID_POSITION
+F16CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F16SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+VOID
+F16GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   WARM_RESET_REQUEST *Request
+  );
+
+#endif  // _CPU_F16_UTILITES_H_
+
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
new file mode 100644
index 0000000000..ab06fe196f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
@@ -0,0 +1,127 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_16 WHEA initial Data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x16
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G3_DXE)
+RDATA_GROUP (G3_DXE)
+
+#define FILECODE PROC_CPU_FAMILY_0X16_CPUF16WHEAINITDATATABLES_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF16WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F16WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AMD_HEST_BANK_INIT_DATA F16HestBankInitData[] = {
+  {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
+  {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
+  {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
+  {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
+  {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
+  {0xFFFFFFFF,0xFFFFFFFF,0x418,0x419,0x41A,0x41B},
+};
+
+AMD_WHEA_INIT_DATA F16WheaInitData = {
+  0x000000000,              // AmdGlobCapInitDataLsd
+  0x000000000,              // AmdGlobCapInitDataMsd
+  0x000000077,              // AmdGlobCtrlInitDataLsd
+  0x000000000,              // AmdGlobCtrlInitDataMsd
+  0x00,                     // AmdMcbClrStatusOnInit
+  0x02,                     // AmdMcbStatusDataFormat
+  0x00,                     // AmdMcbConfWriteEn
+  (sizeof (F16HestBankInitData) / sizeof (F16HestBankInitData[0])), // HestBankNum
+  &F16HestBankInitData[0]   // Pointer to Initial data of HEST Bank
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific WHEA table properties.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  F16WheaInitDataPtr       Points to the family 16h WHEA properties.
+ *  @param[out]  NumberOfElements         Will be one to indicate one structure.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF16WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F16WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *F16WheaInitDataPtr = &F16WheaInitData;
+}
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h
new file mode 100644
index 0000000000..cfd0dae86a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h
@@ -0,0 +1,125 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FAM_REGISTERS_H_
+#define _CPU_FAM_REGISTERS_H_
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      M O D U L E S    U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ *                      D E F I N I T I O N S  /  M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+// This define should be equal to the total number of families
+// in the cpuFamily enum.
+#define MAX_CPU_FAMILIES    64
+#define MAX_CPU_REVISIONS   63    // Max Cpu Revisions Per Family
+
+// CPU_LOGICAL_ID.Family equates
+// Family 15h equates
+#define AMD_FAMILY_15_TN  0x0000000000000200ull
+#define AMD_FAMILY_TN     (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_15     (AMD_FAMILY_15_TN)
+
+// Family 16h equates
+#define AMD_FAMILY_16_KB  0x0000000000010000ull
+#define AMD_FAMILY_KB     AMD_FAMILY_16_KB
+#define AMD_FAMILY_16     (AMD_FAMILY_KB)
+
+// Family Unknown
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
+
+
+// Family 15h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+  // Family 15h TN steppings
+#define AMD_F15_TN_A0    0x0000000000000100ull
+#define AMD_F15_TN_A1    0x0000000000000200ull
+  // Family 15h Unknown stepping
+  // * This equate is used to ensure that unknown CPU revisions are       *
+  // * identified as the last known revision of the silicon family:       *
+  // * - Update AMD_F15_UNKNOWN whenever newer F15h steppings are added   *
+#define AMD_F15_UNKNOWN  (AMD_FAMILY_UNKNOWN | AMD_F15_TN_A1)
+
+
+#define AMD_F15_TN_Ax    (AMD_F15_TN_A0 | AMD_F15_TN_A1)
+#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0)
+#define AMD_F15_TN_ONLY  (AMD_F15_TN_Ax)
+#define AMD_F15_TN_ALL   (AMD_F15_TN_Ax | AMD_F15_RL_ALL)
+
+
+#define AMD_F15_ALL      (AMD_F15_TN_ALL)
+
+// Family 16h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+  // Family 16h KB steppings
+#define AMD_F16_KB_A0    0x0000000000000001ull
+#define AMD_F16_KB_A1    0x0000000000000002ull
+  // Family 16h ML steppings
+  // Family 16h Unknown stepping
+  // * This equate is used to ensure that unknown CPU revisions are       *
+  // * identified as the last known revision of the silicon family:       *
+  // * - Update AMD_F16_UNKNOWN whenever newer F16h steppings are added   *
+#define AMD_F16_UNKNOWN  (AMD_FAMILY_UNKNOWN | AMD_F16_KB_A1)
+
+#define AMD_F16_KB_Ax    (AMD_F16_KB_A0 | AMD_F16_KB_A1)
+#define AMD_F16_KB_ALL   (AMD_F16_KB_Ax)
+
+
+#define AMD_F16_ALL      (AMD_F16_KB_ALL)
+
+#endif      // _CPU_FAM_REGISTERS_H_
+
author	Siyuan Wang <wangsiyuanbuaa@gmail.com>	2013-07-25 15:14:15 +0800
committer	Bruce Griffith <Bruce.Griffith@se-eng.com>	2013-08-04 05:40:37 +0200
commit	affe85fbc8a13d35960aa92ae87cbb6330ad253f (patch)
tree	9c1ace69f12b06b6544faf041994aa4288fb2e45 /src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family
parent	ae8d06969bdde9b1250bc3c4ad93f5db408dae98 (diff)