vendorcode/amd: 64bit fixes

Change-Id: I6a0752cf0c0e484e670acca97c4991b5578845fb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11081
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

14 files changed, 65 insertions, 59 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
index abbb6d4ef9..b2cf9f35e5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h
@@ -840,7 +840,7 @@ typedef enum {                        //vv- for debug reference only
 #define IDS_CALLOUT_POWER_PLAN_INIT               0x8D        ///< The function data of IDS callout function of Override Power Plan Init
 /// Function entry for HDT script to call
 typedef struct _SCRIPT_FUNCTION {
-  UINT32  FuncAddr;       ///< Function address in ROM
+  UINTN   FuncAddr;       ///< Function address in ROM
   CHAR8   FuncName[40];   ///< Function name
 } SCRIPT_FUNCTION;
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
index a60667f293..5fe172c6e3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionIdsInstall.h
@@ -74,29 +74,29 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
   #if (AGESA_ENTRY_INIT_POST == TRUE)
     #include <mu.h>
     CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINT32) /*(UINT64)*/ MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
-      { (UINT32) /*(UINT64)*/ MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
-      { (UINT32) /*(UINT64)*/ MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
+      { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+      { (UINTN) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+      { (UINTN) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
     };
   #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
     #include <mru.h>
     CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
-      { (UINT32) (UINT64) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
-      { (UINT32) (UINT64) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
+      { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+      { (UINTN) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
+      { (UINTN) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
     };
   #else
     CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
-      { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
-      { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
+      { (UINTN) CommonReturnFalse, "DefRet()"},
+      { (UINTN) CommonReturnFalse,  "DefRet()"},
+      { (UINTN) CommonReturnFalse,    "DefRet()"}
     };
   #endif
 #else
   CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-    { (UINT32) /*(UINT64)*/ CommonReturnFalse, "DefRet()"},
-    { (UINT32) /*(UINT64)*/ CommonReturnFalse,  "DefRet()"},
-    { (UINT32) /*(UINT64)*/ CommonReturnFalse,    "DefRet()"}
+    { (UINTN) CommonReturnFalse, "DefRet()"},
+    { (UINTN) CommonReturnFalse,  "DefRet()"},
+    { (UINTN) CommonReturnFalse,    "DefRet()"}
   };
 #endif
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
index 7d90f8bb5a..9ae45c3ee2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
+++ b/src/vendorcode/amd/agesa/f15tn/Include/gcc-intrin.h
@@ -27,11 +27,11 @@
  */
 
 #if defined (__GNUC__)
-
+#include <stdint.h>
 /* I/O intrin functions.  */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint8_t __inbyte(uint16_t Port)
 {
-  unsigned char value;
+  uint8_t value;
 
   __asm__ __volatile__ (
     "in  %1, %0"
@@ -42,9 +42,9 @@ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned
   return value;
 }
 
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint16_t __inword(uint16_t Port)
 {
-  unsigned short value;
+  uint16_t value;
 
   __asm__ __volatile__ (
     "in  %1, %0"
@@ -55,9 +55,9 @@ static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigne
   return value;
 }
 
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+static __inline__ __attribute__((always_inline)) uint32_t __indword(uint16_t Port)
 {
-  unsigned long value;
+  uint32_t value;
 
   __asm__ __volatile__ (
     "in  %1, %0"
@@ -68,7 +68,7 @@ static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigne
 
 }
 
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+static __inline__ __attribute__((always_inline)) void __outbyte(uint16_t Port,uint8_t Data)
 {
   __asm__ __volatile__ (
     "out  %0, %1"
@@ -77,7 +77,7 @@ static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short P
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+static __inline__ __attribute__((always_inline)) void __outword(uint16_t Port,uint16_t Data)
 {
   __asm__ __volatile__ (
     "out  %0, %1"
@@ -86,7 +86,7 @@ static __inline__ __attribute__((always_inline)) void __outword(unsigned short P
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+static __inline__ __attribute__((always_inline)) void __outdword(uint16_t Port,uint32_t Data)
 {
   __asm__ __volatile__ (
     "out  %0, %1"
@@ -95,7 +95,7 @@ static __inline__ __attribute__((always_inline)) void __outdword(unsigned short
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
 {
   __asm__ __volatile__ (
     "rep ; insb"
@@ -104,7 +104,7 @@ static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned sh
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __inwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
 {
   __asm__ __volatile__ (
     "rep ; insw"
@@ -113,7 +113,7 @@ static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned sh
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __indwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
 {
   __asm__ __volatile__ (
     "rep ; insl"
@@ -122,7 +122,7 @@ static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned s
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outbytestring(uint16_t Port,uint8_t *Buffer,unsigned long Count)
 {
   __asm__ __volatile__ (
     "rep ; outsb"
@@ -131,7 +131,7 @@ static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned s
     );
 }
 
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outwordstring(uint16_t Port,uint16_t *Buffer,unsigned long Count)
 {
   __asm__ __volatile__ (
     "rep ; outsw"
@@ -140,7 +140,7 @@ static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned s
   );
 }
 
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+static __inline__ __attribute__((always_inline)) void __outdwordstring(uint16_t Port,unsigned long *Buffer,unsigned long Count)
 {
   __asm__ __volatile__ (
    "rep ; outsl"
@@ -525,7 +525,7 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
 }
 
 static __inline__ __attribute__((always_inline)) void
-__writefsbyte(const unsigned long Offset, const unsigned char Data)
+__writefsbyte(const unsigned long Offset, const uint8_t Data)
 {
   __asm__ ("movb %[Data], %%fs:%a[Offset]"
           :
@@ -533,7 +533,7 @@ __writefsbyte(const unsigned long Offset, const unsigned char Data)
 }
 
 static __inline__ __attribute__((always_inline)) void
-__writefsword(const unsigned long Offset, const unsigned short Data)
+__writefsword(const unsigned long Offset, const uint16_t Data)
 {
   __asm__ ("movw %[Data], %%fs:%a[Offset]"
           :
@@ -541,14 +541,14 @@ __writefsword(const unsigned long Offset, const unsigned short Data)
 }
 
 static __inline__ __attribute__((always_inline)) void
-__writefsdword(const unsigned long Offset, const unsigned long Data)
+__writefsdword(const unsigned long Offset, const uint32_t Data)
 {
   __asm__ ("movl %[Data], %%fs:%a[Offset]"
            :
            : [Offset] "ir" (Offset), [Data] "ir" (Data));
 }
 
-static __inline__ __attribute__((always_inline)) unsigned char
+static __inline__ __attribute__((always_inline)) uint8_t
 __readfsbyte(const unsigned long Offset)
 {
   unsigned char value;
@@ -558,7 +558,7 @@ __readfsbyte(const unsigned long Offset)
   return value;
 }
 
-static __inline__ __attribute__((always_inline)) unsigned short
+static __inline__ __attribute__((always_inline)) uint16_t
 __readfsword(const unsigned long Offset)
 {
   unsigned short value;
@@ -568,11 +568,11 @@ __readfsword(const unsigned long Offset)
   return value;
 }
 
-static __inline__ __attribute__((always_inline)) unsigned long
+static __inline__ __attribute__((always_inline)) uint32_t
 __readfsdword(unsigned long Offset)
 {
   unsigned long value;
-  __asm__ ("movl %%fs:%a[Offset], %[value]"
+  __asm__ ("mov %%fs:%a[Offset], %[value]"
            : [value] "=r" (value)
            : [Offset] "ir" (Offset));
   return value;
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
index b30770642d..4188f1b7be 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/Dispatcher.c
@@ -82,8 +82,8 @@ AmdAgesaDispatcher (
   IMAGE_ENTRY ImageEntry;
   MODULE_ENTRY  ModuleEntry;
   DISPATCH_TABLE *Entry;
-  UINT32 ImageStart;
-  UINT32 ImageEnd;
+  UINTN ImageStart;
+  UINTN ImageEnd;
   CONST AMD_IMAGE_HEADER* AltImagePtr;
 
   Status = AGESA_UNSUPPORTED;
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
index 1df58aa4c9..198b404f0f 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/agesaCallouts.c
@@ -434,7 +434,7 @@ AgesaFchOemCallout (
   IN      VOID              *FchData
   )
 {
-  AGESA_STATUS Status;  Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINT32)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader);  return  Status;	//return AGESA_UNSUPPORTED;
+  AGESA_STATUS Status;  Status = AmdAgesaCallout(AGESA_FCH_OEM_CALLOUT, (UINTN)FchData, ((FCH_DATA_BLOCK *)FchData)->StdHeader);  return  Status;	//return AGESA_UNSUPPORTED;
 }
 
 /*---------------------------------------------------------------------------------------*/
@@ -454,7 +454,7 @@ excel331  (
 {
   AGESA_STATUS Status;
 
-  Status =  AmdAgesaCallout (0x00028146ul , (UINT32)SocketIdModuleId, MemData);
+  Status =  AmdAgesaCallout (0x00028146ul , SocketIdModuleId, MemData);
 
   return Status;
 }
diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
index 7ed5f16b5c..ec17b95504 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
@@ -147,7 +147,7 @@ CopyHeapToTempRamAtPost (
       //
       // 0xC0000 ~ 0xFFFFF
       //
-      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
+      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + ((((UINTN)AmdHeapRamAddress >> 16) & 0x3) * 2));
       MsrData = AMD_MTRR_FIX4K_UC_DRAM;
       LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
       LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
@@ -155,7 +155,7 @@ CopyHeapToTempRamAtPost (
       //
       // 0x80000~0xBFFFF
       //
-      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
+      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + (((UINTN)AmdHeapRamAddress >> 17) & 0x1));
       MsrData = AMD_MTRR_FIX16K_UC_DRAM;
       LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
     } else {
@@ -164,7 +164,7 @@ CopyHeapToTempRamAtPost (
       //
       LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
       MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
-      MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
+      MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * (((UINTN)AmdHeapRamAddress >> 16) & 0x7)));
       LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
     }
 
@@ -208,7 +208,7 @@ CopyHeapToTempRamAtPost (
     TotalSize = sizeof (HEAP_MANAGER);
     SizeOfNodeData = 0;
     AlignTo16ByteInTempMem = 0;
-    BaseAddressInCache = (UINT8 *) (UINT32)StdHeader->HeapBasePtr;
+    BaseAddressInCache = (UINT8 *) (UINTN)StdHeader->HeapBasePtr;
     HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
     HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
     HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
@@ -307,8 +307,8 @@ CopyHeapToMainRamAtPost (
     TotalSize = sizeof (HEAP_MANAGER);
     SizeOfNodeData = 0;
     AlignTo16ByteInMainMem = 0;
-    BaseAddressInTempMem = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
-    HeapManagerInTempMem = (HEAP_MANAGER *)(UINT32) StdHeader->HeapBasePtr;
+    BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
+    HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr;
     HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
     HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc
index 0de46b01d3..986fbc5a15 100644
--- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc
+++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc
@@ -77,15 +77,21 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Include/Library
 AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson
 
 CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
 
 export AGESA_ROOT := $(AGESA_ROOT)
 export AGESA_INC  := $(AGESA_INC)
 CPPFLAGS_x86_32 += $(AGESA_INC)
+CPPFLAGS_x86_64 += $(AGESA_INC)
 #######################################################################
 
 classes-y += libagesa
 
+ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
 $(eval $(call create_class_compiler,libagesa,x86_32))
+else
+$(eval $(call create_class_compiler,libagesa,x86_64))
+endif
 
 libagesa-y += Legacy/Proc/Dispatcher.c
 libagesa-y += Legacy/Proc/agesaCallouts.c
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
index 2e454714d6..f28159363b 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -155,7 +155,7 @@ HeapManagerInit (
 
   GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
   FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
-  HeapBufferPtr = (UINT8 *)(UINT32) StdHeader->HeapBasePtr;
+  HeapBufferPtr = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
 
   // Check whether the heap manager is already initialized
   LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
@@ -325,14 +325,14 @@ HeapAllocateBuffer (
   // Check Heap database is valid
   if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
     // The base address in StdHeader is incorrect, get base address by itself
-    BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+    BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
     HeapManager = (HEAP_MANAGER *) BaseAddress;
     if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
       // Heap is not available, ASSERT here
       ASSERT (FALSE);
       return AGESA_ERROR;
     }
-    StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+    StdHeader->HeapBasePtr = (UINTN)BaseAddress;
   }
 
   // Allocate
@@ -470,14 +470,14 @@ HeapDeallocateBuffer (
   // Check Heap database is valid
   if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
     // The base address in StdHeader is incorrect, get base address by itself
-    BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+    BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
     HeapManager = (HEAP_MANAGER *) BaseAddress;
     if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
       // Heap is not available, ASSERT here
       ASSERT (FALSE);
       return AGESA_ERROR;
     }
-    StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+    StdHeader->HeapBasePtr = (UINTN)BaseAddress;
   }
 
   OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
@@ -599,14 +599,14 @@ HeapLocateBuffer (
   // Check Heap database is valid
   if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
     // The base address in StdHeader is incorrect, get base address by itself
-    BaseAddress = (UINT8 *)(UINT32) HeapGetBaseAddress (StdHeader);
+    BaseAddress = (UINT8 *)(UINTN) HeapGetBaseAddress (StdHeader);
     HeapManager = (HEAP_MANAGER *) BaseAddress;
     if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
       // Heap is not available, ASSERT here
       ASSERT (FALSE);
       return AGESA_ERROR;
     }
-    StdHeader->HeapBasePtr = (UINT64)(UINT32) BaseAddress;
+    StdHeader->HeapBasePtr = (UINTN)BaseAddress;
   }
   OffsetOfCurrentNode =  HeapManager->FirstActiveBufferOffset;
   CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
index fb8edd9835..2f23a7ab7e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdS3LateRestore.c
@@ -119,7 +119,7 @@ AmdS3LateRestore (
   ASSERT (S3LateParams != NULL);
 
   BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
-  S3LateParams->StdHeader.HeapBasePtr = (UINT32) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+  S3LateParams->StdHeader.HeapBasePtr = (UINTN) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
   ASSERT (S3LateParams->StdHeader.HeapBasePtr != 0);
 
   IDS_HDT_CONSOLE_INIT (&S3LateParams->StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
index 1a934eb916..ac3318ab95 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
@@ -125,7 +125,7 @@ typedef enum {
 
 /// Graphics Platform Configuration
 typedef struct {
-  UINT32                       StdHeader;                ///< Standard Header TODO: Used to be PVOID
+  UINTN                       StdHeader;                ///< Standard Header TODO: Used to be PVOID
   PCI_ADDR                    GfxPciAddress;            ///< Graphics PCI Address
   UMA_INFO                    UmaInfo;                  ///< UMA Information
   UINT32                      GmmBase;                  ///< GMM Base
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
index b25c50c7b3..e8194f8202 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
@@ -355,7 +355,7 @@ typedef struct {
 /// PCIe platform configuration info
 typedef struct {
   PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
-  UINT32                  StdHeader;                    ///< Standard configuration header TODO:Used to be PVOID
+  UINTN                   StdHeader;                    ///< Standard configuration header TODO:Used to be PVOID
   UINT32                  LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
   UINT32                  LinkL0Pooling;                ///< Pooling for link to get to L0 in us
   UINT32                  LinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
index b822294573..8befb2cd5e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -183,7 +183,7 @@ GfxLocateConfigData (
     IDS_ERROR_TRAP;
     return  AGESA_FATAL;
   }
-  (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+  (*Gfx)->StdHeader = /* (PVOID) */(UINTN)StdHeader;
   return AGESA_SUCCESS;
 }
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
index 49fd4cb7de..f0fe7f86a5 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -113,7 +113,7 @@ GfxConfigPostInterface (
       Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
       Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
     }
-    Gfx->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+    Gfx->StdHeader = /* (PVOID) */(UINTN) StdHeader;
     Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
     Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
     Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
index 0719e5256e..f66fd9b419 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -432,7 +432,7 @@ PcieLocateConfigurationData (
     IDS_ERROR_TRAP;
     return AGESA_FATAL;
   }
-  (*Pcie)->StdHeader = /* (PVOID) */ (UINT32)StdHeader;
+  (*Pcie)->StdHeader = /* (PVOID) */ (UINTN)StdHeader;
   PcieUpdateConfigurationData (*Pcie);
   return  AGESA_SUCCESS;
 }