src/vendorcode/amd: correct spelling of MTRR

Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

6 files changed, 10 insertions, 10 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
index ec17b95504..577ff14852 100644
--- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
@@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost (
   //
   if (AmdHeapRamAddress < 0x100000) {
     // Region below 1MB
-    // Fixed MTTR region
+    // Fixed MTRR region
     // turn on modification bit
     LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
     MsrData |= 0x80000;
@@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost (
       LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
     }
 
-    // Turn on MTTR enable bit and turn off modification bit
+    // Turn on MTRR enable bit and turn off modification bit
     LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
     MsrData |= 0x40000;
     MsrData &= 0xFFFFFFFFFFF7FFFF;
     LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
   } else {
     // Region above 1MB
-    // Variable MTTR region
+    // Variable MTRR region
     // Get family specific cache Info
     GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
     FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
index fcd7bf466c..e9c89227dc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
@@ -281,7 +281,7 @@ AllocateExecutionCache (
     RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
 
     if (RequestStartAddr < 0x100000) {
-      // Region starts below 1MB - Fixed MTTR region,
+      // Region starts below 1MB - Fixed MTRR region,
       // turn on modification bit: MtrrFixDramModEn
       LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
       MsrData |= 0x80000;
@@ -299,7 +299,7 @@ AllocateExecutionCache (
                      i, RequestStartAddr, RequestSize, 0, StdHeader);
       }
 
-      // Find start MTTR and end MTTR for the requested region
+      // Find start MTRR and end MTRR for the requested region
       StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
       EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
 
@@ -325,7 +325,7 @@ AllocateExecutionCache (
 
 
     } else {
-      // Region above 1MB -  Variable MTTR region
+      // Region above 1MB -  Variable MTRR region
       //    Need to check both VarMTRRs for each requested region for match or overlap
       //
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
index 4ab535a3fe..c1e7ab7b6c 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
@@ -187,7 +187,7 @@ EFLoop:
 
     AMD_DISABLE_STACK_FAMILY_HOOK
 
-    /* restore variable MTTR6 and MTTR7 to default states */
+    /* restore variable MTRR6 and MTRR7 to default states */
     bt $FLAG_IS_PRIMARY, %esi                     /* .if (esi & 1h) */
     jz  6f
       movl $AMD_MTRR_VARIABLE_MASK7,  %ecx  /* clear MTRRPhysBase6 MTRRPhysMask6 */
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
index f28159363b..4b6b6ec675 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
@@ -188,7 +188,7 @@ HeapManagerInit (
   MsrData = (UINT64) (AMD_TEMP_TOM);
   LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
 
-  // Enable variable MTTRs
+  // Enable variable MTRRs
   LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
   MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
   LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
index 24a607377c..8947491717 100644
--- a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
+++ b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
@@ -221,7 +221,7 @@ AMD_ENABLE_STACK MACRO
     mov     ecx, TOP_MEM2               ; MSR:C001_001D
     _WRMSR
 
-    ; setup MTTRs for stacks
+    ; setup MTRRs for stacks
     ;   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
     ;    or due to a data zone being interpreted as code. When a speculative read occurs outside a
     ;    controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index 5118a4ca4a..1701a213f3 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1677,7 +1677,7 @@ SetupStack:
     mov     $TOP_MEM2, %ecx               # MSR:C001_001D
     _WRMSR
 
-    # setup MTTRs for stacks
+    # setup MTRRs for stacks
     #   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
     #    or due to a data zone being interpreted as code. When a speculative read occurs outside a
     #    controlled region (intentionally used by software), it could cause an unwanted cache eviction.