diff options
author | zbao <fishbaozi@gmail.com> | 2012-07-02 14:19:14 +0800 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-03 09:36:35 +0200 |
commit | 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc (patch) | |
tree | b0b385455992f0ad3ca6dbbd3266a7a386a80d4f /src/vendorcode/amd/agesa/f15tn/Proc/IDS | |
parent | 78efc4c36c68b51b3e73acdb721a12ec23ed0369 (diff) |
AGESA F15tn: AMD family15 AGESA code for Trinity
AMD AGESA code for trinity.
Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/IDS')
25 files changed, 8092 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c new file mode 100644 index 0000000000..c0e0cbcac4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsCtrl.c @@ -0,0 +1,855 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Option Backend Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "Topology.h" +#include "htFeat.h" +#include "IdsHt.h" +#include "amdlib.h" +#include "mm.h" +#include "mn.h" +#include "cpuRegisters.h" +#include "heapManager.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "IdsLib.h" +#include "IdsNvToCmos.h" +#include "Filecode.h" +#ifdef __IDS_EXTENDED__ + #include IDS_EXT_INCLUDE (IdsInternalLib) +#endif +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_CONTROL_IDSCTRL_FILECODE + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +extern CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[]; + + +/** + * IDS option hooking function dispatcher. + * + * This is the top level interface for IDS option Backend code. + * + * @param[in] IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION + * @param[in,out] DataPtr Data pointer. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + **/ +IDS_STATUS +AmdIdsCtrlDispatcher ( + IN AGESA_IDS_OPTION IdsOption, + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_NV_ITEM *IdsNvPtr; + IDS_STATUS ReturnFlag; + IDS_STATUS ExtendedFlag; + + IdsNvPtr = NULL; + ReturnFlag = IDS_SUCCESS; + + ASSERT (StdHeader != NULL); + if (AmdGetIdsNvTable ((VOID **) &IdsNvPtr, StdHeader) != AGESA_SUCCESS) { + IDS_HDT_CONSOLE (IDS_TRACE , "IDS initialize\n"); + AmdIdsCtrlInitialize (StdHeader); + AmdGetIdsNvTable ((VOID **) &IdsNvPtr, StdHeader); + } + + if (IdsNvPtr != NULL) { + ReturnFlag = IdsParseFeatTbl (IdsOption, IdsContorlFeats, DataPtr, IdsNvPtr, StdHeader); + ExtendedFlag = IDS_EXTENDED_HOOK (IdsOption, DataPtr, IdsNvPtr, StdHeader); + if (ExtendedFlag != IDS_SUCCESS) { + ReturnFlag = IDS_UNSUPPORTED; + } + } + return ReturnFlag; +} + +/** + * Ids code for parse IDS feat table. + * + * Feat table in IDS is used to decribe the IDS support feat and its according family,handler. + * + * @param[in] PIdsFeatTbl point to Ids Feat table + * @param[in] IdsOption IDS indicator value, see @ref AGESA_IDS_OPTION + * @param[in,out] DataPtr Data pointer. + * @param[in] IdsNvPtr Ids Nvram pointer. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + **/ +IDS_STATUS +IdsParseFeatTbl ( + IN AGESA_IDS_OPTION IdsOption, + IN CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[], + IN OUT VOID *DataPtr, + IN IDS_NV_ITEM *IdsNvPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 i; + AGESA_STATUS Tmpsts; + CPU_LOGICAL_ID CpuLogicalId; + BOOLEAN No_Check_Bsp; + CONST IDS_FAMILY_FEAT_STRUCT *PIdsFeat; + IDS_STATUS ReturnFlag; + + ReturnFlag = IDS_SUCCESS; + + for (i = 0; PIdsFeatTbl[i] != NULL; i++) { + PIdsFeat = PIdsFeatTbl[i]; + //Does specified IdsOption reached + if (PIdsFeat->IdsOption == IdsOption) { + //check if bsp only + if (PIdsFeat->IsBsp) { + No_Check_Bsp = 0; + } else { + No_Check_Bsp = 1; + } + if (No_Check_Bsp || IsBsp (StdHeader, &Tmpsts)) { + //Does Family Match required + GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader); + if ((CpuLogicalId.Family) & (PIdsFeat->CpuFamily)) { + //Excute the code for specific Ids Feat + IDS_HDT_CONSOLE (IDS_TRACE, "\tIDS Excute HookPoint [%x] Start\n", IdsOption); + ReturnFlag = PIdsFeat->pf_idsoption (DataPtr, StdHeader, IdsNvPtr); + IDS_HDT_CONSOLE (IDS_TRACE, "\tIDS Excute HookPoint [%x] End\n", IdsOption); + } + } + } + } + return ReturnFlag; +} + +/** + * + * IDS Object Initialization + * + * Initializer routine that will be invoked by the wrapper to initialize + * the data buffer in heap for the IDS object. It includes IDS control + * structure, IDS mem table and IDS GRA table. + * + * @param[in,out] StdHeader The Pointer of IDS Initial Parameter + * + * @retval AGESA_SUCCESS Success to init IDS Object. + * @retval AGESA_ERROR Fail to init IDS Object. + * + **/ + +#ifdef IDS_HEAP_2STAGES + #define IDS_HEAP_PERSIST_EARLY HEAP_LOCAL_CACHE + #define IDS_HEAP_ASSERTION_LATE +#else + #define IDS_HEAP_PERSIST_EARLY HEAP_SYSTEM_MEM + #define IDS_HEAP_ASSERTION_LATE ASSERT(FALSE) +#endif + +AGESA_STATUS +AmdIdsCtrlInitialize ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + AGESA_STATUS IgnoreStatus; + UINT16 NvTblSize; + UINT16 i; + IDS_NV_ITEM IdsNvTable[IDS_NUM_NV_ITEM]; + IDS_NV_ITEM *NvTable; + IDS_NV_ITEM *NvPtr; + IDS_CONTROL_STRUCT *IdsCtrlPtr; + IDS_CALLOUT_STRUCT IdsCalloutData; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MemTblSize; + UINT8 HeapPersist; + + NvTblSize = 0; + MemTblSize = 0; + HeapPersist = HEAP_SYSTEM_MEM; + //Heap status with HEAP_LOCAL_CACHE, will allocate heap with HEAP_LOCAL_CACHE + //with HEAP_TEMP_MEM HEAP_SYSTEM_MEM HEAP_DO_NOT_EXIST_ANYMORE HEAP_S3_RESUME + // with allocate with HEAP_SYSTEM_MEM + if (StdHeader->HeapStatus == HEAP_LOCAL_CACHE) { + MemTblSize = IDS_MAX_MEM_ITEMS; + HeapPersist = IDS_HEAP_PERSIST_EARLY; + } else if ((StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_YET) || (StdHeader->HeapStatus == HEAP_DO_NOT_EXIST_ANYMORE)) { + return AGESA_ERROR; + } else { + IDS_HEAP_ASSERTION_LATE; + } + + IdsCalloutData.IdsNvPtr = IdsNvTable; + IdsCalloutData.StdHeader = *StdHeader; + IdsCalloutData.Reserved = FALSE; +//init IDS_CALLOUT_STRUCT before calling out, give NVITEM default value + for (i = AGESA_IDS_EXT_ID_START; i < IDS_NUM_NV_ITEM; i++) { + IdsNvTable[i].IdsNvId = i; + IdsNvTable[i].IdsNvValue = AGESA_IDS_DFT_VAL; + } + + AGESA_TESTPOINT (TpIfBeforeGetIdsData, StdHeader); + if (AgesaGetIdsData (IDS_CALLOUT_INIT, &IdsCalloutData) == AGESA_SUCCESS) { + IDS_HDT_CONSOLE (IDS_TRACE , "Get IDS options from CBS Done\n"); + NvTable = IdsCalloutData.IdsNvPtr; + NvPtr = NvTable; + while (NvPtr->IdsNvId != AGESA_IDS_NV_END) { + IDS_HDT_CONSOLE (IDS_TRACE , "\tIDS_ID (%X) = %X\n", NvPtr->IdsNvId, NvPtr->IdsNvValue); + NvTblSize ++; + NvPtr ++; + } + NvTblSize ++; + + AllocHeapParams.RequestedBufferSize = sizeof (IDS_CONTROL_STRUCT); + AllocHeapParams.RequestedBufferSize += NvTblSize * sizeof (IDS_NV_ITEM); + AllocHeapParams.RequestedBufferSize += MemTblSize * sizeof (MEM_TABLE_ALIAS); + AllocHeapParams.RequestedBufferSize += IDS_EXTENDED_HEAP_SIZE; + AllocHeapParams.BufferHandle = IDS_CONTROL_HANDLE; + AllocHeapParams.Persist = HeapPersist; + + // + // Allocate data buffer in heap + // + if (HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader) == AGESA_SUCCESS) { + // + // Initialize IDS Date Buffer + // + IdsCtrlPtr = (IDS_CONTROL_STRUCT *) AllocHeapParams.BufferPtr; + IdsCtrlPtr->IgnoreIdsDefault = (BOOLEAN) IdsCalloutData.Reserved; + IdsCtrlPtr->IdsHeapMemSize = AllocHeapParams.RequestedBufferSize; + IdsCtrlPtr->IdsNvTableOffset = sizeof (IDS_CONTROL_STRUCT); + IdsCtrlPtr->IdsMemTableOffset = IdsCtrlPtr->IdsNvTableOffset + NvTblSize * sizeof (IDS_NV_ITEM); + IdsCtrlPtr->IdsExtendOffset = IdsCtrlPtr->IdsMemTableOffset + MemTblSize * sizeof (MEM_TABLE_ALIAS); + + NvPtr = (IDS_NV_ITEM *) (AllocHeapParams.BufferPtr + IdsCtrlPtr->IdsNvTableOffset); + for (i = 0; i < NvTblSize ; i++) { + NvPtr->IdsNvId = NvTable->IdsNvId; + NvPtr->IdsNvValue = NvTable->IdsNvValue; + NvPtr ++; + NvTable ++; + } + status = AGESA_SUCCESS; + } else { + status = AGESA_ERROR; + } + } else { + if (!IsBsp (StdHeader, &IgnoreStatus)) { + status = IDS_AP_GET_NV_FROM_CMOS (StdHeader); + } else { + IDS_HDT_CONSOLE (IDS_TRACE , "Get IDS options from CBS Fail\n"); + status = AGESA_ERROR; + } + } + AGESA_TESTPOINT (TpIfAfterGetIdsData, StdHeader); + + return status; +} +/** + * IDS Backend Function for Target Pstate + * + * + * @param[in,out] DataPtr The Pointer of AMD_CPU_EARLY_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubTargetPstate ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS tarpst; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + IDS_NV_READ_SKIP (tarpst, AGESA_IDS_NV_TARGET_PSTATE, IdsNvPtr, StdHeader) { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) tarpst, (BOOLEAN) FALSE, StdHeader); + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for HdtOut + * + * + * @param[in,out] DataPtr The Pointer of AMD_CPU_EARLY_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubHdtOut ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS idsvalue; + +//set HDTOUT En/Dis + IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_HDTOUT, IdsNvPtr, StdHeader) { +//if HDTOUT set to enable, set the corresponding DR2 flag to 0x99cc + if (idsvalue == 1) { + LibAmdWriteCpuReg (DR2_REG, 0x99cc); + } + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Power down mode + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubPowerDownCtrl ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + MEM_PARAMETER_STRUCT *RefPtr; + IDS_STATUS idsvalue; + MEM_DATA_STRUCT * memdataptr; + + PostParamsPtr = (AMD_POST_PARAMS *)DataPtr; + memdataptr = PostParamsPtr->MemConfig.MemData; + RefPtr = memdataptr->ParameterListPtr; + + IDS_NV_READ_SKIP (idsvalue, AGESA_IDS_NV_MEMORY_POWER_DOWN, IdsNvPtr, StdHeader) { + //if the idsvalue isn't auto do the override + if (idsvalue < (IDS_STATUS)0x2) { + RefPtr->EnablePowerDown = (BOOLEAN) idsvalue; + } + } + return IDS_SUCCESS; +} + +/** + * Backend Function for IDS Option Hook Point: IDS_UCODE + * + * This function is used to disable UCode Installation if IDS Option disables ucode. + * The method is to force the number of total patches to ZERO. + * + * @param[in,out] DataPtr The Pointer of Data to Override. + * @param[in,out] StdHeader The Pointer of AGESA Header. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubUCode ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS status; + IDS_STATUS NvValue; + UINT8 ** pUcodeptr; + + pUcodeptr = (UINT8 **) DataPtr; + status = IDS_SUCCESS; + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_UCODE, IdsNvPtr, StdHeader) { + //Disabled + if (NvValue == 0) { + status = IDS_UNSUPPORTED; + } + } + + IDS_EXTENDED_CODE ( + IdsGetBvmUcodeBase (pUcodeptr, StdHeader); + ) + + return status; +} + +/** + * IDS Backend Function for Post P-State + * + * This function is used to set Post P-State which are CPU specifically. + * + * @param[in,out] DataPtr The Pointer of AMD_CPU_EARLY_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubPostPState ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + AMD_CPU_EARLY_PARAMS *PCpuEarlyParams; + IDS_STATUS idsvalue; + UINT8 curpstatesnum; + + PCpuEarlyParams = (AMD_CPU_EARLY_PARAMS *)DataPtr; + curpstatesnum = IdsGetNumPstatesFamCommon (StdHeader); + idsvalue = AmdIdsNvReader (AGESA_IDS_NV_POSTPSTATE, IdsNvPtr, StdHeader); + + if (idsvalue < (IDS_STATUS) (curpstatesnum + 3)) { + switch (idsvalue) { + case (IDS_STATUS) 0x0: + // Auto + break; + case (IDS_STATUS) 0x1: + // Maximum Performance + PCpuEarlyParams->MemInitPState = 0; + break; + case (IDS_STATUS) 0x2: + // Minimum Performance + PCpuEarlyParams->MemInitPState = curpstatesnum - 1; + break; + default: + PCpuEarlyParams->MemInitPState = (UINT8) (idsvalue - 3); + break; + } + } + return IDS_SUCCESS; +} + + + +/** + * IDS Backend Function for Memory Mode Unganged + * + * This function is used to override Memory Mode Unganged. + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubGangingMode ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS GangingMode; + IDS_NV_READ_SKIP (GangingMode, AGESA_IDS_NV_DCT_GANGING_MODE, IdsNvPtr, StdHeader) { + *((UINT8 *)DataPtr) = (UINT8) GangingMode; + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Power Down Mode + * + * This function is used to override Power Down Mode. + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubPowerDownMode ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS PowerDownMode; + PowerDownMode = AmdIdsNvReader (AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, IdsNvPtr, StdHeader); + if (PowerDownMode < (IDS_STATUS)0x2) { + *((UINT8 *) DataPtr) = (UINT8)PowerDownMode; + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Burst Length32 + * + * This function is used to override Burst Length32. + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubBurstLength32 ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS BurstLength32; + BurstLength32 = AmdIdsNvReader (AGESA_IDS_NV_DRAM_BURST_LENGTH32, IdsNvPtr, StdHeader); + if (BurstLength32 < (IDS_STATUS)0x2) { + *((UINT8 *) DataPtr) = (UINT8)BurstLength32; + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for All Memory Clks Enable + * + * This function is used to override All Memory Clks Enable + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubAllMemClkEn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS AllMemClkEn; + + AllMemClkEn = AmdIdsNvReader (AGESA_IDS_NV_ALL_MEMCLKS , IdsNvPtr, StdHeader); + if (AllMemClkEn < (IDS_STATUS)0x2) { + *((UINT8 *) DataPtr) = (UINT8)AllMemClkEn; + } + + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Dll Shut Down + * + * This function is used to override Dll Shut Down Option + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubDllShutDownSR ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS DllShutDownSR; + IDS_NV_READ_SKIP (DllShutDownSR, AGESA_IDS_NV_DLL_SHUT_DOWN , IdsNvPtr, StdHeader) { + *((UINT8 *) DataPtr) = (UINT8)DllShutDownSR; + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for HT Link Configuration + * + * Provide the nv settings to the HT code in the form of a port override list. + * Create the list on the heap, so the HT code doesn't have to keep asking for it. + * + * @param[out] Data A reference to the HT Port Override List + * @param[in] StdHeader Header for library and services. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + */ +IDS_STATUS +IdsSubHtLinkControl ( + OUT VOID *Data, + IN AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + ALLOCATE_HEAP_PARAMS AllocHeapParams; + HTIDS_PORT_OVERRIDE_LIST *ListReference; + HTIDS_PORT_OVERRIDE_LIST PortOverrideList; + UINT32 HTlinkSocket; + UINT32 HTlinkPort; + UINT32 HTlinkFre; + UINT32 HTlinkWidthIn; + UINT32 HTlinkWidthOut; + + ASSERT (IdsNvPtr != NULL); + ASSERT (Data != NULL); + + ListReference = Data; + *ListReference = NULL; + // Allocated the number of portlist override option sets supported (currently 2) plus 1 more for terminal. + AllocHeapParams.RequestedBufferSize = (sizeof (HTIDS_PORT_OVERRIDE) * 3); + AllocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST) AllocHeapParams.BufferPtr; + LibAmdMemFill (PortOverrideList, HT_LIST_TERMINAL, AllocHeapParams.RequestedBufferSize, StdHeader); + *ListReference = PortOverrideList; + + HTlinkSocket = AmdIdsNvReader (AGESA_IDS_NV_HTLINKSOCKET, IdsNvPtr, StdHeader); + if (HTlinkSocket != IDS_UNSUPPORTED) { + switch (HTlinkSocket) { + case (UINT32) 0xE: + HTlinkSocket = 0xFE; + break; + case (UINT32) 0xF: + HTlinkSocket = 0xFF; + break; + default: + break; + } + PortOverrideList->Socket = (UINT8) HTlinkSocket; + } + HTlinkPort = AmdIdsNvReader (AGESA_IDS_NV_HTLINKPORT, IdsNvPtr, StdHeader); + if (HTlinkPort != IDS_UNSUPPORTED) { + switch (HTlinkPort) { + case (UINT32) 0xC: + HTlinkPort = 0xFC; + break; + case (UINT32) 0xD: + HTlinkPort = 0xFD; + break; + case (UINT32) 0xE: + HTlinkPort = 0xFE; + break; + case (UINT32) 0xF: + HTlinkPort = 0xFF; + break; + default: + break; + } + PortOverrideList->Link = (UINT8) HTlinkPort; + } + HTlinkFre = AmdIdsNvReader (AGESA_IDS_NV_HTLINKFREQ, IdsNvPtr, StdHeader); + if (HTlinkFre != IDS_UNSUPPORTED) { + switch (HTlinkFre) { + case (UINT32) 0x1F: + HTlinkFre = 0xFF; + break; + default: + break; + } + PortOverrideList->Frequency = (UINT8) HTlinkFre; + } + HTlinkWidthIn = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHIN , IdsNvPtr, StdHeader); + if (HTlinkWidthIn != IDS_UNSUPPORTED) { + switch (HTlinkWidthIn) { + case (UINT32) 0x0: + HTlinkWidthIn = 8; + break; + case (UINT32) 0x01: + HTlinkWidthIn = 16; + break; + case (UINT32) 0x04: + HTlinkWidthIn = 2; + break; + case (UINT32) 0x5: + HTlinkWidthIn = 4; + break; + case (UINT32) 0x7: + HTlinkWidthIn = 0xFF; + break; + default: + break; + } + PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn; + } + HTlinkWidthOut = AmdIdsNvReader (AGESA_IDS_NV_HTLINKWIDTHOUT, IdsNvPtr, StdHeader); + if (HTlinkWidthOut != IDS_UNSUPPORTED) { + switch (HTlinkWidthOut) { + case (UINT32) 0x0: + HTlinkWidthOut = 8; + break; + case (UINT32) 0x01: + HTlinkWidthOut = 16; + break; + case (UINT32) 0x04: + HTlinkWidthOut = 2; + break; + case (UINT32) 0x5: + HTlinkWidthOut = 4; + break; + case (UINT32) 0x7: + HTlinkWidthOut = 0xFF; + break; + default: + break; + } + PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut; + } + if (PortOverrideList->Link == 0xFC) { + // force both internal and external links + // switch first PortOverride to force External + HTlinkPort = 0xFE; //Match external + PortOverrideList->Link = (UINT8) HTlinkPort; + + // read all settings from first override list except Link + HTlinkSocket = PortOverrideList->Socket; + HTlinkPort = 0xFD; //Match internal + HTlinkFre = PortOverrideList->Frequency; + HTlinkWidthIn = PortOverrideList->WidthIn; + HTlinkWidthOut = PortOverrideList->WidthOut; + + // copy settings into second override list + PortOverrideList++; + + PortOverrideList->Socket = (UINT8) HTlinkSocket; + PortOverrideList->Link = (UINT8) HTlinkPort; + PortOverrideList->Frequency = (UINT8) HTlinkFre; + PortOverrideList->WidthIn = (UINT8) HTlinkWidthIn; + PortOverrideList->WidthOut = (UINT8) HTlinkWidthOut; + } + } + return IDS_SUCCESS; +} +/** + * IDS Backend Function for Select Platform Power Policy + * + * Parameters: + * @param[in,out] DataPtr The Pointer of PLATFORM_CONFIGURATION. + * @param[in,out] StdHeader AMD standard header config param + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval AGESA_SUCCESS Always Succeeds. + * + */ +IDS_STATUS +IdsSubPowerPolicyOverride ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + PLATFORM_CONFIGURATION *PlatformConfig; + IDS_STATUS NvValue; + + PlatformConfig = (PLATFORM_CONFIGURATION *)DataPtr; + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_POWER_POLICY, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IDS_POWER_POLICY_PERFORMANCE: + PlatformConfig->PlatformProfile.PlatformPowerPolicy = Performance; + break; + case IDS_POWER_POLICY_POWER: + PlatformConfig->PlatformProfile.PlatformPowerPolicy = BatteryLife; + break; + case IDS_POWER_POLICY_AUTO: + break; + default: + ASSERT (FALSE); + break; + } + } + + return IDS_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm new file mode 100644 index 0000000000..9615e853cd --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib32.asm @@ -0,0 +1,362 @@ +;/** +; * @file +; * +; * Ids Assembly library 32bit +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: IDS +; * @e \$Revision: 14305 $ @e \$Date: 2009-05-24 02:20:55 +0800 (Sun, 24 May 2009) $ +; */ +;***************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + +.586p +.model flat +ASSUME FS:NOTHING +.code +public IdsDelay +IdsDelay PROC NEAR C USES EAX EDX +Local targetedx:dword, targeteax:dword + rdtsc +;set target time + add eax,1500000000 + adc edx,0 + mov targetedx,edx + mov targeteax,eax + + rdtsc +;set "Si!=0" skip below loop + .while(1) + .if(si != 0) + jmp delay_exit + .endif + .if(edx > targetedx) + jmp delay_exit + .elseif (edx == targetedx) + .if(eax > targeteax) + jmp delay_exit + .endif + .endif + rdtsc + .endw +delay_exit: + ret +IdsDelay ENDP +;/*++ +; +;Routine Description: +; +; IdsErrorStop -- Function for Assert +; +;Arguments: +; Filecode +; +;Returns: +; +; None +; +;--*/ +public IdsErrorStop +IdsErrorStop PROC NEAR C filecode:dword +local tmpebx:dword,tmpedx:dword + pushad + + mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop +; send debug port 1st, then fire SimNow breakpoint + mov ax, 0deadh + out 0e0h, ax + mov eax, filecode + out 84h, eax + mov eax, 0BACCD00Bh ; Backdoor in SimNow + mov ebx, 2 ; Select breakpoint feature + cpuid + + mov ebx,0dead0000h + mov edx,filecode + ror edx,16 + mov bx,dx + mov dx,0 +;ebx:edx = deadxxxxyyyy0000 xxxx is the filecode yyyy is the line num + mov tmpebx,ebx + mov tmpedx,edx + + xor eax,eax + mov cl,6 + + .while((cl != 0) && (si == 0)) + .if(cl <= 2) + shld eax,edx,8 + shl edx,8 + .else + shld eax,ebx,8 + shl ebx,8 + .endif + + out 80h,eax + call IdsDelay + dec cl + .if(cl == 0) + mov cl,6 + mov ebx,tmpebx + mov edx,tmpedx + .endif + .endw + + popad + xor eax,eax + ret +IdsErrorStop endp + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Stop CPU +; * +; * +; * +; */ +IDS_STOP_HERE MACRO +@@: + jmp short @b +ENDM + +;====================================================================== +; IdsExceptionHandler: Simply performs a jmp $ and IRET. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +PUBLIC _IdsExceptionHandler +PUBLIC _SizeIdtDescriptor +PUBLIC _SizeTotalIdtDescriptors + +; Size of each exception MUST be the same +Exception00: + push eax + mov al, 00h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception01: + push eax + mov al, 01h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception02: + push eax + mov al, 02h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception03: + push eax + mov al, 03h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception04: + push eax + mov al, 04h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception05: + push eax + mov al, 05h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception06: + push eax + mov al, 06h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception07: + push eax + mov al, 07h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception08: + push eax + mov al, 08h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception09: + push eax + mov al, 09h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception10: + push eax + mov al, 10h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception11: + push eax + mov al, 11h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception12: + push eax + mov al, 12h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception13: + push eax + mov al, 13h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception14: + push eax + mov al, 14h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception15: + push eax + mov al, 15h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception16: + push eax + mov al, 16h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception17: + push eax + mov al, 17h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception18: + push eax + mov al, 18h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception19: + push eax + mov al, 19h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception20: + push eax + mov al, 20h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception21: + push eax + mov al, 21h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception22: + push eax + mov al, 22h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception23: + push eax + mov al, 23h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception24: + push eax + mov al, 24h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception25: + push eax + mov al, 25h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception26: + push eax + mov al, 26 + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception27: + push eax + mov al, 27h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception28: + push eax + mov al, 28h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception29: + push eax + mov al, 29h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception30: + push eax + mov al, 30h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception31: + push eax + mov al, 31h + jmp near ptr CommonHandler +CommonHandler: + out 80h, al + pop eax + IDS_STOP_HERE + iretd + +_IdsExceptionHandler dq offset Exception00 +_SizeIdtDescriptor dd (offset Exception01 - offset Exception00) +_SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00) + +END diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm new file mode 100644 index 0000000000..2651494e4f --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsLib64.asm @@ -0,0 +1,369 @@ +;/** +; * @file +; * +; * Ids Assembly library 64bit +; * +; * +; * @xrefitem bom "File Content Label" "Release Content" +; * @e project: AGESA +; * @e sub-project: IDS +; * @e \$Revision: 14126 $ @e \$Date: 2009-05-21 23:02:32 +0800 (Thu, 21 May 2009) $ +; */ +;***************************************************************************** +; +; Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +; +; AMD is granting you permission to use this software (the Materials) +; pursuant to the terms and conditions of your Software License Agreement +; with AMD. This header does *NOT* give you permission to use the Materials +; or any rights under AMD's intellectual property. Your use of any portion +; of these Materials shall constitute your acceptance of those terms and +; conditions. If you do not agree to the terms and conditions of the Software +; License Agreement, please do not use any portion of these Materials. +; +; CONFIDENTIALITY: The Materials and all other information, identified as +; confidential and provided to you by AMD shall be kept confidential in +; accordance with the terms and conditions of the Software License Agreement. +; +; LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION +; PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED +; WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF +; MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, +; OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. +; IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER +; (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS +; INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, +; GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER +; RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF +; THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE +; EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, +; THE ABOVE LIMITATION MAY NOT APPLY TO YOU. +; +; AMD does not assume any responsibility for any errors which may appear in +; the Materials or any other related information provided to you by AMD, or +; result from use of the Materials or any related information. +; +; You agree that you will not reverse engineer or decompile the Materials. +; +; NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any +; further information, software, technical information, know-how, or show-how +; available to you. Additionally, AMD retains the right to modify the +; Materials at any time, without notice, and is not obligated to provide such +; modified Materials to you. +; +; U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with +; "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is +; subject to the restrictions as set forth in FAR 52.227-14 and +; DFAR252.227-7013, et seq., or its successor. Use of the Materials by the +; Government constitutes acknowledgement of AMD's proprietary rights in them. +; +; EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any +; direct product thereof will be exported directly or indirectly, into any +; country prohibited by the United States Export Administration Act and the +; regulations thereunder, without the required authorization from the U.S. +; government nor will be used for any purpose prohibited by the same. +;***************************************************************************** + +.code +IdsDelay PROC + push rax + push rdx + push rbx + xor rax,rax + xor rdx,rdx + rdtsc +;set target time + add eax,1500000000 + adc edx,0 + shl rdx,32 + add rdx,rax + mov rbx,rdx +;rbx store the target +;set "Si!=0" skip below loop +__loop: + cmp si,0 + jnz __loopexit + rdtsc + shl rdx,32 + add rdx,rax + cmp rdx,rbx + jae __loopexit + jmp __loop +__loopexit: + pop rbx + pop rdx + pop rax + ret +IdsDelay ENDP +;/*++ +; +;Routine Description: +; +; IdsErrorStop -- Function for Assert +; +;Arguments: +; Filecode +; +;Returns: +; +; None +; +;--*/ +public IdsErrorStop +IdsErrorStop PROC +;As x64 calling convention RCX is used as input parameters + push rcx + push rbx + push si + push dx + push rbx + + mov si,0 ; Si is used as control flag, "Si!=0" skip postcode loop +; send debug port 1st, then fire SimNow breakpoint + mov ax, 0deadh + out 0e0h, ax + mov eax, ecx + out 84h, eax + mov eax, 0BACCD00Bh ; Backdoor in SimNow + mov ebx, 2 ; Select breakpoint feature + cpuid + + mov rax,0dead00000000h + or rcx,rax +;rcx= 0dead__FILECODE + shl rcx,16 +;rcx= 0dead__FILECODE__0000 + mov rbx,rcx + + xor rax,rax + mov dl,6 + +IdsErrorStopLoop: + cmp dl,0 + jz IdsErrorStopExit + cmp si,0 + jnz IdsErrorStopExit + + shld rax,rcx,8 + shl rcx,8 + out 80h,eax + call IdsDelay + + dec dl + cmp dl,0 + jnz _nextloop + mov dl,6 + mov rcx,rbx +_nextloop: + jmp IdsErrorStopLoop +IdsErrorStopExit: + pop rbx + pop dx + pop si + pop rbx + pop rcx + xor rax,rax + ret +IdsErrorStop endp + +;/*---------------------------------------------------------------------------------------*/ +;/** +; * Stop CPU +; * +; * +; * +; */ +IDS_STOP_HERE MACRO +@@: + jmp short @b +ENDM + +;====================================================================== +; IdsExceptionHandler: Simply performs a jmp $ and IRET. +; +; In: +; None +; +; Out: +; None +; +; Destroyed: +; None +; +;====================================================================== +PUBLIC IdsExceptionHandler +PUBLIC SizeIdtDescriptor +PUBLIC SizeTotalIdtDescriptors + +; Size of each exception MUST be the same +Exception00: + push rax + mov al, 00h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception01: + push rax + mov al, 01h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception02: + push rax + mov al, 02h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception03: + push rax + mov al, 03h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception04: + push rax + mov al, 04h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception05: + push rax + mov al, 05h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception06: + push rax + mov al, 06h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception07: + push rax + mov al, 07h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception08: + push rax + mov al, 08h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception09: + push rax + mov al, 09h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception10: + push rax + mov al, 10h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception11: + push rax + mov al, 11h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception12: + push rax + mov al, 12h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception13: + push rax + mov al, 13h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception14: + push rax + mov al, 14h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception15: + push rax + mov al, 15h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception16: + push rax + mov al, 16h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception17: + push rax + mov al, 17h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception18: + push rax + mov al, 18h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception19: + push rax + mov al, 19h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception20: + push rax + mov al, 20h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception21: + push rax + mov al, 21h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception22: + push rax + mov al, 22h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception23: + push rax + mov al, 23h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception24: + push rax + mov al, 24h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception25: + push rax + mov al, 25h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception26: + push rax + mov al, 26 + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception27: + push rax + mov al, 27h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception28: + push rax + mov al, 28h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception29: + push rax + mov al, 29h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception30: + push rax + mov al, 30h + jmp near ptr CommonHandler +; Size of each exception MUST be the same +Exception31: + push rax + mov al, 31h + jmp near ptr CommonHandler +CommonHandler: + out 80h, al + pop rax + IDS_STOP_HERE + iretq + +IdsExceptionHandler dq offset Exception00 +SizeIdtDescriptor dd (offset Exception01 - offset Exception00) +SizeTotalIdtDescriptors dd (offset CommonHandler - offset Exception00) + +END + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c new file mode 100644 index 0000000000..b9a69b7863 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.c @@ -0,0 +1,442 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug library Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "heapManager.h" +#include "IdsNvToCmos.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern IDS_NV_TO_CMOS gIdsNVToCmos[]; + +/** + * + * Read CMOS + * + * @param[in] IndexPort Index port of access CMOS + * @param[in] DataPort Data port of access CMOS + * @param[in] Index Index of CMOS + * @param[in,out] Value Point to Value + * @param[in,out] StdHeader The Pointer of Standard Header. + * + **/ +VOID +IdsReadCmos ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN UINT16 Index, + IN OUT UINT8 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth8, IndexPort, &Index, StdHeader); + LibAmdIoRead (AccessWidth8, DataPort, Value, StdHeader); +} +/** + * + * Write CMOS + * + * @param[in] IndexPort Index port of access CMOS + * @param[in] DataPort Data port of access CMOS + * @param[in] Index Index of CMOS + * @param[in,out] Value Point to Value + * @param[in,out] StdHeader The Pointer of Standard Header. + * + **/ +VOID +IdsWriteCmos ( + IN UINT16 IndexPort, + IN UINT16 DataPort, + IN UINT16 Index, + IN OUT UINT8 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth8, IndexPort, &Index, StdHeader); + LibAmdIoWrite (AccessWidth8, DataPort, Value, StdHeader); +} +/** + * + * Get IDS CMOS save region in the AGESA Heap. + * + * @param[in,out] IdsCmosRegion The Pointer of IDS CMOS save address in heap. + * @param[in,out] StdHeader The Pointer of Standard Header. + * + * @retval AGESA_SUCCESS Success to get the pointer of NV Table. + * @retval AGESA_ERROR Fail to get the pointer of NV Table. + **/ +AGESA_STATUS +AmdGetIdsCmosSaveRegion ( + IN OUT VOID **IdsCmosRegion, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + LOCATE_HEAP_PTR LocateHeapStructPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + LocateHeapStructPtr.BufferHandle = IDS_NV_TO_CMOS_HANDLE; + LocateHeapStructPtr.BufferPtr = NULL; + status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); + if (status == AGESA_SUCCESS) { + *IdsCmosRegion = LocateHeapStructPtr.BufferPtr; + } else { + //Allocated the heap when can't located + AllocHeapParams.RequestedBufferSize = IDS_CMOS_REGION_END - IDS_CMOS_REGION_START + 1; + AllocHeapParams.BufferHandle = IDS_NV_TO_CMOS_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + status = HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader); + if (status == AGESA_SUCCESS) { + *IdsCmosRegion = AllocHeapParams.BufferPtr; + } + } + return status; +} + + +/** + * IDS Backend Function for save BSP's NV heap to CMOS + * + * + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsCheckCmosValid ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 CmosIndex; + UINT8 TmpValue; + UINT8 Len; + UINT8 Sum; + CmosIndex = IDS_CMOS_REGION_SIGNATURE_OFFSET; + //Validate the Signature + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + if (TmpValue != 'N') { + return IDS_UNSUPPORTED; + } + + CmosIndex++; + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + if (TmpValue != 'V') { + return IDS_UNSUPPORTED; + } + + CmosIndex = IDS_CMOS_REGION_LENGTH_OFFSET; + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &Len, StdHeader); + if (Len > (IDS_CMOS_REGION_END - IDS_CMOS_REGION_START - IDS_NV_TO_CMOS_HEADER_SIZE + 1)) { + return IDS_UNSUPPORTED; + } + Sum = 0; + CmosIndex = IDS_CMOS_REGION_CHECKSUM_OFFSET; + for (; CmosIndex < IDS_CMOS_REGION_DATA_OFFSET + Len; CmosIndex++) { + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + Sum = (UINT8) (Sum + TmpValue); + } + if (Sum != 0) { + return IDS_UNSUPPORTED; + } + return IDS_SUCCESS; +} + +/** + * + * AP get NV from CMOS + * + * If Ap Can't get Nv Data from Callout, Try to Create NV heap via the + * CMOS data area save by BSP previous + + * + * @param[in,out] StdHeader The Pointer of IDS Initial Parameter + * + * @retval AGESA_SUCCESS Success to get the NV from CMOS + * @retval AGESA_ERROR Fail to get + * + **/ +AGESA_STATUS +AmdIdsApGetNvFromCmos ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + IDS_CONTROL_STRUCT *IdsCtrlPtr; + UINT8 CmosIndex; + UINT8 TmpValue; + UINT8 TmpU16Value; + UINT8 k; + UINT16 i; + IDS_NV_ITEM *NvPtr; + UINT8 Len; + status = AGESA_ERROR; + if (IdsCheckCmosValid (StdHeader) == IDS_SUCCESS) { + AllocHeapParams.RequestedBufferSize = sizeof (IDS_CONTROL_STRUCT); + AllocHeapParams.RequestedBufferSize += (IDS_CMOS_REGION_END - IDS_CMOS_REGION_START - IDS_NV_TO_CMOS_HEADER_SIZE + 2) * sizeof (IDS_NV_ITEM) ; + AllocHeapParams.BufferHandle = IDS_CONTROL_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + + // + // Allocate data buffer in heap + // + status = HeapAllocateBuffer (&AllocHeapParams, (AMD_CONFIG_PARAMS *) StdHeader); + if (status == AGESA_SUCCESS) { + IdsCtrlPtr = (IDS_CONTROL_STRUCT *) AllocHeapParams.BufferPtr; + IdsCtrlPtr->IgnoreIdsDefault = TRUE; + IdsCtrlPtr->IdsHeapMemSize = AllocHeapParams.RequestedBufferSize; + IdsCtrlPtr->IdsNvTableOffset = sizeof (IDS_CONTROL_STRUCT); + NvPtr = (IDS_NV_ITEM *) (AllocHeapParams.BufferPtr + IdsCtrlPtr->IdsNvTableOffset); + i = 0; + CmosIndex = IDS_CMOS_REGION_LENGTH_OFFSET; + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &Len, StdHeader); + CmosIndex = IDS_CMOS_REGION_DATA_OFFSET; + while ((gIdsNVToCmos[i].Length != IDS_NV_TO_CMOS_LEN_END) && + (gIdsNVToCmos[i].IDS_NV_ID != IDS_NV_TO_CMOS_ID_END) && + (CmosIndex <= IDS_CMOS_REGION_END) && + (Len-- > 0)) { + if (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_BYTE || gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_WORD) { + TmpU16Value = 0; + for (k = 0; k < gIdsNVToCmos[i].Length; k++, CmosIndex++) { + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + TmpU16Value |= (UINT16)TmpValue << (k * 8); + } + if ((TmpU16Value != IDS_NV_TO_CMOS_BYTE_IGNORED && (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_BYTE)) || + (TmpU16Value != IDS_NV_TO_CMOS_WORD_IGNORED && (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_WORD))) { + NvPtr->IdsNvId = gIdsNVToCmos[i].IDS_NV_ID; + NvPtr->IdsNvValue = TmpU16Value; + NvPtr ++; + } + } + i++; + } + NvPtr->IdsNvId = AGESA_IDS_NV_END; + } + } + return status; +} + +/** + * IDS Backend Function for Restore CMOS + * + * + * @param[in,out] DataPtr NULL + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubRestoreCmos ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + UINT8 *PCmosSave; + UINT8 CmosIndex; + + //Save CMOS to BSP heap + if (AmdGetIdsCmosSaveRegion ((VOID **) &PCmosSave, StdHeader) == AGESA_SUCCESS) { + for (CmosIndex = IDS_CMOS_REGION_START; CmosIndex <= IDS_CMOS_REGION_END; CmosIndex++, PCmosSave++) { + IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, PCmosSave, StdHeader); + } + } + return IDS_SUCCESS; +} +/** + * IDS Backend Function for save BSP's NV heap to CMOS + * + * + * @param[in,out] DataPtr NULL + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +IDS_STATUS +IdsSubSaveBspNvHeapToCmos ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + UINT8 i; + UINT8 k; + UINT8 CmosIndex; + UINT8 TmpValue; + UINT8 Sum; + UINT8 Len; + UINT8 *PCmosSave; + IDS_STATUS IdsNvValue; + + //Save CMOS to BSP heap + if (AmdGetIdsCmosSaveRegion ((VOID **) &PCmosSave, StdHeader) == AGESA_SUCCESS) { + for (CmosIndex = IDS_CMOS_REGION_START; CmosIndex <= IDS_CMOS_REGION_END; CmosIndex++) { + IdsReadCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + *(PCmosSave++) = TmpValue; + } + //The CMOS Region is saved to heap,Now we can save BSP NV to CMOS + i = 0; + CmosIndex = IDS_CMOS_REGION_SIGNATURE_OFFSET; + //CMOS Map + // ********************************************************************************** + // Field | Offset | Description + // ********************************************************************************** + // Signature | 0 | 'NV' specify the IDS Cmos save region + // ********************************************************************************** + // Length | 2 | Actual Length of all save NV, may less than platform + // | | define + // ********************************************************************************** + // CheckSum | 3 | CheckSum of all NV fields exclue Signature & Length + // ********************************************************************************** + // NVSaveRegion | 4 | Nv Save Region + // ********************************************************************************** + // Set Signature 'NV'; + TmpValue = 'N'; + IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + CmosIndex++; + TmpValue = 'V'; + IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + + CmosIndex = IDS_CMOS_REGION_DATA_OFFSET; + Sum = 0; + Len = 0; + while ((gIdsNVToCmos[i].Length != IDS_NV_TO_CMOS_LEN_END) && + (gIdsNVToCmos[i].IDS_NV_ID != IDS_NV_TO_CMOS_ID_END) && + (CmosIndex <= IDS_CMOS_REGION_END)) { + //Get NV Value length + if (gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_BYTE || gIdsNVToCmos[i].Length == IDS_NV_TO_CMOS_LEN_WORD) { + IdsNvValue = AmdIdsNvReader (gIdsNVToCmos[i].IDS_NV_ID, IdsNvPtr, StdHeader); + for (k = 0; k < gIdsNVToCmos[i].Length; k++) { + TmpValue = (UINT8) ((IdsNvValue >> (8 * k)) & 0xFF); + Sum = (UINT8) (Sum + TmpValue); + Len++; + IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + CmosIndex++; + } + } else { + ASSERT (FALSE); + } + i++; + } + CmosIndex = IDS_CMOS_REGION_LENGTH_OFFSET; + IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &Len, StdHeader); + CmosIndex = IDS_CMOS_REGION_CHECKSUM_OFFSET; + TmpValue = (UINT8) (0x100 - Sum); + IdsWriteCmos (IDS_CMOS_INDEX_PORT, IDS_CMOS_DATA_PORT, CmosIndex, &TmpValue, StdHeader); + } + return IDS_SUCCESS; +} + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock = +{ + IDS_FEAT_NV_TO_CMOS, + IDS_BSP_ONLY, + IDS_CPU_Early_Override, + IDS_FAMILY_ALL, + IdsSubSaveBspNvHeapToCmos +}; + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock = +{ + IDS_FEAT_NV_TO_CMOS, + IDS_BSP_ONLY, + IDS_BEFORE_AP_EARLY_HALT, + IDS_FAMILY_ALL, + IdsSubRestoreCmos +}; + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h new file mode 100644 index 0000000000..4e2a41f0d1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Control/IdsNvToCmos.h @@ -0,0 +1,110 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug library Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +#ifndef _IDSNVTOCMOS_H_ +#define _IDSNVTOCMOS_H_ +AGESA_STATUS +AmdGetIdsCmosSaveRegion ( + IN OUT VOID **IdsCmosRegion, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +IdsCheckCmosValid ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AmdIdsApGetNvFromCmos ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +IdsSubRestoreCmos ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubSaveBspNvHeapToCmos ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +#define IDS_NV_TO_CMOS_HEADER_SIZE 4 + +#define IDS_CMOS_REGION_SIGNATURE_OFFSET IDS_CMOS_REGION_START +#define IDS_CMOS_REGION_LENGTH_OFFSET (IDS_CMOS_REGION_START + 2) +#define IDS_CMOS_REGION_CHECKSUM_OFFSET (IDS_CMOS_REGION_START + 3) +#define IDS_CMOS_REGION_DATA_OFFSET (IDS_CMOS_REGION_START + 4) + +#define IDS_NV_TO_CMOS_BYTE_IGNORED 0xFF +#define IDS_NV_TO_CMOS_WORD_IGNORED 0xFFFF +#endif //_IDSNVTOCMOS_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c new file mode 100644 index 0000000000..24d64b3fc0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebug.c @@ -0,0 +1,229 @@ +/** + * @file + * + * AMD Integrated Debug Debug_library Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63552 $ @e \$Date: 2011-12-26 19:46:05 -0600 (Mon, 26 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + /*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "AMD.h" +#include "heapManager.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "IdsDebugPrint.h" +#include "IdsDpHdtout.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_DEBUG_IDSDEBUG_FILECODE + +/*--------------------------------------------------------------------------------------*/ +/** + * IDS back-end code for AGESA_TESTPOINT + * + * @param[in] TestPoint Progress indicator value, see @ref AGESA_TP + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +/*--------------------------------------------------------------------------------------*/ +VOID +IdsAgesaTestPoint ( + IN AGESA_TP TestPoint, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PORT, &TestPoint, StdHeader); +} + +/** + * + * HDT out Function for Assert. + * + * fire a HDTOUT Command of assert to let hdtout script do corresponding things. + * + * @param[in,out] FileCode FileCode of the line + * + **/ +#if 0 +VOID +AmdIdsDebugPrintAssert ( + IN UINT32 FileCode + ) +{ + //TODO:if (AmdIdsHdtOutSupport ()) { + // IdsOutPort (HDTOUT_ASSERT, FileCode, 0); + //} +} +#endif + +/** + * IDS Backend Function for ASSERT + * + * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that + * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display, + * to help distinguish the stop code from a post code loop. + * Additional features may be available if using simulation. + * + * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num. + * + * @retval TRUE No error + **/ +BOOLEAN +IdsAssert ( + IN UINT32 FileCode + ) +{ + UINT32 file; + UINT32 line; + + file = (FileCode >> 16); + line = (FileCode & 0xFFFF); + IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line); + IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL); + IDS_HDT_CONSOLE_ASSERT (FileCode); + //IdsErrorStop (FileCode); + return TRUE; +} + +/** + * IDS Backend Function for Memory timeout control + * + * This function is used to override Memory timeout control. + * + * @param[in,out] DataPtr The Pointer of UINT8. + * + **/ +VOID +IdsMemTimeOut ( + IN OUT VOID *DataPtr + ) +{ +//TODO: UINTN i; +// +// IDS_DEBUG_PRINT **DebugPrintList; +// +// GetDebugPrintList (&DebugPrintList); +// +// for (i = 0; DebugPrintList[i] != NULL; i++) { +// if (DebugPrintList[i]->support ()) { +// // Turn timeout off if any Debug service is on +// *((UINT8 *)DataPtr) = (UINT8)0; +// } +// } +} + +/** + * + * IDS Debug Function to check the sentinels are intact + * + * This function complete heap walk and check to be performed at any time. + * + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE No error + * + **/ +BOOLEAN +AmdHeapIntactCheck ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return TRUE; +} + +/** + * Check for CAR Corruption, the performance monitor number three programed to log the CAR Corruption. + * Check to see if control register is enabled and then check the preformance counter and stop the system by executing + * IDS_ERROR_TRAP if counter has any value other than zero. + * + * @param[in,out] StdHeader The Pointer of Standard Header. + * + * + **/ +VOID +IdsCarCorruptionCheck ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + UINT64 Perf_Msr; + + LibAmdMsrRead (MSR_PERF_CONTROL3, (UINT64*)&Perf_Msr, StdHeader); + if ((Perf_Msr & PERF_RESERVE_BIT_MASK) == PERF_CAR_CORRUPTION_EVENT) { + LibAmdMsrRead (MSR_PERF_COUNTER3, (UINT64*)&Perf_Msr, StdHeader); + if ((Perf_Msr != 0)) { + IDS_ERROR_TRAP; + } + } +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c new file mode 100644 index 0000000000..67ec5974c2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.c @@ -0,0 +1,678 @@ +/** + * @file + * + * AMD Integrated Debug Print Routines + * + * Contains all functions related to IDS Debug Print + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + /*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "IdsDebugPrint.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE + +// +// Also support coding convention rules for var arg macros +// +#define _INT_SIZE_OF(n) ((sizeof (n) + sizeof (UINTN) - 1) &~(sizeof (UINTN) - 1)) +typedef CHAR8 *VA_LIST; +#define VA_START(ap, v) (ap = (VA_LIST) & (v) + _INT_SIZE_OF (v)) +#define VA_ARG(ap, t) (*(t *) ((ap += _INT_SIZE_OF (t)) - _INT_SIZE_OF (t))) +#define VA_END(ap) (ap = (VA_LIST) 0) + +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMA_TYPE 0x08 +#define LONG_TYPE 0x10 +#define PREFIX_ZERO 0x20 + +#define MAX_LOCAL_BUFFER_SIZE 512 +#define BUFFER_OVERFLOW 0xFFFF + +/** + * Check If any print service is enabled. + * + * @param[in] DebugPrintList The Pointer to print service list + * + * @retval TRUE At least on print service is enabled + * @retval FALSE All print service is disabled + * + **/ +STATIC BOOLEAN +AmdIdsDebugPrintCheckSupportAll ( + IN IDS_DEBUG_PRINT **DebugPrintList + ) +{ + BOOLEAN IsSupported; + UINTN i; + IsSupported = FALSE; + for (i = 0; DebugPrintList[i] != NULL; i++) { + if (DebugPrintList[i]->support ()) { + IsSupported = TRUE; + } + } + return IsSupported; +} + +/** + * Parses flag and width information from theFormat string and returns the next index + * into the Format string that needs to be parsed. See file headed for details of Flag and Width. + * + * @param[in] Format Current location in the AvSPrint format string. + * @param[out] Flags Returns flags + * @param[out] Width Returns width of element + * @param[out] Marker Vararg list that may be partially consumed and returned. + * + * @retval Pointer indexed into the Format string for all the information parsed by this routine. + * + **/ +STATIC CHAR8 * +GetFlagsAndWidth ( + IN CHAR8 *Format, + OUT UINTN *Flags, + OUT UINTN *Width, + IN OUT VA_LIST *Marker + ) +{ + UINTN Count; + BOOLEAN Done; + + *Flags = 0; + *Width = 0; + for (Done = FALSE; !Done; ) { + Format++; + + switch (*Format) { + + case '-': /* ' - ' */ + *Flags |= LEFT_JUSTIFY; + break; + case '+': /* ' + ' */ + *Flags |= PREFIX_SIGN; + break; + case ' ': + *Flags |= PREFIX_BLANK; + break; + case ',': /* ', ' */ + *Flags |= COMMA_TYPE; + break; + case 'L': + case 'l': + *Flags |= LONG_TYPE; + break; + + case '*': + *Width = VA_ARG (*Marker, UINTN); + break; + + case '0': + *Flags |= PREFIX_ZERO; + break; + + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + Count = 0; + do { + Count = (Count * 10) + *Format - '0'; + Format++; + } while ((*Format >= '0') && (*Format <= '9')); + Format--; + *Width = Count; + break; + + default: + Done = TRUE; + } + } + return Format; +} + +CHAR8 STATIC HexStr[] = { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; +extern CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[]; + +/** + * + * @param[in,out] Value - Hex value to convert to a string in Buffer. + * + * + */ +VOID +GetDebugPrintList ( + IN OUT CONST IDS_DEBUG_PRINT ***pIdsDebugPrintListPtr + ) +{ + *pIdsDebugPrintListPtr = &IdsDebugPrint[0]; +} + +/** + * + * @param[in,out] Buffer Location to place ascii hex string of Value. + * @param[in] Value - Hex value to convert to a string in Buffer. + * @param[in] Flags - Flags to use in printing Hex string, see file header for details. + * @param[in] Width - Width of hex value. + * @param[in,out] BufferSize - Size of input buffer + * + * @retval Number of characters printed. + **/ + +STATIC UINTN +ValueToHexStr ( + IN OUT CHAR8 *Buffer, + IN UINT64 Value, + IN UINTN Flags, + IN UINTN Width, + IN OUT UINTN *BufferSize + ) +{ + CHAR8 TempBuffer[30]; + CHAR8 *TempStr; + CHAR8 Prefix; + CHAR8 *BufferPtr; + UINTN Count; + UINTN Index; + + TempStr = TempBuffer; + BufferPtr = Buffer; + // + // Count starts at one since we will null terminate. Each iteration of the + // loop picks off one nibble. Oh yea TempStr ends up backwards + // + Count = 0; + do { + *(TempStr++) = HexStr[Value & 0x0f]; + Value >>= 4; + Count++; + } while (Value != 0); + + if (Flags & PREFIX_ZERO) { + Prefix = '0'; + } else if (!(Flags & LEFT_JUSTIFY)) { + Prefix = ' '; + } else { + Prefix = 0x00; + } + for (Index = Count; Index < Width; Index++) { + *(TempStr++) = Prefix; + } + + // + // Reverse temp string into Buffer. + // + while (TempStr != TempBuffer) { + (*BufferSize)--; + if (*BufferSize == 0) { + return BUFFER_OVERFLOW; + } + *(BufferPtr++) = *(--TempStr); + } + + *BufferPtr = 0; + return Index; +} + +/** + * Prints a Value as a decimal number in Buffer + * + * @param[in] Buffer Location to place ascii decimal number string of Value. + * @param[in] Value Decimal value to convert to a string in Buffer. + * @param[in] Flags Flags to use in printing decimal string, see file header for details. + * @param[in,out] BufferSize Size of input buffer + * + * @retval Number of characters printed. + * +**/ + +STATIC UINTN +ValueToString ( + IN OUT CHAR8 *Buffer, + IN INT32 Value, + IN UINTN Flags, + IN OUT UINTN *BufferSize + ) +{ + CHAR8 TempBuffer[30]; + CHAR8 *TempStr; + CHAR8 *BufferPtr; + UINTN Count; + UINTN Remainder; + + ASSERT (*BufferSize); + TempStr = TempBuffer; + BufferPtr = Buffer; + Count = 0; + + if (Value < 0) { + (*BufferSize)--; + if (*BufferSize == 0) { + return BUFFER_OVERFLOW; + } + *(BufferPtr++) = '-'; /* ' - ' */ + Value = - Value; + Count++; + } + + do { + Remainder = Value % 10; + Value /= 10; + *(TempStr++) = (CHAR8)(Remainder + '0'); + Count++; + if ((Flags & COMMA_TYPE) == COMMA_TYPE) { + if (Count % 3 == 0) { + *(TempStr++) = ','; + } + } + } while (Value != 0); + + // + // Reverse temp string into Buffer. + // + while (TempStr != TempBuffer) { + (*BufferSize)--; + if (*BufferSize == 0) { + return BUFFER_OVERFLOW; + } + *(BufferPtr++) = *(--TempStr); + } + + *BufferPtr = 0; + return Count; +} + +/** + * Worker function for print string to buffer + * + * @param[in] Flag - filter flag + * @param[in] *Format - format string + * @param[in] Marker - Variable parameter + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[out] OutputStringLen - output string length, include '\0' at the end + * + * @retval IDS_DEBUG_PRINT_SUCCESS succeed + * @retval IDS_DEBUG_PRINT_BUFFER_OVERFLOW input buffer overflow +**/ +STATIC IDS_DEBUG_PRINT_STATUS +AmdIdsDebugPrintWorker ( + IN CONST CHAR8 *Format, + IN VA_LIST Marker, + IN CHAR8 *Buffer, + IN UINTN BufferSize, + OUT UINTN *OutputStringLen + ) +{ + UINTN Index; + UINTN Length; + UINTN Flags; + UINTN Width; + UINT64 Value; + CHAR8 *AsciiStr; + + //Init the default Value + Index = 0; + // + // Process format string + // + for (; (*Format != '\0') && (BufferSize > 0); Format++) { + if (*Format != '%') { + Buffer[Index++] = *Format; + BufferSize--; + } else { + Format = GetFlagsAndWidth ((CHAR8 *)Format, &Flags, &Width, &Marker); + switch (*Format) { + case 'X': + Flags |= PREFIX_ZERO; + Width = sizeof (UINT64) * 2; + // + // break skipped on purpose + // + case 'x': + if ((Flags & LONG_TYPE) == LONG_TYPE) { + Value = VA_ARG (Marker, UINT64); + } else { + Value = VA_ARG (Marker, UINTN); + } + Length = ValueToHexStr (&Buffer[Index], Value, Flags, Width, &BufferSize); + if (Length != BUFFER_OVERFLOW) { + Index += Length; + } else { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + break; + + case 'd': + Value = (UINTN)VA_ARG (Marker, UINT32); + Length = ValueToString (&Buffer[Index], (UINT32)Value, Flags, &BufferSize); + if (Length != BUFFER_OVERFLOW) { + Index += Length; + } else { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + + break; + + case 's': + case 'S': + AsciiStr = (CHAR8 *)VA_ARG (Marker, CHAR8 *); + while (*AsciiStr != '\0') { + BufferSize--; + if (BufferSize == 0) { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + Buffer[Index++] = *AsciiStr++; + } + break; + + case 'c': + BufferSize--; + if (BufferSize == 0) { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + Buffer[Index++] = (CHAR8)VA_ARG (Marker, UINTN); + break; + + case 'v': + ASSERT (FALSE); // %v is no longer supported + break; + + case '%': + BufferSize--; + if (BufferSize == 0) { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + Buffer[Index++] = *Format; + break; + + default: + // + // if the type is unknown print it to the screen + // + BufferSize--; + if (BufferSize == 0) { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + Buffer[Index++] = '%'; + + BufferSize--; + if (BufferSize == 0) { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + Buffer[Index++] = *Format; + break; + } + } + } + if (BufferSize == 0) { + return IDS_DEBUG_PRINT_BUFFER_OVERFLOW; + } + //Mark the end of word + Buffer[Index] = 0; + *OutputStringLen = Index; + return IDS_DEBUG_PRINT_SUCCESS; +} + + +/** + * Insert Overflow warning to the tail of output + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * +**/ +STATIC VOID +InsertOverflowWarningMessage ( + IN CHAR8 *Buffer, + IN UINTN BufferSize + ) +{ + CHAR8 *Destination; + CHAR8 WarningString[] = "\n#BUFFER OVERFLOW#\n"; + AMD_CONFIG_PARAMS StdHeader; + + Destination = Buffer + BufferSize - sizeof (WarningString); + LibAmdMemCopy (Destination, WarningString, sizeof (WarningString), &StdHeader); +} + +/** + * Process debug string + * + * @param[in] Flag - filter flag + * @param[in] *Format - format string + * @param[in] Marker - Variable parameter + * +**/ +STATIC VOID +AmdIdsDebugPrintProcess ( + IN UINT64 Flag, + IN CONST CHAR8 *Format, + IN VA_LIST Marker + ) +{ + UINT64 Filter; + CHAR8 LocalBuffer[MAX_LOCAL_BUFFER_SIZE]; + UINTN OutPutStringLen; + IDS_DEBUG_PRINT **DebugPrintList; + IDS_DEBUG_PRINT_PRIVATE_DATA debugPrintPrivate; + UINT8 i; + + + GetDebugPrintList ((CONST IDS_DEBUG_PRINT ***)&DebugPrintList); + if (AmdIdsDebugPrintCheckSupportAll (DebugPrintList)) { + if (AmdIdsDebugPrintWorker (Format, Marker, &LocalBuffer[0], sizeof (LocalBuffer), &OutPutStringLen) == IDS_DEBUG_PRINT_BUFFER_OVERFLOW) { + InsertOverflowWarningMessage (&LocalBuffer[0], sizeof (LocalBuffer)); + OutPutStringLen = sizeof (LocalBuffer); + } + + //init input + debugPrintPrivate.saveContext = FALSE; + + for (i = 0; DebugPrintList[i] != NULL; i++) { + if (DebugPrintList[i]->support ()) { + Filter = IDS_DEBUG_PRINT_MASK; + //Get Customize filter (Option) + DebugPrintList[i]->customfilter (&Filter); + if (Flag & Filter) { + //Init Private Date (Option) + DebugPrintList[i]->InitPrivateData (Flag, &debugPrintPrivate); + //Print Physical Layer + DebugPrintList[i]->print (&LocalBuffer[0], OutPutStringLen, &debugPrintPrivate); + } + } + } + } +} + +/** + * Prints string to debug host like printf in C + * + * @param[in] Flag - filter flag + * @param[in] *Format - format string + * @param[in] ... Variable parameter + * +**/ +VOID +AmdIdsDebugPrint ( + IN UINT64 Flag, + IN CONST CHAR8 *Format, + IN ... + ) +{ + VA_LIST Marker; + VA_START (Marker, Format); //init marker to 1st dynamic parameters. + AmdIdsDebugPrintProcess (Flag, Format, Marker); + VA_END (Marker); +} + +/** + * Prints memory debug strings + * + * @param[in] *Format - format string + * @param[in] ... Variable parameter + * +**/ +VOID +AmdIdsDebugPrintMem ( + IN CHAR8 *Format, + IN ... + ) +{ + VA_LIST Marker; + VA_START (Marker, Format); //init marker to 1st dynamic parameters. + AmdIdsDebugPrintProcess (MEM_FLOW, Format, Marker); + VA_END (Marker); +} + +/** + * Prints CPU debug strings + * + * @param[in] *Format - format string + * @param[in] ... Variable parameter + * +**/ +VOID +AmdIdsDebugPrintCpu ( + IN CHAR8 *Format, + IN ... + ) +{ + VA_LIST Marker; + VA_START (Marker, Format); //init marker to 1st dynamic parameters. + AmdIdsDebugPrintProcess (CPU_TRACE, Format, Marker); + VA_END (Marker); +} + + +/** + * Prints HT debug strings + * + * @param[in] *Format - format string + * @param[in] ... Variable parameter + * +**/ +VOID +AmdIdsDebugPrintHt ( + IN CHAR8 *Format, + IN ... + ) +{ + VA_LIST Marker; + VA_START (Marker, Format); //init marker to 1st dynamic parameters. + AmdIdsDebugPrintProcess (HT_TRACE, Format, Marker); + VA_END (Marker); +} + + +/** + * Prints GNB debug strings + * + * @param[in] *Format - format string + * @param[in] ... Variable parameter + * +**/ +VOID +AmdIdsDebugPrintGnb ( + IN CHAR8 *Format, + IN ... + ) +{ + VA_LIST Marker; + VA_START (Marker, Format); //init marker to 1st dynamic parameters. + AmdIdsDebugPrintProcess (GNB_TRACE, Format, Marker); + VA_END (Marker); +} + +/** + * Prints debug strings in any condition + * + * @param[in] *Format - format string + * @param[in] ... Variable parameter + * +**/ +VOID +AmdIdsDebugPrintAll ( + IN CHAR8 *Format, + IN ... + ) +{ + VA_LIST Marker; + VA_START (Marker, Format); //init marker to 1st dynamic parameters. + AmdIdsDebugPrintProcess (TRACE_MASK_ALL, Format, Marker); + VA_END (Marker); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h new file mode 100644 index 0000000000..5061426cd0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDebugPrint.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Print Routines + * + * Contains all functions related to IDS Debug Print + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _IDS_DEBUGPRINT_H_ +#define _IDS_DEBUGPRINT_H_ + +/// return status for debug print +typedef enum { + IDS_DEBUG_PRINT_SUCCESS = 0, ///< success + IDS_DEBUG_PRINT_BUFFER_OVERFLOW, ///< Bufer overflow +} IDS_DEBUG_PRINT_STATUS; + +/// Private datas for debug print +typedef struct _IDS_DEBUG_PRINT_PRIVATE_DATA { + BOOLEAN saveContext; /// save context +} IDS_DEBUG_PRINT_PRIVATE_DATA; + +typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_SUPPORT) (VOID); +typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_FILTER) (UINT64 *Filter); +typedef VOID (*PF_IDS_DEBUG_PRINT_PRINT) (CHAR8 *Buffer, UINTN BufferSize, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate); +typedef VOID (*PF_IDS_DEBUG_INIT_PRIVATE_DATA) (UINT64 flag, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate); + +/// Debug print Hw layer service class +typedef struct _IDS_DEBUG_PRINT { + PF_IDS_DEBUG_PRINT_SUPPORT support; ///Check if support + PF_IDS_DEBUG_PRINT_FILTER customfilter; ///Get if any customize filters + PF_IDS_DEBUG_INIT_PRIVATE_DATA InitPrivateData; ///Init private data + PF_IDS_DEBUG_PRINT_PRINT print; ///Print data to Hw layer +} IDS_DEBUG_PRINT; + + +VOID +GetDebugPrintList ( + IN OUT CONST IDS_DEBUG_PRINT ***pIdsDebugPrintListPtr + ); + + +#endif //_IDS_DEBUGPRINT_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c new file mode 100644 index 0000000000..bb180cefb9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.c @@ -0,0 +1,778 @@ +/** + * @file + * + * AMD Integrated Debug Debug_library Routines + * + * Contains all functions related to HDTOUT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63688 $ @e \$Date: 2012-01-03 21:18:53 -0600 (Tue, 03 Jan 2012) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + /*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "AMD.h" +#include "heapManager.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "IdsDebugPrint.h" +#include "IdsDpHdtout.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE + +/** + * Check if String contain the substring + * + * @param[in] String Pointer of string. + * @param[in] Substr Pointer of sub string. + * + * @retval TRUE S2 is substring of S1 + * @retval FALSE S2 isn't substring of S1 + * +**/ +BOOLEAN +AmdIdsSubStr ( + IN CHAR8 *String, + IN CHAR8 *Substr + ) +{ + UINT16 i; + UINT16 j; + + for (i = 0; String[i] != 0 ; i++) { + for (j = 0; (Substr[j] != 0) && (Substr[j] == String[i + j]); j++) { + } + if (Substr[j] == 0) { + return TRUE; + } + } + + return FALSE; +} + +/** + * Determine whether IDS console is enabled. + * + * @param[in,out] pHdtoutHeader Address of hdtout header pointer + * @param[in,out] StdHeader The Pointer of AGESA Header + * + * @retval TRUE pHdtoutHeader Non zero + * @retval FALSE pHdtoutHeader is NULL + * + **/ +BOOLEAN +AmdIdsHdtoutGetHeader ( + IN OUT HDTOUT_HEADER **pHdtoutHeaderPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Dr3Reg; + HDTOUT_HEADER *HdtoutHeaderPtr; + LibAmdReadCpuReg (DR3_REG, &Dr3Reg); + HdtoutHeaderPtr = (HDTOUT_HEADER *) (UINTN) Dr3Reg; + if ((HdtoutHeaderPtr != NULL) && (HdtoutHeaderPtr->Signature == HDTOUT_HEADER_SIGNATURE)) { + *pHdtoutHeaderPtr = HdtoutHeaderPtr; + return TRUE; + } else { + return FALSE; + } +} +/** + * Determine whether IDS console is enabled. + * + * @param[in,out] IdsConsole The Pointer of Ids console data + * + * @retval TRUE Ids console is enabled. + * @retval FALSE Ids console is disabled. + * + **/ +BOOLEAN +AmdIdsHdtOutSupport ( + VOID + ) +{ + BOOLEAN Result; + UINT32 DR2reg; + + Result = FALSE; + + LibAmdReadCpuReg (DR2_REG, &DR2reg); + if (DR2reg == 0x99CC) { + Result = TRUE; + } + + return Result; +} + +/** + * Get HDTOUT customize Filter + * + * @param[in,out] Filter Filter do be filled + * + * @retval TRUE Alway return true, for HDTOUT has its own filter mechanism + * + **/ +BOOLEAN +AmdIdsHdtOutGetFilter ( + IN OUT UINT64 *Filter + ) +{ + HDTOUT_HEADER *HdtoutHeaderPtr; + + if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, NULL) == TRUE) { + *Filter = HdtoutHeaderPtr->ConsoleFilter; + } + return TRUE; +} + +/** + * + * Initial register setting used for HDT out Function. + * + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutRegisterRestore ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CR4reg; + UINT64 SMsr; + + SMsr &= ~BIT0; + + LibAmdWriteCpuReg (DR2_REG, 0); + LibAmdWriteCpuReg (DR3_REG, 0); + LibAmdWriteCpuReg (DR7_REG, 0); + + LibAmdReadCpuReg (CR4_REG, &CR4reg); + LibAmdWriteCpuReg (CR4_REG, CR4reg & (~BIT3)); + +} + +/** + * + * Restore register setting used for HDT out Function. + * + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutRegisterInit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CR4reg; + UINT64 SMsr; + + SMsr |= 1; + + LibAmdWriteCpuReg (DR2_REG, 0x99CC); + + LibAmdWriteCpuReg (DR7_REG, 0x02000420); + + LibAmdReadCpuReg (CR4_REG, &CR4reg); + LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3)); +} + +/** + * + * Initial function for HDT out Function. + * + * Init required Debug register & heap, and will also fire a HDTOUT + * Command to let hdtout script do corresponding things. + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutInit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + ALLOCATE_HEAP_PARAMS AllocHeapParams; + HDTOUT_HEADER HdtoutHeader; + UINT8 Persist; + AGESA_STATUS IgnoreSts; + HDTOUT_HEADER *pHdtoutHeader; + + IDS_FUNCLIST_EXTERN (); + if (AmdIdsHdtOutSupport ()) { + AmdIdsHdtOutRegisterInit (StdHeader); + // Initialize HDTOUT Header + HdtoutHeader.Signature = HDTOUT_HEADER_SIGNATURE; + HdtoutHeader.Version = HDTOUT_VERSION; + HdtoutHeader.BufferSize = HDTOUT_DEFAULT_BUFFER_SIZE; + HdtoutHeader.DataIndex = 0; + HdtoutHeader.PrintCtrl = HDTOUT_PRINTCTRL_ON; + HdtoutHeader.NumBreakpointUnit = 0; + HdtoutHeader.FuncListAddr = (UINT32) (UINT64) IDS_FUNCLIST_ADDR; + HdtoutHeader.StatusStr[0] = 0; + HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON; + HdtoutHeader.EnableMask = 0; + HdtoutHeader.ConsoleFilter = IDS_DEBUG_PRINT_MASK; + + // Trigger HDTOUT breakpoint to get inputs from script + IdsOutPort (HDTOUT_INIT, (UINT32) (UINT64) &HdtoutHeader, 0); + // Disable AP HDTOUT if set BspOnlyFlag + if (HdtoutHeader.BspOnlyFlag == HDTOUT_BSP_ONLY) { + if (!IsBsp (StdHeader, &IgnoreSts)) { + AmdIdsHdtOutRegisterRestore (StdHeader); + return; + } + } + // Convert legacy EnableMask to new ConsoleFilter + HdtoutHeader.ConsoleFilter |= HdtoutHeader.EnableMask; + + // Disable the buffer if the size is not large enough + if (HdtoutHeader.BufferSize < 128) { + HdtoutHeader.BufferSize = 0; + HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_OFF; + } else { + HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON; + } + + // Check if Hdtout header have been initialed, if so it must 2nd time come here + if (AmdIdsHdtoutGetHeader (&pHdtoutHeader, StdHeader)) { + Persist = HEAP_SYSTEM_MEM; + } else { + Persist = HEAP_LOCAL_CACHE; + } + + // Allocate heap + do { + AllocHeapParams.RequestedBufferSize = HdtoutHeader.BufferSize + sizeof (HdtoutHeader) - 2; + AllocHeapParams.BufferHandle = IDS_HDT_OUT_BUFFER_HANDLE; + AllocHeapParams.Persist = Persist; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + break; + } else { + IdsOutPort (HDTOUT_ERROR, HDTOUT_ERROR_HEAP_ALLOCATION, AllocHeapParams.RequestedBufferSize); + HdtoutHeader.BufferSize -= 256; + } + } while ((HdtoutHeader.BufferSize & 0x8000) == 0); + // If the buffer have been successfully allocated? + if ((HdtoutHeader.BufferSize & 0x8000) == 0) { + LibAmdWriteCpuReg (DR3_REG, (UINT32) (UINT64) AllocHeapParams.BufferPtr); + LibAmdMemCopy (AllocHeapParams.BufferPtr, &HdtoutHeader, sizeof (HdtoutHeader) - 2, StdHeader); + } else { + /// Clear DR3_REG + IdsOutPort (HDTOUT_ERROR, HDTOUT_ERROR_HEAP_AllOCATE_FAIL, IDS_DEBUG_PRINT_MASK); + LibAmdWriteCpuReg (DR3_REG, 0); + } + } +} + +/** + * + * Flush all HDTOUT buffer data before HOB transfer + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutBufferFlush ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + HDTOUT_HEADER *HdtoutHeaderPtr ; + + if (AmdIdsHdtOutSupport ()) { + if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) { + if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) && + (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) { + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINT64) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); + HdtoutHeaderPtr->DataIndex = 0; + } + } + } +} + +/** + * Exit function for HDT out Function for each cores + * + * @param[in] Ignored no used + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval AGESA_SUCCESS Success + * @retval AGESA_ERROR meet some error + * + **/ +AGESA_STATUS +AmdIdsHdtOutExitCoreTask ( + IN VOID *Ignored, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + HDTOUT_HEADER *HdtoutHeaderPtr; + + if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, StdHeader)) { + if ((HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) && + (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON)) { + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINT64) HdtoutHeaderPtr->Data, HdtoutHeaderPtr->DataIndex); + } + } + IdsOutPort (HDTOUT_EXIT, (UINT32) (UINT64) HdtoutHeaderPtr, 0); + + AmdIdsHdtOutRegisterRestore (StdHeader); + + return AGESA_SUCCESS; +} +/** + * + * Exit function for HDT out Function. + * + * Restore debug register and Deallocate heap, and will also fire a HDTOUT + * Command to let hdtout script do corresponding things. + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutExit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDSAPLATETASK IdsApLateTask; + if (AmdIdsHdtOutSupport ()) { + IdsApLateTask.ApTask = (PF_IDS_AP_TASK) AmdIdsHdtOutExitCoreTask; + IdsApLateTask.ApTaskPara = NULL; + IdsAgesaRunFcnOnAllCoresLate (&IdsApLateTask, StdHeader); + HeapDeallocateBuffer (IDS_HDT_OUT_BUFFER_HANDLE, StdHeader); + } +} + +/** + * + * Exit function for HDT out Function of S3 Resume + * + * Restore debug register and Deallocate heap, and will also fire a HDTOUT + * Command to let hdtout script do corresponding things. + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutS3Exit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + + if (AmdIdsHdtOutSupport ()) { + //Ap debug print exit have been done at the end of AmdInitResume, so we only BSP at here + AmdIdsHdtOutExitCoreTask (NULL, StdHeader); + if (IsBsp (StdHeader, &AgesaStatus)) { + HeapDeallocateBuffer (IDS_HDT_OUT_BUFFER_HANDLE, StdHeader); + } + } +} +/** + * + * Exit function for HDT out Function of S3 Resume + * + * Restore debug register and Deallocate heap, and will also fire a HDTOUT + * Command to let hdtout script do corresponding things. + * + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +VOID +AmdIdsHdtOutS3ApExit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK TaskPtr; + UINT32 Ignored; + UINT32 BscSocket; + UINT32 BscCoreNum; + UINT32 Core; + UINT32 Socket; + UINT32 NumberOfSockets; + UINT32 NumberOfCores; + AGESA_STATUS IgnoredSts; + + if (AmdIdsHdtOutSupport ()) { + // run code on all APs except BSP + TaskPtr.FuncAddress.PfApTaskI = (PF_AP_TASK_I)AmdIdsHdtOutExitCoreTask; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.DataTransfer.DataPtr = NULL; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + NumberOfSockets = GetPlatformNumberOfSockets (); + IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts); + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (IsProcessorPresent (Socket, StdHeader)) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != BscSocket) || (Core != BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader); + } + } + } + } + } + } +} + +/** + * Print formated string with accerate buffer + * Flow out only when buffer will full + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[in] HdtoutHeaderPtr - Point to Hdtout Header + * +**/ +VOID +AmdIdsHdtOutPrintWithBuffer ( + IN CHAR8 *Buffer, + IN UINTN BufferSize, + IN HDTOUT_HEADER *HdtoutHeaderPtr + ) +{ + if ((HdtoutHeaderPtr == NULL) || (Buffer == NULL)) { + ASSERT (FALSE); + return; + } + + while (BufferSize--) { + if (HdtoutHeaderPtr->DataIndex >= HdtoutHeaderPtr->BufferSize) { + //Flow out current buffer, and clear the index + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) &HdtoutHeaderPtr->Data[0], HdtoutHeaderPtr->BufferSize); + HdtoutHeaderPtr->DataIndex = 0; + } + HdtoutHeaderPtr->Data[HdtoutHeaderPtr->DataIndex++] = *(Buffer++); + } +} +/** + * Save HDTOUT context, use for break point function + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[in] HdtoutHeaderPtr - Point to Hdtout Header + * +**/ +VOID +AmdIdsHdtOutSaveContext ( + IN CHAR8 *Buffer, + IN UINTN BufferSize, + IN HDTOUT_HEADER *HdtoutHeaderPtr + ) +{ + UINTN i; + UINTN j; + UINTN ArrayIndex; + UINTN unusedPrefix; + UINTN ArrayLength; + BOOLEAN SaveStatus; + + ArrayLength = 0; + + // Look for the start of the first ASCII + for (i = 0; i < BufferSize - 1; i++) { + if ((Buffer[i] > 32) && (Buffer[i] < 127)) { + break; + } + } + + unusedPrefix = i; + //ASSERT if no "\n" in status string + ASSERT (AmdIdsSubStr (&Buffer[i], "\n")); + + if (i < (BufferSize - 1)) { + // Match the first word in StatusStr + SaveStatus = FALSE; + for (j = 0; !SaveStatus && (HdtoutHeaderPtr->StatusStr[j] != 0); j++) { + for (; (Buffer[i] == HdtoutHeaderPtr->StatusStr[j]) && (i < BufferSize); i++, j++) { + ArrayLength++; + if (Buffer[i] == ' ') { + ArrayIndex = j; + for (; HdtoutHeaderPtr->StatusStr[j] != '\n'; j++) { + ArrayLength++; + } + // Remove old entry if it's size does not fit + if (ArrayLength != ((UINT32) BufferSize - unusedPrefix)) { + for (++j; HdtoutHeaderPtr->StatusStr[j] != 0; j++) { + HdtoutHeaderPtr->StatusStr[j - ArrayLength] = HdtoutHeaderPtr->StatusStr[j]; + } + j = j - ArrayLength - 1; + i = unusedPrefix; + // Mark the end of string + HdtoutHeaderPtr->StatusStr[j + BufferSize - unusedPrefix + 1] = 0; + } else { + j = ArrayIndex - 1; + } + + // Word match, exit for saving + SaveStatus = TRUE; + break; + } + } + } + + // Copy string to StatusStr + if ((HdtoutHeaderPtr->StatusStr[j] == 0) || SaveStatus) { + for (; i < BufferSize; j++, i++) { + HdtoutHeaderPtr->StatusStr[j] = Buffer[i]; + } + } + + if (!SaveStatus) { + // Mark the end of string if not done so + HdtoutHeaderPtr->StatusStr[j] = 0; + } + } +} + +BOOLEAN +AmdIdsHdtOutBreakPointUnit ( + IN OUT BREAKPOINT_UNIT **pBpunitptr, + IN OUT UINT32 *numBp, + IN HDTOUT_HEADER *HdtoutHeaderPtr, + IN CHAR8 *Buffer + ) +{ + BOOLEAN isMatched; + CHAR8 *PCmpStr; + CHAR8 *Pbpstr; + BREAKPOINT_UNIT *pBpunit; + + pBpunit = *pBpunitptr; + if ((pBpunit == NULL) || + (numBp == NULL) || + (HdtoutHeaderPtr == NULL) || + (*numBp == 0)) { + ASSERT (FALSE); + return FALSE; + } + //Get to be compared string + if (pBpunit->BpFlag == IDS_HDTOUT_BPFLAG_FORMAT_STR) { + PCmpStr = Buffer; + } else { + PCmpStr = HdtoutHeaderPtr->StatusStr; + } + //Get BreakPoint string + Pbpstr = HdtoutHeaderPtr->BreakpointList + pBpunit->BpStrOffset; + isMatched = AmdIdsSubStr (PCmpStr, Pbpstr); + //Point to next one, and decrease the numbp + *pBpunitptr = ++pBpunit; + (*numBp)--; + return isMatched; +} +/** + * Process HDTOUT breakpoint + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[in] HdtoutHeaderPtr - Point to Hdtout Header + * +**/ +VOID +AmdIdsHdtOutBreakPoint ( + IN CHAR8 *Buffer, + IN UINTN BufferSize, + IN HDTOUT_HEADER *HdtoutHeaderPtr + ) +{ + UINT32 numBp; + BREAKPOINT_UNIT *Pbpunit; + BOOLEAN isMatched; + UINT32 i; + Pbpunit = (BREAKPOINT_UNIT *) &HdtoutHeaderPtr->BreakpointList[0]; + numBp = HdtoutHeaderPtr->NumBreakpointUnit; + + for (;;) { + if (Pbpunit->AndFlag == IDS_HDTOUT_BP_AND_ON) { + isMatched = TRUE; + do { + isMatched &= AmdIdsHdtOutBreakPointUnit (&Pbpunit, &numBp, HdtoutHeaderPtr, Buffer); + } while ((Pbpunit->AndFlag == IDS_HDTOUT_BP_AND_ON) && + (isMatched == TRUE) && + (numBp > 0)); + //Next one is IDS_HDTOUT_BP_AND_OFF + if (numBp > 0) { + if (isMatched == TRUE) { + isMatched &= AmdIdsHdtOutBreakPointUnit (&Pbpunit, &numBp, HdtoutHeaderPtr, Buffer); + } else { + Pbpunit++; + numBp--; + } + } + } else { + isMatched = AmdIdsHdtOutBreakPointUnit (&Pbpunit, &numBp, HdtoutHeaderPtr, Buffer); + } + if ((isMatched == TRUE) || (numBp == 0)) { + break; + } + } + //Do action + if (isMatched) { +// AmdIdsSerialPrint (Buffer, BufferSize, NULL); + Pbpunit--; + switch (Pbpunit->Action) { + case HDTOUT_BP_ACTION_HALT: + i = (UINT32) (Pbpunit - ((BREAKPOINT_UNIT *) &HdtoutHeaderPtr->BreakpointList[0])); + IdsOutPort (HDTOUT_BREAKPOINT, (UINT32) (UINTN) Buffer, ( i << 16) | (UINT32) BufferSize); + break; + case HDTOUT_BP_ACTION_PRINTON: + if (HdtoutHeaderPtr->PrintCtrl != 1) { + HdtoutHeaderPtr->PrintCtrl = 1; + if (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON) { + AmdIdsHdtOutPrintWithBuffer (Buffer, BufferSize, HdtoutHeaderPtr); + } else { + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32) BufferSize); + } + } + break; + case HDTOUT_BP_ACTION_PRINTOFF: + if (HdtoutHeaderPtr->PrintCtrl != 0) { + HdtoutHeaderPtr->PrintCtrl = 0; + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32)BufferSize); + } + break; + default: + ASSERT (FALSE); + } + } +} + + +/** + * Print formated string to HDTOUT + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[in] debugPrintPrivate - Option + * +**/ +VOID +AmdIdsHdtOutPrint ( + IN CHAR8 *Buffer, + IN UINTN BufferSize, + IN IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate + ) +{ + HDTOUT_HEADER *HdtoutHeaderPtr; + if (AmdIdsHdtoutGetHeader (&HdtoutHeaderPtr, NULL)) { + //Print Function + if (HdtoutHeaderPtr->PrintCtrl == HDTOUT_PRINTCTRL_ON) { + if (HdtoutHeaderPtr->OutBufferMode == HDTOUT_BUFFER_MODE_ON) { + AmdIdsHdtOutPrintWithBuffer (Buffer, BufferSize, HdtoutHeaderPtr); + } else { + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32) BufferSize); + } + } + //Check BreakPoint + if (HdtoutHeaderPtr->NumBreakpointUnit) { + AmdIdsHdtOutBreakPoint (Buffer, BufferSize, HdtoutHeaderPtr); + if (debugPrintPrivate->saveContext) { + AmdIdsHdtOutSaveContext (Buffer, BufferSize, HdtoutHeaderPtr); + debugPrintPrivate->saveContext = FALSE; + } + } + } else { + //No HDTOUT header found print directly without buffer + IdsOutPort (HDTOUT_PRINT, (UINT32) (UINTN) Buffer, (UINT32) BufferSize); + } +} + +/** + * Init local private data for HDTOUT + * + * @param[in] Flag - filter flag + * @param[in] debugPrintPrivate - Point to debugPrintPrivate + * +**/ +VOID +AmdIdsHdtOutInitPrivateData ( + IN UINT64 Flag, + IN IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate + ) +{ + if (Flag == MEM_STATUS) { + debugPrintPrivate->saveContext = TRUE; + } +} + +CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintHdtoutInstance = +{ + AmdIdsHdtOutSupport, + AmdIdsHdtOutGetFilter, + AmdIdsHdtOutInitPrivateData, + AmdIdsHdtOutPrint +}; + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h new file mode 100644 index 0000000000..bb4cc1df87 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpHdtout.h @@ -0,0 +1,146 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Debug_library Routines + * + * Contains all functions related to HDTOUT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _IDS_HDTOUT_H_ +#define _IDS_HDTOUT_H_ + +#define HDTOUT_VERSION 0x0200 + +/// HDTOUT command +#define HDTOUT_COMMAND 0x99cc +#define HDTOUT_INIT (0x10BF0000ul | HDTOUT_COMMAND) +#define HDTOUT_ASSERT (0xA0BF0000ul | HDTOUT_COMMAND) +#define HDTOUT_EXIT (0xE0BF0000ul | HDTOUT_COMMAND) +#define HDTOUT_PRINT (0xC0BF0000ul | HDTOUT_COMMAND) +#define HDTOUT_TIME_ANALYSE (0xD0BF0000ul | HDTOUT_COMMAND) +#define HDTOUT_BREAKPOINT (0xB0BF0000ul | HDTOUT_COMMAND) +#define HDTOUT_ERROR (0x1EBF0000ul | HDTOUT_COMMAND) + + +#define HDTOUT_ERROR_HEAP_ALLOCATION 0x1 +#define HDTOUT_ERROR_HEAP_AllOCATE_FAIL 0x2 + +#define HDTOUT_PRINTCTRL_OFF 0 +#define HDTOUT_PRINTCTRL_ON 1 +#define HDTOUT_ALL_CORES 0 +#define HDTOUT_BSP_ONLY 1 +#define HDTOUT_BUFFER_MODE_OFF 0 +#define HDTOUT_BUFFER_MODE_ON 1 + +#define HDTOUT_HEADER_SIGNATURE 0xDB1099CCul +#define HDTOUT_DEFAULT_BUFFER_SIZE 0x1000 +/// HDTOUT Header. +typedef struct _HDTOUT_HEADER { + UINT32 Signature; ///< 0xDB1099CC + UINT16 Version; ///< HDTOUT version. + UINT16 BufferSize; ///< Size in bytes. + UINT16 DataIndex; ///< Data Index. + UINT8 PrintCtrl; ///< 0 off no print 1 on print + UINT8 NumBreakpointUnit; ///< default 0 no bp unit others number of bp unit + UINT32 FuncListAddr; ///< 32 bit address to the list of functions that script can execute + UINT8 ConsoleType; ///< Console type - deprecated + UINT8 Event; ///< Event type. - deprecated + UINT8 OutBufferMode; ///< Off:stack mode, On: heap mode - deprecated + UINT32 EnableMask; ///< Bitmap to select which part should be streamed out + UINT64 ConsoleFilter; ///< Filter use to select which part should be streamed out + UINT8 BspOnlyFlag; ///< 1 Only Enable Bsp output, 0 enable On All cores + UINT8 Reserved[56 - 32]; ///< Reserved for header expansion + + CHAR8 BreakpointList[300]; ///< Breakpoint list + CHAR8 StatusStr[156]; ///< Shows current node, DCT, CS,... + CHAR8 Data[2]; ///< HDTOUT content. Its size will be determined by BufferSize. +} HDTOUT_HEADER; + +#define IDS_HDTOUT_BP_AND_OFF 0 +#define IDS_HDTOUT_BP_AND_ON 1 + +#define IDS_HDTOUT_BPFLAG_FORMAT_STR 0 +#define IDS_HDTOUT_BPFLAG_STATUS_STR 1 + +#define HDTOUT_BP_ACTION_HALT 1 +#define HDTOUT_BP_ACTION_PRINTON 2 +#define HDTOUT_BP_ACTION_PRINTONE 3 +#define HDTOUT_BP_ACTION_PRINTOFF 4 + +///breakpoint unit of HDTOUT +typedef struct _BREAKPOINT_UNIT { + UINT8 AndFlag : 1; ///< Next string is ANDed to current string + UINT8 BpFlag : 1; ///< Format string or Status string + UINT8 Action : 4; ///< Halt, start HDTOUT, or stop HDT,... + UINT8 BpStrOffset; ///< Offset from BreakpointList to the breakpoint string +} BREAKPOINT_UNIT; + + +BOOLEAN +AmdIdsHdtOutSupport ( + VOID + ); + +#endif //_IDS_HDTOUT_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c new file mode 100644 index 0000000000..fbcf1b749d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpRedirectIo.c @@ -0,0 +1,172 @@ +/** + * @file + * + * AMD Integrated Debug Debug_library Routines + * + * Contains all functions related to Redirect IO + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + /*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "AMD.h" +#include "IdsDebugPrint.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE + +/** + * Determine whether IDS console is enabled. + * + * + * @retval TRUE Alway return true + * + **/ +BOOLEAN +AmdIdsRedirectIoSupport ( + VOID + ) +{ + + return TRUE; +} + +/** + * Get customize Filter + * + * @param[in,out] Filter Filter do be filled + * + * @retval FALSE Alway return FALSE + * + **/ +BOOLEAN +AmdIdsRedirectIoGetFilter ( + IN OUT UINT64 *Filter + ) +{ + return FALSE; +} + +#define REDIRECT_IO_DATA_BEGIN 0x5f535452ul +#define REDIRECT_IO_DATA_END 0x5f454e44ul + +/** + * Print formated string with redirect IO + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[in] debugPrintPrivate - Option + * +**/ +VOID +AmdIdsRedirectIoPrint ( + IN CHAR8 *Buffer, + IN UINTN BufferSize, + IN IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate + ) +{ + UINT32 Value; + + Value = REDIRECT_IO_DATA_BEGIN; + LibAmdIoWrite (AccessWidth32, IDS_DEBUG_PRINT_IO_PORT, &Value, NULL); + + while (BufferSize--) { + LibAmdIoWrite (AccessWidth8, IDS_DEBUG_PRINT_IO_PORT, Buffer++, NULL); + } + + Value = REDIRECT_IO_DATA_END; + LibAmdIoWrite (AccessWidth32, IDS_DEBUG_PRINT_IO_PORT, &Value, NULL); +} + +/** + * Init local private data + * + * @param[in] Flag - filter flag + * @param[in] debugPrintPrivate - Point to debugPrintPrivate + * +**/ +VOID +AmdIdsRedirectIoInitPrivateData ( + IN UINT64 Flag, + IN IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate + ) +{ + +} + +CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRedirectIoInstance = +{ + AmdIdsRedirectIoSupport, + AmdIdsRedirectIoGetFilter, + AmdIdsRedirectIoInitPrivateData, + AmdIdsRedirectIoPrint +}; + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c new file mode 100644 index 0000000000..749c02a652 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsDpSerial.c @@ -0,0 +1,211 @@ +/** + * @file + * + * AMD Integrated Debug Debug_library Routines + * + * Contains all functions related to HDTOUT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + /*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "AMD.h" +#include "IdsDebugPrint.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE + +/** + * Determine whether IDS console is enabled. + * + * + * @retval TRUE Alway return true + * + **/ +STATIC BOOLEAN +AmdIdsSerialSupport ( + VOID + ) +{ + + return TRUE; +} + +/** + * Get Serial customize Filter + * + * @param[in,out] Filter Filter do be filled + * + * @retval FALSE Alway return FALSE + * + **/ +STATIC BOOLEAN +AmdIdsSerialGetFilter ( + IN OUT UINT64 *Filter + ) +{ + return FALSE; +} + + +#define IDS_SERIAL_PORT_LSR (IDS_SERIAL_PORT + 5) +#define IDS_LSR_TRANSMIT_HOLDING_REGISTER_EMPTY_MASK BIT5 +/** + * Send byte to Serial Port + * + * Before use this routine, please make sure Serial Communications Chip have been initialed + * + * @param[in] ByteSended Byte to be sended + * + * @retval TRUE Byte sended successfully + * @retval FALSE Byte sended failed + * + **/ +STATIC BOOLEAN +AmdIdsSerialSendByte ( + IN CHAR8 ByteSended + ) +{ + UINT32 RetryCount; + UINT8 Value; + + //Wait until LSR.Bit5 (Transmitter holding register Empty) + RetryCount = 200; + do { + LibAmdIoRead (AccessWidth8, IDS_SERIAL_PORT_LSR, &Value, NULL); + RetryCount--; + } while (((Value & IDS_LSR_TRANSMIT_HOLDING_REGISTER_EMPTY_MASK) == 0) && + (RetryCount > 0)); + + if (RetryCount == 0) { + //Time expired + return FALSE; + } else { + LibAmdIoWrite (AccessWidth8, IDS_SERIAL_PORT, &ByteSended, NULL); + return TRUE; + } +} + + +/** + * Print formated string + * + * @param[in] Buffer - Point to input buffer + * @param[in] BufferSize - Buffer size + * @param[in] debugPrintPrivate - Option + * +**/ +STATIC VOID +AmdIdsSerialPrint ( + IN CHAR8 *Buffer, + IN UINTN BufferSize, + IN IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate + ) +{ + BOOLEAN SendStatus; + UINT32 RetryCount; + RetryCount = 200; + while (BufferSize--) { + do { + if (*Buffer == '\n') { + SendStatus = AmdIdsSerialSendByte ('\r'); + } + SendStatus = AmdIdsSerialSendByte (*Buffer); + RetryCount--; + } while ((SendStatus == FALSE) && (RetryCount > 0)); + Buffer ++; + } +} + +/** + * Init local private data + * + * @param[in] Flag - filter flag + * @param[in] debugPrintPrivate - Point to debugPrintPrivate + * +**/ +STATIC VOID +AmdIdsSerialInitPrivateData ( + IN UINT64 Flag, + IN IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate + ) +{ + +} + +CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintSerialInstance = +{ + AmdIdsSerialSupport, + AmdIdsSerialGetFilter, + AmdIdsSerialInitPrivateData, + AmdIdsSerialPrint +}; + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c new file mode 100644 index 0000000000..f7e6a560eb --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Debug/IdsIdtTable.c @@ -0,0 +1,329 @@ +/** + * @file + * + * Adding IDT table for debugging exception + * + * Contains IDT related function + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + + /*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "amdlib.h" +#include "AMD.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "heapManager.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + IDS_STATUS +STATIC +IdsReplaceIdtr ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +STATIC +IdsRestoreIdtr ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +STATIC +IdsUpdateExceptionVector ( + IN VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern UINT64 IdsExceptionHandler; +extern UINT32 SizeIdtDescriptor; +extern UINT32 SizeTotalIdtDescriptors; + +/** + * IDS IDT table. + * + * This is the top level interface for IDS IDT table function. + * Adding a 'jmp $' into every exception handler. + * So debugger could use HDT to skip 'jmp $' and execute the iret, + * then they could find which instruction cause the exception. + * + * @param[in] IdsIdtFuncId IDT indicator value, see @ref IDS_IDT_FUNC_ID + * @param[in] DataPtr Points to data that may used by IdsIdtTable routine + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + **/ +IDS_STATUS +IdsExceptionTrap ( + IN IDS_IDT_FUNC_ID IdsIdtFuncId, + IN VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_STATUS ReturnFlag; + AGESA_STATUS Ignored; + + ReturnFlag = IDS_SUCCESS; + switch (IdsIdtFuncId) { + case IDS_IDT_REPLACE_IDTR_FOR_BSC: + if (IsBsp (StdHeader, &Ignored)) { + ReturnFlag = IdsReplaceIdtr (StdHeader); + } + break; + case IDS_IDT_RESTORE_IDTR_FOR_BSC: + if (IsBsp (StdHeader, &Ignored)) { + ReturnFlag = IdsRestoreIdtr (StdHeader); + } + break; + case IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP: + ReturnFlag = IdsUpdateExceptionVector (DataPtr, StdHeader); + break; + default: + return IDS_UNSUPPORTED; + break; + } + return ReturnFlag; +} + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/** + * Replace IDTR of BSC. + * + * Save IDTR of BSC to heap and replace IDTR. + * + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + **/ +IDS_STATUS +STATIC +IdsReplaceIdtr ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + ALLOCATE_HEAP_PARAMS AllocParams; + LOCATE_HEAP_PTR LocateHeap; + IDT_BASE_LIMIT IdtInfo; + + // Save IDTR to Heap + AllocParams.BufferHandle = IDS_SAVE_IDTR_HANDLE; + AllocParams.RequestedBufferSize = sizeof (IDT_BASE_LIMIT); + AllocParams.Persist = HEAP_TEMP_MEM; + if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { + return IDS_UNSUPPORTED; + } + GetIdtr ((IDT_BASE_LIMIT *) AllocParams.BufferPtr, StdHeader); + + // Check if host env has their own IDT + if (((IDT_BASE_LIMIT *) AllocParams.BufferPtr)->Base == 0) { + // Load AGESA's IDT + LocateHeap.BufferHandle = IDS_BSC_IDT_HANDLE; + // Check if we already allocated heap for creating IDT + if (HeapLocateBuffer (&LocateHeap, StdHeader) != AGESA_SUCCESS) { + // Create IDT for BSC in heap + AllocParams.BufferHandle = IDS_BSC_IDT_HANDLE; + AllocParams.RequestedBufferSize = sizeof (IDT_DESCRIPTOR) * 32; + AllocParams.Persist = HEAP_SYSTEM_MEM; + if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) { + return IDS_UNSUPPORTED; + } + IdtInfo.Base = (UINT64) AllocParams.BufferPtr; + } else { + IdtInfo.Base = (UINT64) LocateHeap.BufferPtr; + } + IdsUpdateExceptionVector ((VOID *) &IdtInfo, StdHeader); + SetIdtr (&IdtInfo, StdHeader); + } else { + return IDS_UNSUPPORTED; + } + return IDS_SUCCESS; +} + +/** + * Restore IDTR of BSC. + * + * Restore IDTR of BSC from heap. + * + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + **/ +IDS_STATUS +STATIC +IdsRestoreIdtr ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateHeap; + IDT_BASE_LIMIT IdtInfo; + + IdtInfo.Base = 0; + IdtInfo.Limit = 0; + GetIdtr (&IdtInfo, StdHeader); + + LocateHeap.BufferHandle = IDS_BSC_IDT_HANDLE; + if (HeapLocateBuffer (&LocateHeap, StdHeader) != AGESA_SUCCESS) { + // If AGESA loaded its own IDT, there must be a buffer with handle IDS_BSC_IDT_HANDLE in heap + return IDS_UNSUPPORTED; + } + // If current IDTR.Base != address of AGESA's own IDT, it is possibile that Host env load their own IDT + if (IdtInfo.Base != ((UINT64) (LocateHeap.BufferPtr))) { + return IDS_UNSUPPORTED; + } else { + LocateHeap.BufferHandle = IDS_SAVE_IDTR_HANDLE; + if (HeapLocateBuffer (&LocateHeap, StdHeader) != AGESA_SUCCESS) { + return IDS_UNSUPPORTED; + } + SetIdtr ((IDT_BASE_LIMIT *) LocateHeap.BufferPtr, StdHeader); + HeapDeallocateBuffer (IDS_SAVE_IDTR_HANDLE, StdHeader); + } + return IDS_SUCCESS; +} + +/** + * Update exception vector. + * + * Adding a 'jmp $' into every exception handler. + * So debugger could use HDT to skip 'jmp $' and execute the iret, + * then they could find which instruction cause the exception. + * + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + **/ +IDS_STATUS +STATIC +IdsUpdateExceptionVector ( + IN VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDT_DESCRIPTOR *IdtDesc; + UINT8 DescSize; + UINT16 Selector; + UINT16 i; + UINT64 HandlerOffset; + UINT64 EferRegister; + AGESA_STATUS Ignored; + + LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader); + if ((EferRegister & 0x100) != 0) { + DescSize = 16; + } else { + DescSize = 8; + } + + // Update limit + ((IDT_BASE_LIMIT *) DataPtr)->Limit = (UINT16) ((DescSize * 32) - 1); + // Update IDT + IdtDesc = (IDT_DESCRIPTOR *) (((IDT_BASE_LIMIT *) DataPtr)->Base); + HandlerOffset = (UINT64) IdsExceptionHandler; + GetCsSelector (&Selector, StdHeader); + + ASSERT (SizeTotalIdtDescriptors == (SizeIdtDescriptor * 32)); + for (i = 0; i < 32; i++) { + // Vector - 2 NMI handler for APs is used by AGESA. So we should not replace that handler. + if ((i == 2) && (!IsBsp (StdHeader, &Ignored))) { + IdtDesc = (IDT_DESCRIPTOR *) (((UINT8 *) IdtDesc) + DescSize); + HandlerOffset += SizeIdtDescriptor; + continue; + } + IdtDesc->OffsetLo = (UINT16) HandlerOffset & 0xFFFF; + IdtDesc->OffsetHi = (UINT16) (HandlerOffset >> 16); + IdtDesc->Flags = IDT_DESC_PRESENT | IDT_DESC_TYPE_INT32; + IdtDesc->Selector = Selector; + IdtDesc->Rsvd = 0; + if ((EferRegister & 0x100) != 0) { + IdtDesc->Offset64 = (UINT32) (HandlerOffset >> 32); + IdtDesc->Rsvd64 = 0; + } + IdtDesc = (IDT_DESCRIPTOR *) (((UINT8 *) IdtDesc) + DescSize); + HandlerOffset += SizeIdtDescriptor; + } + return IDS_SUCCESS; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c new file mode 100644 index 0000000000..ba19c87441 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.c @@ -0,0 +1,79 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Option Specific Routines for common F15 + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "IdsLib.h" + + +#define FILECODE PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h new file mode 100644 index 0000000000..dcea949c5b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/IdsF15AllService.h @@ -0,0 +1,76 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA IDS Translation + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ +#ifndef _IDS_F15_ALLSERVICE_H_ +#define _IDS_F15_ALLSERVICE_H_ +#ifdef __IDS_EXTENDED__ + #include IDS_EXT_INCLUDE_F15 (IdsIntF15AllService) +#endif + +#endif + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c new file mode 100644 index 0000000000..633d821c45 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c @@ -0,0 +1,420 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Option Specific Routines for common F15 + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "IdsLib.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "IdsF15AllService.h" +#include "IdsF15TnAllService.h" +#include "IdsF15TnNvDef.h" +#include "Gnb.h" +#include "GnbGfx.h" +#include "GnbRegistersTN.h" +#include "GnbRegisterAccTN.h" +#include "IdsRegAcc.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE + +/** + * IDS F15 Backend Function for HTC Controls + * + * This function is used to override HTC control Parameter. + * + * @param[in,out] DataPtr The Pointer of HTC register. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsSubHTCControlF15Tn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + HTC_REGISTER *PHtcReg; + IDS_STATUS NvValue; + + PHtcReg = (HTC_REGISTER *) DataPtr; + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_EN, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvThermalHTCEnDisabled: + PHtcReg->HtcEn = 0; + break; + case IdsNvThermalHTCEnEnabled: + PHtcReg->HtcEn = 1; + break; + case IdsNvThermalHTCEnAuto: + break; + default: + ASSERT (FALSE); + break; + } + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_OVERRIDE, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvThermalHTCOverrideDisabled: + break; + case IdsNvThermalHTCOverrideEnabled: + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_PSTATE_LIMIT, IdsNvPtr, StdHeader) { + ASSERT ((NvValue >= IdsNvThermalHtcPstateLimitMin) && (NvValue <= IdsNvThermalHtcPstateLimitMax)); + PHtcReg->HtcPstateLimit = NvValue; + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_TEMP_HYS, IdsNvPtr, StdHeader) { + ASSERT ((NvValue >= IdsNvThermalHTCTempHysMin) && (NvValue <= IdsNvThermalHTCTempHysMax)); + PHtcReg->HtcHystLmt = NvValue; + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_HTC_ACT_TEMP, IdsNvPtr, StdHeader) { + ASSERT ((NvValue >= IdsNvThermalHTCActTempMin) && (NvValue <= IdsNvThermalHTCActTempMax)); + PHtcReg->HtcTmpLmt = NvValue; + } + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Memory Mapping + * + * This function is used to override the following setting. + * EnableBankIntlv, ChannelIntlvMode, EnableNodeIntlv, MemHole, + * EnablePowerDown, PowerDownMode, EnableBurstLen32, BankSwizzle, + * UserTimingMode, MemClockValue, EnableParity, DqsTrainCtl, AllMemClks, + * and EnableClkHZAltVidC3. + * + * @param[in,out] DataPtr The Pointer of AMD_POST_PARAMS. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsSubMemoryMappingF15Tn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + AMD_POST_PARAMS *PostParamsPtr; + MEM_PARAMETER_STRUCT *RefPtr; + IDS_STATUS NvValue; + MEM_DATA_STRUCT * memdataptr; + + PostParamsPtr = (AMD_POST_PARAMS *)DataPtr; + memdataptr = PostParamsPtr->MemConfig.MemData; + RefPtr = memdataptr->ParameterListPtr; + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_BANK_INTERLEAVE, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvMemMappingBankInterleaveDisabled: + RefPtr->EnableBankIntlv = FALSE; + break; + case IdsNvMemMappingBankInterleaveAuto: + RefPtr->EnableBankIntlv = TRUE; + break; + default: + ASSERT (FALSE); + break; + } + } + + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_CHANNEL_INTERLEAVE, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvMemMappingChlInterleaveAddress_bit_6: + case IdsNvMemMappingChlInterleaveAddress_bit_12: + case IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_: + case IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_: + case IdsNvMemMappingChlInterleaveAddress_bit_8: + case IdsNvMemMappingChlInterleaveAddress_bit_9: + RefPtr->EnableChannelIntlv = TRUE; + break; + case IdsNvMemMappingChlInterleaveDisabled: + RefPtr->EnableChannelIntlv = FALSE; + break; + case IdsNvMemMappingChlInterleaveAuto: + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for Channel Interleave F10 + * + * This function is used to override Channel Interleave. + * + * @param[in,out] DataPtr The Pointer of Data to Override. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsIntSubChannelInterleaveF15Tn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_STATUS NvValue; + UINT8 *PDctSelIntLvAddr; + + PDctSelIntLvAddr = (UINT8 *)DataPtr; + //DctSelIntLvAddr DCT Select Function + //000b Address bit 6. + //001b Address bit 12. + //010b Hash: exclusive OR of address bits[20:16, 6]. + //011b Hash: exclusive OR of address bits[20:16, 9]. + //100b Address bit 8. + //101b Address bit 9. + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_CHANNEL_INTERLEAVE, IdsNvPtr, StdHeader) { + switch (NvValue) { + case IdsNvMemMappingChlInterleaveAddress_bit_6: + *PDctSelIntLvAddr = 0; + break; + case IdsNvMemMappingChlInterleaveAddress_bit_12: + *PDctSelIntLvAddr = 1; + break; + case IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_: + *PDctSelIntLvAddr = 2; + break; + case IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_: + *PDctSelIntLvAddr = 3; + break; + case IdsNvMemMappingChlInterleaveAddress_bit_8: + *PDctSelIntLvAddr = 4; + break; + case IdsNvMemMappingChlInterleaveAddress_bit_9: + *PDctSelIntLvAddr = 5; + break; + case IdsNvMemMappingChlInterleaveDisabled: + case IdsNvMemMappingChlInterleaveAuto: + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} + +/** + * IDS Backend Function for override GNB platform config + * + * @param[in,out] DataPtr The Pointer of BOOLEAN. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * @retval IDS_UNSUPPORTED No Backend function is found. + * + **/ +STATIC IDS_STATUS +IdsSubGnbPlatformCfgF15Tn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + GFX_PLATFORM_CONFIG *PGfx; + IDS_STATUS NvValue; + + PGfx = (GFX_PLATFORM_CONFIG*) DataPtr; + IDS_NV_READ_SKIP (NvValue, AGESA_IDS_NV_GNBHDAUDIOEN, IdsNvPtr, StdHeader) { + switch (NvValue) { + //Auto + case IdsNvGnbGfxNbAzaliaAuto: + break; + //Disabled + case IdsNvGnbGfxNbAzaliaDisabled: + PGfx->GnbHdAudio = 0; + break; + //Enabled + case IdsNvGnbGfxNbAzaliaEnabled: + PGfx->GnbHdAudio = 1; + break; + default: + ASSERT (FALSE); + break; + } + } + return IDS_SUCCESS; +} +/** + * IDS Family specific Function for programming GMMX register + * + * @param[in,out] DataPtr The Pointer of BOOLEAN. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Backend function is called successfully. + * + **/ +STATIC IDS_STATUS +IdsRegSetGmmxF15Tn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + IDS_REG_GMMX *PIdsRegGmmx; + UINT32 Value; + + PIdsRegGmmx = (IDS_REG_GMMX *) DataPtr; + GnbRegisterReadTN ( + TYPE_GMM, + PIdsRegGmmx->Offset, + &Value, + 0, + StdHeader); + + IdsLibDataMaskSet32 (&Value, PIdsRegGmmx->AndMask, PIdsRegGmmx->OrMask); + + GnbRegisterWriteTN ( + TYPE_GMM, + PIdsRegGmmx->Offset, + &Value, + 0, + StdHeader); + + return IDS_SUCCESS; +} + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn = +{ + IDS_FEAT_HTC_CTRL, + IDS_ALL_CORES, + IDS_HTC_CTRL, + AMD_FAMILY_15_TN, + IdsSubHTCControlF15Tn +}; + + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn = +{ + IDS_FEAT_MEMORY_MAPPING, + IDS_ALL_CORES, + IDS_INIT_POST_BEFORE, + AMD_FAMILY_15_TN, + IdsSubMemoryMappingF15Tn +}; + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn = +{ + IDS_FEAT_MEMORY_MAPPING, + IDS_ALL_CORES, + IDS_CHANNEL_INTERLEAVE, + AMD_FAMILY_15_TN, + IdsIntSubChannelInterleaveF15Tn +}; + +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn = +{ + IDS_FEAT_GNB_PLATFORMCFG, + IDS_ALL_CORES, + IDS_GNB_PLATFORMCFG_OVERRIDE, + AMD_FAMILY_15_TN, + IdsSubGnbPlatformCfgF15Tn +}; + +// For register access +CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn = + MAKE_IDS_FAMILY_FEAT_ALL_CORES ( + IDS_FAM_REG_GMMX, + AMD_FAMILY_15_TN, + IdsRegSetGmmxF15Tn + ); + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h new file mode 100644 index 0000000000..ed9df50b3a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h @@ -0,0 +1,76 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA IDS Translation + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ +#ifndef _IDS_F15_TN_ALLSERVICE_H_ +#define _IDS_F15_TN_ALLSERVICE_H_ +#ifdef __IDS_EXTENDED__ + #include IDS_EXT_INCLUDE_F15_TN (IdsIntF15TnAllService) +#endif + +#endif //_IDS_F15_TN_ALLSERVICE_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h new file mode 100644 index 0000000000..53007a4159 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h @@ -0,0 +1,311 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IDS NV definition for F15Tn + * + * Auto generated from CBS XML file + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS F15Tn + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + +#ifndef _IDSF15TNNVDEF_H_ +#define _IDSF15TNNVDEF_H_ +///HTC Enable +///Enable or disable Hardware Thermal Control. D18F3x64[0] +typedef enum { + IdsNvThermalHTCEnDisabled = 0,///<Disabled + IdsNvThermalHTCEnEnabled = 1,///<Enabled + IdsNvThermalHTCEnAuto = 3,///<Auto +} IdsNvThermalHTCEn; + +///HTC Override +///Enable or disable Thermal Control Override +typedef enum { + IdsNvThermalHTCOverrideDisabled = 0,///<Disabled + IdsNvThermalHTCOverrideEnabled = 1,///<Enabled +} IdsNvThermalHTCOverride; + +///HTC P-state limit select +///Specifies the P-state limit of all cores when in the P-state based HTC-active state +#define IdsNvThermalHtcPstateLimitMin 0 +#define IdsNvThermalHtcPstateLimitMax 7 + +///HTC Temperature Hysteresis +///Sets the temperature hysteresis for HTC. D18F3x64[27:24] +#define IdsNvThermalHTCTempHysMin 0 +#define IdsNvThermalHTCTempHysMax 0xF + +///HTC Activation Temp +///Sets the HTC temperature limit. D18F3x64[22:16] +#define IdsNvThermalHTCActTempMin 0 +#define IdsNvThermalHTCActTempMax 0x7F + +///Bank Interleave +///Interleave memory blocks across the DRAM chip selects for node 0. +typedef enum { + IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled + IdsNvMemMappingBankInterleaveAuto = 1,///<Auto +} IdsNvMemMappingBankInterleave; + +///DRAM Channel Interleave +///Interleave between two DCTs when they are in unganged mode. +typedef enum { + IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6 + IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12 + IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6] + IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9] + IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8 + IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9 + IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled + IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto +} IdsNvMemMappingChlInterleave; + +///ECC Symbol Size +///ECC symbol size and code selection. D18F3x180[25] +typedef enum { + IdsNvEccSymbolSizex4 = 0,///<x4 + IdsNvEccSymbolSizex8 = 1,///<x8 + IdsNvEccSymbolSizeAuto = 3,///<Auto +} IdsNvEccSymbolSize; + +///DRAM prefetches triggered from CPU requests +///Enable or disable DRAM prefetches Prefetch triggered by CPU requests. +typedef enum { + IdsNvPrefetchPrefCpuDis0 = 0,///<0 + IdsNvPrefetchPrefCpuDis1 = 1,///<1 + IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto +} IdsNvPrefetchPrefCpuDis; + +///HW prefetch training on SW Prefetches +///Enable or disable Hardware Prefetch training on Software Prefetches +typedef enum { + IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0 + IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1 + IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto +} IdsNvPrefetchDisHWPFforSWPF; + +///Hardware Prefetches +///Enable or disable Hardware Prefetches. +typedef enum { + IdsNvPrefetchDisHWPF0 = 0,///<0 + IdsNvPrefetchDisHWPF1 = 1,///<1 + IdsNvPrefetchDisHWPFAuto = 3,///<Auto +} IdsNvPrefetchDisHWPF; + +///UMI Gen2 +///Enable or disable UMI link Gen2 +typedef enum { + IdsNvFchGppUmiGen2Disabled = 0,///<Disabled + IdsNvFchGppUmiGen2Enabled = 1,///<Enabled +} IdsNvFchGppUmiGen2; + +///SATA Controller +///Disable or enable OnChip SATA controller +typedef enum { + IdsNvFchSataEnableDisabled = 0,///<Disabled + IdsNvFchSataEnableEnabled = 1,///<Enabled +} IdsNvFchSataEnable; + +///SATA Mode +///Select OnChip SATA Type +typedef enum { + IdsNvFchSataClassNative_IDE = 0,///<Native IDE + IdsNvFchSataClassRAID = 1,///<RAID + IdsNvFchSataClassAHCI = 3,///<AHCI + IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE + IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI + IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804 + IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804 +} IdsNvFchSataClass; + +///OnChip IDE +///Select OnChip IDE controller mode +typedef enum { + IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE + IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE +} IdsNvFchSataIdeMode; + +///IDE Controller +///Disable or enable OnChip IDE controller +typedef enum { + IdsNvFchSataIdeEnableDisabled = 0,///<Disabled + IdsNvFchSataIdeEnableEnabled = 1,///<Enabled +} IdsNvFchSataIdeEnable; + +///XHC Switch (Bus 0 Dev 16 Fn 0/1) +///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1) +typedef enum { + IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled + IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled +} IdsNvFchUsbXhciSwitch; + +///USB1(Bus 0 Dev 18 Fn 0/2) +///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2) +typedef enum { + IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci1Enable; + +///USB2 (Bus 0 Dev 19 Fn 0/2) +///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2) +typedef enum { + IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci2Enable; + +///USB3 (Bus 0 Dev 22 Fn 0/2) +///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2) +typedef enum { + IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci3Enable; + +///USB4 (Bus 0 Dev 20 Fn 5) +///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5) +typedef enum { + IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled + IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled +} IdsNvFchUsbOhci4Enable; + +///Hardware Monitor Enable +///Master switch to enable or disable hardware monitor function +typedef enum { + IdsNvFchHwmEnableDisabled = 0,///<Disabled + IdsNvFchHwmEnableEnabled = 1,///<Enabled +} IdsNvFchHwmEnable; + +///In-Chip IR +///Enable or disable the In-Chip IR +typedef enum { + IdsNvFchIrConfigDisabled = 0,///<Disabled + IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only + IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only + IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1 +} IdsNvFchIrConfig; + +///SD Configuration Mode +///Select SD Mode +typedef enum { + IdsNvFchSdConfigDisabled = 0,///<Disabled + IdsNvFchSdConfigADMA = 1,///<ADMA + IdsNvFchSdConfigDMA = 2,///<DMA + IdsNvFchSdConfigPIO = 3,///<PIO +} IdsNvFchSdConfig; + +typedef enum { + IdsNvFchAzaliaControlAuto = 0,///<Auto + IdsNvFchAzaliaControlDisabled = 1,///<Disabled + IdsNvFchAzaliaControlEnabled = 2,///<Enabled + IdsNvFchAzaliaControlReserved = 3,///<Reserved +} IdsNvFchAzaliaControl; + +///Integrated Graphics Controller +///Enable Integrate Graphics controller +typedef enum { + IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto + IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled + IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces +} IdsNvGnbGfxiGPU_CONTROL; + +///UMA Frame buffer Size +///Set UMA FB size +typedef enum { + IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto + IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M + IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M + IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M + IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M + IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M + IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M + IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G + IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G + IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G +} IdsNvGnbGfxUmaFrameBufferSize; + +///Enable Integrate HD Audio controller +typedef enum { + IdsNvGnbGfxNbAzaliaAuto = 0,///<Auto + IdsNvGnbGfxNbAzaliaDisabled = 1,///<Disabled + IdsNvGnbGfxNbAzaliaEnabled = 2,///<Enabled +} IdsNvGnbGfxNbAzalia; + +///PSPP Policy +///PCIe speed power policy +typedef enum { + IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled + IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance + IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High + IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low + IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving + IdsNvGnbPciePsppPolicyAuto = 5,///<Auto +} IdsNvGnbPciePsppPolicy; + +///IOMMU +/// +typedef enum { + IdsNvGnbNbIOMMUDisabled = 0,///<Disabled + IdsNvGnbNbIOMMUEnabled = 1,///<Enabled +} IdsNvGnbNbIOMMU; + +#endif // _IDSF15TNNVDEF_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h new file mode 100644 index 0000000000..a5db129f12 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsLib.h @@ -0,0 +1,444 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD IDS Routines + * + * Contains AMD AGESA Integrated Debug Macros + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + +#ifndef _IDS_LIB_H_ +#define _IDS_LIB_H_ +#include "OptionsIds.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "Table.h" +///Specific time stamp performance analysis which need ids control support +#if IDSOPT_CONTROL_ENABLED == TRUE + #define PERF_SPEC_TS_ANALYSE(StdHeader) IdsPerfSpecTsAnalyse(StdHeader) +#else + #define PERF_SPEC_TS_ANALYSE(StdHeader) +#endif + + +#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader)\ + if (((NvValue) = AmdIdsNvReader ((Nvid), (IdsNvPtr), (StdHeader))) != IDS_UNSUPPORTED) +#define IDS_GET_MASK32(HighBit, LowBit) ((((UINT32) 1 << (HighBit - LowBit + 1)) - 1) << LowBit) + +#define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap. +///Macro for Ids family feat +#define MAKE_IDS_FAMILY_FEAT_ALL_CORES(FEAT_ID, FAMILY, FUNCTION) \ + {IDS_FEAT_COMMON, IDS_ALL_CORES, FEAT_ID, FAMILY, FUNCTION} + + +// TYPEDEFS, STRUCTURES, ENUMS +// + +typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader); + +///Structure define for IdsAgesaRunFcnOnApLate +typedef struct _IDSAPLATETASK { + PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do + VOID *ApTaskPara; ///< Point to Ap function parameter1 +} IDSAPLATETASK; + +/// Data Structure defining IDS Data in HEAP +/// This data structure contains information that is stored in HEAP and will be +/// used in IDS backend function. It includes the size of memory to be allocated +/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA +/// table and the register table to override mem setting. It also includes a base +/// address of IDS override image which will be used to control the behavior of +/// AGESA testpoint if this feature is enabled. +typedef struct { + BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset + UINT64 IdsImageBase; ///< IDS Override Image Base Address + UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap + UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table + UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table + UINT32 IdsExtendOffset; ///< Offset of Ids extend heap +} IDS_CONTROL_STRUCT; + +#define MAX_PERFORMANCE_UNIT_NUM 100 +/// Data Structure of Parameters for TestPoint_TSC. +typedef struct { + UINT32 LineInFile; ///< Line of current time counter + UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC +} TestPoint_TSC; + +/// Data Structure of Parameters for TP_Perf_STRUCT. +typedef struct { + UINT32 Signature; ///< "TIME" + UINT32 Index; ///< The Index of TP_Perf_STRUCT + UINT32 TscInMhz; ///< Tsc counter in 1 mhz + TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT +} TP_Perf_STRUCT; + +///Bus speed Optimization +typedef enum { + IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance + IDS_POWER_POLICY_POWER = 1, ///< Power + IDS_POWER_POLICY_AUTO = 3, ///< Auto +} IDS_NV_AMDBUSSPEEDOPTIMIZATION; + +///IDS early AP task +typedef struct _IDS_EARLY_AP_TASK0 { + UINT8 Core; ///< Core to run Aptask + AP_TASK ApTask; ///< Speicify task property +} IDS_EARLY_AP_TASK0; + +#define IDS_EARLY_AP_TASK_PARA_NUM 100 +///IDS early AP task +typedef struct _IDS_EARLY_AP_TASK { + IDS_EARLY_AP_TASK0 Ap_Task0; ///< Ap Task exclude parameter buffer + UINT8 Parameters[IDS_EARLY_AP_TASK_PARA_NUM]; ///< Parameter buffer +} IDS_EARLY_AP_TASK; + + +#define IDS_ALL_SOCKET 0xFF +#define IDS_ALL_MODULE 0xFF +#define IDS_ALL_CORE 0xFF +#define IDS_ALL_DCT 0xFF + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +IDS_STATUS +IdsSubUCode ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubGangingMode ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubPowerDownMode ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubBurstLength32 ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + + +IDS_STATUS +IdsSubAllMemClkEn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubDllShutDownSR ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubHtLinkControl ( + OUT VOID *Data, + IN AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubPostPState ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubPowerPolicyOverride ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +AGESA_STATUS +AmdIdsCtrlInitialize ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +AmdIdsNvReader ( + IN UINT16 IdsNvId, + IN IDS_NV_ITEM *NvTablePtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +AmdGetIdsNvTable ( + IN OUT VOID **IdsNvTable, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +IdsOutPort ( + IN UINT32 Addr, + IN UINT32 Value, + IN UINT32 Flag + ); + +IDS_STATUS +IdsCommonReturn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +AGESA_STATUS +IdsAgesaRunFcnOnApLate ( + IN UINTN ApicIdOfCore, + IN IDSAPLATETASK *ApLateTaskPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +IdsAgesaRunFcnOnAllCoresLate ( + IN IDSAPLATETASK *ApLateTaskPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +IdsParseFeatTbl ( + IN AGESA_IDS_OPTION IdsOption, + IN CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[], + IN OUT VOID *DataPtr, + IN IDS_NV_ITEM *IdsNvPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +IDS_STATUS +IdsSubPowerDownCtrl ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +IDS_STATUS +IdsSubHdtOut ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +UINT8 +IdsGetNumPstatesFamCommon ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +IdsApRunCodeOnAllLocalCores ( + IN AP_TASK *TaskPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); +IDS_STATUS +IdsSubTargetPstate ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ); + +VOID +IdsMakePciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +IdsMakeHtLinkPciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtHostFeat, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +IdsMakeHtFeatPciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtHostFeat, + IN UINT32 PackageType, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +IdsMakeHtHostPciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtHostFeat, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +IdsMakeHtPhyRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtPhyLinkFeat, + IN UINT32 Address, + IN UINT32 Data, + IN UINT32 Mask + ); + +VOID +IdsLibPciWriteBitsToAllNode ( + IN PCI_ADDR PciAddress, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN UINT32 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); +VOID +IdsRunCodeOnCoreEarly ( + IN UINT8 Socket, + IN UINT8 Core, + IN AP_TASK* ApTask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +IdsGetMask64bits ( + IN UINT64 RegVal, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN OUT UINT64 *AndMask, + IN OUT UINT64 *OrMask + ); + +VOID +IdsGetMask32bits ( + IN UINT32 RegVal, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN OUT UINT32 *AndMask, + IN OUT UINT32 *OrMask + ); + +VOID +IdsGetMask16bits ( + IN UINT16 RegVal, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN OUT UINT32 *AndMask, + IN OUT UINT32 *OrMask + ); + +VOID +IdsGetStartEndModule ( + IN UINT8 ModuleId, + IN OUT UINT8 *StartModule, + IN OUT UINT8 *EndModule + ); + + +VOID +IdsGetStartEndSocket ( + IN UINT8 SocketId, + IN OUT UINT8 *StartSocket, + IN OUT UINT8 *EndSocket + ); + +BOOLEAN +IdsCheckPciExisit ( + IN PCI_ADDR PciAddr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +IdsLibDataMaskSet32 ( + IN OUT UINT32 *Value, + IN UINT32 AndMask, + IN UINT32 OrMask + ); +#define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFFul + +#endif //_IDS_LIB_H_ + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h new file mode 100644 index 0000000000..a3995e8a15 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/IdsPage.h @@ -0,0 +1,84 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Create outline and references for Integrated Debug Support Component mainpage documentation. + * + * Design guides, maintenance guides, and general documentation, are + * collected using this file onto the documentation mainpage. + * This file contains doxygen comment blocks, only. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Documentation + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/** + * @page idsmain Integrated Debug Support Component Documentation + * + * Additional documentation for the Integrated Debug Support component consists of + * + * - Maintenance Guides: + * - add here >>> + * - Design Guides: + * - add here >>> + * + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c new file mode 100644 index 0000000000..ec9355a70a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsLib.c @@ -0,0 +1,959 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug library Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "IdsLib.h" +#include "heapManager.h" + +#include "mm.h" +#include "mn.h" +#include "cpuLateInit.h" +#include "Filecode.h" +CODE_GROUP (G1_PEICC) +RDATA_GROUP (G1_PEICC) + +#define FILECODE PROC_IDS_LIBRARY_IDSLIB_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/** + * + * Get IDS NV table pointer in the AGESA Heap. + * + * @param[in,out] IdsNvTable The Pointer of IDS NV Table. + * @param[in,out] StdHeader The Pointer of Standard Header. + * + * @retval AGESA_SUCCESS Success to get the pointer of NV Table. + * @retval AGESA_ERROR Fail to get the pointer of NV Table. + **/ +AGESA_STATUS +AmdGetIdsNvTable ( + IN OUT VOID **IdsNvTable, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + LOCATE_HEAP_PTR LocateHeapStructPtr; + IDS_CONTROL_STRUCT *IdsCtrlPtr; + + LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE; + LocateHeapStructPtr.BufferPtr = NULL; + status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); + if (status == AGESA_SUCCESS) { + IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr; + *IdsNvTable = LocateHeapStructPtr.BufferPtr + IdsCtrlPtr->IdsNvTableOffset; + } + return status; +} + +/** + * + * Get IDS Override Image Base Address + * + * @param[in,out] IdsImageBase The Base Address of IDS Override Image. + * @param[in,out] StdHeader The Pointer of Standard Header. + * + * @retval AGESA_SUCCESS Success to get the pointer of NV Table. + * @retval AGESA_ERROR Fail to get the pointer of NV Table. + * + **/ +#if 0 +AGESA_STATUS +AmdGetIdsImagebase ( + IN OUT UINT64 *IdsImageBase, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + LOCATE_HEAP_PTR LocateHeapStructPtr; + IDS_CONTROL_STRUCT *IdsCtrlPtr; + + LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE; + LocateHeapStructPtr.BufferPtr = NULL; + status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); + if (status == AGESA_SUCCESS) { + IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr; + *IdsImageBase = IdsCtrlPtr->IdsImageBase; + } + return status; +} +#endif +/** + * + * Read IDS NV value in NV table. + * + * It searches the table until the Nv Id is found and return the NV value + * in the table. Otherwise, return IDS_UNSUPPORTED. + * + * @param[in] IdsNvId IDS NV ID + * @param[in] NvTablePtr NV Table pointer. + * @param[in,out] StdHeader The Pointer of Standard Header. + * + * @retval IDS_UNSUPPORTED NV ID is not found in the table + * Other Value The NV value + * + **/ +IDS_STATUS +AmdIdsNvReader ( + IN UINT16 IdsNvId, + IN IDS_NV_ITEM *NvTablePtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_STATUS Status; + IDS_NV_ITEM *NvPtr; + BOOLEAN IgnoreIdsDefault; + AGESA_STATUS status; + LOCATE_HEAP_PTR LocateHeapStructPtr; + IDS_CONTROL_STRUCT *IdsCtrlPtr; + + IgnoreIdsDefault = FALSE; + Status = IDS_UNSUPPORTED; + NvPtr = NvTablePtr; + + if (NvPtr != NULL) { + while (NvPtr->IdsNvId != AGESA_IDS_NV_END) { + if (NvPtr->IdsNvId == IdsNvId) { + break; + } else { + NvPtr ++; + } + } + if ((NvPtr->IdsNvId != AGESA_IDS_NV_END)) { + //Get IgnoreIdsDefault from heap + LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE; + LocateHeapStructPtr.BufferPtr = NULL; + status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); + if (status == AGESA_SUCCESS) { + IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr; + IgnoreIdsDefault = IdsCtrlPtr->IgnoreIdsDefault; + } + + if (IgnoreIdsDefault || (NvPtr->IdsNvValue != AGESA_IDS_DFT_VAL)) { + Status = NvPtr->IdsNvValue; + } + } + } + return Status; +} + +/** + * IDS function for only return IDS_SUCCESS + * + * + * @param[in,out] DataPtr meaningless data pointer + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * @param[in] IdsNvPtr The Pointer of NV Table. + * + * @retval IDS_SUCCESS Always succeeds. + * + **/ +IDS_STATUS +IdsCommonReturn ( + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN IDS_NV_ITEM *IdsNvPtr + ) +{ + return IDS_SUCCESS; +} + + +/** + * IDS function for ap run specific task after amdinitpost + * + * + * @param[in] ApicIdOfCore apic id of specific AP + * @param[in] ApLateTaskPtr The Pointer of IDSAPLATETASK. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval AGESA_SUCCESS Success + * @retval AGESA_ERROR meet some error + * + **/ +AGESA_STATUS +IdsAgesaRunFcnOnApLate ( + IN UINTN ApicIdOfCore, + IN IDSAPLATETASK *ApLateTaskPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS LaunchApParams; + +//init AgesaRunFcnOnAp parameters + LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID; + LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK); + LaunchApParams.RelatedDataBlock = ApLateTaskPtr; + LaunchApParams.StdHeader = *StdHeader; + + AGESA_TESTPOINT (TpIfBeforeRunApFromIds, StdHeader); + Status = AgesaRunFcnOnAp ((UINTN) ApicIdOfCore, &LaunchApParams); + AGESA_TESTPOINT (TpIfAfterRunApFromIds, StdHeader); + + return Status; +} + +/** + * IDS function force all cores run specific task after amdinitpost + * + * + * @param[in] ApLateTaskPtr The Pointer of IDSAPLATETASK. + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval AGESA_SUCCESS Success + * @retval AGESA_ERROR meet some error + * + **/ +AGESA_STATUS +IdsAgesaRunFcnOnAllCoresLate ( + IN IDSAPLATETASK *ApLateTaskPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_EXE_PARAMS LaunchApParams; + AGESA_STATUS Status; + +//init AgesaRunFcnOnAp parameters + Status = AGESA_SUCCESS; + LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID; + LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK); + LaunchApParams.RelatedDataBlock = ApLateTaskPtr; + LaunchApParams.StdHeader = *StdHeader; + + Status = RunLateApTaskOnAllAPs (&LaunchApParams, StdHeader); + +//do it on Bsp + Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, StdHeader); + return Status; +} + +/** + * IDS call-back function for ApDispatchTable + * + * @param[in] AmdApExeParams AP_EXE_PARAMS. + * + * @retval AGESA_SUCCESS Success + * @retval AGESA_ERROR meet some error + * + **/ +AGESA_STATUS +AmdIdsRunApTaskLate ( + IN AP_EXE_PARAMS *AmdApExeParams + ) +{ + IDSAPLATETASK *ApLateTaskPtr; + AGESA_STATUS Status; + + ApLateTaskPtr = (IDSAPLATETASK *)AmdApExeParams->RelatedDataBlock; + Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, &AmdApExeParams->StdHeader); + return Status; +} + +/** + * Get the number of P-State to support + * + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * @retval num The number of P-State to support. + * + **/ +UINT8 +IdsGetNumPstatesFamCommon ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 pstatesnum; + UINT8 i; + UINT8 IgnoredByte; + UINT32 Ignored; + BOOLEAN PStateEnabled; + UINT32 TempVar_c; + PSTATE_CPU_FAMILY_SERVICES *FamilyServices; + + pstatesnum = 0; + GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + + FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &IgnoredByte, StdHeader); + for (i = 0; i <= TempVar_c; i++) { + // Check if PState is enabled + FamilyServices->GetPstateRegisterInfo ( FamilyServices, + (UINT32) i, + &PStateEnabled, + &Ignored, + &Ignored, + &Ignored, + StdHeader); + if (PStateEnabled) { + pstatesnum++; + } + } + return pstatesnum; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Runs the given task on all cores (including self) on the socket of the executing + * core 0. + * + * This function is used to invoke all APs on the socket of the executing core 0 to + * run a specified AGESA procedure. + * + * @param[in] TaskPtr Function descriptor + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +IdsApRunCodeOnAllLocalCores ( + IN AP_TASK *TaskPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Core; + UINT32 BscCoreNum; + UINT32 Socket; + UINT32 BscSocket; + UINT32 IgnoredModule; + UINT32 NumberOfCores; + UINT32 NumberOfSockets; + AGESA_STATUS IgnoredSts; + + IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts); + NumberOfSockets = GetPlatformNumberOfSockets (); + + + for (Socket = 0; Socket < NumberOfSockets; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + for (Core = 0; Core < NumberOfCores; Core++) { + if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, TaskPtr, StdHeader); + } + } + } + } + // BSP codes + ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL); +} + +/** + * IdsMakePciRegEntry + * + * + * @param[in,out] TableEntry The Pointer of TableEntry +* @param[in] Family Family +* @param[in] Revision Revision +* @param[in] PciAddr PCI address +* @param[in] Data Or Mask +* @param[in] Mask And Mask + * + * + */ +VOID +IdsMakePciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + (*TableEntry)->EntryType = PciRegister; + (*TableEntry)->CpuRevision.Family = Family; + (*TableEntry)->CpuRevision.Revision = Revision; + (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; + (*TableEntry)->Entry.PciEntry.Address.AddressValue = PciAddr; + (*TableEntry)->Entry.PciEntry.Data = Data; + (*TableEntry)->Entry.PciEntry.Mask = Mask; + (*TableEntry)++; +} + +/** + * IdsMakeHtLinkPciRegEntry + * + * + * @param[in,out] TableEntry The Pointer of TableEntry +* @param[in] Family Family +* @param[in] Revision Revision +* @param[in] HtHostFeat HtHostFeat +* @param[in] PciAddr PCI address +* @param[in] Data Or Mask +* @param[in] Mask And Mask + * + * + */ +VOID +IdsMakeHtLinkPciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtHostFeat, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + (*TableEntry)->EntryType = HtLinkPciRegister; + (*TableEntry)->CpuRevision.Family = Family; + (*TableEntry)->CpuRevision.Revision = Revision; + (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; + (*TableEntry)->Entry.HtLinkPciEntry.LinkFeats.HtHostValue = HtHostFeat; + (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Address.AddressValue = PciAddr; + (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Data = Data; + (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Mask = Mask; + (*TableEntry)++; +} +/** + * IdsMakeHtFeatPciRegEntry + * + * + * @param[in,out] TableEntry The Pointer of TableEntry +* @param[in] Family Family +* @param[in] Revision Revision +* @param[in] HtHostFeat HtHostFeat +* @param[in] PackageType PackageType +* @param[in] PciAddr PCI address +* @param[in] Data Or Mask +* @param[in] Mask And Mask + * + * + */ +VOID +IdsMakeHtFeatPciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtHostFeat, + IN UINT32 PackageType, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + (*TableEntry)->EntryType = HtFeatPciRegister; + (*TableEntry)->CpuRevision.Family = Family; + (*TableEntry)->CpuRevision.Revision = Revision; + (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; + (*TableEntry)->Entry.HtFeatPciEntry.LinkFeats.HtHostValue = HtHostFeat; + (*TableEntry)->Entry.HtFeatPciEntry.PackageType.PackageTypeValue = PackageType; + (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Address.AddressValue = PciAddr; + (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Data = Data; + (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Mask = Mask; + (*TableEntry)++; +} +/** + * IdsMakeHostPciRegEntry + * + * + * @param[in,out] TableEntry The Pointer of TableEntry +* @param[in] Family Family +* @param[in] Revision Revision +* @param[in] HtHostFeat HtHostFeat +* @param[in] PciAddr PCI address +* @param[in] Data Or Mask +* @param[in] Mask And Mask + * + * + */ +VOID +IdsMakeHtHostPciRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtHostFeat, + IN UINT32 PciAddr, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + (*TableEntry)->EntryType = HtHostPciRegister; + (*TableEntry)->CpuRevision.Family = Family; + (*TableEntry)->CpuRevision.Revision = Revision; + (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; + (*TableEntry)->Entry.HtHostEntry.TypeFeats.HtHostValue = HtHostFeat; + (*TableEntry)->Entry.HtHostEntry.Address.AddressValue = PciAddr; + (*TableEntry)->Entry.HtHostEntry.Data = Data; + (*TableEntry)->Entry.HtHostEntry.Mask = Mask; + (*TableEntry)++; +} +/** + * IdsMakeHtPhyRegEntry + * + * + * @param[in,out] TableEntry The Pointer of TableEntry +* @param[in] Family Family +* @param[in] Revision Revision +* @param[in] HtPhyLinkFeat HtPhyLinkFeat +* @param[in] Address PCI address +* @param[in] Data Or Mask +* @param[in] Mask And Mask + * + * + */ +VOID +IdsMakeHtPhyRegEntry ( + IN OUT TABLE_ENTRY_FIELDS **TableEntry, + IN UINT64 Family, + IN UINT64 Revision, + IN UINT32 HtPhyLinkFeat, + IN UINT32 Address, + IN UINT32 Data, + IN UINT32 Mask + ) +{ + (*TableEntry)->EntryType = HtPhyRegister; + (*TableEntry)->CpuRevision.Family = Family; + (*TableEntry)->CpuRevision.Revision = Revision; + (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; + (*TableEntry)->Entry.HtPhyEntry.TypeFeats.HtPhyLinkValue = HtPhyLinkFeat; + (*TableEntry)->Entry.HtPhyEntry.Address = Address; + (*TableEntry)->Entry.HtPhyEntry.Data = Data; + (*TableEntry)->Entry.HtPhyEntry.Mask = Mask; + (*TableEntry)++; +} + +/** + * IdsOptionCallout + * + * Description + * Call the host environment interface to provide a user hook opportunity. + * + * @param[in] CallOutId This parameter indicates the IDS Call-Out-function desired. + * @param[in,out] DataPtr The pointer for callout function use + * @param[in,out] StdHeader Config handle for library and services + * + * @retval AGESA_SUCCESS Success + * @retval AGESA_ERROR meet some error + * + */ +AGESA_STATUS +IdsOptionCallout ( + IN UINTN CallOutId, + IN OUT VOID *DataPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_CALLOUT_STRUCT IdsCalloutData; + IDS_NV_ITEM NullEntry; + + NullEntry.IdsNvId = 0xFFFF; + NullEntry.IdsNvValue = 0xFFFF; + IdsCalloutData.StdHeader = *StdHeader; + IdsCalloutData.IdsNvPtr = &NullEntry; + IdsCalloutData.Reserved = (UINTN) DataPtr; + + return AgesaGetIdsData (CallOutId, &IdsCalloutData); + +} + +/** + * Ids Write PCI register to All node + * + * + * @param[in] PciAddress Pci address + * @param[in] Highbit High bit position of the field in DWORD + * @param[in] Lowbit Low bit position of the field in DWORD + * @param[in] Value Pointer to input value + * @param[in] StdHeader Standard configuration header + * + */ +VOID +IdsLibPciWriteBitsToAllNode ( + IN PCI_ADDR PciAddress, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN UINT32 *Value, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + AGESA_STATUS IgnoreStatus; + PCI_ADDR PciAddr; + + + for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoreStatus)) { + PciAddr.Address.Function = PciAddress.Address.Function; + PciAddr.Address.Register = PciAddress.Address.Register; + LibAmdPciWriteBits (PciAddr, Highbit, Lowbit, Value, StdHeader); + } + } + } +} + +/** + * + * + * Core 0 task to run local ap task at early + * + * @param[in] PEarlyApTask - point to IDS_EARLY_AP_TASK structure + * @param[in,out] StdHeader - The Pointer of AGESA Header + * + */ + +STATIC VOID +IdsCmnTaskCore0Early ( + IN IDS_EARLY_AP_TASK *PEarlyApTask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 IgnoredModule; + UINT32 IgnoredCore; + AGESA_STATUS IgnoredSts; + + ASSERT (PEarlyApTask->Ap_Task0.Core != 0); + + PEarlyApTask->Ap_Task0.ApTask.DataTransfer.DataPtr = &PEarlyApTask->Parameters[0]; + IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts); + ApUtilRunCodeOnSocketCore ((UINT8)Socket, PEarlyApTask->Ap_Task0.Core, &PEarlyApTask->Ap_Task0.ApTask, StdHeader); +} + +/** + * + * + * BSC task to run Core0 task at early, must only run on BSC + * + * @param[in] Socket - Socket which run the task + * @param[in] Core - Core which run the task + * @param[in] ApTask - Task for AP + * @param[in,out] StdHeader - The Pointer of AGESA Header + * + */ +VOID +IdsRunCodeOnCoreEarly ( + IN UINT8 Socket, + IN UINT8 Core, + IN AP_TASK* ApTask, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 BscSocket; + UINT32 BscCoreNum; + UINT32 IgnoredModule; + AGESA_STATUS IgnoredSts; + AP_TASK Core0Task; + IDS_EARLY_AP_TASK IdsEarlyTask; + + IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts); + ASSERT (~((Socket == BscSocket) && (Core == BscCoreNum))); + if ((Socket == BscSocket) || (Core == 0)) { + ApUtilRunCodeOnSocketCore (Socket, Core, ApTask, StdHeader); + } else { + //Init IDS_EARLY_AP_TASK for Core 0 + IdsEarlyTask.Ap_Task0.ApTask = *ApTask; + IdsEarlyTask.Ap_Task0.Core = Core; + //Init Parameter buffer, Target core can't get the parameter from pointer, which point to Host Core memory space + ASSERT ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM); + LibAmdMemCopy (&IdsEarlyTask.Parameters[0], ApTask->DataTransfer.DataPtr, sizeof (UINT32) * ApTask->DataTransfer.DataSizeInDwords, StdHeader); + if ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM) { + //Lauch Core0 1st + Core0Task.FuncAddress.PfApTaskI = (PF_AP_TASK_I)IdsCmnTaskCore0Early; + Core0Task.ExeFlags = WAIT_FOR_CORE; + Core0Task.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (IDS_EARLY_AP_TASK0) + ApTask->DataTransfer.DataSizeInDwords; + Core0Task.DataTransfer.DataPtr = &IdsEarlyTask; + Core0Task.DataTransfer.DataTransferFlags = 0; + ApUtilRunCodeOnSocketCore (Socket, 0, &Core0Task, StdHeader); + } + } +} + +/** + * + * + * This function get start end Module according to input ModuleId + * + * @param[in] ModuleId - 0xFF means all nodes, other value Specifies real NodeId + * @param[in,out] StartModule - Point to start Node + * @param[in,out] EndModule - Point to end Node + * + */ +VOID +IdsGetStartEndModule ( + IN UINT8 ModuleId, + IN OUT UINT8 *StartModule, + IN OUT UINT8 *EndModule + ) +{ + if (ModuleId == 0xFF) { + *StartModule = 0; + *EndModule = (UINT8) (GetPlatformNumberOfSockets () * GetPlatformNumberOfModules () - 1); + if (*EndModule > 7) { + *EndModule = 7; + } + } else { + *StartModule = ModuleId; + *EndModule = ModuleId; + } +} + +/** + * + * + * This function get start end socket according to input SocketId + * + * @param[in] SocketId - 0xFF means all sockets, other value Specifies real SokcetId + * @param[in,out] StartSocket - Point to start Socket + * @param[in,out] EndSocket - Point to end Socket + * + */ +VOID +IdsGetStartEndSocket ( + IN UINT8 SocketId, + IN OUT UINT8 *StartSocket, + IN OUT UINT8 *EndSocket + ) +{ + if (SocketId == 0xFF) { + *StartSocket = 0; + *EndSocket = (UINT8) (GetPlatformNumberOfSockets () - 1); + } else { + *StartSocket = SocketId; + *EndSocket = SocketId; + } +} + +/** + * + * + * This function transfer input High low bit to Mask + * + * @param[in] RegVal - Regval want to set + * @param[in] Highbit - (0~63) + * @param[in] Lowbit - (0~63) + * @param[in,out] AndMask - point value contain output AndMask + * @param[in,out] OrMask - point value contain output OrMask + * + */ +VOID +IdsGetMask64bits ( + IN UINT64 RegVal, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN OUT UINT64 *AndMask, + IN OUT UINT64 *OrMask + ) +{ + UINT64 Mask; + + if ((Highbit - Lowbit) != 63) { + Mask = (((UINT64) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT64) 0xFFFFFFFFFFFFFFFF; + } + *AndMask = ~(Mask << Lowbit); + *OrMask = (RegVal & Mask) << Lowbit; +} +/** + * + * + * This function transfer input High low bit to Mask + * + * @param[in] RegVal - Regval want to set + * @param[in] Highbit - (0~31) + * @param[in] Lowbit - (0~31) + * @param[in,out] AndMask - point value contain output AndMask + * @param[in,out] OrMask - point value contain output OrMask + * + */ + +VOID +IdsGetMask32bits ( + IN UINT32 RegVal, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN OUT UINT32 *AndMask, + IN OUT UINT32 *OrMask + ) +{ + UINT32 Mask; + + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32) 0xFFFFFFFF; + } + *AndMask = ~(Mask << Lowbit); + *OrMask = (RegVal & Mask) << Lowbit; + +} +/** + * + * + * This function transfer input High low bit to Mask + * + * @param[in] RegVal - Regval want to set + * @param[in] Highbit - (0~15) + * @param[in] Lowbit - (0~15) + * @param[in,out] AndMask - point value contain output AndMask + * @param[in,out] OrMask - point value contain output OrMask + * + */ + +VOID +IdsGetMask16bits ( + IN UINT16 RegVal, + IN UINT8 Highbit, + IN UINT8 Lowbit, + IN OUT UINT32 *AndMask, + IN OUT UINT32 *OrMask + ) +{ + UINT16 Mask; + + if ((Highbit - Lowbit) != 15) { + Mask = (((UINT16) 1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT16) 0xFFFF; + } + *AndMask = ~(Mask << Lowbit); + *OrMask = (RegVal & Mask) << Lowbit; +} + +/** + * + * + * IdsCheckPciExisit + * Use to check is the PCI device exisit of given address + * + * @param[in] PciAddr - Given PCI address + * @param[in,out] StdHeader - The Pointer of AGESA Header + * + * @retval TRUE The PCI device exisit + * @retval FALSE The PCI device doesn't exisit + * + * + */ +BOOLEAN +IdsCheckPciExisit ( + IN PCI_ADDR PciAddr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR _pciaddr; + UINT32 _pcidata; + BOOLEAN status; + + status = FALSE; + _pciaddr = PciAddr; + _pciaddr.Address.Register = 0; + LibAmdPciRead (AccessWidth32, _pciaddr, &_pcidata, StdHeader); + if (_pcidata != 0xFFFFFFFF || _pcidata != 0) { + status = TRUE; + } + return status; +} + +/** + * + * + * This function transfer input High low bit to Mask + * + * @param[in,out] Value - Regval want to And Or with Mask + * @param[in] AndMask - AndMask + * @param[in] OrMask - OrMask + * + */ + +VOID +IdsLibDataMaskSet32 ( + IN OUT UINT32 *Value, + IN UINT32 AndMask, + IN UINT32 OrMask + ) +{ + *Value &= AndMask; + *Value |= OrMask; +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c new file mode 100644 index 0000000000..02b2ed7be2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.c @@ -0,0 +1,316 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug library Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Filecode.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "Ids.h" +#include "IdsLib.h" +#include "IdsRegAcc.h" + +#define FILECODE PROC_IDS_LIBRARY_IDSREGACC_FILECODE + +extern CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[]; + +/** + * + * set the MSR of AP + * + * @param[in] PRegMsr point to REG_MSR + * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. + * + * + **/ +VOID +IdsRegSetMsrCmnTask ( + IN IDS_REG_MSR *PRegMsr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 value; + + LibAmdMsrRead (PRegMsr->MsrAddr, &value, StdHeader); + value &= PRegMsr->AndMask; + value |= PRegMsr->OrMask; + LibAmdMsrWrite (PRegMsr->MsrAddr, &value, StdHeader); +} + +/** + * + * + * IDS Common routine for RMW MSR for both ealry & later stage + * This routine can only be used when AP service have been established + * + * @param[in] PMsrReg Point MSR reg structure, contain TimePoint, Socket, Core,address, andmask, ormask + * @param[in,out] StdHeader - The Pointer of AGESA Header + * + */ +VOID +IdsRegSetMsr ( + IN IDS_REG_MSR *PMsrReg, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AP_TASK ApTask; + IDSAPLATETASK IdsLateTask; + UINT32 NumberOfCores; + UINT8 StartSocket; + UINT8 EndSocket; + UINT8 Socket; + UINT8 StartCore; + UINT8 EndCore; + UINT8 Core; + UINT32 BscCoreNum; + UINT32 BscSocket; + UINT32 IgnoredModule; + UINT32 ApicIdOfCore; + AGESA_STATUS IgnoredSts; + IDS_REG_AP_SERVICE_TIMEPOINT TimePoint; + + TimePoint = PMsrReg->TimePoint; + ASSERT ((TimePoint == IDS_REG_AP_SERVICE_EARLY) || + (TimePoint == IDS_REG_AP_SERVICE_POST) || + (TimePoint == IDS_REG_AP_SERVICE_LATE)); + + IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts); + IdsGetStartEndSocket (PMsrReg->Socket, &StartSocket, &EndSocket); + //TaskPtr for both IDS_REG_AP_SERVICE_EARLY, IDS_REG_AP_SERVICE_POST + ApTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)IdsRegSetMsrCmnTask; + ApTask.ExeFlags = WAIT_FOR_CORE; + ApTask.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (IDS_REG_MSR); + ApTask.DataTransfer.DataPtr = PMsrReg; + ApTask.DataTransfer.DataTransferFlags = 0; + + for (Socket = StartSocket; Socket <= EndSocket; Socket++) { + if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { + if (PMsrReg->Core == IDS_ALL_CORE) { + StartCore = 0; + EndCore = (UINT8)NumberOfCores - 1; + } else { + StartCore = PMsrReg->Core; + EndCore = PMsrReg->Core; + } + for (Core = StartCore; (Core <= EndCore) && (Core <= (NumberOfCores - 1)); Core++) { + if ((Core == BscCoreNum) && (Socket == BscSocket)) { + IdsRegSetMsrCmnTask (PMsrReg, StdHeader); + } else { + if (IsProcessorPresent (Socket, StdHeader)) { + if (TimePoint == IDS_REG_AP_SERVICE_EARLY) { + // At early stage, the AP's task has to be called by core 0, not by bsc + IdsRunCodeOnCoreEarly (Socket, Core, &ApTask, StdHeader); + } else if (TimePoint == IDS_REG_AP_SERVICE_POST) { + ApUtilRunCodeOnSocketCore (Socket, Core, &ApTask, StdHeader); + } else if (TimePoint == IDS_REG_AP_SERVICE_LATE) { + IdsLateTask.ApTask = (PF_IDS_AP_TASK)IdsRegSetMsrCmnTask; + IdsLateTask.ApTaskPara = PMsrReg; + GetLocalApicIdForCore (Socket, Core, &ApicIdOfCore, StdHeader); + IdsAgesaRunFcnOnApLate (ApicIdOfCore, &IdsLateTask, StdHeader); + } + } + } + } + } + } +} + +/** + * + * + * IDS Common routine for set Memory bit field using memory sevice + * + * @param[in] PMemReg Point to MEM reg structure + * @param[in,out] NBPtr - The Pointer of NBPtr + * + */ + +AGESA_STATUS +IdsRegSetMemBitField ( + IN IDS_REG_MEM *PMemReg, + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 CurDct; + UINT32 BfType; + UINT32 BfIndex; + UINT8 HighBit; + UINT8 LowBit; + UINT32 RegValue; + UINT8 Dct; + HighBit = 31; + LowBit = 0; + //Check if current module need set + if ((PMemReg->Module == IDS_ALL_MODULE) || (PMemReg->Module == NBPtr->Node)) { + //Save Current DCT + CurDct = NBPtr->Dct; + //Set BfType for MAKE_TSEFO + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + if ((PMemReg->Dct == IDS_ALL_DCT) || (PMemReg->Dct == Dct)) { + if (PMemReg->Type == IDS_REG_MEM_NB) { + BfType = NB_ACCESS; + BfIndex = _FN (PMemReg->Addr.PciAddr.Func, PMemReg->Addr.PciAddr.Offset); + } else if (PMemReg->Type == IDS_REG_MEM_PHY) { + if ((PMemReg->Addr.Index & 0xFFF00000) == 0x0D000000) { + BfType = DCT_PHY_DIRECT; + //Dram debug PHY only support 16 bits access + HighBit = 15; + LowBit = 0; + } else { + BfType = DCT_PHY_ACCESS; + } + BfIndex = PMemReg->Addr.Index; + } else if (PMemReg->Type == IDS_REG_MEM_EXTRA) { + BfType = DCT_EXTRA; + BfIndex = PMemReg->Addr.Index; + } else { + return AGESA_UNSUPPORTED; + } + MAKE_TSEFO (NBPtr->NBRegTable, BfType, BfIndex, HighBit, LowBit, BFIdsCmnMemReg); + + NBPtr->SwitchDCT (NBPtr, Dct); + RegValue = NBPtr->GetBitField (NBPtr, BFIdsCmnMemReg); + RegValue &= PMemReg->AndMask; + RegValue |= PMemReg->OrMask; + NBPtr->SetBitField (NBPtr, BFIdsCmnMemReg, RegValue); + } + } + //Restore DCT + NBPtr->SwitchDCT (NBPtr, CurDct); + } + return AGESA_SUCCESS; +} + +/** + * + * + * IDS routine for set family specific register + * + * @param[in] PFamReg Point Famreg structure, contain register define, and type + * @param[in,out] StdHeader - The Pointer of AGESA Header + * + */ + +VOID +IdsFamRegAccess ( + IN IDS_FAM_REG *PFamReg, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_IDS_OPTION RegFamId; + + switch (PFamReg->Type) { + case IDS_FAM_REG_TYPE_GMMX: + RegFamId = IDS_FAM_REG_GMMX; + break; + default: + RegFamId = IDS_OPTION_END; + } + if (RegFamId != IDS_OPTION_END) { + IdsParseFeatTbl (RegFamId, IdsRegAccessTbl, &PFamReg->Reg, NULL, StdHeader); + } +} + +/** + * Set PCI indirect registers + * + * + * @param[in] PPciIndirectReg Point to IDS_REG_PCI_INDIRECT structure + * @param[in,out] StdHeader - The Pointer of AGESA Header + */ + +VOID +IdsRegSetPciIndirect ( + IN IDS_REG_PCI_INDIRECT *PPciIndirectReg, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 IndexOffset; + UINT32 IndexValue; + UINT32 Value; + PCI_ADDR PciIndexPortAddr; + PCI_ADDR PciDataPortAddr; + + IndexOffset = LibAmdAccessWidth (PPciIndirectReg->Width); + PciIndexPortAddr.AddressValue = PPciIndirectReg->PciAddr; + PciDataPortAddr.AddressValue = PPciIndirectReg->PciAddr + IndexOffset; + //Read + LibAmdPciWrite (PPciIndirectReg->Width, PciIndexPortAddr, &PPciIndirectReg->IndirectRegOff, StdHeader); + LibAmdPciRead (PPciIndirectReg->Width, PciDataPortAddr, &Value, StdHeader); + //Modify + IdsLibDataMaskSet32 (&Value, PPciIndirectReg->AndMask, PPciIndirectReg->OrMask); + //Write + IndexValue = PPciIndirectReg->IndirectRegOff | PPciIndirectReg->WriteEnBit; + LibAmdPciWrite (PPciIndirectReg->Width, PciIndexPortAddr, &IndexValue, StdHeader); + LibAmdPciWrite (PPciIndirectReg->Width, PciDataPortAddr, &Value, StdHeader); +} + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h new file mode 100644 index 0000000000..250eae5f6c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Library/IdsRegAcc.h @@ -0,0 +1,180 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug library Routines + * + * Contains AMD AGESA debug macros and library functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#ifndef _IDSREGACC_H_ +#define _IDSREGACC_H_ +#include "mm.h" +#include "mn.h" +///AP service Time Point +typedef enum { + IDS_REG_AP_SERVICE_EARLY, ///< Amdinitearly + IDS_REG_AP_SERVICE_POST, ///< Amdinitpost + IDS_REG_AP_SERVICE_LATE, ///< After AmdInitPost +} IDS_REG_AP_SERVICE_TIMEPOINT; + +///Structure define for MSR register +typedef struct _IDS_REG_MSR { + IDS_REG_AP_SERVICE_TIMEPOINT TimePoint; ///< TimePoint + UINT8 Socket; ///< Socket + UINT8 Core; ///< Core + UINT32 MsrAddr; ///< Address of MSR Register + UINT64 AndMask; ///< And Mask + UINT64 OrMask; ///< Or Mask +} IDS_REG_MSR; + +///Enum for Mem Register access Type +typedef enum { + IDS_REG_MEM_NB, ///< PCI access + IDS_REG_MEM_PHY, ///< Memory Phy access + IDS_REG_MEM_EXTRA, ///< Memory Extra register access + IDS_REG_MEM_END, ///< End +} IDS_REG_MEM_ACCESS_TYPE; + +///Structure define for Mem register +typedef struct _IDS_REG_MEM { + IDS_REG_MEM_ACCESS_TYPE Type; ///< Type + UINT8 Module; ///< Module + UINT8 Dct; ///< Dct + union { + struct { + UINT8 Func; ///< PCI function + UINT16 Offset; ///< PCI offset + } PciAddr; ///< Pci Address + UINT32 Index; ///< index of indirect access + } Addr; ///< address + UINT32 AndMask; ///< And Mask + UINT32 OrMask; ///< Or Mask +} IDS_REG_MEM; + +///Family register type +typedef enum { + IDS_FAM_REG_TYPE_GMMX, ///< GMMX register access + IDS_FAM_REG_TYPE_END, ///< End +} IDS_FAM_REG_TYPE; + +///Structure define for GMMX register +typedef struct _IDS_REG_GMMX { + UINT32 Offset; ///< Offset of GMMX register + UINT32 AndMask; ///< And Mask + UINT32 OrMask; ///< Or Mask +} IDS_REG_GMMX; + +///Structure define for family specific register +typedef struct _IDS_FAM_REG { + IDS_FAM_REG_TYPE Type; ///< Register type + union { + IDS_REG_GMMX Gmmx; ///< GMMX + } Reg; +} IDS_FAM_REG; + +///Structure define for PCI indirect register +typedef struct _IDS_REG_PCI_INDIRECT { + ACCESS_WIDTH Width; ///< access width + UINT32 PciAddr; ///< PCI address + UINT32 IndirectRegOff; ///< PCI indirect register offset + UINT32 WriteEnBit; ///< Write Enable bit + UINT32 AndMask; ///< And Mask + UINT32 OrMask; ///< Or Mask +} IDS_REG_PCI_INDIRECT; + +VOID +IdsRegSetMsrCmnTask ( + IN IDS_REG_MSR *PRegMsr, + IN OUT AMD_CONFIG_PARAMS *StdHeader +); + +VOID +IdsRegSetMsr ( + IN IDS_REG_MSR *PMsrReg, + IN OUT AMD_CONFIG_PARAMS *StdHeader +); + +AGESA_STATUS +IdsRegSetMemBitField ( + IN IDS_REG_MEM *PMemReg, + IN OUT MEM_NB_BLOCK *NBPtr +); + +VOID +IdsFamRegAccess ( + IN IDS_FAM_REG *PFamReg, + IN OUT AMD_CONFIG_PARAMS *StdHeader +); + +VOID +IdsRegSetPciIndirect ( + IN IDS_REG_PCI_INDIRECT *PPciIndirectReg, + IN OUT AMD_CONFIG_PARAMS *StdHeader +); + +#endif //_IDSREGACC_H_ + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h new file mode 100644 index 0000000000..39c83f6eb7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/OptionsIds.h @@ -0,0 +1,113 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * + * Warning: When you enable the IDSOPT_CONTROL_NV_TO_CMOS feature. + * please make the cmos region defined by IDS_OPT_CMOS_REGION_START & + * IDS_OPT_CMOS_REGION_END can be touched between IDS HOOK point + * IDS_CPU_Early_Override and IDS_BEFORE_AP_EARLY_HALT of BSP + * + * IDSOPT_CONTROL_NV_TO_CMOS + * IDS_OPT_CMOS_INDEX_PORT + * IDS_OPT_CMOS_DATA_PORT + * IDS_OPT_CMOS_REGION_START + * IDS_OPT_CMOS_REGION_END + * + * IDSOPT_TRACING_ENABLED + * IDSOPT_CUSTOMIZE_TRACING_SERVICE + * + * IDSOPT_TRACING_CONSOLE_HDTOUT + * IDSOPT_TRACING_CONSOLE_SERIALPORT + * IDSOPT_SERIAL_PORT (default 0x3F8) + * IDSOPT_TRACING_CONSOLE_REDIRECT_IO + * IDSOPT_DEBUG_PRINT_IO_PORT (default 0x80) + * IDSOPT_TRACE_BLD_CFG + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * IDSOPT_DEBUG_CODE_ENABLED + * IDSOPT_IDT_EXCEPTION_TRAP + * IDSOPT_C_OPTIMIZATION_DISABLED + * + **/ + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c new file mode 100644 index 0000000000..a94ba44db0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Perf/IdsPerf.c @@ -0,0 +1,248 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Integrated Debug Routines for performance analysis + * + * Contains AMD AGESA debug macros and functions for performance analysis + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: IDS + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + */ +/***************************************************************************** + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "IdsLib.h" +#include "IdsDpHdtout.h" +#include "heapManager.h" +#include "cpuFamilyTranslation.h" +#include "amdlib.h" + +#define FILECODE PROC_IDS_PERF_IDSPERF_FILECODE +/** + * + * IDS Performance function for Output to HDT. + * + * Invoke communications with the HDT environment to allow the user to issue + * debug commands. If the sign = 0x0, HDT Control Register will be initialized to + * catch the special I/O for HDT_OUT. Otherwise, it will inform HDT script + * function what is meaning for the value to output to HDT. + * + * @param[in] Command HDT_OUT Command. + * @param[in] Data The Data to output to HDT. + * @param[in,out] StdHeader The Pointer of AGESA Header + * + **/ +#define HDTOUT_COMMAND 0x99cc +#define HDTOUT_TIME_ANALYSE (0xD0BF0000ul | HDTOUT_COMMAND) + +VOID +IdsPerfHdtOut ( + IN UINT16 Command, + IN UINT32 Data, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + IdsOutPort (HDTOUT_TIME_ANALYSE, Data, 0); +} + +/** + * + * Get Ids Performance analysis table pointer in the AGESA Heap. + * + * @param[in] LineInFile ((FILECODE) shift 16)+ Line number + * @param[in,out] StdHeader The Pointer of AGESA Header + * + * @retval AGESA_SUCCESS Success to get the pointer of Performance analysis Table. + * @retval AGESA_ERROR Fail to get the pointer of Performance analysis Table. + * @retval AGESA_UNSUPPORTED Get an exclude testpoint + * + **/ +AGESA_STATUS +IdsPerfTimestamp ( + IN UINT32 LineInFile, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + UINT32 Index; + TP_Perf_STRUCT *PerfTableEntry; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + LOCATE_HEAP_PTR LocateHeapStructPtr; + UINT64 CurrentTsc; + + //if heap is not ready yet, don't invoke locate buffer, or else will cause event log & locate heap dead loop + if (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET ) { + LibAmdMsrRead (TSC, &CurrentTsc, StdHeader); + + LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE; + LocateHeapStructPtr.BufferPtr = NULL; + status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); + if (status == AGESA_SUCCESS) { + PerfTableEntry = (TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr); + } else { + AllocHeapParams.RequestedBufferSize = sizeof (TP_Perf_STRUCT); + AllocHeapParams.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE; + AllocHeapParams.Persist = HEAP_SYSTEM_MEM; + status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); + if (status != AGESA_SUCCESS) { + return status; + } + PerfTableEntry = (TP_Perf_STRUCT *) (AllocHeapParams.BufferPtr); + LibAmdMemFill (PerfTableEntry, 0, sizeof (TP_Perf_STRUCT), StdHeader); + PerfTableEntry->Signature = 'EMIT'; + } + + Index = PerfTableEntry ->Index; + + PerfTableEntry ->TP[Index].LineInFile = LineInFile; + PerfTableEntry ->TP[Index].StartTsc = CurrentTsc; + PerfTableEntry ->Index = ++Index; + } + return AGESA_SUCCESS; +} + +typedef struct _PERFREGBACKUP { + UINT64 SMsr; + UINT32 Dr0Reg; + UINT32 Dr7Reg; + UINT32 Cr4Reg; +} PERFREGBACKUP; + +VOID +IdsPerfSaveReg ( + IN OUT PERFREGBACKUP * perfreg, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + LibAmdReadCpuReg (DR0_REG, &perfreg->Dr0Reg); + + LibAmdReadCpuReg (DR7_REG, &perfreg->Dr7Reg); + + LibAmdReadCpuReg (CR4_REG, &perfreg->Cr4Reg); +} + +VOID +IdsPerfRestoreReg ( + IN PERFREGBACKUP * perfreg, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + + LibAmdWriteCpuReg (DR0_REG, perfreg->Dr0Reg); + + LibAmdWriteCpuReg (DR7_REG, perfreg->Dr7Reg); + + LibAmdWriteCpuReg (CR4_REG, perfreg->Cr4Reg); +} +/** + * Output Test Point function . + * + * @param[in,out] StdHeader The Pointer of Standard Header. + * + * @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE. + * @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE. + * + **/ +AGESA_STATUS +IdsPerfAnalyseTimestamp ( + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS status; + LOCATE_HEAP_PTR LocateHeapStructPtr; + UINT32 TscRateInMhz; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + PERFREGBACKUP PerfReg; + UINT32 CR4reg; + UINT64 SMsr; + + LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE; + LocateHeapStructPtr.BufferPtr = NULL; + status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); + if (status != AGESA_SUCCESS) { + return status; + } + GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader); + ((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz; + if (AmdIdsHdtOutSupport () == FALSE) { + //Init break point + IdsPerfSaveReg (&PerfReg, StdHeader); + + SMsr |= 1; + + LibAmdWriteCpuReg (DR2_REG, 0x99cc); + LibAmdWriteCpuReg (DR7_REG, 0x02000420); + + LibAmdReadCpuReg (CR4_REG, &CR4reg); + LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3)); + + IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader); + IdsPerfRestoreReg (&PerfReg, StdHeader); + } + return status; +} + + |