AGESA F15tn: AMD family15 AGESA code for Trinity

AMD AGESA code for trinity.

Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

183 files changed, 114850 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h
new file mode 100644
index 0000000000..32bfc95353
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h
@@ -0,0 +1,194 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Misc common definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNB_H_
+#define _GNB_H_
+
+#pragma pack (push, 1)
+
+#define GNB_DEADLOOP() \
+{ \
+  VOLATILE BOOLEAN k; \
+  k = TRUE; \
+  while (k) { \
+  } \
+}
+#ifdef IDSOPT_TRACING_ENABLED
+  #if (IDSOPT_TRACING_ENABLED == TRUE)
+    #define GNB_TRACE_ENABLE
+  #endif
+#endif
+
+
+#ifndef GNB_DEBUG_CODE
+  #ifdef GNB_TRACE_ENABLE
+    #define  GNB_DEBUG_CODE(Code) Code
+  #else
+    #define  GNB_DEBUG_CODE(Code)
+  #endif
+#endif
+
+#ifndef MIN
+  #define MIN(x, y) (((x) > (y))? (y):(x))
+#endif
+
+#ifndef MAX
+  #define MAX(x, y) (((x) > (y))? (x):(y))
+#endif
+
+#define OFF 0
+
+#define PVOID UINT64
+
+#define STRING_TO_UINT32(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a))
+
+#define GnbLibGetHeader(x)  ((AMD_CONFIG_PARAMS*) (x)->StdHeader)
+
+#define AGESA_STATUS_UPDATE(Current, Aggregated) \
+if (Current > Aggregated) { \
+  Aggregated = Current; \
+}
+
+#ifndef offsetof
+  #define offsetof(s, m) (UINTN)&(((s *)0)->m)
+#endif
+
+
+//Table properties
+
+#define TABLE_PROPERTY_DEAFULT                     0x00000000ul
+#define TABLE_PROPERTY_IGFX_DISABLED               0x00000001ul
+#define TABLE_PROPERTY_IOMMU_DISABLED              0x00000002ul
+#define TABLE_PROPERTY_LCLK_DEEP_SLEEP             0x00000004ul
+#define TABLE_PROPERTY_ORB_CLK_GATING              0x00000008ul
+#define TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING       0x00000010ul
+#define TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING       0x00000020ul
+#define TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING       0x00000040ul
+#define TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING       0x00000080ul
+#define TABLE_PROPERTY_BAPM                        0x00000100ul
+#define TABLE_PROPERTY_SECONDARY_GNB               0x00000200ul
+#define TABLE_PROPERTY_NMI_SYNCFLOOD               0x00000400ul
+#define TABLE_PROPERTY_NBDPM                       0x00000800ul
+#define TABLE_PROPERTY_LOADLINE_ENABLE             0x00001000ul
+#define TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING       0x00002000ul
+
+//Register access flags Flags
+#define GNB_REG_ACC_FLAG_S3SAVE                    0x00000001ul
+
+/// LCLK DPM enable control
+typedef enum {
+  LclkDpmDisabled,          ///<LCLK DPM disabled
+  LclkDpmRcActivity,        ///<LCLK DPM enabled and use Root Complex Activity monitor method
+} LCLK_DPM_MODE;
+
+
+/// Power gaiter data setting (do not change this structure definition)
+typedef struct {
+  UINT16  pwrdata0 ;
+  UINT16  pwrdata1 ;
+  UINT16  pwrdata2 ;
+  UINT16  pwrdata3 ;
+  UINT16  ResetTimer;           ///< Reset Timer
+  UINT16  IsoTimer;             ///< Isolation Timer
+} POWER_GATE_DATA;
+
+
+/// Topology information
+typedef struct {
+  BOOLEAN   PhantomFunction;    ///< PCIe topology have device with phantom function
+  BOOLEAN   PcieToPciexBridge;  ///< PCIe topology have device with Pcieto Pcix bridge
+} GNB_TOPOLOGY_INFO;
+
+
+/// GNB installable services
+typedef enum {
+  GnbPcieFamConfigService,                ///< PCIe config service
+  GnbPcieFamInitService,                  ///< PCIe Init service
+  GnbPcieFamDebugService,                 ///< PCIe Debug service
+  GnbRegisterAccessService,               ///< GNB register access service
+  GnbIommuService                         ///< GNB IOMMU config service
+} GNB_SERVICE_ID;
+
+/// GNB service entry
+typedef struct _GNB_SERVICE {
+  GNB_SERVICE_ID        ServiceId;        ///< Service ID
+  UINT64                Family;           ///< CPU family
+  VOID                  *ServiceProtocol; ///< Service protocol
+  struct  _GNB_SERVICE  *NextService;     ///< Pointer to next service
+} GNB_SERVICE;
+
+#define GNB_STRINGIZE(x)                  #x
+#define GNB_SERVICE_DEFINITIONS(x)        GNB_STRINGIZE (Services/x/x.h)
+#define GNB_MODULE_DEFINITIONS(x)         GNB_STRINGIZE (Modules/x/x.h)
+#define GNB_MODULE_INSTALL(x)             GNB_STRINGIZE (Modules/x/x##Install.h)
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h
new file mode 100644
index 0000000000..3a54cf9992
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFamServices.h
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe family specific services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBFAMSERVICES_H_
+#define _GNBFAMSERVICES_H_
+
+#include "Gnb.h"
+#include "GnbPcie.h"
+#include "GnbIommu.h"
+
+typedef AGESA_STATUS (F_GNB_REGISTER_ACCESS) (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       UINT8                      RegisterSpaceType,
+  IN       UINT32                     Address,
+  IN       VOID                       *Value,
+  IN       UINT32                     Flags,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+);
+
+/// Register Read/Write protocol
+typedef struct {
+  F_GNB_REGISTER_ACCESS               *Read;    ///< Read Register
+  F_GNB_REGISTER_ACCESS               *Write;   ///< Write Register
+} GNB_REGISTER_SERVICE;
+
+AGESA_STATUS
+GnbFmCreateIvrsEntry (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+typedef AGESA_STATUS F_GNBFMCREATEIVRSENTRY (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GnbFmCheckIommuPresent (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+typedef BOOLEAN F_GNBFMCHECKIOMMUPRESENT (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+/// GNB IOMMU services
+typedef struct {
+  F_GNBFMCHECKIOMMUPRESENT             *GnbFmCheckIommuPresent;       ///< GnbFmCheckIommuPresent
+  F_GNBFMCREATEIVRSENTRY               *GnbFmCreateIvrsEntry;         ///< GnbFmCreateIvrsEntry
+} GNB_FAM_IOMMU_SERVICES;
+
+
+PCI_ADDR
+GnbFmGetPciAddress (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbFmGetBusDecodeRange (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *StartBusNumber,
+     OUT   UINT8                      *EndBusNumber,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbFmGetLinkId (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *LinkId,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
new file mode 100644
index 0000000000..02c38d684c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbFuseTable.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Graphics controller BIF straps control services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GNBFUSETABLE_H_
+#define _GNBFUSETABLE_H_
+
+#pragma pack (push, 1)
+
+#define PP_FUSE_MAX_NUM_DPM_STATE 5
+#define PP_FUSE_MAX_NUM_SW_STATE  6
+
+/// Fuse definition structure
+typedef struct  {
+  UINT8                       PPlayTableRev;              ///< PP table revision
+  UINT8                       SclkDpmValid[6];            ///< Valid DPM states
+  UINT8                       SclkDpmDid[6];              ///< Sclk DPM DID
+  UINT8                       SclkDpmVid[6];              ///< Sclk DPM VID
+  UINT8                       SclkDpmCac[5];              ///< Sclk DPM Cac
+  UINT8                       PolicyFlags[6];             ///< State policy flags
+  UINT8                       PolicyLabel[6];             ///< State policy label
+  UINT8                       VclkDid[4];                 ///< VCLK DID
+  UINT8                       DclkDid[4];                 ///< DCLK DID
+  UINT8                       SclkThermDid;               ///< Thermal SCLK
+  UINT8                       VclkDclkSel[6];             ///< Vclk/Dclk selector
+  UINT8                       LclkDpmValid[4];            ///< Valid Lclk DPM states
+  UINT8                       LclkDpmDid[4];              ///< Lclk DPM DID
+  UINT8                       LclkDpmVid[4];              ///< Lclk DPM VID
+  UINT8                       DisplclkDid[4];             ///< Displclk DID
+  UINT8                       PcieGen2Vid;                ///< Pcie Gen 2 VID
+  UINT8                       MainPllId;                  ///< Main PLL Id from fuses
+  UINT8                       WrCkDid;                    ///< WRCK SMU clock Divisor
+  UINT8                       SclkVid[4];                 ///< Sclk VID
+  UINT8                       GpuBoostCap;                ///< GPU boost cap
+  UINT16                      SclkDpmTdpLimit[6];         ///< Sclk DPM TDP limit
+  UINT16                      SclkDpmTdpLimitPG;          ///< TDP limit PG
+  UINT32                      SclkDpmBoostMargin;         ///< Boost margin
+  UINT32                      SclkDpmThrottleMargin;      ///< Throttle margin
+  BOOLEAN                     VceSateTableSupport;        ///< Support VCE in PP table
+  UINT8                       VceFlags[4];                ///< VCE Flags
+  UINT8                       VceMclk[4];                 ///< MCLK for VCE
+  UINT8                       VceReqSclkSel[4];           ///< SCLK selector for VCE
+  UINT8                       EclkDid[4];                 ///< Eclk DID
+} PP_FUSE_ARRAY;
+
+#pragma pack (pop)
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
new file mode 100644
index 0000000000..1c8eab082b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfx.h
@@ -0,0 +1,472 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64730 $   @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBGFX_H_
+#define _GNBGFX_H_
+
+//#ifndef PVOID
+//  typedef UINT64 PVOID;
+//#endif
+
+#define DEVICE_DFP                                0x1
+#define DEVICE_CRT                                0x2
+#define DEVICE_LCD                                0x3
+
+
+#define CONNECTOR_DISPLAYPORT_ENUM                0x3013
+#define CONNECTOR_HDMI_TYPE_A_ENUM                0x300c
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM          0x3003
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM            0x3004
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM          0x3001
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM            0x3002
+#define CONNECTOR_VGA_ENUM                        0x3005
+#define CONNECTOR_LVDS_ENUM                       0x300E
+#define CONNECTOR_eDP_ENUM                        0x3014
+#define CONNECTOR_LVDS_eDP_ENUM                   0x3016
+#define ENCODER_TRAVIS_ENUM_ID1                   0x2123
+#define ENCODER_TRAVIS_ENUM_ID2                   0x2223
+#define ENCODER_ALMOND_ENUM_ID1                   0x2122
+#define ENCODER_NOT_PRESENT                       0x0000
+
+// no eDP->LVDS translator chip
+#define eDP_TO_LVDS_RX_DISABLE                    0x00
+// common eDP->LVDS translator chip without AMD SW init
+#define eDP_TO_LVDS_COMMON_ID                     0x01
+// Realtek tansaltor which require AMD SW init
+#define eDP_TO_LVDS_REALTEK_ID                    0x02
+
+
+#define ATOM_DEVICE_CRT1_SUPPORT                  0x0001
+#define ATOM_DEVICE_DFP1_SUPPORT                  0x0008
+#define ATOM_DEVICE_DFP6_SUPPORT                  0x0040
+#define ATOM_DEVICE_DFP2_SUPPORT                  0x0080
+#define ATOM_DEVICE_DFP3_SUPPORT                  0x0200
+#define ATOM_DEVICE_DFP4_SUPPORT                  0x0400
+#define ATOM_DEVICE_DFP5_SUPPORT                  0x0800
+#define ATOM_DEVICE_LCD1_SUPPORT                  0x0002
+
+/// Graphics card information structure
+typedef struct {
+  UINT32   AmdPcieGfxCardBitmap;                  ///< AMD PCIE graphics card information
+  UINT32   PcieGfxCardBitmap;                     ///< All PCIE graphics card information
+  UINT32   PciGfxCardBitmap;                      ///< All PCI graphics card information
+} GFX_CARD_CARD_INFO;
+
+typedef enum {
+  iGpuVgaAdapter,                                       ///< Configure iGPU as VGA adapter
+  iGpuVgaNonAdapter                                     ///< Configure iGPU as non VGA adapter
+} GFX_IGPU_VGA_MODE;
+
+typedef enum {
+  excel992,
+  excel993
+} UMA_STEERING;
+
+/// User Options
+typedef enum {
+  OptionDisabled,                                       ///< Disabled
+  OptionEnabled                                         ///< Enabled
+} CONTROL_OPTION;
+
+/// GFX enable Policy
+typedef enum {
+  GmcPowerGatingDisabled,                               ///< Disable Power gating
+  GmcPowerGatingStutterOnly,                            ///< GMC Stutter Only mode
+  GmcPowerGatingWidthStutter                            ///< GMC Power gating with Stutter mode
+} GMC_POWER_GATING;
+
+/// Internal GFX mode
+typedef enum {
+  GfxControllerLegacyBridgeMode,                        ///< APC bridge Legacy mode
+  GfxControllerPcieEndpointMode,                        ///< IGFX PCIE Bus 0, Device 1
+} GFX_CONTROLLER_MODE;
+
+/// Graphics Platform Configuration
+typedef struct {
+  UINT32                       StdHeader;                ///< Standard Header TODO: Used to be PVOID
+  PCI_ADDR                    GfxPciAddress;            ///< Graphics PCI Address
+  UMA_INFO                    UmaInfo;                  ///< UMA Information
+  UINT32                      GmmBase;                  ///< GMM Base
+  UINT8                       GnbHdAudio;               ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                        ///< essentially it enables function 1 of graphics device.
+                                                        ///< @li 0 = HD Audio disable
+                                                        ///< @li 1 = HD Audio enable
+  UINT8                       AbmSupport;               ///< Automatic adjust LVDS/eDP Back light level support.It is
+                                                        ///< characteristic specific to display panel which used by platform design.
+                                                        ///< @li 0 = ABM support disabled
+                                                        ///< @li 1 = ABM support enabled
+  UINT8                       DynamicRefreshRate;       ///< Adjust refresh rate on LVDS/eDP.
+  UINT16                      LcdBackLightControl;      ///< The PWM frequency to LCD backlight control.
+                                                        ///< If equal to 0 backlight not controlled by iGPU.
+  UINT32                      AmdPlatformType;          ///< Platform type
+  UMA_STEERING                UmaSteering;              ///< UMA Steering
+  GFX_IGPU_VGA_MODE           iGpuVgaMode;              ///< iGPU VGA mode
+  BOOLEAN                     GmcClockGating;           ///< Clock gating
+  BOOLEAN                     GmcLockRegisters;         ///< GmcLock Registers
+  BOOLEAN                     GfxFusedOff;              ///< Record if GFX is fused off.
+  GMC_POWER_GATING            GmcPowerGating;           ///< Gmc Power Gating.
+  UINT8                       Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID
+  GFX_CONTROLLER_MODE         GfxControllerMode;        ///< Gfx controller mode
+  UINT16                      LvdsSpreadSpectrum;       ///< Spread spectrum value in 0.01 %
+  UINT16                      LvdsSpreadSpectrumRate;   ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+  UINT8                       LvdsPowerOnSeqDigonToDe;    ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqDeToVaryBl;   ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqDeToDigon;    ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqVaryBlToDe;   ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing.
+  UINT8                       LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing.
+  UINT16                      LvdsMaxPixelClockFreq;      ///< The maximum pixel clock frequency supported.
+  UINT32                      LcdBitDepthControlValue;    ///< The LCD bit depth control settings.
+  UINT8                       Lvds24bbpPanelMode;         ///< The LVDS 24 BBP mode.
+  LVDS_MISC_CONTROL           LvdsMiscControl;            ///< THe LVDS swap/Hsync/Vsync/BLON/Volt-overwrite control
+  GFX_CARD_CARD_INFO          GfxDiscreteCardInfo;        ///< Discrete GFX card info
+  UINT16                      PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
+  BOOLEAN                     GnbRemoteDisplaySupport;    ///< Wireless Display Enable
+  UINT8                       gfxplmcfg0 ;
+  DISPLAY_MISC_CONTROL        DisplayMiscControl;         ///< The Display misc control
+} GFX_PLATFORM_CONFIG;
+
+
+typedef UINT32 ULONG;
+typedef UINT16 USHORT;
+typedef UINT8  UCHAR;
+
+/// Driver interface header structure
+typedef struct _ATOM_COMMON_TABLE_HEADER {
+  USHORT                      usStructureSize;             ///< Structure size
+  UCHAR                       ucTableFormatRevision;       ///< Format revision number
+  UCHAR                       ucTableContentRevision;      ///< Contents revision number
+} ATOM_COMMON_TABLE_HEADER;
+
+/// Link ping mapping for DP/eDP/LVDS
+typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING {
+  UCHAR ucDP_Lane0_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDP_Lane1_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDP_Lane2_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDP_Lane3_Source  :2;                      ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+} ATOM_DP_CONN_CHANNEL_MAPPING;
+
+/// Link ping mapping for DVI/HDMI
+typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING {
+  UCHAR ucDVI_DATA2_Source  :2;                     ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDVI_DATA1_Source  :2;                     ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDVI_DATA0_Source  :2;                     ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+  UCHAR ucDVI_CLK_Source    :2;                     ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
+} ATOM_DVI_CONN_CHANNEL_MAPPING;
+
+
+/// External Display Path
+typedef struct _EXT_DISPLAY_PATH {
+  USHORT                      usDeviceTag;          ///< A bit vector to show what devices are supported
+  USHORT                      usDeviceACPIEnum;     ///< 16bit device ACPI id.
+  USHORT                      usDeviceConnector;    ///< A physical connector for displays to plug in, using object connector definitions
+  UCHAR                       ucExtAUXDDCLutIndex;  ///< An index into external AUX/DDC channel LUT
+  UCHAR                       ucExtHPDPINLutIndex;  ///< An index into external HPD pin LUT
+  USHORT                      usExtEncoderObjId;    ///< external encoder object id
+  union {                                           ///< Lane mapping
+    UCHAR                     ucChannelMapping;     ///< lane mapping on connector (ucChannelMapping=0 use default)
+    ATOM_DP_CONN_CHANNEL_MAPPING  asDPMapping;      ///< lane mapping on connector (ucChannelMapping=0 use default)
+    ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;     ///< lane mapping on connector (ucChannelMapping=0 use default)
+  } ChannelMapping;
+  UCHAR                       ucChPNInvert;         ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted
+  USHORT                      usCaps;               ///< Capabilities IF BIT[0] == 1, downgrade phy link to DP1.1
+  USHORT                      usReserved;           ///< Reserved
+} EXT_DISPLAY_PATH;
+
+/// External Display Connection Information
+typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO {
+  ATOM_COMMON_TABLE_HEADER    sHeader;              ///< Standard Header
+  UCHAR                       ucGuid [16];          ///< Guid
+  EXT_DISPLAY_PATH            sPath[7];             ///< External Display Path
+  UCHAR                       ucChecksum;           ///< Checksum
+  UCHAR                       uc3DStereoPinId;      ///< 3D Stereo Pin ID
+  UCHAR                       ucRemoteDisplayConfig;   ///< Bit0=1:Enable Wireless Display through APU VCE HW function
+  UCHAR                       uceDPToLVDSRxId;      ///< 3rd party eDP to LVDS translator chip presented. 0:no, 1:chip without AMD SW init, 2:Realtek tansaltor which require AMD SW init
+  UCHAR                       Reserved [4];         ///< Reserved
+} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
+
+/// Displclk to VID relation table
+typedef struct _ATOM_CLK_VOLT_CAPABILITY {
+  ULONG                       ulVoltageIndex;       ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
+  ULONG                       ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz
+} ATOM_CLK_VOLT_CAPABILITY;
+
+/// Available Sclk table
+typedef struct _ATOM_AVAILABLE_SCLK_LIST {
+  ULONG                        ulSupportedSCLK;     ///< Maximum clock supported with specified voltage index,  unit in 10kHz
+  USHORT                       usVoltageIndex;      ///< The Voltage Index indicated by FUSE for specified SCLK
+  USHORT                       usVoltageID;         ///< The Voltage ID indicated by FUSE for specified SCLK
+} ATOM_AVAILABLE_SCLK_LIST;
+
+/// Integrate System Info Table is used for Llano/Ontario APU
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 {
+  ATOM_COMMON_TABLE_HEADER    sHeader;                       ///< Standard Header
+  ULONG                       ulBootUpEngineClock;           ///< VBIOS bootup Engine clock frequency, in 10kHz unit.
+  ULONG                       excel994;
+  ULONG                       ulBootUpUMAClock;              ///< System memory boot up clock frequency in 10Khz unit.
+  ATOM_CLK_VOLT_CAPABILITY    sDISPCLK_Voltage[4];           ///< Report Display clock voltage requirement.
+  ULONG                       ulBootUpReqDisplayVector;      /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects:
+                                                               * ATOM_DEVICE_CRT1_SUPPORT                  0x0001
+                                                               * ATOM_DEVICE_CRT2_SUPPORT                  0x0010
+                                                               * ATOM_DEVICE_DFP1_SUPPORT                  0x0008
+                                                               * ATOM_DEVICE_DFP6_SUPPORT                  0x0040
+                                                               * ATOM_DEVICE_DFP2_SUPPORT                  0x0080
+                                                               * ATOM_DEVICE_DFP3_SUPPORT                  0x0200
+                                                               * ATOM_DEVICE_DFP4_SUPPORT                  0x0400
+                                                               * ATOM_DEVICE_DFP5_SUPPORT                  0x0800
+                                                               * ATOM_DEVICE_LCD1_SUPPORT                  0x0002
+                                                               */
+  ULONG                       ulOtherDisplayMisc;            ///< Other display related flags, not defined yet.
+  ULONG                       ulGPUCapInfo;                  /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode.
+                                                               *  @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode
+                                                               *  @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable
+                                                               */
+  ULONG                       ulSB_MMIO_Base_Addr;           ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage.
+  USHORT                      usRequestedPWMFreqInHz;        ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled.
+  UCHAR                       ucHtcTmpLmt;                   ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt.
+  UCHAR                       ucHtcHystLmt;                  ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt.
+  ULONG                       ulMinEngineClock;              ///< Min SCLK
+  ULONG                       ulSystemConfig;                /**< System configuration
+                                                               *  @li BIT[0] - 0: PCIE Power Gating Disabled, 1: PCIE Power Gating Enabled.
+                                                               *  @li BIT[1] - 0: DDR-DLL shut-down feature disabled, 1: DDR-DLL shut-down feature enabled.
+                                                               *  @li BIT[2] - 0: DDR-PLL Power down feature disabled, 1: DDR-PLL Power down feature enabled.
+                                                               */
+  ULONG                       ulCPUCapInfo;                  ///< TBD
+  USHORT                      usNBP0Voltage;                 ///< VID for voltage on NB P0 State
+  USHORT                      usNBP1Voltage;                 ///< VID for voltage on NB P1 State
+  USHORT                      usBootUpNBVoltage;             ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement.
+  USHORT                      usExtDispConnInfoOffset;       ///< Offset to sExtDispConnInfo inside the structure
+  USHORT                      usPanelRefreshRateRange;       /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set.
+                                                               * SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
+                                                               * SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
+                                                               * SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
+                                                               * SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
+                                                               */
+  UCHAR                       ucMemoryType;                  ///< Memory type (3 for DDR3)
+  UCHAR                       ucUMAChannelNumber;            ///< System memory channel numbers.
+  ULONG                       ulCSR_M3_ARB_CNTL_DEFAULT[10]; ///< Arrays with values for CSR M3 arbiter for default.
+  ULONG                       ulCSR_M3_ARB_CNTL_UVD[10];     ///< Arrays with values for CSR M3 arbiter for UVD playback.
+  ULONG                       ulCSR_M3_ARB_CNTL_FS3D[10];    ///< Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
+  ATOM_AVAILABLE_SCLK_LIST    sAvail_SCLK[5];                ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
+  ULONG                       ulGMCRestoreResetTime;         ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
+  ULONG                       ulMinimumNClk;                 ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
+  ULONG                       ulIdleNClk;                    ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
+  ULONG                       ulDDR_DLL_PowerUpTime;         ///< DDR PHY DLL power up time. Unit in ns.
+  ULONG                       ulDDR_PLL_PowerUpTime;         ///< DDR PHY PLL power up time. Unit in ns
+  USHORT                      usPCIEClkSSPercentage;         ///< usPCIEClkSSPercentage
+  USHORT                      usPCIEClkSSType;               ///< usPCIEClkSSType
+  USHORT                      usLvdsSSPercentage;            ///< usLvdsSSPercentage
+  USHORT                      usLvdsSSpreadRateIn10Hz;       ///< usLvdsSSpreadRateIn10Hz
+  USHORT                      usHDMISSPercentage;            ///< usHDMISSPercentage
+  USHORT                      usHDMISSpreadRateIn10Hz;       ///< usHDMISSpreadRateIn10Hz
+  USHORT                      usDVISSPercentage;             ///< usDVISSPercentage
+  USHORT                      usDVISSpreadRateIn10Hz;        ///< usDVISSpreadRateIn10Hz
+  ULONG                       SclkDpmBoostMargin;            ///< SclkDpmBoostMargin
+  ULONG                       SclkDpmThrottleMargin;         ///< SclkDpmThrottleMargin
+  USHORT                      SclkDpmTdpLimitPG;             ///< SclkDpmTdpLimitPG
+  USHORT                      SclkDpmTdpLimitBoost;          ///< SclkDpmTdpLimitBoost
+  ULONG                       ulBoostEngineCLock;            ///< ulBoostEngineCLock
+  UCHAR                       ulBoostVid_2bit;               ///< ulBoostVid_2bit
+  UCHAR                       EnableBoost;                   ///< EnableBoost
+  USHORT                      GnbTdpLimit;                   ///< GnbTdpLimit
+  USHORT                      usMaxLVDSPclkFreqInSingleLink; ///< usMaxLVDSPclkFreqInSingleLink
+  UCHAR                       ucLvdsMisc;                    ///< ucLvdsMisc
+  UCHAR                       ucLVDSReserved;                ///< ucLVDSReserved
+  ULONG                       ulReserved3[15];               ///< Reserved
+  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;    ///< Display connector definition
+} ATOM_INTEGRATED_SYSTEM_INFO_V6;
+
+/// this Table is used for Llano/Ontario APU
+typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 {
+  ATOM_INTEGRATED_SYSTEM_INFO_V6    sIntegratedSysInfo;      ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
+  ULONG                             ulPowerplayTable[128];   ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
+} ATOM_FUSION_SYSTEM_INFO_V1;
+
+/// Integrated Info table
+/// Upgrade is followed by Trinity SBIOS/VBIOS & Driver interface Design Document VER 0.5
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 {
+  ATOM_COMMON_TABLE_HEADER    sHeader;                       ///< Standard Header
+  ULONG                       ulBootUpEngineClock;           ///< VBIOS bootup Engine clock frequency, in 10kHz unit.
+  ULONG                       ulDentistVCOFreq;              ///< Dentist VCO clock in 10kHz unit.
+  ULONG                       ulBootUpUMAClock;              ///< System memory boot up clock frequency in 10Khz unit.
+  ATOM_CLK_VOLT_CAPABILITY    sDISPCLK_Voltage[4];           ///< Report Display clock voltage requirement.
+  ULONG                       ulBootUpReqDisplayVector;      /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects:
+                                                               * ATOM_DEVICE_CRT1_SUPPORT                  0x0001
+                                                               * ATOM_DEVICE_CRT2_SUPPORT                  0x0010
+                                                               * ATOM_DEVICE_DFP1_SUPPORT                  0x0008
+                                                               * ATOM_DEVICE_DFP6_SUPPORT                  0x0040
+                                                               * ATOM_DEVICE_DFP2_SUPPORT                  0x0080
+                                                               * ATOM_DEVICE_DFP3_SUPPORT                  0x0200
+                                                               * ATOM_DEVICE_DFP4_SUPPORT                  0x0400
+                                                               * ATOM_DEVICE_DFP5_SUPPORT                  0x0800
+                                                               * ATOM_DEVICE_LCD1_SUPPORT                  0x0002
+                                                               */
+  ULONG                       ulOtherDisplayMisc;            ///< Other display related flags, not defined yet.
+  ULONG                       ulGPUCapInfo;                  /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode.
+                                                               *  @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode
+                                                               *  @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable
+                                                               */
+  ULONG                       ulSB_MMIO_Base_Addr;           ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage.
+  USHORT                      usRequestedPWMFreqInHz;        ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled.
+  UCHAR                       ucHtcTmpLmt;                   ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt.
+  UCHAR                       ucHtcHystLmt;                  ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt.
+  ULONG                       ulMinEngineClock;              ///< Min SCLK
+  ULONG                       ulSystemConfig;                ///< TBD
+  ULONG                       ulCPUCapInfo;                  ///< TBD
+  USHORT                      usNBP0Voltage;                 ///< VID for voltage on NB P0 State
+  USHORT                      usNBP1Voltage;                 ///< VID for voltage on NB P1 State
+  USHORT                      usBootUpNBVoltage;             ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement.
+  USHORT                      usExtDispConnInfoOffset;       ///< Offset to sExtDispConnInfo inside the structure
+  USHORT                      usPanelRefreshRateRange;       /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set.
+                                                               * SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
+                                                               * SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
+                                                               * SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
+                                                               * SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
+                                                               */
+  UCHAR                       ucMemoryType;                  ///< Memory type (3 for DDR3)
+  UCHAR                       ucUMAChannelNumber;            ///< System memory channel numbers.
+  UCHAR                       strVBIOSMsg[40];               ///< Allow customer to have its own VBIOS message
+  ULONG                       ulReserved[20];                ///<
+  ATOM_AVAILABLE_SCLK_LIST    sAvail_SCLK[5];                ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
+  ULONG                       ulGMCRestoreResetTime;         ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
+  ULONG                       ulMinimumNClk;                 ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
+  ULONG                       ulIdleNClk;                    ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
+  ULONG                       ulDDR_DLL_PowerUpTime;         ///< DDR PHY DLL power up time. Unit in ns.
+  ULONG                       ulDDR_PLL_PowerUpTime;         ///< DDR PHY PLL power up time. Unit in ns
+  USHORT                      usPCIEClkSSPercentage;         ///<
+  USHORT                      usPCIEClkSSType;               ///<
+  USHORT                      usLvdsSSPercentage;            ///<
+  USHORT                      usLvdsSSpreadRateIn10Hz;       ///<
+  USHORT                      usHDMISSPercentage;            ///<
+  USHORT                      usHDMISSpreadRateIn10Hz;       ///<
+  USHORT                      usDVISSPercentage;             ///<
+  USHORT                      usDVISSpreadRateIn10Hz;        ///<
+  ULONG                       SclkDpmBoostMargin;            ///<
+  ULONG                       SclkDpmThrottleMargin;         ///<
+  USHORT                      SclkDpmTdpLimitPG;             ///<
+  USHORT                      SclkDpmTdpLimitBoost;          ///<
+  ULONG                       ulBoostEngineCLock;            ///<
+  UCHAR                       ulBoostVid_2bit;               ///<
+  UCHAR                       EnableBoost;                   ///<
+  USHORT                      GnbTdpLimit;                   ///<
+  USHORT                      usMaxLVDSPclkFreqInSingleLink; ///<
+  UCHAR                       ucLvdsMisc;                    ///<
+  UCHAR                       gnbgfxline429 ;        ///<
+  UCHAR                       ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///<
+  UCHAR                       ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;    ///<
+  UCHAR                       ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;   ///<
+  UCHAR                       ucLVDSPwrOffSeqDEtoDIGON_in4Ms;     ///<
+  UCHAR                       ucLVDSOffToOnDelay_in4Ms;           ///<
+  UCHAR                       ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;  ///<
+  UCHAR                       ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///<
+  UCHAR                       ucLVDSReserved1;                    ///<
+  ULONG                       ulLCDBitDepthControlVal;            ///<
+  ULONG                       ulNbpStateMemclkFreq[4];            ///<
+  USHORT                      usNBP2Voltage;                      ///<
+  USHORT                      usNBP3Voltage;                      ///<
+  ULONG                       ulNbpStateNClkFreq[4];              ///<
+  UCHAR                       ucNBDPMEnable;                      ///<
+  UCHAR                       ucReserved[3];                      ///<
+  UCHAR                       ucDPMState0VclkFid;                 ///<
+  UCHAR                       ucDPMState0DclkFid;                 ///<
+  UCHAR                       ucDPMState1VclkFid;                 ///<
+  UCHAR                       ucDPMState1DclkFid;                 ///<
+  UCHAR                       ucDPMState2VclkFid;                 ///<
+  UCHAR                       ucDPMState2DclkFid;                 ///<
+  UCHAR                       ucDPMState3VclkFid;                 ///<
+  UCHAR                       ucDPMState3DclkFid;                 ///<
+  ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;         ///<
+} ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
+
+/// this Table is used for Llano/Ontario APU
+typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 {
+  ATOM_INTEGRATED_SYSTEM_INFO_V1_7  sIntegratedSysInfo;      ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_7 definition.
+  ULONG                             ulPowerplayTable[128];   ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
+} ATOM_FUSION_SYSTEM_INFO_V2;
+
+#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0)
+
+/// Define configuration values for ulGPUCapInfo
+// BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode.
+#define GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE      0x00ul
+#define GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE       0x01ul
+
+// BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode
+#define GPUCAPINFO_DP_MODE_USE_CASCADE_PLL_MODE        0x00ul
+#define GPUCAPINFO_DP_USE_SINGLE_PLL_MODE              0x02ul
+
+// BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable
+#define GPUCAPINFO_AUX_HW_MODE_DETECTION_ENABLE        0x00ul
+#define GPUCAPINFO_AUX_HW_MODE_DETECTION_DISABLE       0x08ul
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h
new file mode 100644
index 0000000000..0957f9d194
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbGfxFamServices.h
@@ -0,0 +1,108 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe family specific services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBGFXFAMSERVICES_H_
+#define _GNBGFXFAMSERVICES_H_
+
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbPcie.h"
+
+
+AGESA_STATUS
+GfxFmMapEngineToDisplayPath (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+VOID
+GfxFmSetIdleVoltageMode (
+  IN      GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+VOID
+GfxFmDisableController (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h
new file mode 100644
index 0000000000..2a3d02414c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbIommu.h
@@ -0,0 +1,222 @@
+/**
+ * @file
+ *
+ * Misc common definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBIOMMU_H_
+#define _GNBIOMMU_H_
+
+#pragma pack (push, 1)
+
+
+/// IVRS block
+typedef enum {
+  IvrsIvhdBlock               = 0x10,       ///< I/O Virtualization Hardware Definition Block
+  IvrsIvmdBlock               = 0x20,       ///< I/O Virtualization Memory Definition Block for all peripherals
+  IvrsIvmdBlockSingle         = 0x21,       ///< IVMD block for specified peripheral
+  IvrsIvmdBlockRange          = 0x22,       ///< IVMD block for peripheral range
+  IvrsIvhdrBlock              = 0x40,       ///< IVHDR (Relative) block
+  IvrsIvmdrBlock              = 0x50,       ///< IVMDR (Relative) block for all peripherals
+  IvrsIvmdrBlockSingle        = 0x51        ///< IVMDR block for last IVHDR
+} IVRS_BLOCK_TYPE;
+
+#define DEVICE_ID(PciAddress) (UINT16) (((PciAddress).Address.Bus << 8) | ((PciAddress).Address.Device << 3) | (PciAddress).Address.Function)
+
+/// IVHD entry types
+typedef enum {
+  IvhdEntryPadding            =  0,         ///< Table padding
+  IvhdEntrySelect             =  2,         ///< Select
+  IvhdEntryStartRange         =  3,         ///< Start Range
+  IvhdEntryEndRange           =  4,         ///< End Range
+  IvhdEntryAliasSelect        =  66,        ///< Alias select
+  IvhdEntryAliasStartRange    =  67,        ///< Alias start range
+  IvhdEntryExtendedSelect     =  70,        ///< Extended select
+  IvhdEntryExtendedStartRange =  71,        ///< Extended Start range
+  IvhdEntrySpecialDevice      =  72         ///< Special device
+} IVHD_ENTRY_TYPE;
+
+/// Special device variety
+typedef enum {
+  IvhdSpecialDeviceIoapic     = 0x1,        ///< IOAPIC
+  IvhdSpecialDeviceHpet       = 0x2         ///< HPET
+} IVHD_SPECIAL_DEVICE;
+
+
+#define IVHD_FLAG_COHERENT          BIT5
+#define IVHD_FLAG_IOTLBSUP          BIT4
+#define IVHD_FLAG_ISOC              BIT3
+#define IVHD_FLAG_RESPASSPW         BIT2
+#define IVHD_FLAG_PASSPW            BIT1
+#define IVHD_FLAG_PPRSUB            BIT7
+#define IVHD_FLAG_PREFSUP           BIT6
+
+#define IVHD_EFR_XTSUP_OFFSET       0
+#define IVHD_EFR_NXSUP_OFFSET       1
+#define IVHD_EFR_GTSUP_OFFSET       2
+#define IVHD_EFR_GLXSUP_OFFSET      3
+#define IVHD_EFR_IASUP_OFFSET       5
+#define IVHD_EFR_GASUP_OFFSET       6
+#define IVHD_EFR_HESUP_OFFSET       7
+#define IVHD_EFR_PASMAX_OFFSET      8
+#define IVHD_EFR_PNCOUNTERS_OFFSET  13
+#define IVHD_EFR_PNBANKS_OFFSET     17
+#define IVHD_EFR_MSINUMPPR_OFFSET   23
+#define IVHD_EFR_GATS_OFFSET        28
+#define IVHD_EFR_HATS_OFFSET        30
+
+#define IVINFO_HTATSRESV_MASK       0x00400000ul
+#define IVINFO_VASIZE_MASK          0x003F8000ul
+#define IVINFO_PASIZE_MASK          0x00007F00ul
+#define IVINFO_GASIZE_MASK          0x000000E0ul
+
+#define IVHD_INFO_MSINUM_OFFSET     0
+#define IVHD_INFO_UNITID_OFFSET     8
+
+#define IVMD_FLAG_EXCLUSION_RANGE   BIT3
+#define IVMD_FLAG_IW                BIT2
+#define IVMD_FLAG_IR                BIT1
+#define IVMD_FLAG_UNITY             BIT0
+
+/// IVRS header
+typedef struct {
+  UINT8   Sign[4];           ///< Signature
+  UINT32  TableLength;       ///< Table Length
+  UINT8   Revision;          ///< Revision
+  UINT8   Checksum;          ///< Checksum
+  UINT8   OemId[6];          ///< OEM ID
+  UINT8   OemTableId[8];     ///< OEM Tabled ID
+  UINT32  OemRev;            ///< OEM Revision
+  UINT8   CreatorId[4];      ///< Creator ID
+  UINT32  CreatorRev;        ///< Creator Revision
+  UINT32  IvInfo;            ///< IvInfo
+  UINT64  Reserved;          ///< Reserved
+} IOMMU_IVRS_HEADER;
+
+/// IVRS IVHD Entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT8   Flags;              ///< Flags
+  UINT16  Length;             ///< Length
+  UINT16  DeviceId;           ///< DeviceId
+  UINT16  CapabilityOffset;   ///< CapabilityOffset
+  UINT64  BaseAddress;        ///< BaseAddress
+  UINT16  PciSegment;         ///< Pci segment
+  UINT16  IommuInfo;          ///< IOMMU info
+  UINT32  IommuEfr;           ///< reserved
+} IVRS_IVHD_ENTRY;
+
+/// IVHD generic entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  DeviceId;           ///< Device id
+  UINT8   DataSetting;        ///< Data settings
+} IVHD_GENERIC_ENTRY;
+
+///IVHD alias entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  DeviceId;           ///< Device id
+  UINT8   DataSetting;        ///< Data settings
+  UINT8   Reserved;           ///< Reserved
+  UINT16  AliasDeviceId;      ///< Alias device id
+  UINT8   Reserved2;          ///< Reserved
+} IVHD_ALIAS_ENTRY;
+
+///IVHD extended entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  DeviceId;           ///< Device id
+  UINT8   DataSetting;        ///< Data settings
+  UINT32  ExtSetting;         ///< Extended settings
+} IVHD_EXT_ENTRY;
+
+/// IVHD special entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT16  Reserved;           ///< Reserved
+  UINT8   DataSetting;        ///< Data settings
+  UINT8   Handle;             ///< Handle
+  UINT16  AliasDeviceId;      ///< Alis device id
+  UINT8   Variety;            ///< Variety
+} IVHD_SPECIAL_ENTRY;
+
+/// IVRS IVMD Entry
+typedef struct {
+  UINT8   Type;               ///< Type
+  UINT8   Flags;              ///< Flags
+  UINT16  Length;             ///< Length
+  UINT16  DeviceId;           ///< DeviceId
+  UINT16  AuxiliaryData;      ///< Auxiliary data
+  UINT64  Reserved;           ///< Reserved (0000_0000_0000_0000)
+  UINT64  BlockStart;         ///< IVMD start address
+  UINT64  BlockLength;        ///< IVMD memory block length
+} IVRS_IVMD_ENTRY;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
new file mode 100644
index 0000000000..1985beb3a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.c
@@ -0,0 +1,132 @@
+/* $NoKeywords:$ */
+ /**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "GeneralServices.h"
+#include  "cpuFamilyTranslation.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define  FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DIspathc feature tanle
+ *
+ *
+ */
+
+AGESA_STATUS
+GnbLibDispatchFeatures (
+  IN      OPTION_GNB_CONFIGURATION  *ConfigTable,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  AGESA_STATUS    Status;
+  AGESA_STATUS    AgesaStatus;
+  CPU_LOGICAL_ID  LogicalId;
+
+  AgesaStatus = AGESA_SUCCESS;
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  while (ConfigTable->GnbFeature != NULL) {
+    if ((ConfigTable->Type & LogicalId.Family) != 0) {
+      Status = ConfigTable->GnbFeature (StdHeader);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+    ConfigTable++;
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h
new file mode 100644
index 0000000000..dfbbc9e708
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbLibFeatures.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBLIBFEATURES_H_
+#define _GNBLIBFEATURES_H_
+
+
+AGESA_STATUS
+GnbLibDispatchFeatures (
+  IN      OPTION_GNB_CONFIGURATION  *ConfigTable,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
new file mode 100644
index 0000000000..fbb8d3b6a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h
@@ -0,0 +1,418 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe component definitions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+
+*
+*/
+
+#ifndef _GNBPCIE_H_
+#define _GNBPCIE_H_
+
+#pragma pack (push, 1)
+
+#define MAX_NUMBER_OF_COMPLEXES                4
+
+#define DESCRIPTOR_TERMINATE_GNB               0x40000000ull
+#define DESCRIPTOR_TERMINATE_TOPOLOGY          0x20000000ull
+#define DESCRIPTOR_ALLOCATED                   0x10000000ull
+#define DESCRIPTOR_VIRTUAL                     0x08000000ull
+#define DESCRIPTOR_PLATFORM                    0x04000000ull
+#define DESCRIPTOR_COMPLEX                     0x02000000ull
+#define DESCRIPTOR_SILICON                     0x01000000ull
+#define DESCRIPTOR_PCIE_WRAPPER                0x00800000ull
+#define DESCRIPTOR_DDI_WRAPPER                 0x00400000ull
+#define DESCRIPTOR_PCIE_ENGINE                 0x00200000ull
+#define DESCRIPTOR_DDI_ENGINE                  0x00100000ull
+
+#define DESCRIPTOR_ALL_WRAPPERS                (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER)
+#define DESCRIPTOR_ALL_ENGINES                 (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
+
+#define DESCRIPTOR_ALL_TYPES                   (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM)
+
+#define UNUSED_LANE_ID                         128
+//#define PCIE_LINK_RECEIVER_DETECTION_POOLING   (60 * 1000)
+//#define PCIE_LINK_L0_POOLING                   (60 * 1000)
+//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME       (2  * 1000)
+//#define PCIE_LINK_RESET_TO_TRAINING_TIME       (2  * 1000)
+
+// Get lowest PHY lane on engine
+#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0)
+// Get highest PHY lane on engine
+#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0)
+// Get number of lanes on wrapper
+#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0)
+// Check if virtual descriptor
+#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE)
+// Check if it is allocated descriptor
+#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE)
+// Check if it is last descriptor in list
+#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : TRUE)
+// Check if descriptor a PCIe engine
+#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE)
+// Check if descriptor a DDI engine
+#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE)
+// Check if descriptor a DDI wrapper
+#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE)
+// Check if descriptor a PCIe wrapper
+#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE)
+// Check if descriptor a PCIe wrapper
+#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1)) : NULL)
+
+#define LANE_TYPE_PCIE_CORE_CONFIG              0x00000001ul
+#define LANE_TYPE_PCIE_CORE_ALLOC               0x00000002ul
+#define LANE_TYPE_PCIE_CORE_ACTIVE              0x00000004ul
+#define LANE_TYPE_PCIE_SB_CORE_CONFIG           0x00000008ul
+#define LANE_TYPE_PCIE_CORE_HOTPLUG             0x00000010ul
+#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE        0x00000020ul
+#define LANE_TYPE_PCIE_PHY                      0x00000100ul
+#define LANE_TYPE_PCIE_PHY_NATIVE               0x00000200ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE        0x00000400ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG       0x00000800ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE  0x00001000ul
+#define LANE_TYPE_DDI_PHY                       0x00010000ul
+#define LANE_TYPE_DDI_PHY_NATIVE                0x00020000ul
+#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE         0x00040000ul
+#define LANE_TYPE_PHY_NATIVE_ALL                0x00100000ul
+#define LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL    0x00200000ul
+#define LANE_TYPE_CORE_ALL                      LANE_TYPE_PHY_NATIVE_ALL
+#define LANE_TYPE_ALL                           LANE_TYPE_PHY_NATIVE_ALL
+
+#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \
+                              LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \
+                              LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \
+                              LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \
+                              LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \
+                              LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)
+
+#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE)
+
+
+#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY          0x00000001ull
+#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY   0x00000002ull
+#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL          0x00000004ull
+#define INIT_STATUS_PCIE_TRAINING_SUCCESS            0x00000008ull
+#define INIT_STATUS_PCIE_EP_NOT_PRESENT              0x00000010ull
+#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE          0x00000020ull
+#define INIT_STATUS_DDI_ACTIVE                       0x00000040ull
+#define INIT_STATUS_ALLOCATED                        0x00000080ull
+
+#define PCIE_PORT_GEN_CAP_BOOT                       0x00000001ul
+#define PCIE_PORT_GEN_CAP_MAX                        0x00000002ul
+#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS                0x00000010ul
+#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS            0x00000011ul
+#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS            0x00000012ul
+
+#define PCIE_POWERGATING_SKIP_CORE                   0x00000001ul
+#define PCIE_POWERGATING_SKIP_PHY                    0x00000002ul
+
+/// PCIe Link Training State
+typedef enum {
+  PcieTrainingStandard,                                ///< Standard training algorithm. Training contained to AmdEarlyInit.
+                                                       ///< PCIe device accessible after AmdEarlyInit complete
+  PcieTrainingDistributed,                             ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore
+                                                       ///< PCIe device accessible after AmdPostInit complete.
+                                                       ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots.
+} PCIE_TRAINING_ALGORITHM;
+
+/// PCIe Link Training State
+typedef enum {
+  LinkStateResetAssert,                                 ///< Assert port GPIO reset
+  LinkStateResetDuration,                               ///< Timeout for reset duration
+  LinkStateResetExit,                                   ///< Deassert port GPIO reset
+  LinkTrainingResetTimeout,                             ///< Port GPIO reset timeout
+  LinkStateReleaseTraining,                             ///< Release link training
+  LinkStateDetectPresence,                              ///< Detect device presence
+  LinkStateDetecting,                                   ///< Detect link training.
+  LinkStateBrokenLane,                                  ///< Check and handle broken lane
+  LinkStateGen2Fail,                                    ///< Check and handle device that fail training if GEN2 capability advertised
+  LinkStateL0,                                          ///< Device trained to L0
+  LinkStateVcoNegotiation,                              ///< Check VCO negotiation complete
+  LinkStateRetrain,                                     ///< Force retrain link.
+  LinkStateTrainingFail,                                ///< Link training fail
+  LinkStateTrainingSuccess,                             ///< Link training success
+  LinkStateGfxWorkaround,                               ///< GFX workaround
+  LinkStateCompliance,                                  ///< Link in compliance mode
+  LinkStateDeviceNotPresent,                            ///< Link is not connected
+  LinkStateTrainingCompleted                            ///< Link training completed
+} PCIE_LINK_TRAINING_STATE;
+
+/// PCIe Port Visibility
+typedef enum {
+  UnhidePorts,                                          ///< Command to unhide port
+  HidePorts,                                            ///< Command to hide unused ports
+} PCIE_PORT_VISIBILITY;
+
+
+/// Table Register Entry
+typedef struct {
+  UINT16          Reg;                                  ///< Address
+  UINT32          Mask;                                 ///< Mask
+  UINT32          Data;                                 ///< Data
+} PCIE_PORT_REGISTER_ENTRY;
+
+/// Table Register Entry
+typedef struct {
+  PCIE_PORT_REGISTER_ENTRY  *Table;                     ///< Table
+  UINT32                    Length;                     ///< Length
+} PCIE_PORT_REGISTER_TABLE_HEADER;
+
+/// Table Register Entry
+typedef struct {
+  UINT32          Reg;                                  ///< Address
+  UINT32          Mask;                                 ///< Mask
+  UINT32          Data;                                 ///< Data
+} PCIE_HOST_REGISTER_ENTRY;
+
+/// Table Register Entry
+typedef struct {
+  PCIE_HOST_REGISTER_ENTRY  *Table;                     ///< Table
+  UINT32                    Length;                     ///< Length
+} PCIE_HOST_REGISTER_TABLE_HEADER;
+
+///Link ASPM info
+typedef struct {
+  PCI_ADDR        DownstreamPort;                       ///< PCI address of downstream port
+  PCIE_ASPM_TYPE  DownstreamAspm;                       ///< Downstream Device Aspm
+  PCI_ADDR        UpstreamPort;                         ///< PCI address of upstream port
+  PCIE_ASPM_TYPE  UpstreamAspm;                         ///< Upstream Device Capability
+  PCIE_ASPM_TYPE  RequestedAspm;                        ///< Requested ASPM
+} PCIe_LINK_ASPM;
+
+///PCIe ASPM Latency Information
+typedef struct {
+  UINT8  MaxL0sExitLatency;                             ///< Max L0s exit latency in us
+  UINT8  MaxL1ExitLatency;                              ///< Max L1 exit latency in us
+} PCIe_ASPM_LATENCY_INFO;
+
+/// PCI address association
+typedef struct {
+  UINT8 NewDeviceAddress;                                ///< New PCI address (Device,Fucntion)
+  UINT8 NativeDeviceAddress;                             ///< Native PCI address (Device,Fucntion)
+} PCI_ADDR_LIST;
+
+/// The return status for GFX Card Workaround.
+typedef enum {
+  GFX_WORKAROUND_DEVICE_NOT_READY,                       ///< GFX Workaround device is not ready.
+  GFX_WORKAROUND_RESET_DEVICE,                           ///< GFX Workaround device need reset.
+  GFX_WORKAROUND_SUCCESS                                 ///< The service completed normally.
+} GFX_WORKAROUND_STATUS;
+
+/// GFX workaround control
+typedef enum {
+  GfxWorkaroundDisable,                                   ///< GFX Workaround disabled
+  GfxWorkaroundEnable                                     ///< GFX Workaround enabled
+} GFX_WORKAROUND_CONTROL;
+
+/// PIF lane power state
+typedef enum {
+  PifPowerStateL0,                                        ///<
+  PifPowerStateLS1,                                       ///<
+  PifPowerStateLS2,                                       ///<
+  PifPowerStateOff = 0x7,                                 ///<
+} PCIE_PIF_POWER_STATE;
+
+/// PIF lane power control
+typedef enum {
+  PowerDownPifs,                                          ///<
+  PowerUpPifs                                             ///<
+} PCIE_PIF_POWER_CONTROL;
+
+///PLL rumup time
+typedef enum {
+  NormalRampup,                                           ///<
+  LongRampup,                                             ///<
+} PCIE_PLL_RAMPUP_TIME;
+
+typedef UINT16 PCIe_ENGINE_INIT_STATUS;
+
+/// PCIe port configuration info
+typedef struct {
+  PCIe_PORT_DATA          PortData;                     ///< Port data
+  UINT8                   StartCoreLane;                ///< Start Core Lane
+  UINT8                   EndCoreLane;                  ///< End Core lane
+  UINT8                   NativeDevNumber :5;           ///< Native PCI device number of the port
+  UINT8                   NativeFunNumber :3;           ///< Native PCI function number of the port
+  UINT8                   CoreId :4;                    ///< PCIe core ID
+  UINT8                   PortId :4;                    ///< Port ID on wrapper
+  PCI_ADDR                Address;                      ///< PCI address of the port
+  UINT8                   State;                        ///< Training state
+  UINT8                   PcieBridgeId:4;               ///< IOC PCIe bridge ID
+  UINT16                  UnitId:12;                    ///< Port start unit ID
+  UINT16                  NumberOfUnitId:4;             ///< Def number of unitIDs assigned to port
+  UINT8                   GfxWrkRetryCount:4;           ///< Number of retry for GFX workaround
+  UINT32                  TimeStamp;                    ///< Time stamp used to during training process
+  UINT8                   LogicalBridgeId;              ///< Logical Bridge ID
+} PCIe_PORT_CONFIG;
+
+///Descriptor header
+typedef struct {
+  UINT32                  DescriptorFlags;              ///< Descriptor flags
+  UINT16                  Parent;                       ///< Offset of parent descriptor
+  UINT16                  Peer;                         ///< Offset of the peer descriptor
+  UINT16                  Child;                        ///< Offset of the list of child descriptors
+} PCIe_DESCRIPTOR_HEADER;
+
+/// DDI (Digital Display Interface) configuration info
+typedef struct {
+  PCIe_DDI_DATA           DdiData;                      ///< DDI Data
+  UINT8                   DisplayPriorityIndex;         ///< Display priority index
+  UINT8                   ConnectorId;                  ///< Connector id determined by enumeration
+  UINT8                   DisplayDeviceId;              ///< Display device id determined by enumeration
+} PCIe_DDI_CONFIG;
+
+
+/// Engine configuration data
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descripto header
+  PCIe_ENGINE_DATA        EngineData;                   ///< Engine Data
+  PCIe_ENGINE_INIT_STATUS InitStatus;                   ///< Initialization Status
+  UINT8                   Scratch;                      ///< Scratch pad
+  union {
+    PCIe_PORT_CONFIG      Port;                         ///< PCIe port configuration data
+    PCIe_DDI_CONFIG       Ddi;                          ///< DDI configuration data
+  } Type;
+} PCIe_ENGINE_CONFIG;
+
+/// Wrapper configuration data
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT8                   WrapId;                       ///< Wrapper ID
+  UINT8                   NumberOfPIFs;                 ///< Number of PIFs on wrapper
+  UINT8                   StartPhyLane;                 ///< Start PHY Lane
+  UINT8                   EndPhyLane;                   ///< End PHY Lane
+  UINT8                   StartPcieCoreId:4;            ///< Start PCIe Core ID
+  UINT8                   EndPcieCoreId:4;              ///< End PCIe Core ID
+  UINT8                   NumberOfLanes;                ///< Number of lanes
+  struct {
+    UINT8                 PowerOffUnusedLanes:1;        ///< Power Off unused lanes
+    UINT8                 PowerOffUnusedPlls:1;         ///< Power Off unused Plls
+    UINT8                 ClkGating:1;                  ///< TXCLK gating
+    UINT8                 LclkGating:1;                 ///< LCLK gating
+    UINT8                 TxclkGatingPllPowerDown:1;    ///< TXCLK clock gating PLL power down
+    UINT8                 PllOffInL1:1;                 ///< PLL off in L1
+    UINT8                 AccessEncoding:1;             ///< Reg access encoding
+  } Features;
+  UINT8                   MasterPll;                    ///< Bitmap of master PLL
+} PCIe_WRAPPER_CONFIG;
+
+
+/// Silicon configuration data
+typedef struct  {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT8                   SiliconId;                    ///< Gnb silicon(module) ID
+  UINT8                   NodeId;                       ///< Node to which GNB connected
+  UINT8                   LinkId;                       ///< Link to which GNB connected if LinkId > 3 GNB connected to sublink = LinkId - 4
+  PCI_ADDR                Address;                      ///< PCI address of GNB host bridge
+} PCIe_SILICON_CONFIG;
+
+typedef PCIe_SILICON_CONFIG GNB_HANDLE;
+
+/// Complex configuration data
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT8                   SocketId;                     ///< Processor socket ID
+} PCIe_COMPLEX_CONFIG;
+
+/// PCIe platform configuration info
+typedef struct {
+  PCIe_DESCRIPTOR_HEADER  Header;                       ///< Descrptor Header
+  UINT32                  StdHeader;                    ///< Standard configuration header TODO:Used to be PVOID
+  UINT32                  LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+  UINT32                  LinkL0Pooling;                ///< Pooling for link to get to L0 in us
+  UINT32                  LinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
+  UINT32                  LinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us                                                      ///
+  UINT8                   GfxCardWorkaround;            ///< GFX Card Workaround
+  UINT8                   PsppPolicy;                   ///< PSPP policy
+  UINT8                   TrainingExitState;            ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE)
+  UINT8                   TrainingAlgorithm;            ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
+  PCIe_COMPLEX_CONFIG     ComplexList[MAX_NUMBER_OF_COMPLEXES];  ///< Complex
+} PCIe_PLATFORM_CONFIG;
+
+/// PCIe Engine Description
+typedef struct {
+  UINT32                  Flags;                        /**< Descriptor flags
+                                                         * @li @b Bit31 - last descriptor on wrapper
+                                                         * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
+                                                         */
+  PCIe_ENGINE_DATA        EngineData;                   ///< Engine Data
+} PCIe_ENGINE_DESCRIPTOR;
+
+/// PCIe Lane allocation descriptor
+typedef struct {
+  UINT32                  Flags;                        ///< Flags
+  UINT8                   WrapId;                       ///< Wrapper ID
+  UINT8                   EngineType;                   ///< Engine Type
+  UINT8                   NumberOfEngines;              ///< Number of engines to configure
+  UINT8                   NumberOfConfigurations;       ///< Number of possible configurations
+  UINT8                   *ConfigTable;                 ///< Pointer to config table
+} PCIe_LANE_ALLOC_DESCRIPTOR;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h
new file mode 100644
index 0000000000..5942a71df6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcieFamServices.h
@@ -0,0 +1,275 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe family specific services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIEFAMSERVICES_H_
+#define _GNBPCIEFAMSERVICES_H_
+
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+
+AGESA_STATUS
+PcieFmGetComplexDataLength (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+typedef AGESA_STATUS F_PCIEFMGETCOMPLEXDATALENGTH (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieFmBuildComplexConfiguration (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+typedef AGESA_STATUS F_PCIEFMBUILDCOMPLEXCONFIGURATION (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieFmConfigureEnginesLaneAllocation (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIE_ENGINE_TYPE              EngineType,
+  IN       UINT8                         ConfigurationId
+  );
+
+typedef AGESA_STATUS F_PCIEFMCONFIGUREENGINESLANEALLOCATION (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIE_ENGINE_TYPE              EngineType,
+  IN       UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+PcieFmGetCoreConfigurationValue (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         CoreId,
+  IN       UINT64                        ConfigurationSignature,
+  IN       UINT8                         *ConfigurationValue
+  );
+
+typedef AGESA_STATUS F_PCIEFMGETCORECONFIGURATIONVALUE (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         CoreId,
+  IN       UINT64                        ConfigurationSignature,
+  IN       UINT8                         *ConfigurationValue
+  );
+
+BOOLEAN
+PcieFmCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+typedef BOOLEAN F_PCIEFMCHECKPORTPCIDEVICEMAPPING (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+AGESA_STATUS
+PcieFmMapPortPciAddress (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+typedef AGESA_STATUS F_PCIEFMMAPPORTPCIADDRESS (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+BOOLEAN
+PcieFmCheckPortPcieLaneCanBeMuxed (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+typedef BOOLEAN F_PCIEFMCHECKPORTPCIELANECANBEMUXED (
+  IN      PCIe_PORT_DESCRIPTOR           *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+CONST CHAR8*
+PcieFmDebugGetCoreConfigurationString (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         ConfigurationValue
+ );
+
+typedef CONST CHAR8* F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       UINT8                         ConfigurationValue
+ );
+
+CONST CHAR8*
+PcieFmDebugGetWrapperNameString (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper
+ );
+
+typedef CONST CHAR8* F_PCIEFMDEBUGGETWRAPPERNAMESTRING (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper
+ );
+
+CONST CHAR8*
+PcieFmDebugGetHostRegAddressSpaceString (
+  IN      PCIe_SILICON_CONFIG            *Silicon,
+  IN      UINT16                         AddressFrame
+  );
+
+typedef CONST CHAR8* F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING (
+  IN      PCIe_SILICON_CONFIG            *Silicon,
+  IN      UINT16                         AddressFrame
+  );
+
+PCIE_LINK_SPEED_CAP
+PcieFmGetLinkSpeedCap (
+  IN       UINT32                        Flags,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+typedef PCIE_LINK_SPEED_CAP F_PCIEFMGETLINKSPEEDCAP (
+  IN       UINT32                        Flags,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+VOID
+PcieFmSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP            LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+typedef VOID F_PCIEFMSETLINKSPEEDCAP (
+  IN      PCIE_LINK_SPEED_CAP            LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+UINT32
+PcieFmGetNativePhyLaneBitmap (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+typedef UINT32 F_PCIEFMGETNATIVEPHYLANEBITMAP (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+AGESA_STATUS
+PcieFmAlibBuildAcpiTable (
+  IN       VOID                          *AlibSsdtPtr,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieFmGetSbConfigInfo (
+  IN       UINT8                        SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR         *SbPort,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+typedef AGESA_STATUS F_PCIEFMGETSBCONFIGINFO (
+  IN       UINT8                        SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR         *SbPort,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  );
+
+
+/// PCIe config services
+typedef struct {
+  F_PCIEFMGETCOMPLEXDATALENGTH              *PcieFmGetComplexDataLength;              ///< PcieFmGetComplexDataLength
+  F_PCIEFMBUILDCOMPLEXCONFIGURATION         *PcieFmBuildComplexConfiguration;         ///< PcieFmBuildComplexConfiguration
+  F_PCIEFMCONFIGUREENGINESLANEALLOCATION    *PcieFmConfigureEnginesLaneAllocation;    ///< PcieFmConfigureEnginesLaneAllocation
+  F_PCIEFMCHECKPORTPCIDEVICEMAPPING         *PcieFmCheckPortPciDeviceMapping;         ///< PcieFmCheckPortPciDeviceMapping
+  F_PCIEFMMAPPORTPCIADDRESS                 *PcieFmMapPortPciAddress;                 ///< PcieFmMapPortPciAddress
+  F_PCIEFMCHECKPORTPCIELANECANBEMUXED       *PcieFmCheckPortPcieLaneCanBeMuxed;       ///< PcieFmCheckPortPcieLaneCanBeMuxed
+  F_PCIEFMGETSBCONFIGINFO                   *PcieFmGetSbConfigInfo;                   ///< PcieFmGetSbConfigInfo
+} PCIe_FAM_CONFIG_SERVICES;
+
+/// PCIe init services
+typedef struct {
+  F_PCIEFMGETCORECONFIGURATIONVALUE         *PcieFmGetCoreConfigurationValue;         ///< PcieFmGetCoreConfigurationValue
+  F_PCIEFMGETLINKSPEEDCAP                   *PcieFmGetLinkSpeedCap;                   ///< PcieFmGetLinkSpeedCap
+  F_PCIEFMGETNATIVEPHYLANEBITMAP            *PcieFmGetNativePhyLaneBitmap;            ///< PcieFmGetNativePhyLaneBitmap
+  F_PCIEFMSETLINKSPEEDCAP                   *PcieFmSetLinkSpeedCap;                   ///< PcieFmSetLinkSpeedCap
+} PCIe_FAM_INIT_SERVICES;
+
+///PCIe debug services
+typedef struct {
+  F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING *PcieFmDebugGetHostRegAddressSpaceString; ///< PcieFmGetCoreConfigurationValue
+  F_PCIEFMDEBUGGETWRAPPERNAMESTRING         *PcieFmDebugGetWrapperNameString;         ///< PcieFmDebugGetWrapperNameString
+  F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING   *PcieFmDebugGetCoreConfigurationString;   ///< PcieFmDebugGetCoreConfigurationString
+} PCIe_FAM_DEBUG_SERVICES;
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h
new file mode 100644
index 0000000000..42824205ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersLN.h
@@ -0,0 +1,10111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Register definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBREGISTERSLN_H_
+#define _GNBREGISTERSLN_H_
+#define  TYPE_D0F0                  0x1
+#define  TYPE_D0F0x64               0x2
+#define  TYPE_D0F0x98               0x3
+#define  TYPE_D0F0xE4               0x5
+#define  TYPE_DxF0                  0x6
+#define  TYPE_DxF0xE4               0x7
+#define  TYPE_D18F1                 0xb
+#define  TYPE_D18F2                 0xc
+#define  TYPE_D18F3                 0xd
+#define  TYPE_MSR                   0x10
+#define  TYPE_D1F0                  0x11
+#define  TYPE_GMM                   0x12
+#define  D18F2x9C  0xe
+#define  GMM       0x11
+#ifndef WRAP_SPACE
+  #define  WRAP_SPACE(w, x)   (0x01300000 | (w << 16) | (x))
+#endif
+#ifndef CORE_SPACE
+  #define  CORE_SPACE(c, x)   (0x00010000 | (c << 24) | (x))
+#endif
+#ifndef PHY_SPACE
+  #define  PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+#ifndef  PIF_SPACE
+  #define  PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+// **** D0F0x00 Register Definition ****
+// Address
+#define D0F0x00_ADDRESS                                         0x0
+
+// Type
+#define D0F0x00_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x00_VendorID_OFFSET                                 0
+#define D0F0x00_VendorID_WIDTH                                  16
+#define D0F0x00_VendorID_MASK                                   0xffff
+#define D0F0x00_DeviceID_OFFSET                                 16
+#define D0F0x00_DeviceID_WIDTH                                  16
+#define D0F0x00_DeviceID_MASK                                   0xffff0000
+
+/// D0F0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x00_STRUCT;
+
+// **** D0F0x04 Register Definition ****
+// Address
+#define D0F0x04_ADDRESS                                         0x4
+
+// Type
+#define D0F0x04_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x04_IoAccessEn_OFFSET                               0
+#define D0F0x04_IoAccessEn_WIDTH                                1
+#define D0F0x04_IoAccessEn_MASK                                 0x1
+#define D0F0x04_MemAccessEn_OFFSET                              1
+#define D0F0x04_MemAccessEn_WIDTH                               1
+#define D0F0x04_MemAccessEn_MASK                                0x2
+#define D0F0x04_BusMasterEn_OFFSET                              2
+#define D0F0x04_BusMasterEn_WIDTH                               1
+#define D0F0x04_BusMasterEn_MASK                                0x4
+#define D0F0x04_SpecialCycleEn_OFFSET                           3
+#define D0F0x04_SpecialCycleEn_WIDTH                            1
+#define D0F0x04_SpecialCycleEn_MASK                             0x8
+#define D0F0x04_MemWriteInvalidateEn_OFFSET                     4
+#define D0F0x04_MemWriteInvalidateEn_WIDTH                      1
+#define D0F0x04_MemWriteInvalidateEn_MASK                       0x10
+#define D0F0x04_PalSnoopEn_OFFSET                               5
+#define D0F0x04_PalSnoopEn_WIDTH                                1
+#define D0F0x04_PalSnoopEn_MASK                                 0x20
+#define D0F0x04_ParityErrorEn_OFFSET                            6
+#define D0F0x04_ParityErrorEn_WIDTH                             1
+#define D0F0x04_ParityErrorEn_MASK                              0x40
+#define D0F0x04_Reserved_7_7_OFFSET                             7
+#define D0F0x04_Reserved_7_7_WIDTH                              1
+#define D0F0x04_Reserved_7_7_MASK                               0x80
+#define D0F0x04_SerrEn_OFFSET                                   8
+#define D0F0x04_SerrEn_WIDTH                                    1
+#define D0F0x04_SerrEn_MASK                                     0x100
+#define D0F0x04_FastB2BEn_OFFSET                                9
+#define D0F0x04_FastB2BEn_WIDTH                                 1
+#define D0F0x04_FastB2BEn_MASK                                  0x200
+#define D0F0x04_Reserved_19_10_OFFSET                           10
+#define D0F0x04_Reserved_19_10_WIDTH                            10
+#define D0F0x04_Reserved_19_10_MASK                             0xffc00
+#define D0F0x04_CapList_OFFSET                                  20
+#define D0F0x04_CapList_WIDTH                                   1
+#define D0F0x04_CapList_MASK                                    0x100000
+#define D0F0x04_PCI66En_OFFSET                                  21
+#define D0F0x04_PCI66En_WIDTH                                   1
+#define D0F0x04_PCI66En_MASK                                    0x200000
+#define D0F0x04_Reserved_22_22_OFFSET                           22
+#define D0F0x04_Reserved_22_22_WIDTH                            1
+#define D0F0x04_Reserved_22_22_MASK                             0x400000
+#define D0F0x04_FastBackCapable_OFFSET                          23
+#define D0F0x04_FastBackCapable_WIDTH                           1
+#define D0F0x04_FastBackCapable_MASK                            0x800000
+#define D0F0x04_Reserved_24_24_OFFSET                           24
+#define D0F0x04_Reserved_24_24_WIDTH                            1
+#define D0F0x04_Reserved_24_24_MASK                             0x1000000
+#define D0F0x04_DevselTiming_OFFSET                             25
+#define D0F0x04_DevselTiming_WIDTH                              2
+#define D0F0x04_DevselTiming_MASK                               0x6000000
+#define D0F0x04_SignalTargetAbort_OFFSET                        27
+#define D0F0x04_SignalTargetAbort_WIDTH                         1
+#define D0F0x04_SignalTargetAbort_MASK                          0x8000000
+#define D0F0x04_ReceivedTargetAbort_OFFSET                      28
+#define D0F0x04_ReceivedTargetAbort_WIDTH                       1
+#define D0F0x04_ReceivedTargetAbort_MASK                        0x10000000
+#define D0F0x04_ReceivedMasterAbort_OFFSET                      29
+#define D0F0x04_ReceivedMasterAbort_WIDTH                       1
+#define D0F0x04_ReceivedMasterAbort_MASK                        0x20000000
+#define D0F0x04_SignaledSystemError_OFFSET                      30
+#define D0F0x04_SignaledSystemError_WIDTH                       1
+#define D0F0x04_SignaledSystemError_MASK                        0x40000000
+#define D0F0x04_ParityErrorDetected_OFFSET                      31
+#define D0F0x04_ParityErrorDetected_WIDTH                       1
+#define D0F0x04_ParityErrorDetected_MASK                        0x80000000
+
+/// D0F0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                           SpecialCycleEn:1 ; ///<
+    UINT32                                     MemWriteInvalidateEn:1 ; ///<
+    UINT32                                               PalSnoopEn:1 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                FastB2BEn:1 ; ///<
+    UINT32                                           Reserved_19_10:10; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x04_STRUCT;
+
+// **** D0F0x08 Register Definition ****
+// Address
+#define D0F0x08_ADDRESS                                         0x8
+
+// Type
+#define D0F0x08_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x08_RevID_OFFSET                                    0
+#define D0F0x08_RevID_WIDTH                                     8
+#define D0F0x08_RevID_MASK                                      0xff
+#define D0F0x08_ClassCode_OFFSET                                8
+#define D0F0x08_ClassCode_WIDTH                                 24
+#define D0F0x08_ClassCode_MASK                                  0xffffff00
+
+/// D0F0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x08_STRUCT;
+
+// **** D0F0x0C Register Definition ****
+// Address
+#define D0F0x0C_ADDRESS                                         0xc
+
+// Type
+#define D0F0x0C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x0C_CacheLineSize_OFFSET                            0
+#define D0F0x0C_CacheLineSize_WIDTH                             8
+#define D0F0x0C_CacheLineSize_MASK                              0xff
+#define D0F0x0C_LatencyTimer_OFFSET                             8
+#define D0F0x0C_LatencyTimer_WIDTH                              8
+#define D0F0x0C_LatencyTimer_MASK                               0xff00
+#define D0F0x0C_HeaderTypeReg_OFFSET                            16
+#define D0F0x0C_HeaderTypeReg_WIDTH                             8
+#define D0F0x0C_HeaderTypeReg_MASK                              0xff0000
+#define D0F0x0C_BIST_OFFSET                                     24
+#define D0F0x0C_BIST_WIDTH                                      8
+#define D0F0x0C_BIST_MASK                                       0xff000000
+
+/// D0F0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x0C_STRUCT;
+
+// **** D0F0x2C Register Definition ****
+// Address
+#define D0F0x2C_ADDRESS                                         0x2c
+
+// Type
+#define D0F0x2C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x2C_SubsystemVendorID_OFFSET                        0
+#define D0F0x2C_SubsystemVendorID_WIDTH                         16
+#define D0F0x2C_SubsystemVendorID_MASK                          0xffff
+#define D0F0x2C_SubsystemID_OFFSET                              16
+#define D0F0x2C_SubsystemID_WIDTH                               16
+#define D0F0x2C_SubsystemID_MASK                                0xffff0000
+
+/// D0F0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorID:16; ///<
+    UINT32                                              SubsystemID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x2C_STRUCT;
+
+// **** D0F0x34 Register Definition ****
+// Address
+#define D0F0x34_ADDRESS                                         0x34
+
+// Type
+#define D0F0x34_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x34_CapPtr_OFFSET                                   0
+#define D0F0x34_CapPtr_WIDTH                                    8
+#define D0F0x34_CapPtr_MASK                                     0xff
+#define D0F0x34_Reserved_31_8_OFFSET                            8
+#define D0F0x34_Reserved_31_8_WIDTH                             24
+#define D0F0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x34_STRUCT;
+
+// **** D0F0x4C Register Definition ****
+// Address
+#define D0F0x4C_ADDRESS                                         0x4c
+
+// Type
+#define D0F0x4C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x4C_Function1Enable_OFFSET                          0
+#define D0F0x4C_Function1Enable_WIDTH                           1
+#define D0F0x4C_Function1Enable_MASK                            0x1
+#define D0F0x4C_ApicEnable_OFFSET                               1
+#define D0F0x4C_ApicEnable_WIDTH                                1
+#define D0F0x4C_ApicEnable_MASK                                 0x2
+#define D0F0x4C_Reserved_2_2_OFFSET                             2
+#define D0F0x4C_Reserved_2_2_WIDTH                              1
+#define D0F0x4C_Reserved_2_2_MASK                               0x4
+#define D0F0x4C_Cf8Dis_OFFSET                                   3
+#define D0F0x4C_Cf8Dis_WIDTH                                    1
+#define D0F0x4C_Cf8Dis_MASK                                     0x8
+#define D0F0x4C_PMEDis_OFFSET                                   4
+#define D0F0x4C_PMEDis_WIDTH                                    1
+#define D0F0x4C_PMEDis_MASK                                     0x10
+#define D0F0x4C_SerrDis_OFFSET                                  5
+#define D0F0x4C_SerrDis_WIDTH                                   1
+#define D0F0x4C_SerrDis_MASK                                    0x20
+#define D0F0x4C_Reserved_10_6_OFFSET                            6
+#define D0F0x4C_Reserved_10_6_WIDTH                             5
+#define D0F0x4C_Reserved_10_6_MASK                              0x7c0
+#define D0F0x4C_CRS_OFFSET                                      11
+#define D0F0x4C_CRS_WIDTH                                       1
+#define D0F0x4C_CRS_MASK                                        0x800
+#define D0F0x4C_CfgRdTime_OFFSET                                12
+#define D0F0x4C_CfgRdTime_WIDTH                                 3
+#define D0F0x4C_CfgRdTime_MASK                                  0x7000
+#define D0F0x4C_Reserved_22_15_OFFSET                           15
+#define D0F0x4C_Reserved_22_15_WIDTH                            8
+#define D0F0x4C_Reserved_22_15_MASK                             0x7f8000
+#define D0F0x4C_MMIOEnable_OFFSET                               23
+#define D0F0x4C_MMIOEnable_WIDTH                                1
+#define D0F0x4C_MMIOEnable_MASK                                 0x800000
+#define D0F0x4C_Reserved_25_24_OFFSET                           24
+#define D0F0x4C_Reserved_25_24_WIDTH                            2
+#define D0F0x4C_Reserved_25_24_MASK                             0x3000000
+#define D0F0x4C_HPDis_OFFSET                                    26
+#define D0F0x4C_HPDis_WIDTH                                     1
+#define D0F0x4C_HPDis_MASK                                      0x4000000
+#define D0F0x4C_Reserved_31_27_OFFSET                           27
+#define D0F0x4C_Reserved_31_27_WIDTH                            5
+#define D0F0x4C_Reserved_31_27_MASK                             0xf8000000
+
+/// D0F0x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          Function1Enable:1 ; ///<
+    UINT32                                               ApicEnable:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                   Cf8Dis:1 ; ///<
+    UINT32                                                   PMEDis:1 ; ///<
+    UINT32                                                  SerrDis:1 ; ///<
+    UINT32                                            Reserved_10_6:5 ; ///<
+    UINT32                                                      CRS:1 ; ///<
+    UINT32                                                CfgRdTime:3 ; ///<
+    UINT32                                           Reserved_22_15:8 ; ///<
+    UINT32                                               MMIOEnable:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    HPDis:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x4C_STRUCT;
+
+// **** D0F0x60 Register Definition ****
+// Address
+#define D0F0x60_ADDRESS                                         0x60
+
+// Type
+#define D0F0x60_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x60_MiscIndAddr_OFFSET                              0
+#define D0F0x60_MiscIndAddr_WIDTH                               7
+#define D0F0x60_MiscIndAddr_MASK                                0x7f
+#define D0F0x60_MiscIndWrEn_OFFSET                              7
+#define D0F0x60_MiscIndWrEn_WIDTH                               1
+#define D0F0x60_MiscIndWrEn_MASK                                0x80
+#define D0F0x60_Reserved_31_8_OFFSET                            8
+#define D0F0x60_Reserved_31_8_WIDTH                             24
+#define D0F0x60_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndAddr:7 ; ///<
+    UINT32                                              MiscIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x60_STRUCT;
+
+// **** D0F0x64 Register Definition ****
+// Address
+#define D0F0x64_ADDRESS                                         0x64
+
+// Type
+#define D0F0x64_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x64_MiscIndData_OFFSET                              0
+#define D0F0x64_MiscIndData_WIDTH                               32
+#define D0F0x64_MiscIndData_MASK                                0xffffffff
+
+/// D0F0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_STRUCT;
+
+
+/// D0F0x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Scratch:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x78_STRUCT;
+
+// **** D0F0x7C Register Definition ****
+// Address
+#define D0F0x7C_ADDRESS                                         0x7c
+
+// Type
+#define D0F0x7C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x7C_ForceIntGFXDisable_OFFSET                       0
+#define D0F0x7C_ForceIntGFXDisable_WIDTH                        1
+#define D0F0x7C_ForceIntGFXDisable_MASK                         0x1
+#define D0F0x7C_Reserved_31_1_OFFSET                            1
+#define D0F0x7C_Reserved_31_1_WIDTH                             31
+#define D0F0x7C_Reserved_31_1_MASK                              0xfffffffe
+
+/// D0F0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       ForceIntGFXDisable:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x7C_STRUCT;
+
+// **** D0F0x84 Register Definition ****
+// Address
+#define D0F0x84_ADDRESS                                         0x84
+
+// Type
+#define D0F0x84_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x84_Reserved_3_0_OFFSET                             0
+#define D0F0x84_Reserved_3_0_WIDTH                              4
+#define D0F0x84_Reserved_3_0_MASK                               0xf
+#define D0F0x84_Ev6Mode_OFFSET                                  4
+#define D0F0x84_Ev6Mode_WIDTH                                   1
+#define D0F0x84_Ev6Mode_MASK                                    0x10
+#define D0F0x84_Reserved_7_5_OFFSET                             5
+#define D0F0x84_Reserved_7_5_WIDTH                              3
+#define D0F0x84_Reserved_7_5_MASK                               0xe0
+#define D0F0x84_PmeMode_OFFSET                                  8
+#define D0F0x84_PmeMode_WIDTH                                   1
+#define D0F0x84_PmeMode_MASK                                    0x100
+#define D0F0x84_PmeTurnOff_OFFSET                               9
+#define D0F0x84_PmeTurnOff_WIDTH                                1
+#define D0F0x84_PmeTurnOff_MASK                                 0x200
+#define D0F0x84_Reserved_31_10_OFFSET                           10
+#define D0F0x84_Reserved_31_10_WIDTH                            22
+#define D0F0x84_Reserved_31_10_MASK                             0xfffffc00
+
+/// D0F0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                  Ev6Mode:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                  PmeMode:1 ; ///<
+    UINT32                                               PmeTurnOff:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x84_STRUCT;
+
+// **** D0F0x90 Register Definition ****
+// Address
+#define D0F0x90_ADDRESS                                         0x90
+
+// Type
+#define D0F0x90_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x90_Reserved_22_0_OFFSET                            0
+#define D0F0x90_Reserved_22_0_WIDTH                             23
+#define D0F0x90_Reserved_22_0_MASK                              0x7fffff
+#define D0F0x90_TopOfDram_OFFSET                                23
+#define D0F0x90_TopOfDram_WIDTH                                 9
+#define D0F0x90_TopOfDram_MASK                                  0xff800000
+
+/// D0F0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                                TopOfDram:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x90_STRUCT;
+
+// **** D0F0x94 Register Definition ****
+// Address
+#define D0F0x94_ADDRESS                                         0x94
+
+// Type
+#define D0F0x94_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x94_OrbIndAddr_OFFSET                               0
+#define D0F0x94_OrbIndAddr_WIDTH                                7
+#define D0F0x94_OrbIndAddr_MASK                                 0x7f
+#define D0F0x94_Reserved_7_7_OFFSET                             7
+#define D0F0x94_Reserved_7_7_WIDTH                              1
+#define D0F0x94_Reserved_7_7_MASK                               0x80
+#define D0F0x94_OrbIndWrEn_OFFSET                               8
+#define D0F0x94_OrbIndWrEn_WIDTH                                1
+#define D0F0x94_OrbIndWrEn_MASK                                 0x100
+#define D0F0x94_Reserved_31_9_OFFSET                            9
+#define D0F0x94_Reserved_31_9_WIDTH                             23
+#define D0F0x94_Reserved_31_9_MASK                              0xfffffe00
+
+/// D0F0x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndAddr:7 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                               OrbIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x94_STRUCT;
+
+// **** D0F0x98 Register Definition ****
+// Address
+#define D0F0x98_ADDRESS                                         0x98
+
+// Type
+#define D0F0x98_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x98_OrbIndData_OFFSET                               0
+#define D0F0x98_OrbIndData_WIDTH                                32
+#define D0F0x98_OrbIndData_MASK                                 0xffffffff
+
+/// D0F0x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_STRUCT;
+
+// **** D0F0xE0 Register Definition ****
+// Address
+#define D0F0xE0_ADDRESS                                         0xe0
+
+// Type
+#define D0F0xE0_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE0_PcieIndxAddr_OFFSET                             0
+#define D0F0xE0_PcieIndxAddr_WIDTH                              16
+#define D0F0xE0_PcieIndxAddr_MASK                               0xffff
+#define D0F0xE0_FrameType_OFFSET                                16
+#define D0F0xE0_FrameType_WIDTH                                 8
+#define D0F0xE0_FrameType_MASK                                  0xff0000
+#define D0F0xE0_BlockSelect_OFFSET                              24
+#define D0F0xE0_BlockSelect_WIDTH                               8
+#define D0F0xE0_BlockSelect_MASK                                0xff000000
+
+/// D0F0xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxAddr:16; ///<
+    UINT32                                                FrameType:8 ; ///<
+    UINT32                                              BlockSelect:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE0_STRUCT;
+
+// **** D0F0xE4 Register Definition ****
+// Address
+#define D0F0xE4_ADDRESS                                         0xe4
+
+// Type
+#define D0F0xE4_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE4_PcieIndxData_OFFSET                             0
+#define D0F0xE4_PcieIndxData_WIDTH                              32
+#define D0F0xE4_PcieIndxData_MASK                               0xffffffff
+
+/// D0F0xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_STRUCT;
+
+// **** D18F1xF0 Register Definition ****
+// Address
+#define D18F1xF0_ADDRESS                                        0xf0
+
+// Type
+#define D18F1xF0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xF0_DramHoleValid_OFFSET                           0
+#define D18F1xF0_DramHoleValid_WIDTH                            1
+#define D18F1xF0_DramHoleValid_MASK                             0x1
+#define D18F1xF0_Reserved_6_1_OFFSET                            1
+#define D18F1xF0_Reserved_6_1_WIDTH                             6
+#define D18F1xF0_Reserved_6_1_MASK                              0x7e
+#define D18F1xF0_DramHoleOffset_31_23__OFFSET                   7
+#define D18F1xF0_DramHoleOffset_31_23__WIDTH                    9
+#define D18F1xF0_DramHoleOffset_31_23__MASK                     0xff80
+#define D18F1xF0_Reserved_23_16_OFFSET                          16
+#define D18F1xF0_Reserved_23_16_WIDTH                           8
+#define D18F1xF0_Reserved_23_16_MASK                            0xff0000
+#define D18F1xF0_DramHoleBase_31_24__OFFSET                     24
+#define D18F1xF0_DramHoleBase_31_24__WIDTH                      8
+#define D18F1xF0_DramHoleBase_31_24__MASK                       0xff000000
+
+/// D18F1xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DramHoleValid:1 ; ///<
+    UINT32                                             Reserved_6_1:6 ; ///<
+    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
+    UINT32                                           Reserved_23_16:8 ; ///<
+    UINT32                                      DramHoleBase_31_24_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xF0_STRUCT;
+
+// **** D18F2x00 Register Definition ****
+// Address
+#define D18F2x00_ADDRESS                                        0x0
+
+// Type
+#define D18F2x00_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x00_VendorID_OFFSET                                0
+#define D18F2x00_VendorID_WIDTH                                 16
+#define D18F2x00_VendorID_MASK                                  0xffff
+#define D18F2x00_DeviceID_OFFSET                                16
+#define D18F2x00_DeviceID_WIDTH                                 16
+#define D18F2x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F2x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x00_STRUCT;
+
+
+// **** D18F2x08 Register Definition ****
+// Address
+#define D18F2x08_ADDRESS                                        0x8
+
+// Type
+#define D18F2x08_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x08_RevID_OFFSET                                   0
+#define D18F2x08_RevID_WIDTH                                    8
+#define D18F2x08_RevID_MASK                                     0xff
+#define D18F2x08_ClassCode_OFFSET                               8
+#define D18F2x08_ClassCode_WIDTH                                24
+#define D18F2x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F2x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x08_STRUCT;
+
+// **** D18F2x0C Register Definition ****
+// Address
+#define D18F2x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F2x0C_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x0C_HeaderTypeReg_OFFSET                           0
+#define D18F2x0C_HeaderTypeReg_WIDTH                            32
+#define D18F2x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F2x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x0C_STRUCT;
+
+
+// **** D18F2x040 Register Definition ****
+// Address
+#define D18F2x040_ADDRESS                                       0x40
+
+// Type
+#define D18F2x040_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x040_CSEnable_OFFSET                               0
+#define D18F2x040_CSEnable_WIDTH                                1
+#define D18F2x040_CSEnable_MASK                                 0x1
+#define D18F2x040_Reserved_1_1_OFFSET                           1
+#define D18F2x040_Reserved_1_1_WIDTH                            1
+#define D18F2x040_Reserved_1_1_MASK                             0x2
+#define D18F2x040_TestFail_OFFSET                               2
+#define D18F2x040_TestFail_WIDTH                                1
+#define D18F2x040_TestFail_MASK                                 0x4
+#define D18F2x040_OnDimmMirror_OFFSET                           3
+#define D18F2x040_OnDimmMirror_WIDTH                            1
+#define D18F2x040_OnDimmMirror_MASK                             0x8
+#define D18F2x040_Reserved_4_4_OFFSET                           4
+#define D18F2x040_Reserved_4_4_WIDTH                            1
+#define D18F2x040_Reserved_4_4_MASK                             0x10
+#define D18F2x040_Reserved_31_29_OFFSET                         29
+#define D18F2x040_Reserved_31_29_WIDTH                          3
+#define D18F2x040_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x040_STRUCT;
+
+// **** D18F2x044 Register Definition ****
+// Address
+#define D18F2x044_ADDRESS                                       0x44
+
+// Type
+#define D18F2x044_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x044_CSEnable_OFFSET                               0
+#define D18F2x044_CSEnable_WIDTH                                1
+#define D18F2x044_CSEnable_MASK                                 0x1
+#define D18F2x044_Reserved_1_1_OFFSET                           1
+#define D18F2x044_Reserved_1_1_WIDTH                            1
+#define D18F2x044_Reserved_1_1_MASK                             0x2
+#define D18F2x044_TestFail_OFFSET                               2
+#define D18F2x044_TestFail_WIDTH                                1
+#define D18F2x044_TestFail_MASK                                 0x4
+#define D18F2x044_OnDimmMirror_OFFSET                           3
+#define D18F2x044_OnDimmMirror_WIDTH                            1
+#define D18F2x044_OnDimmMirror_MASK                             0x8
+#define D18F2x044_Reserved_4_4_OFFSET                           4
+#define D18F2x044_Reserved_4_4_WIDTH                            1
+#define D18F2x044_Reserved_4_4_MASK                             0x10
+#define D18F2x044_Reserved_31_29_OFFSET                         29
+#define D18F2x044_Reserved_31_29_WIDTH                          3
+#define D18F2x044_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x044
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x044_STRUCT;
+
+// **** D18F2x048 Register Definition ****
+// Address
+#define D18F2x048_ADDRESS                                       0x48
+
+// Type
+#define D18F2x048_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x048_CSEnable_OFFSET                               0
+#define D18F2x048_CSEnable_WIDTH                                1
+#define D18F2x048_CSEnable_MASK                                 0x1
+#define D18F2x048_Reserved_1_1_OFFSET                           1
+#define D18F2x048_Reserved_1_1_WIDTH                            1
+#define D18F2x048_Reserved_1_1_MASK                             0x2
+#define D18F2x048_TestFail_OFFSET                               2
+#define D18F2x048_TestFail_WIDTH                                1
+#define D18F2x048_TestFail_MASK                                 0x4
+#define D18F2x048_OnDimmMirror_OFFSET                           3
+#define D18F2x048_OnDimmMirror_WIDTH                            1
+#define D18F2x048_OnDimmMirror_MASK                             0x8
+#define D18F2x048_Reserved_4_4_OFFSET                           4
+#define D18F2x048_Reserved_4_4_WIDTH                            1
+#define D18F2x048_Reserved_4_4_MASK                             0x10
+#define D18F2x048_Reserved_31_29_OFFSET                         29
+#define D18F2x048_Reserved_31_29_WIDTH                          3
+#define D18F2x048_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x048
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x048_STRUCT;
+
+// **** D18F2x04C Register Definition ****
+// Address
+#define D18F2x04C_ADDRESS                                       0x4c
+
+// Type
+#define D18F2x04C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x04C_CSEnable_OFFSET                               0
+#define D18F2x04C_CSEnable_WIDTH                                1
+#define D18F2x04C_CSEnable_MASK                                 0x1
+#define D18F2x04C_Reserved_1_1_OFFSET                           1
+#define D18F2x04C_Reserved_1_1_WIDTH                            1
+#define D18F2x04C_Reserved_1_1_MASK                             0x2
+#define D18F2x04C_TestFail_OFFSET                               2
+#define D18F2x04C_TestFail_WIDTH                                1
+#define D18F2x04C_TestFail_MASK                                 0x4
+#define D18F2x04C_OnDimmMirror_OFFSET                           3
+#define D18F2x04C_OnDimmMirror_WIDTH                            1
+#define D18F2x04C_OnDimmMirror_MASK                             0x8
+#define D18F2x04C_Reserved_4_4_OFFSET                           4
+#define D18F2x04C_Reserved_4_4_WIDTH                            1
+#define D18F2x04C_Reserved_4_4_MASK                             0x10
+#define D18F2x04C_Reserved_31_29_OFFSET                         29
+#define D18F2x04C_Reserved_31_29_WIDTH                          3
+#define D18F2x04C_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x04C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x04C_STRUCT;
+
+// **** D18F2x060 Register Definition ****
+// Address
+#define D18F2x060_ADDRESS                                       0x60
+
+// Type
+#define D18F2x060_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x060_Reserved_4_0_OFFSET                           0
+#define D18F2x060_Reserved_4_0_WIDTH                            5
+#define D18F2x060_Reserved_4_0_MASK                             0x1f
+#define D18F2x060_Reserved_31_29_OFFSET                         29
+#define D18F2x060_Reserved_31_29_WIDTH                          3
+#define D18F2x060_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x060_STRUCT;
+
+// **** D18F2x064 Register Definition ****
+// Address
+#define D18F2x064_ADDRESS                                       0x64
+
+// Type
+#define D18F2x064_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x064_Reserved_4_0_OFFSET                           0
+#define D18F2x064_Reserved_4_0_WIDTH                            5
+#define D18F2x064_Reserved_4_0_MASK                             0x1f
+#define D18F2x064_Reserved_31_29_OFFSET                         29
+#define D18F2x064_Reserved_31_29_WIDTH                          3
+#define D18F2x064_Reserved_31_29_MASK                           0xe0000000
+
+/// D18F2x064
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          :9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          :10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x064_STRUCT;
+
+// **** D18F2x078 Register Definition ****
+// Address
+#define D18F2x078_ADDRESS                                       0x78
+
+// Type
+#define D18F2x078_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x078_Reserved_14_14_OFFSET                         14
+#define D18F2x078_Reserved_14_14_WIDTH                          1
+#define D18F2x078_Reserved_14_14_MASK                           0x4000
+#define D18F2x078_Reserved_15_15_OFFSET                         15
+#define D18F2x078_Reserved_15_15_WIDTH                          1
+#define D18F2x078_Reserved_15_15_MASK                           0x8000
+#define D18F2x078_Reserved_16_16_OFFSET                         16
+#define D18F2x078_Reserved_16_16_WIDTH                          1
+#define D18F2x078_Reserved_16_16_MASK                           0x10000
+#define D18F2x078_AddrCmdTriEn_OFFSET                           17
+#define D18F2x078_AddrCmdTriEn_WIDTH                            1
+#define D18F2x078_AddrCmdTriEn_MASK                             0x20000
+#define D18F2x078_Reserved_18_18_OFFSET                         18
+#define D18F2x078_Reserved_18_18_WIDTH                          1
+#define D18F2x078_Reserved_18_18_MASK                           0x40000
+#define D18F2x078_Reserved_19_19_OFFSET                         19
+#define D18F2x078_Reserved_19_19_WIDTH                          1
+#define D18F2x078_Reserved_19_19_MASK                           0x80000
+
+/// D18F2x078
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                :4 ; ///<
+    UINT32                                             :2 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                           Reserved_16_16:1 ; ///<
+    UINT32                                             AddrCmdTriEn:1 ; ///<
+    UINT32                                           Reserved_18_18:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                        :1 ; ///<
+    UINT32                                             :10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x078_STRUCT;
+
+
+
+// **** D18F2x084 Register Definition ****
+// Address
+#define D18F2x084_ADDRESS                                       0x84
+
+// Type
+#define D18F2x084_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x084_BurstCtrl_OFFSET                              0
+#define D18F2x084_BurstCtrl_WIDTH                               2
+#define D18F2x084_BurstCtrl_MASK                                0x3
+#define D18F2x084_Reserved_3_2_OFFSET                           2
+#define D18F2x084_Reserved_3_2_WIDTH                            2
+#define D18F2x084_Reserved_3_2_MASK                             0xc
+#define D18F2x084_Reserved_19_7_OFFSET                          7
+#define D18F2x084_Reserved_19_7_WIDTH                           13
+#define D18F2x084_Reserved_19_7_MASK                            0xfff80
+#define D18F2x084_PchgPDModeSel_OFFSET                          23
+#define D18F2x084_PchgPDModeSel_WIDTH                           1
+#define D18F2x084_PchgPDModeSel_MASK                            0x800000
+#define D18F2x084_Reserved_31_24_OFFSET                         24
+#define D18F2x084_Reserved_31_24_WIDTH                          8
+#define D18F2x084_Reserved_31_24_MASK                           0xff000000
+
+/// D18F2x084
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                BurstCtrl:2 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                      :3 ; ///<
+    UINT32                                            Reserved_19_7:13; ///<
+    UINT32                                                     :3 ; ///<
+    UINT32                                            PchgPDModeSel:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x084_STRUCT;
+
+// **** D18F2x088 Register Definition ****
+// Address
+#define D18F2x088_ADDRESS                                       0x88
+
+// Type
+#define D18F2x088_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x088_Reserved_23_4_OFFSET                          4
+#define D18F2x088_Reserved_23_4_WIDTH                           20
+#define D18F2x088_Reserved_23_4_MASK                            0xfffff0
+
+/// D18F2x088
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      :4 ; ///<
+    UINT32                                            Reserved_23_4:20; ///<
+    UINT32                                                :8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x088_STRUCT;
+
+
+
+
+// **** D18F2x098 Register Definition ****
+// Address
+#define D18F2x098_ADDRESS                                       0x98
+
+// Type
+#define D18F2x098_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x098_DctOffset_OFFSET                              0
+#define D18F2x098_DctOffset_WIDTH                               30
+#define D18F2x098_DctOffset_MASK                                0x3fffffff
+#define D18F2x098_DctAccessWrite_OFFSET                         30
+#define D18F2x098_DctAccessWrite_WIDTH                          1
+#define D18F2x098_DctAccessWrite_MASK                           0x40000000
+#define D18F2x098_Reserved_31_31_OFFSET                         31
+#define D18F2x098_Reserved_31_31_WIDTH                          1
+#define D18F2x098_Reserved_31_31_MASK                           0x80000000
+
+/// D18F2x098
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctOffset:30; ///<
+    UINT32                                           DctAccessWrite:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x098_STRUCT;
+
+// **** D18F2x09C Register Definition ****
+// Address
+#define D18F2x09C_ADDRESS                                       0x9c
+
+// Type
+#define D18F2x09C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x09C_DctDataPort_OFFSET                            0
+#define D18F2x09C_DctDataPort_WIDTH                             32
+#define D18F2x09C_DctDataPort_MASK                              0xffffffff
+
+/// D18F2x09C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DctDataPort:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_STRUCT;
+
+
+// **** D18F2xA4 Register Definition ****
+// Address
+#define D18F2xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F2xA4_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xA4_DoubleTrefRateEn_OFFSET                        0
+#define D18F2xA4_DoubleTrefRateEn_WIDTH                         1
+
+
+// **** D18F2xAC Register Definition ****
+// Address
+#define D18F2xAC_ADDRESS                                        0xac
+
+// Type
+#define D18F2xAC_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xAC_Reserved_31_1_OFFSET                           1
+#define D18F2xAC_Reserved_31_1_WIDTH                            31
+#define D18F2xAC_Reserved_31_1_MASK                             0xfffffffe
+
+/// D18F2xAC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               MemTempHot:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xAC_STRUCT;
+
+
+
+// **** D18F2x114 Register Definition ****
+// Address
+#define D18F2x114_ADDRESS                                       0x114
+
+// Type
+#define D18F2x114_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x114_Reserved_8_0_OFFSET                           0
+#define D18F2x114_Reserved_8_0_WIDTH                            9
+#define D18F2x114_Reserved_8_0_MASK                             0x1ff
+#define D18F2x114_DctSelIntLvAddr_2__OFFSET                     9
+#define D18F2x114_DctSelIntLvAddr_2__WIDTH                      1
+#define D18F2x114_DctSelIntLvAddr_2__MASK                       0x200
+
+/// D18F2x114
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
+    UINT32                                  :14; ///<
+    UINT32                                           :8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x114_STRUCT;
+
+
+// **** D18F3x00 Register Definition ****
+// Address
+#define D18F3x00_ADDRESS                                        0x0
+
+// Type
+#define D18F3x00_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x00_VendorID_OFFSET                                0
+#define D18F3x00_VendorID_WIDTH                                 16
+#define D18F3x00_VendorID_MASK                                  0xffff
+#define D18F3x00_DeviceID_OFFSET                                16
+#define D18F3x00_DeviceID_WIDTH                                 16
+#define D18F3x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F3x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x00_STRUCT;
+
+// **** D18F3x04 Register Definition ****
+// Address
+#define D18F3x04_ADDRESS                                        0x4
+
+// Type
+#define D18F3x04_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x04_Command_OFFSET                                 0
+#define D18F3x04_Command_WIDTH                                  16
+#define D18F3x04_Command_MASK                                   0xffff
+#define D18F3x04_Status_OFFSET                                  16
+#define D18F3x04_Status_WIDTH                                   16
+#define D18F3x04_Status_MASK                                    0xffff0000
+
+/// D18F3x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x04_STRUCT;
+
+// **** D18F3x08 Register Definition ****
+// Address
+#define D18F3x08_ADDRESS                                        0x8
+
+// Type
+#define D18F3x08_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x08_RevID_OFFSET                                   0
+#define D18F3x08_RevID_WIDTH                                    8
+#define D18F3x08_RevID_MASK                                     0xff
+#define D18F3x08_ClassCode_OFFSET                               8
+#define D18F3x08_ClassCode_WIDTH                                24
+#define D18F3x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F3x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x08_STRUCT;
+
+// **** D18F3x0C Register Definition ****
+// Address
+#define D18F3x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F3x0C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x0C_HeaderTypeReg_OFFSET                           0
+#define D18F3x0C_HeaderTypeReg_WIDTH                            32
+#define D18F3x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F3x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x0C_STRUCT;
+
+// **** D18F3x34 Register Definition ****
+// Address
+#define D18F3x34_ADDRESS                                        0x34
+
+// Type
+#define D18F3x34_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x34_CapPtr_OFFSET                                  0
+#define D18F3x34_CapPtr_WIDTH                                   8
+#define D18F3x34_CapPtr_MASK                                    0xff
+#define D18F3x34_Reserved_31_8_OFFSET                           8
+#define D18F3x34_Reserved_31_8_WIDTH                            24
+#define D18F3x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F3x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x34_STRUCT;
+
+
+// **** D18F3x48 Register Definition ****
+// Address
+#define D18F3x48_ADDRESS                                        0x48
+
+// Type
+#define D18F3x48_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x48_ErrorCode_OFFSET                               0
+#define D18F3x48_ErrorCode_WIDTH                                16
+#define D18F3x48_ErrorCode_MASK                                 0xffff
+#define D18F3x48_ErrorCodeExt_OFFSET                            16
+#define D18F3x48_ErrorCodeExt_WIDTH                             5
+#define D18F3x48_ErrorCodeExt_MASK                              0x1f0000
+#define D18F3x48_Reserved_31_21_OFFSET                          21
+#define D18F3x48_Reserved_31_21_WIDTH                           11
+#define D18F3x48_Reserved_31_21_MASK                            0xffe00000
+
+/// D18F3x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrorCode:16; ///<
+    UINT32                                             ErrorCodeExt:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x48_STRUCT;
+
+
+// **** D18F3x64 Register Definition ****
+// Address
+#define D18F3x64_ADDRESS                                        0x64
+
+// Type
+#define D18F3x64_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x64_HtcEn_OFFSET                                   0
+#define D18F3x64_HtcEn_WIDTH                                    1
+#define D18F3x64_HtcEn_MASK                                     0x1
+#define D18F3x64_Reserved_3_1_OFFSET                            1
+#define D18F3x64_Reserved_3_1_WIDTH                             3
+#define D18F3x64_Reserved_3_1_MASK                              0xe
+#define D18F3x64_HtcAct_OFFSET                                  4
+#define D18F3x64_HtcAct_WIDTH                                   1
+#define D18F3x64_HtcAct_MASK                                    0x10
+#define D18F3x64_HtcActSts_OFFSET                               5
+#define D18F3x64_HtcActSts_WIDTH                                1
+#define D18F3x64_HtcActSts_MASK                                 0x20
+#define D18F3x64_PslApicHiEn_OFFSET                             6
+#define D18F3x64_PslApicHiEn_WIDTH                              1
+#define D18F3x64_PslApicHiEn_MASK                               0x40
+#define D18F3x64_PslApicLoEn_OFFSET                             7
+#define D18F3x64_PslApicLoEn_WIDTH                              1
+#define D18F3x64_PslApicLoEn_MASK                               0x80
+#define D18F3x64_Reserved_15_8_OFFSET                           8
+#define D18F3x64_Reserved_15_8_WIDTH                            8
+#define D18F3x64_Reserved_15_8_MASK                             0xff00
+#define D18F3x64_HtcTmpLmt_OFFSET                               16
+#define D18F3x64_HtcTmpLmt_WIDTH                                7
+#define D18F3x64_HtcTmpLmt_MASK                                 0x7f0000
+#define D18F3x64_HtcSlewSel_OFFSET                              23
+#define D18F3x64_HtcSlewSel_WIDTH                               1
+#define D18F3x64_HtcSlewSel_MASK                                0x800000
+#define D18F3x64_HtcHystLmt_OFFSET                              24
+#define D18F3x64_HtcHystLmt_WIDTH                               4
+#define D18F3x64_HtcHystLmt_MASK                                0xf000000
+#define D18F3x64_HtcPstateLimit_OFFSET                          28
+#define D18F3x64_HtcPstateLimit_WIDTH                           3
+#define D18F3x64_HtcPstateLimit_MASK                            0x70000000
+
+/// D18F3x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    HtcEn:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                                   HtcAct:1 ; ///<
+    UINT32                                                HtcActSts:1 ; ///<
+    UINT32                                              PslApicHiEn:1 ; ///<
+    UINT32                                              PslApicLoEn:1 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                                HtcTmpLmt:7 ; ///<
+    UINT32                                               HtcSlewSel:1 ; ///<
+    UINT32                                               HtcHystLmt:4 ; ///<
+    UINT32                                           HtcPstateLimit:3 ; ///<
+    UINT32                                                  :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x64_STRUCT;
+
+
+// **** D18F3x88 Register Definition ****
+// Address
+#define D18F3x88_ADDRESS                                        0x88
+
+// Type
+#define D18F3x88_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x88_Reserved_31_0_OFFSET                           0
+#define D18F3x88_Reserved_31_0_WIDTH                            32
+#define D18F3x88_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x88_STRUCT;
+
+
+// **** D18F3xE4 Register Definition ****
+// Address
+#define D18F3xE4_ADDRESS                                        0xe4
+
+// Type
+#define D18F3xE4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xE4_Reserved_0_0_OFFSET                            0
+#define D18F3xE4_Reserved_0_0_WIDTH                             1
+#define D18F3xE4_Reserved_0_0_MASK                              0x1
+#define D18F3xE4_Thermtp_OFFSET                                 1
+#define D18F3xE4_Thermtp_WIDTH                                  1
+#define D18F3xE4_Thermtp_MASK                                   0x2
+#define D18F3xE4_Reserved_2_2_OFFSET                            2
+#define D18F3xE4_Reserved_2_2_WIDTH                             1
+#define D18F3xE4_Reserved_2_2_MASK                              0x4
+#define D18F3xE4_ThermtpSense_OFFSET                            3
+#define D18F3xE4_ThermtpSense_WIDTH                             1
+#define D18F3xE4_ThermtpSense_MASK                              0x8
+#define D18F3xE4_Reserved_4_4_OFFSET                            4
+#define D18F3xE4_Reserved_4_4_WIDTH                             1
+#define D18F3xE4_Reserved_4_4_MASK                              0x10
+#define D18F3xE4_ThermtpEn_OFFSET                               5
+#define D18F3xE4_ThermtpEn_WIDTH                                1
+#define D18F3xE4_ThermtpEn_MASK                                 0x20
+#define D18F3xE4_Reserved_7_6_OFFSET                            6
+#define D18F3xE4_Reserved_7_6_WIDTH                             2
+#define D18F3xE4_Reserved_7_6_MASK                              0xc0
+#define D18F3xE4_Reserved_30_8_OFFSET                           8
+#define D18F3xE4_Reserved_30_8_WIDTH                            23
+#define D18F3xE4_Reserved_30_8_MASK                             0x7fffff00
+#define D18F3xE4_SwThermtp_OFFSET                               31
+#define D18F3xE4_SwThermtp_WIDTH                                1
+#define D18F3xE4_SwThermtp_MASK                                 0x80000000
+
+/// D18F3xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  Thermtp:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             ThermtpSense:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                                ThermtpEn:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                            Reserved_30_8:23; ///<
+    UINT32                                                SwThermtp:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xE4_STRUCT;
+
+
+// **** D18F3xF0 Register Definition ****
+// Address
+#define D18F3xF0_ADDRESS                                        0xf0
+
+// Type
+#define D18F3xF0_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xF0_Reserved_31_0_OFFSET                           0
+#define D18F3xF0_Reserved_31_0_WIDTH                            32
+#define D18F3xF0_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xF0_STRUCT;
+
+// **** D18F3xF4 Register Definition ****
+// Address
+#define D18F3xF4_ADDRESS                                        0xf4
+
+// Type
+#define D18F3xF4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xF4_Reserved_31_0_OFFSET                           0
+#define D18F3xF4_Reserved_31_0_WIDTH                            32
+#define D18F3xF4_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3xF4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xF4_STRUCT;
+
+// **** D18F3xF8 Register Definition ****
+// Address
+#define D18F3xF8_ADDRESS                                        0xf8
+
+// Type
+#define D18F3xF8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xF8_Reserved_31_0_OFFSET                           0
+#define D18F3xF8_Reserved_31_0_WIDTH                            32
+#define D18F3xF8_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F3xF8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xF8_STRUCT;
+
+// **** D18F3xFC Register Definition ****
+// Address
+#define D18F3xFC_ADDRESS                                        0xfc
+
+// Type
+#define D18F3xFC_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xFC_Stepping_OFFSET                                0
+#define D18F3xFC_Stepping_WIDTH                                 4
+#define D18F3xFC_Stepping_MASK                                  0xf
+#define D18F3xFC_BaseModel_OFFSET                               4
+#define D18F3xFC_BaseModel_WIDTH                                4
+#define D18F3xFC_BaseModel_MASK                                 0xf0
+#define D18F3xFC_BaseFamily_OFFSET                              8
+#define D18F3xFC_BaseFamily_WIDTH                               4
+#define D18F3xFC_BaseFamily_MASK                                0xf00
+#define D18F3xFC_Reserved_15_12_OFFSET                          12
+#define D18F3xFC_Reserved_15_12_WIDTH                           4
+#define D18F3xFC_Reserved_15_12_MASK                            0xf000
+#define D18F3xFC_ExtModel_OFFSET                                16
+#define D18F3xFC_ExtModel_WIDTH                                 4
+#define D18F3xFC_ExtModel_MASK                                  0xf0000
+#define D18F3xFC_ExtFamily_OFFSET                               20
+#define D18F3xFC_ExtFamily_WIDTH                                8
+#define D18F3xFC_ExtFamily_MASK                                 0xff00000
+#define D18F3xFC_Reserved_31_28_OFFSET                          28
+#define D18F3xFC_Reserved_31_28_WIDTH                           4
+#define D18F3xFC_Reserved_31_28_MASK                            0xf0000000
+
+/// D18F3xFC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Stepping:4 ; ///<
+    UINT32                                                BaseModel:4 ; ///<
+    UINT32                                               BaseFamily:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                 ExtModel:4 ; ///<
+    UINT32                                                ExtFamily:8 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xFC_STRUCT;
+
+
+
+
+
+
+
+// **** D18F3x1CC Register Definition ****
+// Address
+#define D18F3x1CC_ADDRESS                                       0x1cc
+
+// Type
+#define D18F3x1CC_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1CC_LvtOffset_OFFSET                              0
+#define D18F3x1CC_LvtOffset_WIDTH                               4
+#define D18F3x1CC_LvtOffset_MASK                                0xf
+#define D18F3x1CC_Reserved_7_4_OFFSET                           4
+#define D18F3x1CC_Reserved_7_4_WIDTH                            4
+#define D18F3x1CC_Reserved_7_4_MASK                             0xf0
+#define D18F3x1CC_LvtOffsetVal_OFFSET                           8
+#define D18F3x1CC_LvtOffsetVal_WIDTH                            1
+#define D18F3x1CC_LvtOffsetVal_MASK                             0x100
+#define D18F3x1CC_Reserved_31_9_OFFSET                          9
+#define D18F3x1CC_Reserved_31_9_WIDTH                           23
+#define D18F3x1CC_Reserved_31_9_MASK                            0xfffffe00
+
+/// D18F3x1CC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LvtOffset:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             LvtOffsetVal:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1CC_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+// **** DxF0x00 Register Definition ****
+// Address
+#define DxF0x00_ADDRESS                                         0x0
+
+// Type
+#define DxF0x00_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x00_VendorID_OFFSET                                 0
+#define DxF0x00_VendorID_WIDTH                                  16
+#define DxF0x00_VendorID_MASK                                   0xffff
+#define DxF0x00_DeviceID_OFFSET                                 16
+#define DxF0x00_DeviceID_WIDTH                                  16
+#define DxF0x00_DeviceID_MASK                                   0xffff0000
+
+/// DxF0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x00_STRUCT;
+
+
+// **** DxF0x08 Register Definition ****
+// Address
+#define DxF0x08_ADDRESS                                         0x8
+
+// Type
+#define DxF0x08_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x08_RevID_OFFSET                                    0
+#define DxF0x08_RevID_WIDTH                                     8
+#define DxF0x08_RevID_MASK                                      0xff
+#define DxF0x08_ClassCode_OFFSET                                8
+#define DxF0x08_ClassCode_WIDTH                                 24
+#define DxF0x08_ClassCode_MASK                                  0xffffff00
+
+/// DxF0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x08_STRUCT;
+
+// **** DxF0x0C Register Definition ****
+// Address
+#define DxF0x0C_ADDRESS                                         0xc
+
+// Type
+#define DxF0x0C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x0C_CacheLineSize_OFFSET                            0
+#define DxF0x0C_CacheLineSize_WIDTH                             8
+#define DxF0x0C_CacheLineSize_MASK                              0xff
+#define DxF0x0C_LatencyTimer_OFFSET                             8
+#define DxF0x0C_LatencyTimer_WIDTH                              8
+#define DxF0x0C_LatencyTimer_MASK                               0xff00
+#define DxF0x0C_HeaderTypeReg_OFFSET                            16
+#define DxF0x0C_HeaderTypeReg_WIDTH                             8
+#define DxF0x0C_HeaderTypeReg_MASK                              0xff0000
+#define DxF0x0C_BIST_OFFSET                                     24
+#define DxF0x0C_BIST_WIDTH                                      8
+#define DxF0x0C_BIST_MASK                                       0xff000000
+
+/// DxF0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x0C_STRUCT;
+
+// **** DxF0x18 Register Definition ****
+// Address
+#define DxF0x18_ADDRESS                                         0x18
+
+// Type
+#define DxF0x18_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x18_PrimaryBus_OFFSET                               0
+#define DxF0x18_PrimaryBus_WIDTH                                8
+#define DxF0x18_PrimaryBus_MASK                                 0xff
+#define DxF0x18_SecondaryBus_OFFSET                             8
+#define DxF0x18_SecondaryBus_WIDTH                              8
+#define DxF0x18_SecondaryBus_MASK                               0xff00
+#define DxF0x18_SubBusNumber_OFFSET                             16
+#define DxF0x18_SubBusNumber_WIDTH                              8
+#define DxF0x18_SubBusNumber_MASK                               0xff0000
+#define DxF0x18_SecondaryLatencyTimer_OFFSET                    24
+#define DxF0x18_SecondaryLatencyTimer_WIDTH                     8
+#define DxF0x18_SecondaryLatencyTimer_MASK                      0xff000000
+
+/// DxF0x18
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PrimaryBus:8 ; ///<
+    UINT32                                             SecondaryBus:8 ; ///<
+    UINT32                                             SubBusNumber:8 ; ///<
+    UINT32                                    SecondaryLatencyTimer:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x18_STRUCT;
+
+
+// **** DxF0x20 Register Definition ****
+// Address
+#define DxF0x20_ADDRESS                                         0x20
+
+// Type
+#define DxF0x20_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x20_Reserved_3_0_OFFSET                             0
+#define DxF0x20_Reserved_3_0_WIDTH                              4
+#define DxF0x20_Reserved_3_0_MASK                               0xf
+#define DxF0x20_MemBase_OFFSET                                  4
+#define DxF0x20_MemBase_WIDTH                                   12
+#define DxF0x20_MemBase_MASK                                    0xfff0
+#define DxF0x20_Reserved_19_16_OFFSET                           16
+#define DxF0x20_Reserved_19_16_WIDTH                            4
+#define DxF0x20_Reserved_19_16_MASK                             0xf0000
+#define DxF0x20_MemLimit_OFFSET                                 20
+#define DxF0x20_MemLimit_WIDTH                                  12
+#define DxF0x20_MemLimit_MASK                                   0xfff00000
+
+/// DxF0x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                  MemBase:12; ///<
+    UINT32                                           Reserved_19_16:4 ; ///<
+    UINT32                                                 MemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x20_STRUCT;
+
+// **** DxF0x24 Register Definition ****
+// Address
+#define DxF0x24_ADDRESS                                         0x24
+
+// Type
+#define DxF0x24_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x24_PrefMemBaseR_OFFSET                             0
+#define DxF0x24_PrefMemBaseR_WIDTH                              4
+#define DxF0x24_PrefMemBaseR_MASK                               0xf
+#define DxF0x24_PrefMemBase_31_20__OFFSET                       4
+#define DxF0x24_PrefMemBase_31_20__WIDTH                        12
+#define DxF0x24_PrefMemBase_31_20__MASK                         0xfff0
+#define DxF0x24_PrefMemLimitR_OFFSET                            16
+#define DxF0x24_PrefMemLimitR_WIDTH                             4
+#define DxF0x24_PrefMemLimitR_MASK                              0xf0000
+#define DxF0x24_PrefMemLimit_OFFSET                             20
+#define DxF0x24_PrefMemLimit_WIDTH                              12
+#define DxF0x24_PrefMemLimit_MASK                               0xfff00000
+
+/// DxF0x24
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PrefMemBaseR:4 ; ///<
+    UINT32                                       PrefMemBase_31_20_:12; ///<
+    UINT32                                            PrefMemLimitR:4 ; ///<
+    UINT32                                             PrefMemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x24_STRUCT;
+
+// **** DxF0x28 Register Definition ****
+// Address
+#define DxF0x28_ADDRESS                                         0x28
+
+// Type
+#define DxF0x28_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x28_PrefMemBase_63_32__OFFSET                       0
+#define DxF0x28_PrefMemBase_63_32__WIDTH                        32
+#define DxF0x28_PrefMemBase_63_32__MASK                         0xffffffff
+
+/// DxF0x28
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PrefMemBase_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x28_STRUCT;
+
+// **** DxF0x2C Register Definition ****
+// Address
+#define DxF0x2C_ADDRESS                                         0x2c
+
+// Type
+#define DxF0x2C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x2C_PrefMemLimit_63_32__OFFSET                      0
+#define DxF0x2C_PrefMemLimit_63_32__WIDTH                       32
+#define DxF0x2C_PrefMemLimit_63_32__MASK                        0xffffffff
+
+/// DxF0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      PrefMemLimit_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x2C_STRUCT;
+
+// **** DxF0x30 Register Definition ****
+// Address
+#define DxF0x30_ADDRESS                                         0x30
+
+// Type
+#define DxF0x30_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x30_IOBase_31_16__OFFSET                            0
+#define DxF0x30_IOBase_31_16__WIDTH                             16
+#define DxF0x30_IOBase_31_16__MASK                              0xffff
+#define DxF0x30_IOLimit_31_16__OFFSET                           16
+#define DxF0x30_IOLimit_31_16__WIDTH                            16
+#define DxF0x30_IOLimit_31_16__MASK                             0xffff0000
+
+/// DxF0x30
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            IOBase_31_16_:16; ///<
+    UINT32                                           IOLimit_31_16_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x30_STRUCT;
+
+// **** DxF0x34 Register Definition ****
+// Address
+#define DxF0x34_ADDRESS                                         0x34
+
+// Type
+#define DxF0x34_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x34_CapPtr_OFFSET                                   0
+#define DxF0x34_CapPtr_WIDTH                                    8
+#define DxF0x34_CapPtr_MASK                                     0xff
+#define DxF0x34_Reserved_31_8_OFFSET                            8
+#define DxF0x34_Reserved_31_8_WIDTH                             24
+#define DxF0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// DxF0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x34_STRUCT;
+
+// **** DxF0x3C Register Definition ****
+// Address
+#define DxF0x3C_ADDRESS                                         0x3c
+
+// Type
+#define DxF0x3C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x3C_IntLine_OFFSET                                  0
+#define DxF0x3C_IntLine_WIDTH                                   8
+#define DxF0x3C_IntLine_MASK                                    0xff
+#define DxF0x3C_IntPin_OFFSET                                   8
+#define DxF0x3C_IntPin_WIDTH                                    3
+#define DxF0x3C_IntPin_MASK                                     0x700
+#define DxF0x3C_IntPinR_OFFSET                                  11
+#define DxF0x3C_IntPinR_WIDTH                                   5
+#define DxF0x3C_IntPinR_MASK                                    0xf800
+#define DxF0x3C_ParityResponseEn_OFFSET                         16
+#define DxF0x3C_ParityResponseEn_WIDTH                          1
+#define DxF0x3C_ParityResponseEn_MASK                           0x10000
+#define DxF0x3C_SerrEn_OFFSET                                   17
+#define DxF0x3C_SerrEn_WIDTH                                    1
+#define DxF0x3C_SerrEn_MASK                                     0x20000
+#define DxF0x3C_IsaEn_OFFSET                                    18
+#define DxF0x3C_IsaEn_WIDTH                                     1
+#define DxF0x3C_IsaEn_MASK                                      0x40000
+#define DxF0x3C_VgaEn_OFFSET                                    19
+#define DxF0x3C_VgaEn_WIDTH                                     1
+#define DxF0x3C_VgaEn_MASK                                      0x80000
+#define DxF0x3C_Vga16En_OFFSET                                  20
+#define DxF0x3C_Vga16En_WIDTH                                   1
+#define DxF0x3C_Vga16En_MASK                                    0x100000
+#define DxF0x3C_MasterAbortMode_OFFSET                          21
+#define DxF0x3C_MasterAbortMode_WIDTH                           1
+#define DxF0x3C_MasterAbortMode_MASK                            0x200000
+#define DxF0x3C_SecondaryBusReset_OFFSET                        22
+#define DxF0x3C_SecondaryBusReset_WIDTH                         1
+#define DxF0x3C_SecondaryBusReset_MASK                          0x400000
+#define DxF0x3C_FastB2BCap_OFFSET                               23
+#define DxF0x3C_FastB2BCap_WIDTH                                1
+#define DxF0x3C_FastB2BCap_MASK                                 0x800000
+#define DxF0x3C_Reserved_31_24_OFFSET                           24
+#define DxF0x3C_Reserved_31_24_WIDTH                            8
+#define DxF0x3C_Reserved_31_24_MASK                             0xff000000
+
+/// DxF0x3C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  IntLine:8 ; ///<
+    UINT32                                                   IntPin:3 ; ///<
+    UINT32                                                  IntPinR:5 ; ///<
+    UINT32                                         ParityResponseEn:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                    IsaEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                          MasterAbortMode:1 ; ///<
+    UINT32                                        SecondaryBusReset:1 ; ///<
+    UINT32                                               FastB2BCap:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x3C_STRUCT;
+
+// **** DxF0x50 Register Definition ****
+// Address
+#define DxF0x50_ADDRESS                                         0x50
+
+// Type
+#define DxF0x50_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x50_CapID_OFFSET                                    0
+#define DxF0x50_CapID_WIDTH                                     8
+#define DxF0x50_CapID_MASK                                      0xff
+#define DxF0x50_NextPtr_OFFSET                                  8
+#define DxF0x50_NextPtr_WIDTH                                   8
+#define DxF0x50_NextPtr_MASK                                    0xff00
+#define DxF0x50_Version_OFFSET                                  16
+#define DxF0x50_Version_WIDTH                                   3
+#define DxF0x50_Version_MASK                                    0x70000
+#define DxF0x50_PmeClock_OFFSET                                 19
+#define DxF0x50_PmeClock_WIDTH                                  1
+#define DxF0x50_PmeClock_MASK                                   0x80000
+#define DxF0x50_Reserved_20_20_OFFSET                           20
+#define DxF0x50_Reserved_20_20_WIDTH                            1
+#define DxF0x50_Reserved_20_20_MASK                             0x100000
+#define DxF0x50_DevSpecificInit_OFFSET                          21
+#define DxF0x50_DevSpecificInit_WIDTH                           1
+#define DxF0x50_DevSpecificInit_MASK                            0x200000
+#define DxF0x50_AuxCurrent_OFFSET                               22
+#define DxF0x50_AuxCurrent_WIDTH                                3
+#define DxF0x50_AuxCurrent_MASK                                 0x1c00000
+#define DxF0x50_D1Support_OFFSET                                25
+#define DxF0x50_D1Support_WIDTH                                 1
+#define DxF0x50_D1Support_MASK                                  0x2000000
+#define DxF0x50_D2Support_OFFSET                                26
+#define DxF0x50_D2Support_WIDTH                                 1
+#define DxF0x50_D2Support_MASK                                  0x4000000
+#define DxF0x50_PmeSupport_OFFSET                               27
+#define DxF0x50_PmeSupport_WIDTH                                5
+#define DxF0x50_PmeSupport_MASK                                 0xf8000000
+
+/// DxF0x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:3 ; ///<
+    UINT32                                                 PmeClock:1 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                          DevSpecificInit:1 ; ///<
+    UINT32                                               AuxCurrent:3 ; ///<
+    UINT32                                                D1Support:1 ; ///<
+    UINT32                                                D2Support:1 ; ///<
+    UINT32                                               PmeSupport:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x50_STRUCT;
+
+// **** DxF0x54 Register Definition ****
+// Address
+#define DxF0x54_ADDRESS                                         0x54
+
+// Type
+#define DxF0x54_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x54_PowerState_OFFSET                               0
+#define DxF0x54_PowerState_WIDTH                                2
+#define DxF0x54_PowerState_MASK                                 0x3
+#define DxF0x54_Reserved_2_2_OFFSET                             2
+#define DxF0x54_Reserved_2_2_WIDTH                              1
+#define DxF0x54_Reserved_2_2_MASK                               0x4
+#define DxF0x54_NoSoftReset_OFFSET                              3
+#define DxF0x54_NoSoftReset_WIDTH                               1
+#define DxF0x54_NoSoftReset_MASK                                0x8
+#define DxF0x54_Reserved_7_4_OFFSET                             4
+#define DxF0x54_Reserved_7_4_WIDTH                              4
+#define DxF0x54_Reserved_7_4_MASK                               0xf0
+#define DxF0x54_PmeEn_OFFSET                                    8
+#define DxF0x54_PmeEn_WIDTH                                     1
+#define DxF0x54_PmeEn_MASK                                      0x100
+#define DxF0x54_DataSelect_OFFSET                               9
+#define DxF0x54_DataSelect_WIDTH                                4
+#define DxF0x54_DataSelect_MASK                                 0x1e00
+#define DxF0x54_DataScale_OFFSET                                13
+#define DxF0x54_DataScale_WIDTH                                 2
+#define DxF0x54_DataScale_MASK                                  0x6000
+#define DxF0x54_PmeStatus_OFFSET                                15
+#define DxF0x54_PmeStatus_WIDTH                                 1
+#define DxF0x54_PmeStatus_MASK                                  0x8000
+#define DxF0x54_Reserved_21_16_OFFSET                           16
+#define DxF0x54_Reserved_21_16_WIDTH                            6
+#define DxF0x54_Reserved_21_16_MASK                             0x3f0000
+#define DxF0x54_B2B3Support_OFFSET                              22
+#define DxF0x54_B2B3Support_WIDTH                               1
+#define DxF0x54_B2B3Support_MASK                                0x400000
+#define DxF0x54_BusPwrEn_OFFSET                                 23
+#define DxF0x54_BusPwrEn_WIDTH                                  1
+#define DxF0x54_BusPwrEn_MASK                                   0x800000
+#define DxF0x54_PmeData_OFFSET                                  24
+#define DxF0x54_PmeData_WIDTH                                   8
+#define DxF0x54_PmeData_MASK                                    0xff000000
+
+/// DxF0x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PowerState:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                              NoSoftReset:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    PmeEn:1 ; ///<
+    UINT32                                               DataSelect:4 ; ///<
+    UINT32                                                DataScale:2 ; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                           Reserved_21_16:6 ; ///<
+    UINT32                                              B2B3Support:1 ; ///<
+    UINT32                                                 BusPwrEn:1 ; ///<
+    UINT32                                                  PmeData:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x54_STRUCT;
+
+// **** DxF0x58 Register Definition ****
+// Address
+#define DxF0x58_ADDRESS                                         0x58
+
+// Type
+#define DxF0x58_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x58_CapID_OFFSET                                    0
+#define DxF0x58_CapID_WIDTH                                     8
+#define DxF0x58_CapID_MASK                                      0xff
+#define DxF0x58_NextPtr_OFFSET                                  8
+#define DxF0x58_NextPtr_WIDTH                                   8
+#define DxF0x58_NextPtr_MASK                                    0xff00
+#define DxF0x58_Version_OFFSET                                  16
+#define DxF0x58_Version_WIDTH                                   4
+#define DxF0x58_Version_MASK                                    0xf0000
+#define DxF0x58_DeviceType_OFFSET                               20
+#define DxF0x58_DeviceType_WIDTH                                4
+#define DxF0x58_DeviceType_MASK                                 0xf00000
+#define DxF0x58_SlotImplemented_OFFSET                          24
+#define DxF0x58_SlotImplemented_WIDTH                           1
+#define DxF0x58_SlotImplemented_MASK                            0x1000000
+#define DxF0x58_IntMessageNum_OFFSET                            25
+#define DxF0x58_IntMessageNum_WIDTH                             5
+#define DxF0x58_IntMessageNum_MASK                              0x3e000000
+#define DxF0x58_Reserved_31_30_OFFSET                           30
+#define DxF0x58_Reserved_31_30_WIDTH                            2
+#define DxF0x58_Reserved_31_30_MASK                             0xc0000000
+
+/// DxF0x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:4 ; ///<
+    UINT32                                               DeviceType:4 ; ///<
+    UINT32                                          SlotImplemented:1 ; ///<
+    UINT32                                            IntMessageNum:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x58_STRUCT;
+
+// **** DxF0x5C Register Definition ****
+// Address
+#define DxF0x5C_ADDRESS                                         0x5c
+
+// Type
+#define DxF0x5C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x5C_MaxPayloadSupport_OFFSET                        0
+#define DxF0x5C_MaxPayloadSupport_WIDTH                         3
+#define DxF0x5C_MaxPayloadSupport_MASK                          0x7
+#define DxF0x5C_PhantomFunc_OFFSET                              3
+#define DxF0x5C_PhantomFunc_WIDTH                               2
+#define DxF0x5C_PhantomFunc_MASK                                0x18
+#define DxF0x5C_ExtendedTag_OFFSET                              5
+#define DxF0x5C_ExtendedTag_WIDTH                               1
+#define DxF0x5C_ExtendedTag_MASK                                0x20
+#define DxF0x5C_L0SAcceptableLatency_OFFSET                     6
+#define DxF0x5C_L0SAcceptableLatency_WIDTH                      3
+#define DxF0x5C_L0SAcceptableLatency_MASK                       0x1c0
+#define DxF0x5C_L1AcceptableLatency_OFFSET                      9
+#define DxF0x5C_L1AcceptableLatency_WIDTH                       3
+#define DxF0x5C_L1AcceptableLatency_MASK                        0xe00
+#define DxF0x5C_Reserved_14_12_OFFSET                           12
+#define DxF0x5C_Reserved_14_12_WIDTH                            3
+#define DxF0x5C_Reserved_14_12_MASK                             0x7000
+#define DxF0x5C_RoleBasedErrReporting_OFFSET                    15
+#define DxF0x5C_RoleBasedErrReporting_WIDTH                     1
+#define DxF0x5C_RoleBasedErrReporting_MASK                      0x8000
+#define DxF0x5C_Reserved_17_16_OFFSET                           16
+#define DxF0x5C_Reserved_17_16_WIDTH                            2
+#define DxF0x5C_Reserved_17_16_MASK                             0x30000
+#define DxF0x5C_CapturedSlotPowerLimit_OFFSET                   18
+#define DxF0x5C_CapturedSlotPowerLimit_WIDTH                    8
+#define DxF0x5C_CapturedSlotPowerLimit_MASK                     0x3fc0000
+#define DxF0x5C_CapturedSlotPowerScale_OFFSET                   26
+#define DxF0x5C_CapturedSlotPowerScale_WIDTH                    2
+#define DxF0x5C_CapturedSlotPowerScale_MASK                     0xc000000
+#define DxF0x5C_FlrCapable_OFFSET                               28
+#define DxF0x5C_FlrCapable_WIDTH                                1
+#define DxF0x5C_FlrCapable_MASK                                 0x10000000
+#define DxF0x5C_Reserved_31_29_OFFSET                           29
+#define DxF0x5C_Reserved_31_29_WIDTH                            3
+#define DxF0x5C_Reserved_31_29_MASK                             0xe0000000
+
+/// DxF0x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        MaxPayloadSupport:3 ; ///<
+    UINT32                                              PhantomFunc:2 ; ///<
+    UINT32                                              ExtendedTag:1 ; ///<
+    UINT32                                     L0SAcceptableLatency:3 ; ///<
+    UINT32                                      L1AcceptableLatency:3 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                    RoleBasedErrReporting:1 ; ///<
+    UINT32                                           Reserved_17_16:2 ; ///<
+    UINT32                                   CapturedSlotPowerLimit:8 ; ///<
+    UINT32                                   CapturedSlotPowerScale:2 ; ///<
+    UINT32                                               FlrCapable:1 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x5C_STRUCT;
+
+// **** DxF0x60 Register Definition ****
+// Address
+#define DxF0x60_ADDRESS                                         0x60
+
+// Type
+#define DxF0x60_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x60_CorrErrEn_OFFSET                                0
+#define DxF0x60_CorrErrEn_WIDTH                                 1
+#define DxF0x60_CorrErrEn_MASK                                  0x1
+#define DxF0x60_NonFatalErrEn_OFFSET                            1
+#define DxF0x60_NonFatalErrEn_WIDTH                             1
+#define DxF0x60_NonFatalErrEn_MASK                              0x2
+#define DxF0x60_FatalErrEn_OFFSET                               2
+#define DxF0x60_FatalErrEn_WIDTH                                1
+#define DxF0x60_FatalErrEn_MASK                                 0x4
+#define DxF0x60_UsrReportEn_OFFSET                              3
+#define DxF0x60_UsrReportEn_WIDTH                               1
+#define DxF0x60_UsrReportEn_MASK                                0x8
+#define DxF0x60_RelaxedOrdEn_OFFSET                             4
+#define DxF0x60_RelaxedOrdEn_WIDTH                              1
+#define DxF0x60_RelaxedOrdEn_MASK                               0x10
+#define DxF0x60_MaxPayloadSize_OFFSET                           5
+#define DxF0x60_MaxPayloadSize_WIDTH                            3
+#define DxF0x60_MaxPayloadSize_MASK                             0xe0
+#define DxF0x60_ExtendedTagEn_OFFSET                            8
+#define DxF0x60_ExtendedTagEn_WIDTH                             1
+#define DxF0x60_ExtendedTagEn_MASK                              0x100
+#define DxF0x60_PhantomFuncEn_OFFSET                            9
+#define DxF0x60_PhantomFuncEn_WIDTH                             1
+#define DxF0x60_PhantomFuncEn_MASK                              0x200
+#define DxF0x60_AuxPowerPmEn_OFFSET                             10
+#define DxF0x60_AuxPowerPmEn_WIDTH                              1
+#define DxF0x60_AuxPowerPmEn_MASK                               0x400
+#define DxF0x60_NoSnoopEnable_OFFSET                            11
+#define DxF0x60_NoSnoopEnable_WIDTH                             1
+#define DxF0x60_NoSnoopEnable_MASK                              0x800
+#define DxF0x60_MaxRequestSize_OFFSET                           12
+#define DxF0x60_MaxRequestSize_WIDTH                            3
+#define DxF0x60_MaxRequestSize_MASK                             0x7000
+#define DxF0x60_BridgeCfgRetryEn_OFFSET                         15
+#define DxF0x60_BridgeCfgRetryEn_WIDTH                          1
+#define DxF0x60_BridgeCfgRetryEn_MASK                           0x8000
+#define DxF0x60_CorrErr_OFFSET                                  16
+#define DxF0x60_CorrErr_WIDTH                                   1
+#define DxF0x60_CorrErr_MASK                                    0x10000
+#define DxF0x60_NonFatalErr_OFFSET                              17
+#define DxF0x60_NonFatalErr_WIDTH                               1
+#define DxF0x60_NonFatalErr_MASK                                0x20000
+#define DxF0x60_FatalErr_OFFSET                                 18
+#define DxF0x60_FatalErr_WIDTH                                  1
+#define DxF0x60_FatalErr_MASK                                   0x40000
+#define DxF0x60_UsrDetected_OFFSET                              19
+#define DxF0x60_UsrDetected_WIDTH                               1
+#define DxF0x60_UsrDetected_MASK                                0x80000
+#define DxF0x60_AuxPwr_OFFSET                                   20
+#define DxF0x60_AuxPwr_WIDTH                                    1
+#define DxF0x60_AuxPwr_MASK                                     0x100000
+#define DxF0x60_TransactionsPending_OFFSET                      21
+#define DxF0x60_TransactionsPending_WIDTH                       1
+#define DxF0x60_TransactionsPending_MASK                        0x200000
+#define DxF0x60_Reserved_31_22_OFFSET                           22
+#define DxF0x60_Reserved_31_22_WIDTH                            10
+#define DxF0x60_Reserved_31_22_MASK                             0xffc00000
+
+/// DxF0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CorrErrEn:1 ; ///<
+    UINT32                                            NonFatalErrEn:1 ; ///<
+    UINT32                                               FatalErrEn:1 ; ///<
+    UINT32                                              UsrReportEn:1 ; ///<
+    UINT32                                             RelaxedOrdEn:1 ; ///<
+    UINT32                                           MaxPayloadSize:3 ; ///<
+    UINT32                                            ExtendedTagEn:1 ; ///<
+    UINT32                                            PhantomFuncEn:1 ; ///<
+    UINT32                                             AuxPowerPmEn:1 ; ///<
+    UINT32                                            NoSnoopEnable:1 ; ///<
+    UINT32                                           MaxRequestSize:3 ; ///<
+    UINT32                                         BridgeCfgRetryEn:1 ; ///<
+    UINT32                                                  CorrErr:1 ; ///<
+    UINT32                                              NonFatalErr:1 ; ///<
+    UINT32                                                 FatalErr:1 ; ///<
+    UINT32                                              UsrDetected:1 ; ///<
+    UINT32                                                   AuxPwr:1 ; ///<
+    UINT32                                      TransactionsPending:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x60_STRUCT;
+
+
+// **** DxF0x68 Register Definition ****
+// Address
+#define DxF0x68_ADDRESS                                         0x68
+
+// Type
+#define DxF0x68_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x68_PmControl_OFFSET                                0
+#define DxF0x68_PmControl_WIDTH                                 2
+#define DxF0x68_PmControl_MASK                                  0x3
+#define DxF0x68_Reserved_2_2_OFFSET                             2
+#define DxF0x68_Reserved_2_2_WIDTH                              1
+#define DxF0x68_Reserved_2_2_MASK                               0x4
+#define DxF0x68_ReadCplBoundary_OFFSET                          3
+#define DxF0x68_ReadCplBoundary_WIDTH                           1
+#define DxF0x68_ReadCplBoundary_MASK                            0x8
+#define DxF0x68_LinkDis_OFFSET                                  4
+#define DxF0x68_LinkDis_WIDTH                                   1
+#define DxF0x68_LinkDis_MASK                                    0x10
+#define DxF0x68_RetrainLink_OFFSET                              5
+#define DxF0x68_RetrainLink_WIDTH                               1
+#define DxF0x68_RetrainLink_MASK                                0x20
+#define DxF0x68_CommonClockCfg_OFFSET                           6
+#define DxF0x68_CommonClockCfg_WIDTH                            1
+#define DxF0x68_CommonClockCfg_MASK                             0x40
+#define DxF0x68_ExtendedSync_OFFSET                             7
+#define DxF0x68_ExtendedSync_WIDTH                              1
+#define DxF0x68_ExtendedSync_MASK                               0x80
+#define DxF0x68_ClockPowerManagementEn_OFFSET                   8
+#define DxF0x68_ClockPowerManagementEn_WIDTH                    1
+#define DxF0x68_ClockPowerManagementEn_MASK                     0x100
+#define DxF0x68_HWAutonomousWidthDisable_OFFSET                 9
+#define DxF0x68_HWAutonomousWidthDisable_WIDTH                  1
+#define DxF0x68_HWAutonomousWidthDisable_MASK                   0x200
+#define DxF0x68_LinkBWManagementEn_OFFSET                       10
+#define DxF0x68_LinkBWManagementEn_WIDTH                        1
+#define DxF0x68_LinkBWManagementEn_MASK                         0x400
+#define DxF0x68_LinkAutonomousBWIntEn_OFFSET                    11
+#define DxF0x68_LinkAutonomousBWIntEn_WIDTH                     1
+#define DxF0x68_LinkAutonomousBWIntEn_MASK                      0x800
+#define DxF0x68_Reserved_15_12_OFFSET                           12
+#define DxF0x68_Reserved_15_12_WIDTH                            4
+#define DxF0x68_Reserved_15_12_MASK                             0xf000
+#define DxF0x68_LinkSpeed_OFFSET                                16
+#define DxF0x68_LinkSpeed_WIDTH                                 4
+#define DxF0x68_LinkSpeed_MASK                                  0xf0000
+#define DxF0x68_NegotiatedLinkWidth_OFFSET                      20
+#define DxF0x68_NegotiatedLinkWidth_WIDTH                       6
+#define DxF0x68_NegotiatedLinkWidth_MASK                        0x3f00000
+#define DxF0x68_Reserved_26_26_OFFSET                           26
+#define DxF0x68_Reserved_26_26_WIDTH                            1
+#define DxF0x68_Reserved_26_26_MASK                             0x4000000
+#define DxF0x68_LinkTraining_OFFSET                             27
+#define DxF0x68_LinkTraining_WIDTH                              1
+#define DxF0x68_LinkTraining_MASK                               0x8000000
+#define DxF0x68_SlotClockCfg_OFFSET                             28
+#define DxF0x68_SlotClockCfg_WIDTH                              1
+#define DxF0x68_SlotClockCfg_MASK                               0x10000000
+#define DxF0x68_DlActive_OFFSET                                 29
+#define DxF0x68_DlActive_WIDTH                                  1
+#define DxF0x68_DlActive_MASK                                   0x20000000
+#define DxF0x68_LinkBWManagementStatus_OFFSET                   30
+#define DxF0x68_LinkBWManagementStatus_WIDTH                    1
+#define DxF0x68_LinkBWManagementStatus_MASK                     0x40000000
+#define DxF0x68_LinkAutonomousBWStatus_OFFSET                   31
+#define DxF0x68_LinkAutonomousBWStatus_WIDTH                    1
+#define DxF0x68_LinkAutonomousBWStatus_MASK                     0x80000000
+
+/// DxF0x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PmControl:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          ReadCplBoundary:1 ; ///<
+    UINT32                                                  LinkDis:1 ; ///<
+    UINT32                                              RetrainLink:1 ; ///<
+    UINT32                                           CommonClockCfg:1 ; ///<
+    UINT32                                             ExtendedSync:1 ; ///<
+    UINT32                                   ClockPowerManagementEn:1 ; ///<
+    UINT32                                 HWAutonomousWidthDisable:1 ; ///<
+    UINT32                                       LinkBWManagementEn:1 ; ///<
+    UINT32                                    LinkAutonomousBWIntEn:1 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                LinkSpeed:4 ; ///<
+    UINT32                                      NegotiatedLinkWidth:6 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                             LinkTraining:1 ; ///<
+    UINT32                                             SlotClockCfg:1 ; ///<
+    UINT32                                                 DlActive:1 ; ///<
+    UINT32                                   LinkBWManagementStatus:1 ; ///<
+    UINT32                                   LinkAutonomousBWStatus:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x68_STRUCT;
+
+// **** DxF0x6C Register Definition ****
+// Address
+#define DxF0x6C_ADDRESS                                         0x6c
+
+// Type
+#define DxF0x6C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x6C_AttnButtonPresent_OFFSET                        0
+#define DxF0x6C_AttnButtonPresent_WIDTH                         1
+#define DxF0x6C_AttnButtonPresent_MASK                          0x1
+#define DxF0x6C_PwrControllerPresent_OFFSET                     1
+#define DxF0x6C_PwrControllerPresent_WIDTH                      1
+#define DxF0x6C_PwrControllerPresent_MASK                       0x2
+#define DxF0x6C_MrlSensorPresent_OFFSET                         2
+#define DxF0x6C_MrlSensorPresent_WIDTH                          1
+#define DxF0x6C_MrlSensorPresent_MASK                           0x4
+#define DxF0x6C_AttnIndicatorPresent_OFFSET                     3
+#define DxF0x6C_AttnIndicatorPresent_WIDTH                      1
+#define DxF0x6C_AttnIndicatorPresent_MASK                       0x8
+#define DxF0x6C_PwrIndicatorPresent_OFFSET                      4
+#define DxF0x6C_PwrIndicatorPresent_WIDTH                       1
+#define DxF0x6C_PwrIndicatorPresent_MASK                        0x10
+#define DxF0x6C_HotplugSurprise_OFFSET                          5
+#define DxF0x6C_HotplugSurprise_WIDTH                           1
+#define DxF0x6C_HotplugSurprise_MASK                            0x20
+#define DxF0x6C_HotplugCapable_OFFSET                           6
+#define DxF0x6C_HotplugCapable_WIDTH                            1
+#define DxF0x6C_HotplugCapable_MASK                             0x40
+#define DxF0x6C_SlotPwrLimitValue_OFFSET                        7
+#define DxF0x6C_SlotPwrLimitValue_WIDTH                         8
+#define DxF0x6C_SlotPwrLimitValue_MASK                          0x7f80
+#define DxF0x6C_SlotPwrLimitScale_OFFSET                        15
+#define DxF0x6C_SlotPwrLimitScale_WIDTH                         2
+#define DxF0x6C_SlotPwrLimitScale_MASK                          0x18000
+#define DxF0x6C_ElecMechIlPresent_OFFSET                        17
+#define DxF0x6C_ElecMechIlPresent_WIDTH                         1
+#define DxF0x6C_ElecMechIlPresent_MASK                          0x20000
+#define DxF0x6C_NoCmdCplSupport_OFFSET                          18
+#define DxF0x6C_NoCmdCplSupport_WIDTH                           1
+#define DxF0x6C_NoCmdCplSupport_MASK                            0x40000
+#define DxF0x6C_PhysicalSlotNumber_OFFSET                       19
+#define DxF0x6C_PhysicalSlotNumber_WIDTH                        13
+#define DxF0x6C_PhysicalSlotNumber_MASK                         0xfff80000
+
+/// DxF0x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AttnButtonPresent:1 ; ///<
+    UINT32                                     PwrControllerPresent:1 ; ///<
+    UINT32                                         MrlSensorPresent:1 ; ///<
+    UINT32                                     AttnIndicatorPresent:1 ; ///<
+    UINT32                                      PwrIndicatorPresent:1 ; ///<
+    UINT32                                          HotplugSurprise:1 ; ///<
+    UINT32                                           HotplugCapable:1 ; ///<
+    UINT32                                        SlotPwrLimitValue:8 ; ///<
+    UINT32                                        SlotPwrLimitScale:2 ; ///<
+    UINT32                                        ElecMechIlPresent:1 ; ///<
+    UINT32                                          NoCmdCplSupport:1 ; ///<
+    UINT32                                       PhysicalSlotNumber:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x6C_STRUCT;
+
+// **** DxF0x70 Register Definition ****
+// Address
+#define DxF0x70_ADDRESS                                         0x70
+
+// Type
+#define DxF0x70_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x70_AttnButtonPressedEn_OFFSET                      0
+#define DxF0x70_AttnButtonPressedEn_WIDTH                       1
+#define DxF0x70_AttnButtonPressedEn_MASK                        0x1
+#define DxF0x70_PwrFaultDetectedEn_OFFSET                       1
+#define DxF0x70_PwrFaultDetectedEn_WIDTH                        1
+#define DxF0x70_PwrFaultDetectedEn_MASK                         0x2
+#define DxF0x70_MrlSensorChangedEn_OFFSET                       2
+#define DxF0x70_MrlSensorChangedEn_WIDTH                        1
+#define DxF0x70_MrlSensorChangedEn_MASK                         0x4
+#define DxF0x70_PresenceDetectChangedEn_OFFSET                  3
+#define DxF0x70_PresenceDetectChangedEn_WIDTH                   1
+#define DxF0x70_PresenceDetectChangedEn_MASK                    0x8
+#define DxF0x70_CmdCplIntrEn_OFFSET                             4
+#define DxF0x70_CmdCplIntrEn_WIDTH                              1
+#define DxF0x70_CmdCplIntrEn_MASK                               0x10
+#define DxF0x70_HotplugIntrEn_OFFSET                            5
+#define DxF0x70_HotplugIntrEn_WIDTH                             1
+#define DxF0x70_HotplugIntrEn_MASK                              0x20
+#define DxF0x70_AttnIndicatorControl_OFFSET                     6
+#define DxF0x70_AttnIndicatorControl_WIDTH                      2
+#define DxF0x70_AttnIndicatorControl_MASK                       0xc0
+#define DxF0x70_PwrIndicatorCntl_OFFSET                         8
+#define DxF0x70_PwrIndicatorCntl_WIDTH                          2
+#define DxF0x70_PwrIndicatorCntl_MASK                           0x300
+#define DxF0x70_PwrControllerCntl_OFFSET                        10
+#define DxF0x70_PwrControllerCntl_WIDTH                         1
+#define DxF0x70_PwrControllerCntl_MASK                          0x400
+#define DxF0x70_ElecMechIlCntl_OFFSET                           11
+#define DxF0x70_ElecMechIlCntl_WIDTH                            1
+#define DxF0x70_ElecMechIlCntl_MASK                             0x800
+#define DxF0x70_DlStateChangedEn_OFFSET                         12
+#define DxF0x70_DlStateChangedEn_WIDTH                          1
+#define DxF0x70_DlStateChangedEn_MASK                           0x1000
+#define DxF0x70_Reserved_15_13_OFFSET                           13
+#define DxF0x70_Reserved_15_13_WIDTH                            3
+#define DxF0x70_Reserved_15_13_MASK                             0xe000
+#define DxF0x70_AttnButtonPressed_OFFSET                        16
+#define DxF0x70_AttnButtonPressed_WIDTH                         1
+#define DxF0x70_AttnButtonPressed_MASK                          0x10000
+#define DxF0x70_PwrFaultDetected_OFFSET                         17
+#define DxF0x70_PwrFaultDetected_WIDTH                          1
+#define DxF0x70_PwrFaultDetected_MASK                           0x20000
+#define DxF0x70_MrlSensorChanged_OFFSET                         18
+#define DxF0x70_MrlSensorChanged_WIDTH                          1
+#define DxF0x70_MrlSensorChanged_MASK                           0x40000
+#define DxF0x70_PresenceDetectChanged_OFFSET                    19
+#define DxF0x70_PresenceDetectChanged_WIDTH                     1
+#define DxF0x70_PresenceDetectChanged_MASK                      0x80000
+#define DxF0x70_CmdCpl_OFFSET                                   20
+#define DxF0x70_CmdCpl_WIDTH                                    1
+#define DxF0x70_CmdCpl_MASK                                     0x100000
+#define DxF0x70_MrlSensorState_OFFSET                           21
+#define DxF0x70_MrlSensorState_WIDTH                            1
+#define DxF0x70_MrlSensorState_MASK                             0x200000
+#define DxF0x70_PresenceDetectState_OFFSET                      22
+#define DxF0x70_PresenceDetectState_WIDTH                       1
+#define DxF0x70_PresenceDetectState_MASK                        0x400000
+#define DxF0x70_ElecMechIlSts_OFFSET                            23
+#define DxF0x70_ElecMechIlSts_WIDTH                             1
+#define DxF0x70_ElecMechIlSts_MASK                              0x800000
+#define DxF0x70_DlStateChanged_OFFSET                           24
+#define DxF0x70_DlStateChanged_WIDTH                            1
+#define DxF0x70_DlStateChanged_MASK                             0x1000000
+#define DxF0x70_Reserved_31_25_OFFSET                           25
+#define DxF0x70_Reserved_31_25_WIDTH                            7
+#define DxF0x70_Reserved_31_25_MASK                             0xfe000000
+
+/// DxF0x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      AttnButtonPressedEn:1 ; ///<
+    UINT32                                       PwrFaultDetectedEn:1 ; ///<
+    UINT32                                       MrlSensorChangedEn:1 ; ///<
+    UINT32                                  PresenceDetectChangedEn:1 ; ///<
+    UINT32                                             CmdCplIntrEn:1 ; ///<
+    UINT32                                            HotplugIntrEn:1 ; ///<
+    UINT32                                     AttnIndicatorControl:2 ; ///<
+    UINT32                                         PwrIndicatorCntl:2 ; ///<
+    UINT32                                        PwrControllerCntl:1 ; ///<
+    UINT32                                           ElecMechIlCntl:1 ; ///<
+    UINT32                                         DlStateChangedEn:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                        AttnButtonPressed:1 ; ///<
+    UINT32                                         PwrFaultDetected:1 ; ///<
+    UINT32                                         MrlSensorChanged:1 ; ///<
+    UINT32                                    PresenceDetectChanged:1 ; ///<
+    UINT32                                                   CmdCpl:1 ; ///<
+    UINT32                                           MrlSensorState:1 ; ///<
+    UINT32                                      PresenceDetectState:1 ; ///<
+    UINT32                                            ElecMechIlSts:1 ; ///<
+    UINT32                                           DlStateChanged:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x70_STRUCT;
+
+// **** DxF0x74 Register Definition ****
+// Address
+#define DxF0x74_ADDRESS                                         0x74
+
+// Type
+#define DxF0x74_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x74_SerrOnCorrErrEn_OFFSET                          0
+#define DxF0x74_SerrOnCorrErrEn_WIDTH                           1
+#define DxF0x74_SerrOnCorrErrEn_MASK                            0x1
+#define DxF0x74_SerrOnNonFatalErrEn_OFFSET                      1
+#define DxF0x74_SerrOnNonFatalErrEn_WIDTH                       1
+#define DxF0x74_SerrOnNonFatalErrEn_MASK                        0x2
+#define DxF0x74_SerrOnFatalErrEn_OFFSET                         2
+#define DxF0x74_SerrOnFatalErrEn_WIDTH                          1
+#define DxF0x74_SerrOnFatalErrEn_MASK                           0x4
+#define DxF0x74_PmIntEn_OFFSET                                  3
+#define DxF0x74_PmIntEn_WIDTH                                   1
+#define DxF0x74_PmIntEn_MASK                                    0x8
+#define DxF0x74_CrsSoftVisibilityEn_OFFSET                      4
+#define DxF0x74_CrsSoftVisibilityEn_WIDTH                       1
+#define DxF0x74_CrsSoftVisibilityEn_MASK                        0x10
+#define DxF0x74_Reserved_15_5_OFFSET                            5
+#define DxF0x74_Reserved_15_5_WIDTH                             11
+#define DxF0x74_Reserved_15_5_MASK                              0xffe0
+#define DxF0x74_CrsSoftVisibility_OFFSET                        16
+#define DxF0x74_CrsSoftVisibility_WIDTH                         1
+#define DxF0x74_CrsSoftVisibility_MASK                          0x10000
+#define DxF0x74_Reserved_31_17_OFFSET                           17
+#define DxF0x74_Reserved_31_17_WIDTH                            15
+#define DxF0x74_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          SerrOnCorrErrEn:1 ; ///<
+    UINT32                                      SerrOnNonFatalErrEn:1 ; ///<
+    UINT32                                         SerrOnFatalErrEn:1 ; ///<
+    UINT32                                                  PmIntEn:1 ; ///<
+    UINT32                                      CrsSoftVisibilityEn:1 ; ///<
+    UINT32                                            Reserved_15_5:11; ///<
+    UINT32                                        CrsSoftVisibility:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x74_STRUCT;
+
+// **** DxF0x78 Register Definition ****
+// Address
+#define DxF0x78_ADDRESS                                         0x78
+
+// Type
+#define DxF0x78_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x78_PmeRequestorId_OFFSET                           0
+#define DxF0x78_PmeRequestorId_WIDTH                            16
+#define DxF0x78_PmeRequestorId_MASK                             0xffff
+#define DxF0x78_PmeStatus_OFFSET                                16
+#define DxF0x78_PmeStatus_WIDTH                                 1
+#define DxF0x78_PmeStatus_MASK                                  0x10000
+#define DxF0x78_PmePending_OFFSET                               17
+#define DxF0x78_PmePending_WIDTH                                1
+#define DxF0x78_PmePending_MASK                                 0x20000
+#define DxF0x78_Reserved_31_18_OFFSET                           18
+#define DxF0x78_Reserved_31_18_WIDTH                            14
+#define DxF0x78_Reserved_31_18_MASK                             0xfffc0000
+
+/// DxF0x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PmeRequestorId:16; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                               PmePending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x78_STRUCT;
+
+// **** DxF0x7C Register Definition ****
+// Address
+#define DxF0x7C_ADDRESS                                         0x7c
+
+// Type
+#define DxF0x7C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x7C_CplTimeoutRangeSup_OFFSET                       0
+#define DxF0x7C_CplTimeoutRangeSup_WIDTH                        4
+#define DxF0x7C_CplTimeoutRangeSup_MASK                         0xf
+#define DxF0x7C_CplTimeoutDisSup_OFFSET                         4
+#define DxF0x7C_CplTimeoutDisSup_WIDTH                          1
+#define DxF0x7C_CplTimeoutDisSup_MASK                           0x10
+#define DxF0x7C_AriForwardingSupported_OFFSET                   5
+#define DxF0x7C_AriForwardingSupported_WIDTH                    1
+#define DxF0x7C_AriForwardingSupported_MASK                     0x20
+#define DxF0x7C_Reserved_31_6_OFFSET                            6
+#define DxF0x7C_Reserved_31_6_WIDTH                             26
+#define DxF0x7C_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       CplTimeoutRangeSup:4 ; ///<
+    UINT32                                         CplTimeoutDisSup:1 ; ///<
+    UINT32                                   AriForwardingSupported:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x7C_STRUCT;
+
+// **** DxF0x80 Register Definition ****
+// Address
+#define DxF0x80_ADDRESS                                         0x80
+
+// Type
+#define DxF0x80_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x80_CplTimeoutValue_OFFSET                          0
+#define DxF0x80_CplTimeoutValue_WIDTH                           4
+#define DxF0x80_CplTimeoutValue_MASK                            0xf
+#define DxF0x80_CplTimeoutDis_OFFSET                            4
+#define DxF0x80_CplTimeoutDis_WIDTH                             1
+#define DxF0x80_CplTimeoutDis_MASK                              0x10
+#define DxF0x80_AriForwardingEn_OFFSET                          5
+#define DxF0x80_AriForwardingEn_WIDTH                           1
+#define DxF0x80_AriForwardingEn_MASK                            0x20
+#define DxF0x80_Reserved_31_6_OFFSET                            6
+#define DxF0x80_Reserved_31_6_WIDTH                             26
+#define DxF0x80_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CplTimeoutValue:4 ; ///<
+    UINT32                                            CplTimeoutDis:1 ; ///<
+    UINT32                                          AriForwardingEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x80_STRUCT;
+
+// **** DxF0x84 Register Definition ****
+// Address
+#define DxF0x84_ADDRESS                                         0x84
+
+// Type
+#define DxF0x84_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x84_Reserved_31_0_OFFSET                            0
+#define DxF0x84_Reserved_31_0_WIDTH                             32
+#define DxF0x84_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x84_STRUCT;
+
+// **** DxF0x88 Register Definition ****
+// Address
+#define DxF0x88_ADDRESS                                         0x88
+
+// Type
+#define DxF0x88_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x88_TargetLinkSpeed_OFFSET                          0
+#define DxF0x88_TargetLinkSpeed_WIDTH                           4
+#define DxF0x88_TargetLinkSpeed_MASK                            0xf
+#define DxF0x88_EnterCompliance_OFFSET                          4
+#define DxF0x88_EnterCompliance_WIDTH                           1
+#define DxF0x88_EnterCompliance_MASK                            0x10
+#define DxF0x88_HwAutonomousSpeedDisable_OFFSET                 5
+#define DxF0x88_HwAutonomousSpeedDisable_WIDTH                  1
+#define DxF0x88_HwAutonomousSpeedDisable_MASK                   0x20
+#define DxF0x88_SelectableDeemphasis_OFFSET                     6
+#define DxF0x88_SelectableDeemphasis_WIDTH                      1
+#define DxF0x88_SelectableDeemphasis_MASK                       0x40
+#define DxF0x88_XmitMargin_OFFSET                               7
+#define DxF0x88_XmitMargin_WIDTH                                3
+#define DxF0x88_XmitMargin_MASK                                 0x380
+#define DxF0x88_EnterModCompliance_OFFSET                       10
+#define DxF0x88_EnterModCompliance_WIDTH                        1
+#define DxF0x88_EnterModCompliance_MASK                         0x400
+#define DxF0x88_ComplianceSOS_OFFSET                            11
+#define DxF0x88_ComplianceSOS_WIDTH                             1
+#define DxF0x88_ComplianceSOS_MASK                              0x800
+#define DxF0x88_ComplianceDeemphasis_OFFSET                     12
+#define DxF0x88_ComplianceDeemphasis_WIDTH                      1
+#define DxF0x88_ComplianceDeemphasis_MASK                       0x1000
+#define DxF0x88_Reserved_15_13_OFFSET                           13
+#define DxF0x88_Reserved_15_13_WIDTH                            3
+#define DxF0x88_Reserved_15_13_MASK                             0xe000
+#define DxF0x88_CurDeemphasisLevel_OFFSET                       16
+#define DxF0x88_CurDeemphasisLevel_WIDTH                        1
+#define DxF0x88_CurDeemphasisLevel_MASK                         0x10000
+#define DxF0x88_Reserved_31_17_OFFSET                           17
+#define DxF0x88_Reserved_31_17_WIDTH                            15
+#define DxF0x88_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TargetLinkSpeed:4 ; ///<
+    UINT32                                          EnterCompliance:1 ; ///<
+    UINT32                                 HwAutonomousSpeedDisable:1 ; ///<
+    UINT32                                     SelectableDeemphasis:1 ; ///<
+    UINT32                                               XmitMargin:3 ; ///<
+    UINT32                                       EnterModCompliance:1 ; ///<
+    UINT32                                            ComplianceSOS:1 ; ///<
+    UINT32                                     ComplianceDeemphasis:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                       CurDeemphasisLevel:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x88_STRUCT;
+
+// **** DxF0x8C Register Definition ****
+// Address
+#define DxF0x8C_ADDRESS                                         0x8c
+
+// Type
+#define DxF0x8C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x8C_Reserved_31_0_OFFSET                            0
+#define DxF0x8C_Reserved_31_0_WIDTH                             32
+#define DxF0x8C_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x8C_STRUCT;
+
+// **** DxF0x90 Register Definition ****
+// Address
+#define DxF0x90_ADDRESS                                         0x90
+
+// Type
+#define DxF0x90_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x90_Reserved_31_0_OFFSET                            0
+#define DxF0x90_Reserved_31_0_WIDTH                             32
+#define DxF0x90_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x90_STRUCT;
+
+// **** DxF0x128 Register Definition ****
+// Address
+#define DxF0x128_ADDRESS                                        0x128
+
+// Type
+#define DxF0x128_TYPE                                           TYPE_D4F0
+// Field Data
+#define DxF0x128_Reserved_15_0_OFFSET                           0
+#define DxF0x128_Reserved_15_0_WIDTH                            16
+#define DxF0x128_Reserved_15_0_MASK                             0xffff
+#define DxF0x128_PortArbTableStatus_OFFSET                      16
+#define DxF0x128_PortArbTableStatus_WIDTH                       1
+#define DxF0x128_PortArbTableStatus_MASK                        0x10000
+#define DxF0x128_VcNegotiationPending_OFFSET                    17
+#define DxF0x128_VcNegotiationPending_WIDTH                     1
+#define DxF0x128_VcNegotiationPending_MASK                      0x20000
+#define DxF0x128_Reserved_31_18_OFFSET                          18
+#define DxF0x128_Reserved_31_18_WIDTH                           14
+#define DxF0x128_Reserved_31_18_MASK                            0xfffc0000
+
+/// DxF0x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                       PortArbTableStatus:1 ; ///<
+    UINT32                                     VcNegotiationPending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x128_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// **** D0F0x64_x00 Register Definition ****
+// Address
+#define D0F0x64_x00_ADDRESS                                     0x0
+
+// Type
+#define D0F0x64_x00_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x00_Reserved_5_0_OFFSET                         0
+#define D0F0x64_x00_Reserved_5_0_WIDTH                          6
+#define D0F0x64_x00_Reserved_5_0_MASK                           0x3f
+#define D0F0x64_x00_NbFchCfgEn_OFFSET                           6
+#define D0F0x64_x00_NbFchCfgEn_WIDTH                            1
+#define D0F0x64_x00_NbFchCfgEn_MASK                             0x40
+#define D0F0x64_x00_HwInitWrLock_OFFSET                         7
+#define D0F0x64_x00_HwInitWrLock_WIDTH                          1
+#define D0F0x64_x00_HwInitWrLock_MASK                           0x80
+#define D0F0x64_x00_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x00_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x00_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_5_0:6 ; ///<
+    UINT32                                               NbFchCfgEn:1 ; ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x00_STRUCT;
+
+// **** D0F0x64_x0B Register Definition ****
+// Address
+#define D0F0x64_x0B_ADDRESS                                     0xb
+
+// Type
+#define D0F0x64_x0B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x0B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x0B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x0B_SetPowEn_OFFSET                             20
+#define D0F0x64_x0B_SetPowEn_WIDTH                              1
+#define D0F0x64_x0B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x0B_IocFchSetPowEn_OFFSET                       21
+#define D0F0x64_x0B_IocFchSetPowEn_WIDTH                        1
+#define D0F0x64_x0B_IocFchSetPowEn_MASK                         0x200000
+#define D0F0x64_x0B_Reserved_22_22_OFFSET                       22
+#define D0F0x64_x0B_Reserved_22_22_WIDTH                        1
+#define D0F0x64_x0B_Reserved_22_22_MASK                         0x400000
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET                23
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH                 1
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK                  0x800000
+#define D0F0x64_x0B_Reserved_31_24_OFFSET                       24
+#define D0F0x64_x0B_Reserved_31_24_WIDTH                        8
+#define D0F0x64_x0B_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x64_x0B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           IocFchSetPowEn:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    IocFchSetPmeTurnOffEn:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0B_STRUCT;
+
+// **** D0F0x64_x0C Register Definition ****
+// Address
+#define D0F0x64_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x64_x0C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0C_Reserved_1_0_OFFSET                         0
+#define D0F0x64_x0C_Reserved_1_0_WIDTH                          2
+#define D0F0x64_x0C_Reserved_1_0_MASK                           0x3
+#define D0F0x64_x0C_Dev2BridgeDis_OFFSET                        2
+#define D0F0x64_x0C_Dev2BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev2BridgeDis_MASK                          0x4
+#define D0F0x64_x0C_Dev3BridgeDis_OFFSET                        3
+#define D0F0x64_x0C_Dev3BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev3BridgeDis_MASK                          0x8
+#define D0F0x64_x0C_Dev4BridgeDis_OFFSET                        4
+#define D0F0x64_x0C_Dev4BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev4BridgeDis_MASK                          0x10
+#define D0F0x64_x0C_Dev5BridgeDis_OFFSET                        5
+#define D0F0x64_x0C_Dev5BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev5BridgeDis_MASK                          0x20
+#define D0F0x64_x0C_Dev6BridgeDis_OFFSET                        6
+#define D0F0x64_x0C_Dev6BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev6BridgeDis_MASK                          0x40
+#define D0F0x64_x0C_Dev7BridgeDis_OFFSET                        7
+#define D0F0x64_x0C_Dev7BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev7BridgeDis_MASK                          0x80
+#define D0F0x64_x0C_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x0C_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x0C_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            Dev2BridgeDis:1 ; ///<
+    UINT32                                            Dev3BridgeDis:1 ; ///<
+    UINT32                                            Dev4BridgeDis:1 ; ///<
+    UINT32                                            Dev5BridgeDis:1 ; ///<
+    UINT32                                            Dev6BridgeDis:1 ; ///<
+    UINT32                                            Dev7BridgeDis:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0C_STRUCT;
+
+// **** D0F0x64_x19 Register Definition ****
+// Address
+#define D0F0x64_x19_ADDRESS                                     0x19
+
+// Type
+#define D0F0x64_x19_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x19_TomEn_OFFSET                                0
+#define D0F0x64_x19_TomEn_WIDTH                                 1
+#define D0F0x64_x19_TomEn_MASK                                  0x1
+#define D0F0x64_x19_Reserved_22_1_OFFSET                        1
+#define D0F0x64_x19_Reserved_22_1_WIDTH                         22
+#define D0F0x64_x19_Reserved_22_1_MASK                          0x7ffffe
+#define D0F0x64_x19_Tom2_31_23__OFFSET                          23
+#define D0F0x64_x19_Tom2_31_23__WIDTH                           9
+#define D0F0x64_x19_Tom2_31_23__MASK                            0xff800000
+
+/// D0F0x64_x19
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    TomEn:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                              Tom2_31_23_:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x19_STRUCT;
+
+// **** D0F0x64_x1A Register Definition ****
+// Address
+#define D0F0x64_x1A_ADDRESS                                     0x1a
+
+// Type
+#define D0F0x64_x1A_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1A_Tom2_39_32__OFFSET                          0
+#define D0F0x64_x1A_Tom2_39_32__WIDTH                           8
+#define D0F0x64_x1A_Tom2_39_32__MASK                            0xff
+#define D0F0x64_x1A_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x1A_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x1A_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x1A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Tom2_39_32_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1A_STRUCT;
+
+// **** D0F0x64_x1D Register Definition ****
+// Address
+#define D0F0x64_x1D_ADDRESS                                     0x1d
+
+// Type
+#define D0F0x64_x1D_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET                       0
+#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH                        1
+#define D0F0x64_x1D_IntGfxAsPcieEn_MASK                         0x1
+#define D0F0x64_x1D_VgaEn_OFFSET                                1
+#define D0F0x64_x1D_VgaEn_WIDTH                                 1
+#define D0F0x64_x1D_VgaEn_MASK                                  0x2
+#define D0F0x64_x1D_Reserved_2_2_OFFSET                         2
+#define D0F0x64_x1D_Reserved_2_2_WIDTH                          1
+#define D0F0x64_x1D_Reserved_2_2_MASK                           0x4
+#define D0F0x64_x1D_Vga16En_OFFSET                              3
+#define D0F0x64_x1D_Vga16En_WIDTH                               1
+#define D0F0x64_x1D_Vga16En_MASK                                0x8
+#define D0F0x64_x1D_Reserved_31_4_OFFSET                        4
+#define D0F0x64_x1D_Reserved_31_4_WIDTH                         28
+#define D0F0x64_x1D_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F0x64_x1D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           IntGfxAsPcieEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1D_STRUCT;
+
+
+
+
+
+
+
+
+// **** D0F0x64_x53 Register Definition ****
+// Address
+#define D0F0x64_x53_ADDRESS                                     0x53
+
+// Type
+#define D0F0x64_x53_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x53_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x53_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x53_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x53_SetPowEn_OFFSET                             20
+#define D0F0x64_x53_SetPowEn_WIDTH                              1
+#define D0F0x64_x53_SetPowEn_MASK                               0x100000
+#define D0F0x64_x53_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x53_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x53_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x53
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x53_STRUCT;
+
+// **** D0F0x64_x55 Register Definition ****
+// Address
+#define D0F0x64_x55_ADDRESS                                     0x55
+
+// Type
+#define D0F0x64_x55_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x55_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x55_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x55_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x55_SetPowEn_OFFSET                             20
+#define D0F0x64_x55_SetPowEn_WIDTH                              1
+#define D0F0x64_x55_SetPowEn_MASK                               0x100000
+#define D0F0x64_x55_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x55_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x55_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x55
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x55_STRUCT;
+
+// **** D0F0x64_x57 Register Definition ****
+// Address
+#define D0F0x64_x57_ADDRESS                                     0x57
+
+// Type
+#define D0F0x64_x57_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x57_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x57_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x57_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x57_SetPowEn_OFFSET                             20
+#define D0F0x64_x57_SetPowEn_WIDTH                              1
+#define D0F0x64_x57_SetPowEn_MASK                               0x100000
+#define D0F0x64_x57_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x57_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x57_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x57
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x57_STRUCT;
+
+// **** D0F0x64_x59 Register Definition ****
+// Address
+#define D0F0x64_x59_ADDRESS                                     0x59
+
+// Type
+#define D0F0x64_x59_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x59_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x59_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x59_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x59_SetPowEn_OFFSET                             20
+#define D0F0x64_x59_SetPowEn_WIDTH                              1
+#define D0F0x64_x59_SetPowEn_MASK                               0x100000
+#define D0F0x64_x59_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x59_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x59_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x59
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x59_STRUCT;
+
+// **** D0F0x64_x5B Register Definition ****
+// Address
+#define D0F0x64_x5B_ADDRESS                                     0x5b
+
+// Type
+#define D0F0x64_x5B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x5B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x5B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x5B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x5B_SetPowEn_OFFSET                             20
+#define D0F0x64_x5B_SetPowEn_WIDTH                              1
+#define D0F0x64_x5B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x5B_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x5B_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x5B_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x5B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x5B_STRUCT;
+
+/// D0F0x64_x6A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             VoltageLevel:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex488_STRUCT;
+
+/// D0F0x64_x6B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:2 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex489_STRUCT;
+
+// **** D0F0x98_x06 Register Definition ****
+// Address
+#define D0F0x98_x06_ADDRESS                                     0x6
+
+// Type
+#define D0F0x98_x06_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x06_Reserved_25_0_OFFSET                        0
+#define D0F0x98_x06_Reserved_25_0_WIDTH                         26
+#define D0F0x98_x06_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x98_x06_UmiNpMemWrEn_OFFSET                         26
+#define D0F0x98_x06_UmiNpMemWrEn_WIDTH                          1
+#define D0F0x98_x06_UmiNpMemWrEn_MASK                           0x4000000
+#define D0F0x98_x06_Reserved_31_27_OFFSET                       27
+#define D0F0x98_x06_Reserved_31_27_WIDTH                        5
+#define D0F0x98_x06_Reserved_31_27_MASK                         0xf8000000
+
+/// D0F0x98_x06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                             UmiNpMemWrEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x06_STRUCT;
+
+
+
+
+
+// **** D0F0x98_x1E Register Definition ****
+// Address
+#define D0F0x98_x1E_ADDRESS                                     0x1e
+
+// Type
+#define D0F0x98_x1E_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x1E_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x1E_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x1E_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x1E_HiPriEn_OFFSET                              1
+#define D0F0x98_x1E_HiPriEn_WIDTH                               1
+#define D0F0x98_x1E_HiPriEn_MASK                                0x2
+#define D0F0x98_x1E_Reserved_31_2_OFFSET                        2
+#define D0F0x98_x1E_Reserved_31_2_WIDTH                         30
+#define D0F0x98_x1E_Reserved_31_2_MASK                          0xfffffffc
+
+/// D0F0x98_x1E
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  HiPriEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x1E_STRUCT;
+
+
+/// D0F0x98_x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32           ex495_1:1;
+    UINT32                                            Reserved_15_2:14; ///<
+    UINT32           ex495_3:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex495_STRUCT;
+
+
+// **** D0F0x98_x49 Register Definition ****
+// Address
+#define D0F0x98_x49_ADDRESS                                     0x49
+
+// Type
+#define D0F0x98_x49_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x49_Reserved_3_0_OFFSET                         0
+#define D0F0x98_x49_Reserved_3_0_WIDTH                          4
+#define D0F0x98_x49_Reserved_3_0_MASK                           0xf
+#define D0F0x98_x49_Reserved_23_12_OFFSET                       12
+#define D0F0x98_x49_Reserved_23_12_WIDTH                        12
+#define D0F0x98_x49_Reserved_23_12_MASK                         0xfff000
+#define D0F0x98_x49_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x49_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x49_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x49_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x49_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x49_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x49_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x49_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x49_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x49_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x49_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x49_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x49_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x49_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x49_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x49_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x49_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x49
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                            :8 ; ///<
+    UINT32                                           Reserved_23_12:12; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x49_STRUCT;
+
+// **** D0F0x98_x4A Register Definition ****
+// Address
+#define D0F0x98_x4A_ADDRESS                                     0x4a
+
+// Type
+#define D0F0x98_x4A_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x4A_Reserved_3_0_OFFSET                         0
+#define D0F0x98_x4A_Reserved_3_0_WIDTH                          4
+#define D0F0x98_x4A_Reserved_3_0_MASK                           0xf
+#define D0F0x98_x4A_Reserved_23_12_OFFSET                       12
+#define D0F0x98_x4A_Reserved_23_12_WIDTH                        12
+#define D0F0x98_x4A_Reserved_23_12_MASK                         0xfff000
+#define D0F0x98_x4A_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x4A_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x4A_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x4A_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x4A_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x4A_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x4A_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x4A_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x4A_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x4A_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x4A_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x4A_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x4A_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x4A_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x4A_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x4A_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x4A_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x4A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                            :8 ; ///<
+    UINT32                                           Reserved_23_12:12; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x4A_STRUCT;
+
+
+// **** D0F0xE4_WRAP_0080 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0080_ADDRESS                               0x80
+
+// Type
+#define D0F0xE4_WRAP_0080_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET             0
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH              4
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK               0xf
+#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET                  4
+#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH                   28
+#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK                    0xfffffff0
+
+/// D0F0xE4_WRAP_0080
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       StrapBifLinkConfig:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0080_STRUCT;
+
+// **** D0F0xE4_WRAP_0800 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0800_ADDRESS                               0x800
+
+// Type
+#define D0F0xE4_WRAP_0800_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET                   0
+#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH                    1
+#define D0F0xE4_WRAP_0800_HoldTraining_MASK                     0x1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_WRAP_0800
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HoldTraining:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0800_STRUCT;
+
+// **** D0F0xE4_WRAP_0803 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0803_ADDRESS                               0x803
+
+// Type
+#define D0F0xE4_WRAP_0803_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0803
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0803_STRUCT;
+
+// **** D0F0xE4_WRAP_0903 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0903_ADDRESS                               0x903
+
+// Type
+#define D0F0xE4_WRAP_0903_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0903
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0903_STRUCT;
+
+
+/// D0F0xE4_WRAP_8011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      TxclkDynGateLatency:6 ; ///<
+    UINT32                                        TxclkPermGateEven:1 ; ///<
+    UINT32                                       TxclkDynGateEnable:1 ; ///<
+    UINT32                                            TxclkPermStop:1 ; ///<
+    UINT32                                      TxclkRegsGateEnable:1 ; ///<
+    UINT32                                     TxclkRegsGateLatency:6 ; ///<
+    UINT32                                         RcvrDetClkEnable:1 ; ///<
+    UINT32                                     TxclkPermGateLatency:6 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                      TxclkLcntGateEnable:1 ; ///<
+    UINT32                                           Reserved_30_25:6 ; ///<
+    UINT32                                            StrapBifValid:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex501_STRUCT;
+
+// **** D0F0xE4_WRAP_8012 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8012_ADDRESS                               0x8012
+
+// Type
+#define D0F0xE4_WRAP_8012_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET           0
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK             0x3f
+#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET            7
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK              0x80
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET         8
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK           0x3f00
+#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET         16
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK           0x3f0000
+#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET          23
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH           1
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK            0x800000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET       24
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH        6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK         0x3f000000
+#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     Pif1xIdleGateLatency:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                      Pif1xIdleGateEnable:1 ; ///<
+    UINT32                                   Pif1xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                   Pif2p5xIdleGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    Pif2p5xIdleGateEnable:1 ; ///<
+    UINT32                                 Pif2p5xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8012_STRUCT;
+
+
+// **** D0F0xE4_WRAP_8021 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8021_ADDRESS                               0x8021
+
+// Type
+#define D0F0xE4_WRAP_8021_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8021_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8021_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8021_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8021_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8021_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8021_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8021_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8021_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8021_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8021_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8021
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8021_STRUCT;
+
+// **** D0F0xE4_WRAP_8022 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8022_ADDRESS                               0x8022
+
+// Type
+#define D0F0xE4_WRAP_8022_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8022_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8022_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8022_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8022_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8022_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8022_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8022_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8022_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8022_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8022_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8022
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8022_STRUCT;
+
+// **** D0F0xE4_WRAP_8023 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8023_ADDRESS                               0x8023
+
+// Type
+#define D0F0xE4_WRAP_8023_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET                     0
+#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH                      16
+#define D0F0xE4_WRAP_8023_LaneEnable_MASK                       0xffff
+#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_WRAP_8023
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               LaneEnable:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8023_STRUCT;
+
+// **** D0F0xE4_WRAP_8025 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8025_ADDRESS                               0x8025
+
+// Type
+#define D0F0xE4_WRAP_8025_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET                    0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK                      0x7
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET                    3
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK                      0x18
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET                   5
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK                     0x20
+#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET                   6
+#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH                    2
+#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK                     0xc0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET                    8
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK                      0x700
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET                    11
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK                      0x1800
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET                   13
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK                     0x2000
+#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET                    16
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK                      0x70000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET                    19
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK                      0x180000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET                   21
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK                     0x200000
+#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET                 22
+#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK                   0xc00000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET                    24
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK                      0x7000000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET                    27
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK                      0x18000000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET                   29
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK                     0x20000000
+#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8025
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LMTxPhyCmd0:3 ; ///<
+    UINT32                                              LMRxPhyCmd0:2 ; ///<
+    UINT32                                             LMLinkSpeed0:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                              LMTxPhyCmd1:3 ; ///<
+    UINT32                                              LMRxPhyCmd1:2 ; ///<
+    UINT32                                             LMLinkSpeed1:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                              LMTxPhyCmd2:3 ; ///<
+    UINT32                                              LMRxPhyCmd2:2 ; ///<
+    UINT32                                             LMLinkSpeed2:1 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              LMTxPhyCmd3:3 ; ///<
+    UINT32                                              LMRxPhyCmd3:2 ; ///<
+    UINT32                                             LMLinkSpeed3:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8025_STRUCT;
+
+// **** D0F0xE4_WRAP_8031 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8031_ADDRESS                               0x8031
+
+// Type
+#define D0F0xE4_WRAP_8031_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET                 0
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH                  10
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK                   0x3ff
+#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET                 10
+#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH                  6
+#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK                   0xfc00
+#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET                     16
+#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH                      1
+#define D0F0xE4_WRAP_8031_LnCntValid_MASK                       0x10000
+#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET                 17
+#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH                  15
+#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xE4_WRAP_8031
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LnCntBandwidth:10; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                               LnCntValid:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8031_STRUCT;
+
+/// D0F0xE4_WRAP_8040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  OwnPhyA:1 ; ///<
+    UINT32                                                  OwnPhyB:1 ; ///<
+    UINT32                                                  OwnPhyC:1 ; ///<
+    UINT32                                                  OwnPhyD:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                           DigaPwrdnValue:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           DigbPwrdnValue:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                  CntPhyA:1 ; ///<
+    UINT32                                                  CntPhyB:1 ; ///<
+    UINT32                                                  CntPhyC:1 ; ///<
+    UINT32                                                  CntPhyD:1 ; ///<
+    UINT32                                                  CntDigA:1 ; ///<
+    UINT32                                                  CntDigB:1 ; ///<
+    UINT32                                              ChangeLnSpd:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex502_STRUCT;
+
+// **** D0F0xE4_WRAP_8060 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8060_ADDRESS                               0x8060
+
+// Type
+#define D0F0xE4_WRAP_8060_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET                    0
+#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH                     1
+#define D0F0xE4_WRAP_8060_Reconfigure_MASK                      0x1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET                  2
+#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH                   1
+#define D0F0xE4_WRAP_8060_ResetComplete_MASK                    0x4
+#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET                  3
+#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH                   13
+#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK                    0xfff8
+#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET                 18
+#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH                  14
+#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xE4_WRAP_8060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reconfigure:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                            ResetComplete:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                      :1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8060_STRUCT;
+
+// **** D0F0xE4_WRAP_8062 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8062_ADDRESS                               0x8062
+
+// Type
+#define D0F0xE4_WRAP_8062_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET                  0
+#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH                   1
+#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK                    0x1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET                    2
+#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH                     3
+#define D0F0xE4_WRAP_8062_ResetPeriod_MASK                      0x1c
+#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET                   5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH                    5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK                     0x3e0
+#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET                    10
+#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH                     1
+#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK                      0x400
+#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET                 11
+#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH                  1
+#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK                   0x800
+#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET                 12
+#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH                  20
+#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK                   0xfffff000
+
+/// D0F0xE4_WRAP_8062
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ReconfigureEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              ResetPeriod:3 ; ///<
+    UINT32                                             Reserved_9_5:5 ; ///<
+    UINT32                                              BlockOnIdle:1 ; ///<
+    UINT32                                           ConfigXferMode:1 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8062_STRUCT;
+
+// **** D0F0xE4_WRAP_80F0 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F0_ADDRESS                               0x80f0
+
+// Type
+#define D0F0xE4_WRAP_80F0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET                   0
+#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH                    32
+#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK                     0xffffffff
+
+/// D0F0xE4_WRAP_80F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             MicroSeconds:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F0_STRUCT;
+
+// **** D0F0xE4_WRAP_80F1 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F1_ADDRESS                               0x80f1
+
+// Type
+#define D0F0xE4_WRAP_80F1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET                      0
+#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH                       8
+#define D0F0xE4_WRAP_80F1_ClockRate_MASK                        0xff
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET                  8
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH                   24
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK                    0xffffff00
+
+/// D0F0xE4_WRAP_80F1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ClockRate:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F1_STRUCT;
+
+// **** D0F0xE4_PIF_0010 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0010_ADDRESS                                0x10
+
+// Type
+#define D0F0xE4_PIF_0010_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET                    0
+#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH                     4
+#define D0F0xE4_PIF_0010_Reserved_3_0_MASK                      0xf
+#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET                  4
+#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH                   1
+#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK                    0x10
+#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET                    5
+#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH                     1
+#define D0F0xE4_PIF_0010_Reserved_5_5_MASK                      0x20
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET           6
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH            1
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK             0x40
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET               7
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH                1
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK                 0x80
+#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET                   8
+#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH                    9
+#define D0F0xE4_PIF_0010_Reserved_16_8_MASK                     0x1ff00
+#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET                     17
+#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK                       0xe0000
+#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET                  23
+#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH                   9
+#define D0F0xE4_PIF_0010_Reserved_31_23_MASK                    0xff800000
+
+/// D0F0xE4_PIF_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                           EiDetCycleMode:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                    RxDetectFifoResetMode:1 ; ///<
+    UINT32                                        RxDetectTxPwrMode:1 ; ///<
+    UINT32                                            Reserved_16_8:9 ; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+    UINT32                                           :3 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0010_STRUCT;
+
+// **** D0F0xE4_PIF_0011 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0011_ADDRESS                                0x11
+
+// Type
+#define D0F0xE4_PIF_0011_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0011_X2Lane10_OFFSET                        0
+#define D0F0xE4_PIF_0011_X2Lane10_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane10_MASK                          0x1
+#define D0F0xE4_PIF_0011_X2Lane32_OFFSET                        1
+#define D0F0xE4_PIF_0011_X2Lane32_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane32_MASK                          0x2
+#define D0F0xE4_PIF_0011_X2Lane54_OFFSET                        2
+#define D0F0xE4_PIF_0011_X2Lane54_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane54_MASK                          0x4
+#define D0F0xE4_PIF_0011_X2Lane76_OFFSET                        3
+#define D0F0xE4_PIF_0011_X2Lane76_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane76_MASK                          0x8
+#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET                    4
+#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH                     4
+#define D0F0xE4_PIF_0011_Reserved_7_4_MASK                      0xf0
+#define D0F0xE4_PIF_0011_X4Lane30_OFFSET                        8
+#define D0F0xE4_PIF_0011_X4Lane30_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane30_MASK                          0x100
+#define D0F0xE4_PIF_0011_X4Lane74_OFFSET                        9
+#define D0F0xE4_PIF_0011_X4Lane74_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane74_MASK                          0x200
+#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET                  10
+#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH                   2
+#define D0F0xE4_PIF_0011_Reserved_11_10_MASK                    0xc00
+#define D0F0xE4_PIF_0011_X4Lane52_OFFSET                        12
+#define D0F0xE4_PIF_0011_X4Lane52_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane52_MASK                          0x1000
+#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0011_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0011_X8Lane70_OFFSET                        16
+#define D0F0xE4_PIF_0011_X8Lane70_WIDTH                         1
+#define D0F0xE4_PIF_0011_X8Lane70_MASK                          0x10000
+#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET                  17
+#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH                   8
+#define D0F0xE4_PIF_0011_Reserved_24_17_MASK                    0x1fe0000
+#define D0F0xE4_PIF_0011_MultiPif_OFFSET                        25
+#define D0F0xE4_PIF_0011_MultiPif_WIDTH                         1
+#define D0F0xE4_PIF_0011_MultiPif_MASK                          0x2000000
+#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET                  26
+#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH                   6
+#define D0F0xE4_PIF_0011_Reserved_31_26_MASK                    0xfc000000
+
+/// D0F0xE4_PIF_0011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 X2Lane10:1 ; ///<
+    UINT32                                                 X2Lane32:1 ; ///<
+    UINT32                                                 X2Lane54:1 ; ///<
+    UINT32                                                 X2Lane76:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                 X4Lane30:1 ; ///<
+    UINT32                                                 X4Lane74:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                                                 X4Lane52:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                 X8Lane70:1 ; ///<
+    UINT32                                           Reserved_24_17:8 ; ///<
+    UINT32                                                 MultiPif:1 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0011_STRUCT;
+
+// **** D0F0xE4_PIF_0012 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0012_ADDRESS                                0x12
+
+// Type
+#define D0F0xE4_PIF_0012_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0012_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0012_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0012_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0012_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0012_STRUCT;
+
+// **** D0F0xE4_PIF_0013 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0013_ADDRESS                                0x13
+
+// Type
+#define D0F0xE4_PIF_0013_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0013_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0013_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0013_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0013_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0013_STRUCT;
+
+// **** D0F0xE4_PIF_0015 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0015_ADDRESS                                0x15
+
+// Type
+#define D0F0xE4_PIF_0015_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET                   0
+#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK                     0x1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET                   1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK                     0x2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET                   2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK                     0x4
+#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET                   3
+#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK                     0x8
+#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET                   4
+#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK                     0x10
+#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET                   5
+#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK                     0x20
+#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET                   6
+#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK                     0x40
+#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET                   7
+#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK                     0x80
+#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PIF_0015_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PIF_0015
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            TxPhyStatus00:1 ; ///<
+    UINT32                                            TxPhyStatus01:1 ; ///<
+    UINT32                                            TxPhyStatus02:1 ; ///<
+    UINT32                                            TxPhyStatus03:1 ; ///<
+    UINT32                                            TxPhyStatus04:1 ; ///<
+    UINT32                                            TxPhyStatus05:1 ; ///<
+    UINT32                                            TxPhyStatus06:1 ; ///<
+    UINT32                                            TxPhyStatus07:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0015_STRUCT;
+
+// **** D0F0xE4_CORE_0002 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0002_ADDRESS                               0x2
+
+// Type
+#define D0F0xE4_CORE_0002_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET                     0
+#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH                      1
+#define D0F0xE4_CORE_0002_HwDebug_0__MASK                       0x1
+#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_CORE_0002_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_CORE_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               HwDebug_0_:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0002_STRUCT;
+
+
+
+// **** D0F0xE4_CORE_001C Register Definition ****
+// Address
+#define D0F0xE4_CORE_001C_ADDRESS                               0x1c
+
+// Type
+#define D0F0xE4_CORE_001C_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET              0
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH               1
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK                0x1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET                  1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK                    0x3e
+#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET                  6
+#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK                    0x7c0
+#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET                 11
+#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH                  21
+#define D0F0xE4_CORE_001C_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xE4_CORE_001C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxArbRoundRobinEn:1 ; ///<
+    UINT32                                            TxArbSlvLimit:5 ; ///<
+    UINT32                                            TxArbMstLimit:5 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_001C_STRUCT;
+
+// **** D0F0xE4_CORE_0040 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0040_ADDRESS                               0x40
+
+// Type
+#define D0F0xE4_CORE_0040_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET                  0
+#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH                   14
+#define D0F0xE4_CORE_0040_Reserved_13_0_MASK                    0x3fff
+#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET                  14
+#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH                   2
+#define D0F0xE4_CORE_0040_PElecIdleMode_MASK                    0xc000
+#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_CORE_0040_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_CORE_0040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_13_0:14; ///<
+    UINT32                                            PElecIdleMode:2 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0040_STRUCT;
+
+// **** D0F0xE4_CORE_00B0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00B0_ADDRESS                               0xb0
+
+// Type
+#define D0F0xE4_CORE_00B0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET                   0
+#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK                     0x3
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET                   2
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK                     0x4
+#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET                   3
+#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK                     0x18
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET                   5
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK                     0x20
+#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_CORE_00B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                             StrapF0MsiEn:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                             StrapF0AerEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00B0_STRUCT;
+
+
+// **** D0F0xE4_CORE_00C1 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00C1_ADDRESS                               0xc1
+
+// Type
+#define D0F0xE4_CORE_00C1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET   0
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH    1
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK     0x1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET            1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH             1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK              0x2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET                  2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH                   30
+#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xE4_CORE_00C1
+typedef union {
+  struct {                                                              ///<
+    UINT32                             StrapLinkBwNotificationCapEn:1 ; ///<
+    UINT32                                      StrapGen2Compliance:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00C1_STRUCT;
+
+// **** D0F0xE4_PHY_0009 Register Definition ****
+// Address
+#define D0F0xE4_PHY_0009_ADDRESS                                0x9
+
+// Type
+#define D0F0xE4_PHY_0009_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_0009_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_0009_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_0009_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_0009_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_0009_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_0009_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_0009_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_0009_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_0009_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_0009
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_0009_STRUCT;
+
+// **** D0F0xE4_PHY_000A Register Definition ****
+// Address
+#define D0F0xE4_PHY_000A_ADDRESS                                0xa
+
+// Type
+#define D0F0xE4_PHY_000A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_000A_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_000A_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_000A_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_000A_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_000A_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_000A_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_000A_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_000A_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_000A_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_000A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000A_STRUCT;
+
+// **** D0F0xE4_PHY_000B Register Definition ****
+// Address
+#define D0F0xE4_PHY_000B_ADDRESS                                0xb
+
+// Type
+#define D0F0xE4_PHY_000B_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET                      0
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK                        0x1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET                      1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK                        0x2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET                   2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH                    1
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK                     0x4
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET                    3
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK                      0x8
+#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET                    4
+#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK                      0x10
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET               5
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH                1
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK                 0x20
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET                    6
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK                      0x40
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET              7
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH               1
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK                0x80
+#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET                      8
+#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK                        0x100
+#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET                   9
+#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH                    5
+#define D0F0xE4_PHY_000B_Reserved_13_9_MASK                     0x3e00
+#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET                    14
+#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK                      0x4000
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET                  15
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH                   1
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK                    0x8000
+#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_000B_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_000B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               TxPwrSbiEn:1 ; ///<
+    UINT32                                               RxPwrSbiEn:1 ; ///<
+    UINT32                                            PcieModeSbiEn:1 ; ///<
+    UINT32                                             FreqDivSbiEn:1 ; ///<
+    UINT32                                             DllLockSbiEn:1 ; ///<
+    UINT32                                        OffsetCancelSbiEn:1 ; ///<
+    UINT32                                             SkipBitSbiEn:1 ; ///<
+    UINT32                                       IncoherentClkSbiEn:1 ; ///<
+    UINT32                                               EiDetSbiEn:1 ; ///<
+    UINT32                                            Reserved_13_9:5 ; ///<
+    UINT32                                             MargPktSbiEn:1 ; ///<
+    UINT32                                           PllCmpPktSbiEn:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000B_STRUCT;
+
+// **** D0F0xE4_PHY_2000 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2000_ADDRESS                                0x2000
+
+// Type
+#define D0F0xE4_PHY_2000_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET                  0
+#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH                   3
+#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK                    0x7
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET               3
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH                1
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK                 0x8
+#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET                   4
+#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH                    28
+#define D0F0xE4_PHY_2000_Reserved_31_4_MASK                     0xfffffff0
+
+/// D0F0xE4_PHY_2000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PllPowerDownEn:3 ; ///<
+    UINT32                                        PllAutoPwrDownDis:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2000_STRUCT;
+
+
+// **** D0F0xE4_PHY_2005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2005_ADDRESS                                0x2005
+
+// Type
+#define D0F0xE4_PHY_2005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET                      0
+#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH                       4
+#define D0F0xE4_PHY_2005_PllClkFreq_MASK                        0xf
+#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET                    4
+#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH                     5
+#define D0F0xE4_PHY_2005_Reserved_8_4_MASK                      0x1f0
+#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET                   9
+#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH                    2
+#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK                     0x600
+#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET                  11
+#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH                   2
+#define D0F0xE4_PHY_2005_Reserved_12_11_MASK                    0x1800
+#define D0F0xE4_PHY_2005_PllMode_OFFSET                         13
+#define D0F0xE4_PHY_2005_PllMode_WIDTH                          2
+#define D0F0xE4_PHY_2005_PllMode_MASK                           0x6000
+#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET                  15
+#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH                   17
+#define D0F0xE4_PHY_2005_Reserved_31_15_MASK                    0xffff8000
+
+/// D0F0xE4_PHY_2005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PllClkFreq:4 ; ///<
+    UINT32                                             Reserved_8_4:5 ; ///<
+    UINT32                                            PllClkFreqExt:2 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                  PllMode:2 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2005_STRUCT;
+
+// **** D0F0xE4_PHY_2008 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2008_ADDRESS                                0x2008
+
+// Type
+#define D0F0xE4_PHY_2008_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET                0
+#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH                 1
+#define D0F0xE4_PHY_2008_PllControlUpdate_MASK                  0x1
+#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET                   1
+#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH                    22
+#define D0F0xE4_PHY_2008_Reserved_22_1_MASK                     0x7ffffe
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET              23
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH               3
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK                0x3800000
+#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET                  26
+#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH                   3
+#define D0F0xE4_PHY_2008_Reserved_28_26_MASK                    0x1c000000
+#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET                      29
+#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH                       1
+#define D0F0xE4_PHY_2008_VdDetectEn_MASK                        0x20000000
+#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_2008_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_2008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PllControlUpdate:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                       MeasCycCntVal_2_0_:3 ; ///<
+    UINT32                                           Reserved_28_26:3 ; ///<
+    UINT32                                               VdDetectEn:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2008_STRUCT;
+
+// **** D0F0xE4_PHY_4001 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4001_ADDRESS                                0x4001
+
+// Type
+#define D0F0xE4_PHY_4001_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET                   0
+#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH                    15
+#define D0F0xE4_PHY_4001_Reserved_14_0_MASK                     0x7fff
+#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET                  15
+#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH                   1
+#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK                    0x8000
+#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_4001_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_4001
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                           ForceDccRecalc:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4001_STRUCT;
+
+// **** D0F0xE4_PHY_4002 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4002_ADDRESS                                0x4002
+
+// Type
+#define D0F0xE4_PHY_4002_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET                    0
+#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH                     3
+#define D0F0xE4_PHY_4002_Reserved_2_0_MASK                      0x7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET              3
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH               1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK                0x8
+#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET                  4
+#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH                   3
+#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK                    0x70
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET                7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH                 1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK                  0x80
+#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET                   8
+#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH                    6
+#define D0F0xE4_PHY_4002_Reserved_13_8_MASK                     0x3f00
+#define D0F0xE4_PHY_4002_LfcMin_OFFSET                          14
+#define D0F0xE4_PHY_4002_LfcMin_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMin_MASK                            0x3fc000
+#define D0F0xE4_PHY_4002_LfcMax_OFFSET                          22
+#define D0F0xE4_PHY_4002_LfcMax_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMax_MASK                            0x3fc00000
+#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_4002_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_4002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                       SamClkPiOffsetSign:1 ; ///<
+    UINT32                                           SamClkPiOffset:3 ; ///<
+    UINT32                                         SamClkPiOffsetEn:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                                   LfcMin:8 ; ///<
+    UINT32                                                   LfcMax:8 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4002_STRUCT;
+
+// **** D0F0xE4_PHY_4005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4005_ADDRESS                                0x4005
+
+// Type
+#define D0F0xE4_PHY_4005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET                    0
+#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH                     9
+#define D0F0xE4_PHY_4005_Reserved_8_0_MASK                      0x1ff
+#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET                   9
+#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH                    1
+#define D0F0xE4_PHY_4005_JitterInjHold_MASK                     0x200
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET                 10
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH                  6
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK                   0xfc00
+#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET                  16
+#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH                   7
+#define D0F0xE4_PHY_4005_Reserved_22_16_MASK                    0x7f0000
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET                  23
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH                   6
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK                    0x1f800000
+#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET                    29
+#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH                     1
+#define D0F0xE4_PHY_4005_JitterInjDir_MASK                      0x20000000
+#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET                     30
+#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH                      1
+#define D0F0xE4_PHY_4005_JitterInjEn_MASK                       0x40000000
+#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET                  31
+#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH                   1
+#define D0F0xE4_PHY_4005_Reserved_31_31_MASK                    0x80000000
+
+/// D0F0xE4_PHY_4005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                            JitterInjHold:1 ; ///<
+    UINT32                                          JitterInjOffCnt:6 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                           JitterInjOnCnt:6 ; ///<
+    UINT32                                             JitterInjDir:1 ; ///<
+    UINT32                                              JitterInjEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4005_STRUCT;
+
+// **** D0F0xE4_PHY_4006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4006_ADDRESS                                0x4006
+
+// Type
+#define D0F0xE4_PHY_4006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET                    0
+#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH                     5
+#define D0F0xE4_PHY_4006_Reserved_4_0_MASK                      0x1f
+#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET                      5
+#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH                       2
+#define D0F0xE4_PHY_4006_DfeVoltage_MASK                        0x60
+#define D0F0xE4_PHY_4006_DfeEn_OFFSET                           7
+#define D0F0xE4_PHY_4006_DfeEn_WIDTH                            1
+#define D0F0xE4_PHY_4006_DfeEn_MASK                             0x80
+#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PHY_4006_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PHY_4006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                               DfeVoltage:2 ; ///<
+    UINT32                                                    DfeEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4006_STRUCT;
+
+// **** D0F0xE4_PHY_400A Register Definition ****
+// Address
+#define D0F0xE4_PHY_400A_ADDRESS                                0x400a
+
+// Type
+#define D0F0xE4_PHY_400A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET                 0
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH                  1
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK                   0x1
+#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET                    1
+#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH                     3
+#define D0F0xE4_PHY_400A_Reserved_3_1_MASK                      0xe
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET                4
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH                 1
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK                  0x10
+#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET                    5
+#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH                     2
+#define D0F0xE4_PHY_400A_Reserved_6_5_MASK                      0x60
+#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET                    7
+#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH                     1
+#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK                      0x80
+#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET                   8
+#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH                    5
+#define D0F0xE4_PHY_400A_Reserved_12_8_MASK                     0x1f00
+#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET                  13
+#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH                   2
+#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK                    0x6000
+#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET                  15
+#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH                   2
+#define D0F0xE4_PHY_400A_Reserved_16_15_MASK                    0x18000
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET               17
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH                1
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK                 0x20000
+#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET                  18
+#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH                   11
+#define D0F0xE4_PHY_400A_Reserved_28_18_MASK                    0x1ffc0000
+#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET                     29
+#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK                       0xe0000000
+
+/// D0F0xE4_PHY_400A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          EnCoreLoopFirst:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                         LockDetOnLs2Exit:1 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                             BiasDisInLs2:1 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           AnalogWaitTime:2 ; ///<
+    UINT32                                           Reserved_16_15:2 ; ///<
+    UINT32                                        DllLockFastModeEn:1 ; ///<
+    UINT32                                           Reserved_28_18:11; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_400A_STRUCT;
+
+// **** D0F0xE4_PHY_6005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6005_ADDRESS                                0x6005
+
+// Type
+#define D0F0xE4_PHY_6005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET                   0
+#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH                    29
+#define D0F0xE4_PHY_6005_Reserved_28_0_MASK                     0x1fffffff
+#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET                       29
+#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH                        1
+#define D0F0xE4_PHY_6005_IsOwnMstr_MASK                         0x20000000
+#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET                  30
+#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH                   1
+#define D0F0xE4_PHY_6005_Reserved_30_30_MASK                    0x40000000
+#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET                    31
+#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH                     1
+#define D0F0xE4_PHY_6005_GangedModeEn_MASK                      0x80000000
+
+/// D0F0xE4_PHY_6005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_28_0:29; ///<
+    UINT32                                                IsOwnMstr:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             GangedModeEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6005_STRUCT;
+
+// **** D18F2x09C_x0000_0000 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0000_ADDRESS                            0x0
+
+// Type
+#define D18F2x09C_x0000_0000_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0000_CkeDrvStren_OFFSET                 0
+#define D18F2x09C_x0000_0000_CkeDrvStren_WIDTH                  3
+#define D18F2x09C_x0000_0000_CkeDrvStren_MASK                   0x7
+#define D18F2x09C_x0000_0000_Reserved_3_3_OFFSET                3
+#define D18F2x09C_x0000_0000_Reserved_3_3_WIDTH                 1
+#define D18F2x09C_x0000_0000_Reserved_3_3_MASK                  0x8
+#define D18F2x09C_x0000_0000_CsOdtDrvStren_OFFSET               4
+#define D18F2x09C_x0000_0000_CsOdtDrvStren_WIDTH                3
+#define D18F2x09C_x0000_0000_CsOdtDrvStren_MASK                 0x70
+#define D18F2x09C_x0000_0000_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_0000_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_0000_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_0000_AddrCmdDrvStren_OFFSET             8
+#define D18F2x09C_x0000_0000_AddrCmdDrvStren_WIDTH              3
+#define D18F2x09C_x0000_0000_AddrCmdDrvStren_MASK               0x700
+#define D18F2x09C_x0000_0000_Reserved_11_11_OFFSET              11
+#define D18F2x09C_x0000_0000_Reserved_11_11_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_11_11_MASK                0x800
+#define D18F2x09C_x0000_0000_ClkDrvStren_OFFSET                 12
+#define D18F2x09C_x0000_0000_ClkDrvStren_WIDTH                  3
+#define D18F2x09C_x0000_0000_ClkDrvStren_MASK                   0x7000
+#define D18F2x09C_x0000_0000_Reserved_15_15_OFFSET              15
+#define D18F2x09C_x0000_0000_Reserved_15_15_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_15_15_MASK                0x8000
+#define D18F2x09C_x0000_0000_DataDrvStren_OFFSET                16
+#define D18F2x09C_x0000_0000_DataDrvStren_WIDTH                 3
+#define D18F2x09C_x0000_0000_DataDrvStren_MASK                  0x70000
+#define D18F2x09C_x0000_0000_Reserved_19_19_OFFSET              19
+#define D18F2x09C_x0000_0000_Reserved_19_19_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_19_19_MASK                0x80000
+#define D18F2x09C_x0000_0000_DqsDrvStren_OFFSET                 20
+#define D18F2x09C_x0000_0000_DqsDrvStren_WIDTH                  3
+#define D18F2x09C_x0000_0000_DqsDrvStren_MASK                   0x700000
+#define D18F2x09C_x0000_0000_Reserved_27_23_OFFSET              23
+#define D18F2x09C_x0000_0000_Reserved_27_23_WIDTH               5
+#define D18F2x09C_x0000_0000_Reserved_27_23_MASK                0xf800000
+#define D18F2x09C_x0000_0000_ProcOdt_OFFSET                     28
+#define D18F2x09C_x0000_0000_ProcOdt_WIDTH                      3
+#define D18F2x09C_x0000_0000_ProcOdt_MASK                       0x70000000
+#define D18F2x09C_x0000_0000_Reserved_31_31_OFFSET              31
+#define D18F2x09C_x0000_0000_Reserved_31_31_WIDTH               1
+#define D18F2x09C_x0000_0000_Reserved_31_31_MASK                0x80000000
+
+/// D18F2x09C_x0000_0000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0000_STRUCT;
+
+// **** D18F2x09C_x0000_0001 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0001_ADDRESS                            0x1
+
+// Type
+#define D18F2x09C_x0000_0001_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_MASK           0xe0
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_OFFSET          8
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_MASK            0x1f00
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_OFFSET         13
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_MASK           0xe000
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_OFFSET          16
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_MASK            0x1f0000
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_OFFSET         21
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_MASK           0xe00000
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_OFFSET          24
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_MASK            0x1f000000
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_OFFSET         29
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_WIDTH          3
+#define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_MASK           0xe0000000
+
+/// D18F2x09C_x0000_0001
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDatFineDly_Byte0:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte0:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte1:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte1:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte2:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte2:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte3:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0001_STRUCT;
+
+// **** D18F2x09C_x0000_0002 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0002_ADDRESS                            0x2
+
+// Type
+#define D18F2x09C_x0000_0002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_MASK           0xe0
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_OFFSET          8
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_MASK            0x1f00
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_OFFSET         13
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_MASK           0xe000
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_OFFSET          16
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_MASK            0x1f0000
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_OFFSET         21
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_MASK           0xe00000
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_OFFSET          24
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_MASK            0x1f000000
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_OFFSET         29
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_WIDTH          3
+#define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_MASK           0xe0000000
+
+/// D18F2x09C_x0000_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDatFineDly_Byte4:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte4:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte5:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte5:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte6:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte6:3 ; ///<
+    UINT32                                       WrDatFineDly_Byte7:5 ; ///<
+    UINT32                                      WrDatGrossDly_Byte7:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0002_STRUCT;
+
+// **** D18F2x09C_x0000_0004 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0004_ADDRESS                            0x4
+
+// Type
+#define D18F2x09C_x0000_0004_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0004_CkeFineDelay_OFFSET                0
+#define D18F2x09C_x0000_0004_CkeFineDelay_WIDTH                 5
+#define D18F2x09C_x0000_0004_CkeFineDelay_MASK                  0x1f
+#define D18F2x09C_x0000_0004_CkeSetup_OFFSET                    5
+#define D18F2x09C_x0000_0004_CkeSetup_WIDTH                     1
+#define D18F2x09C_x0000_0004_CkeSetup_MASK                      0x20
+#define D18F2x09C_x0000_0004_Reserved_7_6_OFFSET                6
+#define D18F2x09C_x0000_0004_Reserved_7_6_WIDTH                 2
+#define D18F2x09C_x0000_0004_Reserved_7_6_MASK                  0xc0
+#define D18F2x09C_x0000_0004_CsOdtFineDelay_OFFSET              8
+#define D18F2x09C_x0000_0004_CsOdtFineDelay_WIDTH               5
+#define D18F2x09C_x0000_0004_CsOdtFineDelay_MASK                0x1f00
+#define D18F2x09C_x0000_0004_CsOdtSetup_OFFSET                  13
+#define D18F2x09C_x0000_0004_CsOdtSetup_WIDTH                   1
+#define D18F2x09C_x0000_0004_CsOdtSetup_MASK                    0x2000
+#define D18F2x09C_x0000_0004_Reserved_15_14_OFFSET              14
+#define D18F2x09C_x0000_0004_Reserved_15_14_WIDTH               2
+#define D18F2x09C_x0000_0004_Reserved_15_14_MASK                0xc000
+#define D18F2x09C_x0000_0004_AddrCmdFineDelay_OFFSET            16
+#define D18F2x09C_x0000_0004_AddrCmdFineDelay_WIDTH             5
+#define D18F2x09C_x0000_0004_AddrCmdFineDelay_MASK              0x1f0000
+#define D18F2x09C_x0000_0004_AddrCmdSetup_OFFSET                21
+#define D18F2x09C_x0000_0004_AddrCmdSetup_WIDTH                 1
+#define D18F2x09C_x0000_0004_AddrCmdSetup_MASK                  0x200000
+#define D18F2x09C_x0000_0004_Reserved_31_22_OFFSET              22
+#define D18F2x09C_x0000_0004_Reserved_31_22_WIDTH               10
+#define D18F2x09C_x0000_0004_Reserved_31_22_MASK                0xffc00000
+
+/// D18F2x09C_x0000_0004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0004_STRUCT;
+
+// **** D18F2x09C_x0000_0005 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0005_ADDRESS                            0x5
+
+// Type
+#define D18F2x09C_x0000_0005_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0005_Reserved_0_0_OFFSET                0
+#define D18F2x09C_x0000_0005_Reserved_0_0_WIDTH                 1
+#define D18F2x09C_x0000_0005_Reserved_0_0_MASK                  0x1
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_OFFSET             1
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte0_MASK               0x3e
+#define D18F2x09C_x0000_0005_Reserved_8_6_OFFSET                6
+#define D18F2x09C_x0000_0005_Reserved_8_6_WIDTH                 3
+#define D18F2x09C_x0000_0005_Reserved_8_6_MASK                  0x1c0
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_OFFSET             9
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte1_MASK               0x3e00
+#define D18F2x09C_x0000_0005_Reserved_16_14_OFFSET              14
+#define D18F2x09C_x0000_0005_Reserved_16_14_WIDTH               3
+#define D18F2x09C_x0000_0005_Reserved_16_14_MASK                0x1c000
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_OFFSET             17
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte2_MASK               0x3e0000
+#define D18F2x09C_x0000_0005_Reserved_24_22_OFFSET              22
+#define D18F2x09C_x0000_0005_Reserved_24_22_WIDTH               3
+#define D18F2x09C_x0000_0005_Reserved_24_22_MASK                0x1c00000
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_OFFSET             25
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_WIDTH              5
+#define D18F2x09C_x0000_0005_RdDqsTime_Byte3_MASK               0x3e000000
+#define D18F2x09C_x0000_0005_Reserved_31_30_OFFSET              30
+#define D18F2x09C_x0000_0005_Reserved_31_30_WIDTH               2
+#define D18F2x09C_x0000_0005_Reserved_31_30_MASK                0xc0000000
+
+/// D18F2x09C_x0000_0005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                          RdDqsTime_Byte0:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                          RdDqsTime_Byte1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                          RdDqsTime_Byte2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                          RdDqsTime_Byte3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0005_STRUCT;
+
+// **** D18F2x09C_x0000_0006 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0006_ADDRESS                            0x6
+
+// Type
+#define D18F2x09C_x0000_0006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0006_Reserved_0_0_OFFSET                0
+#define D18F2x09C_x0000_0006_Reserved_0_0_WIDTH                 1
+#define D18F2x09C_x0000_0006_Reserved_0_0_MASK                  0x1
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_OFFSET             1
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte4_MASK               0x3e
+#define D18F2x09C_x0000_0006_Reserved_8_6_OFFSET                6
+#define D18F2x09C_x0000_0006_Reserved_8_6_WIDTH                 3
+#define D18F2x09C_x0000_0006_Reserved_8_6_MASK                  0x1c0
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_OFFSET             9
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte5_MASK               0x3e00
+#define D18F2x09C_x0000_0006_Reserved_16_14_OFFSET              14
+#define D18F2x09C_x0000_0006_Reserved_16_14_WIDTH               3
+#define D18F2x09C_x0000_0006_Reserved_16_14_MASK                0x1c000
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_OFFSET             17
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte6_MASK               0x3e0000
+#define D18F2x09C_x0000_0006_Reserved_24_22_OFFSET              22
+#define D18F2x09C_x0000_0006_Reserved_24_22_WIDTH               3
+#define D18F2x09C_x0000_0006_Reserved_24_22_MASK                0x1c00000
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_OFFSET             25
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_WIDTH              5
+#define D18F2x09C_x0000_0006_RdDqsTime_Byte7_MASK               0x3e000000
+#define D18F2x09C_x0000_0006_Reserved_31_30_OFFSET              30
+#define D18F2x09C_x0000_0006_Reserved_31_30_WIDTH               2
+#define D18F2x09C_x0000_0006_Reserved_31_30_MASK                0xc0000000
+
+/// D18F2x09C_x0000_0006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                          RdDqsTime_Byte4:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                          RdDqsTime_Byte5:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                          RdDqsTime_Byte6:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                          RdDqsTime_Byte7:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0006_STRUCT;
+
+
+
+// **** D18F2x09C_x0000_000D Register Definition ****
+// Address
+#define D18F2x09C_x0000_000D_ADDRESS                            0xd
+
+// Type
+#define D18F2x09C_x0000_000D_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_OFFSET           0
+#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_WIDTH            4
+#define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_MASK             0xf
+#define D18F2x09C_x0000_000D_TxCPUpdPeriod_OFFSET               4
+#define D18F2x09C_x0000_000D_TxCPUpdPeriod_WIDTH                3
+#define D18F2x09C_x0000_000D_TxCPUpdPeriod_MASK                 0x70
+#define D18F2x09C_x0000_000D_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_000D_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_000D_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_000D_TxDLLWakeupTime_OFFSET             8
+#define D18F2x09C_x0000_000D_TxDLLWakeupTime_WIDTH              2
+#define D18F2x09C_x0000_000D_TxDLLWakeupTime_MASK               0x300
+#define D18F2x09C_x0000_000D_Reserved_15_10_OFFSET              10
+#define D18F2x09C_x0000_000D_Reserved_15_10_WIDTH               6
+#define D18F2x09C_x0000_000D_Reserved_15_10_MASK                0xfc00
+#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_OFFSET           16
+#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_WIDTH            4
+#define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_MASK             0xf0000
+#define D18F2x09C_x0000_000D_RxCPUpdPeriod_OFFSET               20
+#define D18F2x09C_x0000_000D_RxCPUpdPeriod_WIDTH                3
+#define D18F2x09C_x0000_000D_RxCPUpdPeriod_MASK                 0x700000
+#define D18F2x09C_x0000_000D_Reserved_23_23_OFFSET              23
+#define D18F2x09C_x0000_000D_Reserved_23_23_WIDTH               1
+#define D18F2x09C_x0000_000D_Reserved_23_23_MASK                0x800000
+#define D18F2x09C_x0000_000D_RxDLLWakeupTime_OFFSET             24
+#define D18F2x09C_x0000_000D_RxDLLWakeupTime_WIDTH              2
+#define D18F2x09C_x0000_000D_RxDLLWakeupTime_MASK               0x3000000
+#define D18F2x09C_x0000_000D_Reserved_31_26_OFFSET              26
+#define D18F2x09C_x0000_000D_Reserved_31_26_WIDTH               6
+#define D18F2x09C_x0000_000D_Reserved_31_26_MASK                0xfc000000
+
+/// D18F2x09C_x0000_000D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_000D_STRUCT;
+
+
+// **** D18F2x09C_x0000_0030 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0030_ADDRESS                            0x30
+
+// Type
+#define D18F2x09C_x0000_0030_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_WIDTH          3
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_MASK           0xe0
+#define D18F2x09C_x0000_0030_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0030_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0030_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_OFFSET          16
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_MASK            0x1f0000
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_OFFSET         21
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_WIDTH          3
+#define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_MASK           0xe00000
+#define D18F2x09C_x0000_0030_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0030_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0030_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0030
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte0:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte0:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte1:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte1:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0030_STRUCT;
+
+// **** D18F2x09C_x0000_0031 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0031_ADDRESS                            0x31
+
+// Type
+#define D18F2x09C_x0000_0031_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_OFFSET          0
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_MASK            0x1f
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_OFFSET         5
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_WIDTH          3
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_MASK           0xe0
+#define D18F2x09C_x0000_0031_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0031_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0031_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_OFFSET          16
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_MASK            0x1f0000
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_OFFSET         21
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_WIDTH          3
+#define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_MASK           0xe00000
+#define D18F2x09C_x0000_0031_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0031_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0031_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0031
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte2:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte2:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte3:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte3:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0031_STRUCT;
+
+// **** D18F2x09C_x0000_0033 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0033_ADDRESS                            0x33
+
+// Type
+#define D18F2x09C_x0000_0033_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_WIDTH          3
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_MASK           0xe0
+#define D18F2x09C_x0000_0033_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0033_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0033_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_OFFSET          16
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_MASK            0x1f0000
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_OFFSET         21
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_WIDTH          3
+#define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_MASK           0xe00000
+#define D18F2x09C_x0000_0033_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0033_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0033_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0033
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte0:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte0:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte1:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte1:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0033_STRUCT;
+
+// **** D18F2x09C_x0000_0034 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0034_ADDRESS                            0x34
+
+// Type
+#define D18F2x09C_x0000_0034_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_OFFSET          0
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_MASK            0x1f
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_OFFSET         5
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_WIDTH          3
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_MASK           0xe0
+#define D18F2x09C_x0000_0034_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0034_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0034_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_OFFSET          16
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_MASK            0x1f0000
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_OFFSET         21
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_WIDTH          3
+#define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_MASK           0xe00000
+#define D18F2x09C_x0000_0034_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0034_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0034_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0034
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte2:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte2:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte3:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte3:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0034_STRUCT;
+
+// **** D18F2x09C_x0000_0040 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0040_ADDRESS                            0x40
+
+// Type
+#define D18F2x09C_x0000_0040_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_WIDTH          3
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_MASK           0xe0
+#define D18F2x09C_x0000_0040_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0040_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0040_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_OFFSET          16
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_MASK            0x1f0000
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_OFFSET         21
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_WIDTH          3
+#define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_MASK           0xe00000
+#define D18F2x09C_x0000_0040_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0040_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0040_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte4:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte4:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte5:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte5:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0040_STRUCT;
+
+// **** D18F2x09C_x0000_0041 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0041_ADDRESS                            0x41
+
+// Type
+#define D18F2x09C_x0000_0041_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_OFFSET          0
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_MASK            0x1f
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_OFFSET         5
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_WIDTH          3
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_MASK           0xe0
+#define D18F2x09C_x0000_0041_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0041_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0041_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_OFFSET          16
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_MASK            0x1f0000
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_OFFSET         21
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_WIDTH          3
+#define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_MASK           0xe00000
+#define D18F2x09C_x0000_0041_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0041_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0041_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0041
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte6:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte6:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte7:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte7:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0041_STRUCT;
+
+// **** D18F2x09C_x0000_0043 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0043_ADDRESS                            0x43
+
+// Type
+#define D18F2x09C_x0000_0043_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_WIDTH          3
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_MASK           0xe0
+#define D18F2x09C_x0000_0043_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0043_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0043_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_OFFSET          16
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_MASK            0x1f0000
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_OFFSET         21
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_WIDTH          3
+#define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_MASK           0xe00000
+#define D18F2x09C_x0000_0043_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0043_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0043_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0043
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte4:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte4:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte5:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte5:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0043_STRUCT;
+
+// **** D18F2x09C_x0000_0044 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0044_ADDRESS                            0x44
+
+// Type
+#define D18F2x09C_x0000_0044_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_OFFSET          0
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_MASK            0x1f
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_OFFSET         5
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_WIDTH          3
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_MASK           0xe0
+#define D18F2x09C_x0000_0044_Reserved_15_8_OFFSET               8
+#define D18F2x09C_x0000_0044_Reserved_15_8_WIDTH                8
+#define D18F2x09C_x0000_0044_Reserved_15_8_MASK                 0xff00
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_OFFSET          16
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_MASK            0x1f0000
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_OFFSET         21
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_WIDTH          3
+#define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_MASK           0xe00000
+#define D18F2x09C_x0000_0044_Reserved_31_24_OFFSET              24
+#define D18F2x09C_x0000_0044_Reserved_31_24_WIDTH               8
+#define D18F2x09C_x0000_0044_Reserved_31_24_MASK                0xff000000
+
+/// D18F2x09C_x0000_0044
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       WrDqsFineDly_Byte6:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte6:3 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                       WrDqsFineDly_Byte7:5 ; ///<
+    UINT32                                      WrDqsGrossDly_Byte7:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0044_STRUCT;
+
+// **** D18F2x09C_x0000_0050 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0050_ADDRESS                            0x50
+
+// Type
+#define D18F2x09C_x0000_0050_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_OFFSET          0
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_MASK            0x1f
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_OFFSET         5
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_MASK           0x60
+#define D18F2x09C_x0000_0050_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_0050_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_0050_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_OFFSET          8
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_MASK            0x1f00
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_OFFSET         13
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_MASK           0x6000
+#define D18F2x09C_x0000_0050_Reserved_15_15_OFFSET              15
+#define D18F2x09C_x0000_0050_Reserved_15_15_WIDTH               1
+#define D18F2x09C_x0000_0050_Reserved_15_15_MASK                0x8000
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_OFFSET          16
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_MASK            0x1f0000
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_OFFSET         21
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_MASK           0x600000
+#define D18F2x09C_x0000_0050_Reserved_23_23_OFFSET              23
+#define D18F2x09C_x0000_0050_Reserved_23_23_WIDTH               1
+#define D18F2x09C_x0000_0050_Reserved_23_23_MASK                0x800000
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_OFFSET          24
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_WIDTH           5
+#define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_MASK            0x1f000000
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_OFFSET         29
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_WIDTH          2
+#define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_MASK           0x60000000
+#define D18F2x09C_x0000_0050_Reserved_31_31_OFFSET              31
+#define D18F2x09C_x0000_0050_Reserved_31_31_WIDTH               1
+#define D18F2x09C_x0000_0050_Reserved_31_31_MASK                0x80000000
+
+/// D18F2x09C_x0000_0050
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PhRecFineDly_Byte0:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte0:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte1:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte1:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte2:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte2:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte3:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte3:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0050_STRUCT;
+
+// **** D18F2x09C_x0000_0051 Register Definition ****
+// Address
+#define D18F2x09C_x0000_0051_ADDRESS                            0x51
+
+// Type
+#define D18F2x09C_x0000_0051_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_OFFSET          0
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_MASK            0x1f
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_OFFSET         5
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_MASK           0x60
+#define D18F2x09C_x0000_0051_Reserved_7_7_OFFSET                7
+#define D18F2x09C_x0000_0051_Reserved_7_7_WIDTH                 1
+#define D18F2x09C_x0000_0051_Reserved_7_7_MASK                  0x80
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_OFFSET          8
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_MASK            0x1f00
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_OFFSET         13
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_MASK           0x6000
+#define D18F2x09C_x0000_0051_Reserved_15_15_OFFSET              15
+#define D18F2x09C_x0000_0051_Reserved_15_15_WIDTH               1
+#define D18F2x09C_x0000_0051_Reserved_15_15_MASK                0x8000
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_OFFSET          16
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_MASK            0x1f0000
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_OFFSET         21
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_MASK           0x600000
+#define D18F2x09C_x0000_0051_Reserved_23_23_OFFSET              23
+#define D18F2x09C_x0000_0051_Reserved_23_23_WIDTH               1
+#define D18F2x09C_x0000_0051_Reserved_23_23_MASK                0x800000
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_OFFSET          24
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_WIDTH           5
+#define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_MASK            0x1f000000
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_OFFSET         29
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_WIDTH          2
+#define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_MASK           0x60000000
+#define D18F2x09C_x0000_0051_Reserved_31_31_OFFSET              31
+#define D18F2x09C_x0000_0051_Reserved_31_31_WIDTH               1
+#define D18F2x09C_x0000_0051_Reserved_31_31_MASK                0x80000000
+
+/// D18F2x09C_x0000_0051
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PhRecFineDly_Byte4:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte4:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte5:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte5:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte6:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte6:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                       PhRecFineDly_Byte7:5 ; ///<
+    UINT32                                      PhRecGrossDly_Byte7:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0000_0051_STRUCT;
+
+
+
+
+
+// **** D18F2x09C_x0D0F_0002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0002_ADDRESS                            0xd0f0002
+
+// Type
+#define D18F2x09C_x0D0F_0002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0002_STRUCT;
+
+// **** D18F2x09C_x0D0F_0006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0006_ADDRESS                            0xd0f0006
+
+// Type
+#define D18F2x09C_x0D0F_0006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0006_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0006_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0006_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0006_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0006_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0006_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0006_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0006_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0006_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0006_STRUCT;
+
+// **** D18F2x09C_x0D0F_000A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_000A_ADDRESS                            0xd0f000a
+
+// Type
+#define D18F2x09C_x0D0F_000A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_000A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_000A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_000A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_000A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_000A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_000A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_000A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_000A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_000A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_000A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_000A_STRUCT;
+
+// **** D18F2x09C_x0D0F_000F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_000F_ADDRESS                            0xd0f000f
+
+// Type
+#define D18F2x09C_x0D0F_000F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_000F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_000F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_000F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_000F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_000F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_000F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_000F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_000F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0010 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0010_ADDRESS                            0xd0f0010
+
+// Type
+#define D18F2x09C_x0D0F_0010_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0010_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0010_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0010_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0010_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0010_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0010_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0010_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0010_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0010_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0010_STRUCT;
+
+
+
+
+// **** D18F2x09C_x0D0F_0102 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0102_ADDRESS                            0xd0f0102
+
+// Type
+#define D18F2x09C_x0D0F_0102_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0102_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0102_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0102_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0102_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0102_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0102_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0102_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0102_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0102_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0102_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0102_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0102_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0102_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0102_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0102_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0102
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0102_STRUCT;
+
+// **** D18F2x09C_x0D0F_0106 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0106_ADDRESS                            0xd0f0106
+
+// Type
+#define D18F2x09C_x0D0F_0106_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0106_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0106_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0106_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0106_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0106_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0106_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0106_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0106_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0106_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0106
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0106_STRUCT;
+
+// **** D18F2x09C_x0D0F_010A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_010A_ADDRESS                            0xd0f010a
+
+// Type
+#define D18F2x09C_x0D0F_010A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_010A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_010A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_010A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_010A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_010A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_010A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_010A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_010A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_010A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_010A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_010A_STRUCT;
+
+// **** D18F2x09C_x0D0F_010F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_010F_ADDRESS                            0xd0f010f
+
+// Type
+#define D18F2x09C_x0D0F_010F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_010F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_010F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_010F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_010F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_010F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_010F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_010F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_010F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0110 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0110_ADDRESS                            0xd0f0110
+
+// Type
+#define D18F2x09C_x0D0F_0110_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0110_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0110_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0110_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0110_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0110_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0110_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0110_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0110_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0110_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0110_STRUCT;
+
+// **** D18F2x09C_x0D0F_011F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_011F_ADDRESS                            0xd0f011f
+
+// Type
+#define D18F2x09C_x0D0F_011F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_011F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_011F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_011F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_011F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_011F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_011F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_011F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_011F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_011F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_011F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_011F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0202 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0202_ADDRESS                            0xd0f0202
+
+// Type
+#define D18F2x09C_x0D0F_0202_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0202_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0202_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0202_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0202_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0202_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0202_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0202_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0202_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0202_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0202_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0202_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0202_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0202_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0202_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0202_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0202
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0202_STRUCT;
+
+// **** D18F2x09C_x0D0F_0206 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0206_ADDRESS                            0xd0f0206
+
+// Type
+#define D18F2x09C_x0D0F_0206_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0206_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0206_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0206_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0206_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0206_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0206_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0206_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0206_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0206_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0206
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0206_STRUCT;
+
+// **** D18F2x09C_x0D0F_020A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_020A_ADDRESS                            0xd0f020a
+
+// Type
+#define D18F2x09C_x0D0F_020A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_020A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_020A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_020A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_020A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_020A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_020A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_020A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_020A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_020A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_020A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_020A_STRUCT;
+
+// **** D18F2x09C_x0D0F_020F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_020F_ADDRESS                            0xd0f020f
+
+// Type
+#define D18F2x09C_x0D0F_020F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_020F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_020F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_020F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_020F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_020F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_020F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_020F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_020F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0210 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0210_ADDRESS                            0xd0f0210
+
+// Type
+#define D18F2x09C_x0D0F_0210_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0210_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0210_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0210_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0210_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0210_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0210_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0210_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0210_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0210_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0210
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0210_STRUCT;
+
+// **** D18F2x09C_x0D0F_021F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_021F_ADDRESS                            0xd0f021f
+
+// Type
+#define D18F2x09C_x0D0F_021F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_021F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_021F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_021F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_021F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_021F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_021F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_021F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_021F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_021F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_021F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_021F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0302 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0302_ADDRESS                            0xd0f0302
+
+// Type
+#define D18F2x09C_x0D0F_0302_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0302_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0302_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0302_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0302_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0302_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0302_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0302_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0302_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0302_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0302_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0302_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0302_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0302_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0302_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0302_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0302
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0302_STRUCT;
+
+// **** D18F2x09C_x0D0F_0306 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0306_ADDRESS                            0xd0f0306
+
+// Type
+#define D18F2x09C_x0D0F_0306_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0306_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0306_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0306_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0306_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0306_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0306_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0306_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0306_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0306_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0306
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0306_STRUCT;
+
+// **** D18F2x09C_x0D0F_030A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_030A_ADDRESS                            0xd0f030a
+
+// Type
+#define D18F2x09C_x0D0F_030A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_030A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_030A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_030A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_030A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_030A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_030A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_030A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_030A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_030A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_030A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_030A_STRUCT;
+
+// **** D18F2x09C_x0D0F_030F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_030F_ADDRESS                            0xd0f030f
+
+// Type
+#define D18F2x09C_x0D0F_030F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_030F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_030F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_030F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_030F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_030F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_030F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_030F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_030F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0310 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0310_ADDRESS                            0xd0f0310
+
+// Type
+#define D18F2x09C_x0D0F_0310_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0310_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0310_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0310_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0310_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0310_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0310_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0310_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0310_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0310_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0310
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0310_STRUCT;
+
+// **** D18F2x09C_x0D0F_031F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_031F_ADDRESS                            0xd0f031f
+
+// Type
+#define D18F2x09C_x0D0F_031F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_031F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_031F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_031F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_031F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_031F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_031F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_031F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_031F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_031F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_031F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_031F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0402 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0402_ADDRESS                            0xd0f0402
+
+// Type
+#define D18F2x09C_x0D0F_0402_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0402_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0402_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0402_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0402_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0402_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0402_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0402_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0402_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0402_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0402_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0402_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0402_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0402_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0402_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0402_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0402
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0402_STRUCT;
+
+// **** D18F2x09C_x0D0F_0406 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0406_ADDRESS                            0xd0f0406
+
+// Type
+#define D18F2x09C_x0D0F_0406_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0406_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0406_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0406_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0406_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0406_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0406_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0406_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0406_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0406_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0406
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0406_STRUCT;
+
+// **** D18F2x09C_x0D0F_040A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_040A_ADDRESS                            0xd0f040a
+
+// Type
+#define D18F2x09C_x0D0F_040A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_040A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_040A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_040A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_040A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_040A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_040A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_040A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_040A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_040A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_040A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_040A_STRUCT;
+
+// **** D18F2x09C_x0D0F_040F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_040F_ADDRESS                            0xd0f040f
+
+// Type
+#define D18F2x09C_x0D0F_040F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_040F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_040F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_040F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_040F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_040F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_040F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_040F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_040F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0410 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0410_ADDRESS                            0xd0f0410
+
+// Type
+#define D18F2x09C_x0D0F_0410_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0410_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0410_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0410_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0410_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0410_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0410_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0410_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0410_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0410_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0410
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0410_STRUCT;
+
+// **** D18F2x09C_x0D0F_041F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_041F_ADDRESS                            0xd0f041f
+
+// Type
+#define D18F2x09C_x0D0F_041F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_041F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_041F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_041F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_041F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_041F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_041F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_041F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_041F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_041F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_041F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_041F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0502 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0502_ADDRESS                            0xd0f0502
+
+// Type
+#define D18F2x09C_x0D0F_0502_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0502_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0502_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0502_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0502_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0502_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0502_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0502_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0502_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0502_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0502_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0502_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0502_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0502_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0502_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0502_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0502
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0502_STRUCT;
+
+// **** D18F2x09C_x0D0F_0506 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0506_ADDRESS                            0xd0f0506
+
+// Type
+#define D18F2x09C_x0D0F_0506_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0506_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0506_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0506_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0506_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0506_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0506_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0506_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0506_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0506_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0506
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0506_STRUCT;
+
+// **** D18F2x09C_x0D0F_050A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_050A_ADDRESS                            0xd0f050a
+
+// Type
+#define D18F2x09C_x0D0F_050A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_050A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_050A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_050A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_050A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_050A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_050A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_050A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_050A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_050A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_050A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_050A_STRUCT;
+
+// **** D18F2x09C_x0D0F_050F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_050F_ADDRESS                            0xd0f050f
+
+// Type
+#define D18F2x09C_x0D0F_050F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_050F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_050F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_050F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_050F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_050F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_050F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_050F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_050F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0510 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0510_ADDRESS                            0xd0f0510
+
+// Type
+#define D18F2x09C_x0D0F_0510_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0510_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0510_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0510_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0510_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0510_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0510_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0510_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0510_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0510_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0510
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0510_STRUCT;
+
+// **** D18F2x09C_x0D0F_051F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_051F_ADDRESS                            0xd0f051f
+
+// Type
+#define D18F2x09C_x0D0F_051F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_051F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_051F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_051F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_051F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_051F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_051F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_051F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_051F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_051F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_051F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_051F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0602 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0602_ADDRESS                            0xd0f0602
+
+// Type
+#define D18F2x09C_x0D0F_0602_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0602_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0602_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0602_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0602_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0602_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0602_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0602_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0602_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0602_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0602_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0602_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0602_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0602_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0602_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0602_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0602
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0602_STRUCT;
+
+// **** D18F2x09C_x0D0F_0606 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0606_ADDRESS                            0xd0f0606
+
+// Type
+#define D18F2x09C_x0D0F_0606_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0606_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0606_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0606_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0606_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0606_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0606_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0606_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0606_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0606_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0606
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0606_STRUCT;
+
+// **** D18F2x09C_x0D0F_060A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_060A_ADDRESS                            0xd0f060a
+
+// Type
+#define D18F2x09C_x0D0F_060A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_060A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_060A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_060A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_060A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_060A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_060A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_060A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_060A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_060A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_060A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_060A_STRUCT;
+
+// **** D18F2x09C_x0D0F_060F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_060F_ADDRESS                            0xd0f060f
+
+// Type
+#define D18F2x09C_x0D0F_060F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_060F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_060F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_060F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_060F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_060F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_060F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_060F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_060F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0610 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0610_ADDRESS                            0xd0f0610
+
+// Type
+#define D18F2x09C_x0D0F_0610_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0610_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0610_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0610_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0610_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0610_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0610_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0610_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0610_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0610_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0610
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0610_STRUCT;
+
+// **** D18F2x09C_x0D0F_061F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_061F_ADDRESS                            0xd0f061f
+
+// Type
+#define D18F2x09C_x0D0F_061F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_061F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_061F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_061F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_061F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_061F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_061F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_061F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_061F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_061F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_061F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_061F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0702 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0702_ADDRESS                            0xd0f0702
+
+// Type
+#define D18F2x09C_x0D0F_0702_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0702_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0702_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0702_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0702_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0702_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0702_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0702_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0702_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0702_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0702_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0702_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0702_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0702_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0702_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0702_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0702
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0702_STRUCT;
+
+// **** D18F2x09C_x0D0F_0706 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0706_ADDRESS                            0xd0f0706
+
+// Type
+#define D18F2x09C_x0D0F_0706_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0706_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0706_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0706_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0706_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0706_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0706_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0706_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0706_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0706_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0706
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0706_STRUCT;
+
+// **** D18F2x09C_x0D0F_070A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_070A_ADDRESS                            0xd0f070a
+
+// Type
+#define D18F2x09C_x0D0F_070A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_070A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_070A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_070A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_070A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_070A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_070A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_070A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_070A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_070A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_070A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_070A_STRUCT;
+
+// **** D18F2x09C_x0D0F_070F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_070F_ADDRESS                            0xd0f070f
+
+// Type
+#define D18F2x09C_x0D0F_070F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_070F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_070F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_070F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_070F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_070F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_070F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_070F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_070F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0710 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0710_ADDRESS                            0xd0f0710
+
+// Type
+#define D18F2x09C_x0D0F_0710_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0710_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0710_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0710_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0710_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0710_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0710_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0710_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0710_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0710_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0710
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0710_STRUCT;
+
+// **** D18F2x09C_x0D0F_071F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_071F_ADDRESS                            0xd0f071f
+
+// Type
+#define D18F2x09C_x0D0F_071F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_071F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_071F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_071F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_071F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_071F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_071F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_071F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_071F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_071F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_071F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_071F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_0F02 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F02_ADDRESS                            0xd0f0f02
+
+// Type
+#define D18F2x09C_x0D0F_0F02_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F02_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0F02_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0F02_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0F02_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0F02_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0F02_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0F02_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_0F02_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_0F02_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_0F02_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_0F02_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_0F02_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_0F02_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_0F02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F02_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F06 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F06_ADDRESS                            0xd0f0f06
+
+// Type
+#define D18F2x09C_x0D0F_0F06_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F06_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0F06_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0F06_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0F06_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0F06_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0F06_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0F06_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0F06_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0F06_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0F06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F06_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F0A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F0A_ADDRESS                            0xd0f0f0a
+
+// Type
+#define D18F2x09C_x0D0F_0F0A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F0A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_0F0A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_0F0A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_0F0A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_0F0A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_0F0A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_0F0A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_0F0A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F0A_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F0F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F0F_ADDRESS                            0xd0f0f0f
+
+// Type
+#define D18F2x09C_x0D0F_0F0F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0F0F_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_OFFSET             12
+#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_WIDTH              3
+#define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_MASK               0x7000
+#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_0F0F_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_0F0F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                          AlwaysEnDllClks:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F0F_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F10 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F10_ADDRESS                            0xd0f0f10
+
+// Type
+#define D18F2x09C_x0D0F_0F10_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F10_Reserved_11_0_OFFSET               0
+#define D18F2x09C_x0D0F_0F10_Reserved_11_0_WIDTH                12
+#define D18F2x09C_x0D0F_0F10_Reserved_11_0_MASK                 0xfff
+#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_OFFSET              12
+#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_WIDTH               1
+#define D18F2x09C_x0D0F_0F10_EnRxPadStandby_MASK                0x1000
+#define D18F2x09C_x0D0F_0F10_Reserved_31_13_OFFSET              13
+#define D18F2x09C_x0D0F_0F10_Reserved_31_13_WIDTH               19
+#define D18F2x09C_x0D0F_0F10_Reserved_31_13_MASK                0xffffe000
+
+/// D18F2x09C_x0D0F_0F10
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           EnRxPadStandby:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F10_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F13 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F13_ADDRESS                            0xd0f0f13
+
+// Type
+#define D18F2x09C_x0D0F_0F13_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_OFFSET                0
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_WIDTH                 1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyL_MASK                  0x1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_OFFSET                1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_WIDTH                 1
+#define D18F2x09C_x0D0F_0F13_DllDisEarlyU_MASK                  0x2
+#define D18F2x09C_x0D0F_0F13_Reserved_6_2_OFFSET                2
+#define D18F2x09C_x0D0F_0F13_Reserved_6_2_WIDTH                 5
+#define D18F2x09C_x0D0F_0F13_Reserved_6_2_MASK                  0x7c
+#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_OFFSET          7
+#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_WIDTH           1
+#define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_MASK            0x80
+#define D18F2x09C_x0D0F_0F13_Reserved_13_8_OFFSET               8
+#define D18F2x09C_x0D0F_0F13_Reserved_13_8_WIDTH                6
+#define D18F2x09C_x0D0F_0F13_Reserved_13_8_MASK                 0x3f00
+#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_OFFSET                  14
+#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_WIDTH                   1
+#define D18F2x09C_x0D0F_0F13_ProcOdtAdv_MASK                    0x4000
+#define D18F2x09C_x0D0F_0F13_Reserved_31_15_OFFSET              15
+#define D18F2x09C_x0D0F_0F13_Reserved_31_15_WIDTH               17
+#define D18F2x09C_x0D0F_0F13_Reserved_31_15_MASK                0xffff8000
+
+/// D18F2x09C_x0D0F_0F13
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DllDisEarlyL:1 ; ///<
+    UINT32                                             DllDisEarlyU:1 ; ///<
+    UINT32                                             Reserved_6_2:5 ; ///<
+    UINT32                                       RxDqsUDllPowerDown:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                               ProcOdtAdv:1 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F13_STRUCT;
+
+// **** D18F2x09C_x0D0F_0F1F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_0F1F_ADDRESS                            0xd0f0f1f
+
+// Type
+#define D18F2x09C_x0D0F_0F1F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_0F1F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_0F1F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_0F1F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_0F1F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_0F1F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_0F1F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_0F1F_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_2002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2002_ADDRESS                            0xd0f2002
+
+// Type
+#define D18F2x09C_x0D0F_2002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_2002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_2002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_2002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_2002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_2002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_2002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_2002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_2002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_2002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_2002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_2002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_2002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_2002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_2002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_2002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2002_STRUCT;
+
+// **** D18F2x09C_x0D0F_201F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_201F_ADDRESS                            0xd0f201f
+
+// Type
+#define D18F2x09C_x0D0F_201F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_201F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_201F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_201F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_201F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_201F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_201F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_201F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_201F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_201F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_201F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_201F_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_2030 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2030_ADDRESS                            0xd0f2030
+
+// Type
+#define D18F2x09C_x0D0F_2030_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2030_Reserved_3_0_OFFSET                0
+#define D18F2x09C_x0D0F_2030_Reserved_3_0_WIDTH                 4
+#define D18F2x09C_x0D0F_2030_Reserved_3_0_MASK                  0xf
+#define D18F2x09C_x0D0F_2030_PwrDn_OFFSET                       4
+#define D18F2x09C_x0D0F_2030_PwrDn_WIDTH                        1
+#define D18F2x09C_x0D0F_2030_PwrDn_MASK                         0x10
+#define D18F2x09C_x0D0F_2030_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_2030_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_2030_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_2030
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                    PwrDn:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2030_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_2102 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2102_ADDRESS                            0xd0f2102
+
+// Type
+#define D18F2x09C_x0D0F_2102_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2102_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_2102_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_2102_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_2102_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_2102_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_2102_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_2102_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_2102_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_2102_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_2102_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_2102_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_2102_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_2102_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_2102_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_2102_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_2102
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2102_STRUCT;
+
+// **** D18F2x09C_x0D0F_211F Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_211F_ADDRESS                            0xd0f211f
+
+// Type
+#define D18F2x09C_x0D0F_211F_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_211F_Reserved_2_0_OFFSET                0
+#define D18F2x09C_x0D0F_211F_Reserved_2_0_WIDTH                 3
+#define D18F2x09C_x0D0F_211F_Reserved_2_0_MASK                  0x7
+#define D18F2x09C_x0D0F_211F_RxVioLvl_OFFSET                    3
+#define D18F2x09C_x0D0F_211F_RxVioLvl_WIDTH                     2
+#define D18F2x09C_x0D0F_211F_RxVioLvl_MASK                      0x18
+#define D18F2x09C_x0D0F_211F_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_211F_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_211F_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_211F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                 RxVioLvl:2 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_211F_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_2130 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_2130_ADDRESS                            0xd0f2130
+
+// Type
+#define D18F2x09C_x0D0F_2130_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_2130_Reserved_3_0_OFFSET                0
+#define D18F2x09C_x0D0F_2130_Reserved_3_0_WIDTH                 4
+#define D18F2x09C_x0D0F_2130_Reserved_3_0_MASK                  0xf
+#define D18F2x09C_x0D0F_2130_PwrDn_OFFSET                       4
+#define D18F2x09C_x0D0F_2130_PwrDn_WIDTH                        1
+#define D18F2x09C_x0D0F_2130_PwrDn_MASK                         0x10
+#define D18F2x09C_x0D0F_2130_Reserved_31_5_OFFSET               5
+#define D18F2x09C_x0D0F_2130_Reserved_31_5_WIDTH                27
+#define D18F2x09C_x0D0F_2130_Reserved_31_5_MASK                 0xffffffe0
+
+/// D18F2x09C_x0D0F_2130
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                    PwrDn:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_2130_STRUCT;
+
+// Field Data
+#define D18F2x09C_x0D0F_4009_Reserved_1_0_OFFSET                0
+#define D18F2x09C_x0D0F_4009_Reserved_1_0_WIDTH                 2
+#define D18F2x09C_x0D0F_4009_Reserved_1_0_MASK                  0x3
+#define D18F2x09C_x0D0F_4009_ComparatorAdjust_OFFSET            2
+#define D18F2x09C_x0D0F_4009_ComparatorAdjust_WIDTH             2
+#define D18F2x09C_x0D0F_4009_ComparatorAdjust_MASK              0xc
+#define D18F2x09C_x0D0F_4009_Reserved_13_4_OFFSET               4
+#define D18F2x09C_x0D0F_4009_Reserved_13_4_WIDTH                10
+#define D18F2x09C_x0D0F_4009_Reserved_13_4_MASK                 0x3ff0
+#define D18F2x09C_x0D0F_4009_CmpVioLvl_OFFSET                   14
+#define D18F2x09C_x0D0F_4009_CmpVioLvl_WIDTH                    2
+#define D18F2x09C_x0D0F_4009_CmpVioLvl_MASK                     0xc000
+#define D18F2x09C_x0D0F_4009_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_4009_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_4009_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_4009
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                         ComparatorAdjust:2 ; ///<
+    UINT32                                            Reserved_13_4:10; ///<
+    UINT32                                                CmpVioLvl:2 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_4009_STRUCT;
+
+// **** D18F2x09C_x0D0F_8002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8002_ADDRESS                            0xd0f8002
+
+// Type
+#define D18F2x09C_x0D0F_8002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_8002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_8002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_8002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_8002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_8002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_8002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_8002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_8002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_8002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8002_STRUCT;
+
+// **** D18F2x09C_x0D0F_8006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8006_ADDRESS                            0xd0f8006
+
+// Type
+#define D18F2x09C_x0D0F_8006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8006_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8006_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8006_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8006_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8006_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8006_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8006_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_8006_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_8006_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_8006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8006_STRUCT;
+
+// **** D18F2x09C_x0D0F_800A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_800A_ADDRESS                            0xd0f800a
+
+// Type
+#define D18F2x09C_x0D0F_800A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_800A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_800A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_800A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_800A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_800A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_800A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_800A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_800A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_800A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_800A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_800A_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0F_8102 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8102_ADDRESS                            0xd0f8102
+
+// Type
+#define D18F2x09C_x0D0F_8102_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8102_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8102_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8102_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8102_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8102_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8102_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8102_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_8102_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_8102_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_8102_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_8102_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_8102_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_8102_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_8102_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_8102_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_8102
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8102_STRUCT;
+
+// **** D18F2x09C_x0D0F_8106 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_8106_ADDRESS                            0xd0f8106
+
+// Type
+#define D18F2x09C_x0D0F_8106_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_8106_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_8106_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_8106_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_8106_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_8106_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_8106_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_8106_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_8106_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_8106_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_8106
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_8106_STRUCT;
+
+// **** D18F2x09C_x0D0F_810A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_810A_ADDRESS                            0xd0f810a
+
+// Type
+#define D18F2x09C_x0D0F_810A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_810A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_810A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_810A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_810A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_810A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_810A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_810A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_810A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_810A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_810A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_810A_STRUCT;
+
+
+
+
+// **** D18F2x09C_x0D0F_C000 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C000_ADDRESS                            0xd0fc000
+
+// Type
+#define D18F2x09C_x0D0F_C000_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C000_Reserved_7_0_OFFSET                0
+#define D18F2x09C_x0D0F_C000_Reserved_7_0_WIDTH                 8
+#define D18F2x09C_x0D0F_C000_Reserved_7_0_MASK                  0xff
+#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_OFFSET       8
+#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_WIDTH        1
+#define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_MASK         0x100
+#define D18F2x09C_x0D0F_C000_Reserved_31_9_OFFSET               9
+#define D18F2x09C_x0D0F_C000_Reserved_31_9_WIDTH                23
+#define D18F2x09C_x0D0F_C000_Reserved_31_9_MASK                 0xfffffe00
+
+/// D18F2x09C_x0D0F_C000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                    LowPowerDrvStrengthEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C000_STRUCT;
+
+// **** D18F2x09C_x0D0F_C002 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C002_ADDRESS                            0xd0fc002
+
+// Type
+#define D18F2x09C_x0D0F_C002_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C002_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C002_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C002_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C002_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C002_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C002_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C002_Reserved_14_12_OFFSET              12
+#define D18F2x09C_x0D0F_C002_Reserved_14_12_WIDTH               3
+#define D18F2x09C_x0D0F_C002_Reserved_14_12_MASK                0x7000
+#define D18F2x09C_x0D0F_C002_ValidTxAndPre_OFFSET               15
+#define D18F2x09C_x0D0F_C002_ValidTxAndPre_WIDTH                1
+#define D18F2x09C_x0D0F_C002_ValidTxAndPre_MASK                 0x8000
+#define D18F2x09C_x0D0F_C002_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_C002_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_C002_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_C002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                            ValidTxAndPre:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C002_STRUCT;
+
+// **** D18F2x09C_x0D0F_C006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C006_ADDRESS                            0xd0fc006
+
+// Type
+#define D18F2x09C_x0D0F_C006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C006_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C006_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C006_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C006_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C006_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C006_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C006_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C006_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C006_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C006_STRUCT;
+
+// **** D18F2x09C_x0D0F_C00A Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C00A_ADDRESS                            0xd0fc00a
+
+// Type
+#define D18F2x09C_x0D0F_C00A_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C00A_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C00A_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C00A_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C00A_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C00A_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C00A_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C00A_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C00A_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C00A_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C00A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C00A_STRUCT;
+
+// **** D18F2x09C_x0D0F_C00E Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C00E_ADDRESS                            0xd0fc00e
+
+// Type
+#define D18F2x09C_x0D0F_C00E_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C00E_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C00E_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C00E_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C00E_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C00E_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C00E_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C00E_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C00E_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C00E_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C00E
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C00E_STRUCT;
+
+// **** D18F2x09C_x0D0F_C012 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_C012_ADDRESS                            0xd0fc012
+
+// Type
+#define D18F2x09C_x0D0F_C012_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_C012_TxPreN_OFFSET                      0
+#define D18F2x09C_x0D0F_C012_TxPreN_WIDTH                       6
+#define D18F2x09C_x0D0F_C012_TxPreN_MASK                        0x3f
+#define D18F2x09C_x0D0F_C012_TxPreP_OFFSET                      6
+#define D18F2x09C_x0D0F_C012_TxPreP_WIDTH                       6
+#define D18F2x09C_x0D0F_C012_TxPreP_MASK                        0xfc0
+#define D18F2x09C_x0D0F_C012_Reserved_31_12_OFFSET              12
+#define D18F2x09C_x0D0F_C012_Reserved_31_12_WIDTH               20
+#define D18F2x09C_x0D0F_C012_Reserved_31_12_MASK                0xfffff000
+
+/// D18F2x09C_x0D0F_C012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   TxPreN:6 ; ///<
+    UINT32                                                   TxPreP:6 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_C012_STRUCT;
+
+
+
+
+// **** D18F2x09C_x0D0F_E006 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_E006_ADDRESS                            0xd0fe006
+
+// Type
+#define D18F2x09C_x0D0F_E006_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_E006_PllLockTime_OFFSET                 0
+#define D18F2x09C_x0D0F_E006_PllLockTime_WIDTH                  16
+#define D18F2x09C_x0D0F_E006_PllLockTime_MASK                   0xffff
+#define D18F2x09C_x0D0F_E006_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_E006_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_E006_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_E006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              PllLockTime:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_E006_STRUCT;
+
+
+// **** D18F2x09C_x0D0F_E013 Register Definition ****
+// Address
+#define D18F2x09C_x0D0F_E013_ADDRESS                            0xd0fe013
+
+// Type
+#define D18F2x09C_x0D0F_E013_TYPE                               TYPE_D18F2x09C
+// Field Data
+#define D18F2x09C_x0D0F_E013_PllRegWaitTime_OFFSET              0
+#define D18F2x09C_x0D0F_E013_PllRegWaitTime_WIDTH               16
+#define D18F2x09C_x0D0F_E013_PllRegWaitTime_MASK                0xffff
+#define D18F2x09C_x0D0F_E013_Reserved_31_16_OFFSET              16
+#define D18F2x09C_x0D0F_E013_Reserved_31_16_WIDTH               16
+#define D18F2x09C_x0D0F_E013_Reserved_31_16_MASK                0xffff0000
+
+/// D18F2x09C_x0D0F_E013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PllRegWaitTime:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0F_E013_STRUCT;
+
+
+// **** DxF0xE4_x02 Register Definition ****
+// Address
+#define DxF0xE4_x02_ADDRESS                                     0x2
+
+// Type
+#define DxF0xE4_x02_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x02_Reserved_14_0_OFFSET                        0
+#define DxF0xE4_x02_Reserved_14_0_WIDTH                         15
+#define DxF0xE4_x02_Reserved_14_0_MASK                          0x7fff
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET               15
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH                1
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK                 0x8000
+#define DxF0xE4_x02_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_x02_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_x02_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_x02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                   RegsLcAllowTxL1Control:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x02_STRUCT;
+
+// **** DxF0xE4_x20 Register Definition ****
+// Address
+#define DxF0xE4_x20_ADDRESS                                     0x20
+
+// Type
+#define DxF0xE4_x20_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x20_Reserved_14_0_OFFSET                        0
+#define DxF0xE4_x20_Reserved_14_0_WIDTH                         15
+#define DxF0xE4_x20_Reserved_14_0_MASK                          0x7fff
+#define DxF0xE4_x20_TxFlushTlpDis_OFFSET                        15
+#define DxF0xE4_x20_TxFlushTlpDis_WIDTH                         1
+#define DxF0xE4_x20_TxFlushTlpDis_MASK                          0x8000
+#define DxF0xE4_x20_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_x20_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_x20_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                            TxFlushTlpDis:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x20_STRUCT;
+
+// **** DxF0xE4_x50 Register Definition ****
+// Address
+#define DxF0xE4_x50_ADDRESS                                     0x50
+
+// Type
+#define DxF0xE4_x50_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x50_PortLaneReversal_OFFSET                     0
+#define DxF0xE4_x50_PortLaneReversal_WIDTH                      1
+#define DxF0xE4_x50_PortLaneReversal_MASK                       0x1
+#define DxF0xE4_x50_PhyLinkWidth_OFFSET                         1
+#define DxF0xE4_x50_PhyLinkWidth_WIDTH                          6
+#define DxF0xE4_x50_PhyLinkWidth_MASK                           0x7e
+#define DxF0xE4_x50_Reserved_31_7_OFFSET                        7
+#define DxF0xE4_x50_Reserved_31_7_WIDTH                         25
+#define DxF0xE4_x50_Reserved_31_7_MASK                          0xffffff80
+
+/// DxF0xE4_x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PortLaneReversal:1 ; ///<
+    UINT32                                             PhyLinkWidth:6 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x50_STRUCT;
+
+// **** DxF0xE4_x70 Register Definition ****
+// Address
+#define DxF0xE4_x70_ADDRESS                                     0x70
+
+// Type
+#define DxF0xE4_x70_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x70_Reserved_15_0_OFFSET                        0
+#define DxF0xE4_x70_Reserved_15_0_WIDTH                         16
+#define DxF0xE4_x70_Reserved_15_0_MASK                          0xffff
+#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET                      16
+#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH                       3
+#define DxF0xE4_x70_RxRcbCplTimeout_MASK                        0x70000
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET                  19
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH                   1
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK                    0x80000
+#define DxF0xE4_x70_Reserved_31_20_OFFSET                       20
+#define DxF0xE4_x70_Reserved_31_20_WIDTH                        12
+#define DxF0xE4_x70_Reserved_31_20_MASK                         0xfff00000
+
+/// DxF0xE4_x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                          RxRcbCplTimeout:3 ; ///<
+    UINT32                                      RxRcbCplTimeoutMode:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x70_STRUCT;
+
+// **** DxF0xE4_xA0 Register Definition ****
+// Address
+#define DxF0xE4_xA0_ADDRESS                                     0xa0
+
+// Type
+#define DxF0xE4_xA0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA0_Reserved_3_0_OFFSET                         0
+#define DxF0xE4_xA0_Reserved_3_0_WIDTH                          4
+#define DxF0xE4_xA0_Reserved_3_0_MASK                           0xf
+#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET                     4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH                      4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK                       0xf0
+#define DxF0xE4_xA0_LcL0sInactivity_OFFSET                      8
+#define DxF0xE4_xA0_LcL0sInactivity_WIDTH                       4
+#define DxF0xE4_xA0_LcL0sInactivity_MASK                        0xf00
+#define DxF0xE4_xA0_LcL1Inactivity_OFFSET                       12
+#define DxF0xE4_xA0_LcL1Inactivity_WIDTH                        4
+#define DxF0xE4_xA0_LcL1Inactivity_MASK                         0xf000
+#define DxF0xE4_xA0_Reserved_22_16_OFFSET                       16
+#define DxF0xE4_xA0_Reserved_22_16_WIDTH                        7
+#define DxF0xE4_xA0_Reserved_22_16_MASK                         0x7f0000
+#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET                     23
+#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH                      1
+#define DxF0xE4_xA0_LcL1ImmediateAck_MASK                       0x800000
+#define DxF0xE4_xA0_Reserved_31_24_OFFSET                       24
+#define DxF0xE4_xA0_Reserved_31_24_WIDTH                        8
+#define DxF0xE4_xA0_Reserved_31_24_MASK                         0xff000000
+
+/// DxF0xE4_xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                         Lc16xClearTxPipe:4 ; ///<
+    UINT32                                          LcL0sInactivity:4 ; ///<
+    UINT32                                           LcL1Inactivity:4 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                         LcL1ImmediateAck:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA0_STRUCT;
+
+// **** DxF0xE4_xA1 Register Definition ****
+// Address
+#define DxF0xE4_xA1_ADDRESS                                     0xa1
+
+// Type
+#define DxF0xE4_xA1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA1_Reserved_10_0_OFFSET                        0
+#define DxF0xE4_xA1_Reserved_10_0_WIDTH                         11
+#define DxF0xE4_xA1_Reserved_10_0_MASK                          0x7ff
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET               11
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH                1
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK                 0x800
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET                12
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH                 1
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK                  0x1000
+#define DxF0xE4_xA1_Reserved_31_13_OFFSET                       13
+#define DxF0xE4_xA1_Reserved_31_13_WIDTH                        19
+#define DxF0xE4_xA1_Reserved_31_13_MASK                         0xffffe000
+
+/// DxF0xE4_xA1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_10_0:11; ///<
+    UINT32                                   LcDontGotoL0sifL1Armed:1 ; ///<
+    UINT32                                    LcInitSpdChgWithCsrEn:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA1_STRUCT;
+
+// **** DxF0xE4_xA2 Register Definition ****
+// Address
+#define DxF0xE4_xA2_ADDRESS                                     0xa2
+
+// Type
+#define DxF0xE4_xA2_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA2_LcLinkWidth_OFFSET                          0
+#define DxF0xE4_xA2_LcLinkWidth_WIDTH                           3
+#define DxF0xE4_xA2_LcLinkWidth_MASK                            0x7
+#define DxF0xE4_xA2_Reserved_3_3_OFFSET                         3
+#define DxF0xE4_xA2_Reserved_3_3_WIDTH                          1
+#define DxF0xE4_xA2_Reserved_3_3_MASK                           0x8
+#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET                        4
+#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH                         3
+#define DxF0xE4_xA2_LcLinkWidthRd_MASK                          0x70
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET           7
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH            1
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK             0x80
+#define DxF0xE4_xA2_LcReconfigNow_OFFSET                        8
+#define DxF0xE4_xA2_LcReconfigNow_WIDTH                         1
+#define DxF0xE4_xA2_LcReconfigNow_MASK                          0x100
+#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET               9
+#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH                1
+#define DxF0xE4_xA2_LcRenegotiationSupport_MASK                 0x200
+#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET                      10
+#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH                       1
+#define DxF0xE4_xA2_LcRenegotiateEn_MASK                        0x400
+#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET                    11
+#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH                     1
+#define DxF0xE4_xA2_LcShortReconfigEn_MASK                      0x800
+#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET                 12
+#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH                  1
+#define DxF0xE4_xA2_LcUpconfigureSupport_MASK                   0x1000
+#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET                     13
+#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH                      1
+#define DxF0xE4_xA2_LcUpconfigureDis_MASK                       0x2000
+#define DxF0xE4_xA2_Reserved_19_14_OFFSET                       14
+#define DxF0xE4_xA2_Reserved_19_14_WIDTH                        6
+#define DxF0xE4_xA2_Reserved_19_14_MASK                         0xfc000
+#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET                    20
+#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH                     1
+#define DxF0xE4_xA2_LcUpconfigCapable_MASK                      0x100000
+#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET                   21
+#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH                    2
+#define DxF0xE4_xA2_LcDynLanesPwrState_MASK                     0x600000
+#define DxF0xE4_xA2_Reserved_31_23_OFFSET                       23
+#define DxF0xE4_xA2_Reserved_31_23_WIDTH                        9
+#define DxF0xE4_xA2_Reserved_31_23_MASK                         0xff800000
+
+/// DxF0xE4_xA2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LcLinkWidth:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            LcLinkWidthRd:3 ; ///<
+    UINT32                               LcReconfigArcMissingEscape:1 ; ///<
+    UINT32                                            LcReconfigNow:1 ; ///<
+    UINT32                                   LcRenegotiationSupport:1 ; ///<
+    UINT32                                          LcRenegotiateEn:1 ; ///<
+    UINT32                                        LcShortReconfigEn:1 ; ///<
+    UINT32                                     LcUpconfigureSupport:1 ; ///<
+    UINT32                                         LcUpconfigureDis:1 ; ///<
+    UINT32                                           Reserved_19_14:6 ; ///<
+    UINT32                                        LcUpconfigCapable:1 ; ///<
+    UINT32                                       LcDynLanesPwrState:2 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA2_STRUCT;
+
+// **** DxF0xE4_xA3 Register Definition ****
+// Address
+#define DxF0xE4_xA3_ADDRESS                                     0xa3
+
+// Type
+#define DxF0xE4_xA3_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA3_Reserved_8_0_OFFSET                         0
+#define DxF0xE4_xA3_Reserved_8_0_WIDTH                          9
+#define DxF0xE4_xA3_Reserved_8_0_MASK                           0x1ff
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET              9
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH               1
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK                0x200
+#define DxF0xE4_xA3_Reserved_31_10_OFFSET                       10
+#define DxF0xE4_xA3_Reserved_31_10_WIDTH                        22
+#define DxF0xE4_xA3_Reserved_31_10_MASK                         0xfffffc00
+
+/// DxF0xE4_xA3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                  LcXmitFtsBeforeRecovery:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA3_STRUCT;
+
+/// DxF0xE4_xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LcGen2EnStrap:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                  LcForceDisSwSpeedChange:1 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                LcInitiateLinkSpeedChange:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                               LcSpeedChangeAttemptFailed:1 ; ///<
+    UINT32                                           Reserved_17_11:7 ; ///<
+    UINT32                                           LcGoToRecovery:1 ; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                  LcOtherSideSupportsGen2:1 ; ///<
+    UINT32                                           Reserved_28_25:4 ; ///<
+    UINT32                              LcMultUpstreamAutoSpdChngEn:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex548_STRUCT;
+
+// **** DxF0xE4_xA5 Register Definition ****
+// Address
+#define DxF0xE4_xA5_ADDRESS                                     0xa5
+
+// Type
+#define DxF0xE4_xA5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA5_LcCurrentState_OFFSET                       0
+#define DxF0xE4_xA5_LcCurrentState_WIDTH                        6
+#define DxF0xE4_xA5_LcCurrentState_MASK                         0x3f
+#define DxF0xE4_xA5_Reserved_7_6_OFFSET                         6
+#define DxF0xE4_xA5_Reserved_7_6_WIDTH                          2
+#define DxF0xE4_xA5_Reserved_7_6_MASK                           0xc0
+#define DxF0xE4_xA5_LcPrevState1_OFFSET                         8
+#define DxF0xE4_xA5_LcPrevState1_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState1_MASK                           0x3f00
+#define DxF0xE4_xA5_Reserved_15_14_OFFSET                       14
+#define DxF0xE4_xA5_Reserved_15_14_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_15_14_MASK                         0xc000
+#define DxF0xE4_xA5_LcPrevState2_OFFSET                         16
+#define DxF0xE4_xA5_LcPrevState2_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState2_MASK                           0x3f0000
+#define DxF0xE4_xA5_Reserved_23_22_OFFSET                       22
+#define DxF0xE4_xA5_Reserved_23_22_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_23_22_MASK                         0xc00000
+#define DxF0xE4_xA5_LcPrevState3_OFFSET                         24
+#define DxF0xE4_xA5_LcPrevState3_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState3_MASK                           0x3f000000
+#define DxF0xE4_xA5_Reserved_31_30_OFFSET                       30
+#define DxF0xE4_xA5_Reserved_31_30_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_31_30_MASK                         0xc0000000
+
+/// DxF0xE4_xA5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LcCurrentState:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                             LcPrevState1:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                             LcPrevState2:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                             LcPrevState3:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA5_STRUCT;
+
+// **** DxF0xE4_xB1 Register Definition ****
+// Address
+#define DxF0xE4_xB1_ADDRESS                                     0xb1
+
+// Type
+#define DxF0xE4_xB1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB1_Reserved_18_0_OFFSET                        0
+#define DxF0xE4_xB1_Reserved_18_0_WIDTH                         19
+#define DxF0xE4_xB1_Reserved_18_0_MASK                          0x7ffff
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET                  19
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH                   1
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK                    0x80000
+#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET                    20
+#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH                     1
+#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK                      0x100000
+#define DxF0xE4_xB1_Reserved_31_21_OFFSET                       21
+#define DxF0xE4_xB1_Reserved_31_21_WIDTH                        11
+#define DxF0xE4_xB1_Reserved_31_21_MASK                         0xffe00000
+
+/// DxF0xE4_xB1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_18_0:19; ///<
+    UINT32                                      LcDeassertRxEnInL0s:1 ; ///<
+    UINT32                                        LcBlockElIdleinL0:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB1_STRUCT;
+
+// **** DxF0xE4_xC0 Register Definition ****
+// Address
+#define DxF0xE4_xC0_ADDRESS                                     0xc0
+
+// Type
+#define DxF0xE4_xC0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xC0_Reserved_12_0_OFFSET                        0
+#define DxF0xE4_xC0_Reserved_12_0_WIDTH                         13
+#define DxF0xE4_xC0_Reserved_12_0_MASK                          0x1fff
+#define DxF0xE4_xC0_StrapForceCompliance_OFFSET                 13
+#define DxF0xE4_xC0_StrapForceCompliance_WIDTH                  1
+#define DxF0xE4_xC0_StrapForceCompliance_MASK                   0x2000
+#define DxF0xE4_xC0_Reserved_14_14_OFFSET                       14
+#define DxF0xE4_xC0_Reserved_14_14_WIDTH                        1
+#define DxF0xE4_xC0_Reserved_14_14_MASK                         0x4000
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET       15
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH        1
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK         0x8000
+#define DxF0xE4_xC0_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_xC0_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_xC0_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_xC0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_12_0:13; ///<
+    UINT32                                     StrapForceCompliance:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                           StrapAutoRcSpeedNegotiationDis:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xC0_STRUCT;
+
+
+
+// **** GMMx4D0 Register Definition ****
+// Address
+#define GMMx4D0_ADDRESS                                         0x4d0
+
+// Type
+#define GMMx4D0_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx4D0_DispclkDccgGateDisable_OFFSET                   0
+#define GMMx4D0_DispclkDccgGateDisable_WIDTH                    1
+#define GMMx4D0_DispclkDccgGateDisable_MASK                     0x1
+#define GMMx4D0_DispclkRDccgGateDisable_OFFSET                  1
+#define GMMx4D0_DispclkRDccgGateDisable_WIDTH                   1
+#define GMMx4D0_DispclkRDccgGateDisable_MASK                    0x2
+#define GMMx4D0_SclkGateDisable_OFFSET                          2
+#define GMMx4D0_SclkGateDisable_WIDTH                           1
+#define GMMx4D0_SclkGateDisable_MASK                            0x4
+#define GMMx4D0_Reserved_7_3_OFFSET                             3
+#define GMMx4D0_Reserved_7_3_WIDTH                              5
+#define GMMx4D0_Reserved_7_3_MASK                               0xf8
+#define GMMx4D0_SymclkaGateDisable_OFFSET                       8
+#define GMMx4D0_SymclkaGateDisable_WIDTH                        1
+#define GMMx4D0_SymclkaGateDisable_MASK                         0x100
+#define GMMx4D0_SymclkbGateDisable_OFFSET                       9
+#define GMMx4D0_SymclkbGateDisable_WIDTH                        1
+#define GMMx4D0_SymclkbGateDisable_MASK                         0x200
+#define GMMx4D0_Reserved_31_10_OFFSET                           10
+#define GMMx4D0_Reserved_31_10_WIDTH                            22
+#define GMMx4D0_Reserved_31_10_MASK                             0xfffffc00
+
+/// GMMx4D0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                   DispclkDccgGateDisable:1 ; ///<
+    UINT32                                  DispclkRDccgGateDisable:1 ; ///<
+    UINT32                                          SclkGateDisable:1 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                       SymclkaGateDisable:1 ; ///<
+    UINT32                                       SymclkbGateDisable:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx4D0_STRUCT;
+
+// **** GMMx770 Register Definition ****
+// Address
+#define GMMx770_ADDRESS                                         0x770
+
+// Type
+#define GMMx770_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx770_VoltageChangeReq_OFFSET                         0
+#define GMMx770_VoltageChangeReq_WIDTH                          1
+#define GMMx770_VoltageChangeReq_MASK                           0x1
+#define GMMx770_VoltageLevel_OFFSET                             1
+#define GMMx770_VoltageLevel_WIDTH                              2
+#define GMMx770_VoltageLevel_MASK                               0x6
+#define GMMx770_VoltageChangeEn_OFFSET                          3
+#define GMMx770_VoltageChangeEn_WIDTH                           1
+#define GMMx770_VoltageChangeEn_MASK                            0x8
+#define GMMx770_VoltageForceEn_OFFSET                           4
+#define GMMx770_VoltageForceEn_WIDTH                            1
+#define GMMx770_VoltageForceEn_MASK                             0x10
+#define GMMx770_Reserved_31_5_OFFSET                            5
+#define GMMx770_Reserved_31_5_WIDTH                             27
+#define GMMx770_Reserved_31_5_MASK                              0xffffffe0
+
+/// GMMx770
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             VoltageLevel:2 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx770_STRUCT;
+
+// **** GMMx774 Register Definition ****
+// Address
+#define GMMx774_ADDRESS                                         0x774
+
+// Type
+#define GMMx774_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx774_VoltageChangeAck_OFFSET                         0
+#define GMMx774_VoltageChangeAck_WIDTH                          1
+#define GMMx774_VoltageChangeAck_MASK                           0x1
+#define GMMx774_CurrentVoltageLevel_OFFSET                      1
+#define GMMx774_CurrentVoltageLevel_WIDTH                       2
+#define GMMx774_CurrentVoltageLevel_MASK                        0x6
+#define GMMx774_Reserved_31_3_OFFSET                            3
+#define GMMx774_Reserved_31_3_WIDTH                             29
+#define GMMx774_Reserved_31_3_MASK                              0xfffffff8
+
+/// GMMx774
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:2 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx774_STRUCT;
+
+// **** GMMx15C0 Register Definition ****
+// Address
+#define GMMx15C0_ADDRESS                                        0x15c0
+
+// Type
+#define GMMx15C0_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx15C0_OnDly_OFFSET                                   0
+#define GMMx15C0_OnDly_WIDTH                                    6
+#define GMMx15C0_OnDly_MASK                                     0x3f
+#define GMMx15C0_OffDly_OFFSET                                  6
+#define GMMx15C0_OffDly_WIDTH                                   6
+#define GMMx15C0_OffDly_MASK                                    0xfc0
+#define GMMx15C0_RdyDly_OFFSET                                  12
+#define GMMx15C0_RdyDly_WIDTH                                   6
+#define GMMx15C0_RdyDly_MASK                                    0x3f000
+#define GMMx15C0_Enable_OFFSET                                  18
+#define GMMx15C0_Enable_WIDTH                                   1
+#define GMMx15C0_Enable_MASK                                    0x40000
+#define GMMx15C0_Reserved_31_19_OFFSET                          19
+#define GMMx15C0_Reserved_31_19_WIDTH                           13
+#define GMMx15C0_Reserved_31_19_MASK                            0xfff80000
+
+/// GMMx15C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    OnDly:6 ; ///<
+    UINT32                                                   OffDly:6 ; ///<
+    UINT32                                                   RdyDly:6 ; ///<
+    UINT32                                                   Enable:1 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx15C0_STRUCT;
+
+
+
+
+
+// **** GMMx2024 Register Definition ****
+// Address
+#define GMMx2024_ADDRESS                                        0x2024
+
+// Type
+#define GMMx2024_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2024_Base_OFFSET                                    0
+#define GMMx2024_Base_WIDTH                                     16
+#define GMMx2024_Base_MASK                                      0xffff
+#define GMMx2024_Top_OFFSET                                     16
+#define GMMx2024_Top_WIDTH                                      16
+#define GMMx2024_Top_MASK                                       0xffff0000
+
+/// GMMx2024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Base:16; ///<
+    UINT32                                                      Top:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2024_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// **** GMMx2814 Register Definition ****
+// Address
+#define GMMx2814_ADDRESS                                        0x2814
+
+// Type
+#define GMMx2814_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2814_WriteClks_OFFSET                               0
+#define GMMx2814_WriteClks_WIDTH                                9
+#define GMMx2814_WriteClks_MASK                                 0x1ff
+#define GMMx2814_UvdHarshPriority_OFFSET                        9
+#define GMMx2814_UvdHarshPriority_WIDTH                         1
+#define GMMx2814_UvdHarshPriority_MASK                          0x200
+#define GMMx2814_Reserved_31_10_OFFSET                          10
+#define GMMx2814_Reserved_31_10_WIDTH                           22
+#define GMMx2814_Reserved_31_10_MASK                            0xfffffc00
+
+/// GMMx2814
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WriteClks:9 ; ///<
+    UINT32                                         UvdHarshPriority:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2814_STRUCT;
+
+// **** GMMx281C Register Definition ****
+// Address
+#define GMMx281C_ADDRESS                                        0x281c
+
+// Type
+#define GMMx281C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx281C_CSEnable_OFFSET                                0
+#define GMMx281C_CSEnable_WIDTH                                 1
+#define GMMx281C_CSEnable_MASK                                  0x1
+#define GMMx281C_Reserved_4_1_OFFSET                            1
+#define GMMx281C_Reserved_4_1_WIDTH                             4
+#define GMMx281C_Reserved_4_1_MASK                              0x1e
+#define GMMx281C_BaseAddr_21_13__OFFSET                         5
+#define GMMx281C_BaseAddr_21_13__WIDTH                          9
+#define GMMx281C_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx281C_Reserved_18_14_OFFSET                          14
+#define GMMx281C_Reserved_18_14_WIDTH                           5
+#define GMMx281C_Reserved_18_14_MASK                            0x7c000
+#define GMMx281C_BaseAddr_36_27__OFFSET                         19
+#define GMMx281C_BaseAddr_36_27__WIDTH                          10
+#define GMMx281C_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx281C_Reserved_31_29_OFFSET                          29
+#define GMMx281C_Reserved_31_29_WIDTH                           3
+#define GMMx281C_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx281C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx281C_STRUCT;
+
+// **** GMMx2820 Register Definition ****
+// Address
+#define GMMx2820_ADDRESS                                        0x2820
+
+// Type
+#define GMMx2820_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2820_CSEnable_OFFSET                                0
+#define GMMx2820_CSEnable_WIDTH                                 1
+#define GMMx2820_CSEnable_MASK                                  0x1
+#define GMMx2820_Reserved_4_1_OFFSET                            1
+#define GMMx2820_Reserved_4_1_WIDTH                             4
+#define GMMx2820_Reserved_4_1_MASK                              0x1e
+#define GMMx2820_BaseAddr_21_13__OFFSET                         5
+#define GMMx2820_BaseAddr_21_13__WIDTH                          9
+#define GMMx2820_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2820_Reserved_18_14_OFFSET                          14
+#define GMMx2820_Reserved_18_14_WIDTH                           5
+#define GMMx2820_Reserved_18_14_MASK                            0x7c000
+#define GMMx2820_BaseAddr_36_27__OFFSET                         19
+#define GMMx2820_BaseAddr_36_27__WIDTH                          10
+#define GMMx2820_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2820_Reserved_31_29_OFFSET                          29
+#define GMMx2820_Reserved_31_29_WIDTH                           3
+#define GMMx2820_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2820
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2820_STRUCT;
+
+// **** GMMx2824 Register Definition ****
+// Address
+#define GMMx2824_ADDRESS                                        0x2824
+
+// Type
+#define GMMx2824_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2824_CSEnable_OFFSET                                0
+#define GMMx2824_CSEnable_WIDTH                                 1
+#define GMMx2824_CSEnable_MASK                                  0x1
+#define GMMx2824_Reserved_4_1_OFFSET                            1
+#define GMMx2824_Reserved_4_1_WIDTH                             4
+#define GMMx2824_Reserved_4_1_MASK                              0x1e
+#define GMMx2824_BaseAddr_21_13__OFFSET                         5
+#define GMMx2824_BaseAddr_21_13__WIDTH                          9
+#define GMMx2824_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2824_Reserved_18_14_OFFSET                          14
+#define GMMx2824_Reserved_18_14_WIDTH                           5
+#define GMMx2824_Reserved_18_14_MASK                            0x7c000
+#define GMMx2824_BaseAddr_36_27__OFFSET                         19
+#define GMMx2824_BaseAddr_36_27__WIDTH                          10
+#define GMMx2824_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2824_Reserved_31_29_OFFSET                          29
+#define GMMx2824_Reserved_31_29_WIDTH                           3
+#define GMMx2824_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2824
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2824_STRUCT;
+
+// **** GMMx2828 Register Definition ****
+// Address
+#define GMMx2828_ADDRESS                                        0x2828
+
+// Type
+#define GMMx2828_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2828_CSEnable_OFFSET                                0
+#define GMMx2828_CSEnable_WIDTH                                 1
+#define GMMx2828_CSEnable_MASK                                  0x1
+#define GMMx2828_Reserved_4_1_OFFSET                            1
+#define GMMx2828_Reserved_4_1_WIDTH                             4
+#define GMMx2828_Reserved_4_1_MASK                              0x1e
+#define GMMx2828_BaseAddr_21_13__OFFSET                         5
+#define GMMx2828_BaseAddr_21_13__WIDTH                          9
+#define GMMx2828_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2828_Reserved_18_14_OFFSET                          14
+#define GMMx2828_Reserved_18_14_WIDTH                           5
+#define GMMx2828_Reserved_18_14_MASK                            0x7c000
+#define GMMx2828_BaseAddr_36_27__OFFSET                         19
+#define GMMx2828_BaseAddr_36_27__WIDTH                          10
+#define GMMx2828_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2828_Reserved_31_29_OFFSET                          29
+#define GMMx2828_Reserved_31_29_WIDTH                           3
+#define GMMx2828_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2828
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2828_STRUCT;
+
+// **** GMMx282C Register Definition ****
+// Address
+#define GMMx282C_ADDRESS                                        0x282c
+
+// Type
+#define GMMx282C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx282C_CSEnable_OFFSET                                0
+#define GMMx282C_CSEnable_WIDTH                                 1
+#define GMMx282C_CSEnable_MASK                                  0x1
+#define GMMx282C_Reserved_4_1_OFFSET                            1
+#define GMMx282C_Reserved_4_1_WIDTH                             4
+#define GMMx282C_Reserved_4_1_MASK                              0x1e
+#define GMMx282C_BaseAddr_21_13__OFFSET                         5
+#define GMMx282C_BaseAddr_21_13__WIDTH                          9
+#define GMMx282C_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx282C_Reserved_18_14_OFFSET                          14
+#define GMMx282C_Reserved_18_14_WIDTH                           5
+#define GMMx282C_Reserved_18_14_MASK                            0x7c000
+#define GMMx282C_BaseAddr_36_27__OFFSET                         19
+#define GMMx282C_BaseAddr_36_27__WIDTH                          10
+#define GMMx282C_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx282C_Reserved_31_29_OFFSET                          29
+#define GMMx282C_Reserved_31_29_WIDTH                           3
+#define GMMx282C_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx282C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx282C_STRUCT;
+
+// **** GMMx2830 Register Definition ****
+// Address
+#define GMMx2830_ADDRESS                                        0x2830
+
+// Type
+#define GMMx2830_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2830_CSEnable_OFFSET                                0
+#define GMMx2830_CSEnable_WIDTH                                 1
+#define GMMx2830_CSEnable_MASK                                  0x1
+#define GMMx2830_Reserved_4_1_OFFSET                            1
+#define GMMx2830_Reserved_4_1_WIDTH                             4
+#define GMMx2830_Reserved_4_1_MASK                              0x1e
+#define GMMx2830_BaseAddr_21_13__OFFSET                         5
+#define GMMx2830_BaseAddr_21_13__WIDTH                          9
+#define GMMx2830_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2830_Reserved_18_14_OFFSET                          14
+#define GMMx2830_Reserved_18_14_WIDTH                           5
+#define GMMx2830_Reserved_18_14_MASK                            0x7c000
+#define GMMx2830_BaseAddr_36_27__OFFSET                         19
+#define GMMx2830_BaseAddr_36_27__WIDTH                          10
+#define GMMx2830_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2830_Reserved_31_29_OFFSET                          29
+#define GMMx2830_Reserved_31_29_WIDTH                           3
+#define GMMx2830_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2830
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2830_STRUCT;
+
+// **** GMMx2834 Register Definition ****
+// Address
+#define GMMx2834_ADDRESS                                        0x2834
+
+// Type
+#define GMMx2834_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2834_CSEnable_OFFSET                                0
+#define GMMx2834_CSEnable_WIDTH                                 1
+#define GMMx2834_CSEnable_MASK                                  0x1
+#define GMMx2834_Reserved_4_1_OFFSET                            1
+#define GMMx2834_Reserved_4_1_WIDTH                             4
+#define GMMx2834_Reserved_4_1_MASK                              0x1e
+#define GMMx2834_BaseAddr_21_13__OFFSET                         5
+#define GMMx2834_BaseAddr_21_13__WIDTH                          9
+#define GMMx2834_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2834_Reserved_18_14_OFFSET                          14
+#define GMMx2834_Reserved_18_14_WIDTH                           5
+#define GMMx2834_Reserved_18_14_MASK                            0x7c000
+#define GMMx2834_BaseAddr_36_27__OFFSET                         19
+#define GMMx2834_BaseAddr_36_27__WIDTH                          10
+#define GMMx2834_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2834_Reserved_31_29_OFFSET                          29
+#define GMMx2834_Reserved_31_29_WIDTH                           3
+#define GMMx2834_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2834
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2834_STRUCT;
+
+// **** GMMx2838 Register Definition ****
+// Address
+#define GMMx2838_ADDRESS                                        0x2838
+
+// Type
+#define GMMx2838_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2838_CSEnable_OFFSET                                0
+#define GMMx2838_CSEnable_WIDTH                                 1
+#define GMMx2838_CSEnable_MASK                                  0x1
+#define GMMx2838_Reserved_4_1_OFFSET                            1
+#define GMMx2838_Reserved_4_1_WIDTH                             4
+#define GMMx2838_Reserved_4_1_MASK                              0x1e
+#define GMMx2838_BaseAddr_21_13__OFFSET                         5
+#define GMMx2838_BaseAddr_21_13__WIDTH                          9
+#define GMMx2838_BaseAddr_21_13__MASK                           0x3fe0
+#define GMMx2838_Reserved_18_14_OFFSET                          14
+#define GMMx2838_Reserved_18_14_WIDTH                           5
+#define GMMx2838_Reserved_18_14_MASK                            0x7c000
+#define GMMx2838_BaseAddr_36_27__OFFSET                         19
+#define GMMx2838_BaseAddr_36_27__WIDTH                          10
+#define GMMx2838_BaseAddr_36_27__MASK                           0x1ff80000
+#define GMMx2838_Reserved_31_29_OFFSET                          29
+#define GMMx2838_Reserved_31_29_WIDTH                           3
+#define GMMx2838_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2838
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_4_1:4 ; ///<
+    UINT32                                          BaseAddr_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          BaseAddr_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2838_STRUCT;
+
+// **** GMMx283C Register Definition ****
+// Address
+#define GMMx283C_ADDRESS                                        0x283c
+
+// Type
+#define GMMx283C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx283C_Reserved_4_0_OFFSET                            0
+#define GMMx283C_Reserved_4_0_WIDTH                             5
+#define GMMx283C_Reserved_4_0_MASK                              0x1f
+#define GMMx283C_AddrMask_21_13__OFFSET                         5
+#define GMMx283C_AddrMask_21_13__WIDTH                          9
+#define GMMx283C_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx283C_Reserved_18_14_OFFSET                          14
+#define GMMx283C_Reserved_18_14_WIDTH                           5
+#define GMMx283C_Reserved_18_14_MASK                            0x7c000
+#define GMMx283C_AddrMask_36_27__OFFSET                         19
+#define GMMx283C_AddrMask_36_27__WIDTH                          10
+#define GMMx283C_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx283C_Reserved_31_29_OFFSET                          29
+#define GMMx283C_Reserved_31_29_WIDTH                           3
+#define GMMx283C_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx283C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx283C_STRUCT;
+
+// **** GMMx2840 Register Definition ****
+// Address
+#define GMMx2840_ADDRESS                                        0x2840
+
+// Type
+#define GMMx2840_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2840_Reserved_4_0_OFFSET                            0
+#define GMMx2840_Reserved_4_0_WIDTH                             5
+#define GMMx2840_Reserved_4_0_MASK                              0x1f
+#define GMMx2840_AddrMask_21_13__OFFSET                         5
+#define GMMx2840_AddrMask_21_13__WIDTH                          9
+#define GMMx2840_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx2840_Reserved_18_14_OFFSET                          14
+#define GMMx2840_Reserved_18_14_WIDTH                           5
+#define GMMx2840_Reserved_18_14_MASK                            0x7c000
+#define GMMx2840_AddrMask_36_27__OFFSET                         19
+#define GMMx2840_AddrMask_36_27__WIDTH                          10
+#define GMMx2840_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx2840_Reserved_31_29_OFFSET                          29
+#define GMMx2840_Reserved_31_29_WIDTH                           3
+#define GMMx2840_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2840
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2840_STRUCT;
+
+// **** GMMx2844 Register Definition ****
+// Address
+#define GMMx2844_ADDRESS                                        0x2844
+
+// Type
+#define GMMx2844_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2844_Reserved_4_0_OFFSET                            0
+#define GMMx2844_Reserved_4_0_WIDTH                             5
+#define GMMx2844_Reserved_4_0_MASK                              0x1f
+#define GMMx2844_AddrMask_21_13__OFFSET                         5
+#define GMMx2844_AddrMask_21_13__WIDTH                          9
+#define GMMx2844_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx2844_Reserved_18_14_OFFSET                          14
+#define GMMx2844_Reserved_18_14_WIDTH                           5
+#define GMMx2844_Reserved_18_14_MASK                            0x7c000
+#define GMMx2844_AddrMask_36_27__OFFSET                         19
+#define GMMx2844_AddrMask_36_27__WIDTH                          10
+#define GMMx2844_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx2844_Reserved_31_29_OFFSET                          29
+#define GMMx2844_Reserved_31_29_WIDTH                           3
+#define GMMx2844_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2844
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2844_STRUCT;
+
+// **** GMMx2848 Register Definition ****
+// Address
+#define GMMx2848_ADDRESS                                        0x2848
+
+// Type
+#define GMMx2848_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2848_Reserved_4_0_OFFSET                            0
+#define GMMx2848_Reserved_4_0_WIDTH                             5
+#define GMMx2848_Reserved_4_0_MASK                              0x1f
+#define GMMx2848_AddrMask_21_13__OFFSET                         5
+#define GMMx2848_AddrMask_21_13__WIDTH                          9
+#define GMMx2848_AddrMask_21_13__MASK                           0x3fe0
+#define GMMx2848_Reserved_18_14_OFFSET                          14
+#define GMMx2848_Reserved_18_14_WIDTH                           5
+#define GMMx2848_Reserved_18_14_MASK                            0x7c000
+#define GMMx2848_AddrMask_36_27__OFFSET                         19
+#define GMMx2848_AddrMask_36_27__WIDTH                          10
+#define GMMx2848_AddrMask_36_27__MASK                           0x1ff80000
+#define GMMx2848_Reserved_31_29_OFFSET                          29
+#define GMMx2848_Reserved_31_29_WIDTH                           3
+#define GMMx2848_Reserved_31_29_MASK                            0xe0000000
+
+/// GMMx2848
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_13_:9 ; ///<
+    UINT32                                           Reserved_18_14:5 ; ///<
+    UINT32                                          AddrMask_36_27_:10; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2848_STRUCT;
+
+// **** GMMx284C Register Definition ****
+// Address
+#define GMMx284C_ADDRESS                                        0x284c
+
+// Type
+#define GMMx284C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx284C_Dimm0AddrMap_OFFSET                            0
+#define GMMx284C_Dimm0AddrMap_WIDTH                             4
+#define GMMx284C_Dimm0AddrMap_MASK                              0xf
+#define GMMx284C_Dimm1AddrMap_OFFSET                            4
+#define GMMx284C_Dimm1AddrMap_WIDTH                             4
+#define GMMx284C_Dimm1AddrMap_MASK                              0xf0
+#define GMMx284C_Reserved_15_8_OFFSET                           8
+#define GMMx284C_Reserved_15_8_WIDTH                            8
+#define GMMx284C_Reserved_15_8_MASK                             0xff00
+#define GMMx284C_BankSwizzleMode_OFFSET                         16
+#define GMMx284C_BankSwizzleMode_WIDTH                          1
+#define GMMx284C_BankSwizzleMode_MASK                           0x10000
+#define GMMx284C_Ddr3Mode_OFFSET                                17
+#define GMMx284C_Ddr3Mode_WIDTH                                 1
+#define GMMx284C_Ddr3Mode_MASK                                  0x20000
+#define GMMx284C_BurstLength32_OFFSET                           18
+#define GMMx284C_BurstLength32_WIDTH                            1
+#define GMMx284C_BurstLength32_MASK                             0x40000
+#define GMMx284C_BankSwap_OFFSET                                19
+#define GMMx284C_BankSwap_WIDTH                                 1
+#define GMMx284C_BankSwap_MASK                                  0x80000
+#define GMMx284C_Reserved_31_20_OFFSET                          20
+#define GMMx284C_Reserved_31_20_WIDTH                           12
+#define GMMx284C_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx284C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Dimm0AddrMap:4 ; ///<
+    UINT32                                             Dimm1AddrMap:4 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                                 Ddr3Mode:1 ; ///<
+    UINT32                                            BurstLength32:1 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx284C_STRUCT;
+
+// **** GMMx2850 Register Definition ****
+// Address
+#define GMMx2850_ADDRESS                                        0x2850
+
+// Type
+#define GMMx2850_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2850_Dimm0AddrMap_OFFSET                            0
+#define GMMx2850_Dimm0AddrMap_WIDTH                             4
+#define GMMx2850_Dimm0AddrMap_MASK                              0xf
+#define GMMx2850_Dimm1AddrMap_OFFSET                            4
+#define GMMx2850_Dimm1AddrMap_WIDTH                             4
+#define GMMx2850_Dimm1AddrMap_MASK                              0xf0
+#define GMMx2850_Reserved_15_8_OFFSET                           8
+#define GMMx2850_Reserved_15_8_WIDTH                            8
+#define GMMx2850_Reserved_15_8_MASK                             0xff00
+#define GMMx2850_BankSwizzleMode_OFFSET                         16
+#define GMMx2850_BankSwizzleMode_WIDTH                          1
+#define GMMx2850_BankSwizzleMode_MASK                           0x10000
+#define GMMx2850_Ddr3Mode_OFFSET                                17
+#define GMMx2850_Ddr3Mode_WIDTH                                 1
+#define GMMx2850_Ddr3Mode_MASK                                  0x20000
+#define GMMx2850_BurstLength32_OFFSET                           18
+#define GMMx2850_BurstLength32_WIDTH                            1
+#define GMMx2850_BurstLength32_MASK                             0x40000
+#define GMMx2850_BankSwap_OFFSET                                19
+#define GMMx2850_BankSwap_WIDTH                                 1
+#define GMMx2850_BankSwap_MASK                                  0x80000
+#define GMMx2850_Reserved_31_20_OFFSET                          20
+#define GMMx2850_Reserved_31_20_WIDTH                           12
+#define GMMx2850_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2850
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Dimm0AddrMap:4 ; ///<
+    UINT32                                             Dimm1AddrMap:4 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                                 Ddr3Mode:1 ; ///<
+    UINT32                                            BurstLength32:1 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2850_STRUCT;
+
+// **** GMMx2854 Register Definition ****
+// Address
+#define GMMx2854_ADDRESS                                        0x2854
+
+// Type
+#define GMMx2854_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2854_DctSelHiRngEn_OFFSET                           0
+#define GMMx2854_DctSelHiRngEn_WIDTH                            1
+#define GMMx2854_DctSelHiRngEn_MASK                             0x1
+#define GMMx2854_DctSelHi_OFFSET                                1
+#define GMMx2854_DctSelHi_WIDTH                                 1
+#define GMMx2854_DctSelHi_MASK                                  0x2
+#define GMMx2854_DctSelIntLvEn_OFFSET                           2
+#define GMMx2854_DctSelIntLvEn_WIDTH                            1
+#define GMMx2854_DctSelIntLvEn_MASK                             0x4
+#define GMMx2854_Reserved_5_3_OFFSET                            3
+#define GMMx2854_Reserved_5_3_WIDTH                             3
+#define GMMx2854_Reserved_5_3_MASK                              0x38
+#define GMMx2854_DctSelIntLvAddr_1_0__OFFSET                    6
+#define GMMx2854_DctSelIntLvAddr_1_0__WIDTH                     2
+#define GMMx2854_DctSelIntLvAddr_1_0__MASK                      0xc0
+#define GMMx2854_Reserved_10_8_OFFSET                           8
+#define GMMx2854_Reserved_10_8_WIDTH                            3
+#define GMMx2854_Reserved_10_8_MASK                             0x700
+#define GMMx2854_DctSelBaseAddr_39_27__OFFSET                   11
+#define GMMx2854_DctSelBaseAddr_39_27__WIDTH                    13
+#define GMMx2854_DctSelBaseAddr_39_27__MASK                     0xfff800
+#define GMMx2854_Reserved_31_24_OFFSET                          24
+#define GMMx2854_Reserved_31_24_WIDTH                           8
+#define GMMx2854_Reserved_31_24_MASK                            0xff000000
+
+/// GMMx2854
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DctSelHiRngEn:1 ; ///<
+    UINT32                                                 DctSelHi:1 ; ///<
+    UINT32                                            DctSelIntLvEn:1 ; ///<
+    UINT32                                             Reserved_5_3:3 ; ///<
+    UINT32                                     DctSelIntLvAddr_1_0_:2 ; ///<
+    UINT32                                            Reserved_10_8:3 ; ///<
+    UINT32                                    DctSelBaseAddr_39_27_:13; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2854_STRUCT;
+
+// **** GMMx2858 Register Definition ****
+// Address
+#define GMMx2858_ADDRESS                                        0x2858
+
+// Type
+#define GMMx2858_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2858_Reserved_8_0_OFFSET                            0
+#define GMMx2858_Reserved_8_0_WIDTH                             9
+#define GMMx2858_Reserved_8_0_MASK                              0x1ff
+#define GMMx2858_DctSelIntLvAddr_2__OFFSET                      9
+#define GMMx2858_DctSelIntLvAddr_2__WIDTH                       1
+#define GMMx2858_DctSelIntLvAddr_2__MASK                        0x200
+#define GMMx2858_DctSelBaseOffset_39_26__OFFSET                 10
+#define GMMx2858_DctSelBaseOffset_39_26__WIDTH                  14
+#define GMMx2858_DctSelBaseOffset_39_26__MASK                   0xfffc00
+#define GMMx2858_Reserved_31_24_OFFSET                          24
+#define GMMx2858_Reserved_31_24_WIDTH                           8
+#define GMMx2858_Reserved_31_24_MASK                            0xff000000
+
+/// GMMx2858
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
+    UINT32                                  DctSelBaseOffset_39_26_:14; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2858_STRUCT;
+
+// **** GMMx285C Register Definition ****
+// Address
+#define GMMx285C_ADDRESS                                        0x285c
+
+// Type
+#define GMMx285C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx285C_DramHoleValid_OFFSET                           0
+#define GMMx285C_DramHoleValid_WIDTH                            1
+#define GMMx285C_DramHoleValid_MASK                             0x1
+#define GMMx285C_Reserved_6_1_OFFSET                            1
+#define GMMx285C_Reserved_6_1_WIDTH                             6
+#define GMMx285C_Reserved_6_1_MASK                              0x7e
+#define GMMx285C_DramHoleOffset_31_23__OFFSET                   7
+#define GMMx285C_DramHoleOffset_31_23__WIDTH                    9
+#define GMMx285C_DramHoleOffset_31_23__MASK                     0xff80
+#define GMMx285C_Reserved_23_16_OFFSET                          16
+#define GMMx285C_Reserved_23_16_WIDTH                           8
+#define GMMx285C_Reserved_23_16_MASK                            0xff0000
+#define GMMx285C_DramHoleBase_31_24__OFFSET                     24
+#define GMMx285C_DramHoleBase_31_24__WIDTH                      8
+#define GMMx285C_DramHoleBase_31_24__MASK                       0xff000000
+
+/// GMMx285C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DramHoleValid:1 ; ///<
+    UINT32                                             Reserved_6_1:6 ; ///<
+    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
+    UINT32                                           Reserved_23_16:8 ; ///<
+    UINT32                                      DramHoleBase_31_24_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx285C_STRUCT;
+
+
+
+
+
+// **** GMMx2870 Register Definition ****
+// Address
+#define GMMx2870_ADDRESS                                        0x2870
+
+// Type
+#define GMMx2870_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2870_Base_OFFSET                                    0
+#define GMMx2870_Base_WIDTH                                     20
+#define GMMx2870_Base_MASK                                      0xfffff
+#define GMMx2870_Reserved_31_20_OFFSET                          20
+#define GMMx2870_Reserved_31_20_WIDTH                           12
+#define GMMx2870_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2870
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Base:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2870_STRUCT;
+
+// **** GMMx2874 Register Definition ****
+// Address
+#define GMMx2874_ADDRESS                                        0x2874
+
+// Type
+#define GMMx2874_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2874_Base_OFFSET                                    0
+#define GMMx2874_Base_WIDTH                                     20
+#define GMMx2874_Base_MASK                                      0xfffff
+#define GMMx2874_Reserved_31_20_OFFSET                          20
+#define GMMx2874_Reserved_31_20_WIDTH                           12
+#define GMMx2874_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2874
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Base:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2874_STRUCT;
+
+
+// **** GMMx287C Register Definition ****
+// Address
+#define GMMx287C_ADDRESS                                        0x287c
+
+// Type
+#define GMMx287C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx287C_Top_OFFSET                                     0
+#define GMMx287C_Top_WIDTH                                      20
+#define GMMx287C_Top_MASK                                       0xfffff
+#define GMMx287C_Reserved_31_20_OFFSET                          20
+#define GMMx287C_Reserved_31_20_WIDTH                           12
+#define GMMx287C_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx287C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Top:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx287C_STRUCT;
+
+
+
+// **** GMMx2888 Register Definition ****
+// Address
+#define GMMx2888_ADDRESS                                        0x2888
+
+// Type
+#define GMMx2888_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2888_Top_OFFSET                                     0
+#define GMMx2888_Top_WIDTH                                      20
+#define GMMx2888_Top_MASK                                       0xfffff
+#define GMMx2888_Reserved_31_20_OFFSET                          20
+#define GMMx2888_Reserved_31_20_WIDTH                           12
+#define GMMx2888_Reserved_31_20_MASK                            0xfff00000
+
+/// GMMx2888
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Top:20; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2888_STRUCT;
+
+
+
+
+
+
+// **** GMMx28D8 Register Definition ****
+// Address
+#define GMMx28D8_ADDRESS                                        0x28d8
+
+// Type
+#define GMMx28D8_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx28D8_ActRd_OFFSET                                   0
+#define GMMx28D8_ActRd_WIDTH                                    8
+#define GMMx28D8_ActRd_MASK                                     0xff
+#define GMMx28D8_ActWr_OFFSET                                   8
+#define GMMx28D8_ActWr_WIDTH                                    8
+#define GMMx28D8_ActWr_MASK                                     0xff00
+#define GMMx28D8_RasMActRd_OFFSET                               16
+#define GMMx28D8_RasMActRd_WIDTH                                8
+#define GMMx28D8_RasMActRd_MASK                                 0xff0000
+#define GMMx28D8_RasMActWr_OFFSET                               24
+#define GMMx28D8_RasMActWr_WIDTH                                8
+#define GMMx28D8_RasMActWr_MASK                                 0xff000000
+
+/// GMMx28D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    ActRd:8 ; ///<
+    UINT32                                                    ActWr:8 ; ///<
+    UINT32                                                RasMActRd:8 ; ///<
+    UINT32                                                RasMActWr:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx28D8_STRUCT;
+
+
+
+
+
+
+
+// **** GMMx2C04 Register Definition ****
+// Address
+#define GMMx2C04_ADDRESS                                        0x2c04
+
+// Type
+#define GMMx2C04_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2C04_NonsurfBase_OFFSET                             0
+#define GMMx2C04_NonsurfBase_WIDTH                              28
+#define GMMx2C04_NonsurfBase_MASK                               0xfffffff
+#define GMMx2C04_Reserved_31_28_OFFSET                          28
+#define GMMx2C04_Reserved_31_28_WIDTH                           4
+#define GMMx2C04_Reserved_31_28_MASK                            0xf0000000
+
+/// GMMx2C04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              NonsurfBase:28; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2C04_STRUCT;
+
+// **** GMMx5428 Register Definition ****
+// Address
+#define GMMx5428_ADDRESS                                        0x5428
+
+// Type
+#define GMMx5428_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5428_ConfigMemsize_OFFSET                           0
+#define GMMx5428_ConfigMemsize_WIDTH                            32
+#define GMMx5428_ConfigMemsize_MASK                             0xffffffff
+
+/// GMMx5428
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ConfigMemsize:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5428_STRUCT;
+
+// **** GMMx5490 Register Definition ****
+// Address
+#define GMMx5490_ADDRESS                                        0x5490
+
+// Type
+#define GMMx5490_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5490_FbReadEn_OFFSET                                0
+#define GMMx5490_FbReadEn_WIDTH                                 1
+#define GMMx5490_FbReadEn_MASK                                  0x1
+#define GMMx5490_FbWriteEn_OFFSET                               1
+#define GMMx5490_FbWriteEn_WIDTH                                1
+#define GMMx5490_FbWriteEn_MASK                                 0x2
+#define GMMx5490_Reserved_31_2_OFFSET                           2
+#define GMMx5490_Reserved_31_2_WIDTH                            30
+#define GMMx5490_Reserved_31_2_MASK                             0xfffffffc
+
+/// GMMx5490
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 FbReadEn:1 ; ///<
+    UINT32                                                FbWriteEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5490_STRUCT;
+
+
+/// SMUx73
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DisLclkGating:1 ; ///<
+    UINT32                                            DisSclkGating:1 ; ///<
+    UINT32                                            Reserved_15_2:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} SMUx73_STRUCT;
+
+// **** MSRC001_001A Register Definition ****
+// Address
+#define MSRC001_001A_ADDRESS                                    0xc001001a
+
+// Type
+#define MSRC001_001A_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_001A_RAZ_22_0_OFFSET                            0
+#define MSRC001_001A_RAZ_22_0_WIDTH                             23
+#define MSRC001_001A_RAZ_22_0_MASK                              0x7fffff
+#define MSRC001_001A_TOM_39_23__OFFSET                          23
+#define MSRC001_001A_TOM_39_23__WIDTH                           17
+#define MSRC001_001A_TOM_39_23__MASK                            0xffff800000
+#define MSRC001_001A_MBZ_47_40_OFFSET                           40
+#define MSRC001_001A_MBZ_47_40_WIDTH                            8
+#define MSRC001_001A_MBZ_47_40_MASK                             0xff0000000000
+#define MSRC001_001A_RAZ_63_48_OFFSET                           48
+#define MSRC001_001A_RAZ_63_48_WIDTH                            16
+#define MSRC001_001A_RAZ_63_48_MASK                             0xffff000000000000
+
+/// MSRC001_001A
+typedef union {
+  struct {                                                              ///<
+    UINT64                                                 RAZ_22_0:23; ///<
+    UINT64                                               TOM_39_23_:17; ///<
+    UINT64                                                MBZ_47_40:8 ; ///<
+    UINT64                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_001A_STRUCT;
+
+
+
+
+
+
+
+// **** D0F0xE4_WRAP_8013 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8013_ADDRESS                               0x8013
+
+// Field Data
+#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET                 0
+#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH                  1
+#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK                   0x1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET                   2
+#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK                     0x4
+#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET                   3
+#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK                     0x8
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET       4
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH        1
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK         0x10
+#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET                   5
+#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK                     0x20
+#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET                   7
+#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH                    1
+#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK                     0x80
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET           8
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH            1
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK             0x100
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET           9
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH            1
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK             0x200
+#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET                 10
+#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK                   0x400
+#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET                 11
+#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK                   0x800
+#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET                 12
+#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK                   0x1000
+#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET                 13
+#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH                  3
+#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK                   0xe000
+#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET                 16
+#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK                   0x10000
+#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET                 17
+#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH                  3
+#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK                   0xe0000
+#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET                 20
+#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH                  1
+#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK                   0x100000
+#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET                 21
+#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH                  11
+#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK                   0xffe00000
+
+/// D0F0xE4_WRAP_8013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MasterPciePllA:1 ; ///<
+    UINT32                                           MasterPciePllB:1 ; ///<
+    UINT32                                           MasterPciePllC:1 ; ///<
+    UINT32                                           MasterPciePllD:1 ; ///<
+    UINT32                                 ClkDividerResetOverrideA:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                     TxclkSelCoreOverride:1 ; ///<
+    UINT32                                     TxclkSelPifAOverride:1 ; ///<
+    UINT32                                           Reserved_10_10:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                           Reserved_16_16:1 ; ///<
+    UINT32                                           Reserved_19_17:3 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8013_STRUCT;
+
+// **** D0F0xE4_WRAP_8014 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8014_ADDRESS                               0x8014
+
+// Field Data
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET            0
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK              0x1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET            1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK              0x2
+#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET                   2
+#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK                     0x4
+#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET                   3
+#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK                     0x8
+#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET                   4
+#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK                     0x10
+#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET                   5
+#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK                     0x20
+#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET                   7
+#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK                     0x80
+#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET                   8
+#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK                     0x100
+#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET                   9
+#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH                    1
+#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK                     0x200
+#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET                 10
+#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK                   0x400
+#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET                 11
+#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK                   0x800
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET           12
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK             0x1000
+#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET                 13
+#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK                   0x2000
+#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET                 14
+#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK                   0x4000
+#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET                 15
+#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK                   0x8000
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET         16
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK           0x10000
+#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET                 17
+#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK                   0x20000
+#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET                 18
+#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK                   0x40000
+#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET                 19
+#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH                  1
+#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK                   0x80000
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET  20
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH   1
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK    0x100000
+#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET                 21
+#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH                  11
+#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK                   0xffe00000
+
+/// D0F0xE4_WRAP_8014
+typedef union {
+  struct {
+    UINT32                                      TxclkPermGateEnable:1 ; ///<
+    UINT32                                      TxclkPrbsGateEnable:1 ; ///<
+    UINT32                                      DdiGatePifA1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifB1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifC1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifD1xEnable:1 ; ///<
+    UINT32                                        DdiGateDigAEnable:1 ; ///<
+    UINT32                                        DdiGateDigBEnable:1 ; ///<
+    UINT32                                    DdiGatePifA2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifB2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifC2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifD2p5xEnable:1 ; ///<
+    UINT32                                     PcieGatePifA1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifB1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifC1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifD1xEnable:1 ; ///<
+    UINT32                                   PcieGatePifA2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifB2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifC2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifD2p5xEnable:1 ; ///<
+    UINT32                            TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8014_STRUCT;
+
+
+
+
+
+// **** GMMx6124 Register Definition ****
+// Address
+#define GMMx6124_ADDRESS                                        0x6124
+
+// **** GMMx6124 Register Definition ****
+// Address
+#define GMMx6124_ADDRESS                                        0x6124
+
+// Type
+#define GMMx6124_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx6124_DoutScratch_OFFSET                             0
+#define GMMx6124_DoutScratch_WIDTH                              32
+#define GMMx6124_DoutScratch_MASK                               0xffffffff
+
+
+
+
+
+
+
+
+// **** D0F0xE4_CORE_0020 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0020_ADDRESS                               0x20
+
+// Type
+#define D0F0xE4_CORE_0020_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0020_Reserved_1_0_OFFSET                   0
+#define D0F0xE4_CORE_0020_Reserved_1_0_WIDTH                    2
+#define D0F0xE4_CORE_0020_Reserved_1_0_MASK                     0x3
+#define D0F0xE4_CORE_0020_Reserved_31_12_OFFSET                 12
+#define D0F0xE4_CORE_0020_Reserved_31_12_WIDTH                  20
+#define D0F0xE4_CORE_0020_Reserved_31_12_MASK                   0xfffff000
+
+/// D0F0xE4_CORE_0020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                       :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                         :2 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                          :1 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                        :1 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0020_STRUCT;
+
+// **** D0F0xE4_CORE_0010 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0010_ADDRESS                               0x10
+
+// Type
+#define D0F0xE4_CORE_0010_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET                   0
+#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH                    1
+#define D0F0xE4_CORE_0010_HwInitWrLock_MASK                     0x1
+#define D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET                1
+#define D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH                 3
+#define D0F0xE4_CORE_0010_LcHotPlugDelSel_MASK                  0xe
+#define D0F0xE4_CORE_0010_Reserved_6_4_OFFSET                   4
+#define D0F0xE4_CORE_0010_Reserved_6_4_WIDTH                    3
+#define D0F0xE4_CORE_0010_Reserved_6_4_MASK                     0x70
+
+/// D0F0xE4_CORE_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                          LcHotPlugDelSel:3 ; ///<
+    UINT32                                             Reserved_6_4:3 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                            :1 ; ///<
+    UINT32                                      :3 ; ///<
+    UINT32                                           :3 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                      :1 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                  :1 ; ///<
+    UINT32                                     :1 ; ///<
+    UINT32                                        :1 ; ///<
+    UINT32                                     :1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                               :6 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                      :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0010_STRUCT;
+
+
+// **** D0F0x98_x0C Register Definition ****
+// Address
+#define D0F0x98_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x98_x0C_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x0C_GcmWrrLenA_OFFSET                           0
+#define D0F0x98_x0C_GcmWrrLenA_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenA_MASK                             0xff
+#define D0F0x98_x0C_GcmWrrLenB_OFFSET                           8
+#define D0F0x98_x0C_GcmWrrLenB_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenB_MASK                             0xff00
+#define D0F0x98_x0C_Reserved_29_16_OFFSET                       16
+#define D0F0x98_x0C_Reserved_29_16_WIDTH                        14
+#define D0F0x98_x0C_Reserved_29_16_MASK                         0x3fff0000
+#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET                    30
+#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH                     1
+#define D0F0x98_x0C_StrictSelWinnerEn_MASK                      0x40000000
+
+/// D0F0x98_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               GcmWrrLenA:8 ; ///<
+    UINT32                                               GcmWrrLenB:8 ; ///<
+    UINT32                                           Reserved_29_16:14; ///<
+    UINT32                                        StrictSelWinnerEn:1 ; ///<
+    UINT32                                             :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x0C_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// **** D0F0xE4_WRAP_8063 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8063_ADDRESS                               0x8063
+
+// Type
+#define D0F0xE4_WRAP_8063_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8063_Reserved_0_0_OFFSET                   0
+#define D0F0xE4_WRAP_8063_Reserved_0_0_WIDTH                    1
+#define D0F0xE4_WRAP_8063_Reserved_0_0_MASK                     0x1
+#define D0F0xE4_WRAP_8063_Reserved_25_25_OFFSET                 25
+#define D0F0xE4_WRAP_8063_Reserved_25_25_WIDTH                  1
+#define D0F0xE4_WRAP_8063_Reserved_25_25_MASK                   0x2000000
+#define D0F0xE4_WRAP_8063_Reserved_27_26_OFFSET                 26
+#define D0F0xE4_WRAP_8063_Reserved_27_26_WIDTH                  2
+#define D0F0xE4_WRAP_8063_Reserved_27_26_MASK                   0xc000000
+#define D0F0xE4_WRAP_8063_Reserved_31_28_OFFSET                 28
+#define D0F0xE4_WRAP_8063_Reserved_31_28_WIDTH                  4
+#define D0F0xE4_WRAP_8063_Reserved_31_28_MASK                   0xf0000000
+
+/// D0F0xE4_WRAP_8063
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    line331:1 ; ///<
+    UINT32    line332:1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :2 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    line338:1 ; ///<
+    UINT32    line339:1 ; ///<
+    UINT32    line340:1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :2 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :1 ; ///<
+    UINT32    :2 ; ///<
+    UINT32    :1 ; ///<
+    UINT32                                           Reserved_25_25:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8063_STRUCT;
+
+// **** D0F0xE4_WRAP_8015 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8015_ADDRESS                               0x8015
+
+// Type
+#define D0F0xE4_WRAP_8015_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8015_EnableD0StateReport_OFFSET            0
+#define D0F0xE4_WRAP_8015_EnableD0StateReport_WIDTH             1
+#define D0F0xE4_WRAP_8015_EnableD0StateReport_MASK              0x1
+#define D0F0xE4_WRAP_8015_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8015_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8015_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_OFFSET     2
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_WIDTH      1
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_MASK       0x4
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_OFFSET      3
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_WIDTH       1
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_MASK        0x8
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_OFFSET      4
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_WIDTH       2
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_MASK        0x30
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_OFFSET       6
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_WIDTH        2
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_MASK         0xc0
+#define D0F0xE4_WRAP_8015_Reserved_8_8_OFFSET                   8
+#define D0F0xE4_WRAP_8015_Reserved_8_8_WIDTH                    1
+#define D0F0xE4_WRAP_8015_Reserved_8_8_MASK                     0x100
+#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_OFFSET        9
+#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_WIDTH         1
+#define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_MASK          0x200
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_OFFSET       10
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_WIDTH        1
+#define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_MASK         0x400
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_OFFSET        11
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_WIDTH         1
+#define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_MASK          0x800
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_OFFSET        12
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_WIDTH         2
+#define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_MASK          0x3000
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_OFFSET         14
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_WIDTH          2
+#define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_MASK           0xc000
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET          16
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK            0x3f0000
+#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET           23
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK             0x800000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET          24
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK            0x3f000000
+#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET                 30
+#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK                   0x40000000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET           31
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK             0x80000000
+
+/// D0F0xE4_WRAP_8015
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      EnableD0StateReport:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                               SlowRefclkThroughTxclk2p5x:1 ; ///<
+    UINT32                                SlowRefclkEnableTxclk2p5x:1 ; ///<
+    UINT32                                SlowRefclkDivideTxclk2p5x:2 ; ///<
+    UINT32                                 SlowRefclkBurstTxclk2p5x:2 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                  SlowRefclkLcntGateForce:1 ; ///<
+    UINT32                                 SlowRefclkThroughTxclk1x:1 ; ///<
+    UINT32                                  SlowRefclkEnableTxclk1x:1 ; ///<
+    UINT32                                  SlowRefclkDivideTxclk1x:2 ; ///<
+    UINT32                                   SlowRefclkBurstTxclk1x:2 ; ///<
+    UINT32                                    RefclkRegsGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                     RefclkRegsGateEnable:1 ; ///<
+    UINT32                                    RefclkBphyGateLatency:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                     RefclkBphyGateEnable:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8015_STRUCT;
+
+// **** DxF0xE4_xB5 Register Definition ****
+// Address
+#define DxF0xE4_xB5_ADDRESS                                     0xb5
+
+// Type
+#define DxF0xE4_xB5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET                   0
+#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH                    1
+#define DxF0xE4_xB5_LcSelectDeemphasis_MASK                     0x1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET               1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH                2
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK                 0x6
+#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET                     3
+#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH                      1
+#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK                       0x8
+#define DxF0xE4_xB5_Reserved_31_23_OFFSET                       23
+#define DxF0xE4_xB5_Reserved_31_23_WIDTH                        9
+#define DxF0xE4_xB5_Reserved_31_23_MASK                         0xff800000
+
+/// DxF0xE4_xB5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       LcSelectDeemphasis:1 ; ///<
+    UINT32                                   LcSelectDeemphasisCntl:2 ; ///<
+    UINT32                                         LcRcvdDeemphasis:1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  line519:1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  line521:2 ; ///<
+    UINT32  line522:2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB5_STRUCT;
+
+
+// **** D0F0xE4_PHY_6006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6006_ADDRESS                                0x6006
+
+// Type
+#define D0F0xE4_PHY_6006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET                     0
+#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH                      8
+#define D0F0xE4_PHY_6006_TxMarginNom_MASK                       0xff
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET                   8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH                    8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK                     0xff00
+#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET                 16
+#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_WIDTH                  8
+#define D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK                   0xff0000
+#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET                 24
+#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_WIDTH                  8
+#define D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK                   0xff000000
+
+/// D0F0xE4_PHY_6006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              TxMarginNom:8 ; ///<
+    UINT32                                            DeemphGen1Nom:8 ; ///<
+    UINT32                                          Deemph35Gen2Nom:8 ; ///<
+    UINT32                                          Deemph60Gen2Nom:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6006_STRUCT;
+
+
+
+// **** D0F0x64_x1C Register Definition ****
+// Address
+#define D0F0x64_x1C_ADDRESS                                     0x1c
+
+// Type
+#define D0F0x64_x1C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1C_WriteDis_OFFSET                             0
+#define D0F0x64_x1C_WriteDis_WIDTH                              1
+#define D0F0x64_x1C_WriteDis_MASK                               0x1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET              1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH               1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK                0x2
+#define D0F0x64_x1C_F064BarEn_OFFSET                            2
+#define D0F0x64_x1C_F064BarEn_WIDTH                             1
+#define D0F0x64_x1C_F064BarEn_MASK                              0x4
+#define D0F0x64_x1C_MemApSize_OFFSET                            3
+#define D0F0x64_x1C_MemApSize_WIDTH                             3
+#define D0F0x64_x1C_MemApSize_MASK                              0x38
+#define D0F0x64_x1C_RegApSize_OFFSET                            6
+#define D0F0x64_x1C_RegApSize_WIDTH                             1
+#define D0F0x64_x1C_RegApSize_MASK                              0x40
+
+/// D0F0x64_x1C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 WriteDis:1 ; ///<
+    UINT32                                  F0NonlegacyDeviceTypeEn:1 ; ///<
+    UINT32                                                F064BarEn:1 ; ///<
+    UINT32                                                MemApSize:3 ; ///<
+    UINT32                                                RegApSize:1 ; ///<
+    UINT32  /*                                        DualfuncDisplayEn*/:1 ; ///<
+    UINT32  /*                                                  AudioEn*/:1 ; ///<
+    UINT32  /*                                                   MsiDis*/:1 ; ///<
+    UINT32  /*                               AudioNonlegacyDeviceTypeEn*/:1 ; ///<
+    UINT32  /*                                             Audio64BarEn*/:1 ; ///<
+    UINT32  /*                                                   VgaDis*/:1 ; ///<
+    UINT32  /*                                               FbAlwaysOn*/:1 ; ///<
+    UINT32  /*                                             FbCplTypeSel*/:2 ; ///<
+    UINT32  /*                                                 IoBarDis*/:1 ; ///<
+    UINT32  /*                                                     F0En*/:1 ; ///<
+    UINT32  /*                                                  F0BarEn*/:1 ; ///<
+    UINT32  /*                                                  F1BarEn*/:1 ; ///<
+    UINT32  /*                                                  F2BarEn*/:1 ; ///<
+    UINT32  /*                                                  PcieDis*/:1 ; ///<
+    UINT32  /*                                          BifBxcntlSpare0*/:1 ; ///<
+    UINT32  /*                                                   RcieEn*/:1 ; ///<
+    UINT32  /*                                           BifBxcntlSpare*/:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1C_STRUCT;
+
+// **** GMMx00 Register Definition ****
+// Address
+#define GMMx00_ADDRESS                                          0x0
+
+// Type
+#define GMMx00_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx00_Offset_OFFSET                                    0
+#define GMMx00_Offset_WIDTH                                     31
+#define GMMx00_Offset_MASK                                      0x7fffffff
+#define GMMx00_Aper_OFFSET                                      31
+#define GMMx00_Aper_WIDTH                                       1
+#define GMMx00_Aper_MASK                                        0x80000000
+
+/// GMMx00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   Offset:31; ///<
+    UINT32                                                     Aper:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx00_STRUCT;
+
+// **** GMMx04 Register Definition ****
+// Address
+#define GMMx04_ADDRESS                                          0x4
+
+// Type
+#define GMMx04_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx04_Data_OFFSET                                      0
+#define GMMx04_Data_WIDTH                                       32
+#define GMMx04_Data_MASK                                        0xffffffff
+
+/// GMMx04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx04_STRUCT;
+
+
+
+// **** D18F2x09C_x0D0FE00A Register Definition ****
+// Address
+#define D18F2x09C_x0D0FE00A_ADDRESS                             0x0D0FE00A
+
+// Type
+#define D18F2x09C_x0D0FE00A_TYPE                                TYPE_D18F2x9C
+// Field Data
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET                 0
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH                  4
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK                   0xF
+#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET                   4
+#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH                    1
+#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK                     0x10
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET                5
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH                 7
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK                  0xFE0
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET               15
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH                17
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK                 0xFFFF8000
+
+/// D18F2x09C_x0D0FE00A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved_3_0:4; ///<
+    UINT32                                                SkewMemClk:1; ///<
+    UINT32                                             Reserved_11_5:7; ///<
+    UINT32                                         :2; ///<
+    UINT32                                           :1; ///<
+    UINT32                                            Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x09C_x0D0FE00A_STRUCT;
+
+/// D0F0xE4_WRAP_8016
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CalibAckLatency:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                         CalibDoneSelPifA:1 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                           Reserved_10_10:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           Gen1OnlyEngage:1 ; ///<
+    UINT32                                          Gen1OnlyEngaged:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                       LclkDynGateLatency:6 ; ///<
+    UINT32                                             LclkGateFree:1 ; ///<
+    UINT32                                        LclkDynGateEnable:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex688_STRUCT;
+
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
new file mode 100644
index 0000000000..fc9f9d6dd6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbRegistersTN.h
@@ -0,0 +1,41005 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Register definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64732 $   @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBREGISTERSTN_H_
+#define _GNBREGISTERSTN_H_
+#define  TYPE_D0F0                  0x1
+#define  TYPE_D0F0x64               0x2
+#define  TYPE_D0F0x98               0x3
+#define  TYPE_D0F0xBC               0x4
+#define  TYPE_D0F0xE4               0x5
+#define  TYPE_DxF0                  0x6
+#define  TYPE_DxF0xE4               0x7
+#define  TYPE_D0F2                  0x8
+#define  TYPE_D0F2xF4               0x9
+#define  TYPE_D0F2xFC               0xa
+#define  TYPE_D18F1                 0xb
+#define  TYPE_D18F2                 0xc
+#define  TYPE_D18F3                 0xd
+#define  TYPE_D18F4                 0xe
+#define  TYPE_D18F5                 0xf
+#define  TYPE_MSR                   0x10
+#define  TYPE_D1F0                  0x11
+#define  TYPE_GMM                   0x12
+#define  TYPE_D18F2x9C_dct0         0x13
+#define  TYPE_D18F2x9C_dct0_mp0     0x14
+#define  TYPE_D18F2x9C_dct0_mp1     0x15
+#define  TYPE_D18F2x9C_dct1         0x16
+#define  TYPE_D18F2x9C_dct1_mp0     0x17
+#define  TYPE_D18F2x9C_dct1_mp1     0x18
+#define  TYPE_D18F2_dct0            0x19
+#define  TYPE_D18F2_dct1            0x1a
+#define  TYPE_D18F2_dct0_mp0        0x1b
+#define  TYPE_D18F2_dct0_mp1        0x1c
+#define  TYPE_D1F1                  0x1d
+#define  TYPE_D18F2_dct1_mp0        0x1e
+#define  TYPE_D18F2_dct1_mp1        0x1f
+#define  TYPE_CGIND                 0x20
+#define  TYPE_SMU_MSG               0x21
+
+#ifndef WRAP_SPACE
+  #define  WRAP_SPACE(w, x)   (0x01300000 | (w << 16) | (x))
+#endif
+#ifndef CORE_SPACE
+  #define  CORE_SPACE(c, x)   (0x00010000 | (c << 24) | (x))
+#endif
+#ifndef PHY_SPACE
+  #define  PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+#ifndef PIF_SPACE
+  #define  PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
+#endif
+
+#define  L1_SEL_GFX                         0
+#define  L1_SEL_GPPSB                       1
+#define  L1_SEL_GBIF                        2
+#define  L1_SEL_INTGEN                      3
+
+#define  SMU_MSG_TYPE                       TYPE_SMU_MSG
+#define  SMC_MSG_FIRMWARE_AUTH              0
+#define  SMC_MSG_HALT                       1
+#define  SMC_MSG_PHY_LN_OFF                 2
+#define  SMC_MSG_PHY_LN_ON                  3
+#define  SMC_MSG_DDI_PHY_OFF                4
+#define  SMC_MSG_DDI_PHY_ON                 5
+#define  SMC_MSG_CASCADE_PLL_OFF            6
+#define  SMC_MSG_CASCADE_PLL_ON             7
+#define  SMC_MSG_PWR_OFF_x16                8
+#define  SMC_MSG_CONFIG_LCLK_DPM            9
+#define  SMC_MSG_FLUSH_DATA_CACHE           10
+#define  SMC_MSG_FLUSH_INSTRUCTION_CACHE    11
+#define  SMC_MSG_CONFIG_VPC_ACCUMULATOR     12
+#define  SMC_MSG_CONFIG_BAPM                13
+#define  SMC_MSG_CONFIG_TDC_LIMIT           14
+#define  SMC_MSG_CONFIG_LPMx                15
+#define  SMC_MSG_CONFIG_HTC_LIMIT           16
+#define  SMC_MSG_CONFIG_THERMAL_CNTL        17
+#define  SMC_MSG_CONFIG_VOLTAGE_CNTL        18
+#define  SMC_MSG_CONFIG_TDP_CNTL            19
+#define  SMC_MSG_EN_PM_CNTL                 20
+#define  SMC_MSG_DIS_PM_CNTL                21
+#define  SMC_MSG_CONFIG_NBDPM               22
+#define  SMC_MSG_CONFIG_LOADLINE            23
+#define  SMC_MSG_ADJUST_LOADLINE            24
+#define  SMC_MSG_RECONFIGURE                25
+#define  SMC_MSG_PCIE_PLLSWITCH             27
+#define  SMC_MSG_ENABLE_BAPM                32
+#define  SMC_MSG_DISABLE_BAPM               33
+
+// **** D0F0x00 Register Definition ****
+// Address
+#define D0F0x00_ADDRESS                                         0x0
+
+// Type
+#define D0F0x00_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x00_VendorID_OFFSET                                 0
+#define D0F0x00_VendorID_WIDTH                                  16
+#define D0F0x00_VendorID_MASK                                   0xffff
+#define D0F0x00_DeviceID_OFFSET                                 16
+#define D0F0x00_DeviceID_WIDTH                                  16
+#define D0F0x00_DeviceID_MASK                                   0xffff0000
+
+/// D0F0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x00_STRUCT;
+
+// **** D0F0x04 Register Definition ****
+// Address
+#define D0F0x04_ADDRESS                                         0x4
+
+// Type
+#define D0F0x04_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x04_IoAccessEn_OFFSET                               0
+#define D0F0x04_IoAccessEn_WIDTH                                1
+#define D0F0x04_IoAccessEn_MASK                                 0x1
+#define D0F0x04_MemAccessEn_OFFSET                              1
+#define D0F0x04_MemAccessEn_WIDTH                               1
+#define D0F0x04_MemAccessEn_MASK                                0x2
+#define D0F0x04_BusMasterEn_OFFSET                              2
+#define D0F0x04_BusMasterEn_WIDTH                               1
+#define D0F0x04_BusMasterEn_MASK                                0x4
+#define D0F0x04_SpecialCycleEn_OFFSET                           3
+#define D0F0x04_SpecialCycleEn_WIDTH                            1
+#define D0F0x04_SpecialCycleEn_MASK                             0x8
+#define D0F0x04_MemWriteInvalidateEn_OFFSET                     4
+#define D0F0x04_MemWriteInvalidateEn_WIDTH                      1
+#define D0F0x04_MemWriteInvalidateEn_MASK                       0x10
+#define D0F0x04_PalSnoopEn_OFFSET                               5
+#define D0F0x04_PalSnoopEn_WIDTH                                1
+#define D0F0x04_PalSnoopEn_MASK                                 0x20
+#define D0F0x04_ParityErrorEn_OFFSET                            6
+#define D0F0x04_ParityErrorEn_WIDTH                             1
+#define D0F0x04_ParityErrorEn_MASK                              0x40
+#define D0F0x04_Reserved_7_7_OFFSET                             7
+#define D0F0x04_Reserved_7_7_WIDTH                              1
+#define D0F0x04_Reserved_7_7_MASK                               0x80
+#define D0F0x04_SerrEn_OFFSET                                   8
+#define D0F0x04_SerrEn_WIDTH                                    1
+#define D0F0x04_SerrEn_MASK                                     0x100
+#define D0F0x04_FastB2BEn_OFFSET                                9
+#define D0F0x04_FastB2BEn_WIDTH                                 1
+#define D0F0x04_FastB2BEn_MASK                                  0x200
+#define D0F0x04_Reserved_19_10_OFFSET                           10
+#define D0F0x04_Reserved_19_10_WIDTH                            10
+#define D0F0x04_Reserved_19_10_MASK                             0xffc00
+#define D0F0x04_CapList_OFFSET                                  20
+#define D0F0x04_CapList_WIDTH                                   1
+#define D0F0x04_CapList_MASK                                    0x100000
+#define D0F0x04_PCI66En_OFFSET                                  21
+#define D0F0x04_PCI66En_WIDTH                                   1
+#define D0F0x04_PCI66En_MASK                                    0x200000
+#define D0F0x04_Reserved_22_22_OFFSET                           22
+#define D0F0x04_Reserved_22_22_WIDTH                            1
+#define D0F0x04_Reserved_22_22_MASK                             0x400000
+#define D0F0x04_FastBackCapable_OFFSET                          23
+#define D0F0x04_FastBackCapable_WIDTH                           1
+#define D0F0x04_FastBackCapable_MASK                            0x800000
+#define D0F0x04_Reserved_24_24_OFFSET                           24
+#define D0F0x04_Reserved_24_24_WIDTH                            1
+#define D0F0x04_Reserved_24_24_MASK                             0x1000000
+#define D0F0x04_DevselTiming_OFFSET                             25
+#define D0F0x04_DevselTiming_WIDTH                              2
+#define D0F0x04_DevselTiming_MASK                               0x6000000
+#define D0F0x04_SignalTargetAbort_OFFSET                        27
+#define D0F0x04_SignalTargetAbort_WIDTH                         1
+#define D0F0x04_SignalTargetAbort_MASK                          0x8000000
+#define D0F0x04_ReceivedTargetAbort_OFFSET                      28
+#define D0F0x04_ReceivedTargetAbort_WIDTH                       1
+#define D0F0x04_ReceivedTargetAbort_MASK                        0x10000000
+#define D0F0x04_ReceivedMasterAbort_OFFSET                      29
+#define D0F0x04_ReceivedMasterAbort_WIDTH                       1
+#define D0F0x04_ReceivedMasterAbort_MASK                        0x20000000
+#define D0F0x04_SignaledSystemError_OFFSET                      30
+#define D0F0x04_SignaledSystemError_WIDTH                       1
+#define D0F0x04_SignaledSystemError_MASK                        0x40000000
+#define D0F0x04_ParityErrorDetected_OFFSET                      31
+#define D0F0x04_ParityErrorDetected_WIDTH                       1
+#define D0F0x04_ParityErrorDetected_MASK                        0x80000000
+
+/// D0F0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                           SpecialCycleEn:1 ; ///<
+    UINT32                                     MemWriteInvalidateEn:1 ; ///<
+    UINT32                                               PalSnoopEn:1 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                FastB2BEn:1 ; ///<
+    UINT32                                           Reserved_19_10:10; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x04_STRUCT;
+
+// **** D0F0x08 Register Definition ****
+// Address
+#define D0F0x08_ADDRESS                                         0x8
+
+// Type
+#define D0F0x08_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x08_RevID_OFFSET                                    0
+#define D0F0x08_RevID_WIDTH                                     8
+#define D0F0x08_RevID_MASK                                      0xff
+#define D0F0x08_ClassCode_OFFSET                                8
+#define D0F0x08_ClassCode_WIDTH                                 24
+#define D0F0x08_ClassCode_MASK                                  0xffffff00
+
+/// D0F0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x08_STRUCT;
+
+// **** D0F0x0C Register Definition ****
+// Address
+#define D0F0x0C_ADDRESS                                         0xc
+
+// Type
+#define D0F0x0C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x0C_CacheLineSize_OFFSET                            0
+#define D0F0x0C_CacheLineSize_WIDTH                             8
+#define D0F0x0C_CacheLineSize_MASK                              0xff
+#define D0F0x0C_LatencyTimer_OFFSET                             8
+#define D0F0x0C_LatencyTimer_WIDTH                              8
+#define D0F0x0C_LatencyTimer_MASK                               0xff00
+#define D0F0x0C_HeaderTypeReg_OFFSET                            16
+#define D0F0x0C_HeaderTypeReg_WIDTH                             8
+#define D0F0x0C_HeaderTypeReg_MASK                              0xff0000
+#define D0F0x0C_BIST_OFFSET                                     24
+#define D0F0x0C_BIST_WIDTH                                      8
+#define D0F0x0C_BIST_MASK                                       0xff000000
+
+/// D0F0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x0C_STRUCT;
+
+// **** D0F0x2C Register Definition ****
+// Address
+#define D0F0x2C_ADDRESS                                         0x2c
+
+// Type
+#define D0F0x2C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x2C_SubsystemVendorID_OFFSET                        0
+#define D0F0x2C_SubsystemVendorID_WIDTH                         16
+#define D0F0x2C_SubsystemVendorID_MASK                          0xffff
+#define D0F0x2C_SubsystemID_OFFSET                              16
+#define D0F0x2C_SubsystemID_WIDTH                               16
+#define D0F0x2C_SubsystemID_MASK                                0xffff0000
+
+/// D0F0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorID:16; ///<
+    UINT32                                              SubsystemID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x2C_STRUCT;
+
+// **** D0F0x34 Register Definition ****
+// Address
+#define D0F0x34_ADDRESS                                         0x34
+
+// Type
+#define D0F0x34_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x34_CapPtr_OFFSET                                   0
+#define D0F0x34_CapPtr_WIDTH                                    8
+#define D0F0x34_CapPtr_MASK                                     0xff
+#define D0F0x34_Reserved_31_8_OFFSET                            8
+#define D0F0x34_Reserved_31_8_WIDTH                             24
+#define D0F0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x34_STRUCT;
+
+// **** D0F0x4C Register Definition ****
+// Address
+#define D0F0x4C_ADDRESS                                         0x4c
+
+// Type
+#define D0F0x4C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x4C_Function1Enable_OFFSET                          0
+#define D0F0x4C_Function1Enable_WIDTH                           1
+#define D0F0x4C_Function1Enable_MASK                            0x1
+#define D0F0x4C_ApicEnable_OFFSET                               1
+#define D0F0x4C_ApicEnable_WIDTH                                1
+#define D0F0x4C_ApicEnable_MASK                                 0x2
+#define D0F0x4C_Reserved_2_2_OFFSET                             2
+#define D0F0x4C_Reserved_2_2_WIDTH                              1
+#define D0F0x4C_Reserved_2_2_MASK                               0x4
+#define D0F0x4C_Cf8Dis_OFFSET                                   3
+#define D0F0x4C_Cf8Dis_WIDTH                                    1
+#define D0F0x4C_Cf8Dis_MASK                                     0x8
+#define D0F0x4C_PMEDis_OFFSET                                   4
+#define D0F0x4C_PMEDis_WIDTH                                    1
+#define D0F0x4C_PMEDis_MASK                                     0x10
+#define D0F0x4C_SerrDis_OFFSET                                  5
+#define D0F0x4C_SerrDis_WIDTH                                   1
+#define D0F0x4C_SerrDis_MASK                                    0x20
+#define D0F0x4C_Reserved_10_6_OFFSET                            6
+#define D0F0x4C_Reserved_10_6_WIDTH                             5
+#define D0F0x4C_Reserved_10_6_MASK                              0x7c0
+#define D0F0x4C_CRS_OFFSET                                      11
+#define D0F0x4C_CRS_WIDTH                                       1
+#define D0F0x4C_CRS_MASK                                        0x800
+#define D0F0x4C_CfgRdTime_OFFSET                                12
+#define D0F0x4C_CfgRdTime_WIDTH                                 3
+#define D0F0x4C_CfgRdTime_MASK                                  0x7000
+#define D0F0x4C_Reserved_22_15_OFFSET                           15
+#define D0F0x4C_Reserved_22_15_WIDTH                            8
+#define D0F0x4C_Reserved_22_15_MASK                             0x7f8000
+#define D0F0x4C_MMIOEnable_OFFSET                               23
+#define D0F0x4C_MMIOEnable_WIDTH                                1
+#define D0F0x4C_MMIOEnable_MASK                                 0x800000
+#define D0F0x4C_Reserved_25_24_OFFSET                           24
+#define D0F0x4C_Reserved_25_24_WIDTH                            2
+#define D0F0x4C_Reserved_25_24_MASK                             0x3000000
+#define D0F0x4C_HPDis_OFFSET                                    26
+#define D0F0x4C_HPDis_WIDTH                                     1
+#define D0F0x4C_HPDis_MASK                                      0x4000000
+#define D0F0x4C_Reserved_31_27_OFFSET                           27
+#define D0F0x4C_Reserved_31_27_WIDTH                            5
+#define D0F0x4C_Reserved_31_27_MASK                             0xf8000000
+
+/// D0F0x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          Function1Enable:1 ; ///<
+    UINT32                                               ApicEnable:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                   Cf8Dis:1 ; ///<
+    UINT32                                                   PMEDis:1 ; ///<
+    UINT32                                                  SerrDis:1 ; ///<
+    UINT32                                            Reserved_10_6:5 ; ///<
+    UINT32                                                      CRS:1 ; ///<
+    UINT32                                                CfgRdTime:3 ; ///<
+    UINT32                                           Reserved_22_15:8 ; ///<
+    UINT32                                               MMIOEnable:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    HPDis:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x4C_STRUCT;
+
+// **** D0F0x60 Register Definition ****
+// Address
+#define D0F0x60_ADDRESS                                         0x60
+
+// Type
+#define D0F0x60_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x60_MiscIndAddr_OFFSET                              0
+#define D0F0x60_MiscIndAddr_WIDTH                               7
+#define D0F0x60_MiscIndAddr_MASK                                0x7f
+#define D0F0x60_MiscIndWrEn_OFFSET                              7
+#define D0F0x60_MiscIndWrEn_WIDTH                               1
+#define D0F0x60_MiscIndWrEn_MASK                                0x80
+#define D0F0x60_Reserved_31_8_OFFSET                            8
+#define D0F0x60_Reserved_31_8_WIDTH                             24
+#define D0F0x60_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndAddr:7 ; ///<
+    UINT32                                              MiscIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x60_STRUCT;
+
+// **** D0F0x64 Register Definition ****
+// Address
+#define D0F0x64_ADDRESS                                         0x64
+
+// Type
+#define D0F0x64_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x64_MiscIndData_OFFSET                              0
+#define D0F0x64_MiscIndData_WIDTH                               32
+#define D0F0x64_MiscIndData_MASK                                0xffffffff
+
+/// D0F0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MiscIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_STRUCT;
+
+// **** D0F0x7C Register Definition ****
+// Address
+#define D0F0x7C_ADDRESS                                         0x7c
+
+// Type
+#define D0F0x7C_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x7C_ForceIntGFXDisable_OFFSET                       0
+#define D0F0x7C_ForceIntGFXDisable_WIDTH                        1
+#define D0F0x7C_ForceIntGFXDisable_MASK                         0x1
+#define D0F0x7C_Reserved_31_1_OFFSET                            1
+#define D0F0x7C_Reserved_31_1_WIDTH                             31
+#define D0F0x7C_Reserved_31_1_MASK                              0xfffffffe
+
+/// D0F0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       ForceIntGFXDisable:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x7C_STRUCT;
+
+// **** D0F0x84 Register Definition ****
+// Address
+#define D0F0x84_ADDRESS                                         0x84
+
+// Type
+#define D0F0x84_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x84_Reserved_2_0_OFFSET                             0
+#define D0F0x84_Reserved_2_0_WIDTH                              3
+#define D0F0x84_Reserved_2_0_MASK                               0x7
+#define D0F0x84_VgaHole_OFFSET                                  3
+#define D0F0x84_VgaHole_WIDTH                                   1
+#define D0F0x84_VgaHole_MASK                                    0x8
+#define D0F0x84_Ev6Mode_OFFSET                                  4
+#define D0F0x84_Ev6Mode_WIDTH                                   1
+#define D0F0x84_Ev6Mode_MASK                                    0x10
+#define D0F0x84_Reserved_7_5_OFFSET                             5
+#define D0F0x84_Reserved_7_5_WIDTH                              3
+#define D0F0x84_Reserved_7_5_MASK                               0xe0
+#define D0F0x84_PmeMode_OFFSET                                  8
+#define D0F0x84_PmeMode_WIDTH                                   1
+#define D0F0x84_PmeMode_MASK                                    0x100
+#define D0F0x84_PmeTurnOff_OFFSET                               9
+#define D0F0x84_PmeTurnOff_WIDTH                                1
+#define D0F0x84_PmeTurnOff_MASK                                 0x200
+#define D0F0x84_Reserved_31_10_OFFSET                           10
+#define D0F0x84_Reserved_31_10_WIDTH                            22
+#define D0F0x84_Reserved_31_10_MASK                             0xfffffc00
+
+/// D0F0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                                  VgaHole:1 ; ///<
+    UINT32                                                  Ev6Mode:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                  PmeMode:1 ; ///<
+    UINT32                                               PmeTurnOff:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x84_STRUCT;
+
+// **** D0F0x90 Register Definition ****
+// Address
+#define D0F0x90_ADDRESS                                         0x90
+
+// Type
+#define D0F0x90_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x90_Reserved_22_0_OFFSET                            0
+#define D0F0x90_Reserved_22_0_WIDTH                             23
+#define D0F0x90_Reserved_22_0_MASK                              0x7fffff
+#define D0F0x90_TopOfDram_OFFSET                                23
+#define D0F0x90_TopOfDram_WIDTH                                 9
+#define D0F0x90_TopOfDram_MASK                                  0xff800000
+
+/// D0F0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                                TopOfDram:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x90_STRUCT;
+
+// **** D0F0x94 Register Definition ****
+// Address
+#define D0F0x94_ADDRESS                                         0x94
+
+// Type
+#define D0F0x94_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x94_OrbIndAddr_OFFSET                               0
+#define D0F0x94_OrbIndAddr_WIDTH                                7
+#define D0F0x94_OrbIndAddr_MASK                                 0x7f
+#define D0F0x94_Reserved_7_7_OFFSET                             7
+#define D0F0x94_Reserved_7_7_WIDTH                              1
+#define D0F0x94_Reserved_7_7_MASK                               0x80
+#define D0F0x94_OrbIndWrEn_OFFSET                               8
+#define D0F0x94_OrbIndWrEn_WIDTH                                1
+#define D0F0x94_OrbIndWrEn_MASK                                 0x100
+#define D0F0x94_Reserved_31_9_OFFSET                            9
+#define D0F0x94_Reserved_31_9_WIDTH                             23
+#define D0F0x94_Reserved_31_9_MASK                              0xfffffe00
+
+/// D0F0x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndAddr:7 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                               OrbIndWrEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x94_STRUCT;
+
+// **** D0F0x98 Register Definition ****
+// Address
+#define D0F0x98_ADDRESS                                         0x98
+
+// Type
+#define D0F0x98_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0x98_OrbIndData_OFFSET                               0
+#define D0F0x98_OrbIndData_WIDTH                                32
+#define D0F0x98_OrbIndData_MASK                                 0xffffffff
+
+/// D0F0x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               OrbIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_STRUCT;
+
+// **** D0F0xB8 Register Definition ****
+// Address
+#define D0F0xB8_ADDRESS                                         0xb8
+
+// Type
+#define D0F0xB8_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xB8_NbSmuIndAddr_OFFSET                             0
+#define D0F0xB8_NbSmuIndAddr_WIDTH                              32
+#define D0F0xB8_NbSmuIndAddr_MASK                               0xffffffff
+
+/// D0F0xB8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NbSmuIndAddr:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xB8_STRUCT;
+
+// **** D0F0xBC Register Definition ****
+// Address
+#define D0F0xBC_ADDRESS                                         0xbc
+
+// Type
+#define D0F0xBC_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xBC_NbSmuIndData_OFFSET                             0
+#define D0F0xBC_NbSmuIndData_WIDTH                              32
+#define D0F0xBC_NbSmuIndData_MASK                               0xffffffff
+
+/// D0F0xBC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NbSmuIndData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_STRUCT;
+
+// **** D0F0xE0 Register Definition ****
+// Address
+#define D0F0xE0_ADDRESS                                         0xe0
+
+// Type
+#define D0F0xE0_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE0_PcieIndxAddr_OFFSET                             0
+#define D0F0xE0_PcieIndxAddr_WIDTH                              16
+#define D0F0xE0_PcieIndxAddr_MASK                               0xffff
+#define D0F0xE0_FrameType_OFFSET                                16
+#define D0F0xE0_FrameType_WIDTH                                 8
+#define D0F0xE0_FrameType_MASK                                  0xff0000
+#define D0F0xE0_BlockSelect_OFFSET                              24
+#define D0F0xE0_BlockSelect_WIDTH                               8
+#define D0F0xE0_BlockSelect_MASK                                0xff000000
+
+/// D0F0xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxAddr:16; ///<
+    UINT32                                                FrameType:8 ; ///<
+    UINT32                                              BlockSelect:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE0_STRUCT;
+
+// **** D0F0xE4 Register Definition ****
+// Address
+#define D0F0xE4_ADDRESS                                         0xe4
+
+// Type
+#define D0F0xE4_TYPE                                            TYPE_D0F0
+// Field Data
+#define D0F0xE4_PcieIndxData_OFFSET                             0
+#define D0F0xE4_PcieIndxData_WIDTH                              32
+#define D0F0xE4_PcieIndxData_MASK                               0xffffffff
+
+/// D0F0xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PcieIndxData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_STRUCT;
+
+// **** D0F2x00 Register Definition ****
+// Address
+#define D0F2x00_ADDRESS                                         0x0
+
+// Type
+#define D0F2x00_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x00_VendorId_OFFSET                                 0
+#define D0F2x00_VendorId_WIDTH                                  16
+#define D0F2x00_VendorId_MASK                                   0xffff
+#define D0F2x00_DeviceId_OFFSET                                 16
+#define D0F2x00_DeviceId_WIDTH                                  16
+#define D0F2x00_DeviceId_MASK                                   0xffff0000
+
+/// D0F2x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorId:16; ///<
+    UINT32                                                 DeviceId:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x00_STRUCT;
+
+// **** D0F2x04 Register Definition ****
+// Address
+#define D0F2x04_ADDRESS                                         0x4
+
+// Type
+#define D0F2x04_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x04_IoAccessEn_OFFSET                               0
+#define D0F2x04_IoAccessEn_WIDTH                                1
+#define D0F2x04_IoAccessEn_MASK                                 0x1
+#define D0F2x04_MemAccessEn_OFFSET                              1
+#define D0F2x04_MemAccessEn_WIDTH                               1
+#define D0F2x04_MemAccessEn_MASK                                0x2
+#define D0F2x04_BusMasterEn_OFFSET                              2
+#define D0F2x04_BusMasterEn_WIDTH                               1
+#define D0F2x04_BusMasterEn_MASK                                0x4
+#define D0F2x04_Reserved_5_3_OFFSET                             3
+#define D0F2x04_Reserved_5_3_WIDTH                              3
+#define D0F2x04_Reserved_5_3_MASK                               0x38
+#define D0F2x04_ParityErrorEn_OFFSET                            6
+#define D0F2x04_ParityErrorEn_WIDTH                             1
+#define D0F2x04_ParityErrorEn_MASK                              0x40
+#define D0F2x04_Reserved_7_7_OFFSET                             7
+#define D0F2x04_Reserved_7_7_WIDTH                              1
+#define D0F2x04_Reserved_7_7_MASK                               0x80
+#define D0F2x04_SerrEn_OFFSET                                   8
+#define D0F2x04_SerrEn_WIDTH                                    1
+#define D0F2x04_SerrEn_MASK                                     0x100
+#define D0F2x04_Reserved_9_9_OFFSET                             9
+#define D0F2x04_Reserved_9_9_WIDTH                              1
+#define D0F2x04_Reserved_9_9_MASK                               0x200
+#define D0F2x04_InterruptDis_OFFSET                             10
+#define D0F2x04_InterruptDis_WIDTH                              1
+#define D0F2x04_InterruptDis_MASK                               0x400
+#define D0F2x04_Reserved_18_11_OFFSET                           11
+#define D0F2x04_Reserved_18_11_WIDTH                            8
+#define D0F2x04_Reserved_18_11_MASK                             0x7f800
+#define D0F2x04_IntStatus_OFFSET                                19
+#define D0F2x04_IntStatus_WIDTH                                 1
+#define D0F2x04_IntStatus_MASK                                  0x80000
+#define D0F2x04_CapList_OFFSET                                  20
+#define D0F2x04_CapList_WIDTH                                   1
+#define D0F2x04_CapList_MASK                                    0x100000
+#define D0F2x04_Reserved_23_21_OFFSET                           21
+#define D0F2x04_Reserved_23_21_WIDTH                            3
+#define D0F2x04_Reserved_23_21_MASK                             0xe00000
+#define D0F2x04_MasterDataError_OFFSET                          24
+#define D0F2x04_MasterDataError_WIDTH                           1
+#define D0F2x04_MasterDataError_MASK                            0x1000000
+#define D0F2x04_Reserved_26_25_OFFSET                           25
+#define D0F2x04_Reserved_26_25_WIDTH                            2
+#define D0F2x04_Reserved_26_25_MASK                             0x6000000
+#define D0F2x04_SignalTargetAbort_OFFSET                        27
+#define D0F2x04_SignalTargetAbort_WIDTH                         1
+#define D0F2x04_SignalTargetAbort_MASK                          0x8000000
+#define D0F2x04_ReceivedTargetAbort_OFFSET                      28
+#define D0F2x04_ReceivedTargetAbort_WIDTH                       1
+#define D0F2x04_ReceivedTargetAbort_MASK                        0x10000000
+#define D0F2x04_ReceivedMasterAbort_OFFSET                      29
+#define D0F2x04_ReceivedMasterAbort_WIDTH                       1
+#define D0F2x04_ReceivedMasterAbort_MASK                        0x20000000
+#define D0F2x04_SignaledSystemError_OFFSET                      30
+#define D0F2x04_SignaledSystemError_WIDTH                       1
+#define D0F2x04_SignaledSystemError_MASK                        0x40000000
+#define D0F2x04_ParityErrorDetected_OFFSET                      31
+#define D0F2x04_ParityErrorDetected_WIDTH                       1
+#define D0F2x04_ParityErrorDetected_MASK                        0x80000000
+
+/// D0F2x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                             Reserved_5_3:3 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             InterruptDis:1 ; ///<
+    UINT32                                           Reserved_18_11:8 ; ///<
+    UINT32                                                IntStatus:1 ; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                          MasterDataError:1 ; ///<
+    UINT32                                           Reserved_26_25:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x04_STRUCT;
+
+// **** D0F2x08 Register Definition ****
+// Address
+#define D0F2x08_ADDRESS                                         0x8
+
+// Type
+#define D0F2x08_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x08_RevID_OFFSET                                    0
+#define D0F2x08_RevID_WIDTH                                     8
+#define D0F2x08_RevID_MASK                                      0xff
+#define D0F2x08_ClassCode_OFFSET                                8
+#define D0F2x08_ClassCode_WIDTH                                 24
+#define D0F2x08_ClassCode_MASK                                  0xffffff00
+
+/// D0F2x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x08_STRUCT;
+
+// **** D0F2x0C Register Definition ****
+// Address
+#define D0F2x0C_ADDRESS                                         0xc
+
+// Type
+#define D0F2x0C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x0C_CacheLineSize_OFFSET                            0
+#define D0F2x0C_CacheLineSize_WIDTH                             8
+#define D0F2x0C_CacheLineSize_MASK                              0xff
+#define D0F2x0C_LatencyTimer_OFFSET                             8
+#define D0F2x0C_LatencyTimer_WIDTH                              8
+#define D0F2x0C_LatencyTimer_MASK                               0xff00
+#define D0F2x0C_HeaderTypeReg_OFFSET                            16
+#define D0F2x0C_HeaderTypeReg_WIDTH                             8
+#define D0F2x0C_HeaderTypeReg_MASK                              0xff0000
+#define D0F2x0C_BIST_OFFSET                                     24
+#define D0F2x0C_BIST_WIDTH                                      8
+#define D0F2x0C_BIST_MASK                                       0xff000000
+
+/// D0F2x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x0C_STRUCT;
+
+// **** D0F2x2C Register Definition ****
+// Address
+#define D0F2x2C_ADDRESS                                         0x2c
+
+// Type
+#define D0F2x2C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x2C_SubsystemVendorId_OFFSET                        0
+#define D0F2x2C_SubsystemVendorId_WIDTH                         16
+#define D0F2x2C_SubsystemVendorId_MASK                          0xffff
+#define D0F2x2C_SubsystemId_OFFSET                              16
+#define D0F2x2C_SubsystemId_WIDTH                               16
+#define D0F2x2C_SubsystemId_MASK                                0xffff0000
+
+/// D0F2x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorId:16; ///<
+    UINT32                                              SubsystemId:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x2C_STRUCT;
+
+// **** D0F2x34 Register Definition ****
+// Address
+#define D0F2x34_ADDRESS                                         0x34
+
+// Type
+#define D0F2x34_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x34_CapPtr_OFFSET                                   0
+#define D0F2x34_CapPtr_WIDTH                                    8
+#define D0F2x34_CapPtr_MASK                                     0xff
+#define D0F2x34_Reserved_31_8_OFFSET                            8
+#define D0F2x34_Reserved_31_8_WIDTH                             24
+#define D0F2x34_Reserved_31_8_MASK                              0xffffff00
+
+/// D0F2x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x34_STRUCT;
+
+// **** D0F2x3C Register Definition ****
+// Address
+#define D0F2x3C_ADDRESS                                         0x3c
+
+// Type
+#define D0F2x3C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x3C_InterruptLine_OFFSET                            0
+#define D0F2x3C_InterruptLine_WIDTH                             8
+#define D0F2x3C_InterruptLine_MASK                              0xff
+#define D0F2x3C_InterruptPin_OFFSET                             8
+#define D0F2x3C_InterruptPin_WIDTH                              8
+#define D0F2x3C_InterruptPin_MASK                               0xff00
+#define D0F2x3C_Reserved_31_16_OFFSET                           16
+#define D0F2x3C_Reserved_31_16_WIDTH                            16
+#define D0F2x3C_Reserved_31_16_MASK                             0xffff0000
+
+/// D0F2x3C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            InterruptLine:8 ; ///<
+    UINT32                                             InterruptPin:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x3C_STRUCT;
+
+// **** D0F2x40 Register Definition ****
+// Address
+#define D0F2x40_ADDRESS                                         0x40
+
+// Type
+#define D0F2x40_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x40_IommuCapId_OFFSET                               0
+#define D0F2x40_IommuCapId_WIDTH                                8
+#define D0F2x40_IommuCapId_MASK                                 0xff
+#define D0F2x40_IommuCapPtr_OFFSET                              8
+#define D0F2x40_IommuCapPtr_WIDTH                               8
+#define D0F2x40_IommuCapPtr_MASK                                0xff00
+#define D0F2x40_IommuCapType_OFFSET                             16
+#define D0F2x40_IommuCapType_WIDTH                              3
+#define D0F2x40_IommuCapType_MASK                               0x70000
+#define D0F2x40_IommuCapRev_OFFSET                              19
+#define D0F2x40_IommuCapRev_WIDTH                               5
+#define D0F2x40_IommuCapRev_MASK                                0xf80000
+#define D0F2x40_IommuIoTlbsup_OFFSET                            24
+#define D0F2x40_IommuIoTlbsup_WIDTH                             1
+#define D0F2x40_IommuIoTlbsup_MASK                              0x1000000
+#define D0F2x40_IommuHtTunnelSup_OFFSET                         25
+#define D0F2x40_IommuHtTunnelSup_WIDTH                          1
+#define D0F2x40_IommuHtTunnelSup_MASK                           0x2000000
+#define D0F2x40_IommuNpCache_OFFSET                             26
+#define D0F2x40_IommuNpCache_WIDTH                              1
+#define D0F2x40_IommuNpCache_MASK                               0x4000000
+#define D0F2x40_IommuEfrSup_OFFSET                              27
+#define D0F2x40_IommuEfrSup_WIDTH                               1
+#define D0F2x40_IommuEfrSup_MASK                                0x8000000
+#define D0F2x40_Reserved_31_28_OFFSET                           28
+#define D0F2x40_Reserved_31_28_WIDTH                            4
+#define D0F2x40_Reserved_31_28_MASK                             0xf0000000
+
+/// D0F2x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IommuCapId:8 ; ///<
+    UINT32                                              IommuCapPtr:8 ; ///<
+    UINT32                                             IommuCapType:3 ; ///<
+    UINT32                                              IommuCapRev:5 ; ///<
+    UINT32                                            IommuIoTlbsup:1 ; ///<
+    UINT32                                         IommuHtTunnelSup:1 ; ///<
+    UINT32                                             IommuNpCache:1 ; ///<
+    UINT32                                              IommuEfrSup:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x40_STRUCT;
+
+// **** D0F2x44 Register Definition ****
+// Address
+#define D0F2x44_ADDRESS                                         0x44
+
+// Type
+#define D0F2x44_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x44_IommuEnable_OFFSET                              0
+#define D0F2x44_IommuEnable_WIDTH                               1
+#define D0F2x44_IommuEnable_MASK                                0x1
+#define D0F2x44_Reserved_13_1_OFFSET                            1
+#define D0F2x44_Reserved_13_1_WIDTH                             13
+#define D0F2x44_Reserved_13_1_MASK                              0x3ffe
+#define D0F2x44_IommuBaseAddr_31_14__OFFSET                     14
+#define D0F2x44_IommuBaseAddr_31_14__WIDTH                      18
+#define D0F2x44_IommuBaseAddr_31_14__MASK                       0xffffc000
+
+/// D0F2x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IommuEnable:1 ; ///<
+    UINT32                                            Reserved_13_1:13; ///<
+    UINT32                                     IommuBaseAddr_31_14_:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x44_STRUCT;
+
+// **** D0F2x48 Register Definition ****
+// Address
+#define D0F2x48_ADDRESS                                         0x48
+
+// Type
+#define D0F2x48_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x48_IommuBaseAddr_63_32__OFFSET                     0
+#define D0F2x48_IommuBaseAddr_63_32__WIDTH                      32
+#define D0F2x48_IommuBaseAddr_63_32__MASK                       0xffffffff
+
+/// D0F2x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     IommuBaseAddr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x48_STRUCT;
+
+// **** D0F2x4C Register Definition ****
+// Address
+#define D0F2x4C_ADDRESS                                         0x4c
+
+// Type
+#define D0F2x4C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x4C_IommuUnitId_OFFSET                              0
+#define D0F2x4C_IommuUnitId_WIDTH                               5
+#define D0F2x4C_IommuUnitId_MASK                                0x1f
+#define D0F2x4C_Reserved_6_5_OFFSET                             5
+#define D0F2x4C_Reserved_6_5_WIDTH                              2
+#define D0F2x4C_Reserved_6_5_MASK                               0x60
+#define D0F2x4C_IommuRngValid_OFFSET                            7
+#define D0F2x4C_IommuRngValid_WIDTH                             1
+#define D0F2x4C_IommuRngValid_MASK                              0x80
+#define D0F2x4C_IommuBusNumber_OFFSET                           8
+#define D0F2x4C_IommuBusNumber_WIDTH                            8
+#define D0F2x4C_IommuBusNumber_MASK                             0xff00
+#define D0F2x4C_IommuFirstDevice_OFFSET                         16
+#define D0F2x4C_IommuFirstDevice_WIDTH                          8
+#define D0F2x4C_IommuFirstDevice_MASK                           0xff0000
+#define D0F2x4C_IommuLastDevice_OFFSET                          24
+#define D0F2x4C_IommuLastDevice_WIDTH                           8
+#define D0F2x4C_IommuLastDevice_MASK                            0xff000000
+
+/// D0F2x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IommuUnitId:5 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                            IommuRngValid:1 ; ///<
+    UINT32                                           IommuBusNumber:8 ; ///<
+    UINT32                                         IommuFirstDevice:8 ; ///<
+    UINT32                                          IommuLastDevice:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x4C_STRUCT;
+
+// **** D0F2x50 Register Definition ****
+// Address
+#define D0F2x50_ADDRESS                                         0x50
+
+// Type
+#define D0F2x50_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x50_IommuMsiNum_OFFSET                              0
+#define D0F2x50_IommuMsiNum_WIDTH                               5
+#define D0F2x50_IommuMsiNum_MASK                                0x1f
+#define D0F2x50_IommuGvaSize_OFFSET                             5
+#define D0F2x50_IommuGvaSize_WIDTH                              3
+#define D0F2x50_IommuGvaSize_MASK                               0xe0
+#define D0F2x50_IommuPaSize_OFFSET                              8
+#define D0F2x50_IommuPaSize_WIDTH                               7
+#define D0F2x50_IommuPaSize_MASK                                0x7f00
+#define D0F2x50_IommuVaSize_OFFSET                              15
+#define D0F2x50_IommuVaSize_WIDTH                               7
+#define D0F2x50_IommuVaSize_MASK                                0x3f8000
+#define D0F2x50_IommuHtAtsResv_OFFSET                           22
+#define D0F2x50_IommuHtAtsResv_WIDTH                            1
+#define D0F2x50_IommuHtAtsResv_MASK                             0x400000
+#define D0F2x50_Reserved_26_23_OFFSET                           23
+#define D0F2x50_Reserved_26_23_WIDTH                            4
+#define D0F2x50_Reserved_26_23_MASK                             0x7800000
+#define D0F2x50_IommuMsiNumPpr_OFFSET                           27
+#define D0F2x50_IommuMsiNumPpr_WIDTH                            5
+#define D0F2x50_IommuMsiNumPpr_MASK                             0xf8000000
+
+/// D0F2x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IommuMsiNum:5 ; ///<
+    UINT32                                             IommuGvaSize:3 ; ///<
+    UINT32                                              IommuPaSize:7 ; ///<
+    UINT32                                              IommuVaSize:7 ; ///<
+    UINT32                                           IommuHtAtsResv:1 ; ///<
+    UINT32                                           Reserved_26_23:4 ; ///<
+    UINT32                                           IommuMsiNumPpr:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x50_STRUCT;
+
+// **** D0F2x54 Register Definition ****
+// Address
+#define D0F2x54_ADDRESS                                         0x54
+
+// Type
+#define D0F2x54_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x54_MsiCapId_OFFSET                                 0
+#define D0F2x54_MsiCapId_WIDTH                                  8
+#define D0F2x54_MsiCapId_MASK                                   0xff
+#define D0F2x54_MsiCapPtr_OFFSET                                8
+#define D0F2x54_MsiCapPtr_WIDTH                                 8
+#define D0F2x54_MsiCapPtr_MASK                                  0xff00
+#define D0F2x54_MsiEn_OFFSET                                    16
+#define D0F2x54_MsiEn_WIDTH                                     1
+#define D0F2x54_MsiEn_MASK                                      0x10000
+#define D0F2x54_MsiMultMessCap_OFFSET                           17
+#define D0F2x54_MsiMultMessCap_WIDTH                            3
+#define D0F2x54_MsiMultMessCap_MASK                             0xe0000
+#define D0F2x54_MsiMultMessEn_OFFSET                            20
+#define D0F2x54_MsiMultMessEn_WIDTH                             3
+#define D0F2x54_MsiMultMessEn_MASK                              0x700000
+#define D0F2x54_Msi64En_OFFSET                                  23
+#define D0F2x54_Msi64En_WIDTH                                   1
+#define D0F2x54_Msi64En_MASK                                    0x800000
+#define D0F2x54_Reserved_31_24_OFFSET                           24
+#define D0F2x54_Reserved_31_24_WIDTH                            8
+#define D0F2x54_Reserved_31_24_MASK                             0xff000000
+
+/// D0F2x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 MsiCapId:8 ; ///<
+    UINT32                                                MsiCapPtr:8 ; ///<
+    UINT32                                                    MsiEn:1 ; ///<
+    UINT32                                           MsiMultMessCap:3 ; ///<
+    UINT32                                            MsiMultMessEn:3 ; ///<
+    UINT32                                                  Msi64En:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x54_STRUCT;
+
+// **** D0F2x58 Register Definition ****
+// Address
+#define D0F2x58_ADDRESS                                         0x58
+
+// Type
+#define D0F2x58_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x58_Reserved_1_0_OFFSET                             0
+#define D0F2x58_Reserved_1_0_WIDTH                              2
+#define D0F2x58_Reserved_1_0_MASK                               0x3
+#define D0F2x58_MsiAddr_31_2__OFFSET                            2
+#define D0F2x58_MsiAddr_31_2__WIDTH                             30
+#define D0F2x58_MsiAddr_31_2__MASK                              0xfffffffc
+
+/// D0F2x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            MsiAddr_31_2_:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x58_STRUCT;
+
+// **** D0F2x5C Register Definition ****
+// Address
+#define D0F2x5C_ADDRESS                                         0x5c
+
+// Type
+#define D0F2x5C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x5C_MsiAddr_63_32__OFFSET                           0
+#define D0F2x5C_MsiAddr_63_32__WIDTH                            32
+#define D0F2x5C_MsiAddr_63_32__MASK                             0xffffffff
+
+/// D0F2x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MsiAddr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x5C_STRUCT;
+
+// **** D0F2x60 Register Definition ****
+// Address
+#define D0F2x60_ADDRESS                                         0x60
+
+// Type
+#define D0F2x60_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x60_MsiData_OFFSET                                  0
+#define D0F2x60_MsiData_WIDTH                                   16
+#define D0F2x60_MsiData_MASK                                    0xffff
+#define D0F2x60_Reserved_31_16_OFFSET                           16
+#define D0F2x60_Reserved_31_16_WIDTH                            16
+#define D0F2x60_Reserved_31_16_MASK                             0xffff0000
+
+/// D0F2x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  MsiData:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x60_STRUCT;
+
+// **** D0F2x64 Register Definition ****
+// Address
+#define D0F2x64_ADDRESS                                         0x64
+
+// Type
+#define D0F2x64_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x64_MsiMapCapId_OFFSET                              0
+#define D0F2x64_MsiMapCapId_WIDTH                               8
+#define D0F2x64_MsiMapCapId_MASK                                0xff
+#define D0F2x64_MsiMapCapPtr_OFFSET                             8
+#define D0F2x64_MsiMapCapPtr_WIDTH                              8
+#define D0F2x64_MsiMapCapPtr_MASK                               0xff00
+#define D0F2x64_MsiMapEn_OFFSET                                 16
+#define D0F2x64_MsiMapEn_WIDTH                                  1
+#define D0F2x64_MsiMapEn_MASK                                   0x10000
+#define D0F2x64_MsiMapFixd_OFFSET                               17
+#define D0F2x64_MsiMapFixd_WIDTH                                1
+#define D0F2x64_MsiMapFixd_MASK                                 0x20000
+#define D0F2x64_Reserved_26_18_OFFSET                           18
+#define D0F2x64_Reserved_26_18_WIDTH                            9
+#define D0F2x64_Reserved_26_18_MASK                             0x7fc0000
+#define D0F2x64_MsiMapCapType_OFFSET                            27
+#define D0F2x64_MsiMapCapType_WIDTH                             5
+#define D0F2x64_MsiMapCapType_MASK                              0xf8000000
+
+/// D0F2x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MsiMapCapId:8 ; ///<
+    UINT32                                             MsiMapCapPtr:8 ; ///<
+    UINT32                                                 MsiMapEn:1 ; ///<
+    UINT32                                               MsiMapFixd:1 ; ///<
+    UINT32                                           Reserved_26_18:9 ; ///<
+    UINT32                                            MsiMapCapType:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x64_STRUCT;
+
+// **** D0F2x6C Register Definition ****
+// Address
+#define D0F2x6C_ADDRESS                                         0x6c
+
+// Type
+#define D0F2x6C_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x6C_InterruptPinW_OFFSET                            0
+#define D0F2x6C_InterruptPinW_WIDTH                             3
+#define D0F2x6C_InterruptPinW_MASK                              0x7
+#define D0F2x6C_Reserved_3_3_OFFSET                             3
+#define D0F2x6C_Reserved_3_3_WIDTH                              1
+#define D0F2x6C_Reserved_3_3_MASK                               0x8
+#define D0F2x6C_MinorRevIdW_OFFSET                              4
+#define D0F2x6C_MinorRevIdW_WIDTH                               4
+#define D0F2x6C_MinorRevIdW_MASK                                0xf0
+#define D0F2x6C_IoTlbsupW_OFFSET                                8
+#define D0F2x6C_IoTlbsupW_WIDTH                                 1
+#define D0F2x6C_IoTlbsupW_MASK                                  0x100
+#define D0F2x6C_EfrSupW_OFFSET                                  9
+#define D0F2x6C_EfrSupW_WIDTH                                   1
+#define D0F2x6C_EfrSupW_MASK                                    0x200
+#define D0F2x6C_Reserved_31_10_OFFSET                           10
+#define D0F2x6C_Reserved_31_10_WIDTH                            22
+#define D0F2x6C_Reserved_31_10_MASK                             0xfffffc00
+
+/// D0F2x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            InterruptPinW:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                              MinorRevIdW:4 ; ///<
+    UINT32                                                IoTlbsupW:1 ; ///<
+    UINT32                                                  EfrSupW:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x6C_STRUCT;
+
+// **** D0F2x70 Register Definition ****
+// Address
+#define D0F2x70_ADDRESS                                         0x70
+
+// Type
+#define D0F2x70_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x70_PrefSupW_OFFSET                                 0
+#define D0F2x70_PrefSupW_WIDTH                                  1
+#define D0F2x70_PrefSupW_MASK                                   0x1
+#define D0F2x70_PprSupW_OFFSET                                  1
+#define D0F2x70_PprSupW_WIDTH                                   1
+#define D0F2x70_PprSupW_MASK                                    0x2
+#define D0F2x70_Reserved_2_2_OFFSET                             2
+#define D0F2x70_Reserved_2_2_WIDTH                              1
+#define D0F2x70_Reserved_2_2_MASK                               0x4
+#define D0F2x70_NxSupW_OFFSET                                   3
+#define D0F2x70_NxSupW_WIDTH                                    1
+#define D0F2x70_NxSupW_MASK                                     0x8
+#define D0F2x70_GtSupW_OFFSET                                   4
+#define D0F2x70_GtSupW_WIDTH                                    1
+#define D0F2x70_GtSupW_MASK                                     0x10
+#define D0F2x70_Reserved_5_5_OFFSET                             5
+#define D0F2x70_Reserved_5_5_WIDTH                              1
+#define D0F2x70_Reserved_5_5_MASK                               0x20
+#define D0F2x70_IaSupW_OFFSET                                   6
+#define D0F2x70_IaSupW_WIDTH                                    1
+#define D0F2x70_IaSupW_MASK                                     0x40
+#define D0F2x70_Reserved_7_7_OFFSET                             7
+#define D0F2x70_Reserved_7_7_WIDTH                              1
+#define D0F2x70_Reserved_7_7_MASK                               0x80
+#define D0F2x70_Reserved_8_8_OFFSET                             8
+#define D0F2x70_Reserved_8_8_WIDTH                              1
+#define D0F2x70_Reserved_8_8_MASK                               0x100
+#define D0F2x70_PcSupW_OFFSET                                   9
+#define D0F2x70_PcSupW_WIDTH                                    1
+#define D0F2x70_PcSupW_MASK                                     0x200
+#define D0F2x70_HatsW_OFFSET                                    10
+#define D0F2x70_HatsW_WIDTH                                     2
+#define D0F2x70_HatsW_MASK                                      0xc00
+#define D0F2x70_Reserved_31_12_OFFSET                           12
+#define D0F2x70_Reserved_31_12_WIDTH                            20
+#define D0F2x70_Reserved_31_12_MASK                             0xfffff000
+
+/// D0F2x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 PrefSupW:1 ; ///<
+    UINT32                                                  PprSupW:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                   NxSupW:1 ; ///<
+    UINT32                                                   GtSupW:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                                   IaSupW:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                                   PcSupW:1 ; ///<
+    UINT32                                                    HatsW:2 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x70_STRUCT;
+
+// **** D0F2x74 Register Definition ****
+// Address
+#define D0F2x74_ADDRESS                                         0x74
+
+// Type
+#define D0F2x74_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x74_PasMaxW_OFFSET                                  0
+#define D0F2x74_PasMaxW_WIDTH                                   4
+#define D0F2x74_PasMaxW_MASK                                    0xf
+#define D0F2x74_Reserved_31_4_OFFSET                            4
+#define D0F2x74_Reserved_31_4_WIDTH                             28
+#define D0F2x74_Reserved_31_4_MASK                              0xfffffff0
+
+/// D0F2x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  PasMaxW:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x74_STRUCT;
+
+// **** D0F2x78 Register Definition ****
+// Address
+#define D0F2x78_ADDRESS                                         0x78
+
+// Type
+#define D0F2x78_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2x78_Reserved_6_0_OFFSET                             0
+#define D0F2x78_Reserved_6_0_WIDTH                              7
+#define D0F2x78_Reserved_6_0_MASK                               0x7f
+#define D0F2x78_RngValidW_OFFSET                                7
+#define D0F2x78_RngValidW_WIDTH                                 1
+#define D0F2x78_RngValidW_MASK                                  0x80
+#define D0F2x78_BusNumberW_OFFSET                               8
+#define D0F2x78_BusNumberW_WIDTH                                8
+#define D0F2x78_BusNumberW_MASK                                 0xff00
+#define D0F2x78_FirstDeviceW_OFFSET                             16
+#define D0F2x78_FirstDeviceW_WIDTH                              8
+#define D0F2x78_FirstDeviceW_MASK                               0xff0000
+#define D0F2x78_LastDeviceW_OFFSET                              24
+#define D0F2x78_LastDeviceW_WIDTH                               8
+#define D0F2x78_LastDeviceW_MASK                                0xff000000
+
+/// D0F2x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_6_0:7 ; ///<
+    UINT32                                                RngValidW:1 ; ///<
+    UINT32                                               BusNumberW:8 ; ///<
+    UINT32                                             FirstDeviceW:8 ; ///<
+    UINT32                                              LastDeviceW:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2x78_STRUCT;
+
+// **** D0F2xF0 Register Definition ****
+// Address
+#define D0F2xF0_ADDRESS                                         0xf0
+
+// Type
+#define D0F2xF0_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xF0_L2cfgIndex_OFFSET                               0
+#define D0F2xF0_L2cfgIndex_WIDTH                                8
+#define D0F2xF0_L2cfgIndex_MASK                                 0xff
+#define D0F2xF0_L2cfgWrEn_OFFSET                                8
+#define D0F2xF0_L2cfgWrEn_WIDTH                                 1
+#define D0F2xF0_L2cfgWrEn_MASK                                  0x100
+#define D0F2xF0_Reserved_31_9_OFFSET                            9
+#define D0F2xF0_Reserved_31_9_WIDTH                             23
+#define D0F2xF0_Reserved_31_9_MASK                              0xfffffe00
+
+/// D0F2xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               L2cfgIndex:8 ; ///<
+    UINT32                                                L2cfgWrEn:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF0_STRUCT;
+
+// **** D0F2xF4 Register Definition ****
+// Address
+#define D0F2xF4_ADDRESS                                         0xf4
+
+// Type
+#define D0F2xF4_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xF4_L2cfgData_OFFSET                                0
+#define D0F2xF4_L2cfgData_WIDTH                                 32
+#define D0F2xF4_L2cfgData_MASK                                  0xffffffff
+
+/// D0F2xF4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L2cfgData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_STRUCT;
+
+// **** D0F2xF8 Register Definition ****
+// Address
+#define D0F2xF8_ADDRESS                                         0xf8
+
+// Type
+#define D0F2xF8_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xF8_L1cfgIndex_OFFSET                               0
+#define D0F2xF8_L1cfgIndex_WIDTH                                16
+#define D0F2xF8_L1cfgIndex_MASK                                 0xffff
+#define D0F2xF8_L1cfgSel_OFFSET                                 16
+#define D0F2xF8_L1cfgSel_WIDTH                                  4
+#define D0F2xF8_L1cfgSel_MASK                                   0xf0000
+#define D0F2xF8_Reserved_30_20_OFFSET                           20
+#define D0F2xF8_Reserved_30_20_WIDTH                            11
+#define D0F2xF8_Reserved_30_20_MASK                             0x7ff00000
+#define D0F2xF8_L1cfgEn_OFFSET                                  31
+#define D0F2xF8_L1cfgEn_WIDTH                                   1
+#define D0F2xF8_L1cfgEn_MASK                                    0x80000000
+
+/// D0F2xF8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               L1cfgIndex:16; ///<
+    UINT32                                                 L1cfgSel:4 ; ///<
+    UINT32                                           Reserved_30_20:11; ///<
+    UINT32                                                  L1cfgEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF8_STRUCT;
+
+// **** D0F2xFC Register Definition ****
+// Address
+#define D0F2xFC_ADDRESS                                         0xfc
+
+// Type
+#define D0F2xFC_TYPE                                            TYPE_D0F2
+// Field Data
+#define D0F2xFC_L1cfgData_OFFSET                                0
+#define D0F2xFC_L1cfgData_WIDTH                                 32
+#define D0F2xFC_L1cfgData_MASK                                  0xffffffff
+
+/// D0F2xFC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L1cfgData:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_STRUCT;
+
+// **** D18F0x00 Register Definition ****
+// Address
+#define D18F0x00_ADDRESS                                        0x0
+
+// Type
+#define D18F0x00_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x00_VendorID_OFFSET                                0
+#define D18F0x00_VendorID_WIDTH                                 16
+#define D18F0x00_VendorID_MASK                                  0xffff
+#define D18F0x00_DeviceID_OFFSET                                16
+#define D18F0x00_DeviceID_WIDTH                                 16
+#define D18F0x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x00_STRUCT;
+
+// **** D18F0x04 Register Definition ****
+// Address
+#define D18F0x04_ADDRESS                                        0x4
+
+// Type
+#define D18F0x04_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x04_Command_OFFSET                                 0
+#define D18F0x04_Command_WIDTH                                  16
+#define D18F0x04_Command_MASK                                   0xffff
+#define D18F0x04_Status_OFFSET                                  16
+#define D18F0x04_Status_WIDTH                                   16
+#define D18F0x04_Status_MASK                                    0xffff0000
+
+/// D18F0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x04_STRUCT;
+
+// **** D18F0x08 Register Definition ****
+// Address
+#define D18F0x08_ADDRESS                                        0x8
+
+// Type
+#define D18F0x08_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x08_RevID_OFFSET                                   0
+#define D18F0x08_RevID_WIDTH                                    8
+#define D18F0x08_RevID_MASK                                     0xff
+#define D18F0x08_ClassCode_OFFSET                               8
+#define D18F0x08_ClassCode_WIDTH                                24
+#define D18F0x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x08_STRUCT;
+
+// **** D18F0x0C Register Definition ****
+// Address
+#define D18F0x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F0x0C_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x0C_HeaderTypeReg_OFFSET                           0
+#define D18F0x0C_HeaderTypeReg_WIDTH                            32
+#define D18F0x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x0C_STRUCT;
+
+// **** D18F0x34 Register Definition ****
+// Address
+#define D18F0x34_ADDRESS                                        0x34
+
+// Type
+#define D18F0x34_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x34_CapPtr_OFFSET                                  0
+#define D18F0x34_CapPtr_WIDTH                                   8
+#define D18F0x34_CapPtr_MASK                                    0xff
+#define D18F0x34_Reserved_31_8_OFFSET                           8
+#define D18F0x34_Reserved_31_8_WIDTH                            24
+#define D18F0x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x34_STRUCT;
+
+// **** D18F0x40 Register Definition ****
+// Address
+#define D18F0x40_ADDRESS                                        0x40
+
+// Type
+#define D18F0x40_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x40_Reserved_31_0_OFFSET                           0
+#define D18F0x40_Reserved_31_0_WIDTH                            32
+#define D18F0x40_Reserved_31_0_MASK                             0xffffffff
+
+/// D18F0x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x40_STRUCT;
+
+// **** D18F0x60 Register Definition ****
+// Address
+#define D18F0x60_ADDRESS                                        0x60
+
+// Type
+#define D18F0x60_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x60_Reserved_15_0_OFFSET                           0
+#define D18F0x60_Reserved_15_0_WIDTH                            16
+#define D18F0x60_Reserved_15_0_MASK                             0xffff
+#define D18F0x60_CpuCnt_4_0__OFFSET                             16
+#define D18F0x60_CpuCnt_4_0__WIDTH                              5
+#define D18F0x60_CpuCnt_4_0__MASK                               0x1f0000
+#define D18F0x60_Reserved_31_21_OFFSET                          21
+#define D18F0x60_Reserved_31_21_WIDTH                           11
+#define D18F0x60_Reserved_31_21_MASK                            0xffe00000
+
+/// D18F0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                              CpuCnt_4_0_:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x60_STRUCT;
+
+// **** D18F0x64 Register Definition ****
+// Address
+#define D18F0x64_ADDRESS                                        0x64
+
+// Type
+#define D18F0x64_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x64_MctUnit_OFFSET                                 4
+#define D18F0x64_MctUnit_WIDTH                                  2
+#define D18F0x64_MctUnit_MASK                                   0x30
+#define D18F0x64_HbUnit_OFFSET                                  6
+#define D18F0x64_HbUnit_WIDTH                                   2
+#define D18F0x64_HbUnit_MASK                                    0xc0
+#define D18F0x64_Reserved_31_8_OFFSET                           8
+#define D18F0x64_Reserved_31_8_WIDTH                            24
+#define D18F0x64_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  CpuUnit:2 ; ///<
+    UINT32                                               ExtCpuUnit:2 ; ///<
+    UINT32                                                  MctUnit:2 ; ///<
+    UINT32                                                   HbUnit:2 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x64_STRUCT;
+
+// **** D18F0x68 Register Definition ****
+// Address
+#define D18F0x68_ADDRESS                                        0x68
+
+// Type
+#define D18F0x68_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x68_Reserved_3_0_OFFSET                            0
+#define D18F0x68_Reserved_3_0_WIDTH                             4
+#define D18F0x68_Reserved_3_0_MASK                              0xf
+#define D18F0x68_DisMTS_OFFSET                                  4
+#define D18F0x68_DisMTS_WIDTH                                   1
+#define D18F0x68_DisMTS_MASK                                    0x10
+#define D18F0x68_Reserved_5_5_OFFSET                            5
+#define D18F0x68_Reserved_5_5_WIDTH                             1
+#define D18F0x68_Reserved_5_5_MASK                              0x20
+#define D18F0x68_CPUReqPassPW_OFFSET                            6
+#define D18F0x68_CPUReqPassPW_WIDTH                             1
+#define D18F0x68_CPUReqPassPW_MASK                              0x40
+#define D18F0x68_CPURdRspPassPW_OFFSET                          7
+#define D18F0x68_CPURdRspPassPW_WIDTH                           1
+#define D18F0x68_CPURdRspPassPW_MASK                            0x80
+#define D18F0x68_DisPMemC_OFFSET                                8
+#define D18F0x68_DisPMemC_WIDTH                                 1
+#define D18F0x68_DisPMemC_MASK                                  0x100
+#define D18F0x68_DisRmtPMemC_OFFSET                             9
+#define D18F0x68_DisRmtPMemC_WIDTH                              1
+#define D18F0x68_DisRmtPMemC_MASK                               0x200
+#define D18F0x68_DisFillP_OFFSET                                10
+#define D18F0x68_DisFillP_WIDTH                                 1
+#define D18F0x68_DisFillP_MASK                                  0x400
+#define D18F0x68_RespPassPW_OFFSET                              11
+#define D18F0x68_RespPassPW_WIDTH                               1
+#define D18F0x68_RespPassPW_MASK                                0x800
+#define D18F0x68_Reserved_14_12_OFFSET                          12
+#define D18F0x68_Reserved_14_12_WIDTH                           3
+#define D18F0x68_Reserved_14_12_MASK                            0x7000
+#define D18F0x68_LimitCldtCfg_OFFSET                            15
+#define D18F0x68_LimitCldtCfg_WIDTH                             1
+#define D18F0x68_LimitCldtCfg_MASK                              0x8000
+#define D18F0x68_LintEn_OFFSET                                  16
+#define D18F0x68_LintEn_WIDTH                                   1
+#define D18F0x68_LintEn_MASK                                    0x10000
+#define D18F0x68_ApicExtBrdCst_OFFSET                           17
+#define D18F0x68_ApicExtBrdCst_WIDTH                            1
+#define D18F0x68_ApicExtBrdCst_MASK                             0x20000
+#define D18F0x68_ApicExtId_OFFSET                               18
+#define D18F0x68_ApicExtId_WIDTH                                1
+#define D18F0x68_ApicExtId_MASK                                 0x40000
+#define D18F0x68_ApicExtSpur_OFFSET                             19
+#define D18F0x68_ApicExtSpur_WIDTH                              1
+#define D18F0x68_ApicExtSpur_MASK                               0x80000
+#define D18F0x68_SeqIdSrcNodeEn_OFFSET                          20
+#define D18F0x68_SeqIdSrcNodeEn_WIDTH                           1
+#define D18F0x68_SeqIdSrcNodeEn_MASK                            0x100000
+#define D18F0x68_DsNpReqLmt_OFFSET                              21
+#define D18F0x68_DsNpReqLmt_WIDTH                               2
+#define D18F0x68_DsNpReqLmt_MASK                                0x600000
+#define D18F0x68_Reserved_31_23_OFFSET                          23
+#define D18F0x68_Reserved_31_23_WIDTH                           9
+#define D18F0x68_Reserved_31_23_MASK                            0xff800000
+
+/// D18F0x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                   DisMTS:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                             CPUReqPassPW:1 ; ///<
+    UINT32                                           CPURdRspPassPW:1 ; ///<
+    UINT32                                                 DisPMemC:1 ; ///<
+    UINT32                                              DisRmtPMemC:1 ; ///<
+    UINT32                                                 DisFillP:1 ; ///<
+    UINT32                                               RespPassPW:1 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                             LimitCldtCfg:1 ; ///<
+    UINT32                                                   LintEn:1 ; ///<
+    UINT32                                            ApicExtBrdCst:1 ; ///<
+    UINT32                                                ApicExtId:1 ; ///<
+    UINT32                                              ApicExtSpur:1 ; ///<
+    UINT32                                           SeqIdSrcNodeEn:1 ; ///<
+    UINT32                                               DsNpReqLmt:2 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x68_STRUCT;
+
+// **** D18F0x6C Register Definition ****
+// Address
+#define D18F0x6C_ADDRESS                                        0x6c
+
+// Type
+#define D18F0x6C_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x6C_RouteTblDis_OFFSET                             0
+#define D18F0x6C_RouteTblDis_WIDTH                              1
+#define D18F0x6C_RouteTblDis_MASK                               0x1
+#define D18F0x6C_Reserved_3_1_OFFSET                            1
+#define D18F0x6C_Reserved_3_1_WIDTH                             3
+#define D18F0x6C_Reserved_3_1_MASK                              0xe
+#define D18F0x6C_ColdRstDet_OFFSET                              4
+#define D18F0x6C_ColdRstDet_WIDTH                               1
+#define D18F0x6C_ColdRstDet_MASK                                0x10
+#define D18F0x6C_BiosRstDet_0__OFFSET                           5
+#define D18F0x6C_BiosRstDet_0__WIDTH                            1
+#define D18F0x6C_BiosRstDet_0__MASK                             0x20
+#define D18F0x6C_InitDet_OFFSET                                 6
+#define D18F0x6C_InitDet_WIDTH                                  1
+#define D18F0x6C_InitDet_MASK                                   0x40
+#define D18F0x6C_Reserved_8_7_OFFSET                            7
+#define D18F0x6C_Reserved_8_7_WIDTH                             2
+#define D18F0x6C_Reserved_8_7_MASK                              0x180
+#define D18F0x6C_BiosRstDet_2_1__OFFSET                         9
+#define D18F0x6C_BiosRstDet_2_1__WIDTH                          2
+#define D18F0x6C_BiosRstDet_2_1__MASK                           0x600
+#define D18F0x6C_Reserved_26_11_OFFSET                          11
+#define D18F0x6C_Reserved_26_11_WIDTH                           16
+#define D18F0x6C_Reserved_26_11_MASK                            0x7fff800
+#define D18F0x6C_ApplyIsocModeEnNow_OFFSET                      27
+#define D18F0x6C_ApplyIsocModeEnNow_WIDTH                       1
+#define D18F0x6C_ApplyIsocModeEnNow_MASK                        0x8000000
+#define D18F0x6C_RlsIntFullTokCntImm_OFFSET                     28
+#define D18F0x6C_RlsIntFullTokCntImm_WIDTH                      1
+#define D18F0x6C_RlsIntFullTokCntImm_MASK                       0x10000000
+#define D18F0x6C_Reserved_29_29_OFFSET                          29
+#define D18F0x6C_Reserved_29_29_WIDTH                           1
+#define D18F0x6C_Reserved_29_29_MASK                            0x20000000
+#define D18F0x6C_RlsLnkFullTokCntImm_OFFSET                     30
+#define D18F0x6C_RlsLnkFullTokCntImm_WIDTH                      1
+#define D18F0x6C_RlsLnkFullTokCntImm_MASK                       0x40000000
+#define D18F0x6C_Reserved_31_31_OFFSET                          31
+#define D18F0x6C_Reserved_31_31_WIDTH                           1
+#define D18F0x6C_Reserved_31_31_MASK                            0x80000000
+
+/// D18F0x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              RouteTblDis:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                               ColdRstDet:1 ; ///<
+    UINT32                                            BiosRstDet_0_:1 ; ///<
+    UINT32                                                  InitDet:1 ; ///<
+    UINT32                                             Reserved_8_7:2 ; ///<
+    UINT32                                          BiosRstDet_2_1_:2 ; ///<
+    UINT32                                           Reserved_26_11:16; ///<
+    UINT32                                       ApplyIsocModeEnNow:1 ; ///<
+    UINT32                                      RlsIntFullTokCntImm:1 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                      RlsLnkFullTokCntImm:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x6C_STRUCT;
+
+// **** D18F0x84 Register Definition ****
+// Address
+#define D18F0x84_ADDRESS                                        0x84
+
+// Type
+#define D18F0x84_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x84_Reserved_3_0_OFFSET                            0
+#define D18F0x84_Reserved_3_0_WIDTH                             4
+#define D18F0x84_Reserved_3_0_MASK                              0xf
+#define D18F0x84_LinkFail_OFFSET                                4
+#define D18F0x84_LinkFail_WIDTH                                 1
+#define D18F0x84_LinkFail_MASK                                  0x10
+#define D18F0x84_Reserved_5_5_OFFSET                            5
+#define D18F0x84_Reserved_5_5_WIDTH                             1
+#define D18F0x84_Reserved_5_5_MASK                              0x20
+#define D18F0x84_Reserved_11_6_OFFSET                           6
+#define D18F0x84_Reserved_11_6_WIDTH                            6
+#define D18F0x84_Reserved_11_6_MASK                             0xfc0
+#define D18F0x84_IsocEn_OFFSET                                  12
+#define D18F0x84_IsocEn_WIDTH                                   1
+#define D18F0x84_IsocEn_MASK                                    0x1000
+#define D18F0x84_Reserved_31_13_OFFSET                          13
+#define D18F0x84_Reserved_31_13_WIDTH                           19
+#define D18F0x84_Reserved_31_13_MASK                            0xffffe000
+
+/// D18F0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                 LinkFail:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                                   IsocEn:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x84_STRUCT;
+
+// **** D18F0x90 Register Definition ****
+// Address
+#define D18F0x90_ADDRESS                                        0x90
+
+// Type
+#define D18F0x90_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x90_NpReqCmd_OFFSET                                0
+#define D18F0x90_NpReqCmd_WIDTH                                 5
+#define D18F0x90_NpReqCmd_MASK                                  0x1f
+#define D18F0x90_PReq_OFFSET                                    5
+#define D18F0x90_PReq_WIDTH                                     3
+#define D18F0x90_PReq_MASK                                      0xe0
+#define D18F0x90_RspCmd_OFFSET                                  8
+#define D18F0x90_RspCmd_WIDTH                                   4
+#define D18F0x90_RspCmd_MASK                                    0xf00
+#define D18F0x90_ProbeCmd_OFFSET                                12
+#define D18F0x90_ProbeCmd_WIDTH                                 4
+#define D18F0x90_ProbeCmd_MASK                                  0xf000
+#define D18F0x90_NpReqData_OFFSET                               16
+#define D18F0x90_NpReqData_WIDTH                                2
+#define D18F0x90_NpReqData_MASK                                 0x30000
+#define D18F0x90_RspData_OFFSET                                 18
+#define D18F0x90_RspData_WIDTH                                  2
+#define D18F0x90_RspData_MASK                                   0xc0000
+#define D18F0x90_FreeCmd_OFFSET                                 20
+#define D18F0x90_FreeCmd_WIDTH                                  5
+#define D18F0x90_FreeCmd_MASK                                   0x1f00000
+#define D18F0x90_FreeData_OFFSET                                25
+#define D18F0x90_FreeData_WIDTH                                 3
+#define D18F0x90_FreeData_MASK                                  0xe000000
+#define D18F0x90_Reserved_30_28_OFFSET                          28
+#define D18F0x90_Reserved_30_28_WIDTH                           3
+#define D18F0x90_Reserved_30_28_MASK                            0x70000000
+#define D18F0x90_LockBc_OFFSET                                  31
+#define D18F0x90_LockBc_WIDTH                                   1
+#define D18F0x90_LockBc_MASK                                    0x80000000
+
+/// D18F0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 NpReqCmd:5 ; ///<
+    UINT32                                                     PReq:3 ; ///<
+    UINT32                                                   RspCmd:4 ; ///<
+    UINT32                                                 ProbeCmd:4 ; ///<
+    UINT32                                                NpReqData:2 ; ///<
+    UINT32                                                  RspData:2 ; ///<
+    UINT32                                                  FreeCmd:5 ; ///<
+    UINT32                                                 FreeData:3 ; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                                   LockBc:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x90_STRUCT;
+
+// **** D18F0x94 Register Definition ****
+// Address
+#define D18F0x94_ADDRESS                                        0x94
+
+// Type
+#define D18F0x94_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x94_Reserved_7_0_OFFSET                            0
+#define D18F0x94_Reserved_7_0_WIDTH                             8
+#define D18F0x94_Reserved_7_0_MASK                              0xff
+#define D18F0x94_SecBusNum_OFFSET                               8
+#define D18F0x94_SecBusNum_WIDTH                                8
+#define D18F0x94_SecBusNum_MASK                                 0xff00
+#define D18F0x94_IsocNpReqCmd_OFFSET                            16
+#define D18F0x94_IsocNpReqCmd_WIDTH                             3
+#define D18F0x94_IsocNpReqCmd_MASK                              0x70000
+#define D18F0x94_IsocPReq_OFFSET                                19
+#define D18F0x94_IsocPReq_WIDTH                                 3
+#define D18F0x94_IsocPReq_MASK                                  0x380000
+#define D18F0x94_IsocRspCmd_OFFSET                              22
+#define D18F0x94_IsocRspCmd_WIDTH                               3
+#define D18F0x94_IsocRspCmd_MASK                                0x1c00000
+#define D18F0x94_IsocNpReqData_OFFSET                           25
+#define D18F0x94_IsocNpReqData_WIDTH                            2
+#define D18F0x94_IsocNpReqData_MASK                             0x6000000
+#define D18F0x94_IsocRspData_OFFSET                             27
+#define D18F0x94_IsocRspData_WIDTH                              2
+#define D18F0x94_IsocRspData_MASK                               0x18000000
+#define D18F0x94_Reserved_31_29_OFFSET                          29
+#define D18F0x94_Reserved_31_29_WIDTH                           3
+#define D18F0x94_Reserved_31_29_MASK                            0xe0000000
+
+/// D18F0x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                SecBusNum:8 ; ///<
+    UINT32                                             IsocNpReqCmd:3 ; ///<
+    UINT32                                                 IsocPReq:3 ; ///<
+    UINT32                                               IsocRspCmd:3 ; ///<
+    UINT32                                            IsocNpReqData:2 ; ///<
+    UINT32                                              IsocRspData:2 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x94_STRUCT;
+
+// **** D18F0x98 Register Definition ****
+// Address
+#define D18F0x98_ADDRESS                                        0x98
+
+// Type
+#define D18F0x98_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x98_Reserved_0_0_OFFSET                            0
+#define D18F0x98_Reserved_0_0_WIDTH                             1
+#define D18F0x98_Reserved_0_0_MASK                              0x1
+#define D18F0x98_Reserved_1_1_OFFSET                            1
+#define D18F0x98_Reserved_1_1_WIDTH                             1
+#define D18F0x98_Reserved_1_1_MASK                              0x2
+#define D18F0x98_Reserved_2_2_OFFSET                            2
+#define D18F0x98_Reserved_2_2_WIDTH                             1
+#define D18F0x98_Reserved_2_2_MASK                              0x4
+#define D18F0x98_Reserved_4_3_OFFSET                            3
+#define D18F0x98_Reserved_4_3_WIDTH                             2
+#define D18F0x98_Reserved_4_3_MASK                              0x18
+#define D18F0x98_PciEligible_OFFSET                             5
+#define D18F0x98_PciEligible_WIDTH                              1
+#define D18F0x98_PciEligible_MASK                               0x20
+#define D18F0x98_Reserved_31_6_OFFSET                           6
+#define D18F0x98_Reserved_31_6_WIDTH                            26
+#define D18F0x98_Reserved_31_6_MASK                             0xffffffc0
+
+/// D18F0x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                              PciEligible:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x98_STRUCT;
+
+// **** D18F0x9C Register Definition ****
+// Address
+#define D18F0x9C_ADDRESS                                        0x9c
+
+// Type
+#define D18F0x9C_TYPE                                           TYPE_D18F0
+// Field Data
+#define D18F0x9C_Reserved_0_0_OFFSET                            0
+#define D18F0x9C_Reserved_0_0_WIDTH                             1
+#define D18F0x9C_Reserved_0_0_MASK                              0x1
+#define D18F0x9C_Reserved_15_1_OFFSET                           1
+#define D18F0x9C_Reserved_15_1_WIDTH                            15
+#define D18F0x9C_Reserved_15_1_MASK                             0xfffe
+#define D18F0x9C_Reserved_31_16_OFFSET                          16
+#define D18F0x9C_Reserved_31_16_WIDTH                           16
+#define D18F0x9C_Reserved_31_16_MASK                            0xffff0000
+
+/// D18F0x9C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                            Reserved_15_1:15; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x9C_STRUCT;
+
+// **** D18F0x110 Register Definition ****
+// Address
+#define D18F0x110_ADDRESS                                       0x110
+
+// Type
+#define D18F0x110_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x110_Reserved_0_0_OFFSET                           0
+#define D18F0x110_Reserved_0_0_WIDTH                            1
+#define D18F0x110_Reserved_0_0_MASK                             0x1
+#define D18F0x110_Reserved_1_1_OFFSET                           1
+#define D18F0x110_Reserved_1_1_WIDTH                            1
+#define D18F0x110_Reserved_1_1_MASK                             0x2
+#define D18F0x110_ClumpEn_OFFSET                                2
+#define D18F0x110_ClumpEn_WIDTH                                 30
+#define D18F0x110_ClumpEn_MASK                                  0xfffffffc
+
+/// D18F0x110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                  ClumpEn:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x110_STRUCT;
+
+// **** D18F0x16C Register Definition ****
+// Address
+#define D18F0x16C_ADDRESS                                       0x16c
+
+// Type
+#define D18F0x16C_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x16C_Reserved_31_0_OFFSET                          0
+#define D18F0x16C_Reserved_31_0_WIDTH                           32
+#define D18F0x16C_Reserved_31_0_MASK                            0xffffffff
+
+/// D18F0x16C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x16C_STRUCT;
+
+// **** D18F0x170 Register Definition ****
+// Address
+#define D18F0x170_ADDRESS                                       0x170
+
+// Type
+#define D18F0x170_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x170_Reserved_31_0_OFFSET                          0
+#define D18F0x170_Reserved_31_0_WIDTH                           32
+#define D18F0x170_Reserved_31_0_MASK                            0xffffffff
+
+/// D18F0x170
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x170_STRUCT;
+
+// **** D18F0x1A0 Register Definition ****
+// Address
+#define D18F0x1A0_ADDRESS                                       0x1a0
+
+// Type
+#define D18F0x1A0_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x1A0_InitComplete_OFFSET                           0
+#define D18F0x1A0_InitComplete_WIDTH                            2
+#define D18F0x1A0_InitComplete_MASK                             0x3
+#define D18F0x1A0_Reserved_30_2_OFFSET                          2
+#define D18F0x1A0_Reserved_30_2_WIDTH                           29
+#define D18F0x1A0_Reserved_30_2_MASK                            0x7ffffffc
+#define D18F0x1A0_InitStatusValid_OFFSET                        31
+#define D18F0x1A0_InitStatusValid_WIDTH                         1
+#define D18F0x1A0_InitStatusValid_MASK                          0x80000000
+
+/// D18F0x1A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             InitComplete:2 ; ///<
+    UINT32                                            Reserved_30_2:29; ///<
+    UINT32                                          InitStatusValid:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x1A0_STRUCT;
+
+// **** D18F0x1DC Register Definition ****
+// Address
+#define D18F0x1DC_ADDRESS                                       0x1dc
+
+// Type
+#define D18F0x1DC_TYPE                                          TYPE_D18F0
+// Field Data
+#define D18F0x1DC_Reserved_0_0_OFFSET                           0
+#define D18F0x1DC_Reserved_0_0_WIDTH                            1
+#define D18F0x1DC_Reserved_0_0_MASK                             0x1
+#define D18F0x1DC_CpuEn_OFFSET                                  1
+#define D18F0x1DC_CpuEn_WIDTH                                   7
+#define D18F0x1DC_CpuEn_MASK                                    0xfe
+#define D18F0x1DC_Reserved_31_8_OFFSET                          8
+#define D18F0x1DC_Reserved_31_8_WIDTH                           24
+#define D18F0x1DC_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F0x1DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                    CpuEn:7 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F0x1DC_STRUCT;
+
+// **** D18F1x00 Register Definition ****
+// Address
+#define D18F1x00_ADDRESS                                        0x0
+
+// Type
+#define D18F1x00_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x00_VendorID_OFFSET                                0
+#define D18F1x00_VendorID_WIDTH                                 16
+#define D18F1x00_VendorID_MASK                                  0xffff
+#define D18F1x00_DeviceID_OFFSET                                16
+#define D18F1x00_DeviceID_WIDTH                                 16
+#define D18F1x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F1x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x00_STRUCT;
+
+// **** D18F1x08 Register Definition ****
+// Address
+#define D18F1x08_ADDRESS                                        0x8
+
+// Type
+#define D18F1x08_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x08_RevID_OFFSET                                   0
+#define D18F1x08_RevID_WIDTH                                    8
+#define D18F1x08_RevID_MASK                                     0xff
+#define D18F1x08_ClassCode_OFFSET                               8
+#define D18F1x08_ClassCode_WIDTH                                24
+#define D18F1x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F1x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x08_STRUCT;
+
+// **** D18F1x0C Register Definition ****
+// Address
+#define D18F1x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F1x0C_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x0C_HeaderTypeReg_OFFSET                           0
+#define D18F1x0C_HeaderTypeReg_WIDTH                            32
+#define D18F1x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F1x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x0C_STRUCT;
+
+// **** D18F1x40 Register Definition ****
+// Address
+#define D18F1x40_ADDRESS                                        0x40
+
+// Type
+#define D18F1x40_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x40_RE_OFFSET                                      0
+#define D18F1x40_RE_WIDTH                                       1
+#define D18F1x40_RE_MASK                                        0x1
+#define D18F1x40_WE_OFFSET                                      1
+#define D18F1x40_WE_WIDTH                                       1
+#define D18F1x40_WE_MASK                                        0x2
+#define D18F1x40_Reserved_15_2_OFFSET                           2
+#define D18F1x40_Reserved_15_2_WIDTH                            14
+#define D18F1x40_Reserved_15_2_MASK                             0xfffc
+#define D18F1x40_DramBase_39_24__OFFSET                         16
+#define D18F1x40_DramBase_39_24__WIDTH                          16
+#define D18F1x40_DramBase_39_24__MASK                           0xffff0000
+
+/// D18F1x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                            Reserved_15_2:14; ///<
+    UINT32                                          DramBase_39_24_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x40_STRUCT;
+
+// **** D18F1x44 Register Definition ****
+// Address
+#define D18F1x44_ADDRESS                                        0x44
+
+// Type
+#define D18F1x44_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x44_DstNode_OFFSET                                 0
+#define D18F1x44_DstNode_WIDTH                                  3
+#define D18F1x44_DstNode_MASK                                   0x7
+#define D18F1x44_Reserved_7_3_OFFSET                            3
+#define D18F1x44_Reserved_7_3_WIDTH                             5
+#define D18F1x44_Reserved_7_3_MASK                              0xf8
+#define D18F1x44_Reserved_10_8_OFFSET                           8
+#define D18F1x44_Reserved_10_8_WIDTH                            3
+#define D18F1x44_Reserved_10_8_MASK                             0x700
+#define D18F1x44_Reserved_15_11_OFFSET                          11
+#define D18F1x44_Reserved_15_11_WIDTH                           5
+#define D18F1x44_Reserved_15_11_MASK                            0xf800
+#define D18F1x44_DramLimit_39_24__OFFSET                        16
+#define D18F1x44_DramLimit_39_24__WIDTH                         16
+#define D18F1x44_DramLimit_39_24__MASK                          0xffff0000
+
+/// D18F1x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                            Reserved_10_8:3 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                         DramLimit_39_24_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x44_STRUCT;
+
+// **** D18F1x80 Register Definition ****
+// Address
+#define D18F1x80_ADDRESS                                        0x80
+
+// Type
+#define D18F1x80_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x80_RE_OFFSET                                      0
+#define D18F1x80_RE_WIDTH                                       1
+#define D18F1x80_RE_MASK                                        0x1
+#define D18F1x80_WE_OFFSET                                      1
+#define D18F1x80_WE_WIDTH                                       1
+#define D18F1x80_WE_MASK                                        0x2
+#define D18F1x80_Reserved_2_2_OFFSET                            2
+#define D18F1x80_Reserved_2_2_WIDTH                             1
+#define D18F1x80_Reserved_2_2_MASK                              0x4
+#define D18F1x80_Lock_OFFSET                                    3
+#define D18F1x80_Lock_WIDTH                                     1
+#define D18F1x80_Lock_MASK                                      0x8
+#define D18F1x80_Reserved_7_4_OFFSET                            4
+#define D18F1x80_Reserved_7_4_WIDTH                             4
+#define D18F1x80_Reserved_7_4_MASK                              0xf0
+#define D18F1x80_MMIOBase_39_16__OFFSET                         8
+#define D18F1x80_MMIOBase_39_16__WIDTH                          24
+#define D18F1x80_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x80_STRUCT;
+
+// **** D18F1x84 Register Definition ****
+// Address
+#define D18F1x84_ADDRESS                                        0x84
+
+// Type
+#define D18F1x84_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x84_DstNode_OFFSET                                 0
+#define D18F1x84_DstNode_WIDTH                                  3
+#define D18F1x84_DstNode_MASK                                   0x7
+#define D18F1x84_Reserved_3_3_OFFSET                            3
+#define D18F1x84_Reserved_3_3_WIDTH                             1
+#define D18F1x84_Reserved_3_3_MASK                              0x8
+#define D18F1x84_DstLink_OFFSET                                 4
+#define D18F1x84_DstLink_WIDTH                                  2
+#define D18F1x84_DstLink_MASK                                   0x30
+#define D18F1x84_DstSubLink_OFFSET                              6
+#define D18F1x84_DstSubLink_WIDTH                               1
+#define D18F1x84_DstSubLink_MASK                                0x40
+#define D18F1x84_NP_OFFSET                                      7
+#define D18F1x84_NP_WIDTH                                       1
+#define D18F1x84_NP_MASK                                        0x80
+#define D18F1x84_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x84_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x84_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x84_STRUCT;
+
+// **** D18F1x88 Register Definition ****
+// Address
+#define D18F1x88_ADDRESS                                        0x88
+
+// Type
+#define D18F1x88_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x88_RE_OFFSET                                      0
+#define D18F1x88_RE_WIDTH                                       1
+#define D18F1x88_RE_MASK                                        0x1
+#define D18F1x88_WE_OFFSET                                      1
+#define D18F1x88_WE_WIDTH                                       1
+#define D18F1x88_WE_MASK                                        0x2
+#define D18F1x88_Reserved_2_2_OFFSET                            2
+#define D18F1x88_Reserved_2_2_WIDTH                             1
+#define D18F1x88_Reserved_2_2_MASK                              0x4
+#define D18F1x88_Lock_OFFSET                                    3
+#define D18F1x88_Lock_WIDTH                                     1
+#define D18F1x88_Lock_MASK                                      0x8
+#define D18F1x88_Reserved_7_4_OFFSET                            4
+#define D18F1x88_Reserved_7_4_WIDTH                             4
+#define D18F1x88_Reserved_7_4_MASK                              0xf0
+#define D18F1x88_MMIOBase_39_16__OFFSET                         8
+#define D18F1x88_MMIOBase_39_16__WIDTH                          24
+#define D18F1x88_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x88_STRUCT;
+
+// **** D18F1x8C Register Definition ****
+// Address
+#define D18F1x8C_ADDRESS                                        0x8c
+
+// Type
+#define D18F1x8C_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x8C_DstNode_OFFSET                                 0
+#define D18F1x8C_DstNode_WIDTH                                  3
+#define D18F1x8C_DstNode_MASK                                   0x7
+#define D18F1x8C_Reserved_3_3_OFFSET                            3
+#define D18F1x8C_Reserved_3_3_WIDTH                             1
+#define D18F1x8C_Reserved_3_3_MASK                              0x8
+#define D18F1x8C_DstLink_OFFSET                                 4
+#define D18F1x8C_DstLink_WIDTH                                  2
+#define D18F1x8C_DstLink_MASK                                   0x30
+#define D18F1x8C_DstSubLink_OFFSET                              6
+#define D18F1x8C_DstSubLink_WIDTH                               1
+#define D18F1x8C_DstSubLink_MASK                                0x40
+#define D18F1x8C_NP_OFFSET                                      7
+#define D18F1x8C_NP_WIDTH                                       1
+#define D18F1x8C_NP_MASK                                        0x80
+#define D18F1x8C_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x8C_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x8C_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x8C_STRUCT;
+
+// **** D18F1x90 Register Definition ****
+// Address
+#define D18F1x90_ADDRESS                                        0x90
+
+// Type
+#define D18F1x90_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x90_RE_OFFSET                                      0
+#define D18F1x90_RE_WIDTH                                       1
+#define D18F1x90_RE_MASK                                        0x1
+#define D18F1x90_WE_OFFSET                                      1
+#define D18F1x90_WE_WIDTH                                       1
+#define D18F1x90_WE_MASK                                        0x2
+#define D18F1x90_Reserved_2_2_OFFSET                            2
+#define D18F1x90_Reserved_2_2_WIDTH                             1
+#define D18F1x90_Reserved_2_2_MASK                              0x4
+#define D18F1x90_Lock_OFFSET                                    3
+#define D18F1x90_Lock_WIDTH                                     1
+#define D18F1x90_Lock_MASK                                      0x8
+#define D18F1x90_Reserved_7_4_OFFSET                            4
+#define D18F1x90_Reserved_7_4_WIDTH                             4
+#define D18F1x90_Reserved_7_4_MASK                              0xf0
+#define D18F1x90_MMIOBase_39_16__OFFSET                         8
+#define D18F1x90_MMIOBase_39_16__WIDTH                          24
+#define D18F1x90_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x90_STRUCT;
+
+// **** D18F1x94 Register Definition ****
+// Address
+#define D18F1x94_ADDRESS                                        0x94
+
+// Type
+#define D18F1x94_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x94_DstNode_OFFSET                                 0
+#define D18F1x94_DstNode_WIDTH                                  3
+#define D18F1x94_DstNode_MASK                                   0x7
+#define D18F1x94_Reserved_3_3_OFFSET                            3
+#define D18F1x94_Reserved_3_3_WIDTH                             1
+#define D18F1x94_Reserved_3_3_MASK                              0x8
+#define D18F1x94_DstLink_OFFSET                                 4
+#define D18F1x94_DstLink_WIDTH                                  2
+#define D18F1x94_DstLink_MASK                                   0x30
+#define D18F1x94_DstSubLink_OFFSET                              6
+#define D18F1x94_DstSubLink_WIDTH                               1
+#define D18F1x94_DstSubLink_MASK                                0x40
+#define D18F1x94_NP_OFFSET                                      7
+#define D18F1x94_NP_WIDTH                                       1
+#define D18F1x94_NP_MASK                                        0x80
+#define D18F1x94_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x94_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x94_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x94_STRUCT;
+
+// **** D18F1x98 Register Definition ****
+// Address
+#define D18F1x98_ADDRESS                                        0x98
+
+// Type
+#define D18F1x98_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x98_RE_OFFSET                                      0
+#define D18F1x98_RE_WIDTH                                       1
+#define D18F1x98_RE_MASK                                        0x1
+#define D18F1x98_WE_OFFSET                                      1
+#define D18F1x98_WE_WIDTH                                       1
+#define D18F1x98_WE_MASK                                        0x2
+#define D18F1x98_Reserved_2_2_OFFSET                            2
+#define D18F1x98_Reserved_2_2_WIDTH                             1
+#define D18F1x98_Reserved_2_2_MASK                              0x4
+#define D18F1x98_Lock_OFFSET                                    3
+#define D18F1x98_Lock_WIDTH                                     1
+#define D18F1x98_Lock_MASK                                      0x8
+#define D18F1x98_Reserved_7_4_OFFSET                            4
+#define D18F1x98_Reserved_7_4_WIDTH                             4
+#define D18F1x98_Reserved_7_4_MASK                              0xf0
+#define D18F1x98_MMIOBase_39_16__OFFSET                         8
+#define D18F1x98_MMIOBase_39_16__WIDTH                          24
+#define D18F1x98_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1x98
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x98_STRUCT;
+
+// **** D18F1x9C Register Definition ****
+// Address
+#define D18F1x9C_ADDRESS                                        0x9c
+
+// Type
+#define D18F1x9C_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1x9C_DstNode_OFFSET                                 0
+#define D18F1x9C_DstNode_WIDTH                                  3
+#define D18F1x9C_DstNode_MASK                                   0x7
+#define D18F1x9C_Reserved_3_3_OFFSET                            3
+#define D18F1x9C_Reserved_3_3_WIDTH                             1
+#define D18F1x9C_Reserved_3_3_MASK                              0x8
+#define D18F1x9C_DstLink_OFFSET                                 4
+#define D18F1x9C_DstLink_WIDTH                                  2
+#define D18F1x9C_DstLink_MASK                                   0x30
+#define D18F1x9C_DstSubLink_OFFSET                              6
+#define D18F1x9C_DstSubLink_WIDTH                               1
+#define D18F1x9C_DstSubLink_MASK                                0x40
+#define D18F1x9C_NP_OFFSET                                      7
+#define D18F1x9C_NP_WIDTH                                       1
+#define D18F1x9C_NP_MASK                                        0x80
+#define D18F1x9C_MMIOLimit_39_16__OFFSET                        8
+#define D18F1x9C_MMIOLimit_39_16__WIDTH                         24
+#define D18F1x9C_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1x9C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x9C_STRUCT;
+
+// **** D18F1xA0 Register Definition ****
+// Address
+#define D18F1xA0_ADDRESS                                        0xa0
+
+// Type
+#define D18F1xA0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xA0_RE_OFFSET                                      0
+#define D18F1xA0_RE_WIDTH                                       1
+#define D18F1xA0_RE_MASK                                        0x1
+#define D18F1xA0_WE_OFFSET                                      1
+#define D18F1xA0_WE_WIDTH                                       1
+#define D18F1xA0_WE_MASK                                        0x2
+#define D18F1xA0_Reserved_2_2_OFFSET                            2
+#define D18F1xA0_Reserved_2_2_WIDTH                             1
+#define D18F1xA0_Reserved_2_2_MASK                              0x4
+#define D18F1xA0_Lock_OFFSET                                    3
+#define D18F1xA0_Lock_WIDTH                                     1
+#define D18F1xA0_Lock_MASK                                      0x8
+#define D18F1xA0_Reserved_7_4_OFFSET                            4
+#define D18F1xA0_Reserved_7_4_WIDTH                             4
+#define D18F1xA0_Reserved_7_4_MASK                              0xf0
+#define D18F1xA0_MMIOBase_39_16__OFFSET                         8
+#define D18F1xA0_MMIOBase_39_16__WIDTH                          24
+#define D18F1xA0_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xA0_STRUCT;
+
+// **** D18F1xA4 Register Definition ****
+// Address
+#define D18F1xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F1xA4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xA4_DstNode_OFFSET                                 0
+#define D18F1xA4_DstNode_WIDTH                                  3
+#define D18F1xA4_DstNode_MASK                                   0x7
+#define D18F1xA4_Reserved_3_3_OFFSET                            3
+#define D18F1xA4_Reserved_3_3_WIDTH                             1
+#define D18F1xA4_Reserved_3_3_MASK                              0x8
+#define D18F1xA4_DstLink_OFFSET                                 4
+#define D18F1xA4_DstLink_WIDTH                                  2
+#define D18F1xA4_DstLink_MASK                                   0x30
+#define D18F1xA4_DstSubLink_OFFSET                              6
+#define D18F1xA4_DstSubLink_WIDTH                               1
+#define D18F1xA4_DstSubLink_MASK                                0x40
+#define D18F1xA4_NP_OFFSET                                      7
+#define D18F1xA4_NP_WIDTH                                       1
+#define D18F1xA4_NP_MASK                                        0x80
+#define D18F1xA4_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xA4_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xA4_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xA4_STRUCT;
+
+// **** D18F1xA8 Register Definition ****
+// Address
+#define D18F1xA8_ADDRESS                                        0xa8
+
+// Type
+#define D18F1xA8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xA8_RE_OFFSET                                      0
+#define D18F1xA8_RE_WIDTH                                       1
+#define D18F1xA8_RE_MASK                                        0x1
+#define D18F1xA8_WE_OFFSET                                      1
+#define D18F1xA8_WE_WIDTH                                       1
+#define D18F1xA8_WE_MASK                                        0x2
+#define D18F1xA8_Reserved_2_2_OFFSET                            2
+#define D18F1xA8_Reserved_2_2_WIDTH                             1
+#define D18F1xA8_Reserved_2_2_MASK                              0x4
+#define D18F1xA8_Lock_OFFSET                                    3
+#define D18F1xA8_Lock_WIDTH                                     1
+#define D18F1xA8_Lock_MASK                                      0x8
+#define D18F1xA8_Reserved_7_4_OFFSET                            4
+#define D18F1xA8_Reserved_7_4_WIDTH                             4
+#define D18F1xA8_Reserved_7_4_MASK                              0xf0
+#define D18F1xA8_MMIOBase_39_16__OFFSET                         8
+#define D18F1xA8_MMIOBase_39_16__WIDTH                          24
+#define D18F1xA8_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xA8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xA8_STRUCT;
+
+// **** D18F1xAC Register Definition ****
+// Address
+#define D18F1xAC_ADDRESS                                        0xac
+
+// Type
+#define D18F1xAC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xAC_DstNode_OFFSET                                 0
+#define D18F1xAC_DstNode_WIDTH                                  3
+#define D18F1xAC_DstNode_MASK                                   0x7
+#define D18F1xAC_Reserved_3_3_OFFSET                            3
+#define D18F1xAC_Reserved_3_3_WIDTH                             1
+#define D18F1xAC_Reserved_3_3_MASK                              0x8
+#define D18F1xAC_DstLink_OFFSET                                 4
+#define D18F1xAC_DstLink_WIDTH                                  2
+#define D18F1xAC_DstLink_MASK                                   0x30
+#define D18F1xAC_DstSubLink_OFFSET                              6
+#define D18F1xAC_DstSubLink_WIDTH                               1
+#define D18F1xAC_DstSubLink_MASK                                0x40
+#define D18F1xAC_NP_OFFSET                                      7
+#define D18F1xAC_NP_WIDTH                                       1
+#define D18F1xAC_NP_MASK                                        0x80
+#define D18F1xAC_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xAC_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xAC_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xAC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xAC_STRUCT;
+
+// **** D18F1xB0 Register Definition ****
+// Address
+#define D18F1xB0_ADDRESS                                        0xb0
+
+// Type
+#define D18F1xB0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xB0_RE_OFFSET                                      0
+#define D18F1xB0_RE_WIDTH                                       1
+#define D18F1xB0_RE_MASK                                        0x1
+#define D18F1xB0_WE_OFFSET                                      1
+#define D18F1xB0_WE_WIDTH                                       1
+#define D18F1xB0_WE_MASK                                        0x2
+#define D18F1xB0_Reserved_2_2_OFFSET                            2
+#define D18F1xB0_Reserved_2_2_WIDTH                             1
+#define D18F1xB0_Reserved_2_2_MASK                              0x4
+#define D18F1xB0_Lock_OFFSET                                    3
+#define D18F1xB0_Lock_WIDTH                                     1
+#define D18F1xB0_Lock_MASK                                      0x8
+#define D18F1xB0_Reserved_7_4_OFFSET                            4
+#define D18F1xB0_Reserved_7_4_WIDTH                             4
+#define D18F1xB0_Reserved_7_4_MASK                              0xf0
+#define D18F1xB0_MMIOBase_39_16__OFFSET                         8
+#define D18F1xB0_MMIOBase_39_16__WIDTH                          24
+#define D18F1xB0_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xB0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xB0_STRUCT;
+
+// **** D18F1xB4 Register Definition ****
+// Address
+#define D18F1xB4_ADDRESS                                        0xb4
+
+// Type
+#define D18F1xB4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xB4_DstNode_OFFSET                                 0
+#define D18F1xB4_DstNode_WIDTH                                  3
+#define D18F1xB4_DstNode_MASK                                   0x7
+#define D18F1xB4_Reserved_3_3_OFFSET                            3
+#define D18F1xB4_Reserved_3_3_WIDTH                             1
+#define D18F1xB4_Reserved_3_3_MASK                              0x8
+#define D18F1xB4_DstLink_OFFSET                                 4
+#define D18F1xB4_DstLink_WIDTH                                  2
+#define D18F1xB4_DstLink_MASK                                   0x30
+#define D18F1xB4_DstSubLink_OFFSET                              6
+#define D18F1xB4_DstSubLink_WIDTH                               1
+#define D18F1xB4_DstSubLink_MASK                                0x40
+#define D18F1xB4_NP_OFFSET                                      7
+#define D18F1xB4_NP_WIDTH                                       1
+#define D18F1xB4_NP_MASK                                        0x80
+#define D18F1xB4_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xB4_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xB4_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xB4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xB4_STRUCT;
+
+// **** D18F1xB8 Register Definition ****
+// Address
+#define D18F1xB8_ADDRESS                                        0xb8
+
+// Type
+#define D18F1xB8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xB8_RE_OFFSET                                      0
+#define D18F1xB8_RE_WIDTH                                       1
+#define D18F1xB8_RE_MASK                                        0x1
+#define D18F1xB8_WE_OFFSET                                      1
+#define D18F1xB8_WE_WIDTH                                       1
+#define D18F1xB8_WE_MASK                                        0x2
+#define D18F1xB8_Reserved_2_2_OFFSET                            2
+#define D18F1xB8_Reserved_2_2_WIDTH                             1
+#define D18F1xB8_Reserved_2_2_MASK                              0x4
+#define D18F1xB8_Lock_OFFSET                                    3
+#define D18F1xB8_Lock_WIDTH                                     1
+#define D18F1xB8_Lock_MASK                                      0x8
+#define D18F1xB8_Reserved_7_4_OFFSET                            4
+#define D18F1xB8_Reserved_7_4_WIDTH                             4
+#define D18F1xB8_Reserved_7_4_MASK                              0xf0
+#define D18F1xB8_MMIOBase_39_16__OFFSET                         8
+#define D18F1xB8_MMIOBase_39_16__WIDTH                          24
+#define D18F1xB8_MMIOBase_39_16__MASK                           0xffffff00
+
+/// D18F1xB8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xB8_STRUCT;
+
+// **** D18F1xBC Register Definition ****
+// Address
+#define D18F1xBC_ADDRESS                                        0xbc
+
+// Type
+#define D18F1xBC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xBC_DstNode_OFFSET                                 0
+#define D18F1xBC_DstNode_WIDTH                                  3
+#define D18F1xBC_DstNode_MASK                                   0x7
+#define D18F1xBC_Reserved_3_3_OFFSET                            3
+#define D18F1xBC_Reserved_3_3_WIDTH                             1
+#define D18F1xBC_Reserved_3_3_MASK                              0x8
+#define D18F1xBC_DstLink_OFFSET                                 4
+#define D18F1xBC_DstLink_WIDTH                                  2
+#define D18F1xBC_DstLink_MASK                                   0x30
+#define D18F1xBC_DstSubLink_OFFSET                              6
+#define D18F1xBC_DstSubLink_WIDTH                               1
+#define D18F1xBC_DstSubLink_MASK                                0x40
+#define D18F1xBC_NP_OFFSET                                      7
+#define D18F1xBC_NP_WIDTH                                       1
+#define D18F1xBC_NP_MASK                                        0x80
+#define D18F1xBC_MMIOLimit_39_16__OFFSET                        8
+#define D18F1xBC_MMIOLimit_39_16__WIDTH                         24
+#define D18F1xBC_MMIOLimit_39_16__MASK                          0xffffff00
+
+/// D18F1xBC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xBC_STRUCT;
+
+// **** D18F1xC0 Register Definition ****
+// Address
+#define D18F1xC0_ADDRESS                                        0xc0
+
+// Type
+#define D18F1xC0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xC0_RE_OFFSET                                      0
+#define D18F1xC0_RE_WIDTH                                       1
+#define D18F1xC0_RE_MASK                                        0x1
+#define D18F1xC0_WE_OFFSET                                      1
+#define D18F1xC0_WE_WIDTH                                       1
+#define D18F1xC0_WE_MASK                                        0x2
+#define D18F1xC0_Reserved_3_2_OFFSET                            2
+#define D18F1xC0_Reserved_3_2_WIDTH                             2
+#define D18F1xC0_Reserved_3_2_MASK                              0xc
+#define D18F1xC0_VE_OFFSET                                      4
+#define D18F1xC0_VE_WIDTH                                       1
+#define D18F1xC0_VE_MASK                                        0x10
+#define D18F1xC0_IE_OFFSET                                      5
+#define D18F1xC0_IE_WIDTH                                       1
+#define D18F1xC0_IE_MASK                                        0x20
+#define D18F1xC0_Reserved_11_6_OFFSET                           6
+#define D18F1xC0_Reserved_11_6_WIDTH                            6
+#define D18F1xC0_Reserved_11_6_MASK                             0xfc0
+#define D18F1xC0_IOBase_24_12__OFFSET                           12
+#define D18F1xC0_IOBase_24_12__WIDTH                            13
+#define D18F1xC0_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xC0_Reserved_31_25_OFFSET                          25
+#define D18F1xC0_Reserved_31_25_WIDTH                           7
+#define D18F1xC0_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xC0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xC0_STRUCT;
+
+// **** D18F1xC4 Register Definition ****
+// Address
+#define D18F1xC4_ADDRESS                                        0xc4
+
+// Type
+#define D18F1xC4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xC4_DstNode_OFFSET                                 0
+#define D18F1xC4_DstNode_WIDTH                                  3
+#define D18F1xC4_DstNode_MASK                                   0x7
+#define D18F1xC4_Reserved_3_3_OFFSET                            3
+#define D18F1xC4_Reserved_3_3_WIDTH                             1
+#define D18F1xC4_Reserved_3_3_MASK                              0x8
+#define D18F1xC4_DstLink_OFFSET                                 4
+#define D18F1xC4_DstLink_WIDTH                                  2
+#define D18F1xC4_DstLink_MASK                                   0x30
+#define D18F1xC4_DstSubLink_OFFSET                              6
+#define D18F1xC4_DstSubLink_WIDTH                               1
+#define D18F1xC4_DstSubLink_MASK                                0x40
+#define D18F1xC4_Reserved_11_7_OFFSET                           7
+#define D18F1xC4_Reserved_11_7_WIDTH                            5
+#define D18F1xC4_Reserved_11_7_MASK                             0xf80
+#define D18F1xC4_IOLimit_24_12__OFFSET                          12
+#define D18F1xC4_IOLimit_24_12__WIDTH                           13
+#define D18F1xC4_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xC4_Reserved_31_25_OFFSET                          25
+#define D18F1xC4_Reserved_31_25_WIDTH                           7
+#define D18F1xC4_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xC4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xC4_STRUCT;
+
+// **** D18F1xC8 Register Definition ****
+// Address
+#define D18F1xC8_ADDRESS                                        0xc8
+
+// Type
+#define D18F1xC8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xC8_RE_OFFSET                                      0
+#define D18F1xC8_RE_WIDTH                                       1
+#define D18F1xC8_RE_MASK                                        0x1
+#define D18F1xC8_WE_OFFSET                                      1
+#define D18F1xC8_WE_WIDTH                                       1
+#define D18F1xC8_WE_MASK                                        0x2
+#define D18F1xC8_Reserved_3_2_OFFSET                            2
+#define D18F1xC8_Reserved_3_2_WIDTH                             2
+#define D18F1xC8_Reserved_3_2_MASK                              0xc
+#define D18F1xC8_VE_OFFSET                                      4
+#define D18F1xC8_VE_WIDTH                                       1
+#define D18F1xC8_VE_MASK                                        0x10
+#define D18F1xC8_IE_OFFSET                                      5
+#define D18F1xC8_IE_WIDTH                                       1
+#define D18F1xC8_IE_MASK                                        0x20
+#define D18F1xC8_Reserved_11_6_OFFSET                           6
+#define D18F1xC8_Reserved_11_6_WIDTH                            6
+#define D18F1xC8_Reserved_11_6_MASK                             0xfc0
+#define D18F1xC8_IOBase_24_12__OFFSET                           12
+#define D18F1xC8_IOBase_24_12__WIDTH                            13
+#define D18F1xC8_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xC8_Reserved_31_25_OFFSET                          25
+#define D18F1xC8_Reserved_31_25_WIDTH                           7
+#define D18F1xC8_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xC8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xC8_STRUCT;
+
+// **** D18F1xCC Register Definition ****
+// Address
+#define D18F1xCC_ADDRESS                                        0xcc
+
+// Type
+#define D18F1xCC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xCC_DstNode_OFFSET                                 0
+#define D18F1xCC_DstNode_WIDTH                                  3
+#define D18F1xCC_DstNode_MASK                                   0x7
+#define D18F1xCC_Reserved_3_3_OFFSET                            3
+#define D18F1xCC_Reserved_3_3_WIDTH                             1
+#define D18F1xCC_Reserved_3_3_MASK                              0x8
+#define D18F1xCC_DstLink_OFFSET                                 4
+#define D18F1xCC_DstLink_WIDTH                                  2
+#define D18F1xCC_DstLink_MASK                                   0x30
+#define D18F1xCC_DstSubLink_OFFSET                              6
+#define D18F1xCC_DstSubLink_WIDTH                               1
+#define D18F1xCC_DstSubLink_MASK                                0x40
+#define D18F1xCC_Reserved_11_7_OFFSET                           7
+#define D18F1xCC_Reserved_11_7_WIDTH                            5
+#define D18F1xCC_Reserved_11_7_MASK                             0xf80
+#define D18F1xCC_IOLimit_24_12__OFFSET                          12
+#define D18F1xCC_IOLimit_24_12__WIDTH                           13
+#define D18F1xCC_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xCC_Reserved_31_25_OFFSET                          25
+#define D18F1xCC_Reserved_31_25_WIDTH                           7
+#define D18F1xCC_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xCC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xCC_STRUCT;
+
+// **** D18F1xD0 Register Definition ****
+// Address
+#define D18F1xD0_ADDRESS                                        0xd0
+
+// Type
+#define D18F1xD0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xD0_RE_OFFSET                                      0
+#define D18F1xD0_RE_WIDTH                                       1
+#define D18F1xD0_RE_MASK                                        0x1
+#define D18F1xD0_WE_OFFSET                                      1
+#define D18F1xD0_WE_WIDTH                                       1
+#define D18F1xD0_WE_MASK                                        0x2
+#define D18F1xD0_Reserved_3_2_OFFSET                            2
+#define D18F1xD0_Reserved_3_2_WIDTH                             2
+#define D18F1xD0_Reserved_3_2_MASK                              0xc
+#define D18F1xD0_VE_OFFSET                                      4
+#define D18F1xD0_VE_WIDTH                                       1
+#define D18F1xD0_VE_MASK                                        0x10
+#define D18F1xD0_IE_OFFSET                                      5
+#define D18F1xD0_IE_WIDTH                                       1
+#define D18F1xD0_IE_MASK                                        0x20
+#define D18F1xD0_Reserved_11_6_OFFSET                           6
+#define D18F1xD0_Reserved_11_6_WIDTH                            6
+#define D18F1xD0_Reserved_11_6_MASK                             0xfc0
+#define D18F1xD0_IOBase_24_12__OFFSET                           12
+#define D18F1xD0_IOBase_24_12__WIDTH                            13
+#define D18F1xD0_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xD0_Reserved_31_25_OFFSET                          25
+#define D18F1xD0_Reserved_31_25_WIDTH                           7
+#define D18F1xD0_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xD0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xD0_STRUCT;
+
+// **** D18F1xD4 Register Definition ****
+// Address
+#define D18F1xD4_ADDRESS                                        0xd4
+
+// Type
+#define D18F1xD4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xD4_DstNode_OFFSET                                 0
+#define D18F1xD4_DstNode_WIDTH                                  3
+#define D18F1xD4_DstNode_MASK                                   0x7
+#define D18F1xD4_Reserved_3_3_OFFSET                            3
+#define D18F1xD4_Reserved_3_3_WIDTH                             1
+#define D18F1xD4_Reserved_3_3_MASK                              0x8
+#define D18F1xD4_DstLink_OFFSET                                 4
+#define D18F1xD4_DstLink_WIDTH                                  2
+#define D18F1xD4_DstLink_MASK                                   0x30
+#define D18F1xD4_DstSubLink_OFFSET                              6
+#define D18F1xD4_DstSubLink_WIDTH                               1
+#define D18F1xD4_DstSubLink_MASK                                0x40
+#define D18F1xD4_Reserved_11_7_OFFSET                           7
+#define D18F1xD4_Reserved_11_7_WIDTH                            5
+#define D18F1xD4_Reserved_11_7_MASK                             0xf80
+#define D18F1xD4_IOLimit_24_12__OFFSET                          12
+#define D18F1xD4_IOLimit_24_12__WIDTH                           13
+#define D18F1xD4_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xD4_Reserved_31_25_OFFSET                          25
+#define D18F1xD4_Reserved_31_25_WIDTH                           7
+#define D18F1xD4_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xD4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xD4_STRUCT;
+
+// **** D18F1xD8 Register Definition ****
+// Address
+#define D18F1xD8_ADDRESS                                        0xd8
+
+// Type
+#define D18F1xD8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xD8_RE_OFFSET                                      0
+#define D18F1xD8_RE_WIDTH                                       1
+#define D18F1xD8_RE_MASK                                        0x1
+#define D18F1xD8_WE_OFFSET                                      1
+#define D18F1xD8_WE_WIDTH                                       1
+#define D18F1xD8_WE_MASK                                        0x2
+#define D18F1xD8_Reserved_3_2_OFFSET                            2
+#define D18F1xD8_Reserved_3_2_WIDTH                             2
+#define D18F1xD8_Reserved_3_2_MASK                              0xc
+#define D18F1xD8_VE_OFFSET                                      4
+#define D18F1xD8_VE_WIDTH                                       1
+#define D18F1xD8_VE_MASK                                        0x10
+#define D18F1xD8_IE_OFFSET                                      5
+#define D18F1xD8_IE_WIDTH                                       1
+#define D18F1xD8_IE_MASK                                        0x20
+#define D18F1xD8_Reserved_11_6_OFFSET                           6
+#define D18F1xD8_Reserved_11_6_WIDTH                            6
+#define D18F1xD8_Reserved_11_6_MASK                             0xfc0
+#define D18F1xD8_IOBase_24_12__OFFSET                           12
+#define D18F1xD8_IOBase_24_12__WIDTH                            13
+#define D18F1xD8_IOBase_24_12__MASK                             0x1fff000
+#define D18F1xD8_Reserved_31_25_OFFSET                          25
+#define D18F1xD8_Reserved_31_25_WIDTH                           7
+#define D18F1xD8_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xD8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       IE:1 ; ///<
+    UINT32                                            Reserved_11_6:6 ; ///<
+    UINT32                                            IOBase_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xD8_STRUCT;
+
+// **** D18F1xDC Register Definition ****
+// Address
+#define D18F1xDC_ADDRESS                                        0xdc
+
+// Type
+#define D18F1xDC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xDC_DstNode_OFFSET                                 0
+#define D18F1xDC_DstNode_WIDTH                                  3
+#define D18F1xDC_DstNode_MASK                                   0x7
+#define D18F1xDC_Reserved_3_3_OFFSET                            3
+#define D18F1xDC_Reserved_3_3_WIDTH                             1
+#define D18F1xDC_Reserved_3_3_MASK                              0x8
+#define D18F1xDC_DstLink_OFFSET                                 4
+#define D18F1xDC_DstLink_WIDTH                                  2
+#define D18F1xDC_DstLink_MASK                                   0x30
+#define D18F1xDC_DstSubLink_OFFSET                              6
+#define D18F1xDC_DstSubLink_WIDTH                               1
+#define D18F1xDC_DstSubLink_MASK                                0x40
+#define D18F1xDC_Reserved_11_7_OFFSET                           7
+#define D18F1xDC_Reserved_11_7_WIDTH                            5
+#define D18F1xDC_Reserved_11_7_MASK                             0xf80
+#define D18F1xDC_IOLimit_24_12__OFFSET                          12
+#define D18F1xDC_IOLimit_24_12__WIDTH                           13
+#define D18F1xDC_IOLimit_24_12__MASK                            0x1fff000
+#define D18F1xDC_Reserved_31_25_OFFSET                          25
+#define D18F1xDC_Reserved_31_25_WIDTH                           7
+#define D18F1xDC_Reserved_31_25_MASK                            0xfe000000
+
+/// D18F1xDC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                           IOLimit_24_12_:13; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xDC_STRUCT;
+
+// **** D18F1xE0 Register Definition ****
+// Address
+#define D18F1xE0_ADDRESS                                        0xe0
+
+// Type
+#define D18F1xE0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xE0_RE_OFFSET                                      0
+#define D18F1xE0_RE_WIDTH                                       1
+#define D18F1xE0_RE_MASK                                        0x1
+#define D18F1xE0_WE_OFFSET                                      1
+#define D18F1xE0_WE_WIDTH                                       1
+#define D18F1xE0_WE_MASK                                        0x2
+#define D18F1xE0_DevCmpEn_OFFSET                                2
+#define D18F1xE0_DevCmpEn_WIDTH                                 1
+#define D18F1xE0_DevCmpEn_MASK                                  0x4
+#define D18F1xE0_Reserved_15_3_OFFSET                           3
+#define D18F1xE0_Reserved_15_3_WIDTH                            13
+#define D18F1xE0_Reserved_15_3_MASK                             0xfff8
+#define D18F1xE0_BusNumBase_7_0__OFFSET                         16
+#define D18F1xE0_BusNumBase_7_0__WIDTH                          8
+#define D18F1xE0_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xE0_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xE0_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xE0_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xE0_STRUCT;
+
+// **** D18F1xE4 Register Definition ****
+// Address
+#define D18F1xE4_ADDRESS                                        0xe4
+
+// Type
+#define D18F1xE4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xE4_RE_OFFSET                                      0
+#define D18F1xE4_RE_WIDTH                                       1
+#define D18F1xE4_RE_MASK                                        0x1
+#define D18F1xE4_WE_OFFSET                                      1
+#define D18F1xE4_WE_WIDTH                                       1
+#define D18F1xE4_WE_MASK                                        0x2
+#define D18F1xE4_DevCmpEn_OFFSET                                2
+#define D18F1xE4_DevCmpEn_WIDTH                                 1
+#define D18F1xE4_DevCmpEn_MASK                                  0x4
+#define D18F1xE4_Reserved_15_3_OFFSET                           3
+#define D18F1xE4_Reserved_15_3_WIDTH                            13
+#define D18F1xE4_Reserved_15_3_MASK                             0xfff8
+#define D18F1xE4_BusNumBase_7_0__OFFSET                         16
+#define D18F1xE4_BusNumBase_7_0__WIDTH                          8
+#define D18F1xE4_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xE4_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xE4_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xE4_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xE4_STRUCT;
+
+// **** D18F1xE8 Register Definition ****
+// Address
+#define D18F1xE8_ADDRESS                                        0xe8
+
+// Type
+#define D18F1xE8_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xE8_RE_OFFSET                                      0
+#define D18F1xE8_RE_WIDTH                                       1
+#define D18F1xE8_RE_MASK                                        0x1
+#define D18F1xE8_WE_OFFSET                                      1
+#define D18F1xE8_WE_WIDTH                                       1
+#define D18F1xE8_WE_MASK                                        0x2
+#define D18F1xE8_DevCmpEn_OFFSET                                2
+#define D18F1xE8_DevCmpEn_WIDTH                                 1
+#define D18F1xE8_DevCmpEn_MASK                                  0x4
+#define D18F1xE8_Reserved_15_3_OFFSET                           3
+#define D18F1xE8_Reserved_15_3_WIDTH                            13
+#define D18F1xE8_Reserved_15_3_MASK                             0xfff8
+#define D18F1xE8_BusNumBase_7_0__OFFSET                         16
+#define D18F1xE8_BusNumBase_7_0__WIDTH                          8
+#define D18F1xE8_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xE8_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xE8_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xE8_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xE8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xE8_STRUCT;
+
+// **** D18F1xEC Register Definition ****
+// Address
+#define D18F1xEC_ADDRESS                                        0xec
+
+// Type
+#define D18F1xEC_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xEC_RE_OFFSET                                      0
+#define D18F1xEC_RE_WIDTH                                       1
+#define D18F1xEC_RE_MASK                                        0x1
+#define D18F1xEC_WE_OFFSET                                      1
+#define D18F1xEC_WE_WIDTH                                       1
+#define D18F1xEC_WE_MASK                                        0x2
+#define D18F1xEC_DevCmpEn_OFFSET                                2
+#define D18F1xEC_DevCmpEn_WIDTH                                 1
+#define D18F1xEC_DevCmpEn_MASK                                  0x4
+#define D18F1xEC_Reserved_15_3_OFFSET                           3
+#define D18F1xEC_Reserved_15_3_WIDTH                            13
+#define D18F1xEC_Reserved_15_3_MASK                             0xfff8
+#define D18F1xEC_BusNumBase_7_0__OFFSET                         16
+#define D18F1xEC_BusNumBase_7_0__WIDTH                          8
+#define D18F1xEC_BusNumBase_7_0__MASK                           0xff0000
+#define D18F1xEC_BusNumLimit_7_0__OFFSET                        24
+#define D18F1xEC_BusNumLimit_7_0__WIDTH                         8
+#define D18F1xEC_BusNumLimit_7_0__MASK                          0xff000000
+
+/// D18F1xEC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                                 DevCmpEn:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          BusNumBase_7_0_:8 ; ///<
+    UINT32                                         BusNumLimit_7_0_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xEC_STRUCT;
+
+// **** D18F1xF0 Register Definition ****
+// Address
+#define D18F1xF0_ADDRESS                                        0xf0
+
+// Type
+#define D18F1xF0_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xF0_DramHoleValid_OFFSET                           0
+#define D18F1xF0_DramHoleValid_WIDTH                            1
+#define D18F1xF0_DramHoleValid_MASK                             0x1
+#define D18F1xF0_DramMemHoistValid_OFFSET                       1
+#define D18F1xF0_DramMemHoistValid_WIDTH                        1
+#define D18F1xF0_DramMemHoistValid_MASK                         0x2
+#define D18F1xF0_Reserved_2_2_OFFSET                            2
+#define D18F1xF0_Reserved_2_2_WIDTH                             1
+#define D18F1xF0_Reserved_2_2_MASK                              0x4
+#define D18F1xF0_Reserved_6_3_OFFSET                            3
+#define D18F1xF0_Reserved_6_3_WIDTH                             4
+#define D18F1xF0_Reserved_6_3_MASK                              0x78
+#define D18F1xF0_DramHoleOffset_31_23__OFFSET                   7
+#define D18F1xF0_DramHoleOffset_31_23__WIDTH                    9
+#define D18F1xF0_DramHoleOffset_31_23__MASK                     0xff80
+#define D18F1xF0_Reserved_23_16_OFFSET                          16
+#define D18F1xF0_Reserved_23_16_WIDTH                           8
+#define D18F1xF0_Reserved_23_16_MASK                            0xff0000
+#define D18F1xF0_DramHoleBase_31_24__OFFSET                     24
+#define D18F1xF0_DramHoleBase_31_24__WIDTH                      8
+#define D18F1xF0_DramHoleBase_31_24__MASK                       0xff000000
+
+/// D18F1xF0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DramHoleValid:1 ; ///<
+    UINT32                                        DramMemHoistValid:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             Reserved_6_3:4 ; ///<
+    UINT32                                    DramHoleOffset_31_23_:9 ; ///<
+    UINT32                                           Reserved_23_16:8 ; ///<
+    UINT32                                      DramHoleBase_31_24_:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xF0_STRUCT;
+
+// **** D18F1xF4 Register Definition ****
+// Address
+#define D18F1xF4_ADDRESS                                        0xf4
+
+// Type
+#define D18F1xF4_TYPE                                           TYPE_D18F1
+// Field Data
+#define D18F1xF4_VE_OFFSET                                      0
+#define D18F1xF4_VE_WIDTH                                       1
+#define D18F1xF4_VE_MASK                                        0x1
+#define D18F1xF4_NP_OFFSET                                      1
+#define D18F1xF4_NP_WIDTH                                       1
+#define D18F1xF4_NP_MASK                                        0x2
+#define D18F1xF4_Reserved_2_2_OFFSET                            2
+#define D18F1xF4_Reserved_2_2_WIDTH                             1
+#define D18F1xF4_Reserved_2_2_MASK                              0x4
+#define D18F1xF4_Lock_OFFSET                                    3
+#define D18F1xF4_Lock_WIDTH                                     1
+#define D18F1xF4_Lock_MASK                                      0x8
+#define D18F1xF4_DstNode_OFFSET                                 4
+#define D18F1xF4_DstNode_WIDTH                                  3
+#define D18F1xF4_DstNode_MASK                                   0x70
+#define D18F1xF4_Reserved_11_7_OFFSET                           7
+#define D18F1xF4_Reserved_11_7_WIDTH                            5
+#define D18F1xF4_Reserved_11_7_MASK                             0xf80
+#define D18F1xF4_DstLink_OFFSET                                 12
+#define D18F1xF4_DstLink_WIDTH                                  2
+#define D18F1xF4_DstLink_MASK                                   0x3000
+#define D18F1xF4_DstSubLink_OFFSET                              14
+#define D18F1xF4_DstSubLink_WIDTH                               1
+#define D18F1xF4_DstSubLink_MASK                                0x4000
+#define D18F1xF4_Reserved_31_15_OFFSET                          15
+#define D18F1xF4_Reserved_31_15_WIDTH                           17
+#define D18F1xF4_Reserved_31_15_MASK                            0xffff8000
+
+/// D18F1xF4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       VE:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                            Reserved_11_7:5 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1xF4_STRUCT;
+
+// **** D18F1x10C Register Definition ****
+// Address
+#define D18F1x10C_ADDRESS                                       0x10c
+
+// Type
+#define D18F1x10C_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x10C_DctCfgSel_OFFSET                              0
+#define D18F1x10C_DctCfgSel_WIDTH                               1
+#define D18F1x10C_DctCfgSel_MASK                                0x1
+#define D18F1x10C_Reserved_2_1_OFFSET                           1
+#define D18F1x10C_Reserved_2_1_WIDTH                            2
+#define D18F1x10C_Reserved_2_1_MASK                             0x6
+#define D18F1x10C_MemPsSel_OFFSET                               3
+#define D18F1x10C_MemPsSel_WIDTH                                1
+#define D18F1x10C_MemPsSel_MASK                                 0x8
+#define D18F1x10C_NbPsSel_OFFSET                                4
+#define D18F1x10C_NbPsSel_WIDTH                                 2
+#define D18F1x10C_NbPsSel_MASK                                  0x30
+#define D18F1x10C_Unused_31_6_OFFSET                            6
+#define D18F1x10C_Unused_31_6_WIDTH                             26
+#define D18F1x10C_Unused_31_6_MASK                              0xffffffc0
+
+/// D18F1x10C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctCfgSel:1 ; ///<
+    UINT32                                             Reserved_2_1:2 ; ///<
+    UINT32                                                 MemPsSel:1 ; ///<
+    UINT32                                                  NbPsSel:2 ; ///<
+    UINT32                                              Unused_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x10C_STRUCT;
+
+// **** D18F1x120 Register Definition ****
+// Address
+#define D18F1x120_ADDRESS                                       0x120
+
+// Type
+#define D18F1x120_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x120_DramBaseAddr_47_27__OFFSET                    0
+#define D18F1x120_DramBaseAddr_47_27__WIDTH                     21
+#define D18F1x120_DramBaseAddr_47_27__MASK                      0x1fffff
+#define D18F1x120_Reserved_31_21_OFFSET                         21
+#define D18F1x120_Reserved_31_21_WIDTH                          11
+#define D18F1x120_Reserved_31_21_MASK                           0xffe00000
+
+/// D18F1x120
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      DramBaseAddr_47_27_:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x120_STRUCT;
+
+// **** D18F1x124 Register Definition ****
+// Address
+#define D18F1x124_ADDRESS                                       0x124
+
+// Type
+#define D18F1x124_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x124_DramLimitAddr_47_27__OFFSET                   0
+#define D18F1x124_DramLimitAddr_47_27__WIDTH                    21
+#define D18F1x124_DramLimitAddr_47_27__MASK                     0x1fffff
+#define D18F1x124_Reserved_31_21_OFFSET                         21
+#define D18F1x124_Reserved_31_21_WIDTH                          11
+#define D18F1x124_Reserved_31_21_MASK                           0xffe00000
+
+/// D18F1x124
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     DramLimitAddr_47_27_:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x124_STRUCT;
+
+// **** D18F1x140 Register Definition ****
+// Address
+#define D18F1x140_ADDRESS                                       0x140
+
+// Type
+#define D18F1x140_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x140_DramBase_47_40__OFFSET                        0
+#define D18F1x140_DramBase_47_40__WIDTH                         8
+#define D18F1x140_DramBase_47_40__MASK                          0xff
+#define D18F1x140_Reserved_31_8_OFFSET                          8
+#define D18F1x140_Reserved_31_8_WIDTH                           24
+#define D18F1x140_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F1x140
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          DramBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x140_STRUCT;
+
+// **** D18F1x144 Register Definition ****
+// Address
+#define D18F1x144_ADDRESS                                       0x144
+
+// Type
+#define D18F1x144_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x144_DramLimit_47_40__OFFSET                       0
+#define D18F1x144_DramLimit_47_40__WIDTH                        8
+#define D18F1x144_DramLimit_47_40__MASK                         0xff
+#define D18F1x144_Reserved_31_8_OFFSET                          8
+#define D18F1x144_Reserved_31_8_WIDTH                           24
+#define D18F1x144_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F1x144
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         DramLimit_47_40_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x144_STRUCT;
+
+// **** D18F1x180 Register Definition ****
+// Address
+#define D18F1x180_ADDRESS                                       0x180
+
+// Type
+#define D18F1x180_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x180_MMIOBase_47_40__OFFSET                        0
+#define D18F1x180_MMIOBase_47_40__WIDTH                         8
+#define D18F1x180_MMIOBase_47_40__MASK                          0xff
+#define D18F1x180_Reserved_15_8_OFFSET                          8
+#define D18F1x180_Reserved_15_8_WIDTH                           8
+#define D18F1x180_Reserved_15_8_MASK                            0xff00
+#define D18F1x180_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x180_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x180_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x180_Reserved_31_24_OFFSET                         24
+#define D18F1x180_Reserved_31_24_WIDTH                          8
+#define D18F1x180_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x180
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x180_STRUCT;
+
+// **** D18F1x184 Register Definition ****
+// Address
+#define D18F1x184_ADDRESS                                       0x184
+
+// Type
+#define D18F1x184_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x184_MMIOBase_47_40__OFFSET                        0
+#define D18F1x184_MMIOBase_47_40__WIDTH                         8
+#define D18F1x184_MMIOBase_47_40__MASK                          0xff
+#define D18F1x184_Reserved_15_8_OFFSET                          8
+#define D18F1x184_Reserved_15_8_WIDTH                           8
+#define D18F1x184_Reserved_15_8_MASK                            0xff00
+#define D18F1x184_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x184_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x184_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x184_Reserved_31_24_OFFSET                         24
+#define D18F1x184_Reserved_31_24_WIDTH                          8
+#define D18F1x184_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x184
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x184_STRUCT;
+
+// **** D18F1x188 Register Definition ****
+// Address
+#define D18F1x188_ADDRESS                                       0x188
+
+// Type
+#define D18F1x188_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x188_MMIOBase_47_40__OFFSET                        0
+#define D18F1x188_MMIOBase_47_40__WIDTH                         8
+#define D18F1x188_MMIOBase_47_40__MASK                          0xff
+#define D18F1x188_Reserved_15_8_OFFSET                          8
+#define D18F1x188_Reserved_15_8_WIDTH                           8
+#define D18F1x188_Reserved_15_8_MASK                            0xff00
+#define D18F1x188_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x188_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x188_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x188_Reserved_31_24_OFFSET                         24
+#define D18F1x188_Reserved_31_24_WIDTH                          8
+#define D18F1x188_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x188_STRUCT;
+
+// **** D18F1x18C Register Definition ****
+// Address
+#define D18F1x18C_ADDRESS                                       0x18c
+
+// Type
+#define D18F1x18C_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x18C_MMIOBase_47_40__OFFSET                        0
+#define D18F1x18C_MMIOBase_47_40__WIDTH                         8
+#define D18F1x18C_MMIOBase_47_40__MASK                          0xff
+#define D18F1x18C_Reserved_15_8_OFFSET                          8
+#define D18F1x18C_Reserved_15_8_WIDTH                           8
+#define D18F1x18C_Reserved_15_8_MASK                            0xff00
+#define D18F1x18C_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x18C_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x18C_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x18C_Reserved_31_24_OFFSET                         24
+#define D18F1x18C_Reserved_31_24_WIDTH                          8
+#define D18F1x18C_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x18C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x18C_STRUCT;
+
+// **** D18F1x190 Register Definition ****
+// Address
+#define D18F1x190_ADDRESS                                       0x190
+
+// Type
+#define D18F1x190_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x190_MMIOBase_47_40__OFFSET                        0
+#define D18F1x190_MMIOBase_47_40__WIDTH                         8
+#define D18F1x190_MMIOBase_47_40__MASK                          0xff
+#define D18F1x190_Reserved_15_8_OFFSET                          8
+#define D18F1x190_Reserved_15_8_WIDTH                           8
+#define D18F1x190_Reserved_15_8_MASK                            0xff00
+#define D18F1x190_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x190_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x190_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x190_Reserved_31_24_OFFSET                         24
+#define D18F1x190_Reserved_31_24_WIDTH                          8
+#define D18F1x190_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x190
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x190_STRUCT;
+
+// **** D18F1x194 Register Definition ****
+// Address
+#define D18F1x194_ADDRESS                                       0x194
+
+// Type
+#define D18F1x194_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x194_MMIOBase_47_40__OFFSET                        0
+#define D18F1x194_MMIOBase_47_40__WIDTH                         8
+#define D18F1x194_MMIOBase_47_40__MASK                          0xff
+#define D18F1x194_Reserved_15_8_OFFSET                          8
+#define D18F1x194_Reserved_15_8_WIDTH                           8
+#define D18F1x194_Reserved_15_8_MASK                            0xff00
+#define D18F1x194_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x194_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x194_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x194_Reserved_31_24_OFFSET                         24
+#define D18F1x194_Reserved_31_24_WIDTH                          8
+#define D18F1x194_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x194
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x194_STRUCT;
+
+// **** D18F1x198 Register Definition ****
+// Address
+#define D18F1x198_ADDRESS                                       0x198
+
+// Type
+#define D18F1x198_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x198_MMIOBase_47_40__OFFSET                        0
+#define D18F1x198_MMIOBase_47_40__WIDTH                         8
+#define D18F1x198_MMIOBase_47_40__MASK                          0xff
+#define D18F1x198_Reserved_15_8_OFFSET                          8
+#define D18F1x198_Reserved_15_8_WIDTH                           8
+#define D18F1x198_Reserved_15_8_MASK                            0xff00
+#define D18F1x198_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x198_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x198_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x198_Reserved_31_24_OFFSET                         24
+#define D18F1x198_Reserved_31_24_WIDTH                          8
+#define D18F1x198_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x198
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x198_STRUCT;
+
+// **** D18F1x19C Register Definition ****
+// Address
+#define D18F1x19C_ADDRESS                                       0x19c
+
+// Type
+#define D18F1x19C_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x19C_MMIOBase_47_40__OFFSET                        0
+#define D18F1x19C_MMIOBase_47_40__WIDTH                         8
+#define D18F1x19C_MMIOBase_47_40__MASK                          0xff
+#define D18F1x19C_Reserved_15_8_OFFSET                          8
+#define D18F1x19C_Reserved_15_8_WIDTH                           8
+#define D18F1x19C_Reserved_15_8_MASK                            0xff00
+#define D18F1x19C_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x19C_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x19C_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x19C_Reserved_31_24_OFFSET                         24
+#define D18F1x19C_Reserved_31_24_WIDTH                          8
+#define D18F1x19C_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x19C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x19C_STRUCT;
+
+// **** D18F1x1A0 Register Definition ****
+// Address
+#define D18F1x1A0_ADDRESS                                       0x1a0
+
+// Type
+#define D18F1x1A0_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1A0_RE_OFFSET                                     0
+#define D18F1x1A0_RE_WIDTH                                      1
+#define D18F1x1A0_RE_MASK                                       0x1
+#define D18F1x1A0_WE_OFFSET                                     1
+#define D18F1x1A0_WE_WIDTH                                      1
+#define D18F1x1A0_WE_MASK                                       0x2
+#define D18F1x1A0_Reserved_2_2_OFFSET                           2
+#define D18F1x1A0_Reserved_2_2_WIDTH                            1
+#define D18F1x1A0_Reserved_2_2_MASK                             0x4
+#define D18F1x1A0_Lock_OFFSET                                   3
+#define D18F1x1A0_Lock_WIDTH                                    1
+#define D18F1x1A0_Lock_MASK                                     0x8
+#define D18F1x1A0_Reserved_7_4_OFFSET                           4
+#define D18F1x1A0_Reserved_7_4_WIDTH                            4
+#define D18F1x1A0_Reserved_7_4_MASK                             0xf0
+#define D18F1x1A0_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1A0_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1A0_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1A0_STRUCT;
+
+// **** D18F1x1A4 Register Definition ****
+// Address
+#define D18F1x1A4_ADDRESS                                       0x1a4
+
+// Type
+#define D18F1x1A4_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1A4_DstNode_OFFSET                                0
+#define D18F1x1A4_DstNode_WIDTH                                 3
+#define D18F1x1A4_DstNode_MASK                                  0x7
+#define D18F1x1A4_Reserved_3_3_OFFSET                           3
+#define D18F1x1A4_Reserved_3_3_WIDTH                            1
+#define D18F1x1A4_Reserved_3_3_MASK                             0x8
+#define D18F1x1A4_DstLink_OFFSET                                4
+#define D18F1x1A4_DstLink_WIDTH                                 2
+#define D18F1x1A4_DstLink_MASK                                  0x30
+#define D18F1x1A4_DstSubLink_OFFSET                             6
+#define D18F1x1A4_DstSubLink_WIDTH                              1
+#define D18F1x1A4_DstSubLink_MASK                               0x40
+#define D18F1x1A4_NP_OFFSET                                     7
+#define D18F1x1A4_NP_WIDTH                                      1
+#define D18F1x1A4_NP_MASK                                       0x80
+#define D18F1x1A4_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1A4_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1A4_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1A4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1A4_STRUCT;
+
+// **** D18F1x1A8 Register Definition ****
+// Address
+#define D18F1x1A8_ADDRESS                                       0x1a8
+
+// Type
+#define D18F1x1A8_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1A8_RE_OFFSET                                     0
+#define D18F1x1A8_RE_WIDTH                                      1
+#define D18F1x1A8_RE_MASK                                       0x1
+#define D18F1x1A8_WE_OFFSET                                     1
+#define D18F1x1A8_WE_WIDTH                                      1
+#define D18F1x1A8_WE_MASK                                       0x2
+#define D18F1x1A8_Reserved_2_2_OFFSET                           2
+#define D18F1x1A8_Reserved_2_2_WIDTH                            1
+#define D18F1x1A8_Reserved_2_2_MASK                             0x4
+#define D18F1x1A8_Lock_OFFSET                                   3
+#define D18F1x1A8_Lock_WIDTH                                    1
+#define D18F1x1A8_Lock_MASK                                     0x8
+#define D18F1x1A8_Reserved_7_4_OFFSET                           4
+#define D18F1x1A8_Reserved_7_4_WIDTH                            4
+#define D18F1x1A8_Reserved_7_4_MASK                             0xf0
+#define D18F1x1A8_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1A8_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1A8_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1A8_STRUCT;
+
+// **** D18F1x1AC Register Definition ****
+// Address
+#define D18F1x1AC_ADDRESS                                       0x1ac
+
+// Type
+#define D18F1x1AC_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1AC_DstNode_OFFSET                                0
+#define D18F1x1AC_DstNode_WIDTH                                 3
+#define D18F1x1AC_DstNode_MASK                                  0x7
+#define D18F1x1AC_Reserved_3_3_OFFSET                           3
+#define D18F1x1AC_Reserved_3_3_WIDTH                            1
+#define D18F1x1AC_Reserved_3_3_MASK                             0x8
+#define D18F1x1AC_DstLink_OFFSET                                4
+#define D18F1x1AC_DstLink_WIDTH                                 2
+#define D18F1x1AC_DstLink_MASK                                  0x30
+#define D18F1x1AC_DstSubLink_OFFSET                             6
+#define D18F1x1AC_DstSubLink_WIDTH                              1
+#define D18F1x1AC_DstSubLink_MASK                               0x40
+#define D18F1x1AC_NP_OFFSET                                     7
+#define D18F1x1AC_NP_WIDTH                                      1
+#define D18F1x1AC_NP_MASK                                       0x80
+#define D18F1x1AC_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1AC_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1AC_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1AC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1AC_STRUCT;
+
+// **** D18F1x1B0 Register Definition ****
+// Address
+#define D18F1x1B0_ADDRESS                                       0x1b0
+
+// Type
+#define D18F1x1B0_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1B0_RE_OFFSET                                     0
+#define D18F1x1B0_RE_WIDTH                                      1
+#define D18F1x1B0_RE_MASK                                       0x1
+#define D18F1x1B0_WE_OFFSET                                     1
+#define D18F1x1B0_WE_WIDTH                                      1
+#define D18F1x1B0_WE_MASK                                       0x2
+#define D18F1x1B0_Reserved_2_2_OFFSET                           2
+#define D18F1x1B0_Reserved_2_2_WIDTH                            1
+#define D18F1x1B0_Reserved_2_2_MASK                             0x4
+#define D18F1x1B0_Lock_OFFSET                                   3
+#define D18F1x1B0_Lock_WIDTH                                    1
+#define D18F1x1B0_Lock_MASK                                     0x8
+#define D18F1x1B0_Reserved_7_4_OFFSET                           4
+#define D18F1x1B0_Reserved_7_4_WIDTH                            4
+#define D18F1x1B0_Reserved_7_4_MASK                             0xf0
+#define D18F1x1B0_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1B0_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1B0_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1B0_STRUCT;
+
+// **** D18F1x1B4 Register Definition ****
+// Address
+#define D18F1x1B4_ADDRESS                                       0x1b4
+
+// Type
+#define D18F1x1B4_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1B4_DstNode_OFFSET                                0
+#define D18F1x1B4_DstNode_WIDTH                                 3
+#define D18F1x1B4_DstNode_MASK                                  0x7
+#define D18F1x1B4_Reserved_3_3_OFFSET                           3
+#define D18F1x1B4_Reserved_3_3_WIDTH                            1
+#define D18F1x1B4_Reserved_3_3_MASK                             0x8
+#define D18F1x1B4_DstLink_OFFSET                                4
+#define D18F1x1B4_DstLink_WIDTH                                 2
+#define D18F1x1B4_DstLink_MASK                                  0x30
+#define D18F1x1B4_DstSubLink_OFFSET                             6
+#define D18F1x1B4_DstSubLink_WIDTH                              1
+#define D18F1x1B4_DstSubLink_MASK                               0x40
+#define D18F1x1B4_NP_OFFSET                                     7
+#define D18F1x1B4_NP_WIDTH                                      1
+#define D18F1x1B4_NP_MASK                                       0x80
+#define D18F1x1B4_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1B4_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1B4_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1B4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1B4_STRUCT;
+
+// **** D18F1x1B8 Register Definition ****
+// Address
+#define D18F1x1B8_ADDRESS                                       0x1b8
+
+// Type
+#define D18F1x1B8_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1B8_RE_OFFSET                                     0
+#define D18F1x1B8_RE_WIDTH                                      1
+#define D18F1x1B8_RE_MASK                                       0x1
+#define D18F1x1B8_WE_OFFSET                                     1
+#define D18F1x1B8_WE_WIDTH                                      1
+#define D18F1x1B8_WE_MASK                                       0x2
+#define D18F1x1B8_Reserved_2_2_OFFSET                           2
+#define D18F1x1B8_Reserved_2_2_WIDTH                            1
+#define D18F1x1B8_Reserved_2_2_MASK                             0x4
+#define D18F1x1B8_Lock_OFFSET                                   3
+#define D18F1x1B8_Lock_WIDTH                                    1
+#define D18F1x1B8_Lock_MASK                                     0x8
+#define D18F1x1B8_Reserved_7_4_OFFSET                           4
+#define D18F1x1B8_Reserved_7_4_WIDTH                            4
+#define D18F1x1B8_Reserved_7_4_MASK                             0xf0
+#define D18F1x1B8_MMIOBase_39_16__OFFSET                        8
+#define D18F1x1B8_MMIOBase_39_16__WIDTH                         24
+#define D18F1x1B8_MMIOBase_39_16__MASK                          0xffffff00
+
+/// D18F1x1B8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       RE:1 ; ///<
+    UINT32                                                       WE:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                     Lock:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                          MMIOBase_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1B8_STRUCT;
+
+// **** D18F1x1BC Register Definition ****
+// Address
+#define D18F1x1BC_ADDRESS                                       0x1bc
+
+// Type
+#define D18F1x1BC_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1BC_DstNode_OFFSET                                0
+#define D18F1x1BC_DstNode_WIDTH                                 3
+#define D18F1x1BC_DstNode_MASK                                  0x7
+#define D18F1x1BC_Reserved_3_3_OFFSET                           3
+#define D18F1x1BC_Reserved_3_3_WIDTH                            1
+#define D18F1x1BC_Reserved_3_3_MASK                             0x8
+#define D18F1x1BC_DstLink_OFFSET                                4
+#define D18F1x1BC_DstLink_WIDTH                                 2
+#define D18F1x1BC_DstLink_MASK                                  0x30
+#define D18F1x1BC_DstSubLink_OFFSET                             6
+#define D18F1x1BC_DstSubLink_WIDTH                              1
+#define D18F1x1BC_DstSubLink_MASK                               0x40
+#define D18F1x1BC_NP_OFFSET                                     7
+#define D18F1x1BC_NP_WIDTH                                      1
+#define D18F1x1BC_NP_MASK                                       0x80
+#define D18F1x1BC_MMIOLimit_39_16__OFFSET                       8
+#define D18F1x1BC_MMIOLimit_39_16__WIDTH                        24
+#define D18F1x1BC_MMIOLimit_39_16__MASK                         0xffffff00
+
+/// D18F1x1BC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DstNode:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                  DstLink:2 ; ///<
+    UINT32                                               DstSubLink:1 ; ///<
+    UINT32                                                       NP:1 ; ///<
+    UINT32                                         MMIOLimit_39_16_:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1BC_STRUCT;
+
+// **** D18F1x1C0 Register Definition ****
+// Address
+#define D18F1x1C0_ADDRESS                                       0x1c0
+
+// Type
+#define D18F1x1C0_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1C0_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1C0_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1C0_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1C0_Reserved_15_8_OFFSET                          8
+#define D18F1x1C0_Reserved_15_8_WIDTH                           8
+#define D18F1x1C0_Reserved_15_8_MASK                            0xff00
+#define D18F1x1C0_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1C0_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1C0_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1C0_Reserved_31_24_OFFSET                         24
+#define D18F1x1C0_Reserved_31_24_WIDTH                          8
+#define D18F1x1C0_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1C0_STRUCT;
+
+// **** D18F1x1C4 Register Definition ****
+// Address
+#define D18F1x1C4_ADDRESS                                       0x1c4
+
+// Type
+#define D18F1x1C4_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1C4_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1C4_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1C4_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1C4_Reserved_15_8_OFFSET                          8
+#define D18F1x1C4_Reserved_15_8_WIDTH                           8
+#define D18F1x1C4_Reserved_15_8_MASK                            0xff00
+#define D18F1x1C4_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1C4_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1C4_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1C4_Reserved_31_24_OFFSET                         24
+#define D18F1x1C4_Reserved_31_24_WIDTH                          8
+#define D18F1x1C4_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1C4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1C4_STRUCT;
+
+// **** D18F1x1C8 Register Definition ****
+// Address
+#define D18F1x1C8_ADDRESS                                       0x1c8
+
+// Type
+#define D18F1x1C8_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1C8_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1C8_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1C8_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1C8_Reserved_15_8_OFFSET                          8
+#define D18F1x1C8_Reserved_15_8_WIDTH                           8
+#define D18F1x1C8_Reserved_15_8_MASK                            0xff00
+#define D18F1x1C8_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1C8_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1C8_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1C8_Reserved_31_24_OFFSET                         24
+#define D18F1x1C8_Reserved_31_24_WIDTH                          8
+#define D18F1x1C8_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1C8_STRUCT;
+
+// **** D18F1x1CC Register Definition ****
+// Address
+#define D18F1x1CC_ADDRESS                                       0x1cc
+
+// Type
+#define D18F1x1CC_TYPE                                          TYPE_D18F1
+// Field Data
+#define D18F1x1CC_MMIOBase_47_40__OFFSET                        0
+#define D18F1x1CC_MMIOBase_47_40__WIDTH                         8
+#define D18F1x1CC_MMIOBase_47_40__MASK                          0xff
+#define D18F1x1CC_Reserved_15_8_OFFSET                          8
+#define D18F1x1CC_Reserved_15_8_WIDTH                           8
+#define D18F1x1CC_Reserved_15_8_MASK                            0xff00
+#define D18F1x1CC_MMIOLimit_47_40__OFFSET                       16
+#define D18F1x1CC_MMIOLimit_47_40__WIDTH                        8
+#define D18F1x1CC_MMIOLimit_47_40__MASK                         0xff0000
+#define D18F1x1CC_Reserved_31_24_OFFSET                         24
+#define D18F1x1CC_Reserved_31_24_WIDTH                          8
+#define D18F1x1CC_Reserved_31_24_MASK                           0xff000000
+
+/// D18F1x1CC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          MMIOBase_47_40_:8 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                         MMIOLimit_47_40_:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F1x1CC_STRUCT;
+
+// **** D18F2x00 Register Definition ****
+// Address
+#define D18F2x00_ADDRESS                                        0x0
+
+// Type
+#define D18F2x00_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x00_VendorID_OFFSET                                0
+#define D18F2x00_VendorID_WIDTH                                 16
+#define D18F2x00_VendorID_MASK                                  0xffff
+#define D18F2x00_DeviceID_OFFSET                                16
+#define D18F2x00_DeviceID_WIDTH                                 16
+#define D18F2x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F2x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x00_STRUCT;
+
+// **** D18F2x08 Register Definition ****
+// Address
+#define D18F2x08_ADDRESS                                        0x8
+
+// Type
+#define D18F2x08_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x08_RevID_OFFSET                                   0
+#define D18F2x08_RevID_WIDTH                                    8
+#define D18F2x08_RevID_MASK                                     0xff
+#define D18F2x08_ClassCode_OFFSET                               8
+#define D18F2x08_ClassCode_WIDTH                                24
+#define D18F2x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F2x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x08_STRUCT;
+
+// **** D18F2x0C Register Definition ****
+// Address
+#define D18F2x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F2x0C_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2x0C_HeaderTypeReg_OFFSET                           0
+#define D18F2x0C_HeaderTypeReg_WIDTH                            32
+#define D18F2x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F2x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x0C_STRUCT;
+
+// **** D18F2x40_dct1 Register Definition ****
+// Address
+#define D18F2x40_dct1_ADDRESS                                   0x40
+
+// Type
+#define D18F2x40_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x40_dct1_CSEnable_OFFSET                           0
+#define D18F2x40_dct1_CSEnable_WIDTH                            1
+#define D18F2x40_dct1_CSEnable_MASK                             0x1
+#define D18F2x40_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x40_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x40_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x40_dct1_TestFail_OFFSET                           2
+#define D18F2x40_dct1_TestFail_WIDTH                            1
+#define D18F2x40_dct1_TestFail_MASK                             0x4
+#define D18F2x40_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x40_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x40_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x40_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x40_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x40_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x40_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x40_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x40_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x40_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x40_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x40_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x40_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x40_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x40_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x40_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x40_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x40_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x40_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x40_dct1_STRUCT;
+
+// **** D18F2x40_dct0 Register Definition ****
+// Address
+#define D18F2x40_dct0_ADDRESS                                   0x40
+
+// Type
+#define D18F2x40_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x40_dct0_CSEnable_OFFSET                           0
+#define D18F2x40_dct0_CSEnable_WIDTH                            1
+#define D18F2x40_dct0_CSEnable_MASK                             0x1
+#define D18F2x40_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x40_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x40_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x40_dct0_TestFail_OFFSET                           2
+#define D18F2x40_dct0_TestFail_WIDTH                            1
+#define D18F2x40_dct0_TestFail_MASK                             0x4
+#define D18F2x40_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x40_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x40_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x40_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x40_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x40_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x40_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x40_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x40_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x40_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x40_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x40_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x40_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x40_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x40_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x40_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x40_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x40_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x40_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x40_dct0_STRUCT;
+
+// **** D18F2x44_dct1 Register Definition ****
+// Address
+#define D18F2x44_dct1_ADDRESS                                   0x44
+
+// Type
+#define D18F2x44_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x44_dct1_CSEnable_OFFSET                           0
+#define D18F2x44_dct1_CSEnable_WIDTH                            1
+#define D18F2x44_dct1_CSEnable_MASK                             0x1
+#define D18F2x44_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x44_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x44_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x44_dct1_TestFail_OFFSET                           2
+#define D18F2x44_dct1_TestFail_WIDTH                            1
+#define D18F2x44_dct1_TestFail_MASK                             0x4
+#define D18F2x44_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x44_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x44_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x44_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x44_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x44_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x44_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x44_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x44_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x44_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x44_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x44_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x44_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x44_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x44_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x44_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x44_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x44_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x44_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x44_dct1_STRUCT;
+
+// **** D18F2x44_dct0 Register Definition ****
+// Address
+#define D18F2x44_dct0_ADDRESS                                   0x44
+
+// Type
+#define D18F2x44_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x44_dct0_CSEnable_OFFSET                           0
+#define D18F2x44_dct0_CSEnable_WIDTH                            1
+#define D18F2x44_dct0_CSEnable_MASK                             0x1
+#define D18F2x44_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x44_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x44_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x44_dct0_TestFail_OFFSET                           2
+#define D18F2x44_dct0_TestFail_WIDTH                            1
+#define D18F2x44_dct0_TestFail_MASK                             0x4
+#define D18F2x44_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x44_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x44_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x44_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x44_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x44_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x44_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x44_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x44_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x44_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x44_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x44_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x44_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x44_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x44_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x44_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x44_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x44_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x44_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x44_dct0_STRUCT;
+
+// **** D18F2x48_dct1 Register Definition ****
+// Address
+#define D18F2x48_dct1_ADDRESS                                   0x48
+
+// Type
+#define D18F2x48_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x48_dct1_CSEnable_OFFSET                           0
+#define D18F2x48_dct1_CSEnable_WIDTH                            1
+#define D18F2x48_dct1_CSEnable_MASK                             0x1
+#define D18F2x48_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x48_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x48_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x48_dct1_TestFail_OFFSET                           2
+#define D18F2x48_dct1_TestFail_WIDTH                            1
+#define D18F2x48_dct1_TestFail_MASK                             0x4
+#define D18F2x48_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x48_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x48_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x48_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x48_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x48_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x48_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x48_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x48_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x48_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x48_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x48_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x48_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x48_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x48_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x48_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x48_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x48_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x48_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x48_dct1_STRUCT;
+
+// **** D18F2x48_dct0 Register Definition ****
+// Address
+#define D18F2x48_dct0_ADDRESS                                   0x48
+
+// Type
+#define D18F2x48_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x48_dct0_CSEnable_OFFSET                           0
+#define D18F2x48_dct0_CSEnable_WIDTH                            1
+#define D18F2x48_dct0_CSEnable_MASK                             0x1
+#define D18F2x48_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x48_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x48_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x48_dct0_TestFail_OFFSET                           2
+#define D18F2x48_dct0_TestFail_WIDTH                            1
+#define D18F2x48_dct0_TestFail_MASK                             0x4
+#define D18F2x48_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x48_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x48_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x48_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x48_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x48_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x48_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x48_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x48_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x48_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x48_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x48_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x48_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x48_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x48_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x48_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x48_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x48_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x48_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x48_dct0_STRUCT;
+
+// **** D18F2x4C_dct1 Register Definition ****
+// Address
+#define D18F2x4C_dct1_ADDRESS                                   0x4c
+
+// Type
+#define D18F2x4C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x4C_dct1_CSEnable_OFFSET                           0
+#define D18F2x4C_dct1_CSEnable_WIDTH                            1
+#define D18F2x4C_dct1_CSEnable_MASK                             0x1
+#define D18F2x4C_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x4C_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x4C_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x4C_dct1_TestFail_OFFSET                           2
+#define D18F2x4C_dct1_TestFail_WIDTH                            1
+#define D18F2x4C_dct1_TestFail_MASK                             0x4
+#define D18F2x4C_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x4C_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x4C_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x4C_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x4C_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x4C_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x4C_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x4C_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x4C_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x4C_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x4C_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x4C_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x4C_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x4C_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x4C_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x4C_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x4C_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x4C_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x4C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x4C_dct1_STRUCT;
+
+// **** D18F2x4C_dct0 Register Definition ****
+// Address
+#define D18F2x4C_dct0_ADDRESS                                   0x4c
+
+// Type
+#define D18F2x4C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x4C_dct0_CSEnable_OFFSET                           0
+#define D18F2x4C_dct0_CSEnable_WIDTH                            1
+#define D18F2x4C_dct0_CSEnable_MASK                             0x1
+#define D18F2x4C_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x4C_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x4C_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x4C_dct0_TestFail_OFFSET                           2
+#define D18F2x4C_dct0_TestFail_WIDTH                            1
+#define D18F2x4C_dct0_TestFail_MASK                             0x4
+#define D18F2x4C_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x4C_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x4C_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x4C_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x4C_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x4C_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x4C_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x4C_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x4C_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x4C_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x4C_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x4C_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x4C_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x4C_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x4C_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x4C_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x4C_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x4C_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x4C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x4C_dct0_STRUCT;
+
+// **** D18F2x50_dct1 Register Definition ****
+// Address
+#define D18F2x50_dct1_ADDRESS                                   0x50
+
+// Type
+#define D18F2x50_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x50_dct1_CSEnable_OFFSET                           0
+#define D18F2x50_dct1_CSEnable_WIDTH                            1
+#define D18F2x50_dct1_CSEnable_MASK                             0x1
+#define D18F2x50_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x50_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x50_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x50_dct1_TestFail_OFFSET                           2
+#define D18F2x50_dct1_TestFail_WIDTH                            1
+#define D18F2x50_dct1_TestFail_MASK                             0x4
+#define D18F2x50_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x50_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x50_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x50_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x50_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x50_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x50_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x50_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x50_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x50_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x50_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x50_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x50_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x50_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x50_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x50_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x50_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x50_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x50_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x50_dct1_STRUCT;
+
+// **** D18F2x50_dct0 Register Definition ****
+// Address
+#define D18F2x50_dct0_ADDRESS                                   0x50
+
+// Type
+#define D18F2x50_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x50_dct0_CSEnable_OFFSET                           0
+#define D18F2x50_dct0_CSEnable_WIDTH                            1
+#define D18F2x50_dct0_CSEnable_MASK                             0x1
+#define D18F2x50_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x50_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x50_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x50_dct0_TestFail_OFFSET                           2
+#define D18F2x50_dct0_TestFail_WIDTH                            1
+#define D18F2x50_dct0_TestFail_MASK                             0x4
+#define D18F2x50_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x50_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x50_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x50_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x50_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x50_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x50_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x50_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x50_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x50_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x50_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x50_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x50_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x50_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x50_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x50_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x50_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x50_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x50_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x50_dct0_STRUCT;
+
+// **** D18F2x54_dct0 Register Definition ****
+// Address
+#define D18F2x54_dct0_ADDRESS                                   0x54
+
+// Type
+#define D18F2x54_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x54_dct0_CSEnable_OFFSET                           0
+#define D18F2x54_dct0_CSEnable_WIDTH                            1
+#define D18F2x54_dct0_CSEnable_MASK                             0x1
+#define D18F2x54_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x54_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x54_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x54_dct0_TestFail_OFFSET                           2
+#define D18F2x54_dct0_TestFail_WIDTH                            1
+#define D18F2x54_dct0_TestFail_MASK                             0x4
+#define D18F2x54_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x54_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x54_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x54_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x54_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x54_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x54_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x54_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x54_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x54_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x54_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x54_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x54_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x54_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x54_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x54_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x54_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x54_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x54_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x54_dct0_STRUCT;
+
+// **** D18F2x54_dct1 Register Definition ****
+// Address
+#define D18F2x54_dct1_ADDRESS                                   0x54
+
+// Type
+#define D18F2x54_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x54_dct1_CSEnable_OFFSET                           0
+#define D18F2x54_dct1_CSEnable_WIDTH                            1
+#define D18F2x54_dct1_CSEnable_MASK                             0x1
+#define D18F2x54_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x54_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x54_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x54_dct1_TestFail_OFFSET                           2
+#define D18F2x54_dct1_TestFail_WIDTH                            1
+#define D18F2x54_dct1_TestFail_MASK                             0x4
+#define D18F2x54_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x54_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x54_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x54_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x54_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x54_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x54_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x54_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x54_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x54_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x54_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x54_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x54_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x54_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x54_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x54_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x54_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x54_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x54_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x54_dct1_STRUCT;
+
+// **** D18F2x58_dct1 Register Definition ****
+// Address
+#define D18F2x58_dct1_ADDRESS                                   0x58
+
+// Type
+#define D18F2x58_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x58_dct1_CSEnable_OFFSET                           0
+#define D18F2x58_dct1_CSEnable_WIDTH                            1
+#define D18F2x58_dct1_CSEnable_MASK                             0x1
+#define D18F2x58_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x58_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x58_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x58_dct1_TestFail_OFFSET                           2
+#define D18F2x58_dct1_TestFail_WIDTH                            1
+#define D18F2x58_dct1_TestFail_MASK                             0x4
+#define D18F2x58_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x58_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x58_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x58_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x58_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x58_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x58_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x58_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x58_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x58_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x58_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x58_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x58_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x58_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x58_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x58_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x58_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x58_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x58_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x58_dct1_STRUCT;
+
+// **** D18F2x58_dct0 Register Definition ****
+// Address
+#define D18F2x58_dct0_ADDRESS                                   0x58
+
+// Type
+#define D18F2x58_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x58_dct0_CSEnable_OFFSET                           0
+#define D18F2x58_dct0_CSEnable_WIDTH                            1
+#define D18F2x58_dct0_CSEnable_MASK                             0x1
+#define D18F2x58_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x58_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x58_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x58_dct0_TestFail_OFFSET                           2
+#define D18F2x58_dct0_TestFail_WIDTH                            1
+#define D18F2x58_dct0_TestFail_MASK                             0x4
+#define D18F2x58_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x58_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x58_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x58_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x58_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x58_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x58_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x58_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x58_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x58_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x58_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x58_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x58_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x58_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x58_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x58_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x58_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x58_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x58_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x58_dct0_STRUCT;
+
+// **** D18F2x5C_dct1 Register Definition ****
+// Address
+#define D18F2x5C_dct1_ADDRESS                                   0x5c
+
+// Type
+#define D18F2x5C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x5C_dct1_CSEnable_OFFSET                           0
+#define D18F2x5C_dct1_CSEnable_WIDTH                            1
+#define D18F2x5C_dct1_CSEnable_MASK                             0x1
+#define D18F2x5C_dct1_Reserved_1_1_OFFSET                       1
+#define D18F2x5C_dct1_Reserved_1_1_WIDTH                        1
+#define D18F2x5C_dct1_Reserved_1_1_MASK                         0x2
+#define D18F2x5C_dct1_TestFail_OFFSET                           2
+#define D18F2x5C_dct1_TestFail_WIDTH                            1
+#define D18F2x5C_dct1_TestFail_MASK                             0x4
+#define D18F2x5C_dct1_OnDimmMirror_OFFSET                       3
+#define D18F2x5C_dct1_OnDimmMirror_WIDTH                        1
+#define D18F2x5C_dct1_OnDimmMirror_MASK                         0x8
+#define D18F2x5C_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2x5C_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2x5C_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2x5C_dct1_BaseAddr_21_11__OFFSET                    5
+#define D18F2x5C_dct1_BaseAddr_21_11__WIDTH                     11
+#define D18F2x5C_dct1_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x5C_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x5C_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x5C_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x5C_dct1_BaseAddr_38_27__OFFSET                    19
+#define D18F2x5C_dct1_BaseAddr_38_27__WIDTH                     12
+#define D18F2x5C_dct1_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x5C_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x5C_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x5C_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x5C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x5C_dct1_STRUCT;
+
+// **** D18F2x5C_dct0 Register Definition ****
+// Address
+#define D18F2x5C_dct0_ADDRESS                                   0x5c
+
+// Type
+#define D18F2x5C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x5C_dct0_CSEnable_OFFSET                           0
+#define D18F2x5C_dct0_CSEnable_WIDTH                            1
+#define D18F2x5C_dct0_CSEnable_MASK                             0x1
+#define D18F2x5C_dct0_Reserved_1_1_OFFSET                       1
+#define D18F2x5C_dct0_Reserved_1_1_WIDTH                        1
+#define D18F2x5C_dct0_Reserved_1_1_MASK                         0x2
+#define D18F2x5C_dct0_TestFail_OFFSET                           2
+#define D18F2x5C_dct0_TestFail_WIDTH                            1
+#define D18F2x5C_dct0_TestFail_MASK                             0x4
+#define D18F2x5C_dct0_OnDimmMirror_OFFSET                       3
+#define D18F2x5C_dct0_OnDimmMirror_WIDTH                        1
+#define D18F2x5C_dct0_OnDimmMirror_MASK                         0x8
+#define D18F2x5C_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2x5C_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2x5C_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2x5C_dct0_BaseAddr_21_11__OFFSET                    5
+#define D18F2x5C_dct0_BaseAddr_21_11__WIDTH                     11
+#define D18F2x5C_dct0_BaseAddr_21_11__MASK                      0xffe0
+#define D18F2x5C_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x5C_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x5C_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x5C_dct0_BaseAddr_38_27__OFFSET                    19
+#define D18F2x5C_dct0_BaseAddr_38_27__WIDTH                     12
+#define D18F2x5C_dct0_BaseAddr_38_27__MASK                      0x7ff80000
+#define D18F2x5C_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x5C_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x5C_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x5C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSEnable:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                                 TestFail:1 ; ///<
+    UINT32                                             OnDimmMirror:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          BaseAddr_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          BaseAddr_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x5C_dct0_STRUCT;
+
+// **** D18F2x60_dct1 Register Definition ****
+// Address
+#define D18F2x60_dct1_ADDRESS                                   0x60
+
+// Type
+#define D18F2x60_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x60_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x60_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x60_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x60_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x60_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x60_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x60_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x60_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x60_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x60_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x60_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x60_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x60_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x60_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x60_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x60_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x60_dct1_STRUCT;
+
+// **** D18F2x60_dct0 Register Definition ****
+// Address
+#define D18F2x60_dct0_ADDRESS                                   0x60
+
+// Type
+#define D18F2x60_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x60_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x60_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x60_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x60_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x60_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x60_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x60_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x60_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x60_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x60_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x60_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x60_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x60_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x60_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x60_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x60_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x60_dct0_STRUCT;
+
+// **** D18F2x64_dct0 Register Definition ****
+// Address
+#define D18F2x64_dct0_ADDRESS                                   0x64
+
+// Type
+#define D18F2x64_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x64_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x64_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x64_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x64_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x64_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x64_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x64_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x64_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x64_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x64_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x64_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x64_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x64_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x64_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x64_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x64_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x64_dct0_STRUCT;
+
+// **** D18F2x64_dct1 Register Definition ****
+// Address
+#define D18F2x64_dct1_ADDRESS                                   0x64
+
+// Type
+#define D18F2x64_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x64_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x64_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x64_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x64_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x64_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x64_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x64_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x64_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x64_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x64_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x64_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x64_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x64_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x64_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x64_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x64_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x64_dct1_STRUCT;
+
+// **** D18F2x68_dct1 Register Definition ****
+// Address
+#define D18F2x68_dct1_ADDRESS                                   0x68
+
+// Type
+#define D18F2x68_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x68_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x68_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x68_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x68_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x68_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x68_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x68_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x68_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x68_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x68_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x68_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x68_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x68_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x68_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x68_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x68_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x68_dct1_STRUCT;
+
+// **** D18F2x68_dct0 Register Definition ****
+// Address
+#define D18F2x68_dct0_ADDRESS                                   0x68
+
+// Type
+#define D18F2x68_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x68_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x68_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x68_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x68_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x68_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x68_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x68_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x68_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x68_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x68_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x68_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x68_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x68_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x68_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x68_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x68_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x68_dct0_STRUCT;
+
+// **** D18F2x6C_dct1 Register Definition ****
+// Address
+#define D18F2x6C_dct1_ADDRESS                                   0x6c
+
+// Type
+#define D18F2x6C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x6C_dct1_Reserved_4_0_OFFSET                       0
+#define D18F2x6C_dct1_Reserved_4_0_WIDTH                        5
+#define D18F2x6C_dct1_Reserved_4_0_MASK                         0x1f
+#define D18F2x6C_dct1_AddrMask_21_11__OFFSET                    5
+#define D18F2x6C_dct1_AddrMask_21_11__WIDTH                     11
+#define D18F2x6C_dct1_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x6C_dct1_Reserved_18_16_OFFSET                     16
+#define D18F2x6C_dct1_Reserved_18_16_WIDTH                      3
+#define D18F2x6C_dct1_Reserved_18_16_MASK                       0x70000
+#define D18F2x6C_dct1_AddrMask_38_27__OFFSET                    19
+#define D18F2x6C_dct1_AddrMask_38_27__WIDTH                     12
+#define D18F2x6C_dct1_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x6C_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x6C_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x6C_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x6C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x6C_dct1_STRUCT;
+
+// **** D18F2x6C_dct0 Register Definition ****
+// Address
+#define D18F2x6C_dct0_ADDRESS                                   0x6c
+
+// Type
+#define D18F2x6C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x6C_dct0_Reserved_4_0_OFFSET                       0
+#define D18F2x6C_dct0_Reserved_4_0_WIDTH                        5
+#define D18F2x6C_dct0_Reserved_4_0_MASK                         0x1f
+#define D18F2x6C_dct0_AddrMask_21_11__OFFSET                    5
+#define D18F2x6C_dct0_AddrMask_21_11__WIDTH                     11
+#define D18F2x6C_dct0_AddrMask_21_11__MASK                      0xffe0
+#define D18F2x6C_dct0_Reserved_18_16_OFFSET                     16
+#define D18F2x6C_dct0_Reserved_18_16_WIDTH                      3
+#define D18F2x6C_dct0_Reserved_18_16_MASK                       0x70000
+#define D18F2x6C_dct0_AddrMask_38_27__OFFSET                    19
+#define D18F2x6C_dct0_AddrMask_38_27__WIDTH                     12
+#define D18F2x6C_dct0_AddrMask_38_27__MASK                      0x7ff80000
+#define D18F2x6C_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x6C_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x6C_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x6C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          AddrMask_21_11_:11; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                          AddrMask_38_27_:12; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x6C_dct0_STRUCT;
+
+// **** D18F2x78_dct0 Register Definition ****
+// Address
+#define D18F2x78_dct0_ADDRESS                                   0x78
+
+// Type
+#define D18F2x78_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x78_dct0_Reserved_16_0_OFFSET                      0
+#define D18F2x78_dct0_Reserved_16_0_WIDTH                       17
+#define D18F2x78_dct0_Reserved_16_0_MASK                        0x1ffff
+#define D18F2x78_dct0_AddrCmdTriEn_OFFSET                       17
+#define D18F2x78_dct0_AddrCmdTriEn_WIDTH                        1
+#define D18F2x78_dct0_AddrCmdTriEn_MASK                         0x20000
+#define D18F2x78_dct0_Reserved_31_18_OFFSET                     18
+#define D18F2x78_dct0_Reserved_31_18_WIDTH                      14
+#define D18F2x78_dct0_Reserved_31_18_MASK                       0xfffc0000
+
+/// D18F2x78_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_16_0:17; ///<
+    UINT32                                             AddrCmdTriEn:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x78_dct0_STRUCT;
+
+// **** D18F2x78_dct1 Register Definition ****
+// Address
+#define D18F2x78_dct1_ADDRESS                                   0x78
+
+// Type
+#define D18F2x78_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x78_dct1_Reserved_16_0_OFFSET                      0
+#define D18F2x78_dct1_Reserved_16_0_WIDTH                       17
+#define D18F2x78_dct1_Reserved_16_0_MASK                        0x1ffff
+#define D18F2x78_dct1_AddrCmdTriEn_OFFSET                       17
+#define D18F2x78_dct1_AddrCmdTriEn_WIDTH                        1
+#define D18F2x78_dct1_AddrCmdTriEn_MASK                         0x20000
+#define D18F2x78_dct1_Reserved_31_18_OFFSET                     18
+#define D18F2x78_dct1_Reserved_31_18_WIDTH                      14
+#define D18F2x78_dct1_Reserved_31_18_MASK                       0xfffc0000
+
+/// D18F2x78_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_16_0:17; ///<
+    UINT32                                             AddrCmdTriEn:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x78_dct1_STRUCT;
+
+// **** D18F2x7C_dct1 Register Definition ****
+// Address
+#define D18F2x7C_dct1_ADDRESS                                   0x7c
+
+// Type
+#define D18F2x7C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x7C_dct1_MrsAddress_17_0__OFFSET                   0
+#define D18F2x7C_dct1_MrsAddress_17_0__WIDTH                    18
+#define D18F2x7C_dct1_MrsAddress_17_0__MASK                     0x3ffff
+#define D18F2x7C_dct1_MrsBank_2_0__OFFSET                       18
+#define D18F2x7C_dct1_MrsBank_2_0__WIDTH                        3
+#define D18F2x7C_dct1_MrsBank_2_0__MASK                         0x1c0000
+#define D18F2x7C_dct1_MrsChipSel_OFFSET                         21
+#define D18F2x7C_dct1_MrsChipSel_WIDTH                          3
+#define D18F2x7C_dct1_MrsChipSel_MASK                           0xe00000
+#define D18F2x7C_dct1_Reserved_24_24_OFFSET                     24
+#define D18F2x7C_dct1_Reserved_24_24_WIDTH                      1
+#define D18F2x7C_dct1_Reserved_24_24_MASK                       0x1000000
+#define D18F2x7C_dct1_SendAutoRefresh_OFFSET                    25
+#define D18F2x7C_dct1_SendAutoRefresh_WIDTH                     1
+#define D18F2x7C_dct1_SendAutoRefresh_MASK                      0x2000000
+#define D18F2x7C_dct1_SendMrsCmd_OFFSET                         26
+#define D18F2x7C_dct1_SendMrsCmd_WIDTH                          1
+#define D18F2x7C_dct1_SendMrsCmd_MASK                           0x4000000
+#define D18F2x7C_dct1_DeassertMemRstX_OFFSET                    27
+#define D18F2x7C_dct1_DeassertMemRstX_WIDTH                     1
+#define D18F2x7C_dct1_DeassertMemRstX_MASK                      0x8000000
+#define D18F2x7C_dct1_AssertCke_OFFSET                          28
+#define D18F2x7C_dct1_AssertCke_WIDTH                           1
+#define D18F2x7C_dct1_AssertCke_MASK                            0x10000000
+#define D18F2x7C_dct1_SendZQCmd_OFFSET                          29
+#define D18F2x7C_dct1_SendZQCmd_WIDTH                           1
+#define D18F2x7C_dct1_SendZQCmd_MASK                            0x20000000
+#define D18F2x7C_dct1_SendControlWord_OFFSET                    30
+#define D18F2x7C_dct1_SendControlWord_WIDTH                     1
+#define D18F2x7C_dct1_SendControlWord_MASK                      0x40000000
+#define D18F2x7C_dct1_EnDramInit_OFFSET                         31
+#define D18F2x7C_dct1_EnDramInit_WIDTH                          1
+#define D18F2x7C_dct1_EnDramInit_MASK                           0x80000000
+
+/// D18F2x7C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         MrsAddress_17_0_:18; ///<
+    UINT32                                             MrsBank_2_0_:3 ; ///<
+    UINT32                                               MrsChipSel:3 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                          SendAutoRefresh:1 ; ///<
+    UINT32                                               SendMrsCmd:1 ; ///<
+    UINT32                                          DeassertMemRstX:1 ; ///<
+    UINT32                                                AssertCke:1 ; ///<
+    UINT32                                                SendZQCmd:1 ; ///<
+    UINT32                                          SendControlWord:1 ; ///<
+    UINT32                                               EnDramInit:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x7C_dct1_STRUCT;
+
+// **** D18F2x7C_dct0 Register Definition ****
+// Address
+#define D18F2x7C_dct0_ADDRESS                                   0x7c
+
+// Type
+#define D18F2x7C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x7C_dct0_MrsAddress_17_0__OFFSET                   0
+#define D18F2x7C_dct0_MrsAddress_17_0__WIDTH                    18
+#define D18F2x7C_dct0_MrsAddress_17_0__MASK                     0x3ffff
+#define D18F2x7C_dct0_MrsBank_2_0__OFFSET                       18
+#define D18F2x7C_dct0_MrsBank_2_0__WIDTH                        3
+#define D18F2x7C_dct0_MrsBank_2_0__MASK                         0x1c0000
+#define D18F2x7C_dct0_MrsChipSel_OFFSET                         21
+#define D18F2x7C_dct0_MrsChipSel_WIDTH                          3
+#define D18F2x7C_dct0_MrsChipSel_MASK                           0xe00000
+#define D18F2x7C_dct0_Reserved_24_24_OFFSET                     24
+#define D18F2x7C_dct0_Reserved_24_24_WIDTH                      1
+#define D18F2x7C_dct0_Reserved_24_24_MASK                       0x1000000
+#define D18F2x7C_dct0_SendAutoRefresh_OFFSET                    25
+#define D18F2x7C_dct0_SendAutoRefresh_WIDTH                     1
+#define D18F2x7C_dct0_SendAutoRefresh_MASK                      0x2000000
+#define D18F2x7C_dct0_SendMrsCmd_OFFSET                         26
+#define D18F2x7C_dct0_SendMrsCmd_WIDTH                          1
+#define D18F2x7C_dct0_SendMrsCmd_MASK                           0x4000000
+#define D18F2x7C_dct0_DeassertMemRstX_OFFSET                    27
+#define D18F2x7C_dct0_DeassertMemRstX_WIDTH                     1
+#define D18F2x7C_dct0_DeassertMemRstX_MASK                      0x8000000
+#define D18F2x7C_dct0_AssertCke_OFFSET                          28
+#define D18F2x7C_dct0_AssertCke_WIDTH                           1
+#define D18F2x7C_dct0_AssertCke_MASK                            0x10000000
+#define D18F2x7C_dct0_SendZQCmd_OFFSET                          29
+#define D18F2x7C_dct0_SendZQCmd_WIDTH                           1
+#define D18F2x7C_dct0_SendZQCmd_MASK                            0x20000000
+#define D18F2x7C_dct0_SendControlWord_OFFSET                    30
+#define D18F2x7C_dct0_SendControlWord_WIDTH                     1
+#define D18F2x7C_dct0_SendControlWord_MASK                      0x40000000
+#define D18F2x7C_dct0_EnDramInit_OFFSET                         31
+#define D18F2x7C_dct0_EnDramInit_WIDTH                          1
+#define D18F2x7C_dct0_EnDramInit_MASK                           0x80000000
+
+/// D18F2x7C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         MrsAddress_17_0_:18; ///<
+    UINT32                                             MrsBank_2_0_:3 ; ///<
+    UINT32                                               MrsChipSel:3 ; ///<
+    UINT32                                           Reserved_24_24:1 ; ///<
+    UINT32                                          SendAutoRefresh:1 ; ///<
+    UINT32                                               SendMrsCmd:1 ; ///<
+    UINT32                                          DeassertMemRstX:1 ; ///<
+    UINT32                                                AssertCke:1 ; ///<
+    UINT32                                                SendZQCmd:1 ; ///<
+    UINT32                                          SendControlWord:1 ; ///<
+    UINT32                                               EnDramInit:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x7C_dct0_STRUCT;
+
+// **** D18F2x80_dct1 Register Definition ****
+// Address
+#define D18F2x80_dct1_ADDRESS                                   0x80
+
+// Type
+#define D18F2x80_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x80_dct1_DimmAddrMap0_OFFSET                       0
+#define D18F2x80_dct1_DimmAddrMap0_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap0_MASK                         0xf
+#define D18F2x80_dct1_DimmAddrMap1_OFFSET                       4
+#define D18F2x80_dct1_DimmAddrMap1_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap1_MASK                         0xf0
+#define D18F2x80_dct1_DimmAddrMap2_OFFSET                       8
+#define D18F2x80_dct1_DimmAddrMap2_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap2_MASK                         0xf00
+#define D18F2x80_dct1_DimmAddrMap3_OFFSET                       12
+#define D18F2x80_dct1_DimmAddrMap3_WIDTH                        4
+#define D18F2x80_dct1_DimmAddrMap3_MASK                         0xf000
+#define D18F2x80_dct1_Reserved_31_16_OFFSET                     16
+#define D18F2x80_dct1_Reserved_31_16_WIDTH                      16
+#define D18F2x80_dct1_Reserved_31_16_MASK                       0xffff0000
+
+/// D18F2x80_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DimmAddrMap0:4 ; ///<
+    UINT32                                             DimmAddrMap1:4 ; ///<
+    UINT32                                             DimmAddrMap2:4 ; ///<
+    UINT32                                             DimmAddrMap3:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x80_dct1_STRUCT;
+
+// **** D18F2x80_dct0 Register Definition ****
+// Address
+#define D18F2x80_dct0_ADDRESS                                   0x80
+
+// Type
+#define D18F2x80_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x80_dct0_DimmAddrMap0_OFFSET                       0
+#define D18F2x80_dct0_DimmAddrMap0_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap0_MASK                         0xf
+#define D18F2x80_dct0_DimmAddrMap1_OFFSET                       4
+#define D18F2x80_dct0_DimmAddrMap1_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap1_MASK                         0xf0
+#define D18F2x80_dct0_DimmAddrMap2_OFFSET                       8
+#define D18F2x80_dct0_DimmAddrMap2_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap2_MASK                         0xf00
+#define D18F2x80_dct0_DimmAddrMap3_OFFSET                       12
+#define D18F2x80_dct0_DimmAddrMap3_WIDTH                        4
+#define D18F2x80_dct0_DimmAddrMap3_MASK                         0xf000
+#define D18F2x80_dct0_Reserved_31_16_OFFSET                     16
+#define D18F2x80_dct0_Reserved_31_16_WIDTH                      16
+#define D18F2x80_dct0_Reserved_31_16_MASK                       0xffff0000
+
+/// D18F2x80_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DimmAddrMap0:4 ; ///<
+    UINT32                                             DimmAddrMap1:4 ; ///<
+    UINT32                                             DimmAddrMap2:4 ; ///<
+    UINT32                                             DimmAddrMap3:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x80_dct0_STRUCT;
+
+// **** D18F2x84_dct1 Register Definition ****
+// Address
+#define D18F2x84_dct1_ADDRESS                                   0x84
+
+// Type
+#define D18F2x84_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x84_dct1_BurstCtrl_OFFSET                          0
+#define D18F2x84_dct1_BurstCtrl_WIDTH                           2
+#define D18F2x84_dct1_BurstCtrl_MASK                            0x3
+#define D18F2x84_dct1_Reserved_22_2_OFFSET                      2
+#define D18F2x84_dct1_Reserved_22_2_WIDTH                       21
+#define D18F2x84_dct1_Reserved_22_2_MASK                        0x7ffffc
+#define D18F2x84_dct1_PchgPDModeSel_OFFSET                      23
+#define D18F2x84_dct1_PchgPDModeSel_WIDTH                       1
+#define D18F2x84_dct1_PchgPDModeSel_MASK                        0x800000
+#define D18F2x84_dct1_Reserved_31_24_OFFSET                     24
+#define D18F2x84_dct1_Reserved_31_24_WIDTH                      8
+#define D18F2x84_dct1_Reserved_31_24_MASK                       0xff000000
+
+/// D18F2x84_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                BurstCtrl:2 ; ///<
+    UINT32                                            Reserved_22_2:21; ///<
+    UINT32                                            PchgPDModeSel:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x84_dct1_STRUCT;
+
+// **** D18F2x84_dct0 Register Definition ****
+// Address
+#define D18F2x84_dct0_ADDRESS                                   0x84
+
+// Type
+#define D18F2x84_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x84_dct0_BurstCtrl_OFFSET                          0
+#define D18F2x84_dct0_BurstCtrl_WIDTH                           2
+#define D18F2x84_dct0_BurstCtrl_MASK                            0x3
+#define D18F2x84_dct0_Reserved_22_2_OFFSET                      2
+#define D18F2x84_dct0_Reserved_22_2_WIDTH                       21
+#define D18F2x84_dct0_Reserved_22_2_MASK                        0x7ffffc
+#define D18F2x84_dct0_PchgPDModeSel_OFFSET                      23
+#define D18F2x84_dct0_PchgPDModeSel_WIDTH                       1
+#define D18F2x84_dct0_PchgPDModeSel_MASK                        0x800000
+#define D18F2x84_dct0_Reserved_31_24_OFFSET                     24
+#define D18F2x84_dct0_Reserved_31_24_WIDTH                      8
+#define D18F2x84_dct0_Reserved_31_24_MASK                       0xff000000
+
+/// D18F2x84_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                BurstCtrl:2 ; ///<
+    UINT32                                            Reserved_22_2:21; ///<
+    UINT32                                            PchgPDModeSel:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x84_dct0_STRUCT;
+
+// **** D18F2x88_dct1 Register Definition ****
+// Address
+#define D18F2x88_dct1_ADDRESS                                   0x88
+
+// Type
+#define D18F2x88_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x88_dct1_Reserved_23_0_OFFSET                      0
+#define D18F2x88_dct1_Reserved_23_0_WIDTH                       24
+#define D18F2x88_dct1_Reserved_23_0_MASK                        0xffffff
+#define D18F2x88_dct1_MemClkDis_OFFSET                          24
+#define D18F2x88_dct1_MemClkDis_WIDTH                           6
+#define D18F2x88_dct1_MemClkDis_MASK                            0x3f000000
+#define D18F2x88_dct1_Reserved_31_30_OFFSET                     30
+#define D18F2x88_dct1_Reserved_31_30_WIDTH                      2
+#define D18F2x88_dct1_Reserved_31_30_MASK                       0xc0000000
+
+/// D18F2x88_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                MemClkDis:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x88_dct1_STRUCT;
+
+// **** D18F2x88_dct0 Register Definition ****
+// Address
+#define D18F2x88_dct0_ADDRESS                                   0x88
+
+// Type
+#define D18F2x88_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x88_dct0_Reserved_23_0_OFFSET                      0
+#define D18F2x88_dct0_Reserved_23_0_WIDTH                       24
+#define D18F2x88_dct0_Reserved_23_0_MASK                        0xffffff
+#define D18F2x88_dct0_MemClkDis_OFFSET                          24
+#define D18F2x88_dct0_MemClkDis_WIDTH                           6
+#define D18F2x88_dct0_MemClkDis_MASK                            0x3f000000
+#define D18F2x88_dct0_Reserved_31_30_OFFSET                     30
+#define D18F2x88_dct0_Reserved_31_30_WIDTH                      2
+#define D18F2x88_dct0_Reserved_31_30_MASK                       0xc0000000
+
+/// D18F2x88_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                MemClkDis:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x88_dct0_STRUCT;
+
+// **** D18F2x8C_dct1 Register Definition ****
+// Address
+#define D18F2x8C_dct1_ADDRESS                                   0x8c
+
+// Type
+#define D18F2x8C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x8C_dct1_Reserved_15_0_OFFSET                      0
+#define D18F2x8C_dct1_Reserved_15_0_WIDTH                       16
+#define D18F2x8C_dct1_Reserved_15_0_MASK                        0xffff
+#define D18F2x8C_dct1_Tref_OFFSET                               16
+#define D18F2x8C_dct1_Tref_WIDTH                                2
+#define D18F2x8C_dct1_Tref_MASK                                 0x30000
+#define D18F2x8C_dct1_DisAutoRefresh_OFFSET                     18
+#define D18F2x8C_dct1_DisAutoRefresh_WIDTH                      1
+#define D18F2x8C_dct1_DisAutoRefresh_MASK                       0x40000
+#define D18F2x8C_dct1_Reserved_31_19_OFFSET                     19
+#define D18F2x8C_dct1_Reserved_31_19_WIDTH                      13
+#define D18F2x8C_dct1_Reserved_31_19_MASK                       0xfff80000
+
+/// D18F2x8C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                                     Tref:2 ; ///<
+    UINT32                                           DisAutoRefresh:1 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x8C_dct1_STRUCT;
+
+// **** D18F2x8C_dct0 Register Definition ****
+// Address
+#define D18F2x8C_dct0_ADDRESS                                   0x8c
+
+// Type
+#define D18F2x8C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x8C_dct0_Reserved_15_0_OFFSET                      0
+#define D18F2x8C_dct0_Reserved_15_0_WIDTH                       16
+#define D18F2x8C_dct0_Reserved_15_0_MASK                        0xffff
+#define D18F2x8C_dct0_Tref_OFFSET                               16
+#define D18F2x8C_dct0_Tref_WIDTH                                2
+#define D18F2x8C_dct0_Tref_MASK                                 0x30000
+#define D18F2x8C_dct0_DisAutoRefresh_OFFSET                     18
+#define D18F2x8C_dct0_DisAutoRefresh_WIDTH                      1
+#define D18F2x8C_dct0_DisAutoRefresh_MASK                       0x40000
+#define D18F2x8C_dct0_Reserved_31_19_OFFSET                     19
+#define D18F2x8C_dct0_Reserved_31_19_WIDTH                      13
+#define D18F2x8C_dct0_Reserved_31_19_MASK                       0xfff80000
+
+/// D18F2x8C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                                     Tref:2 ; ///<
+    UINT32                                           DisAutoRefresh:1 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x8C_dct0_STRUCT;
+
+// **** D18F2x90_dct0 Register Definition ****
+// Address
+#define D18F2x90_dct0_ADDRESS                                   0x90
+
+// Type
+#define D18F2x90_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x90_dct0_Reserved_0_0_OFFSET                       0
+#define D18F2x90_dct0_Reserved_0_0_WIDTH                        1
+#define D18F2x90_dct0_Reserved_0_0_MASK                         0x1
+#define D18F2x90_dct0_ExitSelfRef_OFFSET                        1
+#define D18F2x90_dct0_ExitSelfRef_WIDTH                         1
+#define D18F2x90_dct0_ExitSelfRef_MASK                          0x2
+#define D18F2x90_dct0_Reserved_7_2_OFFSET                       2
+#define D18F2x90_dct0_Reserved_7_2_WIDTH                        6
+#define D18F2x90_dct0_Reserved_7_2_MASK                         0xfc
+#define D18F2x90_dct0_Reserved_8_8_OFFSET                       8
+#define D18F2x90_dct0_Reserved_8_8_WIDTH                        1
+#define D18F2x90_dct0_Reserved_8_8_MASK                         0x100
+#define D18F2x90_dct0_Reserved_11_9_OFFSET                      9
+#define D18F2x90_dct0_Reserved_11_9_WIDTH                       3
+#define D18F2x90_dct0_Reserved_11_9_MASK                        0xe00
+#define D18F2x90_dct0_Reserved_15_12_OFFSET                     12
+#define D18F2x90_dct0_Reserved_15_12_WIDTH                      4
+#define D18F2x90_dct0_Reserved_15_12_MASK                       0xf000
+#define D18F2x90_dct0_UnbuffDimm_OFFSET                         16
+#define D18F2x90_dct0_UnbuffDimm_WIDTH                          1
+#define D18F2x90_dct0_UnbuffDimm_MASK                           0x10000
+#define D18F2x90_dct0_EnterSelfRef_OFFSET                       17
+#define D18F2x90_dct0_EnterSelfRef_WIDTH                        1
+#define D18F2x90_dct0_EnterSelfRef_MASK                         0x20000
+#define D18F2x90_dct0_PendRefPayback_OFFSET                     18
+#define D18F2x90_dct0_PendRefPayback_WIDTH                      1
+#define D18F2x90_dct0_PendRefPayback_MASK                       0x40000
+#define D18F2x90_dct0_Reserved_19_19_OFFSET                     19
+#define D18F2x90_dct0_Reserved_19_19_WIDTH                      1
+#define D18F2x90_dct0_Reserved_19_19_MASK                       0x80000
+#define D18F2x90_dct0_DynPageCloseEn_OFFSET                     20
+#define D18F2x90_dct0_DynPageCloseEn_WIDTH                      1
+#define D18F2x90_dct0_DynPageCloseEn_MASK                       0x100000
+#define D18F2x90_dct0_IdleCycLowLimit_OFFSET                    21
+#define D18F2x90_dct0_IdleCycLowLimit_WIDTH                     2
+#define D18F2x90_dct0_IdleCycLowLimit_MASK                      0x600000
+#define D18F2x90_dct0_ForceAutoPchg_OFFSET                      23
+#define D18F2x90_dct0_ForceAutoPchg_WIDTH                       1
+#define D18F2x90_dct0_ForceAutoPchg_MASK                        0x800000
+#define D18F2x90_dct0_StagRefEn_OFFSET                          24
+#define D18F2x90_dct0_StagRefEn_WIDTH                           1
+#define D18F2x90_dct0_StagRefEn_MASK                            0x1000000
+#define D18F2x90_dct0_PendRefPaybackS3En_OFFSET                 25
+#define D18F2x90_dct0_PendRefPaybackS3En_WIDTH                  1
+#define D18F2x90_dct0_PendRefPaybackS3En_MASK                   0x2000000
+#define D18F2x90_dct0_Reserved_26_26_OFFSET                     26
+#define D18F2x90_dct0_Reserved_26_26_WIDTH                      1
+#define D18F2x90_dct0_Reserved_26_26_MASK                       0x4000000
+#define D18F2x90_dct0_DisDllShutdownSR_OFFSET                   27
+#define D18F2x90_dct0_DisDllShutdownSR_WIDTH                    1
+#define D18F2x90_dct0_DisDllShutdownSR_MASK                     0x8000000
+#define D18F2x90_dct0_Reserved_31_28_OFFSET                     28
+#define D18F2x90_dct0_Reserved_31_28_WIDTH                      4
+#define D18F2x90_dct0_Reserved_31_28_MASK                       0xf0000000
+
+/// D18F2x90_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                              ExitSelfRef:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                            Reserved_11_9:3 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                               UnbuffDimm:1 ; ///<
+    UINT32                                             EnterSelfRef:1 ; ///<
+    UINT32                                           PendRefPayback:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                           DynPageCloseEn:1 ; ///<
+    UINT32                                          IdleCycLowLimit:2 ; ///<
+    UINT32                                            ForceAutoPchg:1 ; ///<
+    UINT32                                                StagRefEn:1 ; ///<
+    UINT32                                       PendRefPaybackS3En:1 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                         DisDllShutdownSR:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x90_dct0_STRUCT;
+
+// **** D18F2x90_dct1 Register Definition ****
+// Address
+#define D18F2x90_dct1_ADDRESS                                   0x90
+
+// Type
+#define D18F2x90_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x90_dct1_Reserved_0_0_OFFSET                       0
+#define D18F2x90_dct1_Reserved_0_0_WIDTH                        1
+#define D18F2x90_dct1_Reserved_0_0_MASK                         0x1
+#define D18F2x90_dct1_ExitSelfRef_OFFSET                        1
+#define D18F2x90_dct1_ExitSelfRef_WIDTH                         1
+#define D18F2x90_dct1_ExitSelfRef_MASK                          0x2
+#define D18F2x90_dct1_Reserved_7_2_OFFSET                       2
+#define D18F2x90_dct1_Reserved_7_2_WIDTH                        6
+#define D18F2x90_dct1_Reserved_7_2_MASK                         0xfc
+#define D18F2x90_dct1_Reserved_8_8_OFFSET                       8
+#define D18F2x90_dct1_Reserved_8_8_WIDTH                        1
+#define D18F2x90_dct1_Reserved_8_8_MASK                         0x100
+#define D18F2x90_dct1_Reserved_11_9_OFFSET                      9
+#define D18F2x90_dct1_Reserved_11_9_WIDTH                       3
+#define D18F2x90_dct1_Reserved_11_9_MASK                        0xe00
+#define D18F2x90_dct1_Reserved_15_12_OFFSET                     12
+#define D18F2x90_dct1_Reserved_15_12_WIDTH                      4
+#define D18F2x90_dct1_Reserved_15_12_MASK                       0xf000
+#define D18F2x90_dct1_UnbuffDimm_OFFSET                         16
+#define D18F2x90_dct1_UnbuffDimm_WIDTH                          1
+#define D18F2x90_dct1_UnbuffDimm_MASK                           0x10000
+#define D18F2x90_dct1_EnterSelfRef_OFFSET                       17
+#define D18F2x90_dct1_EnterSelfRef_WIDTH                        1
+#define D18F2x90_dct1_EnterSelfRef_MASK                         0x20000
+#define D18F2x90_dct1_PendRefPayback_OFFSET                     18
+#define D18F2x90_dct1_PendRefPayback_WIDTH                      1
+#define D18F2x90_dct1_PendRefPayback_MASK                       0x40000
+#define D18F2x90_dct1_Reserved_19_19_OFFSET                     19
+#define D18F2x90_dct1_Reserved_19_19_WIDTH                      1
+#define D18F2x90_dct1_Reserved_19_19_MASK                       0x80000
+#define D18F2x90_dct1_DynPageCloseEn_OFFSET                     20
+#define D18F2x90_dct1_DynPageCloseEn_WIDTH                      1
+#define D18F2x90_dct1_DynPageCloseEn_MASK                       0x100000
+#define D18F2x90_dct1_IdleCycLowLimit_OFFSET                    21
+#define D18F2x90_dct1_IdleCycLowLimit_WIDTH                     2
+#define D18F2x90_dct1_IdleCycLowLimit_MASK                      0x600000
+#define D18F2x90_dct1_ForceAutoPchg_OFFSET                      23
+#define D18F2x90_dct1_ForceAutoPchg_WIDTH                       1
+#define D18F2x90_dct1_ForceAutoPchg_MASK                        0x800000
+#define D18F2x90_dct1_StagRefEn_OFFSET                          24
+#define D18F2x90_dct1_StagRefEn_WIDTH                           1
+#define D18F2x90_dct1_StagRefEn_MASK                            0x1000000
+#define D18F2x90_dct1_PendRefPaybackS3En_OFFSET                 25
+#define D18F2x90_dct1_PendRefPaybackS3En_WIDTH                  1
+#define D18F2x90_dct1_PendRefPaybackS3En_MASK                   0x2000000
+#define D18F2x90_dct1_Reserved_26_26_OFFSET                     26
+#define D18F2x90_dct1_Reserved_26_26_WIDTH                      1
+#define D18F2x90_dct1_Reserved_26_26_MASK                       0x4000000
+#define D18F2x90_dct1_DisDllShutdownSR_OFFSET                   27
+#define D18F2x90_dct1_DisDllShutdownSR_WIDTH                    1
+#define D18F2x90_dct1_DisDllShutdownSR_MASK                     0x8000000
+#define D18F2x90_dct1_Reserved_31_28_OFFSET                     28
+#define D18F2x90_dct1_Reserved_31_28_WIDTH                      4
+#define D18F2x90_dct1_Reserved_31_28_MASK                       0xf0000000
+
+/// D18F2x90_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                              ExitSelfRef:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                            Reserved_11_9:3 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                               UnbuffDimm:1 ; ///<
+    UINT32                                             EnterSelfRef:1 ; ///<
+    UINT32                                           PendRefPayback:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                           DynPageCloseEn:1 ; ///<
+    UINT32                                          IdleCycLowLimit:2 ; ///<
+    UINT32                                            ForceAutoPchg:1 ; ///<
+    UINT32                                                StagRefEn:1 ; ///<
+    UINT32                                       PendRefPaybackS3En:1 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                         DisDllShutdownSR:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x90_dct1_STRUCT;
+
+// **** D18F2x94_dct1 Register Definition ****
+// Address
+#define D18F2x94_dct1_ADDRESS                                   0x94
+
+// Type
+#define D18F2x94_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x94_dct1_MemClkFreq_OFFSET                         0
+#define D18F2x94_dct1_MemClkFreq_WIDTH                          5
+#define D18F2x94_dct1_MemClkFreq_MASK                           0x1f
+#define D18F2x94_dct1_Reserved_6_5_OFFSET                       5
+#define D18F2x94_dct1_Reserved_6_5_WIDTH                        2
+#define D18F2x94_dct1_Reserved_6_5_MASK                         0x60
+#define D18F2x94_dct1_MemClkFreqVal_OFFSET                      7
+#define D18F2x94_dct1_MemClkFreqVal_WIDTH                       1
+#define D18F2x94_dct1_MemClkFreqVal_MASK                        0x80
+#define D18F2x94_dct1_Reserved_9_8_OFFSET                       8
+#define D18F2x94_dct1_Reserved_9_8_WIDTH                        2
+#define D18F2x94_dct1_Reserved_9_8_MASK                         0x300
+#define D18F2x94_dct1_ZqcsInterval_OFFSET                       10
+#define D18F2x94_dct1_ZqcsInterval_WIDTH                        2
+#define D18F2x94_dct1_ZqcsInterval_MASK                         0xc00
+#define D18F2x94_dct1_Reserved_12_12_OFFSET                     12
+#define D18F2x94_dct1_Reserved_12_12_WIDTH                      1
+#define D18F2x94_dct1_Reserved_12_12_MASK                       0x1000
+#define D18F2x94_dct1_Reserved_13_13_OFFSET                     13
+#define D18F2x94_dct1_Reserved_13_13_WIDTH                      1
+#define D18F2x94_dct1_Reserved_13_13_MASK                       0x2000
+#define D18F2x94_dct1_DisDramInterface_OFFSET                   14
+#define D18F2x94_dct1_DisDramInterface_WIDTH                    1
+#define D18F2x94_dct1_DisDramInterface_MASK                     0x4000
+#define D18F2x94_dct1_PowerDownEn_OFFSET                        15
+#define D18F2x94_dct1_PowerDownEn_WIDTH                         1
+#define D18F2x94_dct1_PowerDownEn_MASK                          0x8000
+#define D18F2x94_dct1_PowerDownMode_OFFSET                      16
+#define D18F2x94_dct1_PowerDownMode_WIDTH                       1
+#define D18F2x94_dct1_PowerDownMode_MASK                        0x10000
+#define D18F2x94_dct1_Reserved_18_17_OFFSET                     17
+#define D18F2x94_dct1_Reserved_18_17_WIDTH                      2
+#define D18F2x94_dct1_Reserved_18_17_MASK                       0x60000
+#define D18F2x94_dct1_SlowAccessMode_OFFSET                     20
+#define D18F2x94_dct1_SlowAccessMode_WIDTH                      1
+#define D18F2x94_dct1_SlowAccessMode_MASK                       0x100000
+#define D18F2x94_dct1_FreqChgInProg_OFFSET                      21
+#define D18F2x94_dct1_FreqChgInProg_WIDTH                       1
+#define D18F2x94_dct1_FreqChgInProg_MASK                        0x200000
+#define D18F2x94_dct1_BankSwizzleMode_OFFSET                    22
+#define D18F2x94_dct1_BankSwizzleMode_WIDTH                     1
+#define D18F2x94_dct1_BankSwizzleMode_MASK                      0x400000
+#define D18F2x94_dct1_ProcOdtDis_OFFSET                         23
+#define D18F2x94_dct1_ProcOdtDis_WIDTH                          1
+#define D18F2x94_dct1_ProcOdtDis_MASK                           0x800000
+#define D18F2x94_dct1_DcqBypassMax_OFFSET                       24
+#define D18F2x94_dct1_DcqBypassMax_WIDTH                        5
+#define D18F2x94_dct1_DcqBypassMax_MASK                         0x1f000000
+#define D18F2x94_dct1_Reserved_30_29_OFFSET                     29
+#define D18F2x94_dct1_Reserved_30_29_WIDTH                      2
+#define D18F2x94_dct1_Reserved_30_29_MASK                       0x60000000
+#define D18F2x94_dct1_DphyMemPsSelEn_OFFSET                     31
+#define D18F2x94_dct1_DphyMemPsSelEn_WIDTH                      1
+#define D18F2x94_dct1_DphyMemPsSelEn_MASK                       0x80000000
+
+/// D18F2x94_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               MemClkFreq:5 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                            MemClkFreqVal:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                             ZqcsInterval:2 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                         DisDramInterface:1 ; ///<
+    UINT32                                              PowerDownEn:1 ; ///<
+    UINT32                                            PowerDownMode:1 ; ///<
+    UINT32                                           Reserved_18_17:2 ; ///<
+    UINT32                                           DcqArbBypassEn:1 ; ///<
+    UINT32                                           SlowAccessMode:1 ; ///<
+    UINT32                                            FreqChgInProg:1 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                               ProcOdtDis:1 ; ///<
+    UINT32                                             DcqBypassMax:5 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                           DphyMemPsSelEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x94_dct1_STRUCT;
+
+// **** D18F2x94_dct0 Register Definition ****
+// Address
+#define D18F2x94_dct0_ADDRESS                                   0x94
+
+// Type
+#define D18F2x94_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x94_dct0_MemClkFreq_OFFSET                         0
+#define D18F2x94_dct0_MemClkFreq_WIDTH                          5
+#define D18F2x94_dct0_MemClkFreq_MASK                           0x1f
+#define D18F2x94_dct0_Reserved_6_5_OFFSET                       5
+#define D18F2x94_dct0_Reserved_6_5_WIDTH                        2
+#define D18F2x94_dct0_Reserved_6_5_MASK                         0x60
+#define D18F2x94_dct0_MemClkFreqVal_OFFSET                      7
+#define D18F2x94_dct0_MemClkFreqVal_WIDTH                       1
+#define D18F2x94_dct0_MemClkFreqVal_MASK                        0x80
+#define D18F2x94_dct0_Reserved_9_8_OFFSET                       8
+#define D18F2x94_dct0_Reserved_9_8_WIDTH                        2
+#define D18F2x94_dct0_Reserved_9_8_MASK                         0x300
+#define D18F2x94_dct0_ZqcsInterval_OFFSET                       10
+#define D18F2x94_dct0_ZqcsInterval_WIDTH                        2
+#define D18F2x94_dct0_ZqcsInterval_MASK                         0xc00
+#define D18F2x94_dct0_Reserved_12_12_OFFSET                     12
+#define D18F2x94_dct0_Reserved_12_12_WIDTH                      1
+#define D18F2x94_dct0_Reserved_12_12_MASK                       0x1000
+#define D18F2x94_dct0_Reserved_13_13_OFFSET                     13
+#define D18F2x94_dct0_Reserved_13_13_WIDTH                      1
+#define D18F2x94_dct0_Reserved_13_13_MASK                       0x2000
+#define D18F2x94_dct0_DisDramInterface_OFFSET                   14
+#define D18F2x94_dct0_DisDramInterface_WIDTH                    1
+#define D18F2x94_dct0_DisDramInterface_MASK                     0x4000
+#define D18F2x94_dct0_PowerDownEn_OFFSET                        15
+#define D18F2x94_dct0_PowerDownEn_WIDTH                         1
+#define D18F2x94_dct0_PowerDownEn_MASK                          0x8000
+#define D18F2x94_dct0_PowerDownMode_OFFSET                      16
+#define D18F2x94_dct0_PowerDownMode_WIDTH                       1
+#define D18F2x94_dct0_PowerDownMode_MASK                        0x10000
+#define D18F2x94_dct0_Reserved_18_17_OFFSET                     17
+#define D18F2x94_dct0_Reserved_18_17_WIDTH                      2
+#define D18F2x94_dct0_Reserved_18_17_MASK                       0x60000
+#define D18F2x94_dct0_SlowAccessMode_OFFSET                     20
+#define D18F2x94_dct0_SlowAccessMode_WIDTH                      1
+#define D18F2x94_dct0_SlowAccessMode_MASK                       0x100000
+#define D18F2x94_dct0_FreqChgInProg_OFFSET                      21
+#define D18F2x94_dct0_FreqChgInProg_WIDTH                       1
+#define D18F2x94_dct0_FreqChgInProg_MASK                        0x200000
+#define D18F2x94_dct0_BankSwizzleMode_OFFSET                    22
+#define D18F2x94_dct0_BankSwizzleMode_WIDTH                     1
+#define D18F2x94_dct0_BankSwizzleMode_MASK                      0x400000
+#define D18F2x94_dct0_ProcOdtDis_OFFSET                         23
+#define D18F2x94_dct0_ProcOdtDis_WIDTH                          1
+#define D18F2x94_dct0_ProcOdtDis_MASK                           0x800000
+#define D18F2x94_dct0_DcqBypassMax_OFFSET                       24
+#define D18F2x94_dct0_DcqBypassMax_WIDTH                        5
+#define D18F2x94_dct0_DcqBypassMax_MASK                         0x1f000000
+#define D18F2x94_dct0_Reserved_30_29_OFFSET                     29
+#define D18F2x94_dct0_Reserved_30_29_WIDTH                      2
+#define D18F2x94_dct0_Reserved_30_29_MASK                       0x60000000
+#define D18F2x94_dct0_DphyMemPsSelEn_OFFSET                     31
+#define D18F2x94_dct0_DphyMemPsSelEn_WIDTH                      1
+#define D18F2x94_dct0_DphyMemPsSelEn_MASK                       0x80000000
+
+/// D18F2x94_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               MemClkFreq:5 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                            MemClkFreqVal:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                             ZqcsInterval:2 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                         DisDramInterface:1 ; ///<
+    UINT32                                              PowerDownEn:1 ; ///<
+    UINT32                                            PowerDownMode:1 ; ///<
+    UINT32                                           Reserved_18_17:2 ; ///<
+    UINT32                                           DcqArbBypassEn:1 ; ///<
+    UINT32                                           SlowAccessMode:1 ; ///<
+    UINT32                                            FreqChgInProg:1 ; ///<
+    UINT32                                          BankSwizzleMode:1 ; ///<
+    UINT32                                               ProcOdtDis:1 ; ///<
+    UINT32                                             DcqBypassMax:5 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                           DphyMemPsSelEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x94_dct0_STRUCT;
+
+// **** D18F2x98_dct0 Register Definition ****
+// Address
+#define D18F2x98_dct0_ADDRESS                                   0x98
+
+// Type
+#define D18F2x98_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x98_dct0_DctOffset_OFFSET                          0
+#define D18F2x98_dct0_DctOffset_WIDTH                           30
+#define D18F2x98_dct0_DctOffset_MASK                            0x3fffffff
+#define D18F2x98_dct0_DctAccessWrite_OFFSET                     30
+#define D18F2x98_dct0_DctAccessWrite_WIDTH                      1
+#define D18F2x98_dct0_DctAccessWrite_MASK                       0x40000000
+#define D18F2x98_dct0_Reserved_31_31_OFFSET                     31
+#define D18F2x98_dct0_Reserved_31_31_WIDTH                      1
+#define D18F2x98_dct0_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x98_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctOffset:30; ///<
+    UINT32                                           DctAccessWrite:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x98_dct0_STRUCT;
+
+// **** D18F2x98_dct1 Register Definition ****
+// Address
+#define D18F2x98_dct1_ADDRESS                                   0x98
+
+// Type
+#define D18F2x98_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x98_dct1_DctOffset_OFFSET                          0
+#define D18F2x98_dct1_DctOffset_WIDTH                           30
+#define D18F2x98_dct1_DctOffset_MASK                            0x3fffffff
+#define D18F2x98_dct1_DctAccessWrite_OFFSET                     30
+#define D18F2x98_dct1_DctAccessWrite_WIDTH                      1
+#define D18F2x98_dct1_DctAccessWrite_MASK                       0x40000000
+#define D18F2x98_dct1_Reserved_31_31_OFFSET                     31
+#define D18F2x98_dct1_Reserved_31_31_WIDTH                      1
+#define D18F2x98_dct1_Reserved_31_31_MASK                       0x80000000
+
+/// D18F2x98_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                DctOffset:30; ///<
+    UINT32                                           DctAccessWrite:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x98_dct1_STRUCT;
+
+// **** D18F2x9C_dct1 Register Definition ****
+// Address
+#define D18F2x9C_dct1_ADDRESS                                   0x9c
+
+// Type
+#define D18F2x9C_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2x9C_dct1_Data_OFFSET                               0
+#define D18F2x9C_dct1_Data_WIDTH                                32
+#define D18F2x9C_dct1_Data_MASK                                 0xffffffff
+
+/// D18F2x9C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_dct1_STRUCT;
+
+// **** D18F2x9C_dct0 Register Definition ****
+// Address
+#define D18F2x9C_dct0_ADDRESS                                   0x9c
+
+// Type
+#define D18F2x9C_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2x9C_dct0_Data_OFFSET                               0
+#define D18F2x9C_dct0_Data_WIDTH                                32
+#define D18F2x9C_dct0_Data_MASK                                 0xffffffff
+
+/// D18F2x9C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_dct0_STRUCT;
+
+// **** D18F2xA4 Register Definition ****
+// Address
+#define D18F2xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F2xA4_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xA4_Reserved_7_0_OFFSET                            0
+#define D18F2xA4_Reserved_7_0_WIDTH                             8
+#define D18F2xA4_Reserved_7_0_MASK                              0xff
+#define D18F2xA4_ODTSEn_OFFSET                                  8
+#define D18F2xA4_ODTSEn_WIDTH                                   1
+#define D18F2xA4_ODTSEn_MASK                                    0x100
+#define D18F2xA4_Reserved_10_9_OFFSET                           9
+#define D18F2xA4_Reserved_10_9_WIDTH                            2
+#define D18F2xA4_Reserved_10_9_MASK                             0x600
+#define D18F2xA4_BwCapEn_OFFSET                                 11
+#define D18F2xA4_BwCapEn_WIDTH                                  1
+#define D18F2xA4_BwCapEn_MASK                                   0x800
+#define D18F2xA4_CmdThrottleMode_OFFSET                         12
+#define D18F2xA4_CmdThrottleMode_WIDTH                          3
+#define D18F2xA4_CmdThrottleMode_MASK                           0x7000
+#define D18F2xA4_Reserved_19_15_OFFSET                          15
+#define D18F2xA4_Reserved_19_15_WIDTH                           5
+#define D18F2xA4_Reserved_19_15_MASK                            0xf8000
+#define D18F2xA4_BwCapCmdThrottleMode_OFFSET                    20
+#define D18F2xA4_BwCapCmdThrottleMode_WIDTH                     4
+#define D18F2xA4_BwCapCmdThrottleMode_MASK                      0xf00000
+#define D18F2xA4_Reserved_31_24_OFFSET                          24
+#define D18F2xA4_Reserved_31_24_WIDTH                           8
+#define D18F2xA4_Reserved_31_24_MASK                            0xff000000
+
+/// D18F2xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   ODTSEn:1 ; ///<
+    UINT32                                            Reserved_10_9:2 ; ///<
+    UINT32                                                  BwCapEn:1 ; ///<
+    UINT32                                          CmdThrottleMode:3 ; ///<
+    UINT32                                           Reserved_19_15:5 ; ///<
+    UINT32                                     BwCapCmdThrottleMode:4 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xA4_STRUCT;
+
+// **** D18F2xA8_dct0 Register Definition ****
+// Address
+#define D18F2xA8_dct0_ADDRESS                                   0xa8
+
+// Type
+#define D18F2xA8_dct0_TYPE                                      TYPE_D18F2_dct0
+// Field Data
+#define D18F2xA8_dct0_Reserved_1_0_OFFSET                       0
+#define D18F2xA8_dct0_Reserved_1_0_WIDTH                        2
+#define D18F2xA8_dct0_Reserved_1_0_MASK                         0x3
+#define D18F2xA8_dct0_CSTimingMux67_OFFSET                      2
+#define D18F2xA8_dct0_CSTimingMux67_WIDTH                       1
+#define D18F2xA8_dct0_CSTimingMux67_MASK                        0x4
+#define D18F2xA8_dct0_Reserved_3_3_OFFSET                       3
+#define D18F2xA8_dct0_Reserved_3_3_WIDTH                        1
+#define D18F2xA8_dct0_Reserved_3_3_MASK                         0x8
+#define D18F2xA8_dct0_Reserved_4_4_OFFSET                       4
+#define D18F2xA8_dct0_Reserved_4_4_WIDTH                        1
+#define D18F2xA8_dct0_Reserved_4_4_MASK                         0x10
+#define D18F2xA8_dct0_SubMemclkRegDly_OFFSET                    5
+#define D18F2xA8_dct0_SubMemclkRegDly_WIDTH                     1
+#define D18F2xA8_dct0_SubMemclkRegDly_MASK                      0x20
+#define D18F2xA8_dct0_Reserved_7_6_OFFSET                       6
+#define D18F2xA8_dct0_Reserved_7_6_WIDTH                        2
+#define D18F2xA8_dct0_Reserved_7_6_MASK                         0xc0
+#define D18F2xA8_dct0_CtrlWordCS_7_0__OFFSET                    8
+#define D18F2xA8_dct0_CtrlWordCS_7_0__WIDTH                     8
+#define D18F2xA8_dct0_CtrlWordCS_7_0__MASK                      0xff00
+#define D18F2xA8_dct0_MemPhyPllPdMode_OFFSET                    16
+#define D18F2xA8_dct0_MemPhyPllPdMode_WIDTH                     2
+#define D18F2xA8_dct0_MemPhyPllPdMode_MASK                      0x30000
+#define D18F2xA8_dct0_Reserved_19_18_OFFSET                     18
+#define D18F2xA8_dct0_Reserved_19_18_WIDTH                      2
+#define D18F2xA8_dct0_Reserved_19_18_MASK                       0xc0000
+#define D18F2xA8_dct0_BankSwap_OFFSET                           20
+#define D18F2xA8_dct0_BankSwap_WIDTH                            1
+#define D18F2xA8_dct0_BankSwap_MASK                             0x100000
+#define D18F2xA8_dct0_AggrPDEn_OFFSET                           21
+#define D18F2xA8_dct0_AggrPDEn_WIDTH                            1
+#define D18F2xA8_dct0_AggrPDEn_MASK                             0x200000
+#define D18F2xA8_dct0_PrtlChPDEnhEn_OFFSET                      22
+#define D18F2xA8_dct0_PrtlChPDEnhEn_WIDTH                       1
+#define D18F2xA8_dct0_PrtlChPDEnhEn_MASK                        0x400000
+#define D18F2xA8_dct0_Reserved_23_23_OFFSET                     23
+#define D18F2xA8_dct0_Reserved_23_23_WIDTH                      1
+#define D18F2xA8_dct0_Reserved_23_23_MASK                       0x800000
+#define D18F2xA8_dct0_Reserved_25_24_OFFSET                     24
+#define D18F2xA8_dct0_Reserved_25_24_WIDTH                      2
+#define D18F2xA8_dct0_Reserved_25_24_MASK                       0x3000000
+#define D18F2xA8_dct0_CsMux45_OFFSET                            26
+#define D18F2xA8_dct0_CsMux45_WIDTH                             1
+#define D18F2xA8_dct0_CsMux45_MASK                              0x4000000
+#define D18F2xA8_dct0_CsMux67_OFFSET                            27
+#define D18F2xA8_dct0_CsMux67_WIDTH                             1
+#define D18F2xA8_dct0_CsMux67_MASK                              0x8000000
+#define D18F2xA8_dct0_FastSelfRefEntryDis_OFFSET                28
+#define D18F2xA8_dct0_FastSelfRefEntryDis_WIDTH                 1
+#define D18F2xA8_dct0_FastSelfRefEntryDis_MASK                  0x10000000
+#define D18F2xA8_dct0_RefChCmdMgtDis_OFFSET                     29
+#define D18F2xA8_dct0_RefChCmdMgtDis_WIDTH                      1
+#define D18F2xA8_dct0_RefChCmdMgtDis_MASK                       0x20000000
+#define D18F2xA8_dct0_Reserved_30_30_OFFSET                     30
+#define D18F2xA8_dct0_Reserved_30_30_WIDTH                      1
+#define D18F2xA8_dct0_Reserved_30_30_MASK                       0x40000000
+#define D18F2xA8_dct0_PerRankTimingEn_OFFSET                    31
+#define D18F2xA8_dct0_PerRankTimingEn_WIDTH                     1
+#define D18F2xA8_dct0_PerRankTimingEn_MASK                      0x80000000
+
+/// D18F2xA8_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CSTimingMux67:1 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          SubMemclkRegDly:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                          CtrlWordCS_7_0_:8 ; ///<
+    UINT32                                          MemPhyPllPdMode:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                                 AggrPDEn:1 ; ///<
+    UINT32                                            PrtlChPDEnhEn:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                  CsMux45:1 ; ///<
+    UINT32                                                  CsMux67:1 ; ///<
+    UINT32                                      FastSelfRefEntryDis:1 ; ///<
+    UINT32                                           RefChCmdMgtDis:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                          PerRankTimingEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xA8_dct0_STRUCT;
+
+// **** D18F2xA8_dct1 Register Definition ****
+// Address
+#define D18F2xA8_dct1_ADDRESS                                   0xa8
+
+// Type
+#define D18F2xA8_dct1_TYPE                                      TYPE_D18F2_dct1
+// Field Data
+#define D18F2xA8_dct1_Reserved_1_0_OFFSET                       0
+#define D18F2xA8_dct1_Reserved_1_0_WIDTH                        2
+#define D18F2xA8_dct1_Reserved_1_0_MASK                         0x3
+#define D18F2xA8_dct1_CSTimingMux67_OFFSET                      2
+#define D18F2xA8_dct1_CSTimingMux67_WIDTH                       1
+#define D18F2xA8_dct1_CSTimingMux67_MASK                        0x4
+#define D18F2xA8_dct1_Reserved_3_3_OFFSET                       3
+#define D18F2xA8_dct1_Reserved_3_3_WIDTH                        1
+#define D18F2xA8_dct1_Reserved_3_3_MASK                         0x8
+#define D18F2xA8_dct1_Reserved_4_4_OFFSET                       4
+#define D18F2xA8_dct1_Reserved_4_4_WIDTH                        1
+#define D18F2xA8_dct1_Reserved_4_4_MASK                         0x10
+#define D18F2xA8_dct1_SubMemclkRegDly_OFFSET                    5
+#define D18F2xA8_dct1_SubMemclkRegDly_WIDTH                     1
+#define D18F2xA8_dct1_SubMemclkRegDly_MASK                      0x20
+#define D18F2xA8_dct1_Reserved_7_6_OFFSET                       6
+#define D18F2xA8_dct1_Reserved_7_6_WIDTH                        2
+#define D18F2xA8_dct1_Reserved_7_6_MASK                         0xc0
+#define D18F2xA8_dct1_CtrlWordCS_7_0__OFFSET                    8
+#define D18F2xA8_dct1_CtrlWordCS_7_0__WIDTH                     8
+#define D18F2xA8_dct1_CtrlWordCS_7_0__MASK                      0xff00
+#define D18F2xA8_dct1_MemPhyPllPdMode_OFFSET                    16
+#define D18F2xA8_dct1_MemPhyPllPdMode_WIDTH                     2
+#define D18F2xA8_dct1_MemPhyPllPdMode_MASK                      0x30000
+#define D18F2xA8_dct1_Reserved_19_18_OFFSET                     18
+#define D18F2xA8_dct1_Reserved_19_18_WIDTH                      2
+#define D18F2xA8_dct1_Reserved_19_18_MASK                       0xc0000
+#define D18F2xA8_dct1_BankSwap_OFFSET                           20
+#define D18F2xA8_dct1_BankSwap_WIDTH                            1
+#define D18F2xA8_dct1_BankSwap_MASK                             0x100000
+#define D18F2xA8_dct1_AggrPDEn_OFFSET                           21
+#define D18F2xA8_dct1_AggrPDEn_WIDTH                            1
+#define D18F2xA8_dct1_AggrPDEn_MASK                             0x200000
+#define D18F2xA8_dct1_PrtlChPDEnhEn_OFFSET                      22
+#define D18F2xA8_dct1_PrtlChPDEnhEn_WIDTH                       1
+#define D18F2xA8_dct1_PrtlChPDEnhEn_MASK                        0x400000
+#define D18F2xA8_dct1_Reserved_23_23_OFFSET                     23
+#define D18F2xA8_dct1_Reserved_23_23_WIDTH                      1
+#define D18F2xA8_dct1_Reserved_23_23_MASK                       0x800000
+#define D18F2xA8_dct1_Reserved_25_24_OFFSET                     24
+#define D18F2xA8_dct1_Reserved_25_24_WIDTH                      2
+#define D18F2xA8_dct1_Reserved_25_24_MASK                       0x3000000
+#define D18F2xA8_dct1_CsMux45_OFFSET                            26
+#define D18F2xA8_dct1_CsMux45_WIDTH                             1
+#define D18F2xA8_dct1_CsMux45_MASK                              0x4000000
+#define D18F2xA8_dct1_CsMux67_OFFSET                            27
+#define D18F2xA8_dct1_CsMux67_WIDTH                             1
+#define D18F2xA8_dct1_CsMux67_MASK                              0x8000000
+#define D18F2xA8_dct1_FastSelfRefEntryDis_OFFSET                28
+#define D18F2xA8_dct1_FastSelfRefEntryDis_WIDTH                 1
+#define D18F2xA8_dct1_FastSelfRefEntryDis_MASK                  0x10000000
+#define D18F2xA8_dct1_RefChCmdMgtDis_OFFSET                     29
+#define D18F2xA8_dct1_RefChCmdMgtDis_WIDTH                      1
+#define D18F2xA8_dct1_RefChCmdMgtDis_MASK                       0x20000000
+#define D18F2xA8_dct1_Reserved_30_30_OFFSET                     30
+#define D18F2xA8_dct1_Reserved_30_30_WIDTH                      1
+#define D18F2xA8_dct1_Reserved_30_30_MASK                       0x40000000
+#define D18F2xA8_dct1_PerRankTimingEn_OFFSET                    31
+#define D18F2xA8_dct1_PerRankTimingEn_WIDTH                     1
+#define D18F2xA8_dct1_PerRankTimingEn_MASK                      0x80000000
+
+/// D18F2xA8_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CSTimingMux67:1 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                          SubMemclkRegDly:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                          CtrlWordCS_7_0_:8 ; ///<
+    UINT32                                          MemPhyPllPdMode:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                 BankSwap:1 ; ///<
+    UINT32                                                 AggrPDEn:1 ; ///<
+    UINT32                                            PrtlChPDEnhEn:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                  CsMux45:1 ; ///<
+    UINT32                                                  CsMux67:1 ; ///<
+    UINT32                                      FastSelfRefEntryDis:1 ; ///<
+    UINT32                                           RefChCmdMgtDis:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                          PerRankTimingEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xA8_dct1_STRUCT;
+
+// **** D18F2xAC Register Definition ****
+// Address
+#define D18F2xAC_ADDRESS                                        0xac
+
+// Type
+#define D18F2xAC_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xAC_MemTempHot0_OFFSET                             0
+#define D18F2xAC_MemTempHot0_WIDTH                              1
+#define D18F2xAC_MemTempHot0_MASK                               0x1
+#define D18F2xAC_Reserved_1_1_OFFSET                            1
+#define D18F2xAC_Reserved_1_1_WIDTH                             1
+#define D18F2xAC_Reserved_1_1_MASK                              0x2
+#define D18F2xAC_MemTempHot1_OFFSET                             2
+#define D18F2xAC_MemTempHot1_WIDTH                              1
+#define D18F2xAC_MemTempHot1_MASK                               0x4
+#define D18F2xAC_Reserved_31_3_OFFSET                           3
+#define D18F2xAC_Reserved_31_3_WIDTH                            29
+#define D18F2xAC_Reserved_31_3_MASK                             0xfffffff8
+
+/// D18F2xAC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MemTempHot0:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              MemTempHot1:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xAC_STRUCT;
+
+
+
+// **** D18F2xC4 Register Definition ****
+// Address
+
+
+
+
+
+
+
+
+
+
+
+// **** D18F2xF8 Register Definition ****
+// Address
+#define D18F2xF8_ADDRESS                                        0xf8
+
+// Type
+#define D18F2xF8_TYPE                                           TYPE_D18F2
+// Field Data
+#define D18F2xF8_PwrValue0_OFFSET                               0
+#define D18F2xF8_PwrValue0_WIDTH                                8
+#define D18F2xF8_PwrValue0_MASK                                 0xff
+#define D18F2xF8_PwrValue1_OFFSET                               8
+#define D18F2xF8_PwrValue1_WIDTH                                8
+#define D18F2xF8_PwrValue1_MASK                                 0xff00
+#define D18F2xF8_PwrValue2_OFFSET                               16
+#define D18F2xF8_PwrValue2_WIDTH                                8
+#define D18F2xF8_PwrValue2_MASK                                 0xff0000
+#define D18F2xF8_PwrValue3_OFFSET                               24
+#define D18F2xF8_PwrValue3_WIDTH                                8
+#define D18F2xF8_PwrValue3_MASK                                 0xff000000
+
+/// D18F2xF8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PwrValue0:8 ; ///<
+    UINT32                                                PwrValue1:8 ; ///<
+    UINT32                                                PwrValue2:8 ; ///<
+    UINT32                                                PwrValue3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2xF8_STRUCT;
+
+
+// **** D18F2x104 Register Definition ****
+// Address
+#define D18F2x104_ADDRESS                                       0x104
+
+// Type
+#define D18F2x104_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x104_PwrValue5_OFFSET                              0
+#define D18F2x104_PwrValue5_WIDTH                               8
+#define D18F2x104_PwrValue5_MASK                                0xff
+#define D18F2x104_PwrValue6_OFFSET                              8
+#define D18F2x104_PwrValue6_WIDTH                               8
+#define D18F2x104_PwrValue6_MASK                                0xff00
+#define D18F2x104_PwrValue7_OFFSET                              16
+#define D18F2x104_PwrValue7_WIDTH                               8
+#define D18F2x104_PwrValue7_MASK                                0xff0000
+#define D18F2x104_Reserved_31_24_OFFSET                         24
+#define D18F2x104_Reserved_31_24_WIDTH                          8
+#define D18F2x104_Reserved_31_24_MASK                           0xff000000
+
+/// D18F2x104
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PwrValue5:8 ; ///<
+    UINT32                                                PwrValue6:8 ; ///<
+    UINT32                                                PwrValue7:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x104_STRUCT;
+
+// **** D18F2x10C Register Definition ****
+// Address
+#define D18F2x10C_ADDRESS                                       0x10c
+
+// Type
+#define D18F2x10C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x10C_IntLvRgnSwapEn_OFFSET                         0
+#define D18F2x10C_IntLvRgnSwapEn_WIDTH                          1
+#define D18F2x10C_IntLvRgnSwapEn_MASK                           0x1
+#define D18F2x10C_Reserved_2_1_OFFSET                           1
+#define D18F2x10C_Reserved_2_1_WIDTH                            2
+#define D18F2x10C_Reserved_2_1_MASK                             0x6
+#define D18F2x10C_IntLvRgnBaseAddr_33_27__OFFSET                3
+#define D18F2x10C_IntLvRgnBaseAddr_33_27__WIDTH                 7
+#define D18F2x10C_IntLvRgnBaseAddr_33_27__MASK                  0x3f8
+#define D18F2x10C_Reserved_10_10_OFFSET                         10
+#define D18F2x10C_Reserved_10_10_WIDTH                          1
+#define D18F2x10C_Reserved_10_10_MASK                           0x400
+#define D18F2x10C_IntLvRgnLmtAddr_33_27__OFFSET                 11
+#define D18F2x10C_IntLvRgnLmtAddr_33_27__WIDTH                  7
+#define D18F2x10C_IntLvRgnLmtAddr_33_27__MASK                   0x3f800
+#define D18F2x10C_Reserved_19_18_OFFSET                         18
+#define D18F2x10C_Reserved_19_18_WIDTH                          2
+#define D18F2x10C_Reserved_19_18_MASK                           0xc0000
+#define D18F2x10C_IntLvRgnSize_33_27__OFFSET                    20
+#define D18F2x10C_IntLvRgnSize_33_27__WIDTH                     7
+#define D18F2x10C_IntLvRgnSize_33_27__MASK                      0x7f00000
+#define D18F2x10C_Reserved_31_27_OFFSET                         27
+#define D18F2x10C_Reserved_31_27_WIDTH                          5
+#define D18F2x10C_Reserved_31_27_MASK                           0xf8000000
+
+/// D18F2x10C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           IntLvRgnSwapEn:1 ; ///<
+    UINT32                                             Reserved_2_1:2 ; ///<
+    UINT32                                  IntLvRgnBaseAddr_33_27_:7 ; ///<
+    UINT32                                           Reserved_10_10:1 ; ///<
+    UINT32                                   IntLvRgnLmtAddr_33_27_:7 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                      IntLvRgnSize_33_27_:7 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x10C_STRUCT;
+
+// **** D18F2x110 Register Definition ****
+// Address
+#define D18F2x110_ADDRESS                                       0x110
+
+// Type
+#define D18F2x110_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x110_DctSelHiRngEn_OFFSET                          0
+#define D18F2x110_DctSelHiRngEn_WIDTH                           1
+#define D18F2x110_DctSelHiRngEn_MASK                            0x1
+#define D18F2x110_DctSelHi_OFFSET                               1
+#define D18F2x110_DctSelHi_WIDTH                                1
+#define D18F2x110_DctSelHi_MASK                                 0x2
+#define D18F2x110_DctSelIntLvEn_OFFSET                          2
+#define D18F2x110_DctSelIntLvEn_WIDTH                           1
+#define D18F2x110_DctSelIntLvEn_MASK                            0x4
+#define D18F2x110_MemClrInit_OFFSET                             3
+#define D18F2x110_MemClrInit_WIDTH                              1
+#define D18F2x110_MemClrInit_MASK                               0x8
+#define D18F2x110_Reserved_4_4_OFFSET                           4
+#define D18F2x110_Reserved_4_4_WIDTH                            1
+#define D18F2x110_Reserved_4_4_MASK                             0x10
+#define D18F2x110_DctDatIntLv_OFFSET                            5
+#define D18F2x110_DctDatIntLv_WIDTH                             1
+#define D18F2x110_DctDatIntLv_MASK                              0x20
+#define D18F2x110_DctSelIntLvAddr_1_0__OFFSET                   6
+#define D18F2x110_DctSelIntLvAddr_1_0__WIDTH                    2
+#define D18F2x110_DctSelIntLvAddr_1_0__MASK                     0xc0
+#define D18F2x110_DramEnable_OFFSET                             8
+#define D18F2x110_DramEnable_WIDTH                              1
+#define D18F2x110_DramEnable_MASK                               0x100
+#define D18F2x110_MemClrBusy_OFFSET                             9
+#define D18F2x110_MemClrBusy_WIDTH                              1
+#define D18F2x110_MemClrBusy_MASK                               0x200
+#define D18F2x110_MemCleared_OFFSET                             10
+#define D18F2x110_MemCleared_WIDTH                              1
+#define D18F2x110_MemCleared_MASK                               0x400
+#define D18F2x110_DctSelBaseAddr_47_27__OFFSET                  11
+#define D18F2x110_DctSelBaseAddr_47_27__WIDTH                   21
+#define D18F2x110_DctSelBaseAddr_47_27__MASK                    0xfffff800
+
+/// D18F2x110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DctSelHiRngEn:1 ; ///<
+    UINT32                                                 DctSelHi:1 ; ///<
+    UINT32                                            DctSelIntLvEn:1 ; ///<
+    UINT32                                               MemClrInit:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                              DctDatIntLv:1 ; ///<
+    UINT32                                     DctSelIntLvAddr_1_0_:2 ; ///<
+    UINT32                                               DramEnable:1 ; ///<
+    UINT32                                               MemClrBusy:1 ; ///<
+    UINT32                                               MemCleared:1 ; ///<
+    UINT32                                    DctSelBaseAddr_47_27_:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x110_STRUCT;
+
+// **** D18F2x114 Register Definition ****
+// Address
+#define D18F2x114_ADDRESS                                       0x114
+
+// Type
+#define D18F2x114_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x114_Reserved_8_0_OFFSET                           0
+#define D18F2x114_Reserved_8_0_WIDTH                            9
+#define D18F2x114_Reserved_8_0_MASK                             0x1ff
+#define D18F2x114_DctSelIntLvAddr_2__OFFSET                     9
+#define D18F2x114_DctSelIntLvAddr_2__WIDTH                      1
+#define D18F2x114_DctSelIntLvAddr_2__MASK                       0x200
+#define D18F2x114_DctSelBaseOffset_47_26__OFFSET                10
+#define D18F2x114_DctSelBaseOffset_47_26__WIDTH                 22
+#define D18F2x114_DctSelBaseOffset_47_26__MASK                  0xfffffc00
+
+/// D18F2x114
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                       DctSelIntLvAddr_2_:1 ; ///<
+    UINT32                                  DctSelBaseOffset_47_26_:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x114_STRUCT;
+
+// **** D18F2x118 Register Definition ****
+// Address
+#define D18F2x118_ADDRESS                                       0x118
+
+// Type
+#define D18F2x118_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x118_MctPriCpuRd_OFFSET                            0
+#define D18F2x118_MctPriCpuRd_WIDTH                             2
+#define D18F2x118_MctPriCpuRd_MASK                              0x3
+#define D18F2x118_MctPriCpuWr_OFFSET                            2
+#define D18F2x118_MctPriCpuWr_WIDTH                             2
+#define D18F2x118_MctPriCpuWr_MASK                              0xc
+#define D18F2x118_MctPriIsocRd_OFFSET                           4
+#define D18F2x118_MctPriIsocRd_WIDTH                            2
+#define D18F2x118_MctPriIsocRd_MASK                             0x30
+#define D18F2x118_MctPriIsocWr_OFFSET                           6
+#define D18F2x118_MctPriIsocWr_WIDTH                            2
+#define D18F2x118_MctPriIsocWr_MASK                             0xc0
+#define D18F2x118_MctPriDefault_OFFSET                          8
+#define D18F2x118_MctPriDefault_WIDTH                           2
+#define D18F2x118_MctPriDefault_MASK                            0x300
+#define D18F2x118_MctPriWr_OFFSET                               10
+#define D18F2x118_MctPriWr_WIDTH                                2
+#define D18F2x118_MctPriWr_MASK                                 0xc00
+#define D18F2x118_MctPriIsoc_OFFSET                             12
+#define D18F2x118_MctPriIsoc_WIDTH                              2
+#define D18F2x118_MctPriIsoc_MASK                               0x3000
+#define D18F2x118_MctPriTrace_OFFSET                            14
+#define D18F2x118_MctPriTrace_WIDTH                             2
+#define D18F2x118_MctPriTrace_MASK                              0xc000
+#define D18F2x118_MctPriScrub_OFFSET                            16
+#define D18F2x118_MctPriScrub_WIDTH                             2
+#define D18F2x118_MctPriScrub_MASK                              0x30000
+#define D18F2x118_CC6SaveEn_OFFSET                              18
+#define D18F2x118_CC6SaveEn_WIDTH                               1
+#define D18F2x118_CC6SaveEn_MASK                                0x40000
+#define D18F2x118_LockDramCfg_OFFSET                            19
+#define D18F2x118_LockDramCfg_WIDTH                             1
+#define D18F2x118_LockDramCfg_MASK                              0x80000
+#define D18F2x118_McqMedPriByPassMax_OFFSET                     20
+#define D18F2x118_McqMedPriByPassMax_WIDTH                      3
+#define D18F2x118_McqMedPriByPassMax_MASK                       0x700000
+#define D18F2x118_Reserved_23_23_OFFSET                         23
+#define D18F2x118_Reserved_23_23_WIDTH                          1
+#define D18F2x118_Reserved_23_23_MASK                           0x800000
+#define D18F2x118_McqHiPriByPassMax_OFFSET                      24
+#define D18F2x118_McqHiPriByPassMax_WIDTH                       3
+#define D18F2x118_McqHiPriByPassMax_MASK                        0x7000000
+#define D18F2x118_MctEccDisLatOptEn_OFFSET                      27
+#define D18F2x118_MctEccDisLatOptEn_WIDTH                       1
+#define D18F2x118_MctEccDisLatOptEn_MASK                        0x8000000
+#define D18F2x118_MctVarPriCntLmt_OFFSET                        28
+#define D18F2x118_MctVarPriCntLmt_WIDTH                         4
+#define D18F2x118_MctVarPriCntLmt_MASK                          0xf0000000
+
+/// D18F2x118
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              MctPriCpuRd:2 ; ///<
+    UINT32                                              MctPriCpuWr:2 ; ///<
+    UINT32                                             MctPriIsocRd:2 ; ///<
+    UINT32                                             MctPriIsocWr:2 ; ///<
+    UINT32                                            MctPriDefault:2 ; ///<
+    UINT32                                                 MctPriWr:2 ; ///<
+    UINT32                                               MctPriIsoc:2 ; ///<
+    UINT32                                              MctPriTrace:2 ; ///<
+    UINT32                                              MctPriScrub:2 ; ///<
+    UINT32                                                CC6SaveEn:1 ; ///<
+    UINT32                                              LockDramCfg:1 ; ///<
+    UINT32                                       McqMedPriByPassMax:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        McqHiPriByPassMax:3 ; ///<
+    UINT32                                        MctEccDisLatOptEn:1 ; ///<
+    UINT32                                          MctVarPriCntLmt:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x118_STRUCT;
+
+// **** D18F2x11C Register Definition ****
+// Address
+#define D18F2x11C_ADDRESS                                       0x11c
+
+// Type
+#define D18F2x11C_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x11C_DctWrLimit_OFFSET                             0
+#define D18F2x11C_DctWrLimit_WIDTH                              2
+#define D18F2x11C_DctWrLimit_MASK                               0x3
+#define D18F2x11C_MctWrLimit_OFFSET                             2
+#define D18F2x11C_MctWrLimit_WIDTH                              5
+#define D18F2x11C_MctWrLimit_MASK                               0x7c
+#define D18F2x11C_MctPrefReqLimit_OFFSET                        7
+#define D18F2x11C_MctPrefReqLimit_WIDTH                         5
+#define D18F2x11C_MctPrefReqLimit_MASK                          0xf80
+#define D18F2x11C_PrefCpuDis_OFFSET                             12
+#define D18F2x11C_PrefCpuDis_WIDTH                              1
+#define D18F2x11C_PrefCpuDis_MASK                               0x1000
+#define D18F2x11C_PrefIoDis_OFFSET                              13
+#define D18F2x11C_PrefIoDis_WIDTH                               1
+#define D18F2x11C_PrefIoDis_MASK                                0x2000
+#define D18F2x11C_PrefIoFixStrideEn_OFFSET                      14
+#define D18F2x11C_PrefIoFixStrideEn_WIDTH                       1
+#define D18F2x11C_PrefIoFixStrideEn_MASK                        0x4000
+#define D18F2x11C_PrefFixStrideEn_OFFSET                        15
+#define D18F2x11C_PrefFixStrideEn_WIDTH                         1
+#define D18F2x11C_PrefFixStrideEn_MASK                          0x8000
+#define D18F2x11C_PrefFixDist_OFFSET                            16
+#define D18F2x11C_PrefFixDist_WIDTH                             2
+#define D18F2x11C_PrefFixDist_MASK                              0x30000
+#define D18F2x11C_PrefConfSat_OFFSET                            18
+#define D18F2x11C_PrefConfSat_WIDTH                             2
+#define D18F2x11C_PrefConfSat_MASK                              0xc0000
+#define D18F2x11C_PrefOneConf_OFFSET                            20
+#define D18F2x11C_PrefOneConf_WIDTH                             2
+#define D18F2x11C_PrefOneConf_MASK                              0x300000
+#define D18F2x11C_PrefTwoConf_OFFSET                            22
+#define D18F2x11C_PrefTwoConf_WIDTH                             3
+#define D18F2x11C_PrefTwoConf_MASK                              0x1c00000
+#define D18F2x11C_PrefThreeConf_OFFSET                          25
+#define D18F2x11C_PrefThreeConf_WIDTH                           3
+#define D18F2x11C_PrefThreeConf_MASK                            0xe000000
+#define D18F2x11C_PrefDramTrainMode_OFFSET                      28
+#define D18F2x11C_PrefDramTrainMode_WIDTH                       1
+#define D18F2x11C_PrefDramTrainMode_MASK                        0x10000000
+#define D18F2x11C_FlushWrOnStpGnt_OFFSET                        29
+#define D18F2x11C_FlushWrOnStpGnt_WIDTH                         1
+#define D18F2x11C_FlushWrOnStpGnt_MASK                          0x20000000
+#define D18F2x11C_FlushWr_OFFSET                                30
+#define D18F2x11C_FlushWr_WIDTH                                 1
+#define D18F2x11C_FlushWr_MASK                                  0x40000000
+#define D18F2x11C_Reserved_31_31_OFFSET                         31
+#define D18F2x11C_Reserved_31_31_WIDTH                          1
+#define D18F2x11C_Reserved_31_31_MASK                           0x80000000
+
+/// D18F2x11C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               DctWrLimit:2 ; ///<
+    UINT32                                               MctWrLimit:5 ; ///<
+    UINT32                                          MctPrefReqLimit:5 ; ///<
+    UINT32                                               PrefCpuDis:1 ; ///<
+    UINT32                                                PrefIoDis:1 ; ///<
+    UINT32                                        PrefIoFixStrideEn:1 ; ///<
+    UINT32                                          PrefFixStrideEn:1 ; ///<
+    UINT32                                              PrefFixDist:2 ; ///<
+    UINT32                                              PrefConfSat:2 ; ///<
+    UINT32                                              PrefOneConf:2 ; ///<
+    UINT32                                              PrefTwoConf:3 ; ///<
+    UINT32                                            PrefThreeConf:3 ; ///<
+    UINT32                                        PrefDramTrainMode:1 ; ///<
+    UINT32                                          FlushWrOnStpGnt:1 ; ///<
+    UINT32                                                  FlushWr:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x11C_STRUCT;
+
+
+
+
+
+
+// **** D18F2x1B0 Register Definition ****
+// Address
+#define D18F2x1B0_ADDRESS                                       0x1b0
+
+// Type
+#define D18F2x1B0_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x1B0_AdapPrefMissRatio_OFFSET                      0
+#define D18F2x1B0_AdapPrefMissRatio_WIDTH                       2
+#define D18F2x1B0_AdapPrefMissRatio_MASK                        0x3
+#define D18F2x1B0_AdapPrefPositiveStep_OFFSET                   2
+#define D18F2x1B0_AdapPrefPositiveStep_WIDTH                    2
+#define D18F2x1B0_AdapPrefPositiveStep_MASK                     0xc
+#define D18F2x1B0_AdapPrefNegativeStep_OFFSET                   4
+#define D18F2x1B0_AdapPrefNegativeStep_WIDTH                    2
+#define D18F2x1B0_AdapPrefNegativeStep_MASK                     0x30
+#define D18F2x1B0_Reserved_7_6_OFFSET                           6
+#define D18F2x1B0_Reserved_7_6_WIDTH                            2
+#define D18F2x1B0_Reserved_7_6_MASK                             0xc0
+#define D18F2x1B0_CohPrefPrbLmt_OFFSET                          8
+#define D18F2x1B0_CohPrefPrbLmt_WIDTH                           3
+#define D18F2x1B0_CohPrefPrbLmt_MASK                            0x700
+#define D18F2x1B0_DisIoCohPref_OFFSET                           11
+#define D18F2x1B0_DisIoCohPref_WIDTH                            1
+#define D18F2x1B0_DisIoCohPref_MASK                             0x800
+#define D18F2x1B0_EnSplitDctLimits_OFFSET                       12
+#define D18F2x1B0_EnSplitDctLimits_WIDTH                        1
+#define D18F2x1B0_EnSplitDctLimits_MASK                         0x1000
+#define D18F2x1B0_Reserved_17_13_OFFSET                         13
+#define D18F2x1B0_Reserved_17_13_WIDTH                          5
+#define D18F2x1B0_Reserved_17_13_MASK                           0x3e000
+#define D18F2x1B0_Reserved_19_18_OFFSET                         18
+#define D18F2x1B0_Reserved_19_18_WIDTH                          2
+#define D18F2x1B0_Reserved_19_18_MASK                           0xc0000
+#define D18F2x1B0_DblPrefEn_OFFSET                              20
+#define D18F2x1B0_DblPrefEn_WIDTH                               1
+#define D18F2x1B0_DblPrefEn_MASK                                0x100000
+#define D18F2x1B0_Reserved_21_21_OFFSET                         21
+#define D18F2x1B0_Reserved_21_21_WIDTH                          1
+#define D18F2x1B0_Reserved_21_21_MASK                           0x200000
+#define D18F2x1B0_PrefFourConf_OFFSET                           22
+#define D18F2x1B0_PrefFourConf_WIDTH                            3
+#define D18F2x1B0_PrefFourConf_MASK                             0x1c00000
+#define D18F2x1B0_PrefFiveConf_OFFSET                           25
+#define D18F2x1B0_PrefFiveConf_WIDTH                            3
+#define D18F2x1B0_PrefFiveConf_MASK                             0xe000000
+#define D18F2x1B0_DcqBwThrotWm_OFFSET                           28
+#define D18F2x1B0_DcqBwThrotWm_WIDTH                            4
+#define D18F2x1B0_DcqBwThrotWm_MASK                             0xf0000000
+
+/// D18F2x1B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AdapPrefMissRatio:2 ; ///<
+    UINT32                                     AdapPrefPositiveStep:2 ; ///<
+    UINT32                                     AdapPrefNegativeStep:2 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                            CohPrefPrbLmt:3 ; ///<
+    UINT32                                             DisIoCohPref:1 ; ///<
+    UINT32                                         EnSplitDctLimits:1 ; ///<
+    UINT32                                           Reserved_17_13:5 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                DblPrefEn:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                             PrefFourConf:3 ; ///<
+    UINT32                                             PrefFiveConf:3 ; ///<
+    UINT32                                             DcqBwThrotWm:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x1B0_STRUCT;
+
+// **** D18F2x1B4 Register Definition ****
+// Address
+#define D18F2x1B4_ADDRESS                                       0x1b4
+
+// Type
+#define D18F2x1B4_TYPE                                          TYPE_D18F2
+// Field Data
+#define D18F2x1B4_DcqBwThrotWm1_OFFSET                          0
+#define D18F2x1B4_DcqBwThrotWm1_WIDTH                           5
+#define D18F2x1B4_DcqBwThrotWm1_MASK                            0x1f
+#define D18F2x1B4_DcqBwThrotWm2_OFFSET                          5
+#define D18F2x1B4_DcqBwThrotWm2_WIDTH                           5
+#define D18F2x1B4_DcqBwThrotWm2_MASK                            0x3e0
+#define D18F2x1B4_DemandPropWm1_OFFSET                          10
+#define D18F2x1B4_DemandPropWm1_WIDTH                           1
+#define D18F2x1B4_DemandPropWm1_MASK                            0x400
+#define D18F2x1B4_DemandAlloWm1_OFFSET                          11
+#define D18F2x1B4_DemandAlloWm1_WIDTH                           1
+#define D18F2x1B4_DemandAlloWm1_MASK                            0x800
+#define D18F2x1B4_StridePropWm1_OFFSET                          12
+#define D18F2x1B4_StridePropWm1_WIDTH                           1
+#define D18F2x1B4_StridePropWm1_MASK                            0x1000
+#define D18F2x1B4_StrideAlloWm1_OFFSET                          13
+#define D18F2x1B4_StrideAlloWm1_WIDTH                           1
+#define D18F2x1B4_StrideAlloWm1_MASK                            0x2000
+#define D18F2x1B4_RegionPropWm1_OFFSET                          14
+#define D18F2x1B4_RegionPropWm1_WIDTH                           1
+#define D18F2x1B4_RegionPropWm1_MASK                            0x4000
+#define D18F2x1B4_RegionAlloWm1_OFFSET                          15
+#define D18F2x1B4_RegionAlloWm1_WIDTH                           1
+#define D18F2x1B4_RegionAlloWm1_MASK                            0x8000
+#define D18F2x1B4_DemandPropWm2_OFFSET                          16
+#define D18F2x1B4_DemandPropWm2_WIDTH                           1
+#define D18F2x1B4_DemandPropWm2_MASK                            0x10000
+#define D18F2x1B4_DemandAlloWm2_OFFSET                          17
+#define D18F2x1B4_DemandAlloWm2_WIDTH                           1
+#define D18F2x1B4_DemandAlloWm2_MASK                            0x20000
+#define D18F2x1B4_StridePropWm2_OFFSET                          18
+#define D18F2x1B4_StridePropWm2_WIDTH                           1
+#define D18F2x1B4_StridePropWm2_MASK                            0x40000
+#define D18F2x1B4_StrideAlloWm2_OFFSET                          19
+#define D18F2x1B4_StrideAlloWm2_WIDTH                           1
+#define D18F2x1B4_StrideAlloWm2_MASK                            0x80000
+#define D18F2x1B4_RegionPropWm2_OFFSET                          20
+#define D18F2x1B4_RegionPropWm2_WIDTH                           1
+#define D18F2x1B4_RegionPropWm2_MASK                            0x100000
+#define D18F2x1B4_RegionAlloWm2_OFFSET                          21
+#define D18F2x1B4_RegionAlloWm2_WIDTH                           1
+#define D18F2x1B4_RegionAlloWm2_MASK                            0x200000
+#define D18F2x1B4_SpecPrefDisWm1_OFFSET                         22
+#define D18F2x1B4_SpecPrefDisWm1_WIDTH                          1
+#define D18F2x1B4_SpecPrefDisWm1_MASK                           0x400000
+#define D18F2x1B4_Reserved_25_23_OFFSET                         23
+#define D18F2x1B4_Reserved_25_23_WIDTH                          3
+#define D18F2x1B4_Reserved_25_23_MASK                           0x3800000
+#define D18F2x1B4_EnSplitMctDatBuffers_OFFSET                   26
+#define D18F2x1B4_EnSplitMctDatBuffers_WIDTH                    1
+#define D18F2x1B4_EnSplitMctDatBuffers_MASK                     0x4000000
+#define D18F2x1B4_FlushWrOnS3StpGnt_OFFSET                      27
+#define D18F2x1B4_FlushWrOnS3StpGnt_WIDTH                       1
+#define D18F2x1B4_FlushWrOnS3StpGnt_MASK                        0x8000000
+#define D18F2x1B4_S3SmafId_OFFSET                               28
+#define D18F2x1B4_S3SmafId_WIDTH                                3
+#define D18F2x1B4_S3SmafId_MASK                                 0x70000000
+#define D18F2x1B4_FlushOnMmioWrEn_OFFSET                        31
+#define D18F2x1B4_FlushOnMmioWrEn_WIDTH                         1
+#define D18F2x1B4_FlushOnMmioWrEn_MASK                          0x80000000
+
+/// D18F2x1B4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DcqBwThrotWm1:5 ; ///<
+    UINT32                                            DcqBwThrotWm2:5 ; ///<
+    UINT32                                            DemandPropWm1:1 ; ///<
+    UINT32                                            DemandAlloWm1:1 ; ///<
+    UINT32                                            StridePropWm1:1 ; ///<
+    UINT32                                            StrideAlloWm1:1 ; ///<
+    UINT32                                            RegionPropWm1:1 ; ///<
+    UINT32                                            RegionAlloWm1:1 ; ///<
+    UINT32                                            DemandPropWm2:1 ; ///<
+    UINT32                                            DemandAlloWm2:1 ; ///<
+    UINT32                                            StridePropWm2:1 ; ///<
+    UINT32                                            StrideAlloWm2:1 ; ///<
+    UINT32                                            RegionPropWm2:1 ; ///<
+    UINT32                                            RegionAlloWm2:1 ; ///<
+    UINT32                                           SpecPrefDisWm1:1 ; ///<
+    UINT32                                           Reserved_25_23:3 ; ///<
+    UINT32                                     EnSplitMctDatBuffers:1 ; ///<
+    UINT32                                        FlushWrOnS3StpGnt:1 ; ///<
+    UINT32                                                 S3SmafId:3 ; ///<
+    UINT32                                          FlushOnMmioWrEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x1B4_STRUCT;
+
+// **** D18F2x200_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x200_dct0_mp1_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x200_dct0_mp1_Tcl_OFFSET                           0
+#define D18F2x200_dct0_mp1_Tcl_WIDTH                            5
+#define D18F2x200_dct0_mp1_Tcl_MASK                             0x1f
+#define D18F2x200_dct0_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct0_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct0_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct0_mp1_Trcd_OFFSET                          8
+#define D18F2x200_dct0_mp1_Trcd_WIDTH                           5
+#define D18F2x200_dct0_mp1_Trcd_MASK                            0x1f00
+#define D18F2x200_dct0_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct0_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct0_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct0_mp1_Trp_OFFSET                           16
+#define D18F2x200_dct0_mp1_Trp_WIDTH                            5
+#define D18F2x200_dct0_mp1_Trp_MASK                             0x1f0000
+#define D18F2x200_dct0_mp1_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct0_mp1_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct0_mp1_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct0_mp1_Tras_OFFSET                          24
+#define D18F2x200_dct0_mp1_Tras_WIDTH                           6
+#define D18F2x200_dct0_mp1_Tras_MASK                            0x3f000000
+#define D18F2x200_dct0_mp1_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct0_mp1_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct0_mp1_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct0_mp1_STRUCT;
+
+// **** D18F2x200_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x200_dct0_mp0_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x200_dct0_mp0_Tcl_OFFSET                           0
+#define D18F2x200_dct0_mp0_Tcl_WIDTH                            5
+#define D18F2x200_dct0_mp0_Tcl_MASK                             0x1f
+#define D18F2x200_dct0_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct0_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct0_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct0_mp0_Trcd_OFFSET                          8
+#define D18F2x200_dct0_mp0_Trcd_WIDTH                           5
+#define D18F2x200_dct0_mp0_Trcd_MASK                            0x1f00
+#define D18F2x200_dct0_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct0_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct0_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct0_mp0_Trp_OFFSET                           16
+#define D18F2x200_dct0_mp0_Trp_WIDTH                            5
+#define D18F2x200_dct0_mp0_Trp_MASK                             0x1f0000
+#define D18F2x200_dct0_mp0_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct0_mp0_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct0_mp0_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct0_mp0_Tras_OFFSET                          24
+#define D18F2x200_dct0_mp0_Tras_WIDTH                           6
+#define D18F2x200_dct0_mp0_Tras_MASK                            0x3f000000
+#define D18F2x200_dct0_mp0_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct0_mp0_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct0_mp0_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct0_mp0_STRUCT;
+
+// **** D18F2x200_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x200_dct1_mp1_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x200_dct1_mp1_Tcl_OFFSET                           0
+#define D18F2x200_dct1_mp1_Tcl_WIDTH                            5
+#define D18F2x200_dct1_mp1_Tcl_MASK                             0x1f
+#define D18F2x200_dct1_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct1_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct1_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct1_mp1_Trcd_OFFSET                          8
+#define D18F2x200_dct1_mp1_Trcd_WIDTH                           5
+#define D18F2x200_dct1_mp1_Trcd_MASK                            0x1f00
+#define D18F2x200_dct1_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct1_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct1_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct1_mp1_Trp_OFFSET                           16
+#define D18F2x200_dct1_mp1_Trp_WIDTH                            5
+#define D18F2x200_dct1_mp1_Trp_MASK                             0x1f0000
+#define D18F2x200_dct1_mp1_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct1_mp1_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct1_mp1_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct1_mp1_Tras_OFFSET                          24
+#define D18F2x200_dct1_mp1_Tras_WIDTH                           6
+#define D18F2x200_dct1_mp1_Tras_MASK                            0x3f000000
+#define D18F2x200_dct1_mp1_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct1_mp1_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct1_mp1_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct1_mp1_STRUCT;
+
+// **** D18F2x200_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x200_dct1_mp0_ADDRESS                              0x200
+
+// Type
+#define D18F2x200_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x200_dct1_mp0_Tcl_OFFSET                           0
+#define D18F2x200_dct1_mp0_Tcl_WIDTH                            5
+#define D18F2x200_dct1_mp0_Tcl_MASK                             0x1f
+#define D18F2x200_dct1_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x200_dct1_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x200_dct1_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x200_dct1_mp0_Trcd_OFFSET                          8
+#define D18F2x200_dct1_mp0_Trcd_WIDTH                           5
+#define D18F2x200_dct1_mp0_Trcd_MASK                            0x1f00
+#define D18F2x200_dct1_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x200_dct1_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x200_dct1_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x200_dct1_mp0_Trp_OFFSET                           16
+#define D18F2x200_dct1_mp0_Trp_WIDTH                            5
+#define D18F2x200_dct1_mp0_Trp_MASK                             0x1f0000
+#define D18F2x200_dct1_mp0_Reserved_23_21_OFFSET                21
+#define D18F2x200_dct1_mp0_Reserved_23_21_WIDTH                 3
+#define D18F2x200_dct1_mp0_Reserved_23_21_MASK                  0xe00000
+#define D18F2x200_dct1_mp0_Tras_OFFSET                          24
+#define D18F2x200_dct1_mp0_Tras_WIDTH                           6
+#define D18F2x200_dct1_mp0_Tras_MASK                            0x3f000000
+#define D18F2x200_dct1_mp0_Reserved_31_30_OFFSET                30
+#define D18F2x200_dct1_mp0_Reserved_31_30_WIDTH                 2
+#define D18F2x200_dct1_mp0_Reserved_31_30_MASK                  0xc0000000
+
+/// D18F2x200_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tcl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Trcd:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                      Trp:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                                     Tras:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x200_dct1_mp0_STRUCT;
+
+// **** D18F2x204_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x204_dct0_mp0_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x204_dct0_mp0_Trc_OFFSET                           0
+#define D18F2x204_dct0_mp0_Trc_WIDTH                            6
+#define D18F2x204_dct0_mp0_Trc_MASK                             0x3f
+#define D18F2x204_dct0_mp0_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct0_mp0_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct0_mp0_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct0_mp0_Trrd_OFFSET                          8
+#define D18F2x204_dct0_mp0_Trrd_WIDTH                           4
+#define D18F2x204_dct0_mp0_Trrd_MASK                            0xf00
+#define D18F2x204_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct0_mp0_FourActWindow_OFFSET                 16
+#define D18F2x204_dct0_mp0_FourActWindow_WIDTH                  6
+#define D18F2x204_dct0_mp0_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct0_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct0_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct0_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct0_mp0_Trtp_OFFSET                          24
+#define D18F2x204_dct0_mp0_Trtp_WIDTH                           4
+#define D18F2x204_dct0_mp0_Trtp_MASK                            0xf000000
+#define D18F2x204_dct0_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct0_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct0_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct0_mp0_STRUCT;
+
+// **** D18F2x204_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x204_dct1_mp0_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x204_dct1_mp0_Trc_OFFSET                           0
+#define D18F2x204_dct1_mp0_Trc_WIDTH                            6
+#define D18F2x204_dct1_mp0_Trc_MASK                             0x3f
+#define D18F2x204_dct1_mp0_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct1_mp0_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct1_mp0_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct1_mp0_Trrd_OFFSET                          8
+#define D18F2x204_dct1_mp0_Trrd_WIDTH                           4
+#define D18F2x204_dct1_mp0_Trrd_MASK                            0xf00
+#define D18F2x204_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct1_mp0_FourActWindow_OFFSET                 16
+#define D18F2x204_dct1_mp0_FourActWindow_WIDTH                  6
+#define D18F2x204_dct1_mp0_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct1_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct1_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct1_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct1_mp0_Trtp_OFFSET                          24
+#define D18F2x204_dct1_mp0_Trtp_WIDTH                           4
+#define D18F2x204_dct1_mp0_Trtp_MASK                            0xf000000
+#define D18F2x204_dct1_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct1_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct1_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct1_mp0_STRUCT;
+
+// **** D18F2x204_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x204_dct0_mp1_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x204_dct0_mp1_Trc_OFFSET                           0
+#define D18F2x204_dct0_mp1_Trc_WIDTH                            6
+#define D18F2x204_dct0_mp1_Trc_MASK                             0x3f
+#define D18F2x204_dct0_mp1_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct0_mp1_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct0_mp1_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct0_mp1_Trrd_OFFSET                          8
+#define D18F2x204_dct0_mp1_Trrd_WIDTH                           4
+#define D18F2x204_dct0_mp1_Trrd_MASK                            0xf00
+#define D18F2x204_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct0_mp1_FourActWindow_OFFSET                 16
+#define D18F2x204_dct0_mp1_FourActWindow_WIDTH                  6
+#define D18F2x204_dct0_mp1_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct0_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct0_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct0_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct0_mp1_Trtp_OFFSET                          24
+#define D18F2x204_dct0_mp1_Trtp_WIDTH                           4
+#define D18F2x204_dct0_mp1_Trtp_MASK                            0xf000000
+#define D18F2x204_dct0_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct0_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct0_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct0_mp1_STRUCT;
+
+// **** D18F2x204_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x204_dct1_mp1_ADDRESS                              0x204
+
+// Type
+#define D18F2x204_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x204_dct1_mp1_Trc_OFFSET                           0
+#define D18F2x204_dct1_mp1_Trc_WIDTH                            6
+#define D18F2x204_dct1_mp1_Trc_MASK                             0x3f
+#define D18F2x204_dct1_mp1_Reserved_7_6_OFFSET                  6
+#define D18F2x204_dct1_mp1_Reserved_7_6_WIDTH                   2
+#define D18F2x204_dct1_mp1_Reserved_7_6_MASK                    0xc0
+#define D18F2x204_dct1_mp1_Trrd_OFFSET                          8
+#define D18F2x204_dct1_mp1_Trrd_WIDTH                           4
+#define D18F2x204_dct1_mp1_Trrd_MASK                            0xf00
+#define D18F2x204_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x204_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x204_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x204_dct1_mp1_FourActWindow_OFFSET                 16
+#define D18F2x204_dct1_mp1_FourActWindow_WIDTH                  6
+#define D18F2x204_dct1_mp1_FourActWindow_MASK                   0x3f0000
+#define D18F2x204_dct1_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x204_dct1_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x204_dct1_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x204_dct1_mp1_Trtp_OFFSET                          24
+#define D18F2x204_dct1_mp1_Trtp_WIDTH                           4
+#define D18F2x204_dct1_mp1_Trtp_MASK                            0xf000000
+#define D18F2x204_dct1_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x204_dct1_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x204_dct1_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x204_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Trc:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                     Trrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                            FourActWindow:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                     Trtp:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x204_dct1_mp1_STRUCT;
+
+// **** D18F2x208_dct0 Register Definition ****
+// Address
+#define D18F2x208_dct0_ADDRESS                                  0x208
+
+// Type
+#define D18F2x208_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x208_dct0_Trfc0_OFFSET                             0
+#define D18F2x208_dct0_Trfc0_WIDTH                              3
+#define D18F2x208_dct0_Trfc0_MASK                               0x7
+#define D18F2x208_dct0_Reserved_7_3_OFFSET                      3
+#define D18F2x208_dct0_Reserved_7_3_WIDTH                       5
+#define D18F2x208_dct0_Reserved_7_3_MASK                        0xf8
+#define D18F2x208_dct0_Trfc1_OFFSET                             8
+#define D18F2x208_dct0_Trfc1_WIDTH                              3
+#define D18F2x208_dct0_Trfc1_MASK                               0x700
+#define D18F2x208_dct0_Reserved_15_11_OFFSET                    11
+#define D18F2x208_dct0_Reserved_15_11_WIDTH                     5
+#define D18F2x208_dct0_Reserved_15_11_MASK                      0xf800
+#define D18F2x208_dct0_Trfc2_OFFSET                             16
+#define D18F2x208_dct0_Trfc2_WIDTH                              3
+#define D18F2x208_dct0_Trfc2_MASK                               0x70000
+#define D18F2x208_dct0_Reserved_23_19_OFFSET                    19
+#define D18F2x208_dct0_Reserved_23_19_WIDTH                     5
+#define D18F2x208_dct0_Reserved_23_19_MASK                      0xf80000
+#define D18F2x208_dct0_Trfc3_OFFSET                             24
+#define D18F2x208_dct0_Trfc3_WIDTH                              3
+#define D18F2x208_dct0_Trfc3_MASK                               0x7000000
+#define D18F2x208_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x208_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x208_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x208_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Trfc0:3 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                                    Trfc1:3 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                                    Trfc2:3 ; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                                    Trfc3:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x208_dct0_STRUCT;
+
+// **** D18F2x208_dct1 Register Definition ****
+// Address
+#define D18F2x208_dct1_ADDRESS                                  0x208
+
+// Type
+#define D18F2x208_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x208_dct1_Trfc0_OFFSET                             0
+#define D18F2x208_dct1_Trfc0_WIDTH                              3
+#define D18F2x208_dct1_Trfc0_MASK                               0x7
+#define D18F2x208_dct1_Reserved_7_3_OFFSET                      3
+#define D18F2x208_dct1_Reserved_7_3_WIDTH                       5
+#define D18F2x208_dct1_Reserved_7_3_MASK                        0xf8
+#define D18F2x208_dct1_Trfc1_OFFSET                             8
+#define D18F2x208_dct1_Trfc1_WIDTH                              3
+#define D18F2x208_dct1_Trfc1_MASK                               0x700
+#define D18F2x208_dct1_Reserved_15_11_OFFSET                    11
+#define D18F2x208_dct1_Reserved_15_11_WIDTH                     5
+#define D18F2x208_dct1_Reserved_15_11_MASK                      0xf800
+#define D18F2x208_dct1_Trfc2_OFFSET                             16
+#define D18F2x208_dct1_Trfc2_WIDTH                              3
+#define D18F2x208_dct1_Trfc2_MASK                               0x70000
+#define D18F2x208_dct1_Reserved_23_19_OFFSET                    19
+#define D18F2x208_dct1_Reserved_23_19_WIDTH                     5
+#define D18F2x208_dct1_Reserved_23_19_MASK                      0xf80000
+#define D18F2x208_dct1_Trfc3_OFFSET                             24
+#define D18F2x208_dct1_Trfc3_WIDTH                              3
+#define D18F2x208_dct1_Trfc3_MASK                               0x7000000
+#define D18F2x208_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x208_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x208_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x208_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Trfc0:3 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                                    Trfc1:3 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                                    Trfc2:3 ; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                                    Trfc3:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x208_dct1_STRUCT;
+
+// **** D18F2x20C_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x20C_dct0_mp1_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x20C_dct0_mp1_Tcwl_OFFSET                          0
+#define D18F2x20C_dct0_mp1_Tcwl_WIDTH                           5
+#define D18F2x20C_dct0_mp1_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct0_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct0_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct0_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct0_mp1_Twtr_OFFSET                          8
+#define D18F2x20C_dct0_mp1_Twtr_WIDTH                           4
+#define D18F2x20C_dct0_mp1_Twtr_MASK                            0xf00
+#define D18F2x20C_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct0_mp1_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct0_mp1_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct0_mp1_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct0_mp1_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct0_mp1_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct0_mp1_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct0_mp1_STRUCT;
+
+// **** D18F2x20C_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x20C_dct1_mp1_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x20C_dct1_mp1_Tcwl_OFFSET                          0
+#define D18F2x20C_dct1_mp1_Tcwl_WIDTH                           5
+#define D18F2x20C_dct1_mp1_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct1_mp1_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct1_mp1_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct1_mp1_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct1_mp1_Twtr_OFFSET                          8
+#define D18F2x20C_dct1_mp1_Twtr_WIDTH                           4
+#define D18F2x20C_dct1_mp1_Twtr_MASK                            0xf00
+#define D18F2x20C_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct1_mp1_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct1_mp1_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct1_mp1_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct1_mp1_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct1_mp1_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct1_mp1_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct1_mp1_STRUCT;
+
+// **** D18F2x20C_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x20C_dct1_mp0_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x20C_dct1_mp0_Tcwl_OFFSET                          0
+#define D18F2x20C_dct1_mp0_Tcwl_WIDTH                           5
+#define D18F2x20C_dct1_mp0_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct1_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct1_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct1_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct1_mp0_Twtr_OFFSET                          8
+#define D18F2x20C_dct1_mp0_Twtr_WIDTH                           4
+#define D18F2x20C_dct1_mp0_Twtr_MASK                            0xf00
+#define D18F2x20C_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct1_mp0_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct1_mp0_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct1_mp0_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct1_mp0_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct1_mp0_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct1_mp0_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct1_mp0_STRUCT;
+
+// **** D18F2x20C_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x20C_dct0_mp0_ADDRESS                              0x20c
+
+// Type
+#define D18F2x20C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x20C_dct0_mp0_Tcwl_OFFSET                          0
+#define D18F2x20C_dct0_mp0_Tcwl_WIDTH                           5
+#define D18F2x20C_dct0_mp0_Tcwl_MASK                            0x1f
+#define D18F2x20C_dct0_mp0_Reserved_7_5_OFFSET                  5
+#define D18F2x20C_dct0_mp0_Reserved_7_5_WIDTH                   3
+#define D18F2x20C_dct0_mp0_Reserved_7_5_MASK                    0xe0
+#define D18F2x20C_dct0_mp0_Twtr_OFFSET                          8
+#define D18F2x20C_dct0_mp0_Twtr_WIDTH                           4
+#define D18F2x20C_dct0_mp0_Twtr_MASK                            0xf00
+#define D18F2x20C_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x20C_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x20C_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x20C_dct0_mp0_WrDqDqsEarly_OFFSET                  16
+#define D18F2x20C_dct0_mp0_WrDqDqsEarly_WIDTH                   2
+#define D18F2x20C_dct0_mp0_WrDqDqsEarly_MASK                    0x30000
+#define D18F2x20C_dct0_mp0_Reserved_31_18_OFFSET                18
+#define D18F2x20C_dct0_mp0_Reserved_31_18_WIDTH                 14
+#define D18F2x20C_dct0_mp0_Reserved_31_18_MASK                  0xfffc0000
+
+/// D18F2x20C_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tcwl:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                     Twtr:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrDqDqsEarly:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x20C_dct0_mp0_STRUCT;
+
+// **** D18F2x210_dct1_nbp0 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp0_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp0_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp0_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp0_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp0_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp0_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp0_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp0_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp0_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp0_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp0_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp0_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp0_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp0_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp0_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp0_STRUCT;
+
+// **** D18F2x210_dct0_nbp2 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp2_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp2_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp2_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp2_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp2_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp2_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp2_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp2_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp2_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp2_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp2_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp2_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp2_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp2_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp2_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp2_STRUCT;
+
+// **** D18F2x210_dct1_nbp1 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp1_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp1_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp1_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp1_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp1_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp1_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp1_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp1_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp1_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp1_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp1_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp1_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp1_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp1_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp1_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp1_STRUCT;
+
+// **** D18F2x210_dct1_nbp3 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp3_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp3_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp3_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp3_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp3_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp3_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp3_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp3_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp3_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp3_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp3_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp3_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp3_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp3_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp3_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp3_STRUCT;
+
+// **** D18F2x210_dct0_nbp0 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp0_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp0_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp0_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp0_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp0_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp0_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp0_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp0_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp0_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp0_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp0_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp0_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp0_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp0_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp0_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp0_STRUCT;
+
+// **** D18F2x210_dct0_nbp3 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp3_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp3_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp3_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp3_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp3_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp3_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp3_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp3_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp3_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp3_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp3_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp3_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp3_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp3_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp3_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp3_STRUCT;
+
+// **** D18F2x210_dct1_nbp2 Register Definition ****
+// Address
+#define D18F2x210_dct1_nbp2_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct1_nbp2_TYPE                                TYPE_D18F2_dct1
+// Field Data
+#define D18F2x210_dct1_nbp2_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct1_nbp2_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct1_nbp2_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct1_nbp2_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct1_nbp2_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct1_nbp2_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct1_nbp2_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct1_nbp2_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct1_nbp2_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct1_nbp2_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct1_nbp2_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct1_nbp2_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct1_nbp2_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct1_nbp2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct1_nbp2_STRUCT;
+
+// **** D18F2x210_dct0_nbp1 Register Definition ****
+// Address
+#define D18F2x210_dct0_nbp1_ADDRESS                             0x210
+
+// Type
+#define D18F2x210_dct0_nbp1_TYPE                                TYPE_D18F2_dct0
+// Field Data
+#define D18F2x210_dct0_nbp1_RdPtrInit_OFFSET                    0
+#define D18F2x210_dct0_nbp1_RdPtrInit_WIDTH                     4
+#define D18F2x210_dct0_nbp1_RdPtrInit_MASK                      0xf
+#define D18F2x210_dct0_nbp1_Reserved_15_4_OFFSET                4
+#define D18F2x210_dct0_nbp1_Reserved_15_4_WIDTH                 12
+#define D18F2x210_dct0_nbp1_Reserved_15_4_MASK                  0xfff0
+#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_OFFSET              16
+#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_WIDTH               3
+#define D18F2x210_dct0_nbp1_DataTxFifoWrDly_MASK                0x70000
+#define D18F2x210_dct0_nbp1_Reserved_21_19_OFFSET               19
+#define D18F2x210_dct0_nbp1_Reserved_21_19_WIDTH                3
+#define D18F2x210_dct0_nbp1_Reserved_21_19_MASK                 0x380000
+#define D18F2x210_dct0_nbp1_MaxRdLatency_OFFSET                 22
+#define D18F2x210_dct0_nbp1_MaxRdLatency_WIDTH                  10
+#define D18F2x210_dct0_nbp1_MaxRdLatency_MASK                   0xffc00000
+
+/// D18F2x210_dct0_nbp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                RdPtrInit:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                          DataTxFifoWrDly:3 ; ///<
+    UINT32                                           Reserved_21_19:3 ; ///<
+    UINT32                                             MaxRdLatency:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x210_dct0_nbp1_STRUCT;
+
+// **** D18F2x214_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x214_dct1_mp1_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x214_dct1_mp1_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct1_mp1_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct1_mp1_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct1_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct1_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct1_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct1_mp1_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct1_mp1_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct1_mp1_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct1_mp1_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct1_mp1_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct1_mp1_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct1_mp1_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct1_mp1_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct1_mp1_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct1_mp1_STRUCT;
+
+// **** D18F2x214_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x214_dct0_mp0_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x214_dct0_mp0_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct0_mp0_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct0_mp0_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct0_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct0_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct0_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct0_mp0_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct0_mp0_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct0_mp0_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct0_mp0_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct0_mp0_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct0_mp0_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct0_mp0_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct0_mp0_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct0_mp0_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct0_mp0_STRUCT;
+
+// **** D18F2x214_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x214_dct1_mp0_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x214_dct1_mp0_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct1_mp0_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct1_mp0_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct1_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct1_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct1_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct1_mp0_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct1_mp0_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct1_mp0_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct1_mp0_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct1_mp0_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct1_mp0_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct1_mp0_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct1_mp0_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct1_mp0_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct1_mp0_STRUCT;
+
+// **** D18F2x214_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x214_dct0_mp1_ADDRESS                              0x214
+
+// Type
+#define D18F2x214_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x214_dct0_mp1_TwrwrDd_OFFSET                       0
+#define D18F2x214_dct0_mp1_TwrwrDd_WIDTH                        4
+#define D18F2x214_dct0_mp1_TwrwrDd_MASK                         0xf
+#define D18F2x214_dct0_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x214_dct0_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x214_dct0_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x214_dct0_mp1_TwrwrSdDc_OFFSET                     8
+#define D18F2x214_dct0_mp1_TwrwrSdDc_WIDTH                      4
+#define D18F2x214_dct0_mp1_TwrwrSdDc_MASK                       0xf00
+#define D18F2x214_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x214_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x214_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x214_dct0_mp1_TwrwrSdSc_OFFSET                     16
+#define D18F2x214_dct0_mp1_TwrwrSdSc_WIDTH                      4
+#define D18F2x214_dct0_mp1_TwrwrSdSc_MASK                       0xf0000
+#define D18F2x214_dct0_mp1_Reserved_31_20_OFFSET                20
+#define D18F2x214_dct0_mp1_Reserved_31_20_WIDTH                 12
+#define D18F2x214_dct0_mp1_Reserved_31_20_MASK                  0xfff00000
+
+/// D18F2x214_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TwrwrDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                TwrwrSdDc:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TwrwrSdSc:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x214_dct0_mp1_STRUCT;
+
+// **** D18F2x218_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x218_dct0_mp1_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x218_dct0_mp1_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct0_mp1_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct0_mp1_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct0_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct0_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct0_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct0_mp1_Twrrd_OFFSET                         8
+#define D18F2x218_dct0_mp1_Twrrd_WIDTH                          4
+#define D18F2x218_dct0_mp1_Twrrd_MASK                           0xf00
+#define D18F2x218_dct0_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct0_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct0_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct0_mp1_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct0_mp1_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct0_mp1_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct0_mp1_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct0_mp1_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct0_mp1_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct0_mp1_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct0_mp1_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct0_mp1_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct0_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct0_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct0_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct0_mp1_STRUCT;
+
+// **** D18F2x218_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x218_dct1_mp1_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x218_dct1_mp1_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct1_mp1_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct1_mp1_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct1_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct1_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct1_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct1_mp1_Twrrd_OFFSET                         8
+#define D18F2x218_dct1_mp1_Twrrd_WIDTH                          4
+#define D18F2x218_dct1_mp1_Twrrd_MASK                           0xf00
+#define D18F2x218_dct1_mp1_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct1_mp1_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct1_mp1_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct1_mp1_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct1_mp1_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct1_mp1_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct1_mp1_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct1_mp1_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct1_mp1_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct1_mp1_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct1_mp1_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct1_mp1_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct1_mp1_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct1_mp1_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct1_mp1_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct1_mp1_STRUCT;
+
+// **** D18F2x218_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x218_dct0_mp0_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x218_dct0_mp0_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct0_mp0_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct0_mp0_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct0_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct0_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct0_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct0_mp0_Twrrd_OFFSET                         8
+#define D18F2x218_dct0_mp0_Twrrd_WIDTH                          4
+#define D18F2x218_dct0_mp0_Twrrd_MASK                           0xf00
+#define D18F2x218_dct0_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct0_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct0_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct0_mp0_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct0_mp0_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct0_mp0_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct0_mp0_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct0_mp0_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct0_mp0_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct0_mp0_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct0_mp0_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct0_mp0_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct0_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct0_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct0_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct0_mp0_STRUCT;
+
+// **** D18F2x218_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x218_dct1_mp0_ADDRESS                              0x218
+
+// Type
+#define D18F2x218_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x218_dct1_mp0_TrdrdDd_OFFSET                       0
+#define D18F2x218_dct1_mp0_TrdrdDd_WIDTH                        4
+#define D18F2x218_dct1_mp0_TrdrdDd_MASK                         0xf
+#define D18F2x218_dct1_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x218_dct1_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x218_dct1_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x218_dct1_mp0_Twrrd_OFFSET                         8
+#define D18F2x218_dct1_mp0_Twrrd_WIDTH                          4
+#define D18F2x218_dct1_mp0_Twrrd_MASK                           0xf00
+#define D18F2x218_dct1_mp0_Reserved_15_12_OFFSET                12
+#define D18F2x218_dct1_mp0_Reserved_15_12_WIDTH                 4
+#define D18F2x218_dct1_mp0_Reserved_15_12_MASK                  0xf000
+#define D18F2x218_dct1_mp0_TrdrdSdDc_OFFSET                     16
+#define D18F2x218_dct1_mp0_TrdrdSdDc_WIDTH                      4
+#define D18F2x218_dct1_mp0_TrdrdSdDc_MASK                       0xf0000
+#define D18F2x218_dct1_mp0_Reserved_23_20_OFFSET                20
+#define D18F2x218_dct1_mp0_Reserved_23_20_WIDTH                 4
+#define D18F2x218_dct1_mp0_Reserved_23_20_MASK                  0xf00000
+#define D18F2x218_dct1_mp0_TrdrdSdSc_OFFSET                     24
+#define D18F2x218_dct1_mp0_TrdrdSdSc_WIDTH                      4
+#define D18F2x218_dct1_mp0_TrdrdSdSc_MASK                       0xf000000
+#define D18F2x218_dct1_mp0_Reserved_31_28_OFFSET                28
+#define D18F2x218_dct1_mp0_Reserved_31_28_WIDTH                 4
+#define D18F2x218_dct1_mp0_Reserved_31_28_MASK                  0xf0000000
+
+/// D18F2x218_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  TrdrdDd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Twrrd:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                TrdrdSdDc:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                                TrdrdSdSc:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x218_dct1_mp0_STRUCT;
+
+// **** D18F2x21C_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x21C_dct1_mp1_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x21C_dct1_mp1_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct1_mp1_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct1_mp1_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct1_mp1_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct1_mp1_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct1_mp1_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct1_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct1_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct1_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct1_mp1_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct1_mp1_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct1_mp1_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct1_mp1_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct1_mp1_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct1_mp1_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct1_mp1_STRUCT;
+
+// **** D18F2x21C_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x21C_dct1_mp0_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x21C_dct1_mp0_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct1_mp0_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct1_mp0_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct1_mp0_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct1_mp0_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct1_mp0_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct1_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct1_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct1_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct1_mp0_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct1_mp0_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct1_mp0_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct1_mp0_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct1_mp0_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct1_mp0_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct1_mp0_STRUCT;
+
+// **** D18F2x21C_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x21C_dct0_mp0_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x21C_dct0_mp0_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct0_mp0_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct0_mp0_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct0_mp0_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct0_mp0_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct0_mp0_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct0_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct0_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct0_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct0_mp0_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct0_mp0_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct0_mp0_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct0_mp0_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct0_mp0_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct0_mp0_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct0_mp0_STRUCT;
+
+// **** D18F2x21C_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x21C_dct0_mp1_ADDRESS                              0x21c
+
+// Type
+#define D18F2x21C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x21C_dct0_mp1_Reserved_7_0_OFFSET                  0
+#define D18F2x21C_dct0_mp1_Reserved_7_0_WIDTH                   8
+#define D18F2x21C_dct0_mp1_Reserved_7_0_MASK                    0xff
+#define D18F2x21C_dct0_mp1_TrwtTO_OFFSET                        8
+#define D18F2x21C_dct0_mp1_TrwtTO_WIDTH                         5
+#define D18F2x21C_dct0_mp1_TrwtTO_MASK                          0x1f00
+#define D18F2x21C_dct0_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x21C_dct0_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x21C_dct0_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x21C_dct0_mp1_TrwtWB_OFFSET                        16
+#define D18F2x21C_dct0_mp1_TrwtWB_WIDTH                         5
+#define D18F2x21C_dct0_mp1_TrwtWB_MASK                          0x1f0000
+#define D18F2x21C_dct0_mp1_Reserved_31_21_OFFSET                21
+#define D18F2x21C_dct0_mp1_Reserved_31_21_WIDTH                 11
+#define D18F2x21C_dct0_mp1_Reserved_31_21_MASK                  0xffe00000
+
+/// D18F2x21C_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                                   TrwtTO:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   TrwtWB:5 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x21C_dct0_mp1_STRUCT;
+
+// **** D18F2x220_dct1 Register Definition ****
+// Address
+#define D18F2x220_dct1_ADDRESS                                  0x220
+
+// Type
+#define D18F2x220_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x220_dct1_Tmrd_OFFSET                              0
+#define D18F2x220_dct1_Tmrd_WIDTH                               4
+#define D18F2x220_dct1_Tmrd_MASK                                0xf
+#define D18F2x220_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x220_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x220_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x220_dct1_Tmod_OFFSET                              8
+#define D18F2x220_dct1_Tmod_WIDTH                               5
+#define D18F2x220_dct1_Tmod_MASK                                0x1f00
+#define D18F2x220_dct1_Reserved_31_13_OFFSET                    13
+#define D18F2x220_dct1_Reserved_31_13_WIDTH                     19
+#define D18F2x220_dct1_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x220_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tmrd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                     Tmod:5 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x220_dct1_STRUCT;
+
+// **** D18F2x220_dct0 Register Definition ****
+// Address
+#define D18F2x220_dct0_ADDRESS                                  0x220
+
+// Type
+#define D18F2x220_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x220_dct0_Tmrd_OFFSET                              0
+#define D18F2x220_dct0_Tmrd_WIDTH                               4
+#define D18F2x220_dct0_Tmrd_MASK                                0xf
+#define D18F2x220_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x220_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x220_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x220_dct0_Tmod_OFFSET                              8
+#define D18F2x220_dct0_Tmod_WIDTH                               5
+#define D18F2x220_dct0_Tmod_MASK                                0x1f00
+#define D18F2x220_dct0_Reserved_31_13_OFFSET                    13
+#define D18F2x220_dct0_Reserved_31_13_WIDTH                     19
+#define D18F2x220_dct0_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x220_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Tmrd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                     Tmod:5 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x220_dct0_STRUCT;
+
+// **** D18F2x224_dct0 Register Definition ****
+// Address
+#define D18F2x224_dct0_ADDRESS                                  0x224
+
+// Type
+#define D18F2x224_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x224_dct0_Tzqoper_OFFSET                           0
+#define D18F2x224_dct0_Tzqoper_WIDTH                            4
+#define D18F2x224_dct0_Tzqoper_MASK                             0xf
+#define D18F2x224_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x224_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x224_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x224_dct0_Tzqcs_OFFSET                             8
+#define D18F2x224_dct0_Tzqcs_WIDTH                              3
+#define D18F2x224_dct0_Tzqcs_MASK                               0x700
+#define D18F2x224_dct0_Reserved_31_11_OFFSET                    11
+#define D18F2x224_dct0_Reserved_31_11_WIDTH                     21
+#define D18F2x224_dct0_Reserved_31_11_MASK                      0xfffff800
+
+/// D18F2x224_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Tzqoper:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Tzqcs:3 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x224_dct0_STRUCT;
+
+// **** D18F2x224_dct1 Register Definition ****
+// Address
+#define D18F2x224_dct1_ADDRESS                                  0x224
+
+// Type
+#define D18F2x224_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x224_dct1_Tzqoper_OFFSET                           0
+#define D18F2x224_dct1_Tzqoper_WIDTH                            4
+#define D18F2x224_dct1_Tzqoper_MASK                             0xf
+#define D18F2x224_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x224_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x224_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x224_dct1_Tzqcs_OFFSET                             8
+#define D18F2x224_dct1_Tzqcs_WIDTH                              3
+#define D18F2x224_dct1_Tzqcs_MASK                               0x700
+#define D18F2x224_dct1_Reserved_31_11_OFFSET                    11
+#define D18F2x224_dct1_Reserved_31_11_WIDTH                     21
+#define D18F2x224_dct1_Reserved_31_11_MASK                      0xfffff800
+
+/// D18F2x224_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Tzqoper:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    Tzqcs:3 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x224_dct1_STRUCT;
+
+// **** D18F2x228_dct1 Register Definition ****
+// Address
+#define D18F2x228_dct1_ADDRESS                                  0x228
+
+// Type
+#define D18F2x228_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x228_dct1_Tstag0_OFFSET                            0
+#define D18F2x228_dct1_Tstag0_WIDTH                             8
+#define D18F2x228_dct1_Tstag0_MASK                              0xff
+#define D18F2x228_dct1_Tstag1_OFFSET                            8
+#define D18F2x228_dct1_Tstag1_WIDTH                             8
+#define D18F2x228_dct1_Tstag1_MASK                              0xff00
+#define D18F2x228_dct1_Tstag2_OFFSET                            16
+#define D18F2x228_dct1_Tstag2_WIDTH                             8
+#define D18F2x228_dct1_Tstag2_MASK                              0xff0000
+#define D18F2x228_dct1_Tstag3_OFFSET                            24
+#define D18F2x228_dct1_Tstag3_WIDTH                             8
+#define D18F2x228_dct1_Tstag3_MASK                              0xff000000
+
+/// D18F2x228_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   Tstag0:8 ; ///<
+    UINT32                                                   Tstag1:8 ; ///<
+    UINT32                                                   Tstag2:8 ; ///<
+    UINT32                                                   Tstag3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x228_dct1_STRUCT;
+
+// **** D18F2x228_dct0 Register Definition ****
+// Address
+#define D18F2x228_dct0_ADDRESS                                  0x228
+
+// Type
+#define D18F2x228_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x228_dct0_Tstag0_OFFSET                            0
+#define D18F2x228_dct0_Tstag0_WIDTH                             8
+#define D18F2x228_dct0_Tstag0_MASK                              0xff
+#define D18F2x228_dct0_Tstag1_OFFSET                            8
+#define D18F2x228_dct0_Tstag1_WIDTH                             8
+#define D18F2x228_dct0_Tstag1_MASK                              0xff00
+#define D18F2x228_dct0_Tstag2_OFFSET                            16
+#define D18F2x228_dct0_Tstag2_WIDTH                             8
+#define D18F2x228_dct0_Tstag2_MASK                              0xff0000
+#define D18F2x228_dct0_Tstag3_OFFSET                            24
+#define D18F2x228_dct0_Tstag3_WIDTH                             8
+#define D18F2x228_dct0_Tstag3_MASK                              0xff000000
+
+/// D18F2x228_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   Tstag0:8 ; ///<
+    UINT32                                                   Tstag1:8 ; ///<
+    UINT32                                                   Tstag2:8 ; ///<
+    UINT32                                                   Tstag3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x228_dct0_STRUCT;
+
+// **** D18F2x22C_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x22C_dct1_mp1_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x22C_dct1_mp1_Twr_OFFSET                           0
+#define D18F2x22C_dct1_mp1_Twr_WIDTH                            5
+#define D18F2x22C_dct1_mp1_Twr_MASK                             0x1f
+#define D18F2x22C_dct1_mp1_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct1_mp1_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct1_mp1_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct1_mp1_STRUCT;
+
+// **** D18F2x22C_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x22C_dct1_mp0_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x22C_dct1_mp0_Twr_OFFSET                           0
+#define D18F2x22C_dct1_mp0_Twr_WIDTH                            5
+#define D18F2x22C_dct1_mp0_Twr_MASK                             0x1f
+#define D18F2x22C_dct1_mp0_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct1_mp0_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct1_mp0_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct1_mp0_STRUCT;
+
+// **** D18F2x22C_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x22C_dct0_mp0_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x22C_dct0_mp0_Twr_OFFSET                           0
+#define D18F2x22C_dct0_mp0_Twr_WIDTH                            5
+#define D18F2x22C_dct0_mp0_Twr_MASK                             0x1f
+#define D18F2x22C_dct0_mp0_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct0_mp0_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct0_mp0_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct0_mp0_STRUCT;
+
+// **** D18F2x22C_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x22C_dct0_mp1_ADDRESS                              0x22c
+
+// Type
+#define D18F2x22C_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x22C_dct0_mp1_Twr_OFFSET                           0
+#define D18F2x22C_dct0_mp1_Twr_WIDTH                            5
+#define D18F2x22C_dct0_mp1_Twr_MASK                             0x1f
+#define D18F2x22C_dct0_mp1_Reserved_31_5_OFFSET                 5
+#define D18F2x22C_dct0_mp1_Reserved_31_5_WIDTH                  27
+#define D18F2x22C_dct0_mp1_Reserved_31_5_MASK                   0xffffffe0
+
+/// D18F2x22C_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Twr:5 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x22C_dct0_mp1_STRUCT;
+
+// **** D18F2x230_dct0 Register Definition ****
+// Address
+#define D18F2x230_dct0_ADDRESS                                  0x230
+
+// Type
+#define D18F2x230_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x230_dct0_RdOdtPatCs40_OFFSET                      0
+#define D18F2x230_dct0_RdOdtPatCs40_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs40_MASK                        0xf
+#define D18F2x230_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x230_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x230_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x230_dct0_RdOdtPatCs51_OFFSET                      8
+#define D18F2x230_dct0_RdOdtPatCs51_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x230_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x230_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x230_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x230_dct0_RdOdtPatCs62_OFFSET                      16
+#define D18F2x230_dct0_RdOdtPatCs62_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x230_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x230_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x230_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x230_dct0_RdOdtPatCs73_OFFSET                      24
+#define D18F2x230_dct0_RdOdtPatCs73_WIDTH                       4
+#define D18F2x230_dct0_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x230_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x230_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x230_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x230_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x230_dct0_STRUCT;
+
+// **** D18F2x230_dct1 Register Definition ****
+// Address
+#define D18F2x230_dct1_ADDRESS                                  0x230
+
+// Type
+#define D18F2x230_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x230_dct1_RdOdtPatCs40_OFFSET                      0
+#define D18F2x230_dct1_RdOdtPatCs40_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs40_MASK                        0xf
+#define D18F2x230_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x230_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x230_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x230_dct1_RdOdtPatCs51_OFFSET                      8
+#define D18F2x230_dct1_RdOdtPatCs51_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x230_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x230_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x230_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x230_dct1_RdOdtPatCs62_OFFSET                      16
+#define D18F2x230_dct1_RdOdtPatCs62_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x230_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x230_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x230_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x230_dct1_RdOdtPatCs73_OFFSET                      24
+#define D18F2x230_dct1_RdOdtPatCs73_WIDTH                       4
+#define D18F2x230_dct1_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x230_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x230_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x230_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x230_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x230_dct1_STRUCT;
+
+// **** D18F2x234_dct1 Register Definition ****
+// Address
+#define D18F2x234_dct1_ADDRESS                                  0x234
+
+// Type
+#define D18F2x234_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x234_dct1_RdOdtPatCs40_OFFSET                      0
+#define D18F2x234_dct1_RdOdtPatCs40_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs40_MASK                        0xf
+#define D18F2x234_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x234_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x234_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x234_dct1_RdOdtPatCs51_OFFSET                      8
+#define D18F2x234_dct1_RdOdtPatCs51_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x234_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x234_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x234_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x234_dct1_RdOdtPatCs62_OFFSET                      16
+#define D18F2x234_dct1_RdOdtPatCs62_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x234_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x234_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x234_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x234_dct1_RdOdtPatCs73_OFFSET                      24
+#define D18F2x234_dct1_RdOdtPatCs73_WIDTH                       4
+#define D18F2x234_dct1_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x234_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x234_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x234_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x234_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x234_dct1_STRUCT;
+
+// **** D18F2x234_dct0 Register Definition ****
+// Address
+#define D18F2x234_dct0_ADDRESS                                  0x234
+
+// Type
+#define D18F2x234_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x234_dct0_RdOdtPatCs40_OFFSET                      0
+#define D18F2x234_dct0_RdOdtPatCs40_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs40_MASK                        0xf
+#define D18F2x234_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x234_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x234_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x234_dct0_RdOdtPatCs51_OFFSET                      8
+#define D18F2x234_dct0_RdOdtPatCs51_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs51_MASK                        0xf00
+#define D18F2x234_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x234_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x234_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x234_dct0_RdOdtPatCs62_OFFSET                      16
+#define D18F2x234_dct0_RdOdtPatCs62_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs62_MASK                        0xf0000
+#define D18F2x234_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x234_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x234_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x234_dct0_RdOdtPatCs73_OFFSET                      24
+#define D18F2x234_dct0_RdOdtPatCs73_WIDTH                       4
+#define D18F2x234_dct0_RdOdtPatCs73_MASK                        0xf000000
+#define D18F2x234_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x234_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x234_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x234_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             RdOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             RdOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             RdOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             RdOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x234_dct0_STRUCT;
+
+// **** D18F2x238_dct1 Register Definition ****
+// Address
+#define D18F2x238_dct1_ADDRESS                                  0x238
+
+// Type
+#define D18F2x238_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x238_dct1_WrOdtPatCs40_OFFSET                      0
+#define D18F2x238_dct1_WrOdtPatCs40_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs40_MASK                        0xf
+#define D18F2x238_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x238_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x238_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x238_dct1_WrOdtPatCs51_OFFSET                      8
+#define D18F2x238_dct1_WrOdtPatCs51_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x238_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x238_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x238_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x238_dct1_WrOdtPatCs62_OFFSET                      16
+#define D18F2x238_dct1_WrOdtPatCs62_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x238_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x238_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x238_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x238_dct1_WrOdtPatCs73_OFFSET                      24
+#define D18F2x238_dct1_WrOdtPatCs73_WIDTH                       4
+#define D18F2x238_dct1_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x238_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x238_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x238_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x238_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x238_dct1_STRUCT;
+
+// **** D18F2x238_dct0 Register Definition ****
+// Address
+#define D18F2x238_dct0_ADDRESS                                  0x238
+
+// Type
+#define D18F2x238_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x238_dct0_WrOdtPatCs40_OFFSET                      0
+#define D18F2x238_dct0_WrOdtPatCs40_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs40_MASK                        0xf
+#define D18F2x238_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x238_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x238_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x238_dct0_WrOdtPatCs51_OFFSET                      8
+#define D18F2x238_dct0_WrOdtPatCs51_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x238_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x238_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x238_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x238_dct0_WrOdtPatCs62_OFFSET                      16
+#define D18F2x238_dct0_WrOdtPatCs62_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x238_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x238_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x238_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x238_dct0_WrOdtPatCs73_OFFSET                      24
+#define D18F2x238_dct0_WrOdtPatCs73_WIDTH                       4
+#define D18F2x238_dct0_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x238_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x238_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x238_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x238_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x238_dct0_STRUCT;
+
+// **** D18F2x23C_dct0 Register Definition ****
+// Address
+#define D18F2x23C_dct0_ADDRESS                                  0x23c
+
+// Type
+#define D18F2x23C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x23C_dct0_WrOdtPatCs40_OFFSET                      0
+#define D18F2x23C_dct0_WrOdtPatCs40_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs40_MASK                        0xf
+#define D18F2x23C_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x23C_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x23C_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x23C_dct0_WrOdtPatCs51_OFFSET                      8
+#define D18F2x23C_dct0_WrOdtPatCs51_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x23C_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x23C_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x23C_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x23C_dct0_WrOdtPatCs62_OFFSET                      16
+#define D18F2x23C_dct0_WrOdtPatCs62_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x23C_dct0_Reserved_23_20_OFFSET                    20
+#define D18F2x23C_dct0_Reserved_23_20_WIDTH                     4
+#define D18F2x23C_dct0_Reserved_23_20_MASK                      0xf00000
+#define D18F2x23C_dct0_WrOdtPatCs73_OFFSET                      24
+#define D18F2x23C_dct0_WrOdtPatCs73_WIDTH                       4
+#define D18F2x23C_dct0_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x23C_dct0_Reserved_31_28_OFFSET                    28
+#define D18F2x23C_dct0_Reserved_31_28_WIDTH                     4
+#define D18F2x23C_dct0_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x23C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x23C_dct0_STRUCT;
+
+// **** D18F2x23C_dct1 Register Definition ****
+// Address
+#define D18F2x23C_dct1_ADDRESS                                  0x23c
+
+// Type
+#define D18F2x23C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x23C_dct1_WrOdtPatCs40_OFFSET                      0
+#define D18F2x23C_dct1_WrOdtPatCs40_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs40_MASK                        0xf
+#define D18F2x23C_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x23C_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x23C_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x23C_dct1_WrOdtPatCs51_OFFSET                      8
+#define D18F2x23C_dct1_WrOdtPatCs51_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs51_MASK                        0xf00
+#define D18F2x23C_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x23C_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x23C_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x23C_dct1_WrOdtPatCs62_OFFSET                      16
+#define D18F2x23C_dct1_WrOdtPatCs62_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs62_MASK                        0xf0000
+#define D18F2x23C_dct1_Reserved_23_20_OFFSET                    20
+#define D18F2x23C_dct1_Reserved_23_20_WIDTH                     4
+#define D18F2x23C_dct1_Reserved_23_20_MASK                      0xf00000
+#define D18F2x23C_dct1_WrOdtPatCs73_OFFSET                      24
+#define D18F2x23C_dct1_WrOdtPatCs73_WIDTH                       4
+#define D18F2x23C_dct1_WrOdtPatCs73_MASK                        0xf000000
+#define D18F2x23C_dct1_Reserved_31_28_OFFSET                    28
+#define D18F2x23C_dct1_Reserved_31_28_WIDTH                     4
+#define D18F2x23C_dct1_Reserved_31_28_MASK                      0xf0000000
+
+/// D18F2x23C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrOdtPatCs40:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             WrOdtPatCs51:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                             WrOdtPatCs62:4 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             WrOdtPatCs73:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x23C_dct1_STRUCT;
+
+// **** D18F2x240_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x240_dct0_mp1_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct0_mp1_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct0_mp1_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct0_mp1_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp1_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct0_mp1_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct0_mp1_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct0_mp1_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct0_mp1_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct0_mp1_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct0_mp1_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct0_mp1_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct0_mp1_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct0_mp1_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp1_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct0_mp1_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct0_mp1_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct0_mp1_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct0_mp1_STRUCT;
+
+// **** D18F2x240_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x240_dct1_mp0_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct1_mp0_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct1_mp0_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct1_mp0_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp0_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct1_mp0_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct1_mp0_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct1_mp0_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct1_mp0_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct1_mp0_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct1_mp0_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct1_mp0_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct1_mp0_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct1_mp0_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp0_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct1_mp0_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct1_mp0_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct1_mp0_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct1_mp0_STRUCT;
+
+// **** D18F2x240_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x240_dct0_mp0_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct0_mp0_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct0_mp0_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct0_mp0_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp0_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct0_mp0_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct0_mp0_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct0_mp0_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct0_mp0_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct0_mp0_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct0_mp0_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct0_mp0_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct0_mp0_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct0_mp0_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct0_mp0_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct0_mp0_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct0_mp0_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct0_mp0_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct0_mp0_STRUCT;
+
+// **** D18F2x240_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x240_dct1_mp1_ADDRESS                              0x240
+
+// Type
+#define D18F2x240_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_OFFSET                 0
+#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_WIDTH                  4
+#define D18F2x240_dct1_mp1_RdOdtTrnOnDly_MASK                   0xf
+#define D18F2x240_dct1_mp1_RdOdtOnDuration_OFFSET               4
+#define D18F2x240_dct1_mp1_RdOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp1_RdOdtOnDuration_MASK                 0x70
+#define D18F2x240_dct1_mp1_Reserved_7_7_OFFSET                  7
+#define D18F2x240_dct1_mp1_Reserved_7_7_WIDTH                   1
+#define D18F2x240_dct1_mp1_Reserved_7_7_MASK                    0x80
+#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_OFFSET                 8
+#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_WIDTH                  3
+#define D18F2x240_dct1_mp1_WrOdtTrnOnDly_MASK                   0x700
+#define D18F2x240_dct1_mp1_Reserved_11_11_OFFSET                11
+#define D18F2x240_dct1_mp1_Reserved_11_11_WIDTH                 1
+#define D18F2x240_dct1_mp1_Reserved_11_11_MASK                  0x800
+#define D18F2x240_dct1_mp1_WrOdtOnDuration_OFFSET               12
+#define D18F2x240_dct1_mp1_WrOdtOnDuration_WIDTH                3
+#define D18F2x240_dct1_mp1_WrOdtOnDuration_MASK                 0x7000
+#define D18F2x240_dct1_mp1_Reserved_31_15_OFFSET                15
+#define D18F2x240_dct1_mp1_Reserved_31_15_WIDTH                 17
+#define D18F2x240_dct1_mp1_Reserved_31_15_MASK                  0xffff8000
+
+/// D18F2x240_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            RdOdtTrnOnDly:4 ; ///<
+    UINT32                                          RdOdtOnDuration:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                            WrOdtTrnOnDly:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                          WrOdtOnDuration:3 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x240_dct1_mp1_STRUCT;
+
+// **** D18F2x244_dct1 Register Definition ****
+// Address
+#define D18F2x244_dct1_ADDRESS                                  0x244
+
+// Type
+#define D18F2x244_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x244_dct1_PrtlChPDDynDly_OFFSET                    0
+#define D18F2x244_dct1_PrtlChPDDynDly_WIDTH                     4
+#define D18F2x244_dct1_PrtlChPDDynDly_MASK                      0xf
+#define D18F2x244_dct1_Reserved_31_4_OFFSET                     4
+#define D18F2x244_dct1_Reserved_31_4_WIDTH                      28
+#define D18F2x244_dct1_Reserved_31_4_MASK                       0xfffffff0
+
+/// D18F2x244_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PrtlChPDDynDly:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x244_dct1_STRUCT;
+
+// **** D18F2x244_dct0 Register Definition ****
+// Address
+#define D18F2x244_dct0_ADDRESS                                  0x244
+
+// Type
+#define D18F2x244_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x244_dct0_PrtlChPDDynDly_OFFSET                    0
+#define D18F2x244_dct0_PrtlChPDDynDly_WIDTH                     4
+#define D18F2x244_dct0_PrtlChPDDynDly_MASK                      0xf
+#define D18F2x244_dct0_Reserved_31_4_OFFSET                     4
+#define D18F2x244_dct0_Reserved_31_4_WIDTH                      28
+#define D18F2x244_dct0_Reserved_31_4_MASK                       0xfffffff0
+
+/// D18F2x244_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PrtlChPDDynDly:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x244_dct0_STRUCT;
+
+// **** D18F2x248_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x248_dct1_mp1_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x248_dct1_mp1_Txp_OFFSET                           0
+#define D18F2x248_dct1_mp1_Txp_WIDTH                            4
+#define D18F2x248_dct1_mp1_Txp_MASK                             0xf
+#define D18F2x248_dct1_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct1_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct1_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct1_mp1_Txpdll_OFFSET                        8
+#define D18F2x248_dct1_mp1_Txpdll_WIDTH                         5
+#define D18F2x248_dct1_mp1_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct1_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct1_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct1_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct1_mp1_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct1_mp1_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct1_mp1_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct1_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct1_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct1_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct1_mp1_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct1_mp1_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct1_mp1_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct1_mp1_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct1_mp1_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct1_mp1_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct1_mp1_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct1_mp1_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct1_mp1_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct1_mp1_STRUCT;
+
+// **** D18F2x248_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x248_dct0_mp1_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x248_dct0_mp1_Txp_OFFSET                           0
+#define D18F2x248_dct0_mp1_Txp_WIDTH                            4
+#define D18F2x248_dct0_mp1_Txp_MASK                             0xf
+#define D18F2x248_dct0_mp1_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct0_mp1_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct0_mp1_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct0_mp1_Txpdll_OFFSET                        8
+#define D18F2x248_dct0_mp1_Txpdll_WIDTH                         5
+#define D18F2x248_dct0_mp1_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct0_mp1_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct0_mp1_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct0_mp1_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct0_mp1_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct0_mp1_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct0_mp1_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct0_mp1_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct0_mp1_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct0_mp1_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct0_mp1_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct0_mp1_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct0_mp1_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct0_mp1_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct0_mp1_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct0_mp1_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct0_mp1_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct0_mp1_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct0_mp1_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct0_mp1_STRUCT;
+
+// **** D18F2x248_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x248_dct1_mp0_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x248_dct1_mp0_Txp_OFFSET                           0
+#define D18F2x248_dct1_mp0_Txp_WIDTH                            4
+#define D18F2x248_dct1_mp0_Txp_MASK                             0xf
+#define D18F2x248_dct1_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct1_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct1_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct1_mp0_Txpdll_OFFSET                        8
+#define D18F2x248_dct1_mp0_Txpdll_WIDTH                         5
+#define D18F2x248_dct1_mp0_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct1_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct1_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct1_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct1_mp0_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct1_mp0_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct1_mp0_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct1_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct1_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct1_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct1_mp0_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct1_mp0_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct1_mp0_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct1_mp0_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct1_mp0_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct1_mp0_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct1_mp0_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct1_mp0_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct1_mp0_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct1_mp0_STRUCT;
+
+// **** D18F2x248_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x248_dct0_mp0_ADDRESS                              0x248
+
+// Type
+#define D18F2x248_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x248_dct0_mp0_Txp_OFFSET                           0
+#define D18F2x248_dct0_mp0_Txp_WIDTH                            4
+#define D18F2x248_dct0_mp0_Txp_MASK                             0xf
+#define D18F2x248_dct0_mp0_Reserved_7_4_OFFSET                  4
+#define D18F2x248_dct0_mp0_Reserved_7_4_WIDTH                   4
+#define D18F2x248_dct0_mp0_Reserved_7_4_MASK                    0xf0
+#define D18F2x248_dct0_mp0_Txpdll_OFFSET                        8
+#define D18F2x248_dct0_mp0_Txpdll_WIDTH                         5
+#define D18F2x248_dct0_mp0_Txpdll_MASK                          0x1f00
+#define D18F2x248_dct0_mp0_Reserved_15_13_OFFSET                13
+#define D18F2x248_dct0_mp0_Reserved_15_13_WIDTH                 3
+#define D18F2x248_dct0_mp0_Reserved_15_13_MASK                  0xe000
+#define D18F2x248_dct0_mp0_PchgPDEnDelay_OFFSET                 16
+#define D18F2x248_dct0_mp0_PchgPDEnDelay_WIDTH                  6
+#define D18F2x248_dct0_mp0_PchgPDEnDelay_MASK                   0x3f0000
+#define D18F2x248_dct0_mp0_Reserved_23_22_OFFSET                22
+#define D18F2x248_dct0_mp0_Reserved_23_22_WIDTH                 2
+#define D18F2x248_dct0_mp0_Reserved_23_22_MASK                  0xc00000
+#define D18F2x248_dct0_mp0_AggrPDDelay_OFFSET                   24
+#define D18F2x248_dct0_mp0_AggrPDDelay_WIDTH                    6
+#define D18F2x248_dct0_mp0_AggrPDDelay_MASK                     0x3f000000
+#define D18F2x248_dct0_mp0_Reserved_30_30_OFFSET                30
+#define D18F2x248_dct0_mp0_Reserved_30_30_WIDTH                 1
+#define D18F2x248_dct0_mp0_Reserved_30_30_MASK                  0x40000000
+#define D18F2x248_dct0_mp0_RxChMntClkEn_OFFSET                  31
+#define D18F2x248_dct0_mp0_RxChMntClkEn_WIDTH                   1
+#define D18F2x248_dct0_mp0_RxChMntClkEn_MASK                    0x80000000
+
+/// D18F2x248_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Txp:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Txpdll:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            PchgPDEnDelay:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              AggrPDDelay:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             RxChMntClkEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x248_dct0_mp0_STRUCT;
+
+// **** D18F2x24C_dct0 Register Definition ****
+// Address
+#define D18F2x24C_dct0_ADDRESS                                  0x24c
+
+// Type
+#define D18F2x24C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x24C_dct0_Tpd_OFFSET                               0
+#define D18F2x24C_dct0_Tpd_WIDTH                                4
+#define D18F2x24C_dct0_Tpd_MASK                                 0xf
+#define D18F2x24C_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x24C_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x24C_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x24C_dct0_Tckesr_OFFSET                            8
+#define D18F2x24C_dct0_Tckesr_WIDTH                             6
+#define D18F2x24C_dct0_Tckesr_MASK                              0x3f00
+#define D18F2x24C_dct0_Reserved_15_14_OFFSET                    14
+#define D18F2x24C_dct0_Reserved_15_14_WIDTH                     2
+#define D18F2x24C_dct0_Reserved_15_14_MASK                      0xc000
+#define D18F2x24C_dct0_Tcksre_OFFSET                            16
+#define D18F2x24C_dct0_Tcksre_WIDTH                             6
+#define D18F2x24C_dct0_Tcksre_MASK                              0x3f0000
+#define D18F2x24C_dct0_Reserved_23_22_OFFSET                    22
+#define D18F2x24C_dct0_Reserved_23_22_WIDTH                     2
+#define D18F2x24C_dct0_Reserved_23_22_MASK                      0xc00000
+#define D18F2x24C_dct0_Tcksrx_OFFSET                            24
+#define D18F2x24C_dct0_Tcksrx_WIDTH                             6
+#define D18F2x24C_dct0_Tcksrx_MASK                              0x3f000000
+#define D18F2x24C_dct0_Reserved_31_30_OFFSET                    30
+#define D18F2x24C_dct0_Reserved_31_30_WIDTH                     2
+#define D18F2x24C_dct0_Reserved_31_30_MASK                      0xc0000000
+
+/// D18F2x24C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tpd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Tckesr:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                                   Tcksre:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                   Tcksrx:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x24C_dct0_STRUCT;
+
+// **** D18F2x24C_dct1 Register Definition ****
+// Address
+#define D18F2x24C_dct1_ADDRESS                                  0x24c
+
+// Type
+#define D18F2x24C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x24C_dct1_Tpd_OFFSET                               0
+#define D18F2x24C_dct1_Tpd_WIDTH                                4
+#define D18F2x24C_dct1_Tpd_MASK                                 0xf
+#define D18F2x24C_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x24C_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x24C_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x24C_dct1_Tckesr_OFFSET                            8
+#define D18F2x24C_dct1_Tckesr_WIDTH                             6
+#define D18F2x24C_dct1_Tckesr_MASK                              0x3f00
+#define D18F2x24C_dct1_Reserved_15_14_OFFSET                    14
+#define D18F2x24C_dct1_Reserved_15_14_WIDTH                     2
+#define D18F2x24C_dct1_Reserved_15_14_MASK                      0xc000
+#define D18F2x24C_dct1_Tcksre_OFFSET                            16
+#define D18F2x24C_dct1_Tcksre_WIDTH                             6
+#define D18F2x24C_dct1_Tcksre_MASK                              0x3f0000
+#define D18F2x24C_dct1_Reserved_23_22_OFFSET                    22
+#define D18F2x24C_dct1_Reserved_23_22_WIDTH                     2
+#define D18F2x24C_dct1_Reserved_23_22_MASK                      0xc00000
+#define D18F2x24C_dct1_Tcksrx_OFFSET                            24
+#define D18F2x24C_dct1_Tcksrx_WIDTH                             6
+#define D18F2x24C_dct1_Tcksrx_MASK                              0x3f000000
+#define D18F2x24C_dct1_Reserved_31_30_OFFSET                    30
+#define D18F2x24C_dct1_Reserved_31_30_WIDTH                     2
+#define D18F2x24C_dct1_Reserved_31_30_MASK                      0xc0000000
+
+/// D18F2x24C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Tpd:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                   Tckesr:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                                   Tcksre:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                   Tcksrx:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x24C_dct1_STRUCT;
+
+// **** D18F2x250_dct0 Register Definition ****
+// Address
+#define D18F2x250_dct0_ADDRESS                                  0x250
+
+// Type
+#define D18F2x250_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x250_dct0_Reserved_1_0_OFFSET                      0
+#define D18F2x250_dct0_Reserved_1_0_WIDTH                       2
+#define D18F2x250_dct0_Reserved_1_0_MASK                        0x3
+#define D18F2x250_dct0_CmdTestEnable_OFFSET                     2
+#define D18F2x250_dct0_CmdTestEnable_WIDTH                      1
+#define D18F2x250_dct0_CmdTestEnable_MASK                       0x4
+#define D18F2x250_dct0_ResetAllErr_OFFSET                       3
+#define D18F2x250_dct0_ResetAllErr_WIDTH                        1
+#define D18F2x250_dct0_ResetAllErr_MASK                         0x8
+#define D18F2x250_dct0_StopOnErr_OFFSET                         4
+#define D18F2x250_dct0_StopOnErr_WIDTH                          1
+#define D18F2x250_dct0_StopOnErr_MASK                           0x10
+#define D18F2x250_dct0_CmdType_OFFSET                           5
+#define D18F2x250_dct0_CmdType_WIDTH                            3
+#define D18F2x250_dct0_CmdType_MASK                             0xe0
+#define D18F2x250_dct0_CmdTgt_OFFSET                            8
+#define D18F2x250_dct0_CmdTgt_WIDTH                             2
+#define D18F2x250_dct0_CmdTgt_MASK                              0x300
+#define D18F2x250_dct0_TestStatus_OFFSET                        10
+#define D18F2x250_dct0_TestStatus_WIDTH                         1
+#define D18F2x250_dct0_TestStatus_MASK                          0x400
+#define D18F2x250_dct0_SendCmd_OFFSET                           11
+#define D18F2x250_dct0_SendCmd_WIDTH                            1
+#define D18F2x250_dct0_SendCmd_MASK                             0x800
+#define D18F2x250_dct0_CmdSendInProg_OFFSET                     12
+#define D18F2x250_dct0_CmdSendInProg_WIDTH                      1
+#define D18F2x250_dct0_CmdSendInProg_MASK                       0x1000
+#define D18F2x250_dct0_Reserved_31_13_OFFSET                    13
+#define D18F2x250_dct0_Reserved_31_13_WIDTH                     19
+#define D18F2x250_dct0_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x250_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CmdTestEnable:1 ; ///<
+    UINT32                                              ResetAllErr:1 ; ///<
+    UINT32                                                StopOnErr:1 ; ///<
+    UINT32                                                  CmdType:3 ; ///<
+    UINT32                                                   CmdTgt:2 ; ///<
+    UINT32                                               TestStatus:1 ; ///<
+    UINT32                                                  SendCmd:1 ; ///<
+    UINT32                                            CmdSendInProg:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x250_dct0_STRUCT;
+
+// **** D18F2x250_dct1 Register Definition ****
+// Address
+#define D18F2x250_dct1_ADDRESS                                  0x250
+
+// Type
+#define D18F2x250_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x250_dct1_Reserved_1_0_OFFSET                      0
+#define D18F2x250_dct1_Reserved_1_0_WIDTH                       2
+#define D18F2x250_dct1_Reserved_1_0_MASK                        0x3
+#define D18F2x250_dct1_CmdTestEnable_OFFSET                     2
+#define D18F2x250_dct1_CmdTestEnable_WIDTH                      1
+#define D18F2x250_dct1_CmdTestEnable_MASK                       0x4
+#define D18F2x250_dct1_ResetAllErr_OFFSET                       3
+#define D18F2x250_dct1_ResetAllErr_WIDTH                        1
+#define D18F2x250_dct1_ResetAllErr_MASK                         0x8
+#define D18F2x250_dct1_StopOnErr_OFFSET                         4
+#define D18F2x250_dct1_StopOnErr_WIDTH                          1
+#define D18F2x250_dct1_StopOnErr_MASK                           0x10
+#define D18F2x250_dct1_CmdType_OFFSET                           5
+#define D18F2x250_dct1_CmdType_WIDTH                            3
+#define D18F2x250_dct1_CmdType_MASK                             0xe0
+#define D18F2x250_dct1_CmdTgt_OFFSET                            8
+#define D18F2x250_dct1_CmdTgt_WIDTH                             2
+#define D18F2x250_dct1_CmdTgt_MASK                              0x300
+#define D18F2x250_dct1_TestStatus_OFFSET                        10
+#define D18F2x250_dct1_TestStatus_WIDTH                         1
+#define D18F2x250_dct1_TestStatus_MASK                          0x400
+#define D18F2x250_dct1_SendCmd_OFFSET                           11
+#define D18F2x250_dct1_SendCmd_WIDTH                            1
+#define D18F2x250_dct1_SendCmd_MASK                             0x800
+#define D18F2x250_dct1_CmdSendInProg_OFFSET                     12
+#define D18F2x250_dct1_CmdSendInProg_WIDTH                      1
+#define D18F2x250_dct1_CmdSendInProg_MASK                       0x1000
+#define D18F2x250_dct1_Reserved_31_13_OFFSET                    13
+#define D18F2x250_dct1_Reserved_31_13_WIDTH                     19
+#define D18F2x250_dct1_Reserved_31_13_MASK                      0xffffe000
+
+/// D18F2x250_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            CmdTestEnable:1 ; ///<
+    UINT32                                              ResetAllErr:1 ; ///<
+    UINT32                                                StopOnErr:1 ; ///<
+    UINT32                                                  CmdType:3 ; ///<
+    UINT32                                                   CmdTgt:2 ; ///<
+    UINT32                                               TestStatus:1 ; ///<
+    UINT32                                                  SendCmd:1 ; ///<
+    UINT32                                            CmdSendInProg:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x250_dct1_STRUCT;
+
+// **** D18F2x254_dct0 Register Definition ****
+// Address
+#define D18F2x254_dct0_ADDRESS                                  0x254
+
+// Type
+#define D18F2x254_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x254_dct0_TgtAddress_9_0__OFFSET                   0
+#define D18F2x254_dct0_TgtAddress_9_0__WIDTH                    10
+#define D18F2x254_dct0_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x254_dct0_Reserved_20_10_OFFSET                    10
+#define D18F2x254_dct0_Reserved_20_10_WIDTH                     11
+#define D18F2x254_dct0_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x254_dct0_TgtBank_OFFSET                           21
+#define D18F2x254_dct0_TgtBank_WIDTH                            3
+#define D18F2x254_dct0_TgtBank_MASK                             0xe00000
+#define D18F2x254_dct0_TgtChipSelect_OFFSET                     24
+#define D18F2x254_dct0_TgtChipSelect_WIDTH                      3
+#define D18F2x254_dct0_TgtChipSelect_MASK                       0x7000000
+#define D18F2x254_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x254_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x254_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x254_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x254_dct0_STRUCT;
+
+// **** D18F2x254_dct1 Register Definition ****
+// Address
+#define D18F2x254_dct1_ADDRESS                                  0x254
+
+// Type
+#define D18F2x254_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x254_dct1_TgtAddress_9_0__OFFSET                   0
+#define D18F2x254_dct1_TgtAddress_9_0__WIDTH                    10
+#define D18F2x254_dct1_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x254_dct1_Reserved_20_10_OFFSET                    10
+#define D18F2x254_dct1_Reserved_20_10_WIDTH                     11
+#define D18F2x254_dct1_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x254_dct1_TgtBank_OFFSET                           21
+#define D18F2x254_dct1_TgtBank_WIDTH                            3
+#define D18F2x254_dct1_TgtBank_MASK                             0xe00000
+#define D18F2x254_dct1_TgtChipSelect_OFFSET                     24
+#define D18F2x254_dct1_TgtChipSelect_WIDTH                      3
+#define D18F2x254_dct1_TgtChipSelect_MASK                       0x7000000
+#define D18F2x254_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x254_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x254_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x254_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x254_dct1_STRUCT;
+
+// **** D18F2x258_dct0 Register Definition ****
+// Address
+#define D18F2x258_dct0_ADDRESS                                  0x258
+
+// Type
+#define D18F2x258_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x258_dct0_TgtAddress_9_0__OFFSET                   0
+#define D18F2x258_dct0_TgtAddress_9_0__WIDTH                    10
+#define D18F2x258_dct0_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x258_dct0_Reserved_20_10_OFFSET                    10
+#define D18F2x258_dct0_Reserved_20_10_WIDTH                     11
+#define D18F2x258_dct0_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x258_dct0_TgtBank_OFFSET                           21
+#define D18F2x258_dct0_TgtBank_WIDTH                            3
+#define D18F2x258_dct0_TgtBank_MASK                             0xe00000
+#define D18F2x258_dct0_TgtChipSelect_OFFSET                     24
+#define D18F2x258_dct0_TgtChipSelect_WIDTH                      3
+#define D18F2x258_dct0_TgtChipSelect_MASK                       0x7000000
+#define D18F2x258_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x258_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x258_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x258_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x258_dct0_STRUCT;
+
+// **** D18F2x258_dct1 Register Definition ****
+// Address
+#define D18F2x258_dct1_ADDRESS                                  0x258
+
+// Type
+#define D18F2x258_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x258_dct1_TgtAddress_9_0__OFFSET                   0
+#define D18F2x258_dct1_TgtAddress_9_0__WIDTH                    10
+#define D18F2x258_dct1_TgtAddress_9_0__MASK                     0x3ff
+#define D18F2x258_dct1_Reserved_20_10_OFFSET                    10
+#define D18F2x258_dct1_Reserved_20_10_WIDTH                     11
+#define D18F2x258_dct1_Reserved_20_10_MASK                      0x1ffc00
+#define D18F2x258_dct1_TgtBank_OFFSET                           21
+#define D18F2x258_dct1_TgtBank_WIDTH                            3
+#define D18F2x258_dct1_TgtBank_MASK                             0xe00000
+#define D18F2x258_dct1_TgtChipSelect_OFFSET                     24
+#define D18F2x258_dct1_TgtChipSelect_WIDTH                      3
+#define D18F2x258_dct1_TgtChipSelect_MASK                       0x7000000
+#define D18F2x258_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x258_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x258_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x258_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TgtAddress_9_0_:10; ///<
+    UINT32                                           Reserved_20_10:11; ///<
+    UINT32                                                  TgtBank:3 ; ///<
+    UINT32                                            TgtChipSelect:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x258_dct1_STRUCT;
+
+
+// **** D18F2x260_dct1 Register Definition ****
+// Address
+#define D18F2x260_dct1_ADDRESS                                  0x260
+
+// Type
+#define D18F2x260_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x260_dct1_CmdCount_OFFSET                          0
+#define D18F2x260_dct1_CmdCount_WIDTH                           21
+#define D18F2x260_dct1_CmdCount_MASK                            0x1fffff
+#define D18F2x260_dct1_Reserved_31_21_OFFSET                    21
+#define D18F2x260_dct1_Reserved_31_21_WIDTH                     11
+#define D18F2x260_dct1_Reserved_31_21_MASK                      0xffe00000
+
+/// D18F2x260_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CmdCount:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x260_dct1_STRUCT;
+
+// **** D18F2x260_dct0 Register Definition ****
+// Address
+#define D18F2x260_dct0_ADDRESS                                  0x260
+
+// Type
+#define D18F2x260_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x260_dct0_CmdCount_OFFSET                          0
+#define D18F2x260_dct0_CmdCount_WIDTH                           21
+#define D18F2x260_dct0_CmdCount_MASK                            0x1fffff
+#define D18F2x260_dct0_Reserved_31_21_OFFSET                    21
+#define D18F2x260_dct0_Reserved_31_21_WIDTH                     11
+#define D18F2x260_dct0_Reserved_31_21_MASK                      0xffe00000
+
+/// D18F2x260_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CmdCount:21; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x260_dct0_STRUCT;
+
+// **** D18F2x264_dct1 Register Definition ****
+// Address
+#define D18F2x264_dct1_ADDRESS                                  0x264
+
+// Type
+#define D18F2x264_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x264_dct1_ErrCnt_OFFSET                            0
+#define D18F2x264_dct1_ErrCnt_WIDTH                             25
+#define D18F2x264_dct1_ErrCnt_MASK                              0x1ffffff
+#define D18F2x264_dct1_ErrDqNum_OFFSET                          25
+#define D18F2x264_dct1_ErrDqNum_WIDTH                           7
+#define D18F2x264_dct1_ErrDqNum_MASK                            0xfe000000
+
+/// D18F2x264_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   ErrCnt:25; ///<
+    UINT32                                                 ErrDqNum:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x264_dct1_STRUCT;
+
+// **** D18F2x264_dct0 Register Definition ****
+// Address
+#define D18F2x264_dct0_ADDRESS                                  0x264
+
+// Type
+#define D18F2x264_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x264_dct0_ErrCnt_OFFSET                            0
+#define D18F2x264_dct0_ErrCnt_WIDTH                             25
+#define D18F2x264_dct0_ErrCnt_MASK                              0x1ffffff
+#define D18F2x264_dct0_ErrDqNum_OFFSET                          25
+#define D18F2x264_dct0_ErrDqNum_WIDTH                           7
+#define D18F2x264_dct0_ErrDqNum_MASK                            0xfe000000
+
+/// D18F2x264_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   ErrCnt:25; ///<
+    UINT32                                                 ErrDqNum:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x264_dct0_STRUCT;
+
+// **** D18F2x268_dct1 Register Definition ****
+// Address
+#define D18F2x268_dct1_ADDRESS                                  0x268
+
+// Type
+#define D18F2x268_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x268_dct1_NibbleErrSts_OFFSET                      0
+#define D18F2x268_dct1_NibbleErrSts_WIDTH                       18
+#define D18F2x268_dct1_NibbleErrSts_MASK                        0x3ffff
+#define D18F2x268_dct1_Reserved_31_18_OFFSET                    18
+#define D18F2x268_dct1_Reserved_31_18_WIDTH                     14
+#define D18F2x268_dct1_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x268_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NibbleErrSts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x268_dct1_STRUCT;
+
+// **** D18F2x268_dct0 Register Definition ****
+// Address
+#define D18F2x268_dct0_ADDRESS                                  0x268
+
+// Type
+#define D18F2x268_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x268_dct0_NibbleErrSts_OFFSET                      0
+#define D18F2x268_dct0_NibbleErrSts_WIDTH                       18
+#define D18F2x268_dct0_NibbleErrSts_MASK                        0x3ffff
+#define D18F2x268_dct0_Reserved_31_18_OFFSET                    18
+#define D18F2x268_dct0_Reserved_31_18_WIDTH                     14
+#define D18F2x268_dct0_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x268_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NibbleErrSts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x268_dct0_STRUCT;
+
+// **** D18F2x26C_dct1 Register Definition ****
+// Address
+#define D18F2x26C_dct1_ADDRESS                                  0x26c
+
+// Type
+#define D18F2x26C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x26C_dct1_NibbleErr180Sts_OFFSET                   0
+#define D18F2x26C_dct1_NibbleErr180Sts_WIDTH                    18
+#define D18F2x26C_dct1_NibbleErr180Sts_MASK                     0x3ffff
+#define D18F2x26C_dct1_Reserved_31_18_OFFSET                    18
+#define D18F2x26C_dct1_Reserved_31_18_WIDTH                     14
+#define D18F2x26C_dct1_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x26C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          NibbleErr180Sts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x26C_dct1_STRUCT;
+
+// **** D18F2x26C_dct0 Register Definition ****
+// Address
+#define D18F2x26C_dct0_ADDRESS                                  0x26c
+
+// Type
+#define D18F2x26C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x26C_dct0_NibbleErr180Sts_OFFSET                   0
+#define D18F2x26C_dct0_NibbleErr180Sts_WIDTH                    18
+#define D18F2x26C_dct0_NibbleErr180Sts_MASK                     0x3ffff
+#define D18F2x26C_dct0_Reserved_31_18_OFFSET                    18
+#define D18F2x26C_dct0_Reserved_31_18_WIDTH                     14
+#define D18F2x26C_dct0_Reserved_31_18_MASK                      0xfffc0000
+
+/// D18F2x26C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          NibbleErr180Sts:18; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x26C_dct0_STRUCT;
+
+// **** D18F2x270_dct0 Register Definition ****
+// Address
+#define D18F2x270_dct0_ADDRESS                                  0x270
+
+// Type
+#define D18F2x270_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x270_dct0_DataPrbsSeed_OFFSET                      0
+#define D18F2x270_dct0_DataPrbsSeed_WIDTH                       19
+#define D18F2x270_dct0_DataPrbsSeed_MASK                        0x7ffff
+#define D18F2x270_dct0_Reserved_23_19_OFFSET                    19
+#define D18F2x270_dct0_Reserved_23_19_WIDTH                     5
+#define D18F2x270_dct0_Reserved_23_19_MASK                      0xf80000
+#define D18F2x270_dct0_Reserved_30_24_OFFSET                    24
+#define D18F2x270_dct0_Reserved_30_24_WIDTH                     7
+#define D18F2x270_dct0_Reserved_30_24_MASK                      0x7f000000
+#define D18F2x270_dct0_Reserved_31_31_OFFSET                    31
+#define D18F2x270_dct0_Reserved_31_31_WIDTH                     1
+#define D18F2x270_dct0_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x270_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DataPrbsSeed:19; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                           Reserved_30_24:7 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x270_dct0_STRUCT;
+
+// **** D18F2x270_dct1 Register Definition ****
+// Address
+#define D18F2x270_dct1_ADDRESS                                  0x270
+
+// Type
+#define D18F2x270_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x270_dct1_DataPrbsSeed_OFFSET                      0
+#define D18F2x270_dct1_DataPrbsSeed_WIDTH                       19
+#define D18F2x270_dct1_DataPrbsSeed_MASK                        0x7ffff
+#define D18F2x270_dct1_Reserved_23_19_OFFSET                    19
+#define D18F2x270_dct1_Reserved_23_19_WIDTH                     5
+#define D18F2x270_dct1_Reserved_23_19_MASK                      0xf80000
+#define D18F2x270_dct1_Reserved_30_24_OFFSET                    24
+#define D18F2x270_dct1_Reserved_30_24_WIDTH                     7
+#define D18F2x270_dct1_Reserved_30_24_MASK                      0x7f000000
+#define D18F2x270_dct1_Reserved_31_31_OFFSET                    31
+#define D18F2x270_dct1_Reserved_31_31_WIDTH                     1
+#define D18F2x270_dct1_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x270_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DataPrbsSeed:19; ///<
+    UINT32                                           Reserved_23_19:5 ; ///<
+    UINT32                                           Reserved_30_24:7 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x270_dct1_STRUCT;
+
+// **** D18F2x274_dct0 Register Definition ****
+// Address
+#define D18F2x274_dct0_ADDRESS                                  0x274
+
+// Type
+#define D18F2x274_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x274_dct0_DQMask_31_0__OFFSET                      0
+#define D18F2x274_dct0_DQMask_31_0__WIDTH                       32
+#define D18F2x274_dct0_DQMask_31_0__MASK                        0xffffffff
+
+/// D18F2x274_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQMask_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x274_dct0_STRUCT;
+
+// **** D18F2x274_dct1 Register Definition ****
+// Address
+#define D18F2x274_dct1_ADDRESS                                  0x274
+
+// Type
+#define D18F2x274_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x274_dct1_DQMask_31_0__OFFSET                      0
+#define D18F2x274_dct1_DQMask_31_0__WIDTH                       32
+#define D18F2x274_dct1_DQMask_31_0__MASK                        0xffffffff
+
+/// D18F2x274_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQMask_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x274_dct1_STRUCT;
+
+// **** D18F2x278_dct0 Register Definition ****
+// Address
+#define D18F2x278_dct0_ADDRESS                                  0x278
+
+// Type
+#define D18F2x278_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x278_dct0_DQMask_63_32__OFFSET                     0
+#define D18F2x278_dct0_DQMask_63_32__WIDTH                      32
+#define D18F2x278_dct0_DQMask_63_32__MASK                       0xffffffff
+
+/// D18F2x278_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DQMask_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x278_dct0_STRUCT;
+
+// **** D18F2x278_dct1 Register Definition ****
+// Address
+#define D18F2x278_dct1_ADDRESS                                  0x278
+
+// Type
+#define D18F2x278_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x278_dct1_DQMask_63_32__OFFSET                     0
+#define D18F2x278_dct1_DQMask_63_32__WIDTH                      32
+#define D18F2x278_dct1_DQMask_63_32__MASK                       0xffffffff
+
+/// D18F2x278_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DQMask_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x278_dct1_STRUCT;
+
+// **** D18F2x28C_dct0 Register Definition ****
+// Address
+#define D18F2x28C_dct0_ADDRESS                                  0x28c
+
+// Type
+#define D18F2x28C_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x28C_dct0_CmdAddress_17_0__OFFSET                  0
+#define D18F2x28C_dct0_CmdAddress_17_0__WIDTH                   18
+#define D18F2x28C_dct0_CmdAddress_17_0__MASK                    0x3ffff
+#define D18F2x28C_dct0_Reserved_18_18_OFFSET                    18
+#define D18F2x28C_dct0_Reserved_18_18_WIDTH                     1
+#define D18F2x28C_dct0_Reserved_18_18_MASK                      0x40000
+#define D18F2x28C_dct0_CmdBank_2_0__OFFSET                      19
+#define D18F2x28C_dct0_CmdBank_2_0__WIDTH                       3
+#define D18F2x28C_dct0_CmdBank_2_0__MASK                        0x380000
+#define D18F2x28C_dct0_CmdChipSelect_OFFSET                     22
+#define D18F2x28C_dct0_CmdChipSelect_WIDTH                      8
+#define D18F2x28C_dct0_CmdChipSelect_MASK                       0x3fc00000
+#define D18F2x28C_dct0_SendPchgCmd_OFFSET                       30
+#define D18F2x28C_dct0_SendPchgCmd_WIDTH                        1
+#define D18F2x28C_dct0_SendPchgCmd_MASK                         0x40000000
+#define D18F2x28C_dct0_SendActCmd_OFFSET                        31
+#define D18F2x28C_dct0_SendActCmd_WIDTH                         1
+#define D18F2x28C_dct0_SendActCmd_MASK                          0x80000000
+
+/// D18F2x28C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CmdAddress_17_0_:18; ///<
+    UINT32                                           Reserved_18_18:1 ; ///<
+    UINT32                                             CmdBank_2_0_:3 ; ///<
+    UINT32                                            CmdChipSelect:8 ; ///<
+    UINT32                                              SendPchgCmd:1 ; ///<
+    UINT32                                               SendActCmd:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x28C_dct0_STRUCT;
+
+// **** D18F2x28C_dct1 Register Definition ****
+// Address
+#define D18F2x28C_dct1_ADDRESS                                  0x28c
+
+// Type
+#define D18F2x28C_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x28C_dct1_CmdAddress_17_0__OFFSET                  0
+#define D18F2x28C_dct1_CmdAddress_17_0__WIDTH                   18
+#define D18F2x28C_dct1_CmdAddress_17_0__MASK                    0x3ffff
+#define D18F2x28C_dct1_Reserved_18_18_OFFSET                    18
+#define D18F2x28C_dct1_Reserved_18_18_WIDTH                     1
+#define D18F2x28C_dct1_Reserved_18_18_MASK                      0x40000
+#define D18F2x28C_dct1_CmdBank_2_0__OFFSET                      19
+#define D18F2x28C_dct1_CmdBank_2_0__WIDTH                       3
+#define D18F2x28C_dct1_CmdBank_2_0__MASK                        0x380000
+#define D18F2x28C_dct1_CmdChipSelect_OFFSET                     22
+#define D18F2x28C_dct1_CmdChipSelect_WIDTH                      8
+#define D18F2x28C_dct1_CmdChipSelect_MASK                       0x3fc00000
+#define D18F2x28C_dct1_SendPchgCmd_OFFSET                       30
+#define D18F2x28C_dct1_SendPchgCmd_WIDTH                        1
+#define D18F2x28C_dct1_SendPchgCmd_MASK                         0x40000000
+#define D18F2x28C_dct1_SendActCmd_OFFSET                        31
+#define D18F2x28C_dct1_SendActCmd_WIDTH                         1
+#define D18F2x28C_dct1_SendActCmd_MASK                          0x80000000
+
+/// D18F2x28C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CmdAddress_17_0_:18; ///<
+    UINT32                                           Reserved_18_18:1 ; ///<
+    UINT32                                             CmdBank_2_0_:3 ; ///<
+    UINT32                                            CmdChipSelect:8 ; ///<
+    UINT32                                              SendPchgCmd:1 ; ///<
+    UINT32                                               SendActCmd:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x28C_dct1_STRUCT;
+
+// **** D18F2x290_dct1 Register Definition ****
+// Address
+#define D18F2x290_dct1_ADDRESS                                  0x290
+
+// Type
+#define D18F2x290_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x290_dct1_ErrCmdNum_OFFSET                         0
+#define D18F2x290_dct1_ErrCmdNum_WIDTH                          21
+#define D18F2x290_dct1_ErrCmdNum_MASK                           0x1fffff
+#define D18F2x290_dct1_Reserved_23_21_OFFSET                    21
+#define D18F2x290_dct1_Reserved_23_21_WIDTH                     3
+#define D18F2x290_dct1_Reserved_23_21_MASK                      0xe00000
+#define D18F2x290_dct1_ErrBeatNum_OFFSET                        24
+#define D18F2x290_dct1_ErrBeatNum_WIDTH                         3
+#define D18F2x290_dct1_ErrBeatNum_MASK                          0x7000000
+#define D18F2x290_dct1_Reserved_31_27_OFFSET                    27
+#define D18F2x290_dct1_Reserved_31_27_WIDTH                     5
+#define D18F2x290_dct1_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x290_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrCmdNum:21; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                               ErrBeatNum:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x290_dct1_STRUCT;
+
+// **** D18F2x290_dct0 Register Definition ****
+// Address
+#define D18F2x290_dct0_ADDRESS                                  0x290
+
+// Type
+#define D18F2x290_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x290_dct0_ErrCmdNum_OFFSET                         0
+#define D18F2x290_dct0_ErrCmdNum_WIDTH                          21
+#define D18F2x290_dct0_ErrCmdNum_MASK                           0x1fffff
+#define D18F2x290_dct0_Reserved_23_21_OFFSET                    21
+#define D18F2x290_dct0_Reserved_23_21_WIDTH                     3
+#define D18F2x290_dct0_Reserved_23_21_MASK                      0xe00000
+#define D18F2x290_dct0_ErrBeatNum_OFFSET                        24
+#define D18F2x290_dct0_ErrBeatNum_WIDTH                         3
+#define D18F2x290_dct0_ErrBeatNum_MASK                          0x7000000
+#define D18F2x290_dct0_Reserved_31_27_OFFSET                    27
+#define D18F2x290_dct0_Reserved_31_27_WIDTH                     5
+#define D18F2x290_dct0_Reserved_31_27_MASK                      0xf8000000
+
+/// D18F2x290_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrCmdNum:21; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                               ErrBeatNum:3 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x290_dct0_STRUCT;
+
+// **** D18F2x294_dct1 Register Definition ****
+// Address
+#define D18F2x294_dct1_ADDRESS                                  0x294
+
+// Type
+#define D18F2x294_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x294_dct1_DQErr_31_0__OFFSET                       0
+#define D18F2x294_dct1_DQErr_31_0__WIDTH                        32
+#define D18F2x294_dct1_DQErr_31_0__MASK                         0xffffffff
+
+/// D18F2x294_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DQErr_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x294_dct1_STRUCT;
+
+// **** D18F2x294_dct0 Register Definition ****
+// Address
+#define D18F2x294_dct0_ADDRESS                                  0x294
+
+// Type
+#define D18F2x294_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x294_dct0_DQErr_31_0__OFFSET                       0
+#define D18F2x294_dct0_DQErr_31_0__WIDTH                        32
+#define D18F2x294_dct0_DQErr_31_0__MASK                         0xffffffff
+
+/// D18F2x294_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DQErr_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x294_dct0_STRUCT;
+
+// **** D18F2x298_dct0 Register Definition ****
+// Address
+#define D18F2x298_dct0_ADDRESS                                  0x298
+
+// Type
+#define D18F2x298_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x298_dct0_DQErr_63_32__OFFSET                      0
+#define D18F2x298_dct0_DQErr_63_32__WIDTH                       32
+#define D18F2x298_dct0_DQErr_63_32__MASK                        0xffffffff
+
+/// D18F2x298_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQErr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x298_dct0_STRUCT;
+
+// **** D18F2x298_dct1 Register Definition ****
+// Address
+#define D18F2x298_dct1_ADDRESS                                  0x298
+
+// Type
+#define D18F2x298_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x298_dct1_DQErr_63_32__OFFSET                      0
+#define D18F2x298_dct1_DQErr_63_32__WIDTH                       32
+#define D18F2x298_dct1_DQErr_63_32__MASK                        0xffffffff
+
+/// D18F2x298_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DQErr_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x298_dct1_STRUCT;
+
+// **** D18F2x2E0_dct1 Register Definition ****
+// Address
+#define D18F2x2E0_dct1_ADDRESS                                  0x2e0
+
+// Type
+#define D18F2x2E0_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x2E0_dct1_CurMemPstate_OFFSET                      0
+#define D18F2x2E0_dct1_CurMemPstate_WIDTH                       1
+#define D18F2x2E0_dct1_CurMemPstate_MASK                        0x1
+#define D18F2x2E0_dct1_Reserved_19_1_OFFSET                     1
+#define D18F2x2E0_dct1_Reserved_19_1_WIDTH                      19
+#define D18F2x2E0_dct1_Reserved_19_1_MASK                       0xffffe
+#define D18F2x2E0_dct1_MxMrsEn_OFFSET                           20
+#define D18F2x2E0_dct1_MxMrsEn_WIDTH                            3
+#define D18F2x2E0_dct1_MxMrsEn_MASK                             0x700000
+#define D18F2x2E0_dct1_Reserved_23_23_OFFSET                    23
+#define D18F2x2E0_dct1_Reserved_23_23_WIDTH                     1
+#define D18F2x2E0_dct1_Reserved_23_23_MASK                      0x800000
+#define D18F2x2E0_dct1_M1MemClkFreq_OFFSET                      24
+#define D18F2x2E0_dct1_M1MemClkFreq_WIDTH                       5
+#define D18F2x2E0_dct1_M1MemClkFreq_MASK                        0x1f000000
+#define D18F2x2E0_dct1_Reserved_29_29_OFFSET                    29
+#define D18F2x2E0_dct1_Reserved_29_29_WIDTH                     1
+#define D18F2x2E0_dct1_Reserved_29_29_MASK                      0x20000000
+#define D18F2x2E0_dct1_FastMstateDis_OFFSET                     30
+#define D18F2x2E0_dct1_FastMstateDis_WIDTH                      1
+#define D18F2x2E0_dct1_FastMstateDis_MASK                       0x40000000
+#define D18F2x2E0_dct1_Reserved_31_31_OFFSET                    31
+#define D18F2x2E0_dct1_Reserved_31_31_WIDTH                     1
+#define D18F2x2E0_dct1_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x2E0_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CurMemPstate:1 ; ///<
+    UINT32                                            Reserved_19_1:19; ///<
+    UINT32                                                  MxMrsEn:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                             M1MemClkFreq:5 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                            FastMstateDis:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E0_dct1_STRUCT;
+
+// **** D18F2x2E0_dct0 Register Definition ****
+// Address
+#define D18F2x2E0_dct0_ADDRESS                                  0x2e0
+
+// Type
+#define D18F2x2E0_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x2E0_dct0_CurMemPstate_OFFSET                      0
+#define D18F2x2E0_dct0_CurMemPstate_WIDTH                       1
+#define D18F2x2E0_dct0_CurMemPstate_MASK                        0x1
+#define D18F2x2E0_dct0_Reserved_19_1_OFFSET                     1
+#define D18F2x2E0_dct0_Reserved_19_1_WIDTH                      19
+#define D18F2x2E0_dct0_Reserved_19_1_MASK                       0xffffe
+#define D18F2x2E0_dct0_MxMrsEn_OFFSET                           20
+#define D18F2x2E0_dct0_MxMrsEn_WIDTH                            3
+#define D18F2x2E0_dct0_MxMrsEn_MASK                             0x700000
+#define D18F2x2E0_dct0_Reserved_23_23_OFFSET                    23
+#define D18F2x2E0_dct0_Reserved_23_23_WIDTH                     1
+#define D18F2x2E0_dct0_Reserved_23_23_MASK                      0x800000
+#define D18F2x2E0_dct0_M1MemClkFreq_OFFSET                      24
+#define D18F2x2E0_dct0_M1MemClkFreq_WIDTH                       5
+#define D18F2x2E0_dct0_M1MemClkFreq_MASK                        0x1f000000
+#define D18F2x2E0_dct0_Reserved_29_29_OFFSET                    29
+#define D18F2x2E0_dct0_Reserved_29_29_WIDTH                     1
+#define D18F2x2E0_dct0_Reserved_29_29_MASK                      0x20000000
+#define D18F2x2E0_dct0_FastMstateDis_OFFSET                     30
+#define D18F2x2E0_dct0_FastMstateDis_WIDTH                      1
+#define D18F2x2E0_dct0_FastMstateDis_MASK                       0x40000000
+#define D18F2x2E0_dct0_Reserved_31_31_OFFSET                    31
+#define D18F2x2E0_dct0_Reserved_31_31_WIDTH                     1
+#define D18F2x2E0_dct0_Reserved_31_31_MASK                      0x80000000
+
+/// D18F2x2E0_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CurMemPstate:1 ; ///<
+    UINT32                                            Reserved_19_1:19; ///<
+    UINT32                                                  MxMrsEn:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                             M1MemClkFreq:5 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                            FastMstateDis:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E0_dct0_STRUCT;
+
+// **** D18F2x2E8_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x2E8_dct0_mp1_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x2E8_dct0_mp1_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct0_mp1_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct0_mp1_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct0_mp1_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct0_mp1_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct0_mp1_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct0_mp1_STRUCT;
+
+// **** D18F2x2E8_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x2E8_dct1_mp1_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x2E8_dct1_mp1_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct1_mp1_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct1_mp1_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct1_mp1_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct1_mp1_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct1_mp1_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct1_mp1_STRUCT;
+
+// **** D18F2x2E8_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x2E8_dct1_mp0_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x2E8_dct1_mp0_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct1_mp0_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct1_mp0_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct1_mp0_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct1_mp0_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct1_mp0_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct1_mp0_STRUCT;
+
+// **** D18F2x2E8_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x2E8_dct0_mp0_ADDRESS                              0x2e8
+
+// Type
+#define D18F2x2E8_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x2E8_dct0_mp0_MxMr0_OFFSET                         0
+#define D18F2x2E8_dct0_mp0_MxMr0_WIDTH                          16
+#define D18F2x2E8_dct0_mp0_MxMr0_MASK                           0xffff
+#define D18F2x2E8_dct0_mp0_MxMr1_OFFSET                         16
+#define D18F2x2E8_dct0_mp0_MxMr1_WIDTH                          16
+#define D18F2x2E8_dct0_mp0_MxMr1_MASK                           0xffff0000
+
+/// D18F2x2E8_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr0:16; ///<
+    UINT32                                                    MxMr1:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2E8_dct0_mp0_STRUCT;
+
+// **** D18F2x2EC_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x2EC_dct0_mp0_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x2EC_dct0_mp0_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct0_mp0_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct0_mp0_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct0_mp0_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct0_mp0_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct0_mp0_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct0_mp0_STRUCT;
+
+// **** D18F2x2EC_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x2EC_dct0_mp1_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x2EC_dct0_mp1_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct0_mp1_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct0_mp1_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct0_mp1_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct0_mp1_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct0_mp1_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct0_mp1_STRUCT;
+
+// **** D18F2x2EC_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x2EC_dct1_mp1_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x2EC_dct1_mp1_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct1_mp1_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct1_mp1_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct1_mp1_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct1_mp1_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct1_mp1_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct1_mp1_STRUCT;
+
+// **** D18F2x2EC_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x2EC_dct1_mp0_ADDRESS                              0x2ec
+
+// Type
+#define D18F2x2EC_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x2EC_dct1_mp0_MxMr2_OFFSET                         0
+#define D18F2x2EC_dct1_mp0_MxMr2_WIDTH                          16
+#define D18F2x2EC_dct1_mp0_MxMr2_MASK                           0xffff
+#define D18F2x2EC_dct1_mp0_Reserved_31_16_OFFSET                16
+#define D18F2x2EC_dct1_mp0_Reserved_31_16_WIDTH                 16
+#define D18F2x2EC_dct1_mp0_Reserved_31_16_MASK                  0xffff0000
+
+/// D18F2x2EC_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    MxMr2:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2EC_dct1_mp0_STRUCT;
+
+// **** D18F2x2F0_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x2F0_dct1_mp1_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct1_mp1_TYPE                                 TYPE_D18F2_dct1_mp1
+// Field Data
+#define D18F2x2F0_dct1_mp1_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct1_mp1_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct1_mp1_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct1_mp1_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct1_mp1_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct1_mp1_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct1_mp1_STRUCT;
+
+// **** D18F2x2F0_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x2F0_dct0_mp1_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct0_mp1_TYPE                                 TYPE_D18F2_dct0_mp1
+// Field Data
+#define D18F2x2F0_dct0_mp1_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct0_mp1_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct0_mp1_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct0_mp1_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct0_mp1_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct0_mp1_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct0_mp1_STRUCT;
+
+// **** D18F2x2F0_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x2F0_dct1_mp0_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct1_mp0_TYPE                                 TYPE_D18F2_dct1_mp0
+// Field Data
+#define D18F2x2F0_dct1_mp0_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct1_mp0_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct1_mp0_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct1_mp0_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct1_mp0_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct1_mp0_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct1_mp0_STRUCT;
+
+// **** D18F2x2F0_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x2F0_dct0_mp0_ADDRESS                              0x2f0
+
+// Type
+#define D18F2x2F0_dct0_mp0_TYPE                                 TYPE_D18F2_dct0_mp0
+// Field Data
+#define D18F2x2F0_dct0_mp0_EffArbDis_OFFSET                     0
+#define D18F2x2F0_dct0_mp0_EffArbDis_WIDTH                      1
+#define D18F2x2F0_dct0_mp0_EffArbDis_MASK                       0x1
+#define D18F2x2F0_dct0_mp0_Reserved_31_1_OFFSET                 1
+#define D18F2x2F0_dct0_mp0_Reserved_31_1_WIDTH                  31
+#define D18F2x2F0_dct0_mp0_Reserved_31_1_MASK                   0xfffffffe
+
+/// D18F2x2F0_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                EffArbDis:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x2F0_dct0_mp0_STRUCT;
+
+// **** D18F2x400_dct1 Register Definition ****
+// Address
+#define D18F2x400_dct1_ADDRESS                                  0x400
+
+// Type
+#define D18F2x400_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x400_dct1_MctTokenLimit_OFFSET                     0
+#define D18F2x400_dct1_MctTokenLimit_WIDTH                      4
+#define D18F2x400_dct1_MctTokenLimit_MASK                       0xf
+#define D18F2x400_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x400_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x400_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x400_dct1_GmcTokenLimit_OFFSET                     8
+#define D18F2x400_dct1_GmcTokenLimit_WIDTH                      4
+#define D18F2x400_dct1_GmcTokenLimit_MASK                       0xf00
+#define D18F2x400_dct1_Reserved_15_12_OFFSET                    12
+#define D18F2x400_dct1_Reserved_15_12_WIDTH                     4
+#define D18F2x400_dct1_Reserved_15_12_MASK                      0xf000
+#define D18F2x400_dct1_Reserved_31_16_OFFSET                    16
+#define D18F2x400_dct1_Reserved_31_16_WIDTH                     16
+#define D18F2x400_dct1_Reserved_31_16_MASK                      0xffff0000
+
+/// D18F2x400_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            MctTokenLimit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                            GmcTokenLimit:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x400_dct1_STRUCT;
+
+// **** D18F2x400_dct0 Register Definition ****
+// Address
+#define D18F2x400_dct0_ADDRESS                                  0x400
+
+// Type
+#define D18F2x400_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x400_dct0_MctTokenLimit_OFFSET                     0
+#define D18F2x400_dct0_MctTokenLimit_WIDTH                      4
+#define D18F2x400_dct0_MctTokenLimit_MASK                       0xf
+#define D18F2x400_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x400_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x400_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x400_dct0_GmcTokenLimit_OFFSET                     8
+#define D18F2x400_dct0_GmcTokenLimit_WIDTH                      4
+#define D18F2x400_dct0_GmcTokenLimit_MASK                       0xf00
+#define D18F2x400_dct0_Reserved_15_12_OFFSET                    12
+#define D18F2x400_dct0_Reserved_15_12_WIDTH                     4
+#define D18F2x400_dct0_Reserved_15_12_MASK                      0xf000
+#define D18F2x400_dct0_Reserved_31_16_OFFSET                    16
+#define D18F2x400_dct0_Reserved_31_16_WIDTH                     16
+#define D18F2x400_dct0_Reserved_31_16_MASK                      0xffff0000
+
+/// D18F2x400_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            MctTokenLimit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                            GmcTokenLimit:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x400_dct0_STRUCT;
+
+// **** D18F2x404_dct0 Register Definition ****
+// Address
+#define D18F2x404_dct0_ADDRESS                                  0x404
+
+// Type
+#define D18F2x404_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x404_dct0_UrMctTokenLimit_OFFSET                   0
+#define D18F2x404_dct0_UrMctTokenLimit_WIDTH                    4
+#define D18F2x404_dct0_UrMctTokenLimit_MASK                     0xf
+#define D18F2x404_dct0_UrMctMinTokens_OFFSET                    4
+#define D18F2x404_dct0_UrMctMinTokens_WIDTH                     4
+#define D18F2x404_dct0_UrMctMinTokens_MASK                      0xf0
+#define D18F2x404_dct0_UrGmcTokenLimit_OFFSET                   8
+#define D18F2x404_dct0_UrGmcTokenLimit_WIDTH                    4
+#define D18F2x404_dct0_UrGmcTokenLimit_MASK                     0xf00
+#define D18F2x404_dct0_UrGmcMinTokens_OFFSET                    12
+#define D18F2x404_dct0_UrGmcMinTokens_WIDTH                     4
+#define D18F2x404_dct0_UrGmcMinTokens_MASK                      0xf000
+#define D18F2x404_dct0_UrgentTknDis_OFFSET                      16
+#define D18F2x404_dct0_UrgentTknDis_WIDTH                       1
+#define D18F2x404_dct0_UrgentTknDis_MASK                        0x10000
+#define D18F2x404_dct0_Reserved_31_17_OFFSET                    17
+#define D18F2x404_dct0_Reserved_31_17_WIDTH                     15
+#define D18F2x404_dct0_Reserved_31_17_MASK                      0xfffe0000
+
+/// D18F2x404_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          UrMctTokenLimit:4 ; ///<
+    UINT32                                           UrMctMinTokens:4 ; ///<
+    UINT32                                          UrGmcTokenLimit:4 ; ///<
+    UINT32                                           UrGmcMinTokens:4 ; ///<
+    UINT32                                             UrgentTknDis:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x404_dct0_STRUCT;
+
+// **** D18F2x404_dct1 Register Definition ****
+// Address
+#define D18F2x404_dct1_ADDRESS                                  0x404
+
+// Type
+#define D18F2x404_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x404_dct1_UrMctTokenLimit_OFFSET                   0
+#define D18F2x404_dct1_UrMctTokenLimit_WIDTH                    4
+#define D18F2x404_dct1_UrMctTokenLimit_MASK                     0xf
+#define D18F2x404_dct1_UrMctMinTokens_OFFSET                    4
+#define D18F2x404_dct1_UrMctMinTokens_WIDTH                     4
+#define D18F2x404_dct1_UrMctMinTokens_MASK                      0xf0
+#define D18F2x404_dct1_UrGmcTokenLimit_OFFSET                   8
+#define D18F2x404_dct1_UrGmcTokenLimit_WIDTH                    4
+#define D18F2x404_dct1_UrGmcTokenLimit_MASK                     0xf00
+#define D18F2x404_dct1_UrGmcMinTokens_OFFSET                    12
+#define D18F2x404_dct1_UrGmcMinTokens_WIDTH                     4
+#define D18F2x404_dct1_UrGmcMinTokens_MASK                      0xf000
+#define D18F2x404_dct1_UrgentTknDis_OFFSET                      16
+#define D18F2x404_dct1_UrgentTknDis_WIDTH                       1
+#define D18F2x404_dct1_UrgentTknDis_MASK                        0x10000
+#define D18F2x404_dct1_Reserved_31_17_OFFSET                    17
+#define D18F2x404_dct1_Reserved_31_17_WIDTH                     15
+#define D18F2x404_dct1_Reserved_31_17_MASK                      0xfffe0000
+
+/// D18F2x404_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          UrMctTokenLimit:4 ; ///<
+    UINT32                                           UrMctMinTokens:4 ; ///<
+    UINT32                                          UrGmcTokenLimit:4 ; ///<
+    UINT32                                           UrGmcMinTokens:4 ; ///<
+    UINT32                                             UrgentTknDis:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x404_dct1_STRUCT;
+
+// **** D18F2x408_dct1 Register Definition ****
+// Address
+#define D18F2x408_dct1_ADDRESS                                  0x408
+
+// Type
+#define D18F2x408_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x408_dct1_CpuElevPrioDis_OFFSET                    0
+#define D18F2x408_dct1_CpuElevPrioDis_WIDTH                     1
+#define D18F2x408_dct1_CpuElevPrioDis_MASK                      0x1
+#define D18F2x408_dct1_TokenAllocSelect_OFFSET                  1
+#define D18F2x408_dct1_TokenAllocSelect_WIDTH                   1
+#define D18F2x408_dct1_TokenAllocSelect_MASK                    0x2
+#define D18F2x408_dct1_Reserved_30_2_OFFSET                     2
+#define D18F2x408_dct1_Reserved_30_2_WIDTH                      29
+#define D18F2x408_dct1_Reserved_30_2_MASK                       0x7ffffffc
+#define D18F2x408_dct1_DisHalfNclkPwrGate_OFFSET                31
+#define D18F2x408_dct1_DisHalfNclkPwrGate_WIDTH                 1
+#define D18F2x408_dct1_DisHalfNclkPwrGate_MASK                  0x80000000
+
+/// D18F2x408_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CpuElevPrioDis:1 ; ///<
+    UINT32                                         TokenAllocSelect:1 ; ///<
+    UINT32                                            Reserved_30_2:29; ///<
+    UINT32                                       DisHalfNclkPwrGate:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x408_dct1_STRUCT;
+
+// **** D18F2x408_dct0 Register Definition ****
+// Address
+#define D18F2x408_dct0_ADDRESS                                  0x408
+
+// Type
+#define D18F2x408_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x408_dct0_CpuElevPrioDis_OFFSET                    0
+#define D18F2x408_dct0_CpuElevPrioDis_WIDTH                     1
+#define D18F2x408_dct0_CpuElevPrioDis_MASK                      0x1
+#define D18F2x408_dct0_TokenAllocSelect_OFFSET                  1
+#define D18F2x408_dct0_TokenAllocSelect_WIDTH                   1
+#define D18F2x408_dct0_TokenAllocSelect_MASK                    0x2
+#define D18F2x408_dct0_Reserved_30_2_OFFSET                     2
+#define D18F2x408_dct0_Reserved_30_2_WIDTH                      29
+#define D18F2x408_dct0_Reserved_30_2_MASK                       0x7ffffffc
+#define D18F2x408_dct0_DisHalfNclkPwrGate_OFFSET                31
+#define D18F2x408_dct0_DisHalfNclkPwrGate_WIDTH                 1
+#define D18F2x408_dct0_DisHalfNclkPwrGate_MASK                  0x80000000
+
+/// D18F2x408_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CpuElevPrioDis:1 ; ///<
+    UINT32                                         TokenAllocSelect:1 ; ///<
+    UINT32                                            Reserved_30_2:29; ///<
+    UINT32                                       DisHalfNclkPwrGate:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x408_dct0_STRUCT;
+
+// **** D18F2x420_dct0 Register Definition ****
+// Address
+#define D18F2x420_dct0_ADDRESS                                  0x420
+
+// Type
+#define D18F2x420_dct0_TYPE                                     TYPE_D18F2_dct0
+// Field Data
+#define D18F2x420_dct0_CmdRdPtrInit_OFFSET                      0
+#define D18F2x420_dct0_CmdRdPtrInit_WIDTH                       4
+#define D18F2x420_dct0_CmdRdPtrInit_MASK                        0xf
+#define D18F2x420_dct0_Reserved_7_4_OFFSET                      4
+#define D18F2x420_dct0_Reserved_7_4_WIDTH                       4
+#define D18F2x420_dct0_Reserved_7_4_MASK                        0xf0
+#define D18F2x420_dct0_SbRdPtrInit_OFFSET                       8
+#define D18F2x420_dct0_SbRdPtrInit_WIDTH                        4
+#define D18F2x420_dct0_SbRdPtrInit_MASK                         0xf00
+#define D18F2x420_dct0_Reserved_31_12_OFFSET                    12
+#define D18F2x420_dct0_Reserved_31_12_WIDTH                     20
+#define D18F2x420_dct0_Reserved_31_12_MASK                      0xfffff000
+
+/// D18F2x420_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CmdRdPtrInit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                              SbRdPtrInit:4 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x420_dct0_STRUCT;
+
+// **** D18F2x420_dct1 Register Definition ****
+// Address
+#define D18F2x420_dct1_ADDRESS                                  0x420
+
+// Type
+#define D18F2x420_dct1_TYPE                                     TYPE_D18F2_dct1
+// Field Data
+#define D18F2x420_dct1_CmdRdPtrInit_OFFSET                      0
+#define D18F2x420_dct1_CmdRdPtrInit_WIDTH                       4
+#define D18F2x420_dct1_CmdRdPtrInit_MASK                        0xf
+#define D18F2x420_dct1_Reserved_7_4_OFFSET                      4
+#define D18F2x420_dct1_Reserved_7_4_WIDTH                       4
+#define D18F2x420_dct1_Reserved_7_4_MASK                        0xf0
+#define D18F2x420_dct1_SbRdPtrInit_OFFSET                       8
+#define D18F2x420_dct1_SbRdPtrInit_WIDTH                        4
+#define D18F2x420_dct1_SbRdPtrInit_MASK                         0xf00
+#define D18F2x420_dct1_Reserved_31_12_OFFSET                    12
+#define D18F2x420_dct1_Reserved_31_12_WIDTH                     20
+#define D18F2x420_dct1_Reserved_31_12_MASK                      0xfffff000
+
+/// D18F2x420_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CmdRdPtrInit:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                              SbRdPtrInit:4 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x420_dct1_STRUCT;
+
+// **** D18F3x00 Register Definition ****
+// Address
+#define D18F3x00_ADDRESS                                        0x0
+
+// Type
+#define D18F3x00_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x00_VendorID_OFFSET                                0
+#define D18F3x00_VendorID_WIDTH                                 16
+#define D18F3x00_VendorID_MASK                                  0xffff
+#define D18F3x00_DeviceID_OFFSET                                16
+#define D18F3x00_DeviceID_WIDTH                                 16
+#define D18F3x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F3x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x00_STRUCT;
+
+// **** D18F3x04 Register Definition ****
+// Address
+#define D18F3x04_ADDRESS                                        0x4
+
+// Type
+#define D18F3x04_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x04_Command_OFFSET                                 0
+#define D18F3x04_Command_WIDTH                                  16
+#define D18F3x04_Command_MASK                                   0xffff
+#define D18F3x04_Status_OFFSET                                  16
+#define D18F3x04_Status_WIDTH                                   16
+#define D18F3x04_Status_MASK                                    0xffff0000
+
+/// D18F3x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x04_STRUCT;
+
+// **** D18F3x08 Register Definition ****
+// Address
+#define D18F3x08_ADDRESS                                        0x8
+
+// Type
+#define D18F3x08_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x08_RevID_OFFSET                                   0
+#define D18F3x08_RevID_WIDTH                                    8
+#define D18F3x08_RevID_MASK                                     0xff
+#define D18F3x08_ClassCode_OFFSET                               8
+#define D18F3x08_ClassCode_WIDTH                                24
+#define D18F3x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F3x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x08_STRUCT;
+
+// **** D18F3x0C Register Definition ****
+// Address
+#define D18F3x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F3x0C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x0C_HeaderTypeReg_OFFSET                           0
+#define D18F3x0C_HeaderTypeReg_WIDTH                            32
+#define D18F3x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F3x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x0C_STRUCT;
+
+// **** D18F3x34 Register Definition ****
+// Address
+#define D18F3x34_ADDRESS                                        0x34
+
+// Type
+#define D18F3x34_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x34_CapPtr_OFFSET                                  0
+#define D18F3x34_CapPtr_WIDTH                                   8
+#define D18F3x34_CapPtr_MASK                                    0xff
+#define D18F3x34_Reserved_31_8_OFFSET                           8
+#define D18F3x34_Reserved_31_8_WIDTH                            24
+#define D18F3x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F3x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x34_STRUCT;
+
+// **** D18F3x40 Register Definition ****
+// Address
+#define D18F3x40_ADDRESS                                        0x40
+
+// Type
+#define D18F3x40_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x40_Unused_4_0_OFFSET                              0
+#define D18F3x40_Unused_4_0_WIDTH                               5
+#define D18F3x40_Unused_4_0_MASK                                0x1f
+#define D18F3x40_SyncPktEn_OFFSET                               5
+#define D18F3x40_SyncPktEn_WIDTH                                1
+#define D18F3x40_SyncPktEn_MASK                                 0x20
+#define D18F3x40_Unused_7_6_OFFSET                              6
+#define D18F3x40_Unused_7_6_WIDTH                               2
+#define D18F3x40_Unused_7_6_MASK                                0xc0
+#define D18F3x40_MstrAbortEn_OFFSET                             8
+#define D18F3x40_MstrAbortEn_WIDTH                              1
+#define D18F3x40_MstrAbortEn_MASK                               0x100
+#define D18F3x40_TgtAbortEn_OFFSET                              9
+#define D18F3x40_TgtAbortEn_WIDTH                               1
+#define D18F3x40_TgtAbortEn_MASK                                0x200
+#define D18F3x40_Unused_10_10_OFFSET                            10
+#define D18F3x40_Unused_10_10_WIDTH                             1
+#define D18F3x40_Unused_10_10_MASK                              0x400
+#define D18F3x40_AtomicRMWEn_OFFSET                             11
+#define D18F3x40_AtomicRMWEn_WIDTH                              1
+#define D18F3x40_AtomicRMWEn_MASK                               0x800
+#define D18F3x40_WDTRptEn_OFFSET                                12
+#define D18F3x40_WDTRptEn_WIDTH                                 1
+#define D18F3x40_WDTRptEn_MASK                                  0x1000
+#define D18F3x40_Unused_15_13_OFFSET                            13
+#define D18F3x40_Unused_15_13_WIDTH                             3
+#define D18F3x40_Unused_15_13_MASK                              0xe000
+#define D18F3x40_NbIntProtEn_OFFSET                             16
+#define D18F3x40_NbIntProtEn_WIDTH                              1
+#define D18F3x40_NbIntProtEn_MASK                               0x10000
+#define D18F3x40_CpPktDatEn_OFFSET                              17
+#define D18F3x40_CpPktDatEn_WIDTH                               1
+#define D18F3x40_CpPktDatEn_MASK                                0x20000
+#define D18F3x40_Unused_24_18_OFFSET                            18
+#define D18F3x40_Unused_24_18_WIDTH                             7
+#define D18F3x40_Unused_24_18_MASK                              0x1fc0000
+#define D18F3x40_UsPwDatErrEn_OFFSET                            25
+#define D18F3x40_UsPwDatErrEn_WIDTH                             1
+#define D18F3x40_UsPwDatErrEn_MASK                              0x2000000
+#define D18F3x40_NbArrayParEn_OFFSET                            26
+#define D18F3x40_NbArrayParEn_WIDTH                             1
+#define D18F3x40_NbArrayParEn_MASK                              0x4000000
+#define D18F3x40_Unused_29_27_OFFSET                            27
+#define D18F3x40_Unused_29_27_WIDTH                             3
+#define D18F3x40_Unused_29_27_MASK                              0x38000000
+#define D18F3x40_Unused_30_30_OFFSET                            30
+#define D18F3x40_Unused_30_30_WIDTH                             1
+#define D18F3x40_Unused_30_30_MASK                              0x40000000
+#define D18F3x40_McaCpuDatErrEn_OFFSET                          31
+#define D18F3x40_McaCpuDatErrEn_WIDTH                           1
+#define D18F3x40_McaCpuDatErrEn_MASK                            0x80000000
+
+/// D18F3x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               Unused_4_0:5 ; ///<
+    UINT32                                                SyncPktEn:1 ; ///<
+    UINT32                                               Unused_7_6:2 ; ///<
+    UINT32                                              MstrAbortEn:1 ; ///<
+    UINT32                                               TgtAbortEn:1 ; ///<
+    UINT32                                             Unused_10_10:1 ; ///<
+    UINT32                                              AtomicRMWEn:1 ; ///<
+    UINT32                                                 WDTRptEn:1 ; ///<
+    UINT32                                             Unused_15_13:3 ; ///<
+    UINT32                                              NbIntProtEn:1 ; ///<
+    UINT32                                               CpPktDatEn:1 ; ///<
+    UINT32                                             Unused_24_18:7 ; ///<
+    UINT32                                             UsPwDatErrEn:1 ; ///<
+    UINT32                                             NbArrayParEn:1 ; ///<
+    UINT32                                             Unused_29_27:3 ; ///<
+    UINT32                                             Unused_30_30:1 ; ///<
+    UINT32                                           McaCpuDatErrEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x40_STRUCT;
+
+// **** D18F3x44 Register Definition ****
+// Address
+#define D18F3x44_ADDRESS                                        0x44
+
+// Type
+#define D18F3x44_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x44_Reserved_0_0_OFFSET                            0
+#define D18F3x44_Reserved_0_0_WIDTH                             1
+#define D18F3x44_Reserved_0_0_MASK                              0x1
+#define D18F3x44_CpuRdDatErrEn_OFFSET                           1
+#define D18F3x44_CpuRdDatErrEn_WIDTH                            1
+#define D18F3x44_CpuRdDatErrEn_MASK                             0x2
+#define D18F3x44_SyncPktGenDis_OFFSET                           3
+#define D18F3x44_SyncPktGenDis_WIDTH                            1
+#define D18F3x44_SyncPktGenDis_MASK                             0x8
+#define D18F3x44_SyncPktPropDis_OFFSET                          4
+#define D18F3x44_SyncPktPropDis_WIDTH                           1
+#define D18F3x44_SyncPktPropDis_MASK                            0x10
+#define D18F3x44_IoMstAbortDis_OFFSET                           5
+#define D18F3x44_IoMstAbortDis_WIDTH                            1
+#define D18F3x44_IoMstAbortDis_MASK                             0x20
+#define D18F3x44_CpuErrDis_OFFSET                               6
+#define D18F3x44_CpuErrDis_WIDTH                                1
+#define D18F3x44_CpuErrDis_MASK                                 0x40
+#define D18F3x44_IoErrDis_OFFSET                                7
+#define D18F3x44_IoErrDis_WIDTH                                 1
+#define D18F3x44_IoErrDis_MASK                                  0x80
+#define D18F3x44_WDTDis_OFFSET                                  8
+#define D18F3x44_WDTDis_WIDTH                                   1
+#define D18F3x44_WDTDis_MASK                                    0x100
+#define D18F3x44_WDTCntSel_2_0__OFFSET                          9
+#define D18F3x44_WDTCntSel_2_0__WIDTH                           3
+#define D18F3x44_WDTCntSel_2_0__MASK                            0xe00
+#define D18F3x44_WDTBaseSel_OFFSET                              12
+#define D18F3x44_WDTBaseSel_WIDTH                               2
+#define D18F3x44_WDTBaseSel_MASK                                0x3000
+#define D18F3x44_GenCrcErrByte0_OFFSET                          16
+#define D18F3x44_GenCrcErrByte0_WIDTH                           1
+#define D18F3x44_GenCrcErrByte0_MASK                            0x10000
+#define D18F3x44_GenCrcErrByte1_OFFSET                          17
+#define D18F3x44_GenCrcErrByte1_WIDTH                           1
+#define D18F3x44_GenCrcErrByte1_MASK                            0x20000
+#define D18F3x44_GenSubLinkSel_OFFSET                           18
+#define D18F3x44_GenSubLinkSel_WIDTH                            2
+#define D18F3x44_GenSubLinkSel_MASK                             0xc0000
+#define D18F3x44_Reserved_23_22_WIDTH                           2
+#define D18F3x44_Reserved_23_22_MASK                            0xc00000
+#define D18F3x44_IoRdDatErrEn_OFFSET                            24
+#define D18F3x44_IoRdDatErrEn_WIDTH                             1
+#define D18F3x44_IoRdDatErrEn_MASK                              0x1000000
+#define D18F3x44_DisPciCfgCpuErrRsp_OFFSET                      25
+#define D18F3x44_DisPciCfgCpuErrRsp_WIDTH                       1
+#define D18F3x44_DisPciCfgCpuErrRsp_MASK                        0x2000000
+#define D18F3x44_FlagMcaCorrErr_OFFSET                          26
+#define D18F3x44_FlagMcaCorrErr_WIDTH                           1
+#define D18F3x44_FlagMcaCorrErr_MASK                            0x4000000
+#define D18F3x44_NbMcaToMstCpuEn_OFFSET                         27
+#define D18F3x44_NbMcaToMstCpuEn_WIDTH                          1
+#define D18F3x44_NbMcaToMstCpuEn_MASK                           0x8000000
+#define D18F3x44_DisTgtAbortCpuErrRsp_OFFSET                    28
+#define D18F3x44_DisTgtAbortCpuErrRsp_WIDTH                     1
+#define D18F3x44_DisTgtAbortCpuErrRsp_MASK                      0x10000000
+#define D18F3x44_DisMstAbortCpuErrRsp_OFFSET                    29
+#define D18F3x44_DisMstAbortCpuErrRsp_WIDTH                     1
+#define D18F3x44_DisMstAbortCpuErrRsp_MASK                      0x20000000
+#define D18F3x44_SyncOnDramAdrParErrEn_OFFSET                   30
+#define D18F3x44_SyncOnDramAdrParErrEn_WIDTH                    1
+#define D18F3x44_SyncOnDramAdrParErrEn_MASK                     0x40000000
+#define D18F3x44_NbMcaLogEn_OFFSET                              31
+#define D18F3x44_NbMcaLogEn_WIDTH                               1
+#define D18F3x44_NbMcaLogEn_MASK                                0x80000000
+
+/// D18F3x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                            CpuRdDatErrEn:1 ; ///<
+    UINT32                                            SyncOnUcEccEn:1 ; ///<
+    UINT32                                            SyncPktGenDis:1 ; ///<
+    UINT32                                           SyncPktPropDis:1 ; ///<
+    UINT32                                            IoMstAbortDis:1 ; ///<
+    UINT32                                                CpuErrDis:1 ; ///<
+    UINT32                                                 IoErrDis:1 ; ///<
+    UINT32                                                   WDTDis:1 ; ///<
+    UINT32                                           WDTCntSel_2_0_:3 ; ///<
+    UINT32                                               WDTBaseSel:2 ; ///<
+    UINT32                                               :2 ; ///<
+    UINT32                                           GenCrcErrByte0:1 ; ///<
+    UINT32                                           GenCrcErrByte1:1 ; ///<
+    UINT32                                            GenSubLinkSel:2 ; ///<
+    UINT32                                              :1 ; ///<
+    UINT32                                           :1 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                             IoRdDatErrEn:1 ; ///<
+    UINT32                                       DisPciCfgCpuErrRsp:1 ; ///<
+    UINT32                                           FlagMcaCorrErr:1 ; ///<
+    UINT32                                          NbMcaToMstCpuEn:1 ; ///<
+    UINT32                                     DisTgtAbortCpuErrRsp:1 ; ///<
+    UINT32                                     DisMstAbortCpuErrRsp:1 ; ///<
+    UINT32                                    SyncOnDramAdrParErrEn:1 ; ///<
+    UINT32                                               NbMcaLogEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x44_STRUCT;
+
+// **** D18F3x48 Register Definition ****
+// Address
+#define D18F3x48_ADDRESS                                        0x48
+
+// Type
+#define D18F3x48_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x48_ErrorCode_OFFSET                               0
+#define D18F3x48_ErrorCode_WIDTH                                16
+#define D18F3x48_ErrorCode_MASK                                 0xffff
+#define D18F3x48_ErrorCodeExt_OFFSET                            16
+#define D18F3x48_ErrorCodeExt_WIDTH                             5
+#define D18F3x48_ErrorCodeExt_MASK                              0x1f0000
+#define D18F3x48_Reserved_23_21_OFFSET                          21
+#define D18F3x48_Reserved_23_21_WIDTH                           3
+#define D18F3x48_Reserved_23_21_MASK                            0xe00000
+#define D18F3x48_Reserved_31_24_OFFSET                          24
+#define D18F3x48_Reserved_31_24_WIDTH                           8
+#define D18F3x48_Reserved_31_24_MASK                            0xff000000
+
+/// D18F3x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrorCode:16; ///<
+    UINT32                                             ErrorCodeExt:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x48_STRUCT;
+
+// **** D18F3x4C Register Definition ****
+// Address
+#define D18F3x4C_ADDRESS                                        0x4c
+
+// Type
+#define D18F3x4C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x4C_ErrCoreId_OFFSET                               0
+#define D18F3x4C_ErrCoreId_WIDTH                                4
+#define D18F3x4C_ErrCoreId_MASK                                 0xf
+#define D18F3x4C_Reserved_39_37_OFFSET                          5
+#define D18F3x4C_Reserved_39_37_WIDTH                           3
+#define D18F3x4C_Reserved_39_37_MASK                            0xe0
+#define D18F3x4C_Reserved_40_40_OFFSET                          8
+#define D18F3x4C_Reserved_40_40_WIDTH                           1
+#define D18F3x4C_Reserved_40_40_MASK                            0x100
+#define D18F3x4C_SubLink_OFFSET                                 9
+#define D18F3x4C_SubLink_WIDTH                                  1
+#define D18F3x4C_SubLink_MASK                                   0x200
+#define D18F3x4C_Reserved_43_42_OFFSET                          10
+#define D18F3x4C_Reserved_43_42_WIDTH                           2
+#define D18F3x4C_Reserved_43_42_MASK                            0xc00
+#define D18F3x4C_Reserved_54_45_OFFSET                          13
+#define D18F3x4C_Reserved_54_45_WIDTH                           10
+#define D18F3x4C_Reserved_54_45_MASK                            0x7fe000
+#define D18F3x4C_Reserved_55_55_OFFSET                          23
+#define D18F3x4C_Reserved_55_55_WIDTH                           1
+#define D18F3x4C_Reserved_55_55_MASK                            0x800000
+#define D18F3x4C_ErrCoreIdVal_OFFSET                            24
+#define D18F3x4C_ErrCoreIdVal_WIDTH                             1
+#define D18F3x4C_ErrCoreIdVal_MASK                              0x1000000
+#define D18F3x4C_PCC_OFFSET                                     25
+#define D18F3x4C_PCC_WIDTH                                      1
+#define D18F3x4C_PCC_MASK                                       0x2000000
+#define D18F3x4C_AddrV_OFFSET                                   26
+#define D18F3x4C_AddrV_WIDTH                                    1
+#define D18F3x4C_AddrV_MASK                                     0x4000000
+#define D18F3x4C_MiscV_OFFSET                                   27
+#define D18F3x4C_MiscV_WIDTH                                    1
+#define D18F3x4C_MiscV_MASK                                     0x8000000
+#define D18F3x4C_En_OFFSET                                      28
+#define D18F3x4C_En_WIDTH                                       1
+#define D18F3x4C_En_MASK                                        0x10000000
+#define D18F3x4C_UC_OFFSET                                      29
+#define D18F3x4C_UC_WIDTH                                       1
+#define D18F3x4C_UC_MASK                                        0x20000000
+#define D18F3x4C_Overflow_OFFSET                                30
+#define D18F3x4C_Overflow_WIDTH                                 1
+#define D18F3x4C_Overflow_MASK                                  0x40000000
+#define D18F3x4C_Val_OFFSET                                     31
+#define D18F3x4C_Val_WIDTH                                      1
+#define D18F3x4C_Val_MASK                                       0x80000000
+
+/// D18F3x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ErrCoreId:4 ; ///<
+    UINT32                                                     Link:1 ; ///<
+    UINT32                                           Reserved_39_37:3 ; ///<
+    UINT32                                           Reserved_40_40:1 ; ///<
+    UINT32                                                  SubLink:1 ; ///<
+    UINT32                                           Reserved_43_42:2 ; ///<
+    UINT32                                           Reserved_44_44:1 ; ///<
+    UINT32                                           Reserved_54_45:10; ///<
+    UINT32                                           Reserved_55_55:1 ; ///<
+    UINT32                                             ErrCoreIdVal:1 ; ///<
+    UINT32                                                      PCC:1 ; ///<
+    UINT32                                                    AddrV:1 ; ///<
+    UINT32                                                    MiscV:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                                       UC:1 ; ///<
+    UINT32                                                 Overflow:1 ; ///<
+    UINT32                                                      Val:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x4C_STRUCT;
+
+// **** D18F3x50 Register Definition ****
+// Address
+#define D18F3x50_ADDRESS                                        0x50
+
+// Type
+#define D18F3x50_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x50_Reserved_0_0_OFFSET                            0
+#define D18F3x50_Reserved_0_0_WIDTH                             1
+#define D18F3x50_Reserved_0_0_MASK                              0x1
+#define D18F3x50_ErrAddr_31_1__OFFSET                           1
+#define D18F3x50_ErrAddr_31_1__WIDTH                            31
+#define D18F3x50_ErrAddr_31_1__MASK                             0xfffffffe
+
+/// D18F3x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                            ErrAddr_31_1_:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x50_STRUCT;
+
+// **** D18F3x54 Register Definition ****
+// Address
+#define D18F3x54_ADDRESS                                        0x54
+
+// Type
+#define D18F3x54_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x54_ErrAddr_47_32__OFFSET                          0
+#define D18F3x54_ErrAddr_47_32__WIDTH                           16
+#define D18F3x54_ErrAddr_47_32__MASK                            0xffff
+#define D18F3x54_Reserved_63_48_OFFSET                          16
+#define D18F3x54_Reserved_63_48_WIDTH                           16
+#define D18F3x54_Reserved_63_48_MASK                            0xffff0000
+
+/// D18F3x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           ErrAddr_47_32_:16; ///<
+    UINT32                                           Reserved_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x54_STRUCT;
+
+// **** D18F3x64 Register Definition ****
+// Address
+#define D18F3x64_ADDRESS                                        0x64
+
+// Type
+#define D18F3x64_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x64_HtcEn_OFFSET                                   0
+#define D18F3x64_HtcEn_WIDTH                                    1
+#define D18F3x64_HtcEn_MASK                                     0x1
+#define D18F3x64_Reserved_3_1_OFFSET                            1
+#define D18F3x64_Reserved_3_1_WIDTH                             3
+#define D18F3x64_Reserved_3_1_MASK                              0xe
+#define D18F3x64_HtcAct_OFFSET                                  4
+#define D18F3x64_HtcAct_WIDTH                                   1
+#define D18F3x64_HtcAct_MASK                                    0x10
+#define D18F3x64_HtcActSts_OFFSET                               5
+#define D18F3x64_HtcActSts_WIDTH                                1
+#define D18F3x64_HtcActSts_MASK                                 0x20
+#define D18F3x64_PslApicHiEn_OFFSET                             6
+#define D18F3x64_PslApicHiEn_WIDTH                              1
+#define D18F3x64_PslApicHiEn_MASK                               0x40
+#define D18F3x64_PslApicLoEn_OFFSET                             7
+#define D18F3x64_PslApicLoEn_WIDTH                              1
+#define D18F3x64_PslApicLoEn_MASK                               0x80
+#define D18F3x64_Reserved_15_8_OFFSET                           8
+#define D18F3x64_Reserved_15_8_WIDTH                            8
+#define D18F3x64_Reserved_15_8_MASK                             0xff00
+#define D18F3x64_HtcTmpLmt_OFFSET                               16
+#define D18F3x64_HtcTmpLmt_WIDTH                                7
+#define D18F3x64_HtcTmpLmt_MASK                                 0x7f0000
+#define D18F3x64_HtcSlewSel_OFFSET                              23
+#define D18F3x64_HtcSlewSel_WIDTH                               1
+#define D18F3x64_HtcSlewSel_MASK                                0x800000
+#define D18F3x64_HtcHystLmt_OFFSET                              24
+#define D18F3x64_HtcHystLmt_WIDTH                               4
+#define D18F3x64_HtcHystLmt_MASK                                0xf000000
+#define D18F3x64_HtcPstateLimit_OFFSET                          28
+#define D18F3x64_HtcPstateLimit_WIDTH                           3
+#define D18F3x64_HtcPstateLimit_MASK                            0x70000000
+#define D18F3x64_Reserved_31_31_OFFSET                          31
+#define D18F3x64_Reserved_31_31_WIDTH                           1
+#define D18F3x64_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    HtcEn:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                                   HtcAct:1 ; ///<
+    UINT32                                                HtcActSts:1 ; ///<
+    UINT32                                              PslApicHiEn:1 ; ///<
+    UINT32                                              PslApicLoEn:1 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                                HtcTmpLmt:7 ; ///<
+    UINT32                                               HtcSlewSel:1 ; ///<
+    UINT32                                               HtcHystLmt:4 ; ///<
+    UINT32                                           HtcPstateLimit:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x64_STRUCT;
+
+// **** D18F3x68 Register Definition ****
+// Address
+#define D18F3x68_ADDRESS                                        0x68
+
+// Type
+#define D18F3x68_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x68_Reserved_4_0_OFFSET                            0
+#define D18F3x68_Reserved_4_0_WIDTH                             5
+#define D18F3x68_Reserved_4_0_MASK                              0x1f
+#define D18F3x68_SwPstateLimitEn_OFFSET                         5
+#define D18F3x68_SwPstateLimitEn_WIDTH                          1
+#define D18F3x68_SwPstateLimitEn_MASK                           0x20
+#define D18F3x68_Reserved_27_6_OFFSET                           6
+#define D18F3x68_Reserved_27_6_WIDTH                            22
+#define D18F3x68_Reserved_27_6_MASK                             0xfffffc0
+#define D18F3x68_SwPstateLimit_OFFSET                           28
+#define D18F3x68_SwPstateLimit_WIDTH                            3
+#define D18F3x68_SwPstateLimit_MASK                             0x70000000
+#define D18F3x68_Reserved_31_31_OFFSET                          31
+#define D18F3x68_Reserved_31_31_WIDTH                           1
+#define D18F3x68_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                          SwPstateLimitEn:1 ; ///<
+    UINT32                                            Reserved_27_6:22; ///<
+    UINT32                                            SwPstateLimit:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x68_STRUCT;
+
+// **** D18F3x6C Register Definition ****
+// Address
+#define D18F3x6C_ADDRESS                                        0x6c
+
+// Type
+#define D18F3x6C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x6C_UpReqDBC_OFFSET                                0
+#define D18F3x6C_UpReqDBC_WIDTH                                 3
+#define D18F3x6C_UpReqDBC_MASK                                  0x7
+#define D18F3x6C_Reserved_3_3_OFFSET                            3
+#define D18F3x6C_Reserved_3_3_WIDTH                             1
+#define D18F3x6C_Reserved_3_3_MASK                              0x8
+#define D18F3x6C_DnReqDBC_OFFSET                                4
+#define D18F3x6C_DnReqDBC_WIDTH                                 2
+#define D18F3x6C_DnReqDBC_MASK                                  0x30
+#define D18F3x6C_DnRspDBC_OFFSET                                6
+#define D18F3x6C_DnRspDBC_WIDTH                                 2
+#define D18F3x6C_DnRspDBC_MASK                                  0xc0
+#define D18F3x6C_Reserved_15_8_OFFSET                           8
+#define D18F3x6C_Reserved_15_8_WIDTH                            8
+#define D18F3x6C_Reserved_15_8_MASK                             0xff00
+#define D18F3x6C_UpRspDBC_OFFSET                                16
+#define D18F3x6C_UpRspDBC_WIDTH                                 3
+#define D18F3x6C_UpRspDBC_MASK                                  0x70000
+#define D18F3x6C_Reserved_27_19_OFFSET                          19
+#define D18F3x6C_Reserved_27_19_WIDTH                           9
+#define D18F3x6C_Reserved_27_19_MASK                            0xff80000
+#define D18F3x6C_IsocRspDBC_OFFSET                              28
+#define D18F3x6C_IsocRspDBC_WIDTH                               3
+#define D18F3x6C_IsocRspDBC_MASK                                0x70000000
+#define D18F3x6C_Reserved_31_31_OFFSET                          31
+#define D18F3x6C_Reserved_31_31_WIDTH                           1
+#define D18F3x6C_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqDBC:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                 DnReqDBC:2 ; ///<
+    UINT32                                                 DnRspDBC:2 ; ///<
+    UINT32                                            Reserved_15_8:8 ; ///<
+    UINT32                                                 UpRspDBC:3 ; ///<
+    UINT32                                           Reserved_27_19:9 ; ///<
+    UINT32                                               IsocRspDBC:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x6C_STRUCT;
+
+// **** D18F3x70 Register Definition ****
+// Address
+#define D18F3x70_ADDRESS                                        0x70
+
+// Type
+#define D18F3x70_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x70_UpReqCBC_OFFSET                                0
+#define D18F3x70_UpReqCBC_WIDTH                                 3
+#define D18F3x70_UpReqCBC_MASK                                  0x7
+#define D18F3x70_Reserved_3_3_OFFSET                            3
+#define D18F3x70_Reserved_3_3_WIDTH                             1
+#define D18F3x70_Reserved_3_3_MASK                              0x8
+#define D18F3x70_DnReqCBC_OFFSET                                4
+#define D18F3x70_DnReqCBC_WIDTH                                 2
+#define D18F3x70_DnReqCBC_MASK                                  0x30
+#define D18F3x70_DnRspCBC_OFFSET                                6
+#define D18F3x70_DnRspCBC_WIDTH                                 2
+#define D18F3x70_DnRspCBC_MASK                                  0xc0
+#define D18F3x70_UpPreqCBC_OFFSET                               8
+#define D18F3x70_UpPreqCBC_WIDTH                                3
+#define D18F3x70_UpPreqCBC_MASK                                 0x700
+#define D18F3x70_Reserved_11_11_OFFSET                          11
+#define D18F3x70_Reserved_11_11_WIDTH                           1
+#define D18F3x70_Reserved_11_11_MASK                            0x800
+#define D18F3x70_DnPreqCBC_OFFSET                               12
+#define D18F3x70_DnPreqCBC_WIDTH                                3
+#define D18F3x70_DnPreqCBC_MASK                                 0x7000
+#define D18F3x70_Reserved_15_15_OFFSET                          15
+#define D18F3x70_Reserved_15_15_WIDTH                           1
+#define D18F3x70_Reserved_15_15_MASK                            0x8000
+#define D18F3x70_UpRspCBC_OFFSET                                16
+#define D18F3x70_UpRspCBC_WIDTH                                 3
+#define D18F3x70_UpRspCBC_MASK                                  0x70000
+#define D18F3x70_Reserved_19_19_OFFSET                          19
+#define D18F3x70_Reserved_19_19_WIDTH                           1
+#define D18F3x70_Reserved_19_19_MASK                            0x80000
+#define D18F3x70_IsocReqCBC_OFFSET                              20
+#define D18F3x70_IsocReqCBC_WIDTH                               3
+#define D18F3x70_IsocReqCBC_MASK                                0x700000
+#define D18F3x70_Reserved_23_23_OFFSET                          23
+#define D18F3x70_Reserved_23_23_WIDTH                           1
+#define D18F3x70_Reserved_23_23_MASK                            0x800000
+#define D18F3x70_IsocPreqCBC_OFFSET                             24
+#define D18F3x70_IsocPreqCBC_WIDTH                              3
+#define D18F3x70_IsocPreqCBC_MASK                               0x7000000
+#define D18F3x70_Reserved_27_27_OFFSET                          27
+#define D18F3x70_Reserved_27_27_WIDTH                           1
+#define D18F3x70_Reserved_27_27_MASK                            0x8000000
+#define D18F3x70_IsocRspCBC_OFFSET                              28
+#define D18F3x70_IsocRspCBC_WIDTH                               3
+#define D18F3x70_IsocRspCBC_MASK                                0x70000000
+#define D18F3x70_Reserved_31_31_OFFSET                          31
+#define D18F3x70_Reserved_31_31_WIDTH                           1
+#define D18F3x70_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqCBC:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                 DnReqCBC:2 ; ///<
+    UINT32                                                 DnRspCBC:2 ; ///<
+    UINT32                                                UpPreqCBC:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                                DnPreqCBC:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                 UpRspCBC:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                               IsocReqCBC:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                              IsocPreqCBC:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                               IsocRspCBC:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x70_STRUCT;
+
+// **** D18F3x74 Register Definition ****
+// Address
+#define D18F3x74_ADDRESS                                        0x74
+
+// Type
+#define D18F3x74_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x74_UpReqCBC_OFFSET                                0
+#define D18F3x74_UpReqCBC_WIDTH                                 3
+#define D18F3x74_UpReqCBC_MASK                                  0x7
+#define D18F3x74_Reserved_3_3_OFFSET                            3
+#define D18F3x74_Reserved_3_3_WIDTH                             1
+#define D18F3x74_Reserved_3_3_MASK                              0x8
+#define D18F3x74_DnReqCBC_OFFSET                                4
+#define D18F3x74_DnReqCBC_WIDTH                                 3
+#define D18F3x74_DnReqCBC_MASK                                  0x70
+#define D18F3x74_Reserved_7_7_OFFSET                            7
+#define D18F3x74_Reserved_7_7_WIDTH                             1
+#define D18F3x74_Reserved_7_7_MASK                              0x80
+#define D18F3x74_UpPreqCBC_OFFSET                               8
+#define D18F3x74_UpPreqCBC_WIDTH                                3
+#define D18F3x74_UpPreqCBC_MASK                                 0x700
+#define D18F3x74_Reserved_11_11_OFFSET                          11
+#define D18F3x74_Reserved_11_11_WIDTH                           1
+#define D18F3x74_Reserved_11_11_MASK                            0x800
+#define D18F3x74_DnPreqCBC_OFFSET                               12
+#define D18F3x74_DnPreqCBC_WIDTH                                3
+#define D18F3x74_DnPreqCBC_MASK                                 0x7000
+#define D18F3x74_Reserved_15_15_OFFSET                          15
+#define D18F3x74_Reserved_15_15_WIDTH                           1
+#define D18F3x74_Reserved_15_15_MASK                            0x8000
+#define D18F3x74_ProbeCBC_OFFSET                                16
+#define D18F3x74_ProbeCBC_WIDTH                                 4
+#define D18F3x74_ProbeCBC_MASK                                  0xf0000
+#define D18F3x74_IsocReqCBC_OFFSET                              20
+#define D18F3x74_IsocReqCBC_WIDTH                               4
+#define D18F3x74_IsocReqCBC_MASK                                0xf00000
+#define D18F3x74_IsocPreqCBC_OFFSET                             24
+#define D18F3x74_IsocPreqCBC_WIDTH                              3
+#define D18F3x74_IsocPreqCBC_MASK                               0x7000000
+#define D18F3x74_Reserved_27_27_OFFSET                          27
+#define D18F3x74_Reserved_27_27_WIDTH                           1
+#define D18F3x74_Reserved_27_27_MASK                            0x8000000
+#define D18F3x74_DRReqCBC_OFFSET                                28
+#define D18F3x74_DRReqCBC_WIDTH                                 4
+#define D18F3x74_DRReqCBC_MASK                                  0xf0000000
+
+/// D18F3x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqCBC:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                                 DnReqCBC:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                UpPreqCBC:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                                DnPreqCBC:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                 ProbeCBC:4 ; ///<
+    UINT32                                               IsocReqCBC:4 ; ///<
+    UINT32                                              IsocPreqCBC:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                                 DRReqCBC:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x74_STRUCT;
+
+// **** D18F3x78 Register Definition ****
+// Address
+#define D18F3x78_ADDRESS                                        0x78
+
+// Type
+#define D18F3x78_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x78_RspCBC_OFFSET                                  0
+#define D18F3x78_RspCBC_WIDTH                                   5
+#define D18F3x78_RspCBC_MASK                                    0x1f
+#define D18F3x78_Reserved_7_5_OFFSET                            5
+#define D18F3x78_Reserved_7_5_WIDTH                             3
+#define D18F3x78_Reserved_7_5_MASK                              0xe0
+#define D18F3x78_ProbeCBC_OFFSET                                8
+#define D18F3x78_ProbeCBC_WIDTH                                 5
+#define D18F3x78_ProbeCBC_MASK                                  0x1f00
+#define D18F3x78_Reserved_15_13_OFFSET                          13
+#define D18F3x78_Reserved_15_13_WIDTH                           3
+#define D18F3x78_Reserved_15_13_MASK                            0xe000
+#define D18F3x78_RspDBC_OFFSET                                  16
+#define D18F3x78_RspDBC_WIDTH                                   6
+#define D18F3x78_RspDBC_MASK                                    0x3f0000
+#define D18F3x78_Reserved_31_22_OFFSET                          22
+#define D18F3x78_Reserved_31_22_WIDTH                           10
+#define D18F3x78_Reserved_31_22_MASK                            0xffc00000
+
+/// D18F3x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   RspCBC:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                 ProbeCBC:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                   RspDBC:6 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x78_STRUCT;
+
+// **** D18F3x7C Register Definition ****
+// Address
+#define D18F3x7C_ADDRESS                                        0x7c
+
+// Type
+#define D18F3x7C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x7C_Xbar2SriFreeListCBC_OFFSET                     0
+#define D18F3x7C_Xbar2SriFreeListCBC_WIDTH                      5
+#define D18F3x7C_Xbar2SriFreeListCBC_MASK                       0x1f
+#define D18F3x7C_Reserved_7_5_OFFSET                            5
+#define D18F3x7C_Reserved_7_5_WIDTH                             3
+#define D18F3x7C_Reserved_7_5_MASK                              0xe0
+#define D18F3x7C_Sri2XbarFreeXreqCBC_OFFSET                     8
+#define D18F3x7C_Sri2XbarFreeXreqCBC_WIDTH                      4
+#define D18F3x7C_Sri2XbarFreeXreqCBC_MASK                       0xf00
+#define D18F3x7C_Sri2XbarFreeRspCBC_OFFSET                      12
+#define D18F3x7C_Sri2XbarFreeRspCBC_WIDTH                       4
+#define D18F3x7C_Sri2XbarFreeRspCBC_MASK                        0xf000
+#define D18F3x7C_Sri2XbarFreeXreqDBC_OFFSET                     16
+#define D18F3x7C_Sri2XbarFreeXreqDBC_WIDTH                      4
+#define D18F3x7C_Sri2XbarFreeXreqDBC_MASK                       0xf0000
+#define D18F3x7C_Sri2XbarFreeRspDBC_OFFSET                      20
+#define D18F3x7C_Sri2XbarFreeRspDBC_WIDTH                       3
+#define D18F3x7C_Sri2XbarFreeRspDBC_MASK                        0x700000
+#define D18F3x7C_ExtSrqFreeList_OFFSET                          23
+#define D18F3x7C_ExtSrqFreeList_WIDTH                           4
+#define D18F3x7C_ExtSrqFreeList_MASK                            0x7800000
+#define D18F3x7C_Reserved_27_27_OFFSET                          27
+#define D18F3x7C_Reserved_27_27_WIDTH                           1
+#define D18F3x7C_Reserved_27_27_MASK                            0x8000000
+#define D18F3x7C_Xbar2SriFreeListCBInc_OFFSET                   28
+#define D18F3x7C_Xbar2SriFreeListCBInc_WIDTH                    3
+#define D18F3x7C_Xbar2SriFreeListCBInc_MASK                     0x70000000
+#define D18F3x7C_Reserved_31_31_OFFSET                          31
+#define D18F3x7C_Reserved_31_31_WIDTH                           1
+#define D18F3x7C_Reserved_31_31_MASK                            0x80000000
+
+/// D18F3x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      Xbar2SriFreeListCBC:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                      Sri2XbarFreeXreqCBC:4 ; ///<
+    UINT32                                       Sri2XbarFreeRspCBC:4 ; ///<
+    UINT32                                      Sri2XbarFreeXreqDBC:4 ; ///<
+    UINT32                                       Sri2XbarFreeRspDBC:3 ; ///<
+    UINT32                                           ExtSrqFreeList:4 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                    Xbar2SriFreeListCBInc:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x7C_STRUCT;
+
+// **** D18F3x80 Register Definition ****
+// Address
+#define D18F3x80_ADDRESS                                        0x80
+
+// Type
+#define D18F3x80_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x80_CpuPrbEnSmafAct0_OFFSET                        0
+#define D18F3x80_CpuPrbEnSmafAct0_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct0_MASK                          0x1
+#define D18F3x80_NbLowPwrEnSmafAct0_OFFSET                      1
+#define D18F3x80_NbLowPwrEnSmafAct0_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct0_MASK                        0x2
+#define D18F3x80_NbGateEnSmafAct0_OFFSET                        2
+#define D18F3x80_NbGateEnSmafAct0_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct0_MASK                          0x4
+#define D18F3x80_Reserved_4_3_OFFSET                            3
+#define D18F3x80_Reserved_4_3_WIDTH                             2
+#define D18F3x80_Reserved_4_3_MASK                              0x18
+#define D18F3x80_ClkDivisorSmafAct0_OFFSET                      5
+#define D18F3x80_ClkDivisorSmafAct0_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct0_MASK                        0xe0
+#define D18F3x80_CpuPrbEnSmafAct1_OFFSET                        8
+#define D18F3x80_CpuPrbEnSmafAct1_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct1_MASK                          0x100
+#define D18F3x80_NbLowPwrEnSmafAct1_OFFSET                      9
+#define D18F3x80_NbLowPwrEnSmafAct1_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct1_MASK                        0x200
+#define D18F3x80_NbGateEnSmafAct1_OFFSET                        10
+#define D18F3x80_NbGateEnSmafAct1_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct1_MASK                          0x400
+#define D18F3x80_Reserved_12_11_OFFSET                          11
+#define D18F3x80_Reserved_12_11_WIDTH                           2
+#define D18F3x80_Reserved_12_11_MASK                            0x1800
+#define D18F3x80_ClkDivisorSmafAct1_OFFSET                      13
+#define D18F3x80_ClkDivisorSmafAct1_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct1_MASK                        0xe000
+#define D18F3x80_CpuPrbEnSmafAct2_OFFSET                        16
+#define D18F3x80_CpuPrbEnSmafAct2_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct2_MASK                          0x10000
+#define D18F3x80_NbLowPwrEnSmafAct2_OFFSET                      17
+#define D18F3x80_NbLowPwrEnSmafAct2_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct2_MASK                        0x20000
+#define D18F3x80_NbGateEnSmafAct2_OFFSET                        18
+#define D18F3x80_NbGateEnSmafAct2_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct2_MASK                          0x40000
+#define D18F3x80_Reserved_20_19_OFFSET                          19
+#define D18F3x80_Reserved_20_19_WIDTH                           2
+#define D18F3x80_Reserved_20_19_MASK                            0x180000
+#define D18F3x80_ClkDivisorSmafAct2_OFFSET                      21
+#define D18F3x80_ClkDivisorSmafAct2_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct2_MASK                        0xe00000
+#define D18F3x80_CpuPrbEnSmafAct3_OFFSET                        24
+#define D18F3x80_CpuPrbEnSmafAct3_WIDTH                         1
+#define D18F3x80_CpuPrbEnSmafAct3_MASK                          0x1000000
+#define D18F3x80_NbLowPwrEnSmafAct3_OFFSET                      25
+#define D18F3x80_NbLowPwrEnSmafAct3_WIDTH                       1
+#define D18F3x80_NbLowPwrEnSmafAct3_MASK                        0x2000000
+#define D18F3x80_NbGateEnSmafAct3_OFFSET                        26
+#define D18F3x80_NbGateEnSmafAct3_WIDTH                         1
+#define D18F3x80_NbGateEnSmafAct3_MASK                          0x4000000
+#define D18F3x80_Reserved_28_27_OFFSET                          27
+#define D18F3x80_Reserved_28_27_WIDTH                           2
+#define D18F3x80_Reserved_28_27_MASK                            0x18000000
+#define D18F3x80_ClkDivisorSmafAct3_OFFSET                      29
+#define D18F3x80_ClkDivisorSmafAct3_WIDTH                       3
+#define D18F3x80_ClkDivisorSmafAct3_MASK                        0xe0000000
+
+/// D18F3x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CpuPrbEnSmafAct0:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct0:1 ; ///<
+    UINT32                                         NbGateEnSmafAct0:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct0:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct1:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct1:1 ; ///<
+    UINT32                                         NbGateEnSmafAct1:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct1:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct2:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct2:1 ; ///<
+    UINT32                                         NbGateEnSmafAct2:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct2:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct3:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct3:1 ; ///<
+    UINT32                                         NbGateEnSmafAct3:1 ; ///<
+    UINT32                                           Reserved_28_27:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x80_STRUCT;
+
+// **** D18F3x84 Register Definition ****
+// Address
+#define D18F3x84_ADDRESS                                        0x84
+
+// Type
+#define D18F3x84_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x84_CpuPrbEnSmafAct4_OFFSET                        0
+#define D18F3x84_CpuPrbEnSmafAct4_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct4_MASK                          0x1
+#define D18F3x84_NbLowPwrEnSmafAct4_OFFSET                      1
+#define D18F3x84_NbLowPwrEnSmafAct4_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct4_MASK                        0x2
+#define D18F3x84_NbGateEnSmafAct4_OFFSET                        2
+#define D18F3x84_NbGateEnSmafAct4_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct4_MASK                          0x4
+#define D18F3x84_Reserved_4_3_OFFSET                            3
+#define D18F3x84_Reserved_4_3_WIDTH                             2
+#define D18F3x84_Reserved_4_3_MASK                              0x18
+#define D18F3x84_ClkDivisorSmafAct4_OFFSET                      5
+#define D18F3x84_ClkDivisorSmafAct4_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct4_MASK                        0xe0
+#define D18F3x84_CpuPrbEnSmafAct5_OFFSET                        8
+#define D18F3x84_CpuPrbEnSmafAct5_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct5_MASK                          0x100
+#define D18F3x84_NbLowPwrEnSmafAct5_OFFSET                      9
+#define D18F3x84_NbLowPwrEnSmafAct5_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct5_MASK                        0x200
+#define D18F3x84_NbGateEnSmafAct5_OFFSET                        10
+#define D18F3x84_NbGateEnSmafAct5_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct5_MASK                          0x400
+#define D18F3x84_Reserved_12_11_OFFSET                          11
+#define D18F3x84_Reserved_12_11_WIDTH                           2
+#define D18F3x84_Reserved_12_11_MASK                            0x1800
+#define D18F3x84_ClkDivisorSmafAct5_OFFSET                      13
+#define D18F3x84_ClkDivisorSmafAct5_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct5_MASK                        0xe000
+#define D18F3x84_CpuPrbEnSmafAct6_OFFSET                        16
+#define D18F3x84_CpuPrbEnSmafAct6_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct6_MASK                          0x10000
+#define D18F3x84_NbLowPwrEnSmafAct6_OFFSET                      17
+#define D18F3x84_NbLowPwrEnSmafAct6_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct6_MASK                        0x20000
+#define D18F3x84_NbGateEnSmafAct6_OFFSET                        18
+#define D18F3x84_NbGateEnSmafAct6_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct6_MASK                          0x40000
+#define D18F3x84_Reserved_20_19_OFFSET                          19
+#define D18F3x84_Reserved_20_19_WIDTH                           2
+#define D18F3x84_Reserved_20_19_MASK                            0x180000
+#define D18F3x84_ClkDivisorSmafAct6_OFFSET                      21
+#define D18F3x84_ClkDivisorSmafAct6_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct6_MASK                        0xe00000
+#define D18F3x84_CpuPrbEnSmafAct7_OFFSET                        24
+#define D18F3x84_CpuPrbEnSmafAct7_WIDTH                         1
+#define D18F3x84_CpuPrbEnSmafAct7_MASK                          0x1000000
+#define D18F3x84_NbLowPwrEnSmafAct7_OFFSET                      25
+#define D18F3x84_NbLowPwrEnSmafAct7_WIDTH                       1
+#define D18F3x84_NbLowPwrEnSmafAct7_MASK                        0x2000000
+#define D18F3x84_NbGateEnSmafAct7_OFFSET                        26
+#define D18F3x84_NbGateEnSmafAct7_WIDTH                         1
+#define D18F3x84_NbGateEnSmafAct7_MASK                          0x4000000
+#define D18F3x84_Reserved_28_27_OFFSET                          27
+#define D18F3x84_Reserved_28_27_WIDTH                           2
+#define D18F3x84_Reserved_28_27_MASK                            0x18000000
+#define D18F3x84_ClkDivisorSmafAct7_OFFSET                      29
+#define D18F3x84_ClkDivisorSmafAct7_WIDTH                       3
+#define D18F3x84_ClkDivisorSmafAct7_MASK                        0xe0000000
+
+/// D18F3x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         CpuPrbEnSmafAct4:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct4:1 ; ///<
+    UINT32                                         NbGateEnSmafAct4:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct4:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct5:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct5:1 ; ///<
+    UINT32                                         NbGateEnSmafAct5:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct5:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct6:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct6:1 ; ///<
+    UINT32                                         NbGateEnSmafAct6:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct6:3 ; ///<
+    UINT32                                         CpuPrbEnSmafAct7:1 ; ///<
+    UINT32                                       NbLowPwrEnSmafAct7:1 ; ///<
+    UINT32                                         NbGateEnSmafAct7:1 ; ///<
+    UINT32                                           Reserved_28_27:2 ; ///<
+    UINT32                                       ClkDivisorSmafAct7:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x84_STRUCT;
+
+// **** D18F3x88 Register Definition ****
+// Address
+#define D18F3x88_ADDRESS                                        0x88
+
+// Type
+#define D18F3x88_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x88_Reserved_30_0_OFFSET                           0
+#define D18F3x88_Reserved_30_0_WIDTH                            31
+#define D18F3x88_Reserved_30_0_MASK                             0x7fffffff
+#define D18F3x88_DisCohLdtCfg_OFFSET                            31
+#define D18F3x88_DisCohLdtCfg_WIDTH                             1
+#define D18F3x88_DisCohLdtCfg_MASK                              0x80000000
+
+/// D18F3x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_30_0:31; ///<
+    UINT32                                             DisCohLdtCfg:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x88_STRUCT;
+
+// **** D18F3x8C Register Definition ****
+// Address
+#define D18F3x8C_ADDRESS                                        0x8c
+
+// Type
+#define D18F3x8C_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3x8C_Reserved_35_32_OFFSET                          0
+#define D18F3x8C_Reserved_35_32_WIDTH                           4
+#define D18F3x8C_Reserved_35_32_MASK                            0xf
+#define D18F3x8C_DisDatMsk_OFFSET                               4
+#define D18F3x8C_DisDatMsk_WIDTH                                1
+#define D18F3x8C_DisDatMsk_MASK                                 0x10
+#define D18F3x8C_Reserved_44_37_OFFSET                          5
+#define D18F3x8C_Reserved_44_37_WIDTH                           8
+#define D18F3x8C_Reserved_44_37_MASK                            0x1fe0
+#define D18F3x8C_DisUsSysMgtReqToNcHt_OFFSET                    13
+#define D18F3x8C_DisUsSysMgtReqToNcHt_WIDTH                     1
+#define D18F3x8C_DisUsSysMgtReqToNcHt_MASK                      0x2000
+#define D18F3x8C_EnableCf8ExtCfg_OFFSET                         14
+#define D18F3x8C_EnableCf8ExtCfg_WIDTH                          1
+#define D18F3x8C_EnableCf8ExtCfg_MASK                           0x4000
+#define D18F3x8C_Reserved_49_47_OFFSET                          15
+#define D18F3x8C_Reserved_49_47_WIDTH                           3
+#define D18F3x8C_Reserved_49_47_MASK                            0x38000
+#define D18F3x8C_DisOrderRdRsp_OFFSET                           18
+#define D18F3x8C_DisOrderRdRsp_WIDTH                            1
+#define D18F3x8C_DisOrderRdRsp_MASK                             0x40000
+#define D18F3x8C_Reserved_53_51_OFFSET                          19
+#define D18F3x8C_Reserved_53_51_WIDTH                           3
+#define D18F3x8C_Reserved_53_51_MASK                            0x380000
+#define D18F3x8C_InitApicIdCpuIdLo_OFFSET                       22
+#define D18F3x8C_InitApicIdCpuIdLo_WIDTH                        1
+#define D18F3x8C_InitApicIdCpuIdLo_MASK                         0x400000
+#define D18F3x8C_Reserved_63_55_OFFSET                          23
+#define D18F3x8C_Reserved_63_55_WIDTH                           9
+#define D18F3x8C_Reserved_63_55_MASK                            0xff800000
+
+/// D18F3x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           Reserved_35_32:4 ; ///<
+    UINT32                                                DisDatMsk:1 ; ///<
+    UINT32                                           Reserved_44_37:8 ; ///<
+    UINT32                                     DisUsSysMgtReqToNcHt:1 ; ///<
+    UINT32                                          EnableCf8ExtCfg:1 ; ///<
+    UINT32                                           Reserved_49_47:3 ; ///<
+    UINT32                                            DisOrderRdRsp:1 ; ///<
+    UINT32                                           Reserved_53_51:3 ; ///<
+    UINT32                                        InitApicIdCpuIdLo:1 ; ///<
+    UINT32                                           Reserved_63_55:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x8C_STRUCT;
+
+// **** D18F3xA0 Register Definition ****
+// Address
+#define D18F3xA0_ADDRESS                                        0xa0
+
+// Type
+#define D18F3xA0_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xA0_PsiVid_6_0__OFFSET                             0
+#define D18F3xA0_PsiVid_6_0__WIDTH                              7
+#define D18F3xA0_PsiVid_6_0__MASK                               0x7f
+#define D18F3xA0_PsiVidEn_OFFSET                                7
+#define D18F3xA0_PsiVidEn_WIDTH                                 1
+#define D18F3xA0_PsiVidEn_MASK                                  0x80
+#define D18F3xA0_PsiVid_7__OFFSET                               8
+#define D18F3xA0_PsiVid_7__WIDTH                                1
+#define D18F3xA0_PsiVid_7__MASK                                 0x100
+#define D18F3xA0_Reserved_10_9_OFFSET                           9
+#define D18F3xA0_Reserved_10_9_WIDTH                            2
+#define D18F3xA0_Reserved_10_9_MASK                             0x600
+#define D18F3xA0_PllLockTime_OFFSET                             11
+#define D18F3xA0_PllLockTime_WIDTH                              3
+#define D18F3xA0_PllLockTime_MASK                               0x3800
+#define D18F3xA0_Svi2HighFreqSel_OFFSET                         14
+#define D18F3xA0_Svi2HighFreqSel_WIDTH                          1
+#define D18F3xA0_Svi2HighFreqSel_MASK                           0x4000
+#define D18F3xA0_Reserved_15_15_OFFSET                          15
+#define D18F3xA0_Reserved_15_15_WIDTH                           1
+#define D18F3xA0_Reserved_15_15_MASK                            0x8000
+#define D18F3xA0_ConfigId_OFFSET                                16
+#define D18F3xA0_ConfigId_WIDTH                                 12
+#define D18F3xA0_ConfigId_MASK                                  0xfff0000
+#define D18F3xA0_Reserved_30_28_OFFSET                          28
+#define D18F3xA0_Reserved_30_28_WIDTH                           3
+#define D18F3xA0_Reserved_30_28_MASK                            0x70000000
+#define D18F3xA0_CofVidProg_OFFSET                              31
+#define D18F3xA0_CofVidProg_WIDTH                               1
+#define D18F3xA0_CofVidProg_MASK                                0x80000000
+
+/// D18F3xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              PsiVid_6_0_:7 ; ///<
+    UINT32                                                 PsiVidEn:1 ; ///<
+    UINT32                                                PsiVid_7_:1 ; ///<
+    UINT32                                            Reserved_10_9:2 ; ///<
+    UINT32                                              PllLockTime:3 ; ///<
+    UINT32                                          Svi2HighFreqSel:1 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                                 ConfigId:12; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                               CofVidProg:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xA0_STRUCT;
+
+// **** D18F3xA4 Register Definition ****
+// Address
+#define D18F3xA4_ADDRESS                                        0xa4
+
+// Type
+#define D18F3xA4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xA4_PerStepTimeUp_OFFSET                           0
+#define D18F3xA4_PerStepTimeUp_WIDTH                            5
+#define D18F3xA4_PerStepTimeUp_MASK                             0x1f
+#define D18F3xA4_TmpMaxDiffUp_OFFSET                            5
+#define D18F3xA4_TmpMaxDiffUp_WIDTH                             2
+#define D18F3xA4_TmpMaxDiffUp_MASK                              0x60
+#define D18F3xA4_TmpSlewDnEn_OFFSET                             7
+#define D18F3xA4_TmpSlewDnEn_WIDTH                              1
+#define D18F3xA4_TmpSlewDnEn_MASK                               0x80
+#define D18F3xA4_PerStepTimeDn_OFFSET                           8
+#define D18F3xA4_PerStepTimeDn_WIDTH                            5
+#define D18F3xA4_PerStepTimeDn_MASK                             0x1f00
+#define D18F3xA4_Reserved_15_13_OFFSET                          13
+#define D18F3xA4_Reserved_15_13_WIDTH                           3
+#define D18F3xA4_Reserved_15_13_MASK                            0xe000
+#define D18F3xA4_CurTmpTjSel_OFFSET                             16
+#define D18F3xA4_CurTmpTjSel_WIDTH                              2
+#define D18F3xA4_CurTmpTjSel_MASK                               0x30000
+#define D18F3xA4_Reserved_19_18_OFFSET                          18
+#define D18F3xA4_Reserved_19_18_WIDTH                           2
+#define D18F3xA4_Reserved_19_18_MASK                            0xc0000
+#define D18F3xA4_TcenPwrDnCc6En_OFFSET                          20
+#define D18F3xA4_TcenPwrDnCc6En_WIDTH                           1
+#define D18F3xA4_TcenPwrDnCc6En_MASK                            0x100000
+#define D18F3xA4_CurTmp_OFFSET                                  21
+#define D18F3xA4_CurTmp_WIDTH                                   11
+#define D18F3xA4_CurTmp_MASK                                    0xffe00000
+
+/// D18F3xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PerStepTimeUp:5 ; ///<
+    UINT32                                             TmpMaxDiffUp:2 ; ///<
+    UINT32                                              TmpSlewDnEn:1 ; ///<
+    UINT32                                            PerStepTimeDn:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                              CurTmpTjSel:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                           TcenPwrDnCc6En:1 ; ///<
+    UINT32                                                   CurTmp:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xA4_STRUCT;
+
+// **** D18F3xA8 Register Definition ****
+// Address
+#define D18F3xA8_ADDRESS                                        0xa8
+
+// Type
+#define D18F3xA8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xA8_Reserved_28_0_OFFSET                           0
+#define D18F3xA8_Reserved_28_0_WIDTH                            29
+#define D18F3xA8_Reserved_28_0_MASK                             0x1fffffff
+#define D18F3xA8_PopDownPstate_OFFSET                           29
+#define D18F3xA8_PopDownPstate_WIDTH                            3
+#define D18F3xA8_PopDownPstate_MASK                             0xe0000000
+
+/// D18F3xA8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_28_0:29; ///<
+    UINT32                                            PopDownPstate:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xA8_STRUCT;
+
+
+// **** D18F3xD4 Register Definition ****
+// Address
+#define D18F3xD4_ADDRESS                                        0xd4
+
+// Type
+#define D18F3xD4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xD4_MaxSwPstateCpuCof_OFFSET                       0
+#define D18F3xD4_MaxSwPstateCpuCof_WIDTH                        6
+#define D18F3xD4_MaxSwPstateCpuCof_MASK                         0x3f
+#define D18F3xD4_Reserved_7_6_OFFSET                            6
+#define D18F3xD4_Reserved_7_6_WIDTH                             2
+#define D18F3xD4_Reserved_7_6_MASK                              0xc0
+#define D18F3xD4_ClkRampHystSel_OFFSET                          8
+#define D18F3xD4_ClkRampHystSel_WIDTH                           4
+#define D18F3xD4_ClkRampHystSel_MASK                            0xf00
+#define D18F3xD4_ClkRampHystCtl_OFFSET                          12
+#define D18F3xD4_ClkRampHystCtl_WIDTH                           1
+#define D18F3xD4_ClkRampHystCtl_MASK                            0x1000
+#define D18F3xD4_Reserved_13_13_OFFSET                          13
+#define D18F3xD4_Reserved_13_13_WIDTH                           1
+#define D18F3xD4_Reserved_13_13_MASK                            0x2000
+#define D18F3xD4_CacheFlushImmOnAllHalt_OFFSET                  14
+#define D18F3xD4_CacheFlushImmOnAllHalt_WIDTH                   1
+#define D18F3xD4_CacheFlushImmOnAllHalt_MASK                    0x4000
+#define D18F3xD4_Reserved_17_15_OFFSET                          15
+#define D18F3xD4_Reserved_17_15_WIDTH                           3
+#define D18F3xD4_Reserved_17_15_MASK                            0x38000
+#define D18F3xD4_Reserved_19_18_OFFSET                          18
+#define D18F3xD4_Reserved_19_18_WIDTH                           2
+#define D18F3xD4_Reserved_19_18_MASK                            0xc0000
+#define D18F3xD4_PowerStepDown_OFFSET                           20
+#define D18F3xD4_PowerStepDown_WIDTH                            4
+#define D18F3xD4_PowerStepDown_MASK                             0xf00000
+#define D18F3xD4_PowerStepUp_OFFSET                             24
+#define D18F3xD4_PowerStepUp_WIDTH                              4
+#define D18F3xD4_PowerStepUp_MASK                               0xf000000
+#define D18F3xD4_NbClkDiv_OFFSET                                28
+#define D18F3xD4_NbClkDiv_WIDTH                                 3
+#define D18F3xD4_NbClkDiv_MASK                                  0x70000000
+#define D18F3xD4_NbClkDivApplyAll_OFFSET                        31
+#define D18F3xD4_NbClkDivApplyAll_WIDTH                         1
+#define D18F3xD4_NbClkDivApplyAll_MASK                          0x80000000
+
+/// D18F3xD4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        MaxSwPstateCpuCof:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           ClkRampHystSel:4 ; ///<
+    UINT32                                           ClkRampHystCtl:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                   CacheFlushImmOnAllHalt:1 ; ///<
+    UINT32                                           Reserved_17_15:3 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                            PowerStepDown:4 ; ///<
+    UINT32                                              PowerStepUp:4 ; ///<
+    UINT32                                                 NbClkDiv:3 ; ///<
+    UINT32                                         NbClkDivApplyAll:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xD4_STRUCT;
+
+// **** D18F3xD8 Register Definition ****
+// Address
+#define D18F3xD8_ADDRESS                                        0xd8
+
+// Type
+#define D18F3xD8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xD8_Reserved_3_0_OFFSET                            0
+#define D18F3xD8_Reserved_3_0_WIDTH                             4
+#define D18F3xD8_Reserved_3_0_MASK                              0xf
+#define D18F3xD8_VSRampSlamTime_OFFSET                          4
+#define D18F3xD8_VSRampSlamTime_WIDTH                           3
+#define D18F3xD8_VSRampSlamTime_MASK                            0x70
+#define D18F3xD8_Reserved_31_7_OFFSET                           7
+#define D18F3xD8_Reserved_31_7_WIDTH                            25
+#define D18F3xD8_Reserved_31_7_MASK                             0xffffff80
+
+/// D18F3xD8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                           VSRampSlamTime:3 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xD8_STRUCT;
+
+// **** D18F3xDC Register Definition ****
+// Address
+#define D18F3xDC_ADDRESS                                        0xdc
+
+// Type
+#define D18F3xDC_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xDC_Reserved_7_0_OFFSET                            0
+#define D18F3xDC_Reserved_7_0_WIDTH                             8
+#define D18F3xDC_Reserved_7_0_MASK                              0xff
+#define D18F3xDC_PstateMaxVal_OFFSET                            8
+#define D18F3xDC_PstateMaxVal_WIDTH                             3
+#define D18F3xDC_PstateMaxVal_MASK                              0x700
+#define D18F3xDC_Reserved_11_11_OFFSET                          11
+#define D18F3xDC_Reserved_11_11_WIDTH                           1
+#define D18F3xDC_Reserved_11_11_MASK                            0x800
+#define D18F3xDC_NbsynPtrAdj_OFFSET                             12
+#define D18F3xDC_NbsynPtrAdj_WIDTH                              3
+#define D18F3xDC_NbsynPtrAdj_MASK                               0x7000
+#define D18F3xDC_Reserved_15_15_OFFSET                          15
+#define D18F3xDC_Reserved_15_15_WIDTH                           1
+#define D18F3xDC_Reserved_15_15_MASK                            0x8000
+#define D18F3xDC_CacheFlushOnHaltCtl_OFFSET                     16
+#define D18F3xDC_CacheFlushOnHaltCtl_WIDTH                      3
+#define D18F3xDC_CacheFlushOnHaltCtl_MASK                       0x70000
+#define D18F3xDC_CacheFlushOnHaltTmr_OFFSET                     19
+#define D18F3xDC_CacheFlushOnHaltTmr_WIDTH                      7
+#define D18F3xDC_CacheFlushOnHaltTmr_MASK                       0x3f80000
+#define D18F3xDC_IgnCpuPrbEn_OFFSET                             26
+#define D18F3xDC_IgnCpuPrbEn_WIDTH                              1
+#define D18F3xDC_IgnCpuPrbEn_MASK                               0x4000000
+#define D18F3xDC_Reserved_31_27_OFFSET                          27
+#define D18F3xDC_Reserved_31_27_WIDTH                           5
+#define D18F3xDC_Reserved_31_27_MASK                            0xf8000000
+
+/// D18F3xDC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                             PstateMaxVal:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              NbsynPtrAdj:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                      CacheFlushOnHaltCtl:3 ; ///<
+    UINT32                                      CacheFlushOnHaltTmr:7 ; ///<
+    UINT32                                              IgnCpuPrbEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xDC_STRUCT;
+
+// **** D18F3xE4 Register Definition ****
+// Address
+#define D18F3xE4_ADDRESS                                        0xe4
+
+// Type
+#define D18F3xE4_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xE4_Reserved_0_0_OFFSET                            0
+#define D18F3xE4_Reserved_0_0_WIDTH                             1
+#define D18F3xE4_Reserved_0_0_MASK                              0x1
+#define D18F3xE4_Thermtp_OFFSET                                 1
+#define D18F3xE4_Thermtp_WIDTH                                  1
+#define D18F3xE4_Thermtp_MASK                                   0x2
+#define D18F3xE4_Reserved_2_2_OFFSET                            2
+#define D18F3xE4_Reserved_2_2_WIDTH                             1
+#define D18F3xE4_Reserved_2_2_MASK                              0x4
+#define D18F3xE4_ThermtpSense_OFFSET                            3
+#define D18F3xE4_ThermtpSense_WIDTH                             1
+#define D18F3xE4_ThermtpSense_MASK                              0x8
+#define D18F3xE4_Reserved_4_4_OFFSET                            4
+#define D18F3xE4_Reserved_4_4_WIDTH                             1
+#define D18F3xE4_Reserved_4_4_MASK                              0x10
+#define D18F3xE4_ThermtpEn_OFFSET                               5
+#define D18F3xE4_ThermtpEn_WIDTH                                1
+#define D18F3xE4_ThermtpEn_MASK                                 0x20
+#define D18F3xE4_Reserved_30_6_OFFSET                           6
+#define D18F3xE4_Reserved_30_6_WIDTH                            25
+#define D18F3xE4_Reserved_30_6_MASK                             0x7fffffc0
+#define D18F3xE4_SwThermtp_OFFSET                               31
+#define D18F3xE4_SwThermtp_WIDTH                                1
+#define D18F3xE4_SwThermtp_MASK                                 0x80000000
+
+/// D18F3xE4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  Thermtp:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                             ThermtpSense:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                                ThermtpEn:1 ; ///<
+    UINT32                                            Reserved_30_6:25; ///<
+    UINT32                                                SwThermtp:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xE4_STRUCT;
+
+// **** D18F3xE8 Register Definition ****
+// Address
+#define D18F3xE8_ADDRESS                                        0xe8
+
+// Type
+#define D18F3xE8_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xE8_Reserved_0_0_OFFSET                            0
+#define D18F3xE8_Reserved_0_0_WIDTH                             1
+#define D18F3xE8_Reserved_0_0_MASK                              0x1
+#define D18F3xE8_DualNode_OFFSET                                1
+#define D18F3xE8_DualNode_WIDTH                                 1
+#define D18F3xE8_DualNode_MASK                                  0x2
+#define D18F3xE8_EightNode_OFFSET                               2
+#define D18F3xE8_EightNode_WIDTH                                1
+#define D18F3xE8_EightNode_MASK                                 0x4
+#define D18F3xE8_ECC_OFFSET                                     3
+#define D18F3xE8_ECC_WIDTH                                      1
+#define D18F3xE8_ECC_MASK                                       0x8
+#define D18F3xE8_ChipKill_OFFSET                                4
+#define D18F3xE8_ChipKill_WIDTH                                 1
+#define D18F3xE8_ChipKill_MASK                                  0x10
+#define D18F3xE8_Reserved_7_5_OFFSET                            5
+#define D18F3xE8_Reserved_7_5_WIDTH                             3
+#define D18F3xE8_Reserved_7_5_MASK                              0xe0
+#define D18F3xE8_MctCap_OFFSET                                  8
+#define D18F3xE8_MctCap_WIDTH                                   1
+#define D18F3xE8_MctCap_MASK                                    0x100
+#define D18F3xE8_SvmCapable_OFFSET                              9
+#define D18F3xE8_SvmCapable_WIDTH                               1
+#define D18F3xE8_SvmCapable_MASK                                0x200
+#define D18F3xE8_HtcCapable_OFFSET                              10
+#define D18F3xE8_HtcCapable_WIDTH                               1
+#define D18F3xE8_HtcCapable_MASK                                0x400
+#define D18F3xE8_Reserved_11_11_OFFSET                          11
+#define D18F3xE8_Reserved_11_11_WIDTH                           1
+#define D18F3xE8_Reserved_11_11_MASK                            0x800
+#define D18F3xE8_Reserved_13_12_OFFSET                          12
+#define D18F3xE8_Reserved_13_12_WIDTH                           2
+#define D18F3xE8_Reserved_13_12_MASK                            0x3000
+#define D18F3xE8_MultVidPlane_OFFSET                            14
+#define D18F3xE8_MultVidPlane_WIDTH                             1
+#define D18F3xE8_MultVidPlane_MASK                              0x4000
+#define D18F3xE8_Reserved_15_15_OFFSET                          15
+#define D18F3xE8_Reserved_15_15_WIDTH                           1
+#define D18F3xE8_Reserved_15_15_MASK                            0x8000
+#define D18F3xE8_Reserved_18_16_OFFSET                          16
+#define D18F3xE8_Reserved_18_16_WIDTH                           3
+#define D18F3xE8_Reserved_18_16_MASK                            0x70000
+#define D18F3xE8_x2Apic_OFFSET                                  19
+#define D18F3xE8_x2Apic_WIDTH                                   1
+#define D18F3xE8_x2Apic_MASK                                    0x80000
+#define D18F3xE8_Reserved_23_20_OFFSET                          20
+#define D18F3xE8_Reserved_23_20_WIDTH                           4
+#define D18F3xE8_Reserved_23_20_MASK                            0xf00000
+#define D18F3xE8_MemPstateCap_OFFSET                            24
+#define D18F3xE8_MemPstateCap_WIDTH                             1
+#define D18F3xE8_MemPstateCap_MASK                              0x1000000
+#define D18F3xE8_L3Capable_OFFSET                               25
+#define D18F3xE8_L3Capable_WIDTH                                1
+#define D18F3xE8_L3Capable_MASK                                 0x2000000
+#define D18F3xE8_Reserved_28_26_OFFSET                          26
+#define D18F3xE8_Reserved_28_26_WIDTH                           3
+#define D18F3xE8_Reserved_28_26_MASK                            0x1c000000
+#define D18F3xE8_Reserved_31_29_OFFSET                          29
+#define D18F3xE8_Reserved_31_29_WIDTH                           3
+#define D18F3xE8_Reserved_31_29_MASK                            0xe0000000
+
+/// D18F3xE8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                 DualNode:1 ; ///<
+    UINT32                                                EightNode:1 ; ///<
+    UINT32                                                      ECC:1 ; ///<
+    UINT32                                                 ChipKill:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                   MctCap:1 ; ///<
+    UINT32                                               SvmCapable:1 ; ///<
+    UINT32                                               HtcCapable:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                           Reserved_13_12:2 ; ///<
+    UINT32                                             MultVidPlane:1 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                                   x2Apic:1 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                             MemPstateCap:1 ; ///<
+    UINT32                                                L3Capable:1 ; ///<
+    UINT32                                           Reserved_28_26:3 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xE8_STRUCT;
+
+// **** D18F3xFC Register Definition ****
+// Address
+#define D18F3xFC_ADDRESS                                        0xfc
+
+// Type
+#define D18F3xFC_TYPE                                           TYPE_D18F3
+// Field Data
+#define D18F3xFC_Stepping_OFFSET                                0
+#define D18F3xFC_Stepping_WIDTH                                 4
+#define D18F3xFC_Stepping_MASK                                  0xf
+#define D18F3xFC_BaseModel_OFFSET                               4
+#define D18F3xFC_BaseModel_WIDTH                                4
+#define D18F3xFC_BaseModel_MASK                                 0xf0
+#define D18F3xFC_BaseFamily_OFFSET                              8
+#define D18F3xFC_BaseFamily_WIDTH                               4
+#define D18F3xFC_BaseFamily_MASK                                0xf00
+#define D18F3xFC_Reserved_15_12_OFFSET                          12
+#define D18F3xFC_Reserved_15_12_WIDTH                           4
+#define D18F3xFC_Reserved_15_12_MASK                            0xf000
+#define D18F3xFC_ExtModel_OFFSET                                16
+#define D18F3xFC_ExtModel_WIDTH                                 4
+#define D18F3xFC_ExtModel_MASK                                  0xf0000
+#define D18F3xFC_ExtFamily_OFFSET                               20
+#define D18F3xFC_ExtFamily_WIDTH                                8
+#define D18F3xFC_ExtFamily_MASK                                 0xff00000
+#define D18F3xFC_Reserved_31_28_OFFSET                          28
+#define D18F3xFC_Reserved_31_28_WIDTH                           4
+#define D18F3xFC_Reserved_31_28_MASK                            0xf0000000
+
+/// D18F3xFC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Stepping:4 ; ///<
+    UINT32                                                BaseModel:4 ; ///<
+    UINT32                                               BaseFamily:4 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                 ExtModel:4 ; ///<
+    UINT32                                                ExtFamily:8 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3xFC_STRUCT;
+
+// **** D18F3x140 Register Definition ****
+// Address
+#define D18F3x140_ADDRESS                                       0x140
+
+// Type
+#define D18F3x140_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x140_UpReqTok_OFFSET                               0
+#define D18F3x140_UpReqTok_WIDTH                                2
+#define D18F3x140_UpReqTok_MASK                                 0x3
+#define D18F3x140_DnReqTok_OFFSET                               2
+#define D18F3x140_DnReqTok_WIDTH                                2
+#define D18F3x140_DnReqTok_MASK                                 0xc
+#define D18F3x140_UpPreqTok_OFFSET                              4
+#define D18F3x140_UpPreqTok_WIDTH                               2
+#define D18F3x140_UpPreqTok_MASK                                0x30
+#define D18F3x140_DnPreqTok_OFFSET                              6
+#define D18F3x140_DnPreqTok_WIDTH                               2
+#define D18F3x140_DnPreqTok_MASK                                0xc0
+#define D18F3x140_UpRspTok_OFFSET                               8
+#define D18F3x140_UpRspTok_WIDTH                                2
+#define D18F3x140_UpRspTok_MASK                                 0x300
+#define D18F3x140_DnRspTok_OFFSET                               10
+#define D18F3x140_DnRspTok_WIDTH                                2
+#define D18F3x140_DnRspTok_MASK                                 0xc00
+#define D18F3x140_IsocReqTok_OFFSET                             12
+#define D18F3x140_IsocReqTok_WIDTH                              2
+#define D18F3x140_IsocReqTok_MASK                               0x3000
+#define D18F3x140_IsocPreqTok_OFFSET                            14
+#define D18F3x140_IsocPreqTok_WIDTH                             2
+#define D18F3x140_IsocPreqTok_MASK                              0xc000
+#define D18F3x140_IsocRspTok_OFFSET                             16
+#define D18F3x140_IsocRspTok_WIDTH                              2
+#define D18F3x140_IsocRspTok_MASK                               0x30000
+#define D18F3x140_Reserved_19_18_OFFSET                         18
+#define D18F3x140_Reserved_19_18_WIDTH                          2
+#define D18F3x140_Reserved_19_18_MASK                           0xc0000
+#define D18F3x140_FreeTok_OFFSET                                20
+#define D18F3x140_FreeTok_WIDTH                                 4
+#define D18F3x140_FreeTok_MASK                                  0xf00000
+#define D18F3x140_Reserved_31_24_OFFSET                         24
+#define D18F3x140_Reserved_31_24_WIDTH                          8
+#define D18F3x140_Reserved_31_24_MASK                           0xff000000
+
+/// D18F3x140
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 UpReqTok:2 ; ///<
+    UINT32                                                 DnReqTok:2 ; ///<
+    UINT32                                                UpPreqTok:2 ; ///<
+    UINT32                                                DnPreqTok:2 ; ///<
+    UINT32                                                 UpRspTok:2 ; ///<
+    UINT32                                                 DnRspTok:2 ; ///<
+    UINT32                                               IsocReqTok:2 ; ///<
+    UINT32                                              IsocPreqTok:2 ; ///<
+    UINT32                                               IsocRspTok:2 ; ///<
+    UINT32                                           Reserved_19_18:2 ; ///<
+    UINT32                                                  FreeTok:4 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x140_STRUCT;
+
+// **** D18F3x144 Register Definition ****
+// Address
+#define D18F3x144_ADDRESS                                       0x144
+
+// Type
+#define D18F3x144_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x144_RspTok_OFFSET                                 0
+#define D18F3x144_RspTok_WIDTH                                  4
+#define D18F3x144_RspTok_MASK                                   0xf
+#define D18F3x144_ProbeTok_OFFSET                               4
+#define D18F3x144_ProbeTok_WIDTH                                4
+#define D18F3x144_ProbeTok_MASK                                 0xf0
+#define D18F3x144_Reserved_31_8_OFFSET                          8
+#define D18F3x144_Reserved_31_8_WIDTH                           24
+#define D18F3x144_Reserved_31_8_MASK                            0xffffff00
+
+/// D18F3x144
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   RspTok:4 ; ///<
+    UINT32                                                 ProbeTok:4 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x144_STRUCT;
+
+// **** D18F3x148 Register Definition ****
+// Address
+#define D18F3x148_ADDRESS                                       0x148
+
+// Type
+#define D18F3x148_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x148_ReqTok0_OFFSET                                0
+#define D18F3x148_ReqTok0_WIDTH                                 2
+#define D18F3x148_ReqTok0_MASK                                  0x3
+#define D18F3x148_PReqTok0_OFFSET                               2
+#define D18F3x148_PReqTok0_WIDTH                                2
+#define D18F3x148_PReqTok0_MASK                                 0xc
+#define D18F3x148_RspTok0_OFFSET                                4
+#define D18F3x148_RspTok0_WIDTH                                 2
+#define D18F3x148_RspTok0_MASK                                  0x30
+#define D18F3x148_ProbeTok0_OFFSET                              6
+#define D18F3x148_ProbeTok0_WIDTH                               2
+#define D18F3x148_ProbeTok0_MASK                                0xc0
+#define D18F3x148_IsocReqTok0_OFFSET                            8
+#define D18F3x148_IsocReqTok0_WIDTH                             2
+#define D18F3x148_IsocReqTok0_MASK                              0x300
+#define D18F3x148_IsocPreqTok0_OFFSET                           10
+#define D18F3x148_IsocPreqTok0_WIDTH                            2
+#define D18F3x148_IsocPreqTok0_MASK                             0xc00
+#define D18F3x148_IsocRspTok0_OFFSET                            12
+#define D18F3x148_IsocRspTok0_WIDTH                             2
+#define D18F3x148_IsocRspTok0_MASK                              0x3000
+#define D18F3x148_FreeTok_1_0__OFFSET                           14
+#define D18F3x148_FreeTok_1_0__WIDTH                            2
+#define D18F3x148_FreeTok_1_0__MASK                             0xc000
+#define D18F3x148_ReqTok1_OFFSET                                16
+#define D18F3x148_ReqTok1_WIDTH                                 2
+#define D18F3x148_ReqTok1_MASK                                  0x30000
+#define D18F3x148_PReqTok1_OFFSET                               18
+#define D18F3x148_PReqTok1_WIDTH                                2
+#define D18F3x148_PReqTok1_MASK                                 0xc0000
+#define D18F3x148_RspTok1_OFFSET                                20
+#define D18F3x148_RspTok1_WIDTH                                 2
+#define D18F3x148_RspTok1_MASK                                  0x300000
+#define D18F3x148_ProbeTok1_OFFSET                              22
+#define D18F3x148_ProbeTok1_WIDTH                               2
+#define D18F3x148_ProbeTok1_MASK                                0xc00000
+#define D18F3x148_IsocReqTok1_OFFSET                            24
+#define D18F3x148_IsocReqTok1_WIDTH                             1
+#define D18F3x148_IsocReqTok1_MASK                              0x1000000
+#define D18F3x148_Reserved_25_25_OFFSET                         25
+#define D18F3x148_Reserved_25_25_WIDTH                          1
+#define D18F3x148_Reserved_25_25_MASK                           0x2000000
+#define D18F3x148_IsocPreqTok1_OFFSET                           26
+#define D18F3x148_IsocPreqTok1_WIDTH                            1
+#define D18F3x148_IsocPreqTok1_MASK                             0x4000000
+#define D18F3x148_Reserved_27_27_OFFSET                         27
+#define D18F3x148_Reserved_27_27_WIDTH                          1
+#define D18F3x148_Reserved_27_27_MASK                           0x8000000
+#define D18F3x148_IsocRspTok1_OFFSET                            28
+#define D18F3x148_IsocRspTok1_WIDTH                             1
+#define D18F3x148_IsocRspTok1_MASK                              0x10000000
+#define D18F3x148_Reserved_29_29_OFFSET                         29
+#define D18F3x148_Reserved_29_29_WIDTH                          1
+#define D18F3x148_Reserved_29_29_MASK                           0x20000000
+#define D18F3x148_FreeTok_3_2__OFFSET                           30
+#define D18F3x148_FreeTok_3_2__WIDTH                            2
+#define D18F3x148_FreeTok_3_2__MASK                             0xc0000000
+
+/// D18F3x148
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  ReqTok0:2 ; ///<
+    UINT32                                                 PReqTok0:2 ; ///<
+    UINT32                                                  RspTok0:2 ; ///<
+    UINT32                                                ProbeTok0:2 ; ///<
+    UINT32                                              IsocReqTok0:2 ; ///<
+    UINT32                                             IsocPreqTok0:2 ; ///<
+    UINT32                                              IsocRspTok0:2 ; ///<
+    UINT32                                             FreeTok_1_0_:2 ; ///<
+    UINT32                                                  ReqTok1:2 ; ///<
+    UINT32                                                 PReqTok1:2 ; ///<
+    UINT32                                                  RspTok1:2 ; ///<
+    UINT32                                                ProbeTok1:2 ; ///<
+    UINT32                                              IsocReqTok1:1 ; ///<
+    UINT32                                           Reserved_25_25:1 ; ///<
+    UINT32                                             IsocPreqTok1:1 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                              IsocRspTok1:1 ; ///<
+    UINT32                                           Reserved_29_29:1 ; ///<
+    UINT32                                             FreeTok_3_2_:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x148_STRUCT;
+
+// **** D18F3x17C Register Definition ****
+// Address
+#define D18F3x17C_ADDRESS                                       0x17c
+
+// Type
+#define D18F3x17C_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x17C_SPQPrbFreeCBC_OFFSET                          0
+#define D18F3x17C_SPQPrbFreeCBC_WIDTH                           4
+#define D18F3x17C_SPQPrbFreeCBC_MASK                            0xf
+#define D18F3x17C_Reserved_31_4_OFFSET                          4
+#define D18F3x17C_Reserved_31_4_WIDTH                           28
+#define D18F3x17C_Reserved_31_4_MASK                            0xfffffff0
+
+/// D18F3x17C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            SPQPrbFreeCBC:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x17C_STRUCT;
+
+// **** D18F3x180 Register Definition ****
+// Address
+#define D18F3x180_ADDRESS                                       0x180
+
+// Type
+#define D18F3x180_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x180_Reserved_1_0_OFFSET                           0
+#define D18F3x180_Reserved_1_0_WIDTH                            2
+#define D18F3x180_Reserved_1_0_MASK                             0x3
+#define D18F3x180_WDTCntSel_3__OFFSET                           2
+#define D18F3x180_WDTCntSel_3__WIDTH                            1
+#define D18F3x180_WDTCntSel_3__MASK                             0x4
+#define D18F3x180_ChgDatErrToTgtAbort_OFFSET                    3
+#define D18F3x180_ChgDatErrToTgtAbort_WIDTH                     1
+#define D18F3x180_ChgDatErrToTgtAbort_MASK                      0x8
+#define D18F3x180_ChgMstAbortToNoErr_OFFSET                     4
+#define D18F3x180_ChgMstAbortToNoErr_WIDTH                      1
+#define D18F3x180_ChgMstAbortToNoErr_MASK                       0x10
+#define D18F3x180_DisPciCfgCpuMstAbortRsp_OFFSET                5
+#define D18F3x180_DisPciCfgCpuMstAbortRsp_WIDTH                 1
+#define D18F3x180_DisPciCfgCpuMstAbortRsp_MASK                  0x20
+#define D18F3x180_SyncFloodOnDatErr_OFFSET                      6
+#define D18F3x180_SyncFloodOnDatErr_WIDTH                       1
+#define D18F3x180_SyncFloodOnDatErr_MASK                        0x40
+#define D18F3x180_SyncFloodOnTgtAbortErr_OFFSET                 7
+#define D18F3x180_SyncFloodOnTgtAbortErr_WIDTH                  1
+#define D18F3x180_SyncFloodOnTgtAbortErr_MASK                   0x80
+#define D18F3x180_PwP2pDatErrLclPropDis_OFFSET                  18
+#define D18F3x180_PwP2pDatErrLclPropDis_WIDTH                   1
+#define D18F3x180_PwP2pDatErrLclPropDis_MASK                    0x40000
+#define D18F3x180_PwP2pDatErrRmtPropDis_OFFSET                  19
+#define D18F3x180_PwP2pDatErrRmtPropDis_WIDTH                   1
+#define D18F3x180_PwP2pDatErrRmtPropDis_MASK                    0x80000
+#define D18F3x180_SyncFloodOnL3LeakErr_OFFSET                   20
+#define D18F3x180_SyncFloodOnL3LeakErr_WIDTH                    1
+#define D18F3x180_SyncFloodOnL3LeakErr_MASK                     0x100000
+#define D18F3x180_SyncFloodOnCpuLeakErr_OFFSET                  21
+#define D18F3x180_SyncFloodOnCpuLeakErr_WIDTH                   1
+#define D18F3x180_SyncFloodOnCpuLeakErr_MASK                    0x200000
+#define D18F3x180_SyncFloodOnTblWalkErr_OFFSET                  22
+#define D18F3x180_SyncFloodOnTblWalkErr_WIDTH                   1
+#define D18F3x180_SyncFloodOnTblWalkErr_MASK                    0x400000
+#define D18F3x180_Reserved_23_23_OFFSET                         23
+#define D18F3x180_Reserved_23_23_WIDTH                          1
+#define D18F3x180_Reserved_23_23_MASK                           0x800000
+#define D18F3x180_McaLogErrAddrWdtErr_OFFSET                    24
+#define D18F3x180_McaLogErrAddrWdtErr_WIDTH                     1
+#define D18F3x180_McaLogErrAddrWdtErr_MASK                      0x1000000
+#define D18F3x180_Reserved_25_25_OFFSET                         25
+#define D18F3x180_Reserved_25_25_WIDTH                          1
+#define D18F3x180_Reserved_25_25_MASK                           0x2000000
+#define D18F3x180_ChgUcToCeEn_OFFSET                            26
+#define D18F3x180_ChgUcToCeEn_WIDTH                             1
+#define D18F3x180_ChgUcToCeEn_MASK                              0x4000000
+#define D18F3x180_Reserved_31_27_OFFSET                         27
+#define D18F3x180_Reserved_31_27_WIDTH                          5
+#define D18F3x180_Reserved_31_27_MASK                           0xf8000000
+
+/// D18F3x180
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                             WDTCntSel_3_:1 ; ///<
+    UINT32                                      ChgDatErrToTgtAbort:1 ; ///<
+    UINT32                                       ChgMstAbortToNoErr:1 ; ///<
+    UINT32                                  DisPciCfgCpuMstAbortRsp:1 ; ///<
+    UINT32                                        SyncFloodOnDatErr:1 ; ///<
+    UINT32                                   SyncFloodOnTgtAbortErr:1 ; ///<
+    UINT32                                      :1 ; ///<
+    UINT32                                     :1 ; ///<
+    UINT32                                             :1 ; ///<
+    UINT32                                           :7 ; ///<
+    UINT32                                    PwP2pDatErrLclPropDis:1 ; ///<
+    UINT32                                    PwP2pDatErrRmtPropDis:1 ; ///<
+    UINT32                                     SyncFloodOnL3LeakErr:1 ; ///<
+    UINT32                                    SyncFloodOnCpuLeakErr:1 ; ///<
+    UINT32                                    SyncFloodOnTblWalkErr:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                      McaLogErrAddrWdtErr:1 ; ///<
+    UINT32                                           Reserved_25_25:1 ; ///<
+    UINT32                                              ChgUcToCeEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x180_STRUCT;
+
+// **** D18F3x190 Register Definition ****
+// Address
+#define D18F3x190_ADDRESS                                       0x190
+
+// Type
+#define D18F3x190_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x190_DisCore_OFFSET                                0
+#define D18F3x190_DisCore_WIDTH                                 32
+#define D18F3x190_DisCore_MASK                                  0xffffffff
+
+/// D18F3x190
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  DisCore:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x190_STRUCT;
+
+// **** D18F3x1A0 Register Definition ****
+// Address
+#define D18F3x1A0_ADDRESS                                       0x1a0
+
+// Type
+#define D18F3x1A0_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1A0_CpuCmdBufCnt_OFFSET                           0
+#define D18F3x1A0_CpuCmdBufCnt_WIDTH                            3
+#define D18F3x1A0_CpuCmdBufCnt_MASK                             0x7
+#define D18F3x1A0_Reserved_3_3_OFFSET                           3
+#define D18F3x1A0_Reserved_3_3_WIDTH                            1
+#define D18F3x1A0_Reserved_3_3_MASK                             0x8
+#define D18F3x1A0_Reserved_8_4_OFFSET                           4
+#define D18F3x1A0_Reserved_8_4_WIDTH                            5
+#define D18F3x1A0_Reserved_8_4_MASK                             0x1f0
+#define D18F3x1A0_Reserved_11_9_OFFSET                          9
+#define D18F3x1A0_Reserved_11_9_WIDTH                           3
+#define D18F3x1A0_Reserved_11_9_MASK                            0xe00
+#define D18F3x1A0_Reserved_14_12_OFFSET                         12
+#define D18F3x1A0_Reserved_14_12_WIDTH                          3
+#define D18F3x1A0_Reserved_14_12_MASK                           0x7000
+#define D18F3x1A0_Reserved_15_15_OFFSET                         15
+#define D18F3x1A0_Reserved_15_15_WIDTH                          1
+#define D18F3x1A0_Reserved_15_15_MASK                           0x8000
+#define D18F3x1A0_CpuToNbFreeBufCnt_OFFSET                      16
+#define D18F3x1A0_CpuToNbFreeBufCnt_WIDTH                       2
+#define D18F3x1A0_CpuToNbFreeBufCnt_MASK                        0x30000
+#define D18F3x1A0_Reserved_31_18_OFFSET                         18
+#define D18F3x1A0_Reserved_31_18_WIDTH                          14
+#define D18F3x1A0_Reserved_31_18_MASK                           0xfffc0000
+
+/// D18F3x1A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CpuCmdBufCnt:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                             Reserved_8_4:5 ; ///<
+    UINT32                                            Reserved_11_9:3 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        CpuToNbFreeBufCnt:2 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1A0_STRUCT;
+
+// **** D18F3x1CC Register Definition ****
+// Address
+#define D18F3x1CC_ADDRESS                                       0x1cc
+
+// Type
+#define D18F3x1CC_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1CC_LvtOffset_OFFSET                              0
+#define D18F3x1CC_LvtOffset_WIDTH                               4
+#define D18F3x1CC_LvtOffset_MASK                                0xf
+#define D18F3x1CC_Reserved_7_4_OFFSET                           4
+#define D18F3x1CC_Reserved_7_4_WIDTH                            4
+#define D18F3x1CC_Reserved_7_4_MASK                             0xf0
+#define D18F3x1CC_LvtOffsetVal_OFFSET                           8
+#define D18F3x1CC_LvtOffsetVal_WIDTH                            1
+#define D18F3x1CC_LvtOffsetVal_MASK                             0x100
+#define D18F3x1CC_Reserved_31_9_OFFSET                          9
+#define D18F3x1CC_Reserved_31_9_WIDTH                           23
+#define D18F3x1CC_Reserved_31_9_MASK                            0xfffffe00
+
+/// D18F3x1CC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LvtOffset:4 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                             LvtOffsetVal:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1CC_STRUCT;
+
+
+// **** D18F3x1FC Register Definition ****
+// Address
+#define D18F3x1FC_ADDRESS                                       0x1fc
+
+// Type
+#define D18F3x1FC_TYPE                                          TYPE_D18F3
+// Field Data
+#define D18F3x1FC_DiDtMode_OFFSET                               0
+#define D18F3x1FC_DiDtMode_WIDTH                                1
+#define D18F3x1FC_DiDtMode_MASK                                 0x1
+#define D18F3x1FC_DiDtCfg0_OFFSET                               1
+#define D18F3x1FC_DiDtCfg0_WIDTH                                5
+#define D18F3x1FC_DiDtCfg0_MASK                                 0x3e
+#define D18F3x1FC_DiDtCfg1_OFFSET                               6
+#define D18F3x1FC_DiDtCfg1_WIDTH                                8
+#define D18F3x1FC_DiDtCfg1_MASK                                 0x3fc0
+#define D18F3x1FC_DiDtCfg2_OFFSET                               14
+#define D18F3x1FC_DiDtCfg2_WIDTH                                2
+#define D18F3x1FC_DiDtCfg2_MASK                                 0xc000
+#define D18F3x1FC_Reserved_16_16_OFFSET                         16
+#define D18F3x1FC_Reserved_16_16_WIDTH                          1
+#define D18F3x1FC_Reserved_16_16_MASK                           0x10000
+#define D18F3x1FC_DiDtCfg4_OFFSET                               17
+#define D18F3x1FC_DiDtCfg4_WIDTH                                3
+#define D18F3x1FC_DiDtCfg4_MASK                                 0xe0000
+#define D18F3x1FC_Reserved_23_20_OFFSET                         20
+#define D18F3x1FC_Reserved_23_20_WIDTH                          4
+#define D18F3x1FC_Reserved_23_20_MASK                           0xf00000
+#define D18F3x1FC_SWDllCapTableEn_OFFSET                        24
+#define D18F3x1FC_SWDllCapTableEn_WIDTH                         1
+#define D18F3x1FC_SWDllCapTableEn_MASK                          0x1000000
+#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_OFFSET             25
+#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_WIDTH              4
+#define D18F3x1FC_DllProcFreqCtlIndex2Rate50_MASK               0x1e000000
+
+/// D18F3x1FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 DiDtMode:1 ; ///<
+    UINT32                                                 DiDtCfg0:5 ; ///<
+    UINT32                                                 DiDtCfg1:8 ; ///<
+    UINT32                                                 DiDtCfg2:2 ; ///<
+    UINT32                                           Reserved_16_16:1 ; ///<
+    UINT32                                                 DiDtCfg4:3 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                          SWDllCapTableEn:1 ; ///<
+    UINT32                               DllProcFreqCtlIndex2Rate50:4 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F3x1FC_STRUCT;
+
+// **** D18F4x00 Register Definition ****
+// Address
+#define D18F4x00_ADDRESS                                        0x0
+
+// Type
+#define D18F4x00_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x00_VendorID_OFFSET                                0
+#define D18F4x00_VendorID_WIDTH                                 16
+#define D18F4x00_VendorID_MASK                                  0xffff
+#define D18F4x00_DeviceID_OFFSET                                16
+#define D18F4x00_DeviceID_WIDTH                                 16
+#define D18F4x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F4x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x00_STRUCT;
+
+// **** D18F4x04 Register Definition ****
+// Address
+#define D18F4x04_ADDRESS                                        0x4
+
+// Type
+#define D18F4x04_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x04_Command_OFFSET                                 0
+#define D18F4x04_Command_WIDTH                                  16
+#define D18F4x04_Command_MASK                                   0xffff
+#define D18F4x04_Status_OFFSET                                  16
+#define D18F4x04_Status_WIDTH                                   16
+#define D18F4x04_Status_MASK                                    0xffff0000
+
+/// D18F4x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x04_STRUCT;
+
+// **** D18F4x08 Register Definition ****
+// Address
+#define D18F4x08_ADDRESS                                        0x8
+
+// Type
+#define D18F4x08_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x08_RevID_OFFSET                                   0
+#define D18F4x08_RevID_WIDTH                                    8
+#define D18F4x08_RevID_MASK                                     0xff
+#define D18F4x08_ClassCode_OFFSET                               8
+#define D18F4x08_ClassCode_WIDTH                                24
+#define D18F4x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F4x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x08_STRUCT;
+
+// **** D18F4x0C Register Definition ****
+// Address
+#define D18F4x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F4x0C_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x0C_HeaderTypeReg_OFFSET                           0
+#define D18F4x0C_HeaderTypeReg_WIDTH                            32
+#define D18F4x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F4x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x0C_STRUCT;
+
+// **** D18F4x34 Register Definition ****
+// Address
+#define D18F4x34_ADDRESS                                        0x34
+
+// Type
+#define D18F4x34_TYPE                                           TYPE_D18F4
+// Field Data
+#define D18F4x34_CapPtr_OFFSET                                  0
+#define D18F4x34_CapPtr_WIDTH                                   8
+#define D18F4x34_CapPtr_MASK                                    0xff
+#define D18F4x34_Reserved_31_8_OFFSET                           8
+#define D18F4x34_Reserved_31_8_WIDTH                            24
+#define D18F4x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F4x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x34_STRUCT;
+
+// **** D18F4x108 Register Definition ****
+// Address
+#define D18F4x108_ADDRESS                                       0x108
+
+// Type
+#define D18F4x108_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x108_Reserved_31_0_OFFSET                          0
+#define D18F4x108_Reserved_31_0_WIDTH                           32
+#define D18F4x108_Reserved_31_0_MASK                            0xffffffff
+
+/// D18F4x108
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x108_STRUCT;
+
+// **** D18F4x10C Register Definition ****
+// Address
+#define D18F4x10C_ADDRESS                                       0x10c
+
+// Type
+#define D18F4x10C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x10C_NodeTdpLimit_OFFSET                           0
+#define D18F4x10C_NodeTdpLimit_WIDTH                            12
+#define D18F4x10C_NodeTdpLimit_MASK                             0xfff
+#define D18F4x10C_Reserved_31_12_OFFSET                         12
+#define D18F4x10C_Reserved_31_12_WIDTH                          20
+#define D18F4x10C_Reserved_31_12_MASK                           0xfffff000
+
+/// D18F4x10C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NodeTdpLimit:12; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x10C_STRUCT;
+
+// **** D18F4x110 Register Definition ****
+// Address
+#define D18F4x110_ADDRESS                                       0x110
+
+// Type
+#define D18F4x110_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x110_CSampleTimer_OFFSET                           0
+#define D18F4x110_CSampleTimer_WIDTH                            12
+#define D18F4x110_CSampleTimer_MASK                             0xfff
+#define D18F4x110_Reserved_12_12_OFFSET                         12
+#define D18F4x110_Reserved_12_12_WIDTH                          1
+#define D18F4x110_Reserved_12_12_MASK                           0x1000
+#define D18F4x110_MinResTmr_OFFSET                              13
+#define D18F4x110_MinResTmr_WIDTH                               8
+#define D18F4x110_MinResTmr_MASK                                0x1fe000
+#define D18F4x110_Reserved_31_21_OFFSET                         21
+#define D18F4x110_Reserved_31_21_WIDTH                          11
+#define D18F4x110_Reserved_31_21_MASK                           0xffe00000
+
+/// D18F4x110
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CSampleTimer:12; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                                MinResTmr:8 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x110_STRUCT;
+
+// **** D18F4x118 Register Definition ****
+// Address
+#define D18F4x118_ADDRESS                                       0x118
+
+// Type
+#define D18F4x118_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x118_CpuPrbEnCstAct0_OFFSET                        0
+#define D18F4x118_CpuPrbEnCstAct0_WIDTH                         1
+#define D18F4x118_CpuPrbEnCstAct0_MASK                          0x1
+#define D18F4x118_CacheFlushEnCstAct0_OFFSET                    1
+#define D18F4x118_CacheFlushEnCstAct0_WIDTH                     1
+#define D18F4x118_CacheFlushEnCstAct0_MASK                      0x2
+#define D18F4x118_CacheFlushTmrSelCstAct0_OFFSET                2
+#define D18F4x118_CacheFlushTmrSelCstAct0_WIDTH                 2
+#define D18F4x118_CacheFlushTmrSelCstAct0_MASK                  0xc
+#define D18F4x118_Reserved_4_4_OFFSET                           4
+#define D18F4x118_Reserved_4_4_WIDTH                            1
+#define D18F4x118_Reserved_4_4_MASK                             0x10
+#define D18F4x118_ClkDivisorCstAct0_OFFSET                      5
+#define D18F4x118_ClkDivisorCstAct0_WIDTH                       3
+#define D18F4x118_ClkDivisorCstAct0_MASK                        0xe0
+#define D18F4x118_PwrGateEnCstAct0_OFFSET                       8
+#define D18F4x118_PwrGateEnCstAct0_WIDTH                        1
+#define D18F4x118_PwrGateEnCstAct0_MASK                         0x100
+#define D18F4x118_PwrOffEnCstAct0_OFFSET                        9
+#define D18F4x118_PwrOffEnCstAct0_WIDTH                         1
+#define D18F4x118_PwrOffEnCstAct0_MASK                          0x200
+#define D18F4x118_NbPwrGate0_OFFSET                             10
+#define D18F4x118_NbPwrGate0_WIDTH                              1
+#define D18F4x118_NbPwrGate0_MASK                               0x400
+#define D18F4x118_NbClkGate0_OFFSET                             11
+#define D18F4x118_NbClkGate0_WIDTH                              1
+#define D18F4x118_NbClkGate0_MASK                               0x800
+#define D18F4x118_SelfRefr0_OFFSET                              12
+#define D18F4x118_SelfRefr0_WIDTH                               1
+#define D18F4x118_SelfRefr0_MASK                                0x1000
+#define D18F4x118_SelfRefrEarly0_OFFSET                         13
+#define D18F4x118_SelfRefrEarly0_WIDTH                          1
+#define D18F4x118_SelfRefrEarly0_MASK                           0x2000
+#define D18F4x118_Reserved_15_14_OFFSET                         14
+#define D18F4x118_Reserved_15_14_WIDTH                          2
+#define D18F4x118_Reserved_15_14_MASK                           0xc000
+#define D18F4x118_CpuPrbEnCstAct1_OFFSET                        16
+#define D18F4x118_CpuPrbEnCstAct1_WIDTH                         1
+#define D18F4x118_CpuPrbEnCstAct1_MASK                          0x10000
+#define D18F4x118_CacheFlushEnCstAct1_OFFSET                    17
+#define D18F4x118_CacheFlushEnCstAct1_WIDTH                     1
+#define D18F4x118_CacheFlushEnCstAct1_MASK                      0x20000
+#define D18F4x118_CacheFlushTmrSelCstAct1_OFFSET                18
+#define D18F4x118_CacheFlushTmrSelCstAct1_WIDTH                 2
+#define D18F4x118_CacheFlushTmrSelCstAct1_MASK                  0xc0000
+#define D18F4x118_Reserved_20_20_OFFSET                         20
+#define D18F4x118_Reserved_20_20_WIDTH                          1
+#define D18F4x118_Reserved_20_20_MASK                           0x100000
+#define D18F4x118_ClkDivisorCstAct1_OFFSET                      21
+#define D18F4x118_ClkDivisorCstAct1_WIDTH                       3
+#define D18F4x118_ClkDivisorCstAct1_MASK                        0xe00000
+#define D18F4x118_PwrGateEnCstAct1_OFFSET                       24
+#define D18F4x118_PwrGateEnCstAct1_WIDTH                        1
+#define D18F4x118_PwrGateEnCstAct1_MASK                         0x1000000
+#define D18F4x118_PwrOffEnCstAct1_OFFSET                        25
+#define D18F4x118_PwrOffEnCstAct1_WIDTH                         1
+#define D18F4x118_PwrOffEnCstAct1_MASK                          0x2000000
+#define D18F4x118_NbPwrGate1_OFFSET                             26
+#define D18F4x118_NbPwrGate1_WIDTH                              1
+#define D18F4x118_NbPwrGate1_MASK                               0x4000000
+#define D18F4x118_NbClkGate1_OFFSET                             27
+#define D18F4x118_NbClkGate1_WIDTH                              1
+#define D18F4x118_NbClkGate1_MASK                               0x8000000
+#define D18F4x118_SelfRefr1_OFFSET                              28
+#define D18F4x118_SelfRefr1_WIDTH                               1
+#define D18F4x118_SelfRefr1_MASK                                0x10000000
+#define D18F4x118_SelfRefrEarly1_OFFSET                         29
+#define D18F4x118_SelfRefrEarly1_WIDTH                          1
+#define D18F4x118_SelfRefrEarly1_MASK                           0x20000000
+#define D18F4x118_Reserved_31_30_OFFSET                         30
+#define D18F4x118_Reserved_31_30_WIDTH                          2
+#define D18F4x118_Reserved_31_30_MASK                           0xc0000000
+
+/// D18F4x118
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CpuPrbEnCstAct0:1 ; ///<
+    UINT32                                      CacheFlushEnCstAct0:1 ; ///<
+    UINT32                                  CacheFlushTmrSelCstAct0:2 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                        ClkDivisorCstAct0:3 ; ///<
+    UINT32                                         PwrGateEnCstAct0:1 ; ///<
+    UINT32                                          PwrOffEnCstAct0:1 ; ///<
+    UINT32                                               NbPwrGate0:1 ; ///<
+    UINT32                                               NbClkGate0:1 ; ///<
+    UINT32                                                SelfRefr0:1 ; ///<
+    UINT32                                           SelfRefrEarly0:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                          CpuPrbEnCstAct1:1 ; ///<
+    UINT32                                      CacheFlushEnCstAct1:1 ; ///<
+    UINT32                                  CacheFlushTmrSelCstAct1:2 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                        ClkDivisorCstAct1:3 ; ///<
+    UINT32                                         PwrGateEnCstAct1:1 ; ///<
+    UINT32                                          PwrOffEnCstAct1:1 ; ///<
+    UINT32                                               NbPwrGate1:1 ; ///<
+    UINT32                                               NbClkGate1:1 ; ///<
+    UINT32                                                SelfRefr1:1 ; ///<
+    UINT32                                           SelfRefrEarly1:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x118_STRUCT;
+
+// **** D18F4x11C Register Definition ****
+// Address
+#define D18F4x11C_ADDRESS                                       0x11c
+
+// Type
+#define D18F4x11C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x11C_CpuPrbEnCstAct2_OFFSET                        0
+#define D18F4x11C_CpuPrbEnCstAct2_WIDTH                         1
+#define D18F4x11C_CpuPrbEnCstAct2_MASK                          0x1
+#define D18F4x11C_CacheFlushEnCstAct2_OFFSET                    1
+#define D18F4x11C_CacheFlushEnCstAct2_WIDTH                     1
+#define D18F4x11C_CacheFlushEnCstAct2_MASK                      0x2
+#define D18F4x11C_CacheFlushTmrSelCstAct2_OFFSET                2
+#define D18F4x11C_CacheFlushTmrSelCstAct2_WIDTH                 2
+#define D18F4x11C_CacheFlushTmrSelCstAct2_MASK                  0xc
+#define D18F4x11C_Reserved_4_4_OFFSET                           4
+#define D18F4x11C_Reserved_4_4_WIDTH                            1
+#define D18F4x11C_Reserved_4_4_MASK                             0x10
+#define D18F4x11C_ClkDivisorCstAct2_OFFSET                      5
+#define D18F4x11C_ClkDivisorCstAct2_WIDTH                       3
+#define D18F4x11C_ClkDivisorCstAct2_MASK                        0xe0
+#define D18F4x11C_PwrGateEnCstAct2_OFFSET                       8
+#define D18F4x11C_PwrGateEnCstAct2_WIDTH                        1
+#define D18F4x11C_PwrGateEnCstAct2_MASK                         0x100
+#define D18F4x11C_PwrOffEnCstAct2_OFFSET                        9
+#define D18F4x11C_PwrOffEnCstAct2_WIDTH                         1
+#define D18F4x11C_PwrOffEnCstAct2_MASK                          0x200
+#define D18F4x11C_NbPwrGate2_OFFSET                             10
+#define D18F4x11C_NbPwrGate2_WIDTH                              1
+#define D18F4x11C_NbPwrGate2_MASK                               0x400
+#define D18F4x11C_NbClkGate2_OFFSET                             11
+#define D18F4x11C_NbClkGate2_WIDTH                              1
+#define D18F4x11C_NbClkGate2_MASK                               0x800
+#define D18F4x11C_SelfRefr2_OFFSET                              12
+#define D18F4x11C_SelfRefr2_WIDTH                               1
+#define D18F4x11C_SelfRefr2_MASK                                0x1000
+#define D18F4x11C_SelfRefrEarly2_OFFSET                         13
+#define D18F4x11C_SelfRefrEarly2_WIDTH                          1
+#define D18F4x11C_SelfRefrEarly2_MASK                           0x2000
+#define D18F4x11C_Reserved_31_14_OFFSET                         14
+#define D18F4x11C_Reserved_31_14_WIDTH                          18
+#define D18F4x11C_Reserved_31_14_MASK                           0xffffc000
+
+/// D18F4x11C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CpuPrbEnCstAct2:1 ; ///<
+    UINT32                                      CacheFlushEnCstAct2:1 ; ///<
+    UINT32                                  CacheFlushTmrSelCstAct2:2 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                                        ClkDivisorCstAct2:3 ; ///<
+    UINT32                                         PwrGateEnCstAct2:1 ; ///<
+    UINT32                                          PwrOffEnCstAct2:1 ; ///<
+    UINT32                                               NbPwrGate2:1 ; ///<
+    UINT32                                               NbClkGate2:1 ; ///<
+    UINT32                                                SelfRefr2:1 ; ///<
+    UINT32                                           SelfRefrEarly2:1 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x11C_STRUCT;
+
+// **** D18F4x124 Register Definition ****
+// Address
+#define D18F4x124_ADDRESS                                       0x124
+
+// Type
+#define D18F4x124_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x124_Reserved_21_0_OFFSET                          0
+#define D18F4x124_Reserved_21_0_WIDTH                           22
+#define D18F4x124_Reserved_21_0_MASK                            0x3fffff
+#define D18F4x124_IntMonPC6En_OFFSET                            22
+#define D18F4x124_IntMonPC6En_WIDTH                             1
+#define D18F4x124_IntMonPC6En_MASK                              0x400000
+#define D18F4x124_IntMonPC6Limit_OFFSET                         23
+#define D18F4x124_IntMonPC6Limit_WIDTH                          4
+#define D18F4x124_IntMonPC6Limit_MASK                           0x7800000
+#define D18F4x124_Reserved_31_27_OFFSET                         27
+#define D18F4x124_Reserved_31_27_WIDTH                          5
+#define D18F4x124_Reserved_31_27_MASK                           0xf8000000
+
+/// D18F4x124
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_21_0:22; ///<
+    UINT32                                              IntMonPC6En:1 ; ///<
+    UINT32                                           IntMonPC6Limit:4 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x124_STRUCT;
+
+// **** D18F4x128 Register Definition ****
+// Address
+#define D18F4x128_ADDRESS                                       0x128
+
+// Type
+#define D18F4x128_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x128_Reserved_0_0_OFFSET                           0
+#define D18F4x128_Reserved_0_0_WIDTH                            1
+#define D18F4x128_Reserved_0_0_MASK                             0x1
+#define D18F4x128_CoreCstatePolicy_OFFSET                       1
+#define D18F4x128_CoreCstatePolicy_WIDTH                        1
+#define D18F4x128_CoreCstatePolicy_MASK                         0x2
+#define D18F4x128_HaltCstateIndex_OFFSET                        2
+#define D18F4x128_HaltCstateIndex_WIDTH                         3
+#define D18F4x128_HaltCstateIndex_MASK                          0x1c
+#define D18F4x128_CacheFlushTmr_OFFSET                          5
+#define D18F4x128_CacheFlushTmr_WIDTH                           7
+#define D18F4x128_CacheFlushTmr_MASK                            0xfe0
+#define D18F4x128_Reserved_17_12_OFFSET                         12
+#define D18F4x128_Reserved_17_12_WIDTH                          6
+#define D18F4x128_Reserved_17_12_MASK                           0x3f000
+#define D18F4x128_CacheFlushSucMonThreshold_OFFSET              18
+#define D18F4x128_CacheFlushSucMonThreshold_WIDTH               3
+#define D18F4x128_CacheFlushSucMonThreshold_MASK                0x1c0000
+#define D18F4x128_Reserved_30_21_OFFSET                         21
+#define D18F4x128_Reserved_30_21_WIDTH                          10
+#define D18F4x128_Reserved_30_21_MASK                           0x7fe00000
+#define D18F4x128_CstateMsgDis_OFFSET                           31
+#define D18F4x128_CstateMsgDis_WIDTH                            1
+#define D18F4x128_CstateMsgDis_MASK                             0x80000000
+
+/// D18F4x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                         CoreCstatePolicy:1 ; ///<
+    UINT32                                          HaltCstateIndex:3 ; ///<
+    UINT32                                            CacheFlushTmr:7 ; ///<
+    UINT32                                           Reserved_17_12:6 ; ///<
+    UINT32                                CacheFlushSucMonThreshold:3 ; ///<
+    UINT32                                           Reserved_30_21:10; ///<
+    UINT32                                             CstateMsgDis:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x128_STRUCT;
+
+// **** D18F4x13C Register Definition ****
+// Address
+#define D18F4x13C_ADDRESS                                       0x13c
+
+// Type
+#define D18F4x13C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x13C_SmuPstateLimitEn_OFFSET                       0
+#define D18F4x13C_SmuPstateLimitEn_WIDTH                        1
+#define D18F4x13C_SmuPstateLimitEn_MASK                         0x1
+#define D18F4x13C_SmuPstateLimit_OFFSET                         1
+#define D18F4x13C_SmuPstateLimit_WIDTH                          3
+#define D18F4x13C_SmuPstateLimit_MASK                           0xe
+#define D18F4x13C_Reserved_31_4_OFFSET                          4
+#define D18F4x13C_Reserved_31_4_WIDTH                           28
+#define D18F4x13C_Reserved_31_4_MASK                            0xfffffff0
+
+/// D18F4x13C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         SmuPstateLimitEn:1 ; ///<
+    UINT32                                           SmuPstateLimit:3 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x13C_STRUCT;
+
+// **** D18F4x15C Register Definition ****
+// Address
+#define D18F4x15C_ADDRESS                                       0x15c
+
+// Type
+#define D18F4x15C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x15C_BoostSrc_OFFSET                               0
+#define D18F4x15C_BoostSrc_WIDTH                                2
+#define D18F4x15C_BoostSrc_MASK                                 0x3
+#define D18F4x15C_NumBoostStates_OFFSET                         2
+#define D18F4x15C_NumBoostStates_WIDTH                          3
+#define D18F4x15C_NumBoostStates_MASK                           0x1c
+#define D18F4x15C_Reserved_6_5_OFFSET                           5
+#define D18F4x15C_Reserved_6_5_WIDTH                            2
+#define D18F4x15C_Reserved_6_5_MASK                             0x60
+#define D18F4x15C_ApmMasterEn_OFFSET                            7
+#define D18F4x15C_ApmMasterEn_WIDTH                             1
+#define D18F4x15C_ApmMasterEn_MASK                              0x80
+#define D18F4x15C_Reserved_27_8_OFFSET                          8
+#define D18F4x15C_Reserved_27_8_WIDTH                           20
+#define D18F4x15C_Reserved_27_8_MASK                            0xfffff00
+#define D18F4x15C_Reserved_30_28_OFFSET                         28
+#define D18F4x15C_Reserved_30_28_WIDTH                          3
+#define D18F4x15C_Reserved_30_28_MASK                           0x70000000
+#define D18F4x15C_BoostLock_OFFSET                              31
+#define D18F4x15C_BoostLock_WIDTH                               1
+#define D18F4x15C_BoostLock_MASK                                0x80000000
+
+/// D18F4x15C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 BoostSrc:2 ; ///<
+    UINT32                                           NumBoostStates:3 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                              ApmMasterEn:1 ; ///<
+    UINT32                                            Reserved_27_8:20; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                                BoostLock:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x15C_STRUCT;
+
+
+// **** D18F4x164 Register Definition ****
+// Address
+#define D18F4x164_ADDRESS                                       0x164
+
+// Type
+#define D18F4x164_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x164_FixedErrata_OFFSET                            0
+#define D18F4x164_FixedErrata_WIDTH                             32
+#define D18F4x164_FixedErrata_MASK                              0xffffffff
+
+/// D18F4x164
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              FixedErrata:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x164_STRUCT;
+
+// **** D18F4x16C Register Definition ****
+// Address
+#define D18F4x16C_ADDRESS                                       0x16c
+
+// Type
+#define D18F4x16C_TYPE                                          TYPE_D18F4
+// Field Data
+#define D18F4x16C_CstateBoost_OFFSET                            6
+#define D18F4x16C_CstateBoost_WIDTH                             3
+#define D18F4x16C_CstateBoost_MASK                              0x1c0
+#define D18F4x16C_CstateCnt_OFFSET                              9
+#define D18F4x16C_CstateCnt_WIDTH                               3
+#define D18F4x16C_CstateCnt_MASK                                0xe00
+#define D18F4x16C_Reserved_31_12_OFFSET                         12
+#define D18F4x16C_Reserved_31_12_WIDTH                          20
+#define D18F4x16C_Reserved_31_12_MASK                           0xfffff000
+
+/// D18F4x16C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             :6 ; ///<
+    UINT32                                              CstateBoost:3 ; ///<
+    UINT32                                                CstateCnt:3 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F4x16C_STRUCT;
+
+
+// **** D18F5x00 Register Definition ****
+// Address
+#define D18F5x00_ADDRESS                                        0x0
+
+// Type
+#define D18F5x00_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x00_VendorID_OFFSET                                0
+#define D18F5x00_VendorID_WIDTH                                 16
+#define D18F5x00_VendorID_MASK                                  0xffff
+#define D18F5x00_DeviceID_OFFSET                                16
+#define D18F5x00_DeviceID_WIDTH                                 16
+#define D18F5x00_DeviceID_MASK                                  0xffff0000
+
+/// D18F5x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x00_STRUCT;
+
+// **** D18F5x04 Register Definition ****
+// Address
+#define D18F5x04_ADDRESS                                        0x4
+
+// Type
+#define D18F5x04_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x04_Command_OFFSET                                 0
+#define D18F5x04_Command_WIDTH                                  16
+#define D18F5x04_Command_MASK                                   0xffff
+#define D18F5x04_Status_OFFSET                                  16
+#define D18F5x04_Status_WIDTH                                   16
+#define D18F5x04_Status_MASK                                    0xffff0000
+
+/// D18F5x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Command:16; ///<
+    UINT32                                                   Status:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x04_STRUCT;
+
+// **** D18F5x08 Register Definition ****
+// Address
+#define D18F5x08_ADDRESS                                        0x8
+
+// Type
+#define D18F5x08_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x08_RevID_OFFSET                                   0
+#define D18F5x08_RevID_WIDTH                                    8
+#define D18F5x08_RevID_MASK                                     0xff
+#define D18F5x08_ClassCode_OFFSET                               8
+#define D18F5x08_ClassCode_WIDTH                                24
+#define D18F5x08_ClassCode_MASK                                 0xffffff00
+
+/// D18F5x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x08_STRUCT;
+
+// **** D18F5x0C Register Definition ****
+// Address
+#define D18F5x0C_ADDRESS                                        0xc
+
+// Type
+#define D18F5x0C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x0C_HeaderTypeReg_OFFSET                           0
+#define D18F5x0C_HeaderTypeReg_WIDTH                            32
+#define D18F5x0C_HeaderTypeReg_MASK                             0xffffffff
+
+/// D18F5x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            HeaderTypeReg:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x0C_STRUCT;
+
+// **** D18F5x34 Register Definition ****
+// Address
+#define D18F5x34_ADDRESS                                        0x34
+
+// Type
+#define D18F5x34_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x34_CapPtr_OFFSET                                  0
+#define D18F5x34_CapPtr_WIDTH                                   8
+#define D18F5x34_CapPtr_MASK                                    0xff
+#define D18F5x34_Reserved_31_8_OFFSET                           8
+#define D18F5x34_Reserved_31_8_WIDTH                            24
+#define D18F5x34_Reserved_31_8_MASK                             0xffffff00
+
+/// D18F5x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x34_STRUCT;
+
+// **** D18F5x40 Register Definition ****
+// Address
+#define D18F5x40_ADDRESS                                        0x40
+
+// Type
+#define D18F5x40_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x40_EventSelect_7_0__OFFSET                        0
+#define D18F5x40_EventSelect_7_0__WIDTH                         8
+#define D18F5x40_EventSelect_7_0__MASK                          0xff
+#define D18F5x40_UnitMask_OFFSET                                8
+#define D18F5x40_UnitMask_WIDTH                                 8
+#define D18F5x40_UnitMask_MASK                                  0xff00
+#define D18F5x40_Reserved_18_16_OFFSET                          16
+#define D18F5x40_Reserved_18_16_WIDTH                           3
+#define D18F5x40_Reserved_18_16_MASK                            0x70000
+#define D18F5x40_Reserved_19_19_OFFSET                          19
+#define D18F5x40_Reserved_19_19_WIDTH                           1
+#define D18F5x40_Reserved_19_19_MASK                            0x80000
+#define D18F5x40_Int_OFFSET                                     20
+#define D18F5x40_Int_WIDTH                                      1
+#define D18F5x40_Int_MASK                                       0x100000
+#define D18F5x40_Reserved_21_21_OFFSET                          21
+#define D18F5x40_Reserved_21_21_WIDTH                           1
+#define D18F5x40_Reserved_21_21_MASK                            0x200000
+#define D18F5x40_En_OFFSET                                      22
+#define D18F5x40_En_WIDTH                                       1
+#define D18F5x40_En_MASK                                        0x400000
+#define D18F5x40_Reserved_31_23_OFFSET                          23
+#define D18F5x40_Reserved_31_23_WIDTH                           9
+#define D18F5x40_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x40_STRUCT;
+
+// **** D18F5x44 Register Definition ****
+// Address
+#define D18F5x44_ADDRESS                                        0x44
+
+// Type
+#define D18F5x44_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x44_EventSelect_11_8__OFFSET                       0
+#define D18F5x44_EventSelect_11_8__WIDTH                        4
+#define D18F5x44_EventSelect_11_8__MASK                         0xf
+#define D18F5x44_Reserved_63_36_OFFSET                          4
+#define D18F5x44_Reserved_63_36_WIDTH                           28
+#define D18F5x44_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x44_STRUCT;
+
+// **** D18F5x48 Register Definition ****
+// Address
+#define D18F5x48_ADDRESS                                        0x48
+
+// Type
+#define D18F5x48_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x48_CTR_31_0__OFFSET                               0
+#define D18F5x48_CTR_31_0__WIDTH                                32
+#define D18F5x48_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x48_STRUCT;
+
+// **** D18F5x4C Register Definition ****
+// Address
+#define D18F5x4C_ADDRESS                                        0x4c
+
+// Type
+#define D18F5x4C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x4C_CTR_47_32__OFFSET                              0
+#define D18F5x4C_CTR_47_32__WIDTH                               16
+#define D18F5x4C_CTR_47_32__MASK                                0xffff
+#define D18F5x4C_RAZ_63_48_OFFSET                               16
+#define D18F5x4C_RAZ_63_48_WIDTH                                16
+#define D18F5x4C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x4C_STRUCT;
+
+// **** D18F5x50 Register Definition ****
+// Address
+#define D18F5x50_ADDRESS                                        0x50
+
+// Type
+#define D18F5x50_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x50_EventSelect_7_0__OFFSET                        0
+#define D18F5x50_EventSelect_7_0__WIDTH                         8
+#define D18F5x50_EventSelect_7_0__MASK                          0xff
+#define D18F5x50_UnitMask_OFFSET                                8
+#define D18F5x50_UnitMask_WIDTH                                 8
+#define D18F5x50_UnitMask_MASK                                  0xff00
+#define D18F5x50_Reserved_18_16_OFFSET                          16
+#define D18F5x50_Reserved_18_16_WIDTH                           3
+#define D18F5x50_Reserved_18_16_MASK                            0x70000
+#define D18F5x50_Reserved_19_19_OFFSET                          19
+#define D18F5x50_Reserved_19_19_WIDTH                           1
+#define D18F5x50_Reserved_19_19_MASK                            0x80000
+#define D18F5x50_Int_OFFSET                                     20
+#define D18F5x50_Int_WIDTH                                      1
+#define D18F5x50_Int_MASK                                       0x100000
+#define D18F5x50_Reserved_21_21_OFFSET                          21
+#define D18F5x50_Reserved_21_21_WIDTH                           1
+#define D18F5x50_Reserved_21_21_MASK                            0x200000
+#define D18F5x50_En_OFFSET                                      22
+#define D18F5x50_En_WIDTH                                       1
+#define D18F5x50_En_MASK                                        0x400000
+#define D18F5x50_Reserved_31_23_OFFSET                          23
+#define D18F5x50_Reserved_31_23_WIDTH                           9
+#define D18F5x50_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x50_STRUCT;
+
+// **** D18F5x54 Register Definition ****
+// Address
+#define D18F5x54_ADDRESS                                        0x54
+
+// Type
+#define D18F5x54_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x54_EventSelect_11_8__OFFSET                       0
+#define D18F5x54_EventSelect_11_8__WIDTH                        4
+#define D18F5x54_EventSelect_11_8__MASK                         0xf
+#define D18F5x54_Reserved_63_36_OFFSET                          4
+#define D18F5x54_Reserved_63_36_WIDTH                           28
+#define D18F5x54_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x54_STRUCT;
+
+// **** D18F5x58 Register Definition ****
+// Address
+#define D18F5x58_ADDRESS                                        0x58
+
+// Type
+#define D18F5x58_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x58_CTR_31_0__OFFSET                               0
+#define D18F5x58_CTR_31_0__WIDTH                                32
+#define D18F5x58_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x58_STRUCT;
+
+// **** D18F5x5C Register Definition ****
+// Address
+#define D18F5x5C_ADDRESS                                        0x5c
+
+// Type
+#define D18F5x5C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x5C_CTR_47_32__OFFSET                              0
+#define D18F5x5C_CTR_47_32__WIDTH                               16
+#define D18F5x5C_CTR_47_32__MASK                                0xffff
+#define D18F5x5C_RAZ_63_48_OFFSET                               16
+#define D18F5x5C_RAZ_63_48_WIDTH                                16
+#define D18F5x5C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x5C_STRUCT;
+
+// **** D18F5x60 Register Definition ****
+// Address
+#define D18F5x60_ADDRESS                                        0x60
+
+// Type
+#define D18F5x60_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x60_EventSelect_7_0__OFFSET                        0
+#define D18F5x60_EventSelect_7_0__WIDTH                         8
+#define D18F5x60_EventSelect_7_0__MASK                          0xff
+#define D18F5x60_UnitMask_OFFSET                                8
+#define D18F5x60_UnitMask_WIDTH                                 8
+#define D18F5x60_UnitMask_MASK                                  0xff00
+#define D18F5x60_Reserved_18_16_OFFSET                          16
+#define D18F5x60_Reserved_18_16_WIDTH                           3
+#define D18F5x60_Reserved_18_16_MASK                            0x70000
+#define D18F5x60_Reserved_19_19_OFFSET                          19
+#define D18F5x60_Reserved_19_19_WIDTH                           1
+#define D18F5x60_Reserved_19_19_MASK                            0x80000
+#define D18F5x60_Int_OFFSET                                     20
+#define D18F5x60_Int_WIDTH                                      1
+#define D18F5x60_Int_MASK                                       0x100000
+#define D18F5x60_Reserved_21_21_OFFSET                          21
+#define D18F5x60_Reserved_21_21_WIDTH                           1
+#define D18F5x60_Reserved_21_21_MASK                            0x200000
+#define D18F5x60_En_OFFSET                                      22
+#define D18F5x60_En_WIDTH                                       1
+#define D18F5x60_En_MASK                                        0x400000
+#define D18F5x60_Reserved_31_23_OFFSET                          23
+#define D18F5x60_Reserved_31_23_WIDTH                           9
+#define D18F5x60_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x60_STRUCT;
+
+// **** D18F5x64 Register Definition ****
+// Address
+#define D18F5x64_ADDRESS                                        0x64
+
+// Type
+#define D18F5x64_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x64_EventSelect_11_8__OFFSET                       0
+#define D18F5x64_EventSelect_11_8__WIDTH                        4
+#define D18F5x64_EventSelect_11_8__MASK                         0xf
+#define D18F5x64_Reserved_63_36_OFFSET                          4
+#define D18F5x64_Reserved_63_36_WIDTH                           28
+#define D18F5x64_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x64_STRUCT;
+
+// **** D18F5x68 Register Definition ****
+// Address
+#define D18F5x68_ADDRESS                                        0x68
+
+// Type
+#define D18F5x68_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x68_CTR_31_0__OFFSET                               0
+#define D18F5x68_CTR_31_0__WIDTH                                32
+#define D18F5x68_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x68_STRUCT;
+
+// **** D18F5x6C Register Definition ****
+// Address
+#define D18F5x6C_ADDRESS                                        0x6c
+
+// Type
+#define D18F5x6C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x6C_CTR_47_32__OFFSET                              0
+#define D18F5x6C_CTR_47_32__WIDTH                               16
+#define D18F5x6C_CTR_47_32__MASK                                0xffff
+#define D18F5x6C_RAZ_63_48_OFFSET                               16
+#define D18F5x6C_RAZ_63_48_WIDTH                                16
+#define D18F5x6C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x6C_STRUCT;
+
+// **** D18F5x70 Register Definition ****
+// Address
+#define D18F5x70_ADDRESS                                        0x70
+
+// Type
+#define D18F5x70_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x70_EventSelect_7_0__OFFSET                        0
+#define D18F5x70_EventSelect_7_0__WIDTH                         8
+#define D18F5x70_EventSelect_7_0__MASK                          0xff
+#define D18F5x70_UnitMask_OFFSET                                8
+#define D18F5x70_UnitMask_WIDTH                                 8
+#define D18F5x70_UnitMask_MASK                                  0xff00
+#define D18F5x70_Reserved_18_16_OFFSET                          16
+#define D18F5x70_Reserved_18_16_WIDTH                           3
+#define D18F5x70_Reserved_18_16_MASK                            0x70000
+#define D18F5x70_Reserved_19_19_OFFSET                          19
+#define D18F5x70_Reserved_19_19_WIDTH                           1
+#define D18F5x70_Reserved_19_19_MASK                            0x80000
+#define D18F5x70_Int_OFFSET                                     20
+#define D18F5x70_Int_WIDTH                                      1
+#define D18F5x70_Int_MASK                                       0x100000
+#define D18F5x70_Reserved_21_21_OFFSET                          21
+#define D18F5x70_Reserved_21_21_WIDTH                           1
+#define D18F5x70_Reserved_21_21_MASK                            0x200000
+#define D18F5x70_En_OFFSET                                      22
+#define D18F5x70_En_WIDTH                                       1
+#define D18F5x70_En_MASK                                        0x400000
+#define D18F5x70_Reserved_31_23_OFFSET                          23
+#define D18F5x70_Reserved_31_23_WIDTH                           9
+#define D18F5x70_Reserved_31_23_MASK                            0xff800000
+
+/// D18F5x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         EventSelect_7_0_:8 ; ///<
+    UINT32                                                 UnitMask:8 ; ///<
+    UINT32                                           Reserved_18_16:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                                      Int:1 ; ///<
+    UINT32                                           Reserved_21_21:1 ; ///<
+    UINT32                                                       En:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x70_STRUCT;
+
+// **** D18F5x74 Register Definition ****
+// Address
+#define D18F5x74_ADDRESS                                        0x74
+
+// Type
+#define D18F5x74_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x74_EventSelect_11_8__OFFSET                       0
+#define D18F5x74_EventSelect_11_8__WIDTH                        4
+#define D18F5x74_EventSelect_11_8__MASK                         0xf
+#define D18F5x74_Reserved_63_36_OFFSET                          4
+#define D18F5x74_Reserved_63_36_WIDTH                           28
+#define D18F5x74_Reserved_63_36_MASK                            0xfffffff0
+
+/// D18F5x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        EventSelect_11_8_:4 ; ///<
+    UINT32                                           Reserved_63_36:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x74_STRUCT;
+
+// **** D18F5x78 Register Definition ****
+// Address
+#define D18F5x78_ADDRESS                                        0x78
+
+// Type
+#define D18F5x78_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x78_CTR_31_0__OFFSET                               0
+#define D18F5x78_CTR_31_0__WIDTH                                32
+#define D18F5x78_CTR_31_0__MASK                                 0xffffffff
+
+/// D18F5x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CTR_31_0_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x78_STRUCT;
+
+// **** D18F5x7C Register Definition ****
+// Address
+#define D18F5x7C_ADDRESS                                        0x7c
+
+// Type
+#define D18F5x7C_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x7C_CTR_47_32__OFFSET                              0
+#define D18F5x7C_CTR_47_32__WIDTH                               16
+#define D18F5x7C_CTR_47_32__MASK                                0xffff
+#define D18F5x7C_RAZ_63_48_OFFSET                               16
+#define D18F5x7C_RAZ_63_48_WIDTH                                16
+#define D18F5x7C_RAZ_63_48_MASK                                 0xffff0000
+
+/// D18F5x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               CTR_47_32_:16; ///<
+    UINT32                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x7C_STRUCT;
+
+// **** D18F5x80 Register Definition ****
+// Address
+#define D18F5x80_ADDRESS                                        0x80
+
+// Type
+#define D18F5x80_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x80_Enabled_OFFSET                                 0
+#define D18F5x80_Enabled_WIDTH                                  4
+#define D18F5x80_Enabled_MASK                                   0xf
+#define D18F5x80_Reserved_15_4_OFFSET                           4
+#define D18F5x80_Reserved_15_4_WIDTH                            12
+#define D18F5x80_Reserved_15_4_MASK                             0xfff0
+#define D18F5x80_DualCore_OFFSET                                16
+#define D18F5x80_DualCore_WIDTH                                 4
+#define D18F5x80_DualCore_MASK                                  0xf0000
+#define D18F5x80_Reserved_31_20_OFFSET                          20
+#define D18F5x80_Reserved_31_20_WIDTH                           12
+#define D18F5x80_Reserved_31_20_MASK                            0xfff00000
+
+/// D18F5x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Enabled:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                                 DualCore:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x80_STRUCT;
+
+// **** D18F5x84 Register Definition ****
+// Address
+#define D18F5x84_ADDRESS                                        0x84
+
+// Type
+#define D18F5x84_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x84_CmpCap_OFFSET                                  0
+#define D18F5x84_CmpCap_WIDTH                                   8
+#define D18F5x84_CmpCap_MASK                                    0xff
+#define D18F5x84_Reserved_11_8_OFFSET                           8
+#define D18F5x84_Reserved_11_8_WIDTH                            4
+#define D18F5x84_Reserved_11_8_MASK                             0xf00
+#define D18F5x84_DctEn_OFFSET                                   12
+#define D18F5x84_DctEn_WIDTH                                    2
+#define D18F5x84_DctEn_MASK                                     0x3000
+#define D18F5x84_Reserved_15_14_OFFSET                          14
+#define D18F5x84_Reserved_15_14_WIDTH                           2
+#define D18F5x84_Reserved_15_14_MASK                            0xc000
+#define D18F5x84_DdrMaxRate_OFFSET                              16
+#define D18F5x84_DdrMaxRate_WIDTH                               5
+#define D18F5x84_DdrMaxRate_MASK                                0x1f0000
+#define D18F5x84_Reserved_23_21_OFFSET                          21
+#define D18F5x84_Reserved_23_21_WIDTH                           3
+#define D18F5x84_Reserved_23_21_MASK                            0xe00000
+#define D18F5x84_DdrMaxRateEnf_OFFSET                           24
+#define D18F5x84_DdrMaxRateEnf_WIDTH                            5
+#define D18F5x84_DdrMaxRateEnf_MASK                             0x1f000000
+#define D18F5x84_Reserved_31_29_OFFSET                          29
+#define D18F5x84_Reserved_31_29_WIDTH                           3
+#define D18F5x84_Reserved_31_29_MASK                            0xe0000000
+
+/// D18F5x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CmpCap:8 ; ///<
+    UINT32                                            Reserved_11_8:4 ; ///<
+    UINT32                                                    DctEn:2 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                               DdrMaxRate:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                            DdrMaxRateEnf:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x84_STRUCT;
+
+// **** D18F5x88 Register Definition ****
+// Address
+#define D18F5x88_ADDRESS                                        0x88
+
+// Type
+#define D18F5x88_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5x88_Reserved_1_0_OFFSET                            0
+#define D18F5x88_Reserved_1_0_WIDTH                             2
+#define D18F5x88_Reserved_1_0_MASK                              0x3
+#define D18F5x88_IntStpClkHaltExitEn_OFFSET                     2
+#define D18F5x88_IntStpClkHaltExitEn_WIDTH                      1
+#define D18F5x88_IntStpClkHaltExitEn_MASK                       0x4
+
+/// D18F5x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                      IntStpClkHaltExitEn:1 ; ///<
+    UINT32                                            :29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x88_STRUCT;
+
+// **** D18F5xE0 Register Definition ****
+// Address
+#define D18F5xE0_ADDRESS                                        0xe0
+
+// Type
+#define D18F5xE0_TYPE                                           TYPE_D18F5
+// Field Data
+#define D18F5xE0_RunAvgRange_OFFSET                             0
+#define D18F5xE0_RunAvgRange_WIDTH                              4
+#define D18F5xE0_RunAvgRange_MASK                               0xf
+#define D18F5xE0_Reserved_31_4_OFFSET                           4
+#define D18F5xE0_Reserved_31_4_WIDTH                            28
+#define D18F5xE0_Reserved_31_4_MASK                             0xfffffff0
+
+/// D18F5xE0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              RunAvgRange:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5xE0_STRUCT;
+
+
+// **** D18F5x128 Register Definition ****
+// Address
+#define D18F5x128_ADDRESS                                       0x128
+
+// Type
+#define D18F5x128_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x128_PC6Vid_6_0__OFFSET                            0
+#define D18F5x128_PC6Vid_6_0__WIDTH                             7
+#define D18F5x128_PC6Vid_6_0__MASK                              0x7f
+#define D18F5x128_PllRegTime_OFFSET                             7
+#define D18F5x128_PllRegTime_WIDTH                              2
+#define D18F5x128_PllRegTime_MASK                               0x180
+#define D18F5x128_FastSlamTimeDown_OFFSET                       9
+#define D18F5x128_FastSlamTimeDown_WIDTH                        1
+#define D18F5x128_FastSlamTimeDown_MASK                         0x200
+#define D18F5x128_PllVddOutUpTime_OFFSET                        10
+#define D18F5x128_PllVddOutUpTime_WIDTH                         2
+#define D18F5x128_PllVddOutUpTime_MASK                          0xc00
+#define D18F5x128_PwrGateTmr_OFFSET                             12
+#define D18F5x128_PwrGateTmr_WIDTH                              2
+#define D18F5x128_PwrGateTmr_MASK                               0x3000
+#define D18F5x128_PC6PwrDwnRegEn_OFFSET                         14
+#define D18F5x128_PC6PwrDwnRegEn_WIDTH                          1
+#define D18F5x128_PC6PwrDwnRegEn_MASK                           0x4000
+#define D18F5x128_CC6PwrDwnRegEn_OFFSET                         15
+#define D18F5x128_CC6PwrDwnRegEn_WIDTH                          1
+#define D18F5x128_CC6PwrDwnRegEn_MASK                           0x8000
+#define D18F5x128_Reserved_20_16_OFFSET                         16
+#define D18F5x128_Reserved_20_16_WIDTH                          5
+#define D18F5x128_Reserved_20_16_MASK                           0x1f0000
+#define D18F5x128_PC6Vid_7__OFFSET                              21
+#define D18F5x128_PC6Vid_7__WIDTH                               1
+#define D18F5x128_PC6Vid_7__MASK                                0x200000
+#define D18F5x128_NbPllPwrDwnRegEn_OFFSET                       22
+#define D18F5x128_NbPllPwrDwnRegEn_WIDTH                        1
+#define D18F5x128_NbPllPwrDwnRegEn_MASK                         0x400000
+#define D18F5x128_Reserved_31_23_OFFSET                         23
+#define D18F5x128_Reserved_31_23_WIDTH                          9
+#define D18F5x128_Reserved_31_23_MASK                           0xff800000
+
+/// D18F5x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              PC6Vid_6_0_:7 ; ///<
+    UINT32                                               PllRegTime:2 ; ///<
+    UINT32                                         FastSlamTimeDown:1 ; ///<
+    UINT32                                          PllVddOutUpTime:2 ; ///<
+    UINT32                                               PwrGateTmr:2 ; ///<
+    UINT32                                           PC6PwrDwnRegEn:1 ; ///<
+    UINT32                                           CC6PwrDwnRegEn:1 ; ///<
+    UINT32                                           Reserved_20_16:5 ; ///<
+    UINT32                                                PC6Vid_7_:1 ; ///<
+    UINT32                                         NbPllPwrDwnRegEn:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x128_STRUCT;
+
+// **** D18F5x12C Register Definition ****
+// Address
+#define D18F5x12C_ADDRESS                                       0x12c
+
+// Type
+#define D18F5x12C_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x12C_CoreOffsetTrim_OFFSET                         0
+#define D18F5x12C_CoreOffsetTrim_WIDTH                          2
+#define D18F5x12C_CoreOffsetTrim_MASK                           0x3
+#define D18F5x12C_CoreLoadLineTrim_OFFSET                       2
+#define D18F5x12C_CoreLoadLineTrim_WIDTH                        3
+#define D18F5x12C_CoreLoadLineTrim_MASK                         0x1c
+#define D18F5x12C_CorePsi1En_OFFSET                             5
+#define D18F5x12C_CorePsi1En_WIDTH                              1
+#define D18F5x12C_CorePsi1En_MASK                               0x20
+#define D18F5x12C_Reserved_29_7_OFFSET                          7
+#define D18F5x12C_Reserved_29_7_WIDTH                           23
+#define D18F5x12C_Reserved_29_7_MASK                            0x3fffff80
+#define D18F5x12C_WaitVidCompDis_OFFSET                         30
+#define D18F5x12C_WaitVidCompDis_WIDTH                          1
+#define D18F5x12C_WaitVidCompDis_MASK                           0x40000000
+#define D18F5x12C_Svi2CmdBusy_OFFSET                            31
+#define D18F5x12C_Svi2CmdBusy_WIDTH                             1
+#define D18F5x12C_Svi2CmdBusy_MASK                              0x80000000
+
+/// D18F5x12C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CoreOffsetTrim:2 ; ///<
+    UINT32                                         CoreLoadLineTrim:3 ; ///<
+    UINT32                                               CorePsi1En:1 ; ///<
+    UINT32                                                  :1 ; ///<
+    UINT32                                            Reserved_29_7:23; ///<
+    UINT32                                           WaitVidCompDis:1 ; ///<
+    UINT32                                              Svi2CmdBusy:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x12C_STRUCT;
+
+
+// **** D18F5x160 Register Definition ****
+// Address
+#define D18F5x160_ADDRESS                                       0x160
+
+// Type
+#define D18F5x160_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x160_NbPstateEn_OFFSET                             0
+#define D18F5x160_NbPstateEn_WIDTH                              1
+#define D18F5x160_NbPstateEn_MASK                               0x1
+#define D18F5x160_NbFid_OFFSET                                  1
+#define D18F5x160_NbFid_WIDTH                                   6
+#define D18F5x160_NbFid_MASK                                    0x7e
+#define D18F5x160_NbDid_OFFSET                                  7
+#define D18F5x160_NbDid_WIDTH                                   1
+#define D18F5x160_NbDid_MASK                                    0x80
+#define D18F5x160_Reserved_9_8_OFFSET                           8
+#define D18F5x160_Reserved_9_8_WIDTH                            2
+#define D18F5x160_Reserved_9_8_MASK                             0x300
+#define D18F5x160_NbVid_6_0__OFFSET                             10
+#define D18F5x160_NbVid_6_0__WIDTH                              7
+#define D18F5x160_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x160_Reserved_17_17_OFFSET                         17
+#define D18F5x160_Reserved_17_17_WIDTH                          1
+#define D18F5x160_Reserved_17_17_MASK                           0x20000
+#define D18F5x160_MemPstate_OFFSET                              18
+#define D18F5x160_MemPstate_WIDTH                               1
+#define D18F5x160_MemPstate_MASK                                0x40000
+#define D18F5x160_Reserved_20_19_OFFSET                         19
+#define D18F5x160_Reserved_20_19_WIDTH                          2
+#define D18F5x160_Reserved_20_19_MASK                           0x180000
+#define D18F5x160_NbVid_7__OFFSET                               21
+#define D18F5x160_NbVid_7__WIDTH                                1
+#define D18F5x160_NbVid_7__MASK                                 0x200000
+#define D18F5x160_NbIddDiv_OFFSET                               22
+#define D18F5x160_NbIddDiv_WIDTH                                2
+#define D18F5x160_NbIddDiv_MASK                                 0xc00000
+#define D18F5x160_NbIddValue_OFFSET                             24
+#define D18F5x160_NbIddValue_WIDTH                              8
+#define D18F5x160_NbIddValue_MASK                               0xff000000
+
+/// D18F5x160
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x160_STRUCT;
+
+// **** D18F5x164 Register Definition ****
+// Address
+#define D18F5x164_ADDRESS                                       0x164
+
+// Type
+#define D18F5x164_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x164_NbPstateEn_OFFSET                             0
+#define D18F5x164_NbPstateEn_WIDTH                              1
+#define D18F5x164_NbPstateEn_MASK                               0x1
+#define D18F5x164_NbFid_OFFSET                                  1
+#define D18F5x164_NbFid_WIDTH                                   6
+#define D18F5x164_NbFid_MASK                                    0x7e
+#define D18F5x164_NbDid_OFFSET                                  7
+#define D18F5x164_NbDid_WIDTH                                   1
+#define D18F5x164_NbDid_MASK                                    0x80
+#define D18F5x164_Reserved_9_8_OFFSET                           8
+#define D18F5x164_Reserved_9_8_WIDTH                            2
+#define D18F5x164_Reserved_9_8_MASK                             0x300
+#define D18F5x164_NbVid_6_0__OFFSET                             10
+#define D18F5x164_NbVid_6_0__WIDTH                              7
+#define D18F5x164_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x164_Reserved_17_17_OFFSET                         17
+#define D18F5x164_Reserved_17_17_WIDTH                          1
+#define D18F5x164_Reserved_17_17_MASK                           0x20000
+#define D18F5x164_MemPstate_OFFSET                              18
+#define D18F5x164_MemPstate_WIDTH                               1
+#define D18F5x164_MemPstate_MASK                                0x40000
+#define D18F5x164_Reserved_20_19_OFFSET                         19
+#define D18F5x164_Reserved_20_19_WIDTH                          2
+#define D18F5x164_Reserved_20_19_MASK                           0x180000
+#define D18F5x164_NbVid_7__OFFSET                               21
+#define D18F5x164_NbVid_7__WIDTH                                1
+#define D18F5x164_NbVid_7__MASK                                 0x200000
+#define D18F5x164_NbIddDiv_OFFSET                               22
+#define D18F5x164_NbIddDiv_WIDTH                                2
+#define D18F5x164_NbIddDiv_MASK                                 0xc00000
+#define D18F5x164_NbIddValue_OFFSET                             24
+#define D18F5x164_NbIddValue_WIDTH                              8
+#define D18F5x164_NbIddValue_MASK                               0xff000000
+
+/// D18F5x164
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x164_STRUCT;
+
+// **** D18F5x168 Register Definition ****
+// Address
+#define D18F5x168_ADDRESS                                       0x168
+
+// Type
+#define D18F5x168_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x168_NbPstateEn_OFFSET                             0
+#define D18F5x168_NbPstateEn_WIDTH                              1
+#define D18F5x168_NbPstateEn_MASK                               0x1
+#define D18F5x168_NbFid_OFFSET                                  1
+#define D18F5x168_NbFid_WIDTH                                   6
+#define D18F5x168_NbFid_MASK                                    0x7e
+#define D18F5x168_NbDid_OFFSET                                  7
+#define D18F5x168_NbDid_WIDTH                                   1
+#define D18F5x168_NbDid_MASK                                    0x80
+#define D18F5x168_Reserved_9_8_OFFSET                           8
+#define D18F5x168_Reserved_9_8_WIDTH                            2
+#define D18F5x168_Reserved_9_8_MASK                             0x300
+#define D18F5x168_NbVid_6_0__OFFSET                             10
+#define D18F5x168_NbVid_6_0__WIDTH                              7
+#define D18F5x168_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x168_Reserved_17_17_OFFSET                         17
+#define D18F5x168_Reserved_17_17_WIDTH                          1
+#define D18F5x168_Reserved_17_17_MASK                           0x20000
+#define D18F5x168_MemPstate_OFFSET                              18
+#define D18F5x168_MemPstate_WIDTH                               1
+#define D18F5x168_MemPstate_MASK                                0x40000
+#define D18F5x168_Reserved_20_19_OFFSET                         19
+#define D18F5x168_Reserved_20_19_WIDTH                          2
+#define D18F5x168_Reserved_20_19_MASK                           0x180000
+#define D18F5x168_NbVid_7__OFFSET                               21
+#define D18F5x168_NbVid_7__WIDTH                                1
+#define D18F5x168_NbVid_7__MASK                                 0x200000
+#define D18F5x168_NbIddDiv_OFFSET                               22
+#define D18F5x168_NbIddDiv_WIDTH                                2
+#define D18F5x168_NbIddDiv_MASK                                 0xc00000
+#define D18F5x168_NbIddValue_OFFSET                             24
+#define D18F5x168_NbIddValue_WIDTH                              8
+#define D18F5x168_NbIddValue_MASK                               0xff000000
+
+/// D18F5x168
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x168_STRUCT;
+
+// **** D18F5x16C Register Definition ****
+// Address
+#define D18F5x16C_ADDRESS                                       0x16c
+
+// Type
+#define D18F5x16C_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x16C_NbPstateEn_OFFSET                             0
+#define D18F5x16C_NbPstateEn_WIDTH                              1
+#define D18F5x16C_NbPstateEn_MASK                               0x1
+#define D18F5x16C_NbFid_OFFSET                                  1
+#define D18F5x16C_NbFid_WIDTH                                   6
+#define D18F5x16C_NbFid_MASK                                    0x7e
+#define D18F5x16C_NbDid_OFFSET                                  7
+#define D18F5x16C_NbDid_WIDTH                                   1
+#define D18F5x16C_NbDid_MASK                                    0x80
+#define D18F5x16C_Reserved_9_8_OFFSET                           8
+#define D18F5x16C_Reserved_9_8_WIDTH                            2
+#define D18F5x16C_Reserved_9_8_MASK                             0x300
+#define D18F5x16C_NbVid_6_0__OFFSET                             10
+#define D18F5x16C_NbVid_6_0__WIDTH                              7
+#define D18F5x16C_NbVid_6_0__MASK                               0x1fc00
+#define D18F5x16C_Reserved_17_17_OFFSET                         17
+#define D18F5x16C_Reserved_17_17_WIDTH                          1
+#define D18F5x16C_Reserved_17_17_MASK                           0x20000
+#define D18F5x16C_MemPstate_OFFSET                              18
+#define D18F5x16C_MemPstate_WIDTH                               1
+#define D18F5x16C_MemPstate_MASK                                0x40000
+#define D18F5x16C_Reserved_20_19_OFFSET                         19
+#define D18F5x16C_Reserved_20_19_WIDTH                          2
+#define D18F5x16C_Reserved_20_19_MASK                           0x180000
+#define D18F5x16C_NbVid_7__OFFSET                               21
+#define D18F5x16C_NbVid_7__WIDTH                                1
+#define D18F5x16C_NbVid_7__MASK                                 0x200000
+#define D18F5x16C_NbIddDiv_OFFSET                               22
+#define D18F5x16C_NbIddDiv_WIDTH                                2
+#define D18F5x16C_NbIddDiv_MASK                                 0xc00000
+#define D18F5x16C_NbIddValue_OFFSET                             24
+#define D18F5x16C_NbIddValue_WIDTH                              8
+#define D18F5x16C_NbIddValue_MASK                               0xff000000
+
+/// D18F5x16C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               NbPstateEn:1 ; ///<
+    UINT32                                                    NbFid:6 ; ///<
+    UINT32                                                    NbDid:1 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                               NbVid_6_0_:7 ; ///<
+    UINT32                                           Reserved_17_17:1 ; ///<
+    UINT32                                                MemPstate:1 ; ///<
+    UINT32                                           Reserved_20_19:2 ; ///<
+    UINT32                                                 NbVid_7_:1 ; ///<
+    UINT32                                                 NbIddDiv:2 ; ///<
+    UINT32                                               NbIddValue:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x16C_STRUCT;
+
+// **** D18F5x170 Register Definition ****
+// Address
+#define D18F5x170_ADDRESS                                       0x170
+
+// Type
+#define D18F5x170_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x170_NbPstateMaxVal_OFFSET                         0
+#define D18F5x170_NbPstateMaxVal_WIDTH                          2
+#define D18F5x170_NbPstateMaxVal_MASK                           0x3
+#define D18F5x170_Reserved_2_2_OFFSET                           2
+#define D18F5x170_Reserved_2_2_WIDTH                            1
+#define D18F5x170_Reserved_2_2_MASK                             0x4
+#define D18F5x170_NbPstateLo_OFFSET                             3
+#define D18F5x170_NbPstateLo_WIDTH                              2
+#define D18F5x170_NbPstateLo_MASK                               0x18
+#define D18F5x170_Reserved_5_5_OFFSET                           5
+#define D18F5x170_Reserved_5_5_WIDTH                            1
+#define D18F5x170_Reserved_5_5_MASK                             0x20
+#define D18F5x170_NbPstateHi_OFFSET                             6
+#define D18F5x170_NbPstateHi_WIDTH                              2
+#define D18F5x170_NbPstateHi_MASK                               0xc0
+#define D18F5x170_Reserved_8_8_OFFSET                           8
+#define D18F5x170_Reserved_8_8_WIDTH                            1
+#define D18F5x170_Reserved_8_8_MASK                             0x100
+#define D18F5x170_NbPstateThreshold_OFFSET                      9
+#define D18F5x170_NbPstateThreshold_WIDTH                       3
+#define D18F5x170_NbPstateThreshold_MASK                        0xe00
+#define D18F5x170_Reserved_12_12_OFFSET                         12
+#define D18F5x170_Reserved_12_12_WIDTH                          1
+#define D18F5x170_Reserved_12_12_MASK                           0x1000
+#define D18F5x170_NbPstateDisOnP0_OFFSET                        13
+#define D18F5x170_NbPstateDisOnP0_WIDTH                         1
+#define D18F5x170_NbPstateDisOnP0_MASK                          0x2000
+#define D18F5x170_SwNbPstateLoDis_OFFSET                        14
+#define D18F5x170_SwNbPstateLoDis_WIDTH                         1
+#define D18F5x170_SwNbPstateLoDis_MASK                          0x4000
+#define D18F5x170_Reserved_22_15_OFFSET                         15
+#define D18F5x170_Reserved_22_15_WIDTH                          8
+#define D18F5x170_Reserved_22_15_MASK                           0x7f8000
+#define D18F5x170_NbPstateGnbSlowDis_OFFSET                     23
+#define D18F5x170_NbPstateGnbSlowDis_WIDTH                      1
+#define D18F5x170_NbPstateGnbSlowDis_MASK                       0x800000
+#define D18F5x170_NbPstateLoRes_OFFSET                          24
+#define D18F5x170_NbPstateLoRes_WIDTH                           3
+#define D18F5x170_NbPstateLoRes_MASK                            0x7000000
+#define D18F5x170_NbPstateHiRes_OFFSET                          27
+#define D18F5x170_NbPstateHiRes_WIDTH                           3
+#define D18F5x170_NbPstateHiRes_MASK                            0x38000000
+#define D18F5x170_Reserved_30_30_OFFSET                         30
+#define D18F5x170_Reserved_30_30_WIDTH                          1
+#define D18F5x170_Reserved_30_30_MASK                           0x40000000
+#define D18F5x170_MemPstateDis_OFFSET                           31
+#define D18F5x170_MemPstateDis_WIDTH                            1
+#define D18F5x170_MemPstateDis_MASK                             0x80000000
+
+/// D18F5x170
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           NbPstateMaxVal:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                               NbPstateLo:2 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                               NbPstateHi:2 ; ///<
+    UINT32                                             Reserved_8_8:1 ; ///<
+    UINT32                                        NbPstateThreshold:3 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                          NbPstateDisOnP0:1 ; ///<
+    UINT32                                          SwNbPstateLoDis:1 ; ///<
+    UINT32                                           Reserved_22_15:8 ; ///<
+    UINT32                                       NbPstateGnbSlowDis:1 ; ///<
+    UINT32                                            NbPstateLoRes:3 ; ///<
+    UINT32                                            NbPstateHiRes:3 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             MemPstateDis:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x170_STRUCT;
+
+// **** D18F5x174 Register Definition ****
+// Address
+#define D18F5x174_ADDRESS                                       0x174
+
+// Type
+#define D18F5x174_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x174_NbPstateDis_OFFSET                            0
+#define D18F5x174_NbPstateDis_WIDTH                             1
+#define D18F5x174_NbPstateDis_MASK                              0x1
+#define D18F5x174_StartupNbPstate_OFFSET                        1
+#define D18F5x174_StartupNbPstate_WIDTH                         2
+#define D18F5x174_StartupNbPstate_MASK                          0x6
+#define D18F5x174_CurNbFid_OFFSET                               3
+#define D18F5x174_CurNbFid_WIDTH                                6
+#define D18F5x174_CurNbFid_MASK                                 0x1f8
+#define D18F5x174_CurNbDid_OFFSET                               9
+#define D18F5x174_CurNbDid_WIDTH                                1
+#define D18F5x174_CurNbDid_MASK                                 0x200
+#define D18F5x174_Reserved_11_10_OFFSET                         10
+#define D18F5x174_Reserved_11_10_WIDTH                          2
+#define D18F5x174_Reserved_11_10_MASK                           0xc00
+#define D18F5x174_CurNbVid_6_0__OFFSET                          12
+#define D18F5x174_CurNbVid_6_0__WIDTH                           7
+#define D18F5x174_CurNbVid_6_0__MASK                            0x7f000
+#define D18F5x174_CurNbPstate_OFFSET                            19
+#define D18F5x174_CurNbPstate_WIDTH                             2
+#define D18F5x174_CurNbPstate_MASK                              0x180000
+#define D18F5x174_Reserved_22_21_OFFSET                         21
+#define D18F5x174_Reserved_22_21_WIDTH                          2
+#define D18F5x174_Reserved_22_21_MASK                           0x600000
+#define D18F5x174_CurNbVid_7__OFFSET                            23
+#define D18F5x174_CurNbVid_7__WIDTH                             1
+#define D18F5x174_CurNbVid_7__MASK                              0x800000
+#define D18F5x174_CurMemPstate_OFFSET                           24
+#define D18F5x174_CurMemPstate_WIDTH                            1
+#define D18F5x174_CurMemPstate_MASK                             0x1000000
+#define D18F5x174_Reserved_31_25_OFFSET                         25
+#define D18F5x174_Reserved_31_25_WIDTH                          7
+#define D18F5x174_Reserved_31_25_MASK                           0xfe000000
+
+/// D18F5x174
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              NbPstateDis:1 ; ///<
+    UINT32                                          StartupNbPstate:2 ; ///<
+    UINT32                                                 CurNbFid:6 ; ///<
+    UINT32                                                 CurNbDid:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                                            CurNbVid_6_0_:7 ; ///<
+    UINT32                                              CurNbPstate:2 ; ///<
+    UINT32                                           Reserved_22_21:2 ; ///<
+    UINT32                                              CurNbVid_7_:1 ; ///<
+    UINT32                                             CurMemPstate:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x174_STRUCT;
+
+// **** D18F5x178 Register Definition ****
+// Address
+#define D18F5x178_ADDRESS                                       0x178
+
+// Type
+#define D18F5x178_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x178_Reserved_1_0_OFFSET                           0
+#define D18F5x178_Reserved_1_0_WIDTH                            2
+#define D18F5x178_Reserved_1_0_MASK                             0x3
+#define D18F5x178_CstateFusionDis_OFFSET                        2
+#define D18F5x178_CstateFusionDis_WIDTH                         1
+#define D18F5x178_CstateFusionDis_MASK                          0x4
+#define D18F5x178_CstateThreeWayHsEn_OFFSET                     3
+#define D18F5x178_CstateThreeWayHsEn_WIDTH                      1
+#define D18F5x178_CstateThreeWayHsEn_MASK                       0x8
+#define D18F5x178_Reserved_9_4_OFFSET                           4
+#define D18F5x178_Reserved_9_4_WIDTH                            6
+#define D18F5x178_Reserved_9_4_MASK                             0x3f0
+#define D18F5x178_InbWakeS3Dis_OFFSET                           10
+#define D18F5x178_InbWakeS3Dis_WIDTH                            1
+#define D18F5x178_InbWakeS3Dis_MASK                             0x400
+#define D18F5x178_AllowSelfRefrS3Dis_OFFSET                     11
+#define D18F5x178_AllowSelfRefrS3Dis_WIDTH                      1
+#define D18F5x178_AllowSelfRefrS3Dis_MASK                       0x800
+#define D18F5x178_CstateFusionHsDis_OFFSET                      18
+#define D18F5x178_CstateFusionHsDis_WIDTH                       1
+#define D18F5x178_CstateFusionHsDis_MASK                        0x40000
+#define D18F5x178_SwGfxDis_OFFSET                               19
+#define D18F5x178_SwGfxDis_WIDTH                                1
+#define D18F5x178_SwGfxDis_MASK                                 0x80000
+#define D18F5x178_Reserved_31_20_OFFSET                         20
+#define D18F5x178_Reserved_31_20_WIDTH                          12
+#define D18F5x178_Reserved_31_20_MASK                           0xfff00000
+
+/// D18F5x178
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                          CstateFusionDis:1 ; ///<
+    UINT32                                       CstateThreeWayHsEn:1 ; ///<
+    UINT32                                             Reserved_9_4:6 ; ///<
+    UINT32                                             InbWakeS3Dis:1 ; ///<
+    UINT32                                       AllowSelfRefrS3Dis:1 ; ///<
+    UINT32                                           :6 ; ///<
+    UINT32                                        CstateFusionHsDis:1 ; ///<
+    UINT32                                                 SwGfxDis:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x178_STRUCT;
+
+// **** D18F5x17C Register Definition ****
+// Address
+#define D18F5x17C_ADDRESS                                       0x17c
+
+// Type
+#define D18F5x17C_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x17C_MaxVid_OFFSET                                 0
+#define D18F5x17C_MaxVid_WIDTH                                  8
+#define D18F5x17C_MaxVid_MASK                                   0xff
+#define D18F5x17C_Reserved_9_8_OFFSET                           8
+#define D18F5x17C_Reserved_9_8_WIDTH                            2
+#define D18F5x17C_Reserved_9_8_MASK                             0x300
+#define D18F5x17C_MinVid_OFFSET                                 10
+#define D18F5x17C_MinVid_WIDTH                                  8
+#define D18F5x17C_MinVid_MASK                                   0x3fc00
+#define D18F5x17C_Reserved_22_18_OFFSET                         18
+#define D18F5x17C_Reserved_22_18_WIDTH                          5
+#define D18F5x17C_Reserved_22_18_MASK                           0x7c0000
+#define D18F5x17C_NbPsi0Vid_7_0__OFFSET                         23
+#define D18F5x17C_NbPsi0Vid_7_0__WIDTH                          8
+#define D18F5x17C_NbPsi0Vid_7_0__MASK                           0x7f800000
+#define D18F5x17C_NbPsi0VidEn_OFFSET                            31
+#define D18F5x17C_NbPsi0VidEn_WIDTH                             1
+#define D18F5x17C_NbPsi0VidEn_MASK                              0x80000000
+
+/// D18F5x17C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   MaxVid:8 ; ///<
+    UINT32                                             Reserved_9_8:2 ; ///<
+    UINT32                                                   MinVid:8 ; ///<
+    UINT32                                           Reserved_22_18:5 ; ///<
+    UINT32                                           NbPsi0Vid_7_0_:8 ; ///<
+    UINT32                                              NbPsi0VidEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x17C_STRUCT;
+
+// **** D18F5x188 Register Definition ****
+// Address
+#define D18F5x188_ADDRESS                                       0x188
+
+// Type
+#define D18F5x188_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x188_NbOffsetTrim_OFFSET                           0
+#define D18F5x188_NbOffsetTrim_WIDTH                            2
+#define D18F5x188_NbOffsetTrim_MASK                             0x3
+#define D18F5x188_NbLoadLineTrim_OFFSET                         2
+#define D18F5x188_NbLoadLineTrim_WIDTH                          3
+#define D18F5x188_NbLoadLineTrim_MASK                           0x1c
+#define D18F5x188_NbPsi1_OFFSET                                 5
+#define D18F5x188_NbPsi1_WIDTH                                  1
+#define D18F5x188_NbPsi1_MASK                                   0x20
+#define D18F5x188_Reserved_31_7_OFFSET                          7
+#define D18F5x188_Reserved_31_7_WIDTH                           25
+#define D18F5x188_Reserved_31_7_MASK                            0xffffff80
+
+/// D18F5x188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NbOffsetTrim:2 ; ///<
+    UINT32                                           NbLoadLineTrim:3 ; ///<
+    UINT32                                                   NbPsi1:1 ; ///<
+    UINT32                                                    NbTfn:1 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x188_STRUCT;
+
+// **** D18F5x194 Register Definition ****
+// Address
+#define D18F5x194_ADDRESS                                       0x194
+
+// Type
+#define D18F5x194_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x194_Index_OFFSET                                  0
+#define D18F5x194_Index_WIDTH                                   4
+#define D18F5x194_Index_MASK                                    0xf
+#define D18F5x194_Reserved_31_4_OFFSET                          4
+#define D18F5x194_Reserved_31_4_WIDTH                           28
+#define D18F5x194_Reserved_31_4_MASK                            0xfffffff0
+
+/// D18F5x194
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Index:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x194_STRUCT;
+
+// **** D18F5x198 Register Definition ****
+// Address
+#define D18F5x198_ADDRESS                                       0x198
+
+// Type
+#define D18F5x198_TYPE                                          TYPE_D18F5
+// Field Data
+#define D18F5x198_Data_OFFSET                                   0
+#define D18F5x198_Data_WIDTH                                    32
+#define D18F5x198_Data_MASK                                     0xffffffff
+
+/// D18F5x198
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F5x198_STRUCT;
+
+// **** DxF0x00 Register Definition ****
+// Address
+#define DxF0x00_ADDRESS                                         0x0
+
+// Type
+#define DxF0x00_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x00_VendorID_OFFSET                                 0
+#define DxF0x00_VendorID_WIDTH                                  16
+#define DxF0x00_VendorID_MASK                                   0xffff
+#define DxF0x00_DeviceID_OFFSET                                 16
+#define DxF0x00_DeviceID_WIDTH                                  16
+#define DxF0x00_DeviceID_MASK                                   0xffff0000
+
+/// DxF0x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VendorID:16; ///<
+    UINT32                                                 DeviceID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x00_STRUCT;
+
+// **** DxF0x04 Register Definition ****
+// Address
+#define DxF0x04_ADDRESS                                         0x4
+
+// Type
+#define DxF0x04_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x04_IoAccessEn_OFFSET                               0
+#define DxF0x04_IoAccessEn_WIDTH                                1
+#define DxF0x04_IoAccessEn_MASK                                 0x1
+#define DxF0x04_MemAccessEn_OFFSET                              1
+#define DxF0x04_MemAccessEn_WIDTH                               1
+#define DxF0x04_MemAccessEn_MASK                                0x2
+#define DxF0x04_BusMasterEn_OFFSET                              2
+#define DxF0x04_BusMasterEn_WIDTH                               1
+#define DxF0x04_BusMasterEn_MASK                                0x4
+#define DxF0x04_SpecialCycleEn_OFFSET                           3
+#define DxF0x04_SpecialCycleEn_WIDTH                            1
+#define DxF0x04_SpecialCycleEn_MASK                             0x8
+#define DxF0x04_MemWriteInvalidateEn_OFFSET                     4
+#define DxF0x04_MemWriteInvalidateEn_WIDTH                      1
+#define DxF0x04_MemWriteInvalidateEn_MASK                       0x10
+#define DxF0x04_PalSnoopEn_OFFSET                               5
+#define DxF0x04_PalSnoopEn_WIDTH                                1
+#define DxF0x04_PalSnoopEn_MASK                                 0x20
+#define DxF0x04_ParityErrorEn_OFFSET                            6
+#define DxF0x04_ParityErrorEn_WIDTH                             1
+#define DxF0x04_ParityErrorEn_MASK                              0x40
+#define DxF0x04_Stepping_OFFSET                                 7
+#define DxF0x04_Stepping_WIDTH                                  1
+#define DxF0x04_Stepping_MASK                                   0x80
+#define DxF0x04_SerrEn_OFFSET                                   8
+#define DxF0x04_SerrEn_WIDTH                                    1
+#define DxF0x04_SerrEn_MASK                                     0x100
+#define DxF0x04_FastB2BEn_OFFSET                                9
+#define DxF0x04_FastB2BEn_WIDTH                                 1
+#define DxF0x04_FastB2BEn_MASK                                  0x200
+#define DxF0x04_IntDis_OFFSET                                   10
+#define DxF0x04_IntDis_WIDTH                                    1
+#define DxF0x04_IntDis_MASK                                     0x400
+#define DxF0x04_Reserved_18_11_OFFSET                           11
+#define DxF0x04_Reserved_18_11_WIDTH                            8
+#define DxF0x04_Reserved_18_11_MASK                             0x7f800
+#define DxF0x04_IntStatus_OFFSET                                19
+#define DxF0x04_IntStatus_WIDTH                                 1
+#define DxF0x04_IntStatus_MASK                                  0x80000
+#define DxF0x04_CapList_OFFSET                                  20
+#define DxF0x04_CapList_WIDTH                                   1
+#define DxF0x04_CapList_MASK                                    0x100000
+#define DxF0x04_PCI66En_OFFSET                                  21
+#define DxF0x04_PCI66En_WIDTH                                   1
+#define DxF0x04_PCI66En_MASK                                    0x200000
+#define DxF0x04_UDFEn_OFFSET                                    22
+#define DxF0x04_UDFEn_WIDTH                                     1
+#define DxF0x04_UDFEn_MASK                                      0x400000
+#define DxF0x04_FastBackCapable_OFFSET                          23
+#define DxF0x04_FastBackCapable_WIDTH                           1
+#define DxF0x04_FastBackCapable_MASK                            0x800000
+#define DxF0x04_DataPerr_OFFSET                                 24
+#define DxF0x04_DataPerr_WIDTH                                  1
+#define DxF0x04_DataPerr_MASK                                   0x1000000
+#define DxF0x04_DevselTiming_OFFSET                             25
+#define DxF0x04_DevselTiming_WIDTH                              2
+#define DxF0x04_DevselTiming_MASK                               0x6000000
+#define DxF0x04_SignalTargetAbort_OFFSET                        27
+#define DxF0x04_SignalTargetAbort_WIDTH                         1
+#define DxF0x04_SignalTargetAbort_MASK                          0x8000000
+#define DxF0x04_ReceivedTargetAbort_OFFSET                      28
+#define DxF0x04_ReceivedTargetAbort_WIDTH                       1
+#define DxF0x04_ReceivedTargetAbort_MASK                        0x10000000
+#define DxF0x04_ReceivedMasterAbort_OFFSET                      29
+#define DxF0x04_ReceivedMasterAbort_WIDTH                       1
+#define DxF0x04_ReceivedMasterAbort_MASK                        0x20000000
+#define DxF0x04_SignaledSystemError_OFFSET                      30
+#define DxF0x04_SignaledSystemError_WIDTH                       1
+#define DxF0x04_SignaledSystemError_MASK                        0x40000000
+#define DxF0x04_ParityErrorDetected_OFFSET                      31
+#define DxF0x04_ParityErrorDetected_WIDTH                       1
+#define DxF0x04_ParityErrorDetected_MASK                        0x80000000
+
+/// DxF0x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IoAccessEn:1 ; ///<
+    UINT32                                              MemAccessEn:1 ; ///<
+    UINT32                                              BusMasterEn:1 ; ///<
+    UINT32                                           SpecialCycleEn:1 ; ///<
+    UINT32                                     MemWriteInvalidateEn:1 ; ///<
+    UINT32                                               PalSnoopEn:1 ; ///<
+    UINT32                                            ParityErrorEn:1 ; ///<
+    UINT32                                                 Stepping:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                FastB2BEn:1 ; ///<
+    UINT32                                                   IntDis:1 ; ///<
+    UINT32                                           Reserved_18_11:8 ; ///<
+    UINT32                                                IntStatus:1 ; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                                    UDFEn:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                                 DataPerr:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      SignaledSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x04_STRUCT;
+
+// **** DxF0x08 Register Definition ****
+// Address
+#define DxF0x08_ADDRESS                                         0x8
+
+// Type
+#define DxF0x08_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x08_RevID_OFFSET                                    0
+#define DxF0x08_RevID_WIDTH                                     8
+#define DxF0x08_RevID_MASK                                      0xff
+#define DxF0x08_ClassCode_OFFSET                                8
+#define DxF0x08_ClassCode_WIDTH                                 24
+#define DxF0x08_ClassCode_MASK                                  0xffffff00
+
+/// DxF0x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    RevID:8 ; ///<
+    UINT32                                                ClassCode:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x08_STRUCT;
+
+// **** DxF0x0C Register Definition ****
+// Address
+#define DxF0x0C_ADDRESS                                         0xc
+
+// Type
+#define DxF0x0C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x0C_CacheLineSize_OFFSET                            0
+#define DxF0x0C_CacheLineSize_WIDTH                             8
+#define DxF0x0C_CacheLineSize_MASK                              0xff
+#define DxF0x0C_LatencyTimer_OFFSET                             8
+#define DxF0x0C_LatencyTimer_WIDTH                              8
+#define DxF0x0C_LatencyTimer_MASK                               0xff00
+#define DxF0x0C_HeaderTypeReg_OFFSET                            16
+#define DxF0x0C_HeaderTypeReg_WIDTH                             8
+#define DxF0x0C_HeaderTypeReg_MASK                              0xff0000
+#define DxF0x0C_BIST_OFFSET                                     24
+#define DxF0x0C_BIST_WIDTH                                      8
+#define DxF0x0C_BIST_MASK                                       0xff000000
+
+/// DxF0x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CacheLineSize:8 ; ///<
+    UINT32                                             LatencyTimer:8 ; ///<
+    UINT32                                            HeaderTypeReg:8 ; ///<
+    UINT32                                                     BIST:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x0C_STRUCT;
+
+// **** DxF0x18 Register Definition ****
+// Address
+#define DxF0x18_ADDRESS                                         0x18
+
+// Type
+#define DxF0x18_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x18_PrimaryBus_OFFSET                               0
+#define DxF0x18_PrimaryBus_WIDTH                                8
+#define DxF0x18_PrimaryBus_MASK                                 0xff
+#define DxF0x18_SecondaryBus_OFFSET                             8
+#define DxF0x18_SecondaryBus_WIDTH                              8
+#define DxF0x18_SecondaryBus_MASK                               0xff00
+#define DxF0x18_SubBusNumber_OFFSET                             16
+#define DxF0x18_SubBusNumber_WIDTH                              8
+#define DxF0x18_SubBusNumber_MASK                               0xff0000
+#define DxF0x18_SecondaryLatencyTimer_OFFSET                    24
+#define DxF0x18_SecondaryLatencyTimer_WIDTH                     8
+#define DxF0x18_SecondaryLatencyTimer_MASK                      0xff000000
+
+/// DxF0x18
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PrimaryBus:8 ; ///<
+    UINT32                                             SecondaryBus:8 ; ///<
+    UINT32                                             SubBusNumber:8 ; ///<
+    UINT32                                    SecondaryLatencyTimer:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x18_STRUCT;
+
+// **** DxF0x1C Register Definition ****
+// Address
+#define DxF0x1C_ADDRESS                                         0x1c
+
+// Type
+#define DxF0x1C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x1C_Reserved_3_0_OFFSET                             0
+#define DxF0x1C_Reserved_3_0_WIDTH                              4
+#define DxF0x1C_Reserved_3_0_MASK                               0xf
+#define DxF0x1C_IOBase_15_12__OFFSET                            4
+#define DxF0x1C_IOBase_15_12__WIDTH                             4
+#define DxF0x1C_IOBase_15_12__MASK                              0xf0
+#define DxF0x1C_Reserved_11_8_OFFSET                            8
+#define DxF0x1C_Reserved_11_8_WIDTH                             4
+#define DxF0x1C_Reserved_11_8_MASK                              0xf00
+#define DxF0x1C_IOLimit_15_12__OFFSET                           12
+#define DxF0x1C_IOLimit_15_12__WIDTH                            4
+#define DxF0x1C_IOLimit_15_12__MASK                             0xf000
+#define DxF0x1C_Reserved_19_16_OFFSET                           16
+#define DxF0x1C_Reserved_19_16_WIDTH                            4
+#define DxF0x1C_Reserved_19_16_MASK                             0xf0000
+#define DxF0x1C_CapList_OFFSET                                  20
+#define DxF0x1C_CapList_WIDTH                                   1
+#define DxF0x1C_CapList_MASK                                    0x100000
+#define DxF0x1C_PCI66En_OFFSET                                  21
+#define DxF0x1C_PCI66En_WIDTH                                   1
+#define DxF0x1C_PCI66En_MASK                                    0x200000
+#define DxF0x1C_UDFEn_OFFSET                                    22
+#define DxF0x1C_UDFEn_WIDTH                                     1
+#define DxF0x1C_UDFEn_MASK                                      0x400000
+#define DxF0x1C_FastBackCapable_OFFSET                          23
+#define DxF0x1C_FastBackCapable_WIDTH                           1
+#define DxF0x1C_FastBackCapable_MASK                            0x800000
+#define DxF0x1C_MasterDataPerr_OFFSET                           24
+#define DxF0x1C_MasterDataPerr_WIDTH                            1
+#define DxF0x1C_MasterDataPerr_MASK                             0x1000000
+#define DxF0x1C_DevselTiming_OFFSET                             25
+#define DxF0x1C_DevselTiming_WIDTH                              2
+#define DxF0x1C_DevselTiming_MASK                               0x6000000
+#define DxF0x1C_SignalTargetAbort_OFFSET                        27
+#define DxF0x1C_SignalTargetAbort_WIDTH                         1
+#define DxF0x1C_SignalTargetAbort_MASK                          0x8000000
+#define DxF0x1C_ReceivedTargetAbort_OFFSET                      28
+#define DxF0x1C_ReceivedTargetAbort_WIDTH                       1
+#define DxF0x1C_ReceivedTargetAbort_MASK                        0x10000000
+#define DxF0x1C_ReceivedMasterAbort_OFFSET                      29
+#define DxF0x1C_ReceivedMasterAbort_WIDTH                       1
+#define DxF0x1C_ReceivedMasterAbort_MASK                        0x20000000
+#define DxF0x1C_ReceivedSystemError_OFFSET                      30
+#define DxF0x1C_ReceivedSystemError_WIDTH                       1
+#define DxF0x1C_ReceivedSystemError_MASK                        0x40000000
+#define DxF0x1C_ParityErrorDetected_OFFSET                      31
+#define DxF0x1C_ParityErrorDetected_WIDTH                       1
+#define DxF0x1C_ParityErrorDetected_MASK                        0x80000000
+
+/// DxF0x1C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                            IOBase_15_12_:4 ; ///<
+    UINT32                                            Reserved_11_8:4 ; ///<
+    UINT32                                           IOLimit_15_12_:4 ; ///<
+    UINT32                                           Reserved_19_16:4 ; ///<
+    UINT32                                                  CapList:1 ; ///<
+    UINT32                                                  PCI66En:1 ; ///<
+    UINT32                                                    UDFEn:1 ; ///<
+    UINT32                                          FastBackCapable:1 ; ///<
+    UINT32                                           MasterDataPerr:1 ; ///<
+    UINT32                                             DevselTiming:2 ; ///<
+    UINT32                                        SignalTargetAbort:1 ; ///<
+    UINT32                                      ReceivedTargetAbort:1 ; ///<
+    UINT32                                      ReceivedMasterAbort:1 ; ///<
+    UINT32                                      ReceivedSystemError:1 ; ///<
+    UINT32                                      ParityErrorDetected:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x1C_STRUCT;
+
+// **** DxF0x20 Register Definition ****
+// Address
+#define DxF0x20_ADDRESS                                         0x20
+
+// Type
+#define DxF0x20_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x20_Reserved_3_0_OFFSET                             0
+#define DxF0x20_Reserved_3_0_WIDTH                              4
+#define DxF0x20_Reserved_3_0_MASK                               0xf
+#define DxF0x20_MemBase_OFFSET                                  4
+#define DxF0x20_MemBase_WIDTH                                   12
+#define DxF0x20_MemBase_MASK                                    0xfff0
+#define DxF0x20_Reserved_19_16_OFFSET                           16
+#define DxF0x20_Reserved_19_16_WIDTH                            4
+#define DxF0x20_Reserved_19_16_MASK                             0xf0000
+#define DxF0x20_MemLimit_OFFSET                                 20
+#define DxF0x20_MemLimit_WIDTH                                  12
+#define DxF0x20_MemLimit_MASK                                   0xfff00000
+
+/// DxF0x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                                  MemBase:12; ///<
+    UINT32                                           Reserved_19_16:4 ; ///<
+    UINT32                                                 MemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x20_STRUCT;
+
+// **** DxF0x24 Register Definition ****
+// Address
+#define DxF0x24_ADDRESS                                         0x24
+
+// Type
+#define DxF0x24_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x24_PrefMemBaseR_OFFSET                             0
+#define DxF0x24_PrefMemBaseR_WIDTH                              4
+#define DxF0x24_PrefMemBaseR_MASK                               0xf
+#define DxF0x24_PrefMemBase_31_20__OFFSET                       4
+#define DxF0x24_PrefMemBase_31_20__WIDTH                        12
+#define DxF0x24_PrefMemBase_31_20__MASK                         0xfff0
+#define DxF0x24_PrefMemLimitR_OFFSET                            16
+#define DxF0x24_PrefMemLimitR_WIDTH                             4
+#define DxF0x24_PrefMemLimitR_MASK                              0xf0000
+#define DxF0x24_PrefMemLimit_OFFSET                             20
+#define DxF0x24_PrefMemLimit_WIDTH                              12
+#define DxF0x24_PrefMemLimit_MASK                               0xfff00000
+
+/// DxF0x24
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PrefMemBaseR:4 ; ///<
+    UINT32                                       PrefMemBase_31_20_:12; ///<
+    UINT32                                            PrefMemLimitR:4 ; ///<
+    UINT32                                             PrefMemLimit:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x24_STRUCT;
+
+// **** DxF0x28 Register Definition ****
+// Address
+#define DxF0x28_ADDRESS                                         0x28
+
+// Type
+#define DxF0x28_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x28_PrefMemBase_63_32__OFFSET                       0
+#define DxF0x28_PrefMemBase_63_32__WIDTH                        32
+#define DxF0x28_PrefMemBase_63_32__MASK                         0xffffffff
+
+/// DxF0x28
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PrefMemBase_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x28_STRUCT;
+
+// **** DxF0x2C Register Definition ****
+// Address
+#define DxF0x2C_ADDRESS                                         0x2c
+
+// Type
+#define DxF0x2C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x2C_PrefMemLimit_63_32__OFFSET                      0
+#define DxF0x2C_PrefMemLimit_63_32__WIDTH                       32
+#define DxF0x2C_PrefMemLimit_63_32__MASK                        0xffffffff
+
+/// DxF0x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      PrefMemLimit_63_32_:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x2C_STRUCT;
+
+// **** DxF0x30 Register Definition ****
+// Address
+#define DxF0x30_ADDRESS                                         0x30
+
+// Type
+#define DxF0x30_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x30_IOBase_31_16__OFFSET                            0
+#define DxF0x30_IOBase_31_16__WIDTH                             16
+#define DxF0x30_IOBase_31_16__MASK                              0xffff
+#define DxF0x30_IOLimit_31_16__OFFSET                           16
+#define DxF0x30_IOLimit_31_16__WIDTH                            16
+#define DxF0x30_IOLimit_31_16__MASK                             0xffff0000
+
+/// DxF0x30
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            IOBase_31_16_:16; ///<
+    UINT32                                           IOLimit_31_16_:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x30_STRUCT;
+
+// **** DxF0x34 Register Definition ****
+// Address
+#define DxF0x34_ADDRESS                                         0x34
+
+// Type
+#define DxF0x34_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x34_CapPtr_OFFSET                                   0
+#define DxF0x34_CapPtr_WIDTH                                    8
+#define DxF0x34_CapPtr_MASK                                     0xff
+#define DxF0x34_Reserved_31_8_OFFSET                            8
+#define DxF0x34_Reserved_31_8_WIDTH                             24
+#define DxF0x34_Reserved_31_8_MASK                              0xffffff00
+
+/// DxF0x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CapPtr:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x34_STRUCT;
+
+// **** DxF0x3C Register Definition ****
+// Address
+#define DxF0x3C_ADDRESS                                         0x3c
+
+// Type
+#define DxF0x3C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x3C_IntLine_OFFSET                                  0
+#define DxF0x3C_IntLine_WIDTH                                   8
+#define DxF0x3C_IntLine_MASK                                    0xff
+#define DxF0x3C_IntPin_OFFSET                                   8
+#define DxF0x3C_IntPin_WIDTH                                    3
+#define DxF0x3C_IntPin_MASK                                     0x700
+#define DxF0x3C_IntPinR_OFFSET                                  11
+#define DxF0x3C_IntPinR_WIDTH                                   5
+#define DxF0x3C_IntPinR_MASK                                    0xf800
+#define DxF0x3C_ParityResponseEn_OFFSET                         16
+#define DxF0x3C_ParityResponseEn_WIDTH                          1
+#define DxF0x3C_ParityResponseEn_MASK                           0x10000
+#define DxF0x3C_SerrEn_OFFSET                                   17
+#define DxF0x3C_SerrEn_WIDTH                                    1
+#define DxF0x3C_SerrEn_MASK                                     0x20000
+#define DxF0x3C_IsaEn_OFFSET                                    18
+#define DxF0x3C_IsaEn_WIDTH                                     1
+#define DxF0x3C_IsaEn_MASK                                      0x40000
+#define DxF0x3C_VgaEn_OFFSET                                    19
+#define DxF0x3C_VgaEn_WIDTH                                     1
+#define DxF0x3C_VgaEn_MASK                                      0x80000
+#define DxF0x3C_Vga16En_OFFSET                                  20
+#define DxF0x3C_Vga16En_WIDTH                                   1
+#define DxF0x3C_Vga16En_MASK                                    0x100000
+#define DxF0x3C_MasterAbortMode_OFFSET                          21
+#define DxF0x3C_MasterAbortMode_WIDTH                           1
+#define DxF0x3C_MasterAbortMode_MASK                            0x200000
+#define DxF0x3C_SecondaryBusReset_OFFSET                        22
+#define DxF0x3C_SecondaryBusReset_WIDTH                         1
+#define DxF0x3C_SecondaryBusReset_MASK                          0x400000
+#define DxF0x3C_FastB2BCap_OFFSET                               23
+#define DxF0x3C_FastB2BCap_WIDTH                                1
+#define DxF0x3C_FastB2BCap_MASK                                 0x800000
+#define DxF0x3C_Reserved_31_24_OFFSET                           24
+#define DxF0x3C_Reserved_31_24_WIDTH                            8
+#define DxF0x3C_Reserved_31_24_MASK                             0xff000000
+
+/// DxF0x3C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  IntLine:8 ; ///<
+    UINT32                                                   IntPin:3 ; ///<
+    UINT32                                                  IntPinR:5 ; ///<
+    UINT32                                         ParityResponseEn:1 ; ///<
+    UINT32                                                   SerrEn:1 ; ///<
+    UINT32                                                    IsaEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                          MasterAbortMode:1 ; ///<
+    UINT32                                        SecondaryBusReset:1 ; ///<
+    UINT32                                               FastB2BCap:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x3C_STRUCT;
+
+// **** DxF0x50 Register Definition ****
+// Address
+#define DxF0x50_ADDRESS                                         0x50
+
+// Type
+#define DxF0x50_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x50_CapID_OFFSET                                    0
+#define DxF0x50_CapID_WIDTH                                     8
+#define DxF0x50_CapID_MASK                                      0xff
+#define DxF0x50_NextPtr_OFFSET                                  8
+#define DxF0x50_NextPtr_WIDTH                                   8
+#define DxF0x50_NextPtr_MASK                                    0xff00
+#define DxF0x50_Version_OFFSET                                  16
+#define DxF0x50_Version_WIDTH                                   3
+#define DxF0x50_Version_MASK                                    0x70000
+#define DxF0x50_PmeClock_OFFSET                                 19
+#define DxF0x50_PmeClock_WIDTH                                  1
+#define DxF0x50_PmeClock_MASK                                   0x80000
+#define DxF0x50_Reserved_20_20_OFFSET                           20
+#define DxF0x50_Reserved_20_20_WIDTH                            1
+#define DxF0x50_Reserved_20_20_MASK                             0x100000
+#define DxF0x50_DevSpecificInit_OFFSET                          21
+#define DxF0x50_DevSpecificInit_WIDTH                           1
+#define DxF0x50_DevSpecificInit_MASK                            0x200000
+#define DxF0x50_AuxCurrent_OFFSET                               22
+#define DxF0x50_AuxCurrent_WIDTH                                3
+#define DxF0x50_AuxCurrent_MASK                                 0x1c00000
+#define DxF0x50_D1Support_OFFSET                                25
+#define DxF0x50_D1Support_WIDTH                                 1
+#define DxF0x50_D1Support_MASK                                  0x2000000
+#define DxF0x50_D2Support_OFFSET                                26
+#define DxF0x50_D2Support_WIDTH                                 1
+#define DxF0x50_D2Support_MASK                                  0x4000000
+#define DxF0x50_PmeSupport_OFFSET                               27
+#define DxF0x50_PmeSupport_WIDTH                                5
+#define DxF0x50_PmeSupport_MASK                                 0xf8000000
+
+/// DxF0x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:3 ; ///<
+    UINT32                                                 PmeClock:1 ; ///<
+    UINT32                                           Reserved_20_20:1 ; ///<
+    UINT32                                          DevSpecificInit:1 ; ///<
+    UINT32                                               AuxCurrent:3 ; ///<
+    UINT32                                                D1Support:1 ; ///<
+    UINT32                                                D2Support:1 ; ///<
+    UINT32                                               PmeSupport:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x50_STRUCT;
+
+// **** DxF0x54 Register Definition ****
+// Address
+#define DxF0x54_ADDRESS                                         0x54
+
+// Type
+#define DxF0x54_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x54_PowerState_OFFSET                               0
+#define DxF0x54_PowerState_WIDTH                                2
+#define DxF0x54_PowerState_MASK                                 0x3
+#define DxF0x54_Reserved_2_2_OFFSET                             2
+#define DxF0x54_Reserved_2_2_WIDTH                              1
+#define DxF0x54_Reserved_2_2_MASK                               0x4
+#define DxF0x54_NoSoftReset_OFFSET                              3
+#define DxF0x54_NoSoftReset_WIDTH                               1
+#define DxF0x54_NoSoftReset_MASK                                0x8
+#define DxF0x54_Reserved_7_4_OFFSET                             4
+#define DxF0x54_Reserved_7_4_WIDTH                              4
+#define DxF0x54_Reserved_7_4_MASK                               0xf0
+#define DxF0x54_PmeEn_OFFSET                                    8
+#define DxF0x54_PmeEn_WIDTH                                     1
+#define DxF0x54_PmeEn_MASK                                      0x100
+#define DxF0x54_DataSelect_OFFSET                               9
+#define DxF0x54_DataSelect_WIDTH                                4
+#define DxF0x54_DataSelect_MASK                                 0x1e00
+#define DxF0x54_DataScale_OFFSET                                13
+#define DxF0x54_DataScale_WIDTH                                 2
+#define DxF0x54_DataScale_MASK                                  0x6000
+#define DxF0x54_PmeStatus_OFFSET                                15
+#define DxF0x54_PmeStatus_WIDTH                                 1
+#define DxF0x54_PmeStatus_MASK                                  0x8000
+#define DxF0x54_Reserved_21_16_OFFSET                           16
+#define DxF0x54_Reserved_21_16_WIDTH                            6
+#define DxF0x54_Reserved_21_16_MASK                             0x3f0000
+#define DxF0x54_B2B3Support_OFFSET                              22
+#define DxF0x54_B2B3Support_WIDTH                               1
+#define DxF0x54_B2B3Support_MASK                                0x400000
+#define DxF0x54_BusPwrEn_OFFSET                                 23
+#define DxF0x54_BusPwrEn_WIDTH                                  1
+#define DxF0x54_BusPwrEn_MASK                                   0x800000
+#define DxF0x54_PmeData_OFFSET                                  24
+#define DxF0x54_PmeData_WIDTH                                   8
+#define DxF0x54_PmeData_MASK                                    0xff000000
+
+/// DxF0x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PowerState:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                              NoSoftReset:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                    PmeEn:1 ; ///<
+    UINT32                                               DataSelect:4 ; ///<
+    UINT32                                                DataScale:2 ; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                           Reserved_21_16:6 ; ///<
+    UINT32                                              B2B3Support:1 ; ///<
+    UINT32                                                 BusPwrEn:1 ; ///<
+    UINT32                                                  PmeData:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x54_STRUCT;
+
+// **** DxF0x58 Register Definition ****
+// Address
+#define DxF0x58_ADDRESS                                         0x58
+
+// Type
+#define DxF0x58_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x58_CapID_OFFSET                                    0
+#define DxF0x58_CapID_WIDTH                                     8
+#define DxF0x58_CapID_MASK                                      0xff
+#define DxF0x58_NextPtr_OFFSET                                  8
+#define DxF0x58_NextPtr_WIDTH                                   8
+#define DxF0x58_NextPtr_MASK                                    0xff00
+#define DxF0x58_Version_OFFSET                                  16
+#define DxF0x58_Version_WIDTH                                   4
+#define DxF0x58_Version_MASK                                    0xf0000
+#define DxF0x58_DeviceType_OFFSET                               20
+#define DxF0x58_DeviceType_WIDTH                                4
+#define DxF0x58_DeviceType_MASK                                 0xf00000
+#define DxF0x58_SlotImplemented_OFFSET                          24
+#define DxF0x58_SlotImplemented_WIDTH                           1
+#define DxF0x58_SlotImplemented_MASK                            0x1000000
+#define DxF0x58_IntMessageNum_OFFSET                            25
+#define DxF0x58_IntMessageNum_WIDTH                             5
+#define DxF0x58_IntMessageNum_MASK                              0x3e000000
+#define DxF0x58_Reserved_31_30_OFFSET                           30
+#define DxF0x58_Reserved_31_30_WIDTH                            2
+#define DxF0x58_Reserved_31_30_MASK                             0xc0000000
+
+/// DxF0x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CapID:8 ; ///<
+    UINT32                                                  NextPtr:8 ; ///<
+    UINT32                                                  Version:4 ; ///<
+    UINT32                                               DeviceType:4 ; ///<
+    UINT32                                          SlotImplemented:1 ; ///<
+    UINT32                                            IntMessageNum:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x58_STRUCT;
+
+// **** DxF0x5C Register Definition ****
+// Address
+#define DxF0x5C_ADDRESS                                         0x5c
+
+// Type
+#define DxF0x5C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x5C_MaxPayloadSupport_OFFSET                        0
+#define DxF0x5C_MaxPayloadSupport_WIDTH                         3
+#define DxF0x5C_MaxPayloadSupport_MASK                          0x7
+#define DxF0x5C_PhantomFunc_OFFSET                              3
+#define DxF0x5C_PhantomFunc_WIDTH                               2
+#define DxF0x5C_PhantomFunc_MASK                                0x18
+#define DxF0x5C_ExtendedTag_OFFSET                              5
+#define DxF0x5C_ExtendedTag_WIDTH                               1
+#define DxF0x5C_ExtendedTag_MASK                                0x20
+#define DxF0x5C_L0SAcceptableLatency_OFFSET                     6
+#define DxF0x5C_L0SAcceptableLatency_WIDTH                      3
+#define DxF0x5C_L0SAcceptableLatency_MASK                       0x1c0
+#define DxF0x5C_L1AcceptableLatency_OFFSET                      9
+#define DxF0x5C_L1AcceptableLatency_WIDTH                       3
+#define DxF0x5C_L1AcceptableLatency_MASK                        0xe00
+#define DxF0x5C_Reserved_14_12_OFFSET                           12
+#define DxF0x5C_Reserved_14_12_WIDTH                            3
+#define DxF0x5C_Reserved_14_12_MASK                             0x7000
+#define DxF0x5C_RoleBasedErrReporting_OFFSET                    15
+#define DxF0x5C_RoleBasedErrReporting_WIDTH                     1
+#define DxF0x5C_RoleBasedErrReporting_MASK                      0x8000
+#define DxF0x5C_Reserved_17_16_OFFSET                           16
+#define DxF0x5C_Reserved_17_16_WIDTH                            2
+#define DxF0x5C_Reserved_17_16_MASK                             0x30000
+#define DxF0x5C_CapturedSlotPowerLimit_OFFSET                   18
+#define DxF0x5C_CapturedSlotPowerLimit_WIDTH                    8
+#define DxF0x5C_CapturedSlotPowerLimit_MASK                     0x3fc0000
+#define DxF0x5C_CapturedSlotPowerScale_OFFSET                   26
+#define DxF0x5C_CapturedSlotPowerScale_WIDTH                    2
+#define DxF0x5C_CapturedSlotPowerScale_MASK                     0xc000000
+#define DxF0x5C_FlrCapable_OFFSET                               28
+#define DxF0x5C_FlrCapable_WIDTH                                1
+#define DxF0x5C_FlrCapable_MASK                                 0x10000000
+#define DxF0x5C_Reserved_31_29_OFFSET                           29
+#define DxF0x5C_Reserved_31_29_WIDTH                            3
+#define DxF0x5C_Reserved_31_29_MASK                             0xe0000000
+
+/// DxF0x5C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        MaxPayloadSupport:3 ; ///<
+    UINT32                                              PhantomFunc:2 ; ///<
+    UINT32                                              ExtendedTag:1 ; ///<
+    UINT32                                     L0SAcceptableLatency:3 ; ///<
+    UINT32                                      L1AcceptableLatency:3 ; ///<
+    UINT32                                           Reserved_14_12:3 ; ///<
+    UINT32                                    RoleBasedErrReporting:1 ; ///<
+    UINT32                                           Reserved_17_16:2 ; ///<
+    UINT32                                   CapturedSlotPowerLimit:8 ; ///<
+    UINT32                                   CapturedSlotPowerScale:2 ; ///<
+    UINT32                                               FlrCapable:1 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x5C_STRUCT;
+
+// **** DxF0x60 Register Definition ****
+// Address
+#define DxF0x60_ADDRESS                                         0x60
+
+// Type
+#define DxF0x60_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x60_CorrErrEn_OFFSET                                0
+#define DxF0x60_CorrErrEn_WIDTH                                 1
+#define DxF0x60_CorrErrEn_MASK                                  0x1
+#define DxF0x60_NonFatalErrEn_OFFSET                            1
+#define DxF0x60_NonFatalErrEn_WIDTH                             1
+#define DxF0x60_NonFatalErrEn_MASK                              0x2
+#define DxF0x60_FatalErrEn_OFFSET                               2
+#define DxF0x60_FatalErrEn_WIDTH                                1
+#define DxF0x60_FatalErrEn_MASK                                 0x4
+#define DxF0x60_UsrReportEn_OFFSET                              3
+#define DxF0x60_UsrReportEn_WIDTH                               1
+#define DxF0x60_UsrReportEn_MASK                                0x8
+#define DxF0x60_RelaxedOrdEn_OFFSET                             4
+#define DxF0x60_RelaxedOrdEn_WIDTH                              1
+#define DxF0x60_RelaxedOrdEn_MASK                               0x10
+#define DxF0x60_MaxPayloadSize_OFFSET                           5
+#define DxF0x60_MaxPayloadSize_WIDTH                            3
+#define DxF0x60_MaxPayloadSize_MASK                             0xe0
+#define DxF0x60_ExtendedTagEn_OFFSET                            8
+#define DxF0x60_ExtendedTagEn_WIDTH                             1
+#define DxF0x60_ExtendedTagEn_MASK                              0x100
+#define DxF0x60_PhantomFuncEn_OFFSET                            9
+#define DxF0x60_PhantomFuncEn_WIDTH                             1
+#define DxF0x60_PhantomFuncEn_MASK                              0x200
+#define DxF0x60_AuxPowerPmEn_OFFSET                             10
+#define DxF0x60_AuxPowerPmEn_WIDTH                              1
+#define DxF0x60_AuxPowerPmEn_MASK                               0x400
+#define DxF0x60_NoSnoopEnable_OFFSET                            11
+#define DxF0x60_NoSnoopEnable_WIDTH                             1
+#define DxF0x60_NoSnoopEnable_MASK                              0x800
+#define DxF0x60_MaxRequestSize_OFFSET                           12
+#define DxF0x60_MaxRequestSize_WIDTH                            3
+#define DxF0x60_MaxRequestSize_MASK                             0x7000
+#define DxF0x60_BridgeCfgRetryEn_OFFSET                         15
+#define DxF0x60_BridgeCfgRetryEn_WIDTH                          1
+#define DxF0x60_BridgeCfgRetryEn_MASK                           0x8000
+#define DxF0x60_CorrErr_OFFSET                                  16
+#define DxF0x60_CorrErr_WIDTH                                   1
+#define DxF0x60_CorrErr_MASK                                    0x10000
+#define DxF0x60_NonFatalErr_OFFSET                              17
+#define DxF0x60_NonFatalErr_WIDTH                               1
+#define DxF0x60_NonFatalErr_MASK                                0x20000
+#define DxF0x60_FatalErr_OFFSET                                 18
+#define DxF0x60_FatalErr_WIDTH                                  1
+#define DxF0x60_FatalErr_MASK                                   0x40000
+#define DxF0x60_UsrDetected_OFFSET                              19
+#define DxF0x60_UsrDetected_WIDTH                               1
+#define DxF0x60_UsrDetected_MASK                                0x80000
+#define DxF0x60_AuxPwr_OFFSET                                   20
+#define DxF0x60_AuxPwr_WIDTH                                    1
+#define DxF0x60_AuxPwr_MASK                                     0x100000
+#define DxF0x60_TransactionsPending_OFFSET                      21
+#define DxF0x60_TransactionsPending_WIDTH                       1
+#define DxF0x60_TransactionsPending_MASK                        0x200000
+#define DxF0x60_Reserved_31_22_OFFSET                           22
+#define DxF0x60_Reserved_31_22_WIDTH                            10
+#define DxF0x60_Reserved_31_22_MASK                             0xffc00000
+
+/// DxF0x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                CorrErrEn:1 ; ///<
+    UINT32                                            NonFatalErrEn:1 ; ///<
+    UINT32                                               FatalErrEn:1 ; ///<
+    UINT32                                              UsrReportEn:1 ; ///<
+    UINT32                                             RelaxedOrdEn:1 ; ///<
+    UINT32                                           MaxPayloadSize:3 ; ///<
+    UINT32                                            ExtendedTagEn:1 ; ///<
+    UINT32                                            PhantomFuncEn:1 ; ///<
+    UINT32                                             AuxPowerPmEn:1 ; ///<
+    UINT32                                            NoSnoopEnable:1 ; ///<
+    UINT32                                           MaxRequestSize:3 ; ///<
+    UINT32                                         BridgeCfgRetryEn:1 ; ///<
+    UINT32                                                  CorrErr:1 ; ///<
+    UINT32                                              NonFatalErr:1 ; ///<
+    UINT32                                                 FatalErr:1 ; ///<
+    UINT32                                              UsrDetected:1 ; ///<
+    UINT32                                                   AuxPwr:1 ; ///<
+    UINT32                                      TransactionsPending:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x60_STRUCT;
+
+// **** DxF0x64 Register Definition ****
+// Address
+#define DxF0x64_ADDRESS                                         0x64
+
+// Type
+#define DxF0x64_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x64_LinkSpeed_OFFSET                                0
+#define DxF0x64_LinkSpeed_WIDTH                                 4
+#define DxF0x64_LinkSpeed_MASK                                  0xf
+#define DxF0x64_LinkWidth_OFFSET                                4
+#define DxF0x64_LinkWidth_WIDTH                                 6
+#define DxF0x64_LinkWidth_MASK                                  0x3f0
+#define DxF0x64_PMSupport_OFFSET                                10
+#define DxF0x64_PMSupport_WIDTH                                 2
+#define DxF0x64_PMSupport_MASK                                  0xc00
+#define DxF0x64_L0sExitLatency_OFFSET                           12
+#define DxF0x64_L0sExitLatency_WIDTH                            3
+#define DxF0x64_L0sExitLatency_MASK                             0x7000
+#define DxF0x64_L1ExitLatency_OFFSET                            15
+#define DxF0x64_L1ExitLatency_WIDTH                             3
+#define DxF0x64_L1ExitLatency_MASK                              0x38000
+#define DxF0x64_ClockPowerManagement_OFFSET                     18
+#define DxF0x64_ClockPowerManagement_WIDTH                      1
+#define DxF0x64_ClockPowerManagement_MASK                       0x40000
+#define DxF0x64_SurpriseDownErrReporting_OFFSET                 19
+#define DxF0x64_SurpriseDownErrReporting_WIDTH                  1
+#define DxF0x64_SurpriseDownErrReporting_MASK                   0x80000
+#define DxF0x64_DlActiveReportingCapable_OFFSET                 20
+#define DxF0x64_DlActiveReportingCapable_WIDTH                  1
+#define DxF0x64_DlActiveReportingCapable_MASK                   0x100000
+#define DxF0x64_LinkBWNotificationCap_OFFSET                    21
+#define DxF0x64_LinkBWNotificationCap_WIDTH                     1
+#define DxF0x64_LinkBWNotificationCap_MASK                      0x200000
+#define DxF0x64_AspmOptionalityCompliance_OFFSET                22
+#define DxF0x64_AspmOptionalityCompliance_WIDTH                 1
+#define DxF0x64_AspmOptionalityCompliance_MASK                  0x400000
+#define DxF0x64_Reserved_23_23_OFFSET                           23
+#define DxF0x64_Reserved_23_23_WIDTH                            1
+#define DxF0x64_Reserved_23_23_MASK                             0x800000
+#define DxF0x64_PortNumber_OFFSET                               24
+#define DxF0x64_PortNumber_WIDTH                                8
+#define DxF0x64_PortNumber_MASK                                 0xff000000
+
+/// DxF0x64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LinkSpeed:4 ; ///<
+    UINT32                                                LinkWidth:6 ; ///<
+    UINT32                                                PMSupport:2 ; ///<
+    UINT32                                           L0sExitLatency:3 ; ///<
+    UINT32                                            L1ExitLatency:3 ; ///<
+    UINT32                                     ClockPowerManagement:1 ; ///<
+    UINT32                                 SurpriseDownErrReporting:1 ; ///<
+    UINT32                                 DlActiveReportingCapable:1 ; ///<
+    UINT32                                    LinkBWNotificationCap:1 ; ///<
+    UINT32                                AspmOptionalityCompliance:1 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                               PortNumber:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x64_STRUCT;
+
+// **** DxF0x68 Register Definition ****
+// Address
+#define DxF0x68_ADDRESS                                         0x68
+
+// Type
+#define DxF0x68_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x68_PmControl_OFFSET                                0
+#define DxF0x68_PmControl_WIDTH                                 2
+#define DxF0x68_PmControl_MASK                                  0x3
+#define DxF0x68_Reserved_2_2_OFFSET                             2
+#define DxF0x68_Reserved_2_2_WIDTH                              1
+#define DxF0x68_Reserved_2_2_MASK                               0x4
+#define DxF0x68_ReadCplBoundary_OFFSET                          3
+#define DxF0x68_ReadCplBoundary_WIDTH                           1
+#define DxF0x68_ReadCplBoundary_MASK                            0x8
+#define DxF0x68_LinkDis_OFFSET                                  4
+#define DxF0x68_LinkDis_WIDTH                                   1
+#define DxF0x68_LinkDis_MASK                                    0x10
+#define DxF0x68_RetrainLink_OFFSET                              5
+#define DxF0x68_RetrainLink_WIDTH                               1
+#define DxF0x68_RetrainLink_MASK                                0x20
+#define DxF0x68_CommonClockCfg_OFFSET                           6
+#define DxF0x68_CommonClockCfg_WIDTH                            1
+#define DxF0x68_CommonClockCfg_MASK                             0x40
+#define DxF0x68_ExtendedSync_OFFSET                             7
+#define DxF0x68_ExtendedSync_WIDTH                              1
+#define DxF0x68_ExtendedSync_MASK                               0x80
+#define DxF0x68_ClockPowerManagementEn_OFFSET                   8
+#define DxF0x68_ClockPowerManagementEn_WIDTH                    1
+#define DxF0x68_ClockPowerManagementEn_MASK                     0x100
+#define DxF0x68_HWAutonomousWidthDisable_OFFSET                 9
+#define DxF0x68_HWAutonomousWidthDisable_WIDTH                  1
+#define DxF0x68_HWAutonomousWidthDisable_MASK                   0x200
+#define DxF0x68_LinkBWManagementEn_OFFSET                       10
+#define DxF0x68_LinkBWManagementEn_WIDTH                        1
+#define DxF0x68_LinkBWManagementEn_MASK                         0x400
+#define DxF0x68_LinkAutonomousBWIntEn_OFFSET                    11
+#define DxF0x68_LinkAutonomousBWIntEn_WIDTH                     1
+#define DxF0x68_LinkAutonomousBWIntEn_MASK                      0x800
+#define DxF0x68_Reserved_15_12_OFFSET                           12
+#define DxF0x68_Reserved_15_12_WIDTH                            4
+#define DxF0x68_Reserved_15_12_MASK                             0xf000
+#define DxF0x68_LinkSpeed_OFFSET                                16
+#define DxF0x68_LinkSpeed_WIDTH                                 4
+#define DxF0x68_LinkSpeed_MASK                                  0xf0000
+#define DxF0x68_NegotiatedLinkWidth_OFFSET                      20
+#define DxF0x68_NegotiatedLinkWidth_WIDTH                       6
+#define DxF0x68_NegotiatedLinkWidth_MASK                        0x3f00000
+#define DxF0x68_Reserved_26_26_OFFSET                           26
+#define DxF0x68_Reserved_26_26_WIDTH                            1
+#define DxF0x68_Reserved_26_26_MASK                             0x4000000
+#define DxF0x68_LinkTraining_OFFSET                             27
+#define DxF0x68_LinkTraining_WIDTH                              1
+#define DxF0x68_LinkTraining_MASK                               0x8000000
+#define DxF0x68_SlotClockCfg_OFFSET                             28
+#define DxF0x68_SlotClockCfg_WIDTH                              1
+#define DxF0x68_SlotClockCfg_MASK                               0x10000000
+#define DxF0x68_DlActive_OFFSET                                 29
+#define DxF0x68_DlActive_WIDTH                                  1
+#define DxF0x68_DlActive_MASK                                   0x20000000
+#define DxF0x68_LinkBWManagementStatus_OFFSET                   30
+#define DxF0x68_LinkBWManagementStatus_WIDTH                    1
+#define DxF0x68_LinkBWManagementStatus_MASK                     0x40000000
+#define DxF0x68_LinkAutonomousBWStatus_OFFSET                   31
+#define DxF0x68_LinkAutonomousBWStatus_WIDTH                    1
+#define DxF0x68_LinkAutonomousBWStatus_MASK                     0x80000000
+
+/// DxF0x68
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                PmControl:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          ReadCplBoundary:1 ; ///<
+    UINT32                                                  LinkDis:1 ; ///<
+    UINT32                                              RetrainLink:1 ; ///<
+    UINT32                                           CommonClockCfg:1 ; ///<
+    UINT32                                             ExtendedSync:1 ; ///<
+    UINT32                                   ClockPowerManagementEn:1 ; ///<
+    UINT32                                 HWAutonomousWidthDisable:1 ; ///<
+    UINT32                                       LinkBWManagementEn:1 ; ///<
+    UINT32                                    LinkAutonomousBWIntEn:1 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                LinkSpeed:4 ; ///<
+    UINT32                                      NegotiatedLinkWidth:6 ; ///<
+    UINT32                                           Reserved_26_26:1 ; ///<
+    UINT32                                             LinkTraining:1 ; ///<
+    UINT32                                             SlotClockCfg:1 ; ///<
+    UINT32                                                 DlActive:1 ; ///<
+    UINT32                                   LinkBWManagementStatus:1 ; ///<
+    UINT32                                   LinkAutonomousBWStatus:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x68_STRUCT;
+
+// **** DxF0x6C Register Definition ****
+// Address
+#define DxF0x6C_ADDRESS                                         0x6c
+
+// Type
+#define DxF0x6C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x6C_AttnButtonPresent_OFFSET                        0
+#define DxF0x6C_AttnButtonPresent_WIDTH                         1
+#define DxF0x6C_AttnButtonPresent_MASK                          0x1
+#define DxF0x6C_PwrControllerPresent_OFFSET                     1
+#define DxF0x6C_PwrControllerPresent_WIDTH                      1
+#define DxF0x6C_PwrControllerPresent_MASK                       0x2
+#define DxF0x6C_MrlSensorPresent_OFFSET                         2
+#define DxF0x6C_MrlSensorPresent_WIDTH                          1
+#define DxF0x6C_MrlSensorPresent_MASK                           0x4
+#define DxF0x6C_AttnIndicatorPresent_OFFSET                     3
+#define DxF0x6C_AttnIndicatorPresent_WIDTH                      1
+#define DxF0x6C_AttnIndicatorPresent_MASK                       0x8
+#define DxF0x6C_PwrIndicatorPresent_OFFSET                      4
+#define DxF0x6C_PwrIndicatorPresent_WIDTH                       1
+#define DxF0x6C_PwrIndicatorPresent_MASK                        0x10
+#define DxF0x6C_HotplugSurprise_OFFSET                          5
+#define DxF0x6C_HotplugSurprise_WIDTH                           1
+#define DxF0x6C_HotplugSurprise_MASK                            0x20
+#define DxF0x6C_HotplugCapable_OFFSET                           6
+#define DxF0x6C_HotplugCapable_WIDTH                            1
+#define DxF0x6C_HotplugCapable_MASK                             0x40
+#define DxF0x6C_SlotPwrLimitValue_OFFSET                        7
+#define DxF0x6C_SlotPwrLimitValue_WIDTH                         8
+#define DxF0x6C_SlotPwrLimitValue_MASK                          0x7f80
+#define DxF0x6C_SlotPwrLimitScale_OFFSET                        15
+#define DxF0x6C_SlotPwrLimitScale_WIDTH                         2
+#define DxF0x6C_SlotPwrLimitScale_MASK                          0x18000
+#define DxF0x6C_ElecMechIlPresent_OFFSET                        17
+#define DxF0x6C_ElecMechIlPresent_WIDTH                         1
+#define DxF0x6C_ElecMechIlPresent_MASK                          0x20000
+#define DxF0x6C_NoCmdCplSupport_OFFSET                          18
+#define DxF0x6C_NoCmdCplSupport_WIDTH                           1
+#define DxF0x6C_NoCmdCplSupport_MASK                            0x40000
+#define DxF0x6C_PhysicalSlotNumber_OFFSET                       19
+#define DxF0x6C_PhysicalSlotNumber_WIDTH                        13
+#define DxF0x6C_PhysicalSlotNumber_MASK                         0xfff80000
+
+/// DxF0x6C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AttnButtonPresent:1 ; ///<
+    UINT32                                     PwrControllerPresent:1 ; ///<
+    UINT32                                         MrlSensorPresent:1 ; ///<
+    UINT32                                     AttnIndicatorPresent:1 ; ///<
+    UINT32                                      PwrIndicatorPresent:1 ; ///<
+    UINT32                                          HotplugSurprise:1 ; ///<
+    UINT32                                           HotplugCapable:1 ; ///<
+    UINT32                                        SlotPwrLimitValue:8 ; ///<
+    UINT32                                        SlotPwrLimitScale:2 ; ///<
+    UINT32                                        ElecMechIlPresent:1 ; ///<
+    UINT32                                          NoCmdCplSupport:1 ; ///<
+    UINT32                                       PhysicalSlotNumber:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x6C_STRUCT;
+
+// **** DxF0x70 Register Definition ****
+// Address
+#define DxF0x70_ADDRESS                                         0x70
+
+// Type
+#define DxF0x70_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x70_AttnButtonPressedEn_OFFSET                      0
+#define DxF0x70_AttnButtonPressedEn_WIDTH                       1
+#define DxF0x70_AttnButtonPressedEn_MASK                        0x1
+#define DxF0x70_PwrFaultDetectedEn_OFFSET                       1
+#define DxF0x70_PwrFaultDetectedEn_WIDTH                        1
+#define DxF0x70_PwrFaultDetectedEn_MASK                         0x2
+#define DxF0x70_MrlSensorChangedEn_OFFSET                       2
+#define DxF0x70_MrlSensorChangedEn_WIDTH                        1
+#define DxF0x70_MrlSensorChangedEn_MASK                         0x4
+#define DxF0x70_PresenceDetectChangedEn_OFFSET                  3
+#define DxF0x70_PresenceDetectChangedEn_WIDTH                   1
+#define DxF0x70_PresenceDetectChangedEn_MASK                    0x8
+#define DxF0x70_CmdCplIntrEn_OFFSET                             4
+#define DxF0x70_CmdCplIntrEn_WIDTH                              1
+#define DxF0x70_CmdCplIntrEn_MASK                               0x10
+#define DxF0x70_HotplugIntrEn_OFFSET                            5
+#define DxF0x70_HotplugIntrEn_WIDTH                             1
+#define DxF0x70_HotplugIntrEn_MASK                              0x20
+#define DxF0x70_AttnIndicatorControl_OFFSET                     6
+#define DxF0x70_AttnIndicatorControl_WIDTH                      2
+#define DxF0x70_AttnIndicatorControl_MASK                       0xc0
+#define DxF0x70_PwrIndicatorCntl_OFFSET                         8
+#define DxF0x70_PwrIndicatorCntl_WIDTH                          2
+#define DxF0x70_PwrIndicatorCntl_MASK                           0x300
+#define DxF0x70_PwrControllerCntl_OFFSET                        10
+#define DxF0x70_PwrControllerCntl_WIDTH                         1
+#define DxF0x70_PwrControllerCntl_MASK                          0x400
+#define DxF0x70_ElecMechIlCntl_OFFSET                           11
+#define DxF0x70_ElecMechIlCntl_WIDTH                            1
+#define DxF0x70_ElecMechIlCntl_MASK                             0x800
+#define DxF0x70_DlStateChangedEn_OFFSET                         12
+#define DxF0x70_DlStateChangedEn_WIDTH                          1
+#define DxF0x70_DlStateChangedEn_MASK                           0x1000
+#define DxF0x70_Reserved_15_13_OFFSET                           13
+#define DxF0x70_Reserved_15_13_WIDTH                            3
+#define DxF0x70_Reserved_15_13_MASK                             0xe000
+#define DxF0x70_AttnButtonPressed_OFFSET                        16
+#define DxF0x70_AttnButtonPressed_WIDTH                         1
+#define DxF0x70_AttnButtonPressed_MASK                          0x10000
+#define DxF0x70_PwrFaultDetected_OFFSET                         17
+#define DxF0x70_PwrFaultDetected_WIDTH                          1
+#define DxF0x70_PwrFaultDetected_MASK                           0x20000
+#define DxF0x70_MrlSensorChanged_OFFSET                         18
+#define DxF0x70_MrlSensorChanged_WIDTH                          1
+#define DxF0x70_MrlSensorChanged_MASK                           0x40000
+#define DxF0x70_PresenceDetectChanged_OFFSET                    19
+#define DxF0x70_PresenceDetectChanged_WIDTH                     1
+#define DxF0x70_PresenceDetectChanged_MASK                      0x80000
+#define DxF0x70_CmdCpl_OFFSET                                   20
+#define DxF0x70_CmdCpl_WIDTH                                    1
+#define DxF0x70_CmdCpl_MASK                                     0x100000
+#define DxF0x70_MrlSensorState_OFFSET                           21
+#define DxF0x70_MrlSensorState_WIDTH                            1
+#define DxF0x70_MrlSensorState_MASK                             0x200000
+#define DxF0x70_PresenceDetectState_OFFSET                      22
+#define DxF0x70_PresenceDetectState_WIDTH                       1
+#define DxF0x70_PresenceDetectState_MASK                        0x400000
+#define DxF0x70_ElecMechIlSts_OFFSET                            23
+#define DxF0x70_ElecMechIlSts_WIDTH                             1
+#define DxF0x70_ElecMechIlSts_MASK                              0x800000
+#define DxF0x70_DlStateChanged_OFFSET                           24
+#define DxF0x70_DlStateChanged_WIDTH                            1
+#define DxF0x70_DlStateChanged_MASK                             0x1000000
+#define DxF0x70_Reserved_31_25_OFFSET                           25
+#define DxF0x70_Reserved_31_25_WIDTH                            7
+#define DxF0x70_Reserved_31_25_MASK                             0xfe000000
+
+/// DxF0x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      AttnButtonPressedEn:1 ; ///<
+    UINT32                                       PwrFaultDetectedEn:1 ; ///<
+    UINT32                                       MrlSensorChangedEn:1 ; ///<
+    UINT32                                  PresenceDetectChangedEn:1 ; ///<
+    UINT32                                             CmdCplIntrEn:1 ; ///<
+    UINT32                                            HotplugIntrEn:1 ; ///<
+    UINT32                                     AttnIndicatorControl:2 ; ///<
+    UINT32                                         PwrIndicatorCntl:2 ; ///<
+    UINT32                                        PwrControllerCntl:1 ; ///<
+    UINT32                                           ElecMechIlCntl:1 ; ///<
+    UINT32                                         DlStateChangedEn:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                        AttnButtonPressed:1 ; ///<
+    UINT32                                         PwrFaultDetected:1 ; ///<
+    UINT32                                         MrlSensorChanged:1 ; ///<
+    UINT32                                    PresenceDetectChanged:1 ; ///<
+    UINT32                                                   CmdCpl:1 ; ///<
+    UINT32                                           MrlSensorState:1 ; ///<
+    UINT32                                      PresenceDetectState:1 ; ///<
+    UINT32                                            ElecMechIlSts:1 ; ///<
+    UINT32                                           DlStateChanged:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x70_STRUCT;
+
+// **** DxF0x74 Register Definition ****
+// Address
+#define DxF0x74_ADDRESS                                         0x74
+
+// Type
+#define DxF0x74_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x74_SerrOnCorrErrEn_OFFSET                          0
+#define DxF0x74_SerrOnCorrErrEn_WIDTH                           1
+#define DxF0x74_SerrOnCorrErrEn_MASK                            0x1
+#define DxF0x74_SerrOnNonFatalErrEn_OFFSET                      1
+#define DxF0x74_SerrOnNonFatalErrEn_WIDTH                       1
+#define DxF0x74_SerrOnNonFatalErrEn_MASK                        0x2
+#define DxF0x74_SerrOnFatalErrEn_OFFSET                         2
+#define DxF0x74_SerrOnFatalErrEn_WIDTH                          1
+#define DxF0x74_SerrOnFatalErrEn_MASK                           0x4
+#define DxF0x74_PmIntEn_OFFSET                                  3
+#define DxF0x74_PmIntEn_WIDTH                                   1
+#define DxF0x74_PmIntEn_MASK                                    0x8
+#define DxF0x74_CrsSoftVisibilityEn_OFFSET                      4
+#define DxF0x74_CrsSoftVisibilityEn_WIDTH                       1
+#define DxF0x74_CrsSoftVisibilityEn_MASK                        0x10
+#define DxF0x74_Reserved_15_5_OFFSET                            5
+#define DxF0x74_Reserved_15_5_WIDTH                             11
+#define DxF0x74_Reserved_15_5_MASK                              0xffe0
+#define DxF0x74_CrsSoftVisibility_OFFSET                        16
+#define DxF0x74_CrsSoftVisibility_WIDTH                         1
+#define DxF0x74_CrsSoftVisibility_MASK                          0x10000
+#define DxF0x74_Reserved_31_17_OFFSET                           17
+#define DxF0x74_Reserved_31_17_WIDTH                            15
+#define DxF0x74_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x74
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          SerrOnCorrErrEn:1 ; ///<
+    UINT32                                      SerrOnNonFatalErrEn:1 ; ///<
+    UINT32                                         SerrOnFatalErrEn:1 ; ///<
+    UINT32                                                  PmIntEn:1 ; ///<
+    UINT32                                      CrsSoftVisibilityEn:1 ; ///<
+    UINT32                                            Reserved_15_5:11; ///<
+    UINT32                                        CrsSoftVisibility:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x74_STRUCT;
+
+// **** DxF0x78 Register Definition ****
+// Address
+#define DxF0x78_ADDRESS                                         0x78
+
+// Type
+#define DxF0x78_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x78_PmeRequestorId_OFFSET                           0
+#define DxF0x78_PmeRequestorId_WIDTH                            16
+#define DxF0x78_PmeRequestorId_MASK                             0xffff
+#define DxF0x78_PmeStatus_OFFSET                                16
+#define DxF0x78_PmeStatus_WIDTH                                 1
+#define DxF0x78_PmeStatus_MASK                                  0x10000
+#define DxF0x78_PmePending_OFFSET                               17
+#define DxF0x78_PmePending_WIDTH                                1
+#define DxF0x78_PmePending_MASK                                 0x20000
+#define DxF0x78_Reserved_31_18_OFFSET                           18
+#define DxF0x78_Reserved_31_18_WIDTH                            14
+#define DxF0x78_Reserved_31_18_MASK                             0xfffc0000
+
+/// DxF0x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PmeRequestorId:16; ///<
+    UINT32                                                PmeStatus:1 ; ///<
+    UINT32                                               PmePending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x78_STRUCT;
+
+// **** DxF0x7C Register Definition ****
+// Address
+#define DxF0x7C_ADDRESS                                         0x7c
+
+// Type
+#define DxF0x7C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x7C_CplTimeoutRangeSup_OFFSET                       0
+#define DxF0x7C_CplTimeoutRangeSup_WIDTH                        4
+#define DxF0x7C_CplTimeoutRangeSup_MASK                         0xf
+#define DxF0x7C_CplTimeoutDisSup_OFFSET                         4
+#define DxF0x7C_CplTimeoutDisSup_WIDTH                          1
+#define DxF0x7C_CplTimeoutDisSup_MASK                           0x10
+#define DxF0x7C_AriForwardingSupported_OFFSET                   5
+#define DxF0x7C_AriForwardingSupported_WIDTH                    1
+#define DxF0x7C_AriForwardingSupported_MASK                     0x20
+#define DxF0x7C_Reserved_31_6_OFFSET                            6
+#define DxF0x7C_Reserved_31_6_WIDTH                             26
+#define DxF0x7C_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x7C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       CplTimeoutRangeSup:4 ; ///<
+    UINT32                                         CplTimeoutDisSup:1 ; ///<
+    UINT32                                   AriForwardingSupported:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x7C_STRUCT;
+
+// **** DxF0x80 Register Definition ****
+// Address
+#define DxF0x80_ADDRESS                                         0x80
+
+// Type
+#define DxF0x80_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x80_CplTimeoutValue_OFFSET                          0
+#define DxF0x80_CplTimeoutValue_WIDTH                           4
+#define DxF0x80_CplTimeoutValue_MASK                            0xf
+#define DxF0x80_CplTimeoutDis_OFFSET                            4
+#define DxF0x80_CplTimeoutDis_WIDTH                             1
+#define DxF0x80_CplTimeoutDis_MASK                              0x10
+#define DxF0x80_AriForwardingEn_OFFSET                          5
+#define DxF0x80_AriForwardingEn_WIDTH                           1
+#define DxF0x80_AriForwardingEn_MASK                            0x20
+#define DxF0x80_Reserved_31_6_OFFSET                            6
+#define DxF0x80_Reserved_31_6_WIDTH                             26
+#define DxF0x80_Reserved_31_6_MASK                              0xffffffc0
+
+/// DxF0x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CplTimeoutValue:4 ; ///<
+    UINT32                                            CplTimeoutDis:1 ; ///<
+    UINT32                                          AriForwardingEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x80_STRUCT;
+
+// **** DxF0x84 Register Definition ****
+// Address
+#define DxF0x84_ADDRESS                                         0x84
+
+// Type
+#define DxF0x84_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x84_Reserved_31_0_OFFSET                            0
+#define DxF0x84_Reserved_31_0_WIDTH                             32
+#define DxF0x84_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x84
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x84_STRUCT;
+
+// **** DxF0x88 Register Definition ****
+// Address
+#define DxF0x88_ADDRESS                                         0x88
+
+// Type
+#define DxF0x88_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x88_TargetLinkSpeed_OFFSET                          0
+#define DxF0x88_TargetLinkSpeed_WIDTH                           4
+#define DxF0x88_TargetLinkSpeed_MASK                            0xf
+#define DxF0x88_EnterCompliance_OFFSET                          4
+#define DxF0x88_EnterCompliance_WIDTH                           1
+#define DxF0x88_EnterCompliance_MASK                            0x10
+#define DxF0x88_HwAutonomousSpeedDisable_OFFSET                 5
+#define DxF0x88_HwAutonomousSpeedDisable_WIDTH                  1
+#define DxF0x88_HwAutonomousSpeedDisable_MASK                   0x20
+#define DxF0x88_SelectableDeemphasis_OFFSET                     6
+#define DxF0x88_SelectableDeemphasis_WIDTH                      1
+#define DxF0x88_SelectableDeemphasis_MASK                       0x40
+#define DxF0x88_XmitMargin_OFFSET                               7
+#define DxF0x88_XmitMargin_WIDTH                                3
+#define DxF0x88_XmitMargin_MASK                                 0x380
+#define DxF0x88_EnterModCompliance_OFFSET                       10
+#define DxF0x88_EnterModCompliance_WIDTH                        1
+#define DxF0x88_EnterModCompliance_MASK                         0x400
+#define DxF0x88_ComplianceSOS_OFFSET                            11
+#define DxF0x88_ComplianceSOS_WIDTH                             1
+#define DxF0x88_ComplianceSOS_MASK                              0x800
+#define DxF0x88_ComplianceDeemphasis_OFFSET                     12
+#define DxF0x88_ComplianceDeemphasis_WIDTH                      1
+#define DxF0x88_ComplianceDeemphasis_MASK                       0x1000
+#define DxF0x88_Reserved_15_13_OFFSET                           13
+#define DxF0x88_Reserved_15_13_WIDTH                            3
+#define DxF0x88_Reserved_15_13_MASK                             0xe000
+#define DxF0x88_CurDeemphasisLevel_OFFSET                       16
+#define DxF0x88_CurDeemphasisLevel_WIDTH                        1
+#define DxF0x88_CurDeemphasisLevel_MASK                         0x10000
+#define DxF0x88_Reserved_31_17_OFFSET                           17
+#define DxF0x88_Reserved_31_17_WIDTH                            15
+#define DxF0x88_Reserved_31_17_MASK                             0xfffe0000
+
+/// DxF0x88
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          TargetLinkSpeed:4 ; ///<
+    UINT32                                          EnterCompliance:1 ; ///<
+    UINT32                                 HwAutonomousSpeedDisable:1 ; ///<
+    UINT32                                     SelectableDeemphasis:1 ; ///<
+    UINT32                                               XmitMargin:3 ; ///<
+    UINT32                                       EnterModCompliance:1 ; ///<
+    UINT32                                            ComplianceSOS:1 ; ///<
+    UINT32                                     ComplianceDeemphasis:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                       CurDeemphasisLevel:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x88_STRUCT;
+
+// **** DxF0x8C Register Definition ****
+// Address
+#define DxF0x8C_ADDRESS                                         0x8c
+
+// Type
+#define DxF0x8C_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x8C_Reserved_31_0_OFFSET                            0
+#define DxF0x8C_Reserved_31_0_WIDTH                             32
+#define DxF0x8C_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x8C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x8C_STRUCT;
+
+// **** DxF0x90 Register Definition ****
+// Address
+#define DxF0x90_ADDRESS                                         0x90
+
+// Type
+#define DxF0x90_TYPE                                            TYPE_D4F0
+// Field Data
+#define DxF0x90_Reserved_31_0_OFFSET                            0
+#define DxF0x90_Reserved_31_0_WIDTH                             32
+#define DxF0x90_Reserved_31_0_MASK                              0xffffffff
+
+/// DxF0x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_31_0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x90_STRUCT;
+
+// **** DxF0x128 Register Definition ****
+// Address
+#define DxF0x128_ADDRESS                                        0x128
+
+// Type
+#define DxF0x128_TYPE                                           TYPE_D4F0
+// Field Data
+#define DxF0x128_Reserved_15_0_OFFSET                           0
+#define DxF0x128_Reserved_15_0_WIDTH                            16
+#define DxF0x128_Reserved_15_0_MASK                             0xffff
+#define DxF0x128_PortArbTableStatus_OFFSET                      16
+#define DxF0x128_PortArbTableStatus_WIDTH                       1
+#define DxF0x128_PortArbTableStatus_MASK                        0x10000
+#define DxF0x128_VcNegotiationPending_OFFSET                    17
+#define DxF0x128_VcNegotiationPending_WIDTH                     1
+#define DxF0x128_VcNegotiationPending_MASK                      0x20000
+#define DxF0x128_Reserved_31_18_OFFSET                          18
+#define DxF0x128_Reserved_31_18_WIDTH                           14
+#define DxF0x128_Reserved_31_18_MASK                            0xfffc0000
+
+/// DxF0x128
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                       PortArbTableStatus:1 ; ///<
+    UINT32                                     VcNegotiationPending:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0x128_STRUCT;
+
+// **** D0F0x64_x00 Register Definition ****
+// Address
+#define D0F0x64_x00_ADDRESS                                     0x0
+
+// Type
+#define D0F0x64_x00_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x00_Reserved_5_0_OFFSET                         0
+#define D0F0x64_x00_Reserved_5_0_WIDTH                          6
+#define D0F0x64_x00_Reserved_5_0_MASK                           0x3f
+#define D0F0x64_x00_NbFchCfgEn_OFFSET                           6
+#define D0F0x64_x00_NbFchCfgEn_WIDTH                            1
+#define D0F0x64_x00_NbFchCfgEn_MASK                             0x40
+#define D0F0x64_x00_HwInitWrLock_OFFSET                         7
+#define D0F0x64_x00_HwInitWrLock_WIDTH                          1
+#define D0F0x64_x00_HwInitWrLock_MASK                           0x80
+#define D0F0x64_x00_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x00_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x00_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_5_0:6 ; ///<
+    UINT32                                               NbFchCfgEn:1 ; ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x00_STRUCT;
+
+// **** D0F0x64_x0B Register Definition ****
+// Address
+#define D0F0x64_x0B_ADDRESS                                     0xb
+
+// Type
+#define D0F0x64_x0B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x0B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x0B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x0B_SetPowEn_OFFSET                             20
+#define D0F0x64_x0B_SetPowEn_WIDTH                              1
+#define D0F0x64_x0B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x0B_IocFchSetPowEn_OFFSET                       21
+#define D0F0x64_x0B_IocFchSetPowEn_WIDTH                        1
+#define D0F0x64_x0B_IocFchSetPowEn_MASK                         0x200000
+#define D0F0x64_x0B_Reserved_22_22_OFFSET                       22
+#define D0F0x64_x0B_Reserved_22_22_WIDTH                        1
+#define D0F0x64_x0B_Reserved_22_22_MASK                         0x400000
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET                23
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH                 1
+#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK                  0x800000
+#define D0F0x64_x0B_Reserved_31_24_OFFSET                       24
+#define D0F0x64_x0B_Reserved_31_24_WIDTH                        8
+#define D0F0x64_x0B_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x64_x0B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           IocFchSetPowEn:1 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    IocFchSetPmeTurnOffEn:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0B_STRUCT;
+
+// **** D0F0x64_x0C Register Definition ****
+// Address
+#define D0F0x64_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x64_x0C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0C_Reserved_1_0_OFFSET                         0
+#define D0F0x64_x0C_Reserved_1_0_WIDTH                          2
+#define D0F0x64_x0C_Reserved_1_0_MASK                           0x3
+#define D0F0x64_x0C_Dev2BridgeDis_OFFSET                        2
+#define D0F0x64_x0C_Dev2BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev2BridgeDis_MASK                          0x4
+#define D0F0x64_x0C_Dev3BridgeDis_OFFSET                        3
+#define D0F0x64_x0C_Dev3BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev3BridgeDis_MASK                          0x8
+#define D0F0x64_x0C_Dev4BridgeDis_OFFSET                        4
+#define D0F0x64_x0C_Dev4BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev4BridgeDis_MASK                          0x10
+#define D0F0x64_x0C_Dev5BridgeDis_OFFSET                        5
+#define D0F0x64_x0C_Dev5BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev5BridgeDis_MASK                          0x20
+#define D0F0x64_x0C_Dev6BridgeDis_OFFSET                        6
+#define D0F0x64_x0C_Dev6BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev6BridgeDis_MASK                          0x40
+#define D0F0x64_x0C_Dev7BridgeDis_OFFSET                        7
+#define D0F0x64_x0C_Dev7BridgeDis_WIDTH                         1
+#define D0F0x64_x0C_Dev7BridgeDis_MASK                          0x80
+#define D0F0x64_x0C_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x0C_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x0C_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                            Dev2BridgeDis:1 ; ///<
+    UINT32                                            Dev3BridgeDis:1 ; ///<
+    UINT32                                            Dev4BridgeDis:1 ; ///<
+    UINT32                                            Dev5BridgeDis:1 ; ///<
+    UINT32                                            Dev6BridgeDis:1 ; ///<
+    UINT32                                            Dev7BridgeDis:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0C_STRUCT;
+
+// **** D0F0x64_x0D Register Definition ****
+// Address
+#define D0F0x64_x0D_ADDRESS                                     0xd
+
+// Type
+#define D0F0x64_x0D_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET                      0
+#define D0F0x64_x0D_PciDev0Fn2RegEn_WIDTH                       1
+#define D0F0x64_x0D_PciDev0Fn2RegEn_MASK                        0x1
+#define D0F0x64_x0D_Reserved_31_1_OFFSET                        1
+#define D0F0x64_x0D_Reserved_31_1_WIDTH                         31
+#define D0F0x64_x0D_Reserved_31_1_MASK                          0xfffffffe
+
+/// D0F0x64_x0D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          PciDev0Fn2RegEn:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x0D_STRUCT;
+
+// **** D0F0x64_x16 Register Definition ****
+// Address
+#define D0F0x64_x16_ADDRESS                                     0x16
+
+// Type
+#define D0F0x64_x16_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x16_AerUrMsgEn_OFFSET                           0
+#define D0F0x64_x16_AerUrMsgEn_WIDTH                            1
+#define D0F0x64_x16_AerUrMsgEn_MASK                             0x1
+#define D0F0x64_x16_Reserved_31_1_OFFSET                        1
+#define D0F0x64_x16_Reserved_31_1_WIDTH                         31
+#define D0F0x64_x16_Reserved_31_1_MASK                          0xfffffffe
+
+/// D0F0x64_x16
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               AerUrMsgEn:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x16_STRUCT;
+
+// **** D0F0x64_x19 Register Definition ****
+// Address
+#define D0F0x64_x19_ADDRESS                                     0x19
+
+// Type
+#define D0F0x64_x19_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x19_TomEn_OFFSET                                0
+#define D0F0x64_x19_TomEn_WIDTH                                 1
+#define D0F0x64_x19_TomEn_MASK                                  0x1
+#define D0F0x64_x19_Reserved_22_1_OFFSET                        1
+#define D0F0x64_x19_Reserved_22_1_WIDTH                         22
+#define D0F0x64_x19_Reserved_22_1_MASK                          0x7ffffe
+#define D0F0x64_x19_Tom2_31_23__OFFSET                          23
+#define D0F0x64_x19_Tom2_31_23__WIDTH                           9
+#define D0F0x64_x19_Tom2_31_23__MASK                            0xff800000
+
+/// D0F0x64_x19
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    TomEn:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                              Tom2_31_23_:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x19_STRUCT;
+
+// **** D0F0x64_x1A Register Definition ****
+// Address
+#define D0F0x64_x1A_ADDRESS                                     0x1a
+
+// Type
+#define D0F0x64_x1A_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1A_Tom2_39_32__OFFSET                          0
+#define D0F0x64_x1A_Tom2_39_32__WIDTH                           8
+#define D0F0x64_x1A_Tom2_39_32__MASK                            0xff
+#define D0F0x64_x1A_Reserved_31_8_OFFSET                        8
+#define D0F0x64_x1A_Reserved_31_8_WIDTH                         24
+#define D0F0x64_x1A_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x64_x1A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Tom2_39_32_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1A_STRUCT;
+
+// **** D0F0x64_x1C Register Definition ****
+// Address
+#define D0F0x64_x1C_ADDRESS                                     0x1c
+
+// Type
+#define D0F0x64_x1C_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1C_WriteDis_OFFSET                             0
+#define D0F0x64_x1C_WriteDis_WIDTH                              1
+#define D0F0x64_x1C_WriteDis_MASK                               0x1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET              1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH               1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK                0x2
+#define D0F0x64_x1C_F064BarEn_OFFSET                            2
+#define D0F0x64_x1C_F064BarEn_WIDTH                             1
+#define D0F0x64_x1C_F064BarEn_MASK                              0x4
+#define D0F0x64_x1C_MemApSize_OFFSET                            3
+#define D0F0x64_x1C_MemApSize_WIDTH                             3
+#define D0F0x64_x1C_MemApSize_MASK                              0x38
+#define D0F0x64_x1C_RegApSize_OFFSET                            6
+#define D0F0x64_x1C_RegApSize_WIDTH                             1
+#define D0F0x64_x1C_RegApSize_MASK                              0x40
+#define D0F0x64_x1C_Reserved_7_7_OFFSET                         7
+#define D0F0x64_x1C_Reserved_7_7_WIDTH                          1
+#define D0F0x64_x1C_Reserved_7_7_MASK                           0x80
+#define D0F0x64_x1C_AudioEn_OFFSET                              8
+#define D0F0x64_x1C_AudioEn_WIDTH                               1
+#define D0F0x64_x1C_AudioEn_MASK                                0x100
+#define D0F0x64_x1C_MsiDis_OFFSET                               9
+#define D0F0x64_x1C_MsiDis_WIDTH                                1
+#define D0F0x64_x1C_MsiDis_MASK                                 0x200
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET           10
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH            1
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK             0x400
+#define D0F0x64_x1C_Audio64BarEn_OFFSET                         11
+#define D0F0x64_x1C_Audio64BarEn_WIDTH                          1
+#define D0F0x64_x1C_Audio64BarEn_MASK                           0x800
+#define D0F0x64_x1C_Reserved_15_12_OFFSET                       12
+#define D0F0x64_x1C_Reserved_15_12_WIDTH                        4
+#define D0F0x64_x1C_Reserved_15_12_MASK                         0xf000
+#define D0F0x64_x1C_IoBarDis_OFFSET                             16
+#define D0F0x64_x1C_IoBarDis_WIDTH                              1
+#define D0F0x64_x1C_IoBarDis_MASK                               0x10000
+#define D0F0x64_x1C_F0En_OFFSET                                 17
+#define D0F0x64_x1C_F0En_WIDTH                                  1
+#define D0F0x64_x1C_F0En_MASK                                   0x20000
+#define D0F0x64_x1C_Reserved_22_18_OFFSET                       18
+#define D0F0x64_x1C_Reserved_22_18_WIDTH                        5
+#define D0F0x64_x1C_Reserved_22_18_MASK                         0x7c0000
+#define D0F0x64_x1C_RcieEn_OFFSET                               23
+#define D0F0x64_x1C_RcieEn_WIDTH                                1
+#define D0F0x64_x1C_RcieEn_MASK                                 0x800000
+#define D0F0x64_x1C_Reserved_31_24_OFFSET                       24
+#define D0F0x64_x1C_Reserved_31_24_WIDTH                        8
+#define D0F0x64_x1C_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x64_x1C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 WriteDis:1 ; ///<
+    UINT32                                  F0NonlegacyDeviceTypeEn:1 ; ///<
+    UINT32                                                F064BarEn:1 ; ///<
+    UINT32                                                MemApSize:3 ; ///<
+    UINT32                                                RegApSize:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                                  AudioEn:1 ; ///<
+    UINT32                                                   MsiDis:1 ; ///<
+    UINT32                               AudioNonlegacyDeviceTypeEn:1 ; ///<
+    UINT32                                             Audio64BarEn:1 ; ///<
+    UINT32                                           Reserved_15_12:4 ; ///<
+    UINT32                                                 IoBarDis:1 ; ///<
+    UINT32                                                     F0En:1 ; ///<
+    UINT32                                           Reserved_22_18:5 ; ///<
+    UINT32                                                   RcieEn:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1C_STRUCT;
+
+// **** D0F0x64_x1D Register Definition ****
+// Address
+#define D0F0x64_x1D_ADDRESS                                     0x1d
+
+// Type
+#define D0F0x64_x1D_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET                       0
+#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH                        1
+#define D0F0x64_x1D_IntGfxAsPcieEn_MASK                         0x1
+#define D0F0x64_x1D_VgaEn_OFFSET                                1
+#define D0F0x64_x1D_VgaEn_WIDTH                                 1
+#define D0F0x64_x1D_VgaEn_MASK                                  0x2
+#define D0F0x64_x1D_Reserved_2_2_OFFSET                         2
+#define D0F0x64_x1D_Reserved_2_2_WIDTH                          1
+#define D0F0x64_x1D_Reserved_2_2_MASK                           0x4
+#define D0F0x64_x1D_Vga16En_OFFSET                              3
+#define D0F0x64_x1D_Vga16En_WIDTH                               1
+#define D0F0x64_x1D_Vga16En_MASK                                0x8
+#define D0F0x64_x1D_Reserved_31_4_OFFSET                        4
+#define D0F0x64_x1D_Reserved_31_4_WIDTH                         28
+#define D0F0x64_x1D_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F0x64_x1D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           IntGfxAsPcieEn:1 ; ///<
+    UINT32                                                    VgaEn:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                                  Vga16En:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x1D_STRUCT;
+
+// **** D0F0x64_x20 Register Definition ****
+// Address
+#define D0F0x64_x20_ADDRESS                                     0x20
+
+// Type
+#define D0F0x64_x20_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x20_ProgDevMapEn_OFFSET                         0
+#define D0F0x64_x20_ProgDevMapEn_WIDTH                          1
+#define D0F0x64_x20_ProgDevMapEn_MASK                           0x1
+#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET                   1
+#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH                    1
+#define D0F0x64_x20_IocPcieDevRemapDis_MASK                     0x2
+#define D0F0x64_x20_Reserved_3_2_OFFSET                         2
+#define D0F0x64_x20_Reserved_3_2_WIDTH                          2
+#define D0F0x64_x20_Reserved_3_2_MASK                           0xc
+#define D0F0x64_x20_GppPortBDevmap_OFFSET                       4
+#define D0F0x64_x20_GppPortBDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortBDevmap_MASK                         0xf0
+#define D0F0x64_x20_GppPortCDevmap_OFFSET                       8
+#define D0F0x64_x20_GppPortCDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortCDevmap_MASK                         0xf00
+#define D0F0x64_x20_GppPortDDevmap_OFFSET                       12
+#define D0F0x64_x20_GppPortDDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortDDevmap_MASK                         0xf000
+#define D0F0x64_x20_GppPortEDevmap_OFFSET                       16
+#define D0F0x64_x20_GppPortEDevmap_WIDTH                        4
+#define D0F0x64_x20_GppPortEDevmap_MASK                         0xf0000
+#define D0F0x64_x20_Reserved_31_20_OFFSET                       20
+#define D0F0x64_x20_Reserved_31_20_WIDTH                        12
+#define D0F0x64_x20_Reserved_31_20_MASK                         0xfff00000
+
+/// D0F0x64_x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             ProgDevMapEn:1 ; ///<
+    UINT32                                       IocPcieDevRemapDis:1 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                           GppPortBDevmap:4 ; ///<
+    UINT32                                           GppPortCDevmap:4 ; ///<
+    UINT32                                           GppPortDDevmap:4 ; ///<
+    UINT32                                           GppPortEDevmap:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x20_STRUCT;
+
+// **** D0F0x64_x21 Register Definition ****
+// Address
+#define D0F0x64_x21_ADDRESS                                     0x21
+
+// Type
+#define D0F0x64_x21_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x21_Reserved_11_0_OFFSET                        0
+#define D0F0x64_x21_Reserved_11_0_WIDTH                         12
+#define D0F0x64_x21_Reserved_11_0_MASK                          0xfff
+#define D0F0x64_x21_GfxPortADevmap_OFFSET                       12
+#define D0F0x64_x21_GfxPortADevmap_WIDTH                        4
+#define D0F0x64_x21_GfxPortADevmap_MASK                         0xf000
+#define D0F0x64_x21_GfxPortBDevmap_OFFSET                       16
+#define D0F0x64_x21_GfxPortBDevmap_WIDTH                        4
+#define D0F0x64_x21_GfxPortBDevmap_MASK                         0xf0000
+#define D0F0x64_x21_Reserved_31_20_OFFSET                       20
+#define D0F0x64_x21_Reserved_31_20_WIDTH                        12
+#define D0F0x64_x21_Reserved_31_20_MASK                         0xfff00000
+
+/// D0F0x64_x21
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                           GfxPortADevmap:4 ; ///<
+    UINT32                                           GfxPortBDevmap:4 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x21_STRUCT;
+
+// **** D0F0x64_x22 Register Definition ****
+// Address
+#define D0F0x64_x22_ADDRESS                                     0x22
+
+// Type
+#define D0F0x64_x22_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x22_Reserved_25_0_OFFSET                        0
+#define D0F0x64_x22_Reserved_25_0_WIDTH                         26
+#define D0F0x64_x22_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x64_x22_SoftOverrideClk4_OFFSET                     26
+#define D0F0x64_x22_SoftOverrideClk4_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x64_x22_SoftOverrideClk3_OFFSET                     27
+#define D0F0x64_x22_SoftOverrideClk3_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x64_x22_SoftOverrideClk2_OFFSET                     28
+#define D0F0x64_x22_SoftOverrideClk2_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x64_x22_SoftOverrideClk1_OFFSET                     29
+#define D0F0x64_x22_SoftOverrideClk1_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x64_x22_SoftOverrideClk0_OFFSET                     30
+#define D0F0x64_x22_SoftOverrideClk0_WIDTH                      1
+#define D0F0x64_x22_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x64_x22_Reserved_31_31_OFFSET                       31
+#define D0F0x64_x22_Reserved_31_31_WIDTH                        1
+#define D0F0x64_x22_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x64_x22
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x22_STRUCT;
+
+// **** D0F0x64_x23 Register Definition ****
+// Address
+#define D0F0x64_x23_ADDRESS                                     0x23
+
+// Type
+#define D0F0x64_x23_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x23_Reserved_25_0_OFFSET                        0
+#define D0F0x64_x23_Reserved_25_0_WIDTH                         26
+#define D0F0x64_x23_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x64_x23_SoftOverrideClk4_OFFSET                     26
+#define D0F0x64_x23_SoftOverrideClk4_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x64_x23_SoftOverrideClk3_OFFSET                     27
+#define D0F0x64_x23_SoftOverrideClk3_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x64_x23_SoftOverrideClk2_OFFSET                     28
+#define D0F0x64_x23_SoftOverrideClk2_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x64_x23_SoftOverrideClk1_OFFSET                     29
+#define D0F0x64_x23_SoftOverrideClk1_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x64_x23_SoftOverrideClk0_OFFSET                     30
+#define D0F0x64_x23_SoftOverrideClk0_WIDTH                      1
+#define D0F0x64_x23_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x64_x23_Reserved_31_31_OFFSET                       31
+#define D0F0x64_x23_Reserved_31_31_WIDTH                        1
+#define D0F0x64_x23_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x64_x23
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x23_STRUCT;
+
+
+// **** D0F0x64_x46 Register Definition ****
+// Address
+#define D0F0x64_x46_ADDRESS                                     0x46
+
+// Type
+#define D0F0x64_x46_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x46_Reserved_0_0_OFFSET                         0
+#define D0F0x64_x46_Reserved_0_0_WIDTH                          1
+#define D0F0x64_x46_Reserved_0_0_MASK                           0x1
+#define D0F0x64_x46_Reserved_15_3_OFFSET                        3
+#define D0F0x64_x46_Reserved_15_3_WIDTH                         13
+#define D0F0x64_x46_Reserved_15_3_MASK                          0xfff8
+#define D0F0x64_x46_Msi64bitEn_OFFSET                           16
+#define D0F0x64_x46_Msi64bitEn_WIDTH                            1
+#define D0F0x64_x46_Msi64bitEn_MASK                             0x10000
+#define D0F0x64_x46_Reserved_31_17_OFFSET                       17
+#define D0F0x64_x46_Reserved_31_17_WIDTH                        15
+#define D0F0x64_x46_Reserved_31_17_MASK                         0xfffe0000
+
+/// D0F0x64_x46
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  :2 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                               Msi64bitEn:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x46_STRUCT;
+
+
+// **** D0F0x64_x53 Register Definition ****
+// Address
+#define D0F0x64_x53_ADDRESS                                     0x53
+
+// Type
+#define D0F0x64_x53_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x53_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x53_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x53_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x53_SetPowEn_OFFSET                             20
+#define D0F0x64_x53_SetPowEn_WIDTH                              1
+#define D0F0x64_x53_SetPowEn_MASK                               0x100000
+#define D0F0x64_x53_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x53_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x53_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x53
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x53_STRUCT;
+
+// **** D0F0x64_x55 Register Definition ****
+// Address
+#define D0F0x64_x55_ADDRESS                                     0x55
+
+// Type
+#define D0F0x64_x55_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x55_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x55_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x55_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x55_SetPowEn_OFFSET                             20
+#define D0F0x64_x55_SetPowEn_WIDTH                              1
+#define D0F0x64_x55_SetPowEn_MASK                               0x100000
+#define D0F0x64_x55_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x55_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x55_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x55
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x55_STRUCT;
+
+// **** D0F0x64_x57 Register Definition ****
+// Address
+#define D0F0x64_x57_ADDRESS                                     0x57
+
+// Type
+#define D0F0x64_x57_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x57_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x57_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x57_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x57_SetPowEn_OFFSET                             20
+#define D0F0x64_x57_SetPowEn_WIDTH                              1
+#define D0F0x64_x57_SetPowEn_MASK                               0x100000
+#define D0F0x64_x57_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x57_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x57_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x57
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x57_STRUCT;
+
+// **** D0F0x64_x59 Register Definition ****
+// Address
+#define D0F0x64_x59_ADDRESS                                     0x59
+
+// Type
+#define D0F0x64_x59_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x59_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x59_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x59_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x59_SetPowEn_OFFSET                             20
+#define D0F0x64_x59_SetPowEn_WIDTH                              1
+#define D0F0x64_x59_SetPowEn_MASK                               0x100000
+#define D0F0x64_x59_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x59_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x59_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x59
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x59_STRUCT;
+
+// **** D0F0x64_x5B Register Definition ****
+// Address
+#define D0F0x64_x5B_ADDRESS                                     0x5b
+
+// Type
+#define D0F0x64_x5B_TYPE                                        TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x5B_Reserved_19_0_OFFSET                        0
+#define D0F0x64_x5B_Reserved_19_0_WIDTH                         20
+#define D0F0x64_x5B_Reserved_19_0_MASK                          0xfffff
+#define D0F0x64_x5B_SetPowEn_OFFSET                             20
+#define D0F0x64_x5B_SetPowEn_WIDTH                              1
+#define D0F0x64_x5B_SetPowEn_MASK                               0x100000
+#define D0F0x64_x5B_Reserved_31_21_OFFSET                       21
+#define D0F0x64_x5B_Reserved_31_21_WIDTH                        11
+#define D0F0x64_x5B_Reserved_31_21_MASK                         0xffe00000
+
+/// D0F0x64_x5B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_19_0:20; ///<
+    UINT32                                                 SetPowEn:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x64_x5B_STRUCT;
+
+// **** D0F0x98_x06 Register Definition ****
+// Address
+#define D0F0x98_x06_ADDRESS                                     0x6
+
+// Type
+#define D0F0x98_x06_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x06_Reserved_25_0_OFFSET                        0
+#define D0F0x98_x06_Reserved_25_0_WIDTH                         26
+#define D0F0x98_x06_Reserved_25_0_MASK                          0x3ffffff
+#define D0F0x98_x06_UmiNpMemWrEn_OFFSET                         26
+#define D0F0x98_x06_UmiNpMemWrEn_WIDTH                          1
+#define D0F0x98_x06_UmiNpMemWrEn_MASK                           0x4000000
+#define D0F0x98_x06_Reserved_31_27_OFFSET                       27
+#define D0F0x98_x06_Reserved_31_27_WIDTH                        5
+#define D0F0x98_x06_Reserved_31_27_MASK                         0xf8000000
+
+/// D0F0x98_x06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_25_0:26; ///<
+    UINT32                                             UmiNpMemWrEn:1 ; ///<
+    UINT32                                           Reserved_31_27:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x06_STRUCT;
+
+// **** D0F0x98_x07 Register Definition ****
+// Address
+#define D0F0x98_x07_ADDRESS                                     0x7
+
+// Type
+#define D0F0x98_x07_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x07_IocBwOptEn_OFFSET                           0
+#define D0F0x98_x07_IocBwOptEn_WIDTH                            1
+#define D0F0x98_x07_IocBwOptEn_MASK                             0x1
+#define D0F0x98_x07_Reserved_3_1_OFFSET                         1
+#define D0F0x98_x07_Reserved_3_1_WIDTH                          3
+#define D0F0x98_x07_Reserved_3_1_MASK                           0xe
+#define D0F0x98_x07_IommuBwOptEn_OFFSET                         4
+#define D0F0x98_x07_IommuBwOptEn_WIDTH                          1
+#define D0F0x98_x07_IommuBwOptEn_MASK                           0x10
+#define D0F0x98_x07_Reserved_5_5_OFFSET                         5
+#define D0F0x98_x07_Reserved_5_5_WIDTH                          1
+#define D0F0x98_x07_Reserved_5_5_MASK                           0x20
+#define D0F0x98_x07_DmaReqRespPassPWMode_OFFSET                 6
+#define D0F0x98_x07_DmaReqRespPassPWMode_WIDTH                  1
+#define D0F0x98_x07_DmaReqRespPassPWMode_MASK                   0x40
+#define D0F0x98_x07_IommuIsocPassPWMode_OFFSET                  7
+#define D0F0x98_x07_IommuIsocPassPWMode_WIDTH                   1
+#define D0F0x98_x07_IommuIsocPassPWMode_MASK                    0x80
+#define D0F0x98_x07_Reserved_13_8_OFFSET                        8
+#define D0F0x98_x07_Reserved_13_8_WIDTH                         6
+#define D0F0x98_x07_Reserved_13_8_MASK                          0x3f00
+#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET                 14
+#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH                  1
+#define D0F0x98_x07_MSIHTIntConversionEn_MASK                   0x4000
+#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET                     15
+#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH                      1
+#define D0F0x98_x07_DropZeroMaskWrEn_MASK                       0x8000
+#define D0F0x98_x07_Reserved_29_16_OFFSET                       16
+#define D0F0x98_x07_Reserved_29_16_WIDTH                        14
+#define D0F0x98_x07_Reserved_29_16_MASK                         0x3fff0000
+#define D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET             30
+#define D0F0x98_x07_UnadjustThrottlingStpclk_WIDTH              1
+#define D0F0x98_x07_UnadjustThrottlingStpclk_MASK               0x40000000
+#define D0F0x98_x07_SMUCsrIsocEn_OFFSET                         31
+#define D0F0x98_x07_SMUCsrIsocEn_WIDTH                          1
+#define D0F0x98_x07_SMUCsrIsocEn_MASK                           0x80000000
+
+/// D0F0x98_x07
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               IocBwOptEn:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                             IommuBwOptEn:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                     DmaReqRespPassPWMode:1 ; ///<
+    UINT32                                      IommuIsocPassPWMode:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                     MSIHTIntConversionEn:1 ; ///<
+    UINT32                                         DropZeroMaskWrEn:1 ; ///<
+    UINT32                                           Reserved_29_16:14; ///<
+    UINT32                                 UnadjustThrottlingStpclk:1 ; ///<
+    UINT32                                             SMUCsrIsocEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x07_STRUCT;
+
+// **** D0F0x98_x08 Register Definition ****
+// Address
+#define D0F0x98_x08_ADDRESS                                     0x8
+
+// Type
+#define D0F0x98_x08_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x08_NpWrrLenA_OFFSET                            0
+#define D0F0x98_x08_NpWrrLenA_WIDTH                             8
+#define D0F0x98_x08_NpWrrLenA_MASK                              0xff
+#define D0F0x98_x08_NpWrrLenB_OFFSET                            8
+#define D0F0x98_x08_NpWrrLenB_WIDTH                             8
+#define D0F0x98_x08_NpWrrLenB_MASK                              0xff00
+#define D0F0x98_x08_NpWrrLenC_OFFSET                            16
+#define D0F0x98_x08_NpWrrLenC_WIDTH                             8
+#define D0F0x98_x08_NpWrrLenC_MASK                              0xff0000
+#define D0F0x98_x08_Reserved_31_24_OFFSET                       24
+#define D0F0x98_x08_Reserved_31_24_WIDTH                        8
+#define D0F0x98_x08_Reserved_31_24_MASK                         0xff000000
+
+/// D0F0x98_x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                NpWrrLenA:8 ; ///<
+    UINT32                                                NpWrrLenB:8 ; ///<
+    UINT32                                                NpWrrLenC:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x08_STRUCT;
+
+// **** D0F0x98_x09 Register Definition ****
+// Address
+#define D0F0x98_x09_ADDRESS                                     0x9
+
+// Type
+#define D0F0x98_x09_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x09_PWrrLenA_OFFSET                             0
+#define D0F0x98_x09_PWrrLenA_WIDTH                              8
+#define D0F0x98_x09_PWrrLenA_MASK                               0xff
+#define D0F0x98_x09_PWrrLenB_OFFSET                             8
+#define D0F0x98_x09_PWrrLenB_WIDTH                              8
+#define D0F0x98_x09_PWrrLenB_MASK                               0xff00
+#define D0F0x98_x09_Reserved_31_16_OFFSET                       16
+#define D0F0x98_x09_Reserved_31_16_WIDTH                        16
+#define D0F0x98_x09_Reserved_31_16_MASK                         0xffff0000
+
+/// D0F0x98_x09
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 PWrrLenA:8 ; ///<
+    UINT32                                                 PWrrLenB:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x09_STRUCT;
+
+// **** D0F0x98_x0C Register Definition ****
+// Address
+#define D0F0x98_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F0x98_x0C_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x0C_GcmWrrLenA_OFFSET                           0
+#define D0F0x98_x0C_GcmWrrLenA_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenA_MASK                             0xff
+#define D0F0x98_x0C_GcmWrrLenB_OFFSET                           8
+#define D0F0x98_x0C_GcmWrrLenB_WIDTH                            8
+#define D0F0x98_x0C_GcmWrrLenB_MASK                             0xff00
+#define D0F0x98_x0C_Reserved_29_16_OFFSET                       16
+#define D0F0x98_x0C_Reserved_29_16_WIDTH                        14
+#define D0F0x98_x0C_Reserved_29_16_MASK                         0x3fff0000
+#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET                    30
+#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH                     1
+#define D0F0x98_x0C_StrictSelWinnerEn_MASK                      0x40000000
+#define D0F0x98_x0C_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x0C_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x0C_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               GcmWrrLenA:8 ; ///<
+    UINT32                                               GcmWrrLenB:8 ; ///<
+    UINT32                                           Reserved_29_16:14; ///<
+    UINT32                                        StrictSelWinnerEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x0C_STRUCT;
+
+// **** D0F0x98_x1E Register Definition ****
+// Address
+#define D0F0x98_x1E_ADDRESS                                     0x1e
+
+// Type
+#define D0F0x98_x1E_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x1E_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x1E_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x1E_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x1E_HiPriEn_OFFSET                              1
+#define D0F0x98_x1E_HiPriEn_WIDTH                               1
+#define D0F0x98_x1E_HiPriEn_MASK                                0x2
+#define D0F0x98_x1E_Reserved_31_2_OFFSET                        2
+#define D0F0x98_x1E_Reserved_31_2_WIDTH                         30
+#define D0F0x98_x1E_Reserved_31_2_MASK                          0xfffffffc
+
+/// D0F0x98_x1E
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                  HiPriEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x1E_STRUCT;
+
+// **** D0F0x98_x26 Register Definition ****
+// Address
+#define D0F0x98_x26_ADDRESS                                     0x26
+
+// Type
+#define D0F0x98_x26_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x26_IOMMUUrAddr_39_32__OFFSET                   0
+#define D0F0x98_x26_IOMMUUrAddr_39_32__WIDTH                    8
+#define D0F0x98_x26_IOMMUUrAddr_39_32__MASK                     0xff
+#define D0F0x98_x26_Reserved_31_8_OFFSET                        8
+#define D0F0x98_x26_Reserved_31_8_WIDTH                         24
+#define D0F0x98_x26_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F0x98_x26
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       IOMMUUrAddr_39_32_:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x26_STRUCT;
+
+// **** D0F0x98_x27 Register Definition ****
+// Address
+#define D0F0x98_x27_ADDRESS                                     0x27
+
+// Type
+#define D0F0x98_x27_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x27_Reserved_5_0_OFFSET                         0
+#define D0F0x98_x27_Reserved_5_0_WIDTH                          6
+#define D0F0x98_x27_Reserved_5_0_MASK                           0x3f
+#define D0F0x98_x27_IOMMUUrAddr_31_6__OFFSET                    6
+#define D0F0x98_x27_IOMMUUrAddr_31_6__WIDTH                     26
+#define D0F0x98_x27_IOMMUUrAddr_31_6__MASK                      0xffffffc0
+
+/// D0F0x98_x27
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_5_0:6 ; ///<
+    UINT32                                        IOMMUUrAddr_31_6_:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x27_STRUCT;
+
+// **** D0F0x98_x28 Register Definition ****
+// Address
+#define D0F0x98_x28_ADDRESS                                     0x28
+
+// Type
+#define D0F0x98_x28_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x28_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x28_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x28_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x28_ForceCoherentIntr_OFFSET                    1
+#define D0F0x98_x28_ForceCoherentIntr_WIDTH                     1
+#define D0F0x98_x28_ForceCoherentIntr_MASK                      0x2
+#define D0F0x98_x28_Reserved_31_2_OFFSET                        2
+#define D0F0x98_x28_Reserved_31_2_WIDTH                         30
+#define D0F0x98_x28_Reserved_31_2_MASK                          0xfffffffc
+
+/// D0F0x98_x28
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                        ForceCoherentIntr:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x28_STRUCT;
+
+
+// **** D0F0x98_x2C Register Definition ****
+// Address
+#define D0F0x98_x2C_ADDRESS                                     0x2c
+
+// Type
+#define D0F0x98_x2C_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x2C_Reserved_0_0_OFFSET                         0
+#define D0F0x98_x2C_Reserved_0_0_WIDTH                          1
+#define D0F0x98_x2C_Reserved_0_0_MASK                           0x1
+#define D0F0x98_x2C_DynWakeEn_OFFSET                            1
+#define D0F0x98_x2C_DynWakeEn_WIDTH                             1
+#define D0F0x98_x2C_DynWakeEn_MASK                              0x2
+#define D0F0x98_x2C_Reserved_7_2_OFFSET                         2
+#define D0F0x98_x2C_Reserved_7_2_WIDTH                          6
+#define D0F0x98_x2C_Reserved_7_2_MASK                           0xfc
+#define D0F0x98_x2C_OrbRxIdlesMask_OFFSET                       8
+#define D0F0x98_x2C_OrbRxIdlesMask_WIDTH                        1
+#define D0F0x98_x2C_OrbRxIdlesMask_MASK                         0x100
+#define D0F0x98_x2C_SBDmaActiveMask_OFFSET                      9
+#define D0F0x98_x2C_SBDmaActiveMask_WIDTH                       1
+#define D0F0x98_x2C_SBDmaActiveMask_MASK                        0x200
+#define D0F0x98_x2C_NBOutbWakeMask_OFFSET                       10
+#define D0F0x98_x2C_NBOutbWakeMask_WIDTH                        1
+#define D0F0x98_x2C_NBOutbWakeMask_MASK                         0x400
+#define D0F0x98_x2C_Reserved_15_11_OFFSET                       11
+#define D0F0x98_x2C_Reserved_15_11_WIDTH                        5
+#define D0F0x98_x2C_Reserved_15_11_MASK                         0xf800
+#define D0F0x98_x2C_WakeHysteresis_OFFSET                       16
+#define D0F0x98_x2C_WakeHysteresis_WIDTH                        16
+#define D0F0x98_x2C_WakeHysteresis_MASK                         0xffff0000
+
+/// D0F0x98_x2C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                DynWakeEn:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                           OrbRxIdlesMask:1 ; ///<
+    UINT32                                          SBDmaActiveMask:1 ; ///<
+    UINT32                                           NBOutbWakeMask:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           WakeHysteresis:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x2C_STRUCT;
+
+// **** D0F0x98_x3A Register Definition ****
+// Address
+#define D0F0x98_x3A_ADDRESS                                     0x3a
+
+// Type
+#define D0F0x98_x3A_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x3A_ClumpingEn_OFFSET                           0
+#define D0F0x98_x3A_ClumpingEn_WIDTH                            32
+#define D0F0x98_x3A_ClumpingEn_MASK                             0xffffffff
+
+/// D0F0x98_x3A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               ClumpingEn:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x3A_STRUCT;
+
+// **** D0F0x98_x49 Register Definition ****
+// Address
+#define D0F0x98_x49_ADDRESS                                     0x49
+
+// Type
+#define D0F0x98_x49_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x49_Reserved_23_0_OFFSET                        0
+#define D0F0x98_x49_Reserved_23_0_WIDTH                         24
+#define D0F0x98_x49_Reserved_23_0_MASK                          0xffffff
+#define D0F0x98_x49_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x49_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x49_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x49_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x49_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x49_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x49_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x49_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x49_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x49_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x49_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x49_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x49_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x49_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x49_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x49_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x49_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x49_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x49
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x49_STRUCT;
+
+// **** D0F0x98_x4A Register Definition ****
+// Address
+#define D0F0x98_x4A_ADDRESS                                     0x4a
+
+// Type
+#define D0F0x98_x4A_TYPE                                        TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x4A_Reserved_23_0_OFFSET                        0
+#define D0F0x98_x4A_Reserved_23_0_WIDTH                         24
+#define D0F0x98_x4A_Reserved_23_0_MASK                          0xffffff
+#define D0F0x98_x4A_SoftOverrideClk6_OFFSET                     24
+#define D0F0x98_x4A_SoftOverrideClk6_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk6_MASK                       0x1000000
+#define D0F0x98_x4A_SoftOverrideClk5_OFFSET                     25
+#define D0F0x98_x4A_SoftOverrideClk5_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk5_MASK                       0x2000000
+#define D0F0x98_x4A_SoftOverrideClk4_OFFSET                     26
+#define D0F0x98_x4A_SoftOverrideClk4_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk4_MASK                       0x4000000
+#define D0F0x98_x4A_SoftOverrideClk3_OFFSET                     27
+#define D0F0x98_x4A_SoftOverrideClk3_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk3_MASK                       0x8000000
+#define D0F0x98_x4A_SoftOverrideClk2_OFFSET                     28
+#define D0F0x98_x4A_SoftOverrideClk2_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk2_MASK                       0x10000000
+#define D0F0x98_x4A_SoftOverrideClk1_OFFSET                     29
+#define D0F0x98_x4A_SoftOverrideClk1_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk1_MASK                       0x20000000
+#define D0F0x98_x4A_SoftOverrideClk0_OFFSET                     30
+#define D0F0x98_x4A_SoftOverrideClk0_WIDTH                      1
+#define D0F0x98_x4A_SoftOverrideClk0_MASK                       0x40000000
+#define D0F0x98_x4A_Reserved_31_31_OFFSET                       31
+#define D0F0x98_x4A_Reserved_31_31_WIDTH                        1
+#define D0F0x98_x4A_Reserved_31_31_MASK                         0x80000000
+
+/// D0F0x98_x4A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                         SoftOverrideClk6:1 ; ///<
+    UINT32                                         SoftOverrideClk5:1 ; ///<
+    UINT32                                         SoftOverrideClk4:1 ; ///<
+    UINT32                                         SoftOverrideClk3:1 ; ///<
+    UINT32                                         SoftOverrideClk2:1 ; ///<
+    UINT32                                         SoftOverrideClk1:1 ; ///<
+    UINT32                                         SoftOverrideClk0:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0x98_x4A_STRUCT;
+
+// **** D0F0xBC_x1F200 Register Definition ****
+// Address
+#define D0F0xBC_x1F200_ADDRESS                                  0x1f200
+
+// Type
+#define D0F0xBC_x1F200_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F200_StateValid_OFFSET                        0
+#define D0F0xBC_x1F200_StateValid_WIDTH                         1
+#define D0F0xBC_x1F200_StateValid_MASK                          0x1
+#define D0F0xBC_x1F200_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F200_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F200_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F200_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F200_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F200_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F200_VID_OFFSET                               16
+#define D0F0xBC_x1F200_VID_WIDTH                                8
+#define D0F0xBC_x1F200_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F200_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F200_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F200_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F200
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F200_STRUCT;
+
+// **** D0F0xBC_x1F208 Register Definition ****
+// Address
+#define D0F0xBC_x1F208_ADDRESS                                  0x1f208
+
+// Type
+#define D0F0xBC_x1F208_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F208_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F208_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F208_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F208_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F208_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F208_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F208_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F208_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F208_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F208
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F208_STRUCT;
+
+// **** D0F0xBC_x1F210 Register Definition ****
+// Address
+#define D0F0xBC_x1F210_ADDRESS                                  0x1f210
+
+// Type
+#define D0F0xBC_x1F210_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F210_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F210_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F210_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F210_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F210_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F210_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F210
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F210_STRUCT;
+
+// **** D0F0xBC_x1F220 Register Definition ****
+// Address
+#define D0F0xBC_x1F220_ADDRESS                                  0x1f220
+
+// Type
+#define D0F0xBC_x1F220_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F220_StateValid_OFFSET                        0
+#define D0F0xBC_x1F220_StateValid_WIDTH                         1
+#define D0F0xBC_x1F220_StateValid_MASK                          0x1
+#define D0F0xBC_x1F220_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F220_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F220_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F220_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F220_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F220_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F220_VID_OFFSET                               16
+#define D0F0xBC_x1F220_VID_WIDTH                                8
+#define D0F0xBC_x1F220_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F220_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F220_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F220_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F220
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F220_STRUCT;
+
+// **** D0F0xBC_x1F228 Register Definition ****
+// Address
+#define D0F0xBC_x1F228_ADDRESS                                  0x1f228
+
+// Type
+#define D0F0xBC_x1F228_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F228_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F228_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F228_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F228_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F228_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F228_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F228_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F228_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F228_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F228
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F228_STRUCT;
+
+// **** D0F0xBC_x1F230 Register Definition ****
+// Address
+#define D0F0xBC_x1F230_ADDRESS                                  0x1f230
+
+// Type
+#define D0F0xBC_x1F230_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F230_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F230_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F230_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F230_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F230_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F230_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F230
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F230_STRUCT;
+
+// **** D0F0xBC_x1F240 Register Definition ****
+// Address
+#define D0F0xBC_x1F240_ADDRESS                                  0x1f240
+
+// Type
+#define D0F0xBC_x1F240_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F240_StateValid_OFFSET                        0
+#define D0F0xBC_x1F240_StateValid_WIDTH                         1
+#define D0F0xBC_x1F240_StateValid_MASK                          0x1
+#define D0F0xBC_x1F240_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F240_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F240_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F240_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F240_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F240_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F240_VID_OFFSET                               16
+#define D0F0xBC_x1F240_VID_WIDTH                                8
+#define D0F0xBC_x1F240_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F240_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F240_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F240_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F240
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F240_STRUCT;
+
+// **** D0F0xBC_x1F248 Register Definition ****
+// Address
+#define D0F0xBC_x1F248_ADDRESS                                  0x1f248
+
+// Type
+#define D0F0xBC_x1F248_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F248_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F248_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F248_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F248_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F248_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F248_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F248_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F248_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F248_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F248
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F248_STRUCT;
+
+// **** D0F0xBC_x1F250 Register Definition ****
+// Address
+#define D0F0xBC_x1F250_ADDRESS                                  0x1f250
+
+// Type
+#define D0F0xBC_x1F250_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F250_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F250_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F250_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F250_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F250_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F250_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F250
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F250_STRUCT;
+
+// **** D0F0xBC_x1F260 Register Definition ****
+// Address
+#define D0F0xBC_x1F260_ADDRESS                                  0x1f260
+
+// Type
+#define D0F0xBC_x1F260_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F260_StateValid_OFFSET                        0
+#define D0F0xBC_x1F260_StateValid_WIDTH                         1
+#define D0F0xBC_x1F260_StateValid_MASK                          0x1
+#define D0F0xBC_x1F260_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F260_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F260_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F260_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F260_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F260_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F260_VID_OFFSET                               16
+#define D0F0xBC_x1F260_VID_WIDTH                                8
+#define D0F0xBC_x1F260_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F260_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F260_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F260_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F260
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F260_STRUCT;
+
+// **** D0F0xBC_x1F268 Register Definition ****
+// Address
+#define D0F0xBC_x1F268_ADDRESS                                  0x1f268
+
+// Type
+#define D0F0xBC_x1F268_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F268_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F268_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F268_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F268_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F268_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F268_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F268_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F268_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F268_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F268
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F268_STRUCT;
+
+// **** D0F0xBC_x1F270 Register Definition ****
+// Address
+#define D0F0xBC_x1F270_ADDRESS                                  0x1f270
+
+// Type
+#define D0F0xBC_x1F270_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F270_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F270_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F270_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F270_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F270_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F270_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F270
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F270_STRUCT;
+
+// **** D0F0xBC_x1F280 Register Definition ****
+// Address
+#define D0F0xBC_x1F280_ADDRESS                                  0x1f280
+
+// Type
+#define D0F0xBC_x1F280_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F280_StateValid_OFFSET                        0
+#define D0F0xBC_x1F280_StateValid_WIDTH                         1
+#define D0F0xBC_x1F280_StateValid_MASK                          0x1
+#define D0F0xBC_x1F280_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F280_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F280_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F280_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F280_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F280_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F280_VID_OFFSET                               16
+#define D0F0xBC_x1F280_VID_WIDTH                                8
+#define D0F0xBC_x1F280_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F280_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F280_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F280_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F280
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F280_STRUCT;
+
+// **** D0F0xBC_x1F288 Register Definition ****
+// Address
+#define D0F0xBC_x1F288_ADDRESS                                  0x1f288
+
+// Type
+#define D0F0xBC_x1F288_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F288_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F288_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F288_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F288_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F288_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F288_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F288_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F288_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F288_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F288
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F288_STRUCT;
+
+// **** D0F0xBC_x1F290 Register Definition ****
+// Address
+#define D0F0xBC_x1F290_ADDRESS                                  0x1f290
+
+// Type
+#define D0F0xBC_x1F290_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F290_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F290_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F290_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F290_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F290_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F290_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F290
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F290_STRUCT;
+
+// **** D0F0xBC_x1F2A0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2A0_ADDRESS                                  0x1f2a0
+
+// Type
+#define D0F0xBC_x1F2A0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2A0_StateValid_OFFSET                        0
+#define D0F0xBC_x1F2A0_StateValid_WIDTH                         1
+#define D0F0xBC_x1F2A0_StateValid_MASK                          0x1
+#define D0F0xBC_x1F2A0_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F2A0_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F2A0_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F2A0_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F2A0_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F2A0_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F2A0_VID_OFFSET                               16
+#define D0F0xBC_x1F2A0_VID_WIDTH                                8
+#define D0F0xBC_x1F2A0_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F2A0_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F2A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2A0_STRUCT;
+
+// **** D0F0xBC_x1F2A8 Register Definition ****
+// Address
+#define D0F0xBC_x1F2A8_ADDRESS                                  0x1f2a8
+
+// Type
+#define D0F0xBC_x1F2A8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2A8_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F2A8_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F2A8_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F2A8_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F2A8_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F2A8_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F2A8_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F2A8_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F2A8_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F2A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2A8_STRUCT;
+
+// **** D0F0xBC_x1F2B0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2B0_ADDRESS                                  0x1f2b0
+
+// Type
+#define D0F0xBC_x1F2B0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2B0_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F2B0_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F2B0_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F2B0_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F2B0_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F2B0_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F2B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2B0_STRUCT;
+
+// **** D0F0xBC_x1F2C0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2C0_ADDRESS                                  0x1f2c0
+
+// Type
+#define D0F0xBC_x1F2C0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2C0_StateValid_OFFSET                        0
+#define D0F0xBC_x1F2C0_StateValid_WIDTH                         1
+#define D0F0xBC_x1F2C0_StateValid_MASK                          0x1
+#define D0F0xBC_x1F2C0_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F2C0_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F2C0_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F2C0_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F2C0_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F2C0_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F2C0_VID_OFFSET                               16
+#define D0F0xBC_x1F2C0_VID_WIDTH                                8
+#define D0F0xBC_x1F2C0_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F2C0_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F2C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2C0_STRUCT;
+
+// **** D0F0xBC_x1F2C8 Register Definition ****
+// Address
+#define D0F0xBC_x1F2C8_ADDRESS                                  0x1f2c8
+
+// Type
+#define D0F0xBC_x1F2C8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2C8_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F2C8_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F2C8_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F2C8_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F2C8_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F2C8_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F2C8_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F2C8_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F2C8_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F2C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2C8_STRUCT;
+
+// **** D0F0xBC_x1F2D0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2D0_ADDRESS                                  0x1f2d0
+
+// Type
+#define D0F0xBC_x1F2D0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2D0_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F2D0_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F2D0_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F2D0_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F2D0_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F2D0_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F2D0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2D0_STRUCT;
+
+// **** D0F0xBC_x1F2E0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2E0_ADDRESS                                  0x1f2e0
+
+// Type
+#define D0F0xBC_x1F2E0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2E0_StateValid_OFFSET                        0
+#define D0F0xBC_x1F2E0_StateValid_WIDTH                         1
+#define D0F0xBC_x1F2E0_StateValid_MASK                          0x1
+#define D0F0xBC_x1F2E0_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F2E0_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F2E0_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F2E0_LclkDivider_OFFSET                       8
+#define D0F0xBC_x1F2E0_LclkDivider_WIDTH                        8
+#define D0F0xBC_x1F2E0_LclkDivider_MASK                         0xff00
+#define D0F0xBC_x1F2E0_VID_OFFSET                               16
+#define D0F0xBC_x1F2E0_VID_WIDTH                                8
+#define D0F0xBC_x1F2E0_VID_MASK                                 0xff0000
+#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_OFFSET            24
+#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_WIDTH             8
+#define D0F0xBC_x1F2E0_LowVoltageReqThreshold_MASK              0xff000000
+
+/// D0F0xBC_x1F2E0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               StateValid:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDivider:8 ; ///<
+    UINT32                                                      VID:8 ; ///<
+    UINT32                                   LowVoltageReqThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2E0_STRUCT;
+
+// **** D0F0xBC_x1F2E8 Register Definition ****
+// Address
+#define D0F0xBC_x1F2E8_ADDRESS                                  0x1f2e8
+
+// Type
+#define D0F0xBC_x1F2E8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2E8_HysteresisUp_OFFSET                      0
+#define D0F0xBC_x1F2E8_HysteresisUp_WIDTH                       8
+#define D0F0xBC_x1F2E8_HysteresisUp_MASK                        0xff
+#define D0F0xBC_x1F2E8_HysteresisDown_OFFSET                    8
+#define D0F0xBC_x1F2E8_HysteresisDown_WIDTH                     8
+#define D0F0xBC_x1F2E8_HysteresisDown_MASK                      0xff00
+#define D0F0xBC_x1F2E8_ResidencyCounter_OFFSET                  16
+#define D0F0xBC_x1F2E8_ResidencyCounter_WIDTH                   16
+#define D0F0xBC_x1F2E8_ResidencyCounter_MASK                    0xffff0000
+
+/// D0F0xBC_x1F2E8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HysteresisUp:8 ; ///<
+    UINT32                                           HysteresisDown:8 ; ///<
+    UINT32                                         ResidencyCounter:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2E8_STRUCT;
+
+// **** D0F0xBC_x1F2F0 Register Definition ****
+// Address
+#define D0F0xBC_x1F2F0_ADDRESS                                  0x1f2f0
+
+// Type
+#define D0F0xBC_x1F2F0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F2F0_ActivityThreshold_OFFSET                 0
+#define D0F0xBC_x1F2F0_ActivityThreshold_WIDTH                  8
+#define D0F0xBC_x1F2F0_ActivityThreshold_MASK                   0xff
+#define D0F0xBC_x1F2F0_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F2F0_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F2F0_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F2F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ActivityThreshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F2F0_STRUCT;
+
+// **** D0F0xBC_x1F300 Register Definition ****
+// Address
+#define D0F0xBC_x1F300_ADDRESS                                  0x1f300
+
+// Type
+#define D0F0xBC_x1F300_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F300_LclkDpmEn_OFFSET                         0
+#define D0F0xBC_x1F300_LclkDpmEn_WIDTH                          1
+#define D0F0xBC_x1F300_LclkDpmEn_MASK                           0x1
+#define D0F0xBC_x1F300_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F300_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F300_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F300_LclkDpmType_OFFSET                       8
+#define D0F0xBC_x1F300_LclkDpmType_WIDTH                        1
+#define D0F0xBC_x1F300_LclkDpmType_MASK                         0x100
+#define D0F0xBC_x1F300_Reserved_15_9_OFFSET                     9
+#define D0F0xBC_x1F300_Reserved_15_9_WIDTH                      7
+#define D0F0xBC_x1F300_Reserved_15_9_MASK                       0xfe00
+#define D0F0xBC_x1F300_LclkDpmBootState_OFFSET                  16
+#define D0F0xBC_x1F300_LclkDpmBootState_WIDTH                   8
+#define D0F0xBC_x1F300_LclkDpmBootState_MASK                    0xff0000
+#define D0F0xBC_x1F300_VoltageChgEn_OFFSET                      24
+#define D0F0xBC_x1F300_VoltageChgEn_WIDTH                       1
+#define D0F0xBC_x1F300_VoltageChgEn_MASK                        0x1000000
+#define D0F0xBC_x1F300_Reserved_31_25_OFFSET                    25
+#define D0F0xBC_x1F300_Reserved_31_25_WIDTH                     7
+#define D0F0xBC_x1F300_Reserved_31_25_MASK                      0xfe000000
+
+/// D0F0xBC_x1F300
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                LclkDpmEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                              LclkDpmType:1 ; ///<
+    UINT32                                            Reserved_15_9:7 ; ///<
+    UINT32                                         LclkDpmBootState:8 ; ///<
+    UINT32                                             VoltageChgEn:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F300_STRUCT;
+
+// **** D0F0xBC_x1F308 Register Definition ****
+// Address
+#define D0F0xBC_x1F308_ADDRESS                                  0x1f308
+
+// Type
+#define D0F0xBC_x1F308_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET           0
+#define D0F0xBC_x1F308_LclkThermalThrottlingEn_WIDTH            1
+#define D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK             0x1
+#define D0F0xBC_x1F308_Reserved_7_1_OFFSET                      1
+#define D0F0xBC_x1F308_Reserved_7_1_WIDTH                       7
+#define D0F0xBC_x1F308_Reserved_7_1_MASK                        0xfe
+#define D0F0xBC_x1F308_TemperatureSel_OFFSET                    8
+#define D0F0xBC_x1F308_TemperatureSel_WIDTH                     1
+#define D0F0xBC_x1F308_TemperatureSel_MASK                      0x100
+#define D0F0xBC_x1F308_Reserved_15_9_OFFSET                     9
+#define D0F0xBC_x1F308_Reserved_15_9_WIDTH                      7
+#define D0F0xBC_x1F308_Reserved_15_9_MASK                       0xfe00
+#define D0F0xBC_x1F308_LclkTtMode_OFFSET                        16
+#define D0F0xBC_x1F308_LclkTtMode_WIDTH                         3
+#define D0F0xBC_x1F308_LclkTtMode_MASK                          0x70000
+
+/// D0F0xBC_x1F308
+typedef union {
+  struct {                                                              ///<
+    UINT32                                  LclkThermalThrottlingEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                           TemperatureSel:1 ; ///<
+    UINT32                                            Reserved_15_9:7 ; ///<
+    UINT32                                               LclkTtMode:3 ; ///<
+    UINT32                                           :13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F308_STRUCT;
+
+// **** D0F0xBC_x1F30C Register Definition ****
+// Address
+#define D0F0xBC_x1F30C_ADDRESS                                  0x1f30c
+
+// Type
+#define D0F0xBC_x1F30C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F30C_LowThreshold_OFFSET                      0
+#define D0F0xBC_x1F30C_LowThreshold_WIDTH                       16
+#define D0F0xBC_x1F30C_LowThreshold_MASK                        0xffff
+#define D0F0xBC_x1F30C_HighThreshold_OFFSET                     16
+#define D0F0xBC_x1F30C_HighThreshold_WIDTH                      16
+#define D0F0xBC_x1F30C_HighThreshold_MASK                       0xffff0000
+
+/// D0F0xBC_x1F30C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             LowThreshold:16; ///<
+    UINT32                                            HighThreshold:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F30C_STRUCT;
+
+// **** D0F0xBC_x1F380 Register Definition ****
+// Address
+#define D0F0xBC_x1F380_ADDRESS                                  0x1f380
+
+// Type
+#define D0F0xBC_x1F380_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F380_InterruptsEnabled_OFFSET                 0
+#define D0F0xBC_x1F380_InterruptsEnabled_WIDTH                  1
+#define D0F0xBC_x1F380_InterruptsEnabled_MASK                   0x1
+#define D0F0xBC_x1F380_Reserved_23_1_OFFSET                     1
+#define D0F0xBC_x1F380_Reserved_23_1_WIDTH                      23
+#define D0F0xBC_x1F380_Reserved_23_1_MASK                       0xfffffe
+#define D0F0xBC_x1F380_TestCount_OFFSET                         24
+#define D0F0xBC_x1F380_TestCount_WIDTH                          8
+#define D0F0xBC_x1F380_TestCount_MASK                           0xff000000
+
+/// D0F0xBC_x1F380
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        InterruptsEnabled:1 ; ///<
+    UINT32                                            Reserved_23_1:23; ///<
+    UINT32                                                TestCount:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F380_STRUCT;
+
+// **** D0F0xBC_x1F384 Register Definition ****
+// Address
+#define D0F0xBC_x1F384_ADDRESS                                  0x1f384
+
+// Type
+#define D0F0xBC_x1F384_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F384_FirmwareVid_OFFSET                       0
+#define D0F0xBC_x1F384_FirmwareVid_WIDTH                        8
+#define D0F0xBC_x1F384_FirmwareVid_MASK                         0xff
+#define D0F0xBC_x1F384_Reserved_31_8_OFFSET                     8
+#define D0F0xBC_x1F384_Reserved_31_8_WIDTH                      24
+#define D0F0xBC_x1F384_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F0xBC_x1F384
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              FirmwareVid:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F384_STRUCT;
+
+// **** D0F0xBC_x1F388 Register Definition ****
+// Address
+#define D0F0xBC_x1F388_ADDRESS                                  0x1f388
+
+// Type
+#define D0F0xBC_x1F388_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F388_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F388_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F388_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F388_TcenId_OFFSET                            6
+#define D0F0xBC_x1F388_TcenId_WIDTH                             4
+#define D0F0xBC_x1F388_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F388_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F388_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F388_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F388
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  CsrAddr:6 ; ///<
+    UINT32                                                   TcenId:4 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F388_STRUCT;
+
+// **** D0F0xBC_x1F39C Register Definition ****
+// Address
+#define D0F0xBC_x1F39C_ADDRESS                                  0x1f39c
+
+// Type
+#define D0F0xBC_x1F39C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F39C_Rx_OFFSET                                0
+#define D0F0xBC_x1F39C_Rx_WIDTH                                 1
+#define D0F0xBC_x1F39C_Rx_MASK                                  0x1
+#define D0F0xBC_x1F39C_Tx_OFFSET                                1
+#define D0F0xBC_x1F39C_Tx_WIDTH                                 1
+#define D0F0xBC_x1F39C_Tx_MASK                                  0x2
+#define D0F0xBC_x1F39C_Core_OFFSET                              2
+#define D0F0xBC_x1F39C_Core_WIDTH                               1
+#define D0F0xBC_x1F39C_Core_MASK                                0x4
+#define D0F0xBC_x1F39C_SkipPhy_OFFSET                           3
+#define D0F0xBC_x1F39C_SkipPhy_WIDTH                            1
+#define D0F0xBC_x1F39C_SkipPhy_MASK                             0x8
+#define D0F0xBC_x1F39C_SkipCore_OFFSET                          4
+#define D0F0xBC_x1F39C_SkipCore_WIDTH                           1
+#define D0F0xBC_x1F39C_SkipCore_MASK                            0x10
+#define D0F0xBC_x1F39C_Reserved_15_5_OFFSET                     5
+#define D0F0xBC_x1F39C_Reserved_15_5_WIDTH                      11
+#define D0F0xBC_x1F39C_Reserved_15_5_MASK                       0xffe0
+#define D0F0xBC_x1F39C_LowerLaneID_OFFSET                       16
+#define D0F0xBC_x1F39C_LowerLaneID_WIDTH                        8
+#define D0F0xBC_x1F39C_LowerLaneID_MASK                         0xff0000
+#define D0F0xBC_x1F39C_UpperLaneID_OFFSET                       24
+#define D0F0xBC_x1F39C_UpperLaneID_WIDTH                        8
+#define D0F0xBC_x1F39C_UpperLaneID_MASK                         0xff000000
+
+/// D0F0xBC_x1F39C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                       Rx:1 ; ///<
+    UINT32                                                       Tx:1 ; ///<
+    UINT32                                                     Core:1 ; ///<
+    UINT32                                                  SkipPhy:1 ; ///<
+    UINT32                                                 SkipCore:1 ; ///<
+    UINT32                                            Reserved_15_5:11; ///<
+    UINT32                                              LowerLaneID:8 ; ///<
+    UINT32                                              UpperLaneID:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F39C_STRUCT;
+
+// **** D0F0xBC_x1F3D8 Register Definition ****
+// Address
+#define D0F0xBC_x1F3D8_ADDRESS                                  0x1f3d8
+
+// Type
+#define D0F0xBC_x1F3D8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET                     0
+#define D0F0xBC_x1F3D8_LoadLineTrim3_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim3_MASK                       0xff
+#define D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET                     8
+#define D0F0xBC_x1F3D8_LoadLineTrim2_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim2_MASK                       0xff00
+#define D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET                     16
+#define D0F0xBC_x1F3D8_LoadLineTrim1_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim1_MASK                       0xff0000
+#define D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET                     24
+#define D0F0xBC_x1F3D8_LoadLineTrim0_WIDTH                      8
+#define D0F0xBC_x1F3D8_LoadLineTrim0_MASK                       0xff000000
+
+/// D0F0xBC_x1F3D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LoadLineTrim3:8 ; ///<
+    UINT32                                            LoadLineTrim2:8 ; ///<
+    UINT32                                            LoadLineTrim1:8 ; ///<
+    UINT32                                            LoadLineTrim0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3D8_STRUCT;
+
+// **** D0F0xBC_x1F3DC Register Definition ****
+// Address
+#define D0F0xBC_x1F3DC_ADDRESS                                  0x1f3dc
+
+// Type
+#define D0F0xBC_x1F3DC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET                     0
+#define D0F0xBC_x1F3DC_LoadLineTrim7_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim7_MASK                       0xff
+#define D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET                     8
+#define D0F0xBC_x1F3DC_LoadLineTrim6_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim6_MASK                       0xff00
+#define D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET                     16
+#define D0F0xBC_x1F3DC_LoadLineTrim5_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim5_MASK                       0xff0000
+#define D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET                     24
+#define D0F0xBC_x1F3DC_LoadLineTrim4_WIDTH                      8
+#define D0F0xBC_x1F3DC_LoadLineTrim4_MASK                       0xff000000
+
+/// D0F0xBC_x1F3DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LoadLineTrim7:8 ; ///<
+    UINT32                                            LoadLineTrim6:8 ; ///<
+    UINT32                                            LoadLineTrim5:8 ; ///<
+    UINT32                                            LoadLineTrim4:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3DC_STRUCT;
+
+// **** D0F0xBC_x1F3F8 Register Definition ****
+// Address
+#define D0F0xBC_x1F3F8_ADDRESS                                  0x1f3f8
+
+// Type
+#define D0F0xBC_x1F3F8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET                0
+#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH                 8
+#define D0F0xBC_x1F3F8_SviInitLoadLineVdd_MASK                  0xff
+#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET              8
+#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH               8
+#define D0F0xBC_x1F3F8_SviInitLoadLineVddNB_MASK                0xff00
+#define D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET                   16
+#define D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH                    8
+#define D0F0xBC_x1F3F8_SviTrimValueVdd_MASK                     0xff0000
+#define D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET                 24
+#define D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH                  8
+#define D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK                   0xff000000
+
+/// D0F0xBC_x1F3F8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       SviInitLoadLineVdd:8 ; ///<
+    UINT32                                     SviInitLoadLineVddNB:8 ; ///<
+    UINT32                                          SviTrimValueVdd:8 ; ///<
+    UINT32                                        SviTrimValueVddNB:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3F8_STRUCT;
+
+// **** D0F0xBC_x1F3FC Register Definition ****
+// Address
+#define D0F0xBC_x1F3FC_ADDRESS                                  0x1f3fc
+
+// Type
+#define D0F0xBC_x1F3FC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F3FC_SviVidStepBase_OFFSET                    0
+#define D0F0xBC_x1F3FC_SviVidStepBase_WIDTH                     16
+#define D0F0xBC_x1F3FC_SviVidStepBase_MASK                      0xffff
+#define D0F0xBC_x1F3FC_SviVidStep_OFFSET                        16
+#define D0F0xBC_x1F3FC_SviVidStep_WIDTH                         16
+#define D0F0xBC_x1F3FC_SviVidStep_MASK                          0xffff0000
+
+/// D0F0xBC_x1F3FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SviVidStepBase:16; ///<
+    UINT32                                               SviVidStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F3FC_STRUCT;
+
+// **** D0F0xBC_x1F400 Register Definition ****
+// Address
+#define D0F0xBC_x1F400_ADDRESS                                  0x1f400
+
+// Type
+#define D0F0xBC_x1F400_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET              0
+#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH               8
+#define D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK                0xff
+#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET            8
+#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH             8
+#define D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK              0xff00
+#define D0F0xBC_x1F400_PstateMax_OFFSET                         16
+#define D0F0xBC_x1F400_PstateMax_WIDTH                          8
+#define D0F0xBC_x1F400_PstateMax_MASK                           0xff0000
+#define D0F0xBC_x1F400_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F400_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F400_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F400
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     SviLoadLineOffsetVdd:8 ; ///<
+    UINT32                                   SviLoadLineOffsetVddNB:8 ; ///<
+    UINT32                                                PstateMax:8 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F400_STRUCT;
+
+// **** D0F0xBC_x1F404 Register Definition ****
+// Address
+#define D0F0xBC_x1F404_ADDRESS                                  0x1f404
+
+// Type
+#define D0F0xBC_x1F404_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F404_LoadLineOffset3_OFFSET                   0
+#define D0F0xBC_x1F404_LoadLineOffset3_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset3_MASK                     0xff
+#define D0F0xBC_x1F404_LoadLineOffset2_OFFSET                   8
+#define D0F0xBC_x1F404_LoadLineOffset2_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset2_MASK                     0xff00
+#define D0F0xBC_x1F404_LoadLineOffset1_OFFSET                   16
+#define D0F0xBC_x1F404_LoadLineOffset1_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset1_MASK                     0xff0000
+#define D0F0xBC_x1F404_LoadLineOffset0_OFFSET                   24
+#define D0F0xBC_x1F404_LoadLineOffset0_WIDTH                    8
+#define D0F0xBC_x1F404_LoadLineOffset0_MASK                     0xff000000
+
+/// D0F0xBC_x1F404
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          LoadLineOffset3:8 ; ///<
+    UINT32                                          LoadLineOffset2:8 ; ///<
+    UINT32                                          LoadLineOffset1:8 ; ///<
+    UINT32                                          LoadLineOffset0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F404_STRUCT;
+
+// **** D0F0xBC_x1F428 Register Definition ****
+// Address
+#define D0F0xBC_x1F428_ADDRESS                                  0x1f428
+
+// Type
+#define D0F0xBC_x1F428_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET             0
+#define D0F0xBC_x1F428_EnableVpcAccumulators_WIDTH              1
+#define D0F0xBC_x1F428_EnableVpcAccumulators_MASK               0x1
+#define D0F0xBC_x1F428_EnableBapm_OFFSET                        1
+#define D0F0xBC_x1F428_EnableBapm_WIDTH                         1
+#define D0F0xBC_x1F428_EnableBapm_MASK                          0x2
+#define D0F0xBC_x1F428_EnableTdcLimit_OFFSET                    2
+#define D0F0xBC_x1F428_EnableTdcLimit_WIDTH                     1
+#define D0F0xBC_x1F428_EnableTdcLimit_MASK                      0x4
+#define D0F0xBC_x1F428_EnableLpmx_OFFSET                        3
+#define D0F0xBC_x1F428_EnableLpmx_WIDTH                         1
+#define D0F0xBC_x1F428_EnableLpmx_MASK                          0x8
+#define D0F0xBC_x1F428_EnableHtcLimit_OFFSET                    4
+#define D0F0xBC_x1F428_EnableHtcLimit_WIDTH                     1
+#define D0F0xBC_x1F428_EnableHtcLimit_MASK                      0x10
+#define D0F0xBC_x1F428_EnableNbDpm_OFFSET                       5
+#define D0F0xBC_x1F428_EnableNbDpm_WIDTH                        1
+#define D0F0xBC_x1F428_EnableNbDpm_MASK                         0x20
+#define D0F0xBC_x1F428_EnableLoadline_OFFSET                    6
+#define D0F0xBC_x1F428_EnableLoadline_WIDTH                     1
+#define D0F0xBC_x1F428_EnableLoadline_MASK                      0x40
+#define D0F0xBC_x1F428_Reserved_15_7_OFFSET                     7
+#define D0F0xBC_x1F428_Reserved_15_7_WIDTH                      9
+#define D0F0xBC_x1F428_Reserved_15_7_MASK                       0xff80
+#define D0F0xBC_x1F428_Reserved_23_20_OFFSET                    20
+#define D0F0xBC_x1F428_Reserved_23_20_WIDTH                     4
+#define D0F0xBC_x1F428_Reserved_23_20_MASK                      0xf00000
+#define D0F0xBC_x1F428_PstateAllCpusIdle_OFFSET                 24
+#define D0F0xBC_x1F428_PstateAllCpusIdle_WIDTH                  3
+#define D0F0xBC_x1F428_PstateAllCpusIdle_MASK                   0x7000000
+#define D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET               27
+#define D0F0xBC_x1F428_NbPstateAllCpusIdle_WIDTH                1
+#define D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK                 0x8000000
+#define D0F0xBC_x1F428_BapmCoeffOverride_OFFSET                 28
+#define D0F0xBC_x1F428_BapmCoeffOverride_WIDTH                  1
+#define D0F0xBC_x1F428_BapmCoeffOverride_MASK                   0x10000000
+#define D0F0xBC_x1F428_SviMode_OFFSET                           29
+#define D0F0xBC_x1F428_SviMode_WIDTH                            1
+#define D0F0xBC_x1F428_SviMode_MASK                             0x20000000
+#define D0F0xBC_x1F428_Reserved_31_30_OFFSET                    30
+#define D0F0xBC_x1F428_Reserved_31_30_WIDTH                     2
+#define D0F0xBC_x1F428_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F0xBC_x1F428
+typedef union {
+  struct {                                                              ///<
+    UINT32                                    EnableVpcAccumulators:1 ; ///<
+    UINT32                                               EnableBapm:1 ; ///<
+    UINT32                                           EnableTdcLimit:1 ; ///<
+    UINT32                                               EnableLpmx:1 ; ///<
+    UINT32               field_4:1;
+    UINT32                                              EnableNbDpm:1 ; ///<
+    UINT32                                           EnableLoadline:1 ; ///<
+    UINT32                                            Reserved_15_7:9 ; ///<
+    UINT32                                       :1 ; ///<
+    UINT32                                                  :1 ; ///<
+    UINT32                                                 :1 ; ///<
+    UINT32                                 line180        :1 ; ///<
+    UINT32                                           Reserved_23_20:4 ; ///<
+    UINT32                                        PstateAllCpusIdle:3 ; ///<
+    UINT32                                      NbPstateAllCpusIdle:1 ; ///<
+    UINT32                                        BapmCoeffOverride:1 ; ///<
+    UINT32                                                  SviMode:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F428_STRUCT;
+
+// **** D0F0xBC_x1F460 Register Definition ****
+// Address
+#define D0F0xBC_x1F460_ADDRESS                                  0x1f460
+
+// Type
+#define D0F0xBC_x1F460_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F460_LclkDpm_OFFSET                           0
+#define D0F0xBC_x1F460_LclkDpm_WIDTH                            8
+#define D0F0xBC_x1F460_LclkDpm_MASK                             0xff
+#define D0F0xBC_x1F460_ThermalCntl_OFFSET                       8
+#define D0F0xBC_x1F460_ThermalCntl_WIDTH                        8
+#define D0F0xBC_x1F460_ThermalCntl_MASK                         0xff00
+#define D0F0xBC_x1F460_VoltageCntl_OFFSET                       16
+#define D0F0xBC_x1F460_VoltageCntl_WIDTH                        8
+#define D0F0xBC_x1F460_VoltageCntl_MASK                         0xff0000
+#define D0F0xBC_x1F460_Loadline_OFFSET                          24
+#define D0F0xBC_x1F460_Loadline_WIDTH                           8
+#define D0F0xBC_x1F460_Loadline_MASK                            0xff000000
+
+/// D0F0xBC_x1F460
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  LclkDpm:8 ; ///<
+    UINT32                                              ThermalCntl:8 ; ///<
+    UINT32                                              VoltageCntl:8 ; ///<
+    UINT32                                                 Loadline:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F460_STRUCT;
+
+// **** D0F0xBC_x1F464 Register Definition ****
+// Address
+#define D0F0xBC_x1F464_ADDRESS                                  0x1f464
+
+// Type
+#define D0F0xBC_x1F464_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F464_SclkDpm_OFFSET                           0
+#define D0F0xBC_x1F464_SclkDpm_WIDTH                            8
+#define D0F0xBC_x1F464_SclkDpm_MASK                             0xff
+#define D0F0xBC_x1F464_StaticSimdPgCntl_OFFSET                  8
+#define D0F0xBC_x1F464_StaticSimdPgCntl_WIDTH                   8
+#define D0F0xBC_x1F464_StaticSimdPgCntl_MASK                    0xff00
+#define D0F0xBC_x1F464_DynSimdPgCntl_OFFSET                     16
+#define D0F0xBC_x1F464_DynSimdPgCntl_WIDTH                      8
+#define D0F0xBC_x1F464_DynSimdPgCntl_MASK                       0xff0000
+#define D0F0xBC_x1F464_TdpCntl_OFFSET                           24
+#define D0F0xBC_x1F464_TdpCntl_WIDTH                            8
+#define D0F0xBC_x1F464_TdpCntl_MASK                             0xff000000
+
+/// D0F0xBC_x1F464
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  SclkDpm:8 ; ///<
+    UINT32                                         StaticSimdPgCntl:8 ; ///<
+    UINT32                                            DynSimdPgCntl:8 ; ///<
+    UINT32                                                  TdpCntl:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F464_STRUCT;
+
+// **** D0F0xBC_x1F468 Register Definition ****
+// Address
+#define D0F0xBC_x1F468_ADDRESS                                  0x1f468
+
+// Type
+#define D0F0xBC_x1F468_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F468_TimerPeriod_OFFSET                       0
+#define D0F0xBC_x1F468_TimerPeriod_WIDTH                        32
+#define D0F0xBC_x1F468_TimerPeriod_MASK                         0xffffffff
+
+/// D0F0xBC_x1F468
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              TimerPeriod:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F468_STRUCT;
+
+// **** D0F0xBC_x1F46C Register Definition ****
+// Address
+#define D0F0xBC_x1F46C_ADDRESS                                  0x1f46c
+
+// Type
+#define D0F0xBC_x1F46C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F46C_VpcPeriod_OFFSET                         0
+#define D0F0xBC_x1F46C_VpcPeriod_WIDTH                          16
+#define D0F0xBC_x1F46C_VpcPeriod_MASK                           0xffff
+#define D0F0xBC_x1F46C_BapmPeriod_OFFSET                        16
+#define D0F0xBC_x1F46C_BapmPeriod_WIDTH                         8
+#define D0F0xBC_x1F46C_BapmPeriod_MASK                          0xff0000
+#define D0F0xBC_x1F46C_LpmxPeriod_OFFSET                        24
+#define D0F0xBC_x1F46C_LpmxPeriod_WIDTH                         8
+#define D0F0xBC_x1F46C_LpmxPeriod_MASK                          0xff000000
+
+/// D0F0xBC_x1F46C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                VpcPeriod:16; ///<
+    UINT32                                               BapmPeriod:8 ; ///<
+    UINT32                                               LpmxPeriod:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F46C_STRUCT;
+
+// **** D0F0xBC_x1F5F8 Register Definition ****
+// Address
+#define D0F0xBC_x1F5F8_ADDRESS                                  0x1f5f8
+
+// Type
+#define D0F0xBC_x1F5F8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET                      0
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH                       2
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsLo_MASK                        0x3
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET                      2
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH                       2
+#define D0F0xBC_x1F5F8_Dpm0PgNbPsHi_MASK                        0xc
+#define D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET                        4
+#define D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH                         2
+#define D0F0xBC_x1F5F8_DpmXNbPsLo_MASK                          0x30
+#define D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET                        6
+#define D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH                         2
+#define D0F0xBC_x1F5F8_DpmXNbPsHi_MASK                          0xc0
+#define D0F0xBC_x1F5F8_Hysteresis_OFFSET                        8
+#define D0F0xBC_x1F5F8_Hysteresis_WIDTH                         8
+#define D0F0xBC_x1F5F8_Hysteresis_MASK                          0xff00
+#define D0F0xBC_x1F5F8_SkipPG_OFFSET                            16
+#define D0F0xBC_x1F5F8_SkipPG_WIDTH                             1
+#define D0F0xBC_x1F5F8_SkipPG_MASK                              0x10000
+#define D0F0xBC_x1F5F8_SkipDPM0_OFFSET                          17
+#define D0F0xBC_x1F5F8_SkipDPM0_WIDTH                           1
+#define D0F0xBC_x1F5F8_SkipDPM0_MASK                            0x20000
+#define D0F0xBC_x1F5F8_Reserved_21_18_OFFSET                    18
+#define D0F0xBC_x1F5F8_Reserved_21_18_WIDTH                     4
+#define D0F0xBC_x1F5F8_Reserved_21_18_MASK                      0x3c0000
+#define D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET                      22
+#define D0F0xBC_x1F5F8_EnableNbPsi1_WIDTH                       1
+#define D0F0xBC_x1F5F8_EnableNbPsi1_MASK                        0x400000
+#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET               23
+#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_WIDTH                1
+#define D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK                 0x800000
+#define D0F0xBC_x1F5F8_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F5F8_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F5F8_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F5F8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Dpm0PgNbPsLo:2 ; ///<
+    UINT32                                             Dpm0PgNbPsHi:2 ; ///<
+    UINT32                                               DpmXNbPsLo:2 ; ///<
+    UINT32                                               DpmXNbPsHi:2 ; ///<
+    UINT32                                               Hysteresis:8 ; ///<
+    UINT32                                                   SkipPG:1 ; ///<
+    UINT32                                                 SkipDPM0:1 ; ///<
+    UINT32                                           Reserved_21_18:4 ; ///<
+    UINT32                                             EnableNbPsi1:1 ; ///<
+    UINT32                                      EnableDpmPstatePoll:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F5F8_STRUCT;
+
+// **** D0F0xBC_x1F5FC Register Definition ****
+// Address
+#define D0F0xBC_x1F5FC_ADDRESS                                  0x1f5fc
+
+// Type
+#define D0F0xBC_x1F5FC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F5FC_ChangeInProgress_OFFSET                  0
+#define D0F0xBC_x1F5FC_ChangeInProgress_WIDTH                   1
+#define D0F0xBC_x1F5FC_ChangeInProgress_MASK                    0x1
+#define D0F0xBC_x1F5FC_CurrentPstatePair_OFFSET                 1
+#define D0F0xBC_x1F5FC_CurrentPstatePair_WIDTH                  1
+#define D0F0xBC_x1F5FC_CurrentPstatePair_MASK                   0x2
+#define D0F0xBC_x1F5FC_Reserved_7_2_OFFSET                      2
+#define D0F0xBC_x1F5FC_Reserved_7_2_WIDTH                       6
+#define D0F0xBC_x1F5FC_Reserved_7_2_MASK                        0xfc
+#define D0F0xBC_x1F5FC_PSI1Sts_OFFSET                           8
+#define D0F0xBC_x1F5FC_PSI1Sts_WIDTH                            1
+#define D0F0xBC_x1F5FC_PSI1Sts_MASK                             0x100
+#define D0F0xBC_x1F5FC_Reserved_31_9_OFFSET                     9
+#define D0F0xBC_x1F5FC_Reserved_31_9_WIDTH                      23
+#define D0F0xBC_x1F5FC_Reserved_31_9_MASK                       0xfffffe00
+
+/// D0F0xBC_x1F5FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         ChangeInProgress:1 ; ///<
+    UINT32                                        CurrentPstatePair:1 ; ///<
+    UINT32                                             Reserved_7_2:6 ; ///<
+    UINT32                                                  PSI1Sts:1 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F5FC_STRUCT;
+
+// **** D0F0xBC_x1F610 Register Definition ****
+// Address
+#define D0F0xBC_x1F610_ADDRESS                                  0x1f610
+
+// Type
+#define D0F0xBC_x1F610_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F610_RESERVED_OFFSET                          0
+#define D0F0xBC_x1F610_RESERVED_WIDTH                           8
+#define D0F0xBC_x1F610_RESERVED_MASK                            0xff
+#define D0F0xBC_x1F610_GFXH_OFFSET                              8
+#define D0F0xBC_x1F610_GFXH_WIDTH                               8
+#define D0F0xBC_x1F610_GFXH_MASK                                0xff00
+#define D0F0xBC_x1F610_GFXL_OFFSET                              16
+#define D0F0xBC_x1F610_GFXL_WIDTH                               8
+#define D0F0xBC_x1F610_GFXL_MASK                                0xff0000
+#define D0F0xBC_x1F610_GPPSB_OFFSET                             24
+#define D0F0xBC_x1F610_GPPSB_WIDTH                              8
+#define D0F0xBC_x1F610_GPPSB_MASK                               0xff000000
+
+/// D0F0xBC_x1F610
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 RESERVED:8 ; ///<
+    UINT32                                                     GFXH:8 ; ///<
+    UINT32                                                     GFXL:8 ; ///<
+    UINT32                                                    GPPSB:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F610_STRUCT;
+
+
+// **** D0F0xBC_x1F628 Register Definition ****
+// Address
+#define D0F0xBC_x1F628_ADDRESS                                  0x1f628
+
+// Type
+#define D0F0xBC_x1F628_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F628_Reserved_15_0_OFFSET                     0
+#define D0F0xBC_x1F628_Reserved_15_0_WIDTH                      16
+#define D0F0xBC_x1F628_Reserved_15_0_MASK                       0xffff
+#define D0F0xBC_x1F628_HtcActivePstateLimit_OFFSET              16
+#define D0F0xBC_x1F628_HtcActivePstateLimit_WIDTH               8
+#define D0F0xBC_x1F628_HtcActivePstateLimit_MASK                0xff0000
+#define D0F0xBC_x1F628_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F628_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F628_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F628
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_15_0:16;///<
+    UINT32                                      HtcActivePstateLimit:8; ///<
+    UINT32                                            Reserved_31_24:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F628_STRUCT;
+
+// **** D0F0xBC_x1F62C Register Definition ****
+// Address
+#define D0F0xBC_x1F62C_ADDRESS                                  0x1f62c
+
+// Type
+#define D0F0xBC_x1F62C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F62C_Idd_OFFSET                               0
+#define D0F0xBC_x1F62C_Idd_WIDTH                                16
+#define D0F0xBC_x1F62C_Idd_MASK                                 0xffff
+#define D0F0xBC_x1F62C_Iddnb_OFFSET                             16
+#define D0F0xBC_x1F62C_Iddnb_WIDTH                              16
+#define D0F0xBC_x1F62C_Iddnb_MASK                               0xffff0000
+
+/// D0F0xBC_x1F62C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      Idd:16; ///<
+    UINT32                                                    Iddnb:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F62C_STRUCT;
+
+// **** D0F0xBC_x1F638 Register Definition ****
+// Address
+#define D0F0xBC_x1F638_ADDRESS                                  0x1f638
+
+// Type
+#define D0F0xBC_x1F638_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F638_TdcPeriod_OFFSET                         0
+#define D0F0xBC_x1F638_TdcPeriod_WIDTH                          8
+#define D0F0xBC_x1F638_TdcPeriod_MASK                           0xff
+#define D0F0xBC_x1F638_HtcPeriod_OFFSET                         8
+#define D0F0xBC_x1F638_HtcPeriod_WIDTH                          8
+#define D0F0xBC_x1F638_HtcPeriod_MASK                           0xff00
+#define D0F0xBC_x1F638_NbdpmPeriod_OFFSET                       16
+#define D0F0xBC_x1F638_NbdpmPeriod_WIDTH                        8
+#define D0F0xBC_x1F638_NbdpmPeriod_MASK                         0xff0000
+#define D0F0xBC_x1F638_PginterlockPeriod_OFFSET                 24
+#define D0F0xBC_x1F638_PginterlockPeriod_WIDTH                  8
+#define D0F0xBC_x1F638_PginterlockPeriod_MASK                   0xff000000
+
+/// D0F0xBC_x1F638
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                TdcPeriod:8 ; ///<
+    UINT32                                                HtcPeriod:8 ; ///<
+    UINT32                                              NbdpmPeriod:8 ; ///<
+    UINT32                                        PginterlockPeriod:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F638_STRUCT;
+
+// **** D0F0xBC_x1F6E4 Register Definition ****
+// Address
+#define D0F0xBC_x1F6E4_ADDRESS                                  0x1f6e4
+
+// Type
+#define D0F0xBC_x1F6E4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET                      0
+#define D0F0xBC_x1F6E4_DdrVoltFloor_WIDTH                       8
+#define D0F0xBC_x1F6E4_DdrVoltFloor_MASK                        0xff
+#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET                  8
+#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_WIDTH                   8
+#define D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK                    0xff00
+#define D0F0xBC_x1F6E4_Reserved_OFFSET                          16
+#define D0F0xBC_x1F6E4_Reserved_WIDTH                           16
+#define D0F0xBC_x1F6E4_Reserved_MASK                            0xffff0000
+
+/// D0F0xBC_x1F6E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DdrVoltFloor:8 ; ///<
+    UINT32                                         BapmDdrVoltFloor:8 ; ///<
+    UINT32                                                 Reserved:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F6E4_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32          ex996_0:8 ;
+    UINT32          ex996_1:8 ;
+    UINT32          ex996_2:8 ;
+    UINT32          ex996_3:8 ;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex996_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32           ex997_0:16;
+    UINT32           ex997_1:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex997_STRUCT;
+
+// **** D0F0xBC_x1F6B4 Register Definition ****
+// Address
+#define D0F0xBC_x1F6B4_ADDRESS                                  0x1f6b4
+
+// Type
+#define D0F0xBC_x1F6B4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F6B4_TjOffset_OFFSET                          0
+#define D0F0xBC_x1F6B4_TjOffset_WIDTH                           8
+#define D0F0xBC_x1F6B4_TjOffset_MASK                            0xff
+#define D0F0xBC_x1F6B4_Reserved_OFFSET                          8
+#define D0F0xBC_x1F6B4_Reserved_WIDTH                           24
+#define D0F0xBC_x1F6B4_Reserved_MASK                            0xffffff00
+
+/// D0F0xBC_x1F6B4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 TjOffset:8 ; ///<
+    UINT32                                                 Reserved:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F6B4_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32           ex998_0:16;
+    UINT32           ex998_1:8;
+    UINT32           ex998_2:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex998_STRUCT;
+
+// **** D0F0xBC_x1F844 Register Definition ****
+// Address
+#define D0F0xBC_x1F844_ADDRESS                                  0x1f844
+
+// Type
+#define D0F0xBC_x1F844_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F844_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F844_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F844_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F844_TcenId_OFFSET                            6
+#define D0F0xBC_x1F844_TcenId_WIDTH                             4
+#define D0F0xBC_x1F844_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F844_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F844_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F844_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F844
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CsrAddr:6; ///<
+    UINT32                                                    TcenId:4; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F844_STRUCT;
+
+// **** D0F0xBC_x1F848 Register Definition ****
+// Address
+#define D0F0xBC_x1F848_ADDRESS                                  0x1f848
+
+// Type
+#define D0F0xBC_x1F848_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F848_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F848_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F848_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F848_TcenId_OFFSET                            6
+#define D0F0xBC_x1F848_TcenId_WIDTH                             4
+#define D0F0xBC_x1F848_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F848_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F848_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F848_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F848
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CsrAddr:6; ///<
+    UINT32                                                    TcenId:4; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F848_STRUCT;
+
+// **** D0F0xBC_x1F84C Register Definition ****
+// Address
+#define D0F0xBC_x1F84C_ADDRESS                                  0x1f84c
+
+// Type
+#define D0F0xBC_x1F84C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F84C_CsrAddr_OFFSET                           0
+#define D0F0xBC_x1F84C_CsrAddr_WIDTH                            6
+#define D0F0xBC_x1F84C_CsrAddr_MASK                             0x3f
+#define D0F0xBC_x1F84C_TcenId_OFFSET                            6
+#define D0F0xBC_x1F84C_TcenId_WIDTH                             4
+#define D0F0xBC_x1F84C_TcenId_MASK                              0x3c0
+#define D0F0xBC_x1F84C_Reserved_31_10_OFFSET                    10
+#define D0F0xBC_x1F84C_Reserved_31_10_WIDTH                     22
+#define D0F0xBC_x1F84C_Reserved_31_10_MASK                      0xfffffc00
+
+/// D0F0xBC_x1F84C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   CsrAddr:6; ///<
+    UINT32                                                    TcenId:4; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F84C_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32           ex999_0:8;
+    UINT32           ex999_1:8;
+    UINT32           ex999_2:8;
+    UINT32           ex999_3:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex999_STRUCT;
+
+// **** D0F0xBC_x1F870 Register Definition ****
+// Address
+#define D0F0xBC_x1F870_ADDRESS                                  0x1f870
+
+// Type
+#define D0F0xBC_x1F870_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F870_AmbientTempBase_OFFSET                   0
+#define D0F0xBC_x1F870_AmbientTempBase_WIDTH                    8
+#define D0F0xBC_x1F870_AmbientTempBase_MASK                     0xff
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_OFFSET                 8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_WIDTH                  8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_2_MASK                   0xff00
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_OFFSET                 16
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_WIDTH                  8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_1_MASK                   0xff0000
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_OFFSET                 24
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_WIDTH                  8
+#define D0F0xBC_x1F870_BAPMTI_TjOffset_0_MASK                   0xff000000
+
+/// D0F0xBC_x1F870
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           AmbientTempBase:8; ///<
+    UINT32                                          BAPMTI_TjOffset_2:8; ///<
+    UINT32                                          BAPMTI_TjOffset_1:8; ///<
+    UINT32                                          BAPMTI_TjOffset_0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F870_STRUCT;
+
+/// D0F0xBC_x1F878
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                FUSE_DATA:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F878_STRUCT;
+
+// **** D0F0xBC_x1F87C Register Definition ****
+// Address
+#define D0F0xBC_x1F87C_ADDRESS                                  0x1f87c
+
+// Type
+#define D0F0xBC_x1F87C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_OFFSET                  0
+#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_WIDTH                   16
+#define D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK                    0xffff
+#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_OFFSET              16
+#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_WIDTH               16
+#define D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK                0xffff0000
+
+/// D0F0xBC_x1F87C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         LL_PCIE_LoadStep:16; ///<
+    UINT32                                     LL_VddNbLoadStepBase:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F87C_STRUCT;
+
+// **** D0F0xBC_x1F880 Register Definition ****
+// Address
+#define D0F0xBC_x1F880_ADDRESS                                  0x1f880
+
+// Type
+#define D0F0xBC_x1F880_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F880_LL_VCE_LoadStep_OFFSET                   0
+#define D0F0xBC_x1F880_LL_VCE_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F880_LL_VCE_LoadStep_MASK                     0xffff
+#define D0F0xBC_x1F880_LL_UVD_LoadStep_OFFSET                   16
+#define D0F0xBC_x1F880_LL_UVD_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F880_LL_UVD_LoadStep_MASK                     0xffff0000
+
+/// D0F0xBC_x1F880
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          LL_VCE_LoadStep:16; ///<
+    UINT32                                          LL_UVD_LoadStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F880_STRUCT;
+
+// **** D0F0xBC_x1F884 Register Definition ****
+// Address
+#define D0F0xBC_x1F884_ADDRESS                                  0x1f884
+
+// Type
+#define D0F0xBC_x1F884_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F884_LL_DCE2_LoadStep_OFFSET                  0
+#define D0F0xBC_x1F884_LL_DCE2_LoadStep_WIDTH                   16
+#define D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK                    0xffff
+#define D0F0xBC_x1F884_LL_DCE_LoadStep_OFFSET                   16
+#define D0F0xBC_x1F884_LL_DCE_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F884_LL_DCE_LoadStep_MASK                     0xffff0000
+
+/// D0F0xBC_x1F884
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         LL_DCE2_LoadStep:16; ///<
+    UINT32                                          LL_DCE_LoadStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F884_STRUCT;
+
+// **** D0F0xBC_x1F888 Register Definition ****
+// Address
+#define D0F0xBC_x1F888_ADDRESS                                  0x1f888
+
+// Type
+#define D0F0xBC_x1F888_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F888_VddNbTdp_OFFSET                          0
+#define D0F0xBC_x1F888_VddNbTdp_WIDTH                           16
+#define D0F0xBC_x1F888_VddNbTdp_MASK                            0xffff
+#define D0F0xBC_x1F888_LL_GPU_LoadStep_OFFSET                   16
+#define D0F0xBC_x1F888_LL_GPU_LoadStep_WIDTH                    16
+#define D0F0xBC_x1F888_LL_GPU_LoadStep_MASK                     0xffff0000
+
+/// D0F0xBC_x1F888
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 VddNbTdp:16; ///<
+    UINT32                                          LL_GPU_LoadStep:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F888_STRUCT;
+
+// **** D0F0xBC_x1F88C Register Definition ****
+// Address
+#define D0F0xBC_x1F88C_ADDRESS                                  0x1f88c
+
+// Type
+#define D0F0xBC_x1F88C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F88C_NbVid_3_OFFSET                           0
+#define D0F0xBC_x1F88C_NbVid_3_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_3_MASK                             0xff
+#define D0F0xBC_x1F88C_NbVid_2_OFFSET                           8
+#define D0F0xBC_x1F88C_NbVid_2_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_2_MASK                             0xff00
+#define D0F0xBC_x1F88C_NbVid_1_OFFSET                           16
+#define D0F0xBC_x1F88C_NbVid_1_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_1_MASK                             0xff0000
+#define D0F0xBC_x1F88C_NbVid_0_OFFSET                           24
+#define D0F0xBC_x1F88C_NbVid_0_WIDTH                            8
+#define D0F0xBC_x1F88C_NbVid_0_MASK                             0xff000000
+
+/// D0F0xBC_x1F88C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  NbVid_3:8 ; ///<
+    UINT32                                                  NbVid_2:8 ; ///<
+    UINT32                                                  NbVid_1:8 ; ///<
+    UINT32                                                  NbVid_0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F88C_STRUCT;
+
+// **** D0F0xBC_x1F890 Register Definition ****
+// Address
+#define D0F0xBC_x1F890_ADDRESS                                  0x1f890
+
+// Type
+#define D0F0xBC_x1F890_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F890_CpuVid_3_OFFSET                           0
+#define D0F0xBC_x1F890_CpuVid_3_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_3_MASK                             0xff
+#define D0F0xBC_x1F890_CpuVid_2_OFFSET                           8
+#define D0F0xBC_x1F890_CpuVid_2_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_2_MASK                             0xff00
+#define D0F0xBC_x1F890_CpuVid_1_OFFSET                           16
+#define D0F0xBC_x1F890_CpuVid_1_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_1_MASK                             0xff0000
+#define D0F0xBC_x1F890_CpuVid_0_OFFSET                           24
+#define D0F0xBC_x1F890_CpuVid_0_WIDTH                            8
+#define D0F0xBC_x1F890_CpuVid_0_MASK                             0xff000000
+
+/// D0F0xBC_x1F890
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CpuVid_3:8 ; ///<
+    UINT32                                                 CpuVid_2:8 ; ///<
+    UINT32                                                 CpuVid_1:8 ; ///<
+    UINT32                                                 CpuVid_0:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F890_STRUCT;
+
+// **** D0F0xBC_x1F894 Register Definition ****
+// Address
+#define D0F0xBC_x1F894_ADDRESS                                  0x1f894
+
+// Type
+#define D0F0xBC_x1F894_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F894_CpuVid_7_OFFSET                           0
+#define D0F0xBC_x1F894_CpuVid_7_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_7_MASK                             0xff
+#define D0F0xBC_x1F894_CpuVid_6_OFFSET                           8
+#define D0F0xBC_x1F894_CpuVid_6_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_6_MASK                             0xff00
+#define D0F0xBC_x1F894_CpuVid_5_OFFSET                           16
+#define D0F0xBC_x1F894_CpuVid_5_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_5_MASK                             0xff0000
+#define D0F0xBC_x1F894_CpuVid_4_OFFSET                           24
+#define D0F0xBC_x1F894_CpuVid_4_WIDTH                            8
+#define D0F0xBC_x1F894_CpuVid_4_MASK                             0xff000000
+
+/// D0F0xBC_x1F894
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CpuVid_7:8 ; ///<
+    UINT32                                                 CpuVid_6:8 ; ///<
+    UINT32                                                 CpuVid_5:8 ; ///<
+    UINT32                                                 CpuVid_4:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F894_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1000_0:16;
+    UINT32            ex1000_1:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1000_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1001_0:16;
+    UINT32            ex1001_1:8;
+    UINT32            ex1001_2:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1001_STRUCT;
+
+// **** D0F0xBC_x1F8D4 Register Definition ****
+// Address
+#define D0F0xBC_x1F8D4_ADDRESS                                  0x1f8d4
+
+// Type
+#define D0F0xBC_x1F8D4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8D4_BapmPstateVid_3_OFFSET                   0
+#define D0F0xBC_x1F8D4_BapmPstateVid_3_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_3_MASK                     0xff
+#define D0F0xBC_x1F8D4_BapmPstateVid_2_OFFSET                   8
+#define D0F0xBC_x1F8D4_BapmPstateVid_2_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_2_MASK                     0xff00
+#define D0F0xBC_x1F8D4_BapmPstateVid_1_OFFSET                   16
+#define D0F0xBC_x1F8D4_BapmPstateVid_1_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_1_MASK                     0xff0000
+#define D0F0xBC_x1F8D4_BapmPstateVid_0_OFFSET                   24
+#define D0F0xBC_x1F8D4_BapmPstateVid_0_WIDTH                    8
+#define D0F0xBC_x1F8D4_BapmPstateVid_0_MASK                     0xff000000
+
+/// D0F0xBC_x1F8D4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           BapmPstateVid_3:8; ///<
+    UINT32                                           BapmPstateVid_2:8; ///<
+    UINT32                                           BapmPstateVid_1:8; ///<
+    UINT32                                           BapmPstateVid_0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8D4_STRUCT;
+
+// **** D0F0xBC_x1F8D4 Register Definition ****
+// Address
+#define D0F0xBC_x1F8D8_ADDRESS                                  0x1f8d8
+
+// Type
+#define D0F0xBC_x1F8D8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8D8_BapmPstateVid_7_OFFSET                   0
+#define D0F0xBC_x1F8D8_BapmPstateVid_7_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_7_MASK                     0xff
+#define D0F0xBC_x1F8D8_BapmPstateVid_6_OFFSET                   8
+#define D0F0xBC_x1F8D8_BapmPstateVid_6_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_6_MASK                     0xff00
+#define D0F0xBC_x1F8D8_BapmPstateVid_5_OFFSET                   16
+#define D0F0xBC_x1F8D8_BapmPstateVid_5_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_5_MASK                     0xff0000
+#define D0F0xBC_x1F8D8_BapmPstateVid_4_OFFSET                   24
+#define D0F0xBC_x1F8D8_BapmPstateVid_4_WIDTH                    8
+#define D0F0xBC_x1F8D8_BapmPstateVid_4_MASK                     0xff000000
+
+/// D0F0xBC_x1F8D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           BapmPstateVid_7:8; ///<
+    UINT32                                           BapmPstateVid_6:8; ///<
+    UINT32                                           BapmPstateVid_5:8; ///<
+    UINT32                                           BapmPstateVid_4:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8D8_STRUCT;
+
+// **** D0F0xBC_x1F8DC Register Definition ****
+// Address
+#define D0F0xBC_x1F8DC_ADDRESS                                  0x1f8dc
+
+// Type
+#define D0F0xBC_x1F8DC_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8DC_SClkVid3_OFFSET                          0
+#define D0F0xBC_x1F8DC_SClkVid3_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid3_MASK                            0xff
+#define D0F0xBC_x1F8DC_SClkVid2_OFFSET                          8
+#define D0F0xBC_x1F8DC_SClkVid2_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid2_MASK                            0xff00
+#define D0F0xBC_x1F8DC_SClkVid1_OFFSET                          16
+#define D0F0xBC_x1F8DC_SClkVid1_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid1_MASK                            0xff0000
+#define D0F0xBC_x1F8DC_SClkVid0_OFFSET                          24
+#define D0F0xBC_x1F8DC_SClkVid0_WIDTH                           8
+#define D0F0xBC_x1F8DC_SClkVid0_MASK                            0xff000000
+
+/// D0F0xBC_x1F8DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  SClkVid3:8; ///<
+    UINT32                                                  SClkVid2:8; ///<
+    UINT32                                                  SClkVid1:8; ///<
+    UINT32                                                  SClkVid0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8DC_STRUCT;
+
+// **** D0F0xBC_x1F8E0 Register Definition ****
+// Address
+#define D0F0xBC_x1F8E0_ADDRESS                                  0x1f8e0
+
+// Type
+#define D0F0xBC_x1F8E0_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8E0_BapmSclkVid_2_OFFSET                     0
+#define D0F0xBC_x1F8E0_BapmSclkVid_2_WIDTH                      8
+#define D0F0xBC_x1F8E0_BapmSclkVid_2_MASK                       0xff
+#define D0F0xBC_x1F8E0_BapmSclkVid_1_OFFSET                     8
+#define D0F0xBC_x1F8E0_BapmSclkVid_1_WIDTH                      8
+#define D0F0xBC_x1F8E0_BapmSclkVid_1_MASK                       0xff00
+#define D0F0xBC_x1F8E0_BapmSclkVid_0_OFFSET                     16
+#define D0F0xBC_x1F8E0_BapmSclkVid_0_WIDTH                      8
+#define D0F0xBC_x1F8E0_BapmSclkVid_0_MASK                       0xff0000
+#define D0F0xBC_x1F8E0_DdrVoltFloor_OFFSET                      24
+#define D0F0xBC_x1F8E0_DdrVoltFloor_WIDTH                       8
+#define D0F0xBC_x1F8E0_DdrVoltFloor_MASK                        0xff000000
+
+/// D0F0xBC_x1F8E0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             BapmSclkVid_2:8; ///<
+    UINT32                                             BapmSclkVid_1:8; ///<
+    UINT32                                             BapmSclkVid_0:8; ///<
+    UINT32                                              DdrVoltFloor:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8E0_STRUCT;
+
+// **** D0F0xBC_x1F8E4 Register Definition ****
+// Address
+#define D0F0xBC_x1F8E4_ADDRESS                                  0x1f8e4
+
+// Type
+#define D0F0xBC_x1F8E4_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8E4_BapmNbVid_1_OFFSET                       0
+#define D0F0xBC_x1F8E4_BapmNbVid_1_WIDTH                        8
+#define D0F0xBC_x1F8E4_BapmNbVid_1_MASK                         0xff
+#define D0F0xBC_x1F8E4_BapmNbVid_0_OFFSET                       8
+#define D0F0xBC_x1F8E4_BapmNbVid_0_WIDTH                        8
+#define D0F0xBC_x1F8E4_BapmNbVid_0_MASK                         0xff00
+#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_OFFSET                  16
+#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_WIDTH                   8
+#define D0F0xBC_x1F8E4_BapmDdrVoltFloor_MASK                    0xff0000
+#define D0F0xBC_x1F8E4_BapmSclkVid_3_OFFSET                     24
+#define D0F0xBC_x1F8E4_BapmSclkVid_3_WIDTH                      8
+#define D0F0xBC_x1F8E4_BapmSclkVid_3_MASK                       0xff000000
+
+/// D0F0xBC_x1F8E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               BapmNbVid_1:8; ///<
+    UINT32                                               BapmNbVid_0:8; ///<
+    UINT32                                          BapmDdrVoltFloor:8; ///<
+    UINT32                                             BapmSclkVid_3:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8E4_STRUCT;
+
+// **** D0F0xBC_x1F8E8 Register Definition ****
+// Address
+#define D0F0xBC_x1F8E8_ADDRESS                                  0x1f8e8
+
+// Type
+#define D0F0xBC_x1F8E8_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F8E8_Reserved_15_0_OFFSET                     0
+#define D0F0xBC_x1F8E8_Reserved_15_0_WIDTH                      16
+#define D0F0xBC_x1F8E8_Reserved_15_0_MASK                       0xffff
+#define D0F0xBC_x1F8E8_BapmNbVid_3_OFFSET                       16
+#define D0F0xBC_x1F8E8_BapmNbVid_3_WIDTH                        8
+#define D0F0xBC_x1F8E8_BapmNbVid_3_MASK                         0xff0000
+#define D0F0xBC_x1F8E8_BapmNbVid_2_OFFSET                       24
+#define D0F0xBC_x1F8E8_BapmNbVid_2_WIDTH                        8
+#define D0F0xBC_x1F8E8_BapmNbVid_2_MASK                         0xff000000
+
+/// D0F0xBC_x1F8E8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                              BapmNbVid_3:8;  ///<
+    UINT32                                              BapmNbVid_2:8;  ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F8E8_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1002_0:10;
+    UINT32            ex1002_1:20;
+    UINT32            ex1002_2:2;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1002_STRUCT;
+
+// **** D0F0xBC_x1F85C Register Definition ****
+// Address
+#define D0F0xBC_x1F85C_ADDRESS                                  0x1f85c
+
+// Type
+#define D0F0xBC_x1F85C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F85C_VCETdp_OFFSET                            0
+#define D0F0xBC_x1F85C_VCETdp_WIDTH                             20
+#define D0F0xBC_x1F85C_VCETdp_MASK                              0xfffff
+#define D0F0xBC_x1F85C_spare8_OFFSET                            20
+#define D0F0xBC_x1F85C_spare8_WIDTH                             1
+#define D0F0xBC_x1F85C_spare8_MASK                              0x100000
+#define D0F0xBC_x1F85C_TdpAgeValue_OFFSET                       21
+#define D0F0xBC_x1F85C_TdpAgeValue_WIDTH                        3
+#define D0F0xBC_x1F85C_TdpAgeValue_MASK                         0xe00000
+#define D0F0xBC_x1F85C_TdpAgeRate_OFFSET                        24
+#define D0F0xBC_x1F85C_TdpAgeRate_WIDTH                         8
+#define D0F0xBC_x1F85C_TdpAgeRate_MASK                          0xff000000
+
+/// D0F0xBC_x1F85C
+typedef union {
+  struct {                                                               ///<
+    UINT32                                                    VCETdp:20; ///<
+    UINT32                                                    spare8:1;  ///<
+    UINT32                                               TdpAgeValue:3;  ///<
+    UINT32                                                TdpAgeRate:8;  ///<
+  } Field;                                                               ///<
+  UINT32 Value;                                                          ///<
+} D0F0xBC_x1F85C_STRUCT;
+
+// **** D0F0xBC_x1F860 Register Definition ****
+// Address
+#define D0F0xBC_x1F860_ADDRESS                                  0x1f860
+
+// Type
+#define D0F0xBC_x1F860_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_OFFSET                   0
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_WIDTH                    8
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_1_MASK                     0xff
+#define D0F0xBC_x1F860_BAPMTI_TjMax_1_OFFSET                    8
+#define D0F0xBC_x1F860_BAPMTI_TjMax_1_WIDTH                     8
+#define D0F0xBC_x1F860_BAPMTI_TjMax_1_MASK                      0xff00
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_OFFSET                   16
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_WIDTH                    8
+#define D0F0xBC_x1F860_BAPMTI_TjHyst_0_MASK                     0xff0000
+#define D0F0xBC_x1F860_BAPMTI_TjMax_0_OFFSET                    24
+#define D0F0xBC_x1F860_BAPMTI_TjMax_0_WIDTH                     8
+#define D0F0xBC_x1F860_BAPMTI_TjMax_0_MASK                      0xff000000
+
+/// D0F0xBC_x1F860
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           BAPMTI_TjHyst_1:8; ///<
+    UINT32                                            BAPMTI_TjMax_1:8; ///<
+    UINT32                                           BAPMTI_TjHyst_0:8; ///<
+    UINT32                                            BAPMTI_TjMax_0:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F860_STRUCT;
+
+// **** D0F0xBC_x1F864 Register Definition ****
+// Address
+#define D0F0xBC_x1F864_ADDRESS                                  0x1f864
+
+// Type
+#define D0F0xBC_x1F864_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F864_PCIe2PhyOffset_OFFSET                    0
+#define D0F0xBC_x1F864_PCIe2PhyOffset_WIDTH                     8
+#define D0F0xBC_x1F864_PCIe2PhyOffset_MASK                      0xff
+#define D0F0xBC_x1F864_PCIe1PhyOffset_OFFSET                    8
+#define D0F0xBC_x1F864_PCIe1PhyOffset_WIDTH                     8
+#define D0F0xBC_x1F864_PCIe1PhyOffset_MASK                      0xff00
+#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_OFFSET                  16
+#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_WIDTH                   8
+#define D0F0xBC_x1F864_BAPMTI_GpuTjHyst_MASK                    0xff0000
+#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_OFFSET                   24
+#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_WIDTH                    8
+#define D0F0xBC_x1F864_BAPMTI_GpuTjMax_MASK                     0xff000000
+
+/// D0F0xBC_x1F864
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PCIe2PhyOffset:8; ///<
+    UINT32                                            PCIe1PhyOffset:8; ///<
+    UINT32                                          BAPMTI_GpuTjHyst:8; ///<
+    UINT32                                           BAPMTI_GpuTjMax:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F864_STRUCT;
+
+// **** D0F0xBC_x1F86C Register Definition ****
+// Address
+#define D0F0xBC_x1F86C_ADDRESS                                  0x1f86c
+
+// Type
+#define D0F0xBC_x1F86C_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F86C_Reserved_22_0_OFFSET                     0
+#define D0F0xBC_x1F86C_Reserved_22_0_WIDTH                      23
+#define D0F0xBC_x1F86C_Reserved_22_0_MASK                       0x7fffff
+#define D0F0xBC_x1F86C_BapmLhtcCap_OFFSET                       23
+#define D0F0xBC_x1F86C_BapmLhtcCap_WIDTH                        1
+#define D0F0xBC_x1F86C_BapmLhtcCap_MASK                         0x800000
+#define D0F0xBC_x1F86C_Reserved_31_24_OFFSET                    24
+#define D0F0xBC_x1F86C_Reserved_31_24_WIDTH                     8
+#define D0F0xBC_x1F86C_Reserved_31_24_MASK                      0xff000000
+
+/// D0F0xBC_x1F86C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_22_0:23;///<
+    UINT32                                               BapmLhtcCap:1; ///<
+    UINT32                                            Reserved_31_24:8; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F86C_STRUCT;
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1003_0:32;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1003_STRUCT;
+
+
+
+// **** D0F0xBC_x1FE00 Register Definition ****
+// Address
+#define D0F0xBC_x1FE00_ADDRESS                                  0x1fe00
+
+// Type
+#define D0F0xBC_x1FE00_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1FE00_Data_OFFSET                              0
+#define D0F0xBC_x1FE00_Data_WIDTH                               32
+#define D0F0xBC_x1FE00_Data_MASK                                0xffffffff
+
+/// D0F0xBC_x1FE00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     Data:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1FE00_STRUCT;
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              INTR_MASK_0:1 ; ///<
+    UINT32                                              INTR_MASK_1:1 ; ///<
+    UINT32                                              INTR_MASK_2:1 ; ///<
+    UINT32                                              INTR_MASK_3:1 ; ///<
+    UINT32                                              INTR_MASK_4:1 ; ///<
+    UINT32                                              INTR_MASK_5:1 ; ///<
+    UINT32                                              INTR_MASK_6:1 ; ///<
+    UINT32                                              INTR_MASK_7:1 ; ///<
+    UINT32                                              INTR_MASK_8:1 ; ///<
+    UINT32                                              INTR_MASK_9:1 ; ///<
+    UINT32                                             INTR_MASK_10:1 ; ///<
+    UINT32                                             INTR_MASK_11:1 ; ///<
+    UINT32                                             INTR_MASK_12:1 ; ///<
+    UINT32                                             INTR_MASK_13:1 ; ///<
+    UINT32                                             INTR_MASK_14:1 ; ///<
+    UINT32                                             INTR_MASK_15:1 ; ///<
+    UINT32                                             INTR_MASK_16:1 ; ///<
+    UINT32                                             INTR_MASK_17:1 ; ///<
+    UINT32                                             INTR_MASK_18:1 ; ///<
+    UINT32                                             INTR_MASK_19:1 ; ///<
+    UINT32                                             INTR_MASK_20:1 ; ///<
+    UINT32                                             INTR_MASK_21:1 ; ///<
+    UINT32                                             INTR_MASK_22:1 ; ///<
+    UINT32                                             INTR_MASK_23:1 ; ///<
+    UINT32                                             INTR_MASK_24:1 ; ///<
+    UINT32                                             INTR_MASK_25:1 ; ///<
+    UINT32                                             INTR_MASK_26:1 ; ///<
+    UINT32                                             INTR_MASK_27:1 ; ///<
+    UINT32                                             INTR_MASK_28:1 ; ///<
+    UINT32                                             INTR_MASK_29:1 ; ///<
+    UINT32                                             INTR_MASK_30:1 ; ///<
+    UINT32                                             INTR_MASK_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1005_STRUCT;
+
+// **** D0F0xBC_xE0000004 Register Definition ****
+// Address
+#define D0F0xBC_xE0000004_ADDRESS                               0xe0000004
+
+// Type
+#define D0F0xBC_xE0000004_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_OFFSET            0
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_WIDTH             1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_req_MASK              0x1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_OFFSET           1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_WIDTH            1
+#define D0F0xBC_xE0000004_RCU_TST_jpc_rep_done_MASK             0x2
+#define D0F0xBC_xE0000004_drv_rst_mode_OFFSET                   2
+#define D0F0xBC_xE0000004_drv_rst_mode_WIDTH                    1
+#define D0F0xBC_xE0000004_drv_rst_mode_MASK                     0x4
+#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_OFFSET    3
+#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_WIDTH     1
+#define D0F0xBC_xE0000004_SMU_DC_efuse_status_invalid_MASK      0x8
+#define D0F0xBC_xE0000004_Reserved_OFFSET                       4
+#define D0F0xBC_xE0000004_Reserved_WIDTH                        1
+#define D0F0xBC_xE0000004_Reserved_MASK                         0x10
+#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_OFFSET      5
+#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_WIDTH       1
+#define D0F0xBC_xE0000004_TST_RCU_jpc_DtmSMSCntDone_MASK        0x20
+#define D0F0xBC_xE0000004_TP_Tester_OFFSET                      6
+#define D0F0xBC_xE0000004_TP_Tester_WIDTH                       1
+#define D0F0xBC_xE0000004_TP_Tester_MASK                        0x40
+#define D0F0xBC_xE0000004_boot_seq_done_OFFSET                  7
+#define D0F0xBC_xE0000004_boot_seq_done_WIDTH                   1
+#define D0F0xBC_xE0000004_boot_seq_done_MASK                    0x80
+#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_OFFSET           8
+#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_WIDTH            1
+#define D0F0xBC_xE0000004_sclk_deep_sleep_exit_MASK             0x100
+#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_OFFSET               9
+#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_WIDTH                1
+#define D0F0xBC_xE0000004_BREAK_PT1_ACTIVE_MASK                 0x200
+#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_OFFSET               10
+#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_WIDTH                1
+#define D0F0xBC_xE0000004_BREAK_PT2_ACTIVE_MASK                 0x400
+#define D0F0xBC_xE0000004_FCH_HALT_OFFSET                       11
+#define D0F0xBC_xE0000004_FCH_HALT_WIDTH                        1
+#define D0F0xBC_xE0000004_FCH_HALT_MASK                         0x800
+#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_OFFSET         12
+#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_WIDTH          1
+#define D0F0xBC_xE0000004_FCH_LOCKDOWN_WRITE_DIS_MASK           0x1000
+#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_OFFSET           13
+#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_WIDTH            1
+#define D0F0xBC_xE0000004_RCU_GIO_fch_lockdown_MASK             0x2000
+#define D0F0xBC_xE0000004_Reserved14_23_OFFSET                  14
+#define D0F0xBC_xE0000004_Reserved14_23_WIDTH                   10
+#define D0F0xBC_xE0000004_Reserved14_23_MASK                    0xffc000
+#define D0F0xBC_xE0000004_lm32_irq31_sel_OFFSET                 24
+#define D0F0xBC_xE0000004_lm32_irq31_sel_WIDTH                  2
+#define D0F0xBC_xE0000004_lm32_irq31_sel_MASK                   0x3000000
+#define D0F0xBC_xE0000004_Reserved26_31_OFFSET                  26
+#define D0F0xBC_xE0000004_Reserved26_31_WIDTH                   6
+#define D0F0xBC_xE0000004_Reserved26_31_MASK                    0xfc000000
+
+/// D0F0xBC_xE0000004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      RCU_TST_jpc_rep_req:1 ; ///<
+    UINT32                                     RCU_TST_jpc_rep_done:1 ; ///<
+    UINT32                                             drv_rst_mode:1 ; ///<
+    UINT32                              SMU_DC_efuse_status_invalid:1 ; ///<
+    UINT32                                                 Reserved:1 ; ///<
+    UINT32                                TST_RCU_jpc_DtmSMSCntDone:1 ; ///<
+    UINT32                                                TP_Tester:1 ; ///<
+    UINT32                                            boot_seq_done:1 ; ///<
+    UINT32                                     sclk_deep_sleep_exit:1 ; ///<
+    UINT32                                         BREAK_PT1_ACTIVE:1 ; ///<
+    UINT32                                         BREAK_PT2_ACTIVE:1 ; ///<
+    UINT32                                                 FCH_HALT:1 ; ///<
+    UINT32                                   FCH_LOCKDOWN_WRITE_DIS:1 ; ///<
+    UINT32                                     RCU_GIO_fch_lockdown:1 ; ///<
+    UINT32                                            Reserved14_23:10; ///<
+    UINT32                                           lm32_irq31_sel:2 ; ///<
+    UINT32                                            Reserved26_31:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0000004_STRUCT;
+
+// **** D0F0xBC_xE0000120 Register Definition ****
+// Address
+#define D0F0xBC_xE0000120_ADDRESS                               0xe0000120
+
+// Type
+#define D0F0xBC_xE0000120_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0000120_ActivityCntRst_OFFSET                 0
+#define D0F0xBC_xE0000120_ActivityCntRst_WIDTH                  1
+#define D0F0xBC_xE0000120_ActivityCntRst_MASK                   0x1
+#define D0F0xBC_xE0000120_PeriodCntRst_OFFSET                   1
+#define D0F0xBC_xE0000120_PeriodCntRst_WIDTH                    1
+#define D0F0xBC_xE0000120_PeriodCntRst_MASK                     0x2
+#define D0F0xBC_xE0000120_Reserved_2_2_OFFSET                   2
+#define D0F0xBC_xE0000120_Reserved_2_2_WIDTH                    1
+#define D0F0xBC_xE0000120_Reserved_2_2_MASK                     0x4
+#define D0F0xBC_xE0000120_BusyCntSel_OFFSET                     3
+#define D0F0xBC_xE0000120_BusyCntSel_WIDTH                      2
+#define D0F0xBC_xE0000120_BusyCntSel_MASK                       0x18
+#define D0F0xBC_xE0000120_Reserved_7_5_OFFSET                   5
+#define D0F0xBC_xE0000120_Reserved_7_5_WIDTH                    3
+#define D0F0xBC_xE0000120_Reserved_7_5_MASK                     0xe0
+#define D0F0xBC_xE0000120_EnBifCnt_OFFSET                       8
+#define D0F0xBC_xE0000120_EnBifCnt_WIDTH                        1
+#define D0F0xBC_xE0000120_EnBifCnt_MASK                         0x100
+#define D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET                     9
+#define D0F0xBC_xE0000120_EnOrbUsCnt_WIDTH                      1
+#define D0F0xBC_xE0000120_EnOrbUsCnt_MASK                       0x200
+#define D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET                     10
+#define D0F0xBC_xE0000120_EnOrbDsCnt_WIDTH                      1
+#define D0F0xBC_xE0000120_EnOrbDsCnt_MASK                       0x400
+#define D0F0xBC_xE0000120_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE0000120_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE0000120_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE0000120
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           ActivityCntRst:1 ; ///<
+    UINT32                                             PeriodCntRst:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                               BusyCntSel:2 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                                 EnBifCnt:1 ; ///<
+    UINT32                                               EnOrbUsCnt:1 ; ///<
+    UINT32                                               EnOrbDsCnt:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0000120_STRUCT;
+
+// **** D0F0xBC_xE0001008 Register Definition ****
+// Address
+#define D0F0xBC_xE0001008_ADDRESS                               0xe0001008
+
+// Type
+#define D0F0xBC_xE0001008_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0001008_SClkVid0_OFFSET                       0
+#define D0F0xBC_xE0001008_SClkVid0_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid0_MASK                         0xff
+#define D0F0xBC_xE0001008_SClkVid1_OFFSET                       8
+#define D0F0xBC_xE0001008_SClkVid1_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid1_MASK                         0xff00
+#define D0F0xBC_xE0001008_SClkVid2_OFFSET                       16
+#define D0F0xBC_xE0001008_SClkVid2_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid2_MASK                         0xff0000
+#define D0F0xBC_xE0001008_SClkVid3_OFFSET                       24
+#define D0F0xBC_xE0001008_SClkVid3_WIDTH                        8
+#define D0F0xBC_xE0001008_SClkVid3_MASK                         0xff000000
+
+/// D0F0xBC_xE0001008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 SClkVid0:8 ; ///<
+    UINT32                                                 SClkVid1:8 ; ///<
+    UINT32                                                 SClkVid2:8 ; ///<
+    UINT32                                                 SClkVid3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0001008_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 WriteDis:1 ; ///<
+    UINT32                                                    RfRm7:1 ; ///<
+    UINT32                                                      Rme:1 ; ///<
+    UINT32                                             MbistDisable:1 ; ///<
+    UINT32                                        HardRepairDisable:1 ; ///<
+    UINT32                                        SoftRepairDisable:1 ; ///<
+    UINT32                                         SmsPwrdwnDisable:1 ; ///<
+    UINT32                                           Crbbmp1500Disa:1 ; ///<
+    UINT32                                           Crbbmp1500Disb:1 ; ///<
+    UINT32                                                   GpuDis:1 ; ///<
+    UINT32                      ex1006_0:6;
+    UINT32                      ex1006_1:2;
+    UINT32                                                DftSpare1:1 ; ///<
+    UINT32                                                DftSpare2:1 ; ///<
+    UINT32                                                DftSpare3:1 ; ///<
+    UINT32                                               VceDisable:1 ; ///<
+    UINT32                                           DceScanDisable:1 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1006_STRUCT;
+
+// **** D0F0xBC_xE0003000 Register Definition ****
+// Address
+#define D0F0xBC_xE0003000_ADDRESS                               0xe0003000
+
+// Type
+#define D0F0xBC_xE0003000_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003000_IntToggle_OFFSET                      0
+#define D0F0xBC_xE0003000_IntToggle_WIDTH                       1
+#define D0F0xBC_xE0003000_IntToggle_MASK                        0x1
+#define D0F0xBC_xE0003000_ServiceIndex_OFFSET                   1
+#define D0F0xBC_xE0003000_ServiceIndex_WIDTH                    16
+#define D0F0xBC_xE0003000_ServiceIndex_MASK                     0x1fffe
+#define D0F0xBC_xE0003000_Reserved_31_17_OFFSET                 17
+#define D0F0xBC_xE0003000_Reserved_31_17_WIDTH                  15
+#define D0F0xBC_xE0003000_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xBC_xE0003000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                IntToggle:1 ; ///<
+    UINT32                                             ServiceIndex:16; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003000_STRUCT;
+
+// **** D0F0xBC_xE0003004 Register Definition ****
+// Address
+#define D0F0xBC_xE0003004_ADDRESS                               0xe0003004
+
+// Type
+#define D0F0xBC_xE0003004_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003004_IntAck_OFFSET                         0
+#define D0F0xBC_xE0003004_IntAck_WIDTH                          1
+#define D0F0xBC_xE0003004_IntAck_MASK                           0x1
+#define D0F0xBC_xE0003004_IntDone_OFFSET                        1
+#define D0F0xBC_xE0003004_IntDone_WIDTH                         1
+#define D0F0xBC_xE0003004_IntDone_MASK                          0x2
+#define D0F0xBC_xE0003004_Reserved_31_2_OFFSET                  2
+#define D0F0xBC_xE0003004_Reserved_31_2_WIDTH                   30
+#define D0F0xBC_xE0003004_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xBC_xE0003004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   IntAck:1 ; ///<
+    UINT32                                                  IntDone:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003004_STRUCT;
+
+// **** D0F0xBC_xE0003024 Register Definition ****
+// Address
+#define D0F0xBC_xE0003024_ADDRESS                               0xe0003024
+
+// Type
+#define D0F0xBC_xE0003024_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003024_SMU_SCRATCH_A_OFFSET                  0
+#define D0F0xBC_xE0003024_SMU_SCRATCH_A_WIDTH                   32
+#define D0F0xBC_xE0003024_SMU_SCRATCH_A_MASK                    0xffffffff
+
+/// D0F0xBC_xE0003024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            SMU_SCRATCH_A:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003024_STRUCT;
+
+// **** D0F0xBC_xE0003034 Register Definition ****
+// Address
+#define D0F0xBC_xE0003034_ADDRESS                               0xe0003034
+
+// Type
+#define D0F0xBC_xE0003034_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003034_PmAllcpusincc6_OFFSET                 0
+#define D0F0xBC_xE0003034_PmAllcpusincc6_WIDTH                  1
+#define D0F0xBC_xE0003034_PmAllcpusincc6_MASK                   0x1
+#define D0F0xBC_xE0003034_PmNbps_OFFSET                         1
+#define D0F0xBC_xE0003034_PmNbps_WIDTH                          1
+#define D0F0xBC_xE0003034_PmNbps_MASK                           0x2
+#define D0F0xBC_xE0003034_PmCommitselfrefr_OFFSET               2
+#define D0F0xBC_xE0003034_PmCommitselfrefr_WIDTH                2
+#define D0F0xBC_xE0003034_PmCommitselfrefr_MASK                 0xc
+#define D0F0xBC_xE0003034_PmPreselfrefresh_OFFSET               4
+#define D0F0xBC_xE0003034_PmPreselfrefresh_WIDTH                1
+#define D0F0xBC_xE0003034_PmPreselfrefresh_MASK                 0x10
+#define D0F0xBC_xE0003034_PmReqnbpstate_OFFSET                  5
+#define D0F0xBC_xE0003034_PmReqnbpstate_WIDTH                   1
+#define D0F0xBC_xE0003034_PmReqnbpstate_MASK                    0x20
+#define D0F0xBC_xE0003034_Reserved_8_6_OFFSET                   6
+#define D0F0xBC_xE0003034_Reserved_8_6_WIDTH                    3
+#define D0F0xBC_xE0003034_Reserved_8_6_MASK                     0x1c0
+#define D0F0xBC_xE0003034_NbNbps_OFFSET                         9
+#define D0F0xBC_xE0003034_NbNbps_WIDTH                          1
+#define D0F0xBC_xE0003034_NbNbps_MASK                           0x200
+#define D0F0xBC_xE0003034_NbCommitselfrefr_OFFSET               10
+#define D0F0xBC_xE0003034_NbCommitselfrefr_WIDTH                2
+#define D0F0xBC_xE0003034_NbCommitselfrefr_MASK                 0xc00
+#define D0F0xBC_xE0003034_NbPreselfrefresh_OFFSET               12
+#define D0F0xBC_xE0003034_NbPreselfrefresh_WIDTH                1
+#define D0F0xBC_xE0003034_NbPreselfrefresh_MASK                 0x1000
+#define D0F0xBC_xE0003034_NbReqnbpstate_OFFSET                  13
+#define D0F0xBC_xE0003034_NbReqnbpstate_WIDTH                   1
+#define D0F0xBC_xE0003034_NbReqnbpstate_MASK                    0x2000
+#define D0F0xBC_xE0003034_McNbps_OFFSET                         14
+#define D0F0xBC_xE0003034_McNbps_WIDTH                          1
+#define D0F0xBC_xE0003034_McNbps_MASK                           0x4000
+#define D0F0xBC_xE0003034_GmconCommitselfrefr_OFFSET            15
+#define D0F0xBC_xE0003034_GmconCommitselfrefr_WIDTH             2
+#define D0F0xBC_xE0003034_GmconCommitselfrefr_MASK              0x18000
+#define D0F0xBC_xE0003034_GmconPreselfrefresh_OFFSET            17
+#define D0F0xBC_xE0003034_GmconPreselfrefresh_WIDTH             1
+#define D0F0xBC_xE0003034_GmconPreselfrefresh_MASK              0x20000
+#define D0F0xBC_xE0003034_GmconReqnbpstate_OFFSET               18
+#define D0F0xBC_xE0003034_GmconReqnbpstate_WIDTH                1
+#define D0F0xBC_xE0003034_GmconReqnbpstate_MASK                 0x40000
+#define D0F0xBC_xE0003034_SysIso_OFFSET                         19
+#define D0F0xBC_xE0003034_SysIso_WIDTH                          1
+#define D0F0xBC_xE0003034_SysIso_MASK                           0x80000
+#define D0F0xBC_xE0003034_CpIso_OFFSET                          20
+#define D0F0xBC_xE0003034_CpIso_WIDTH                           1
+#define D0F0xBC_xE0003034_CpIso_MASK                            0x100000
+#define D0F0xBC_xE0003034_Dc0Iso_OFFSET                         21
+#define D0F0xBC_xE0003034_Dc0Iso_WIDTH                          1
+#define D0F0xBC_xE0003034_Dc0Iso_MASK                           0x200000
+#define D0F0xBC_xE0003034_Dc1Iso_OFFSET                         22
+#define D0F0xBC_xE0003034_Dc1Iso_WIDTH                          1
+#define D0F0xBC_xE0003034_Dc1Iso_MASK                           0x400000
+#define D0F0xBC_xE0003034_DciIso_OFFSET                         23
+#define D0F0xBC_xE0003034_DciIso_WIDTH                          1
+#define D0F0xBC_xE0003034_DciIso_MASK                           0x800000
+#define D0F0xBC_xE0003034_DcipgIso_OFFSET                       24
+#define D0F0xBC_xE0003034_DcipgIso_WIDTH                        1
+#define D0F0xBC_xE0003034_DcipgIso_MASK                         0x1000000
+#define D0F0xBC_xE0003034_DdiIso_OFFSET                         25
+#define D0F0xBC_xE0003034_DdiIso_WIDTH                          1
+#define D0F0xBC_xE0003034_DdiIso_MASK                           0x2000000
+#define D0F0xBC_xE0003034_GmcIso_OFFSET                         26
+#define D0F0xBC_xE0003034_GmcIso_WIDTH                          1
+#define D0F0xBC_xE0003034_GmcIso_MASK                           0x4000000
+#define D0F0xBC_xE0003034_Reserved_27_27_OFFSET                 27
+#define D0F0xBC_xE0003034_Reserved_27_27_WIDTH                  1
+#define D0F0xBC_xE0003034_Reserved_27_27_MASK                   0x8000000
+#define D0F0xBC_xE0003034_GmcPmSel_OFFSET                       28
+#define D0F0xBC_xE0003034_GmcPmSel_WIDTH                        2
+#define D0F0xBC_xE0003034_GmcPmSel_MASK                         0x30000000
+#define D0F0xBC_xE0003034_CpPmSel_OFFSET                        30
+#define D0F0xBC_xE0003034_CpPmSel_WIDTH                         2
+#define D0F0xBC_xE0003034_CpPmSel_MASK                          0xc0000000
+
+/// D0F0xBC_xE0003034
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PmAllcpusincc6:1 ; ///<
+    UINT32                                                   PmNbps:1 ; ///<
+    UINT32                                         PmCommitselfrefr:2 ; ///<
+    UINT32                                         PmPreselfrefresh:1 ; ///<
+    UINT32                                            PmReqnbpstate:1 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                                   NbNbps:1 ; ///<
+    UINT32                                         NbCommitselfrefr:2 ; ///<
+    UINT32                                         NbPreselfrefresh:1 ; ///<
+    UINT32                                            NbReqnbpstate:1 ; ///<
+    UINT32                                                   McNbps:1 ; ///<
+    UINT32                                      GmconCommitselfrefr:2 ; ///<
+    UINT32                                      GmconPreselfrefresh:1 ; ///<
+    UINT32                                         GmconReqnbpstate:1 ; ///<
+    UINT32                                                   SysIso:1 ; ///<
+    UINT32                                                    CpIso:1 ; ///<
+    UINT32                                                   Dc0Iso:1 ; ///<
+    UINT32                                                   Dc1Iso:1 ; ///<
+    UINT32                                                   DciIso:1 ; ///<
+    UINT32                                                 DcipgIso:1 ; ///<
+    UINT32                                                   DdiIso:1 ; ///<
+    UINT32                                                   GmcIso:1 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                                 GmcPmSel:2 ; ///<
+    UINT32                                                  CpPmSel:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003034_STRUCT;
+
+// **** D0F0xBC_xE0003048 Register Definition ****
+// Address
+#define D0F0xBC_xE0003048_ADDRESS                               0xe0003048
+
+// Type
+#define D0F0xBC_xE0003048_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003048_Fracv_OFFSET                          0
+#define D0F0xBC_xE0003048_Fracv_WIDTH                           12
+#define D0F0xBC_xE0003048_Fracv_MASK                            0xfff
+#define D0F0xBC_xE0003048_Intv_OFFSET                           12
+#define D0F0xBC_xE0003048_Intv_WIDTH                            7
+#define D0F0xBC_xE0003048_Intv_MASK                             0x7f000
+#define D0F0xBC_xE0003048_Reserved_31_19_OFFSET                 19
+#define D0F0xBC_xE0003048_Reserved_31_19_WIDTH                  13
+#define D0F0xBC_xE0003048_Reserved_31_19_MASK                   0xfff80000
+
+/// D0F0xBC_xE0003048
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    Fracv:12; ///<
+    UINT32                                                     Intv:7 ; ///<
+    UINT32                                           Reserved_31_19:13; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003048_STRUCT;
+
+// **** D0F0xBC_xE0003088 Register Definition ****
+// Address
+#define D0F0xBC_xE0003088_ADDRESS                               0xe0003088
+
+// Type
+#define D0F0xBC_xE0003088_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0003088_SmuAuthDone_OFFSET                    0
+#define D0F0xBC_xE0003088_SmuAuthDone_WIDTH                     1
+#define D0F0xBC_xE0003088_SmuAuthDone_MASK                      0x1
+#define D0F0xBC_xE0003088_SmuAuthPass_OFFSET                    1
+#define D0F0xBC_xE0003088_SmuAuthPass_WIDTH                     1
+#define D0F0xBC_xE0003088_SmuAuthPass_MASK                      0x2
+#define D0F0xBC_xE0003088_Reserved_31_2_OFFSET                  2
+#define D0F0xBC_xE0003088_Reserved_31_2_WIDTH                   30
+#define D0F0xBC_xE0003088_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xBC_xE0003088
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              SmuAuthDone:1 ; ///<
+    UINT32                                              SmuAuthPass:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0003088_STRUCT;
+
+// **** D0F0xBC_xE00030A4 Register Definition ****
+// Address
+#define D0F0xBC_xE00030A4_ADDRESS                               0xe00030a4
+
+// Type
+#define D0F0xBC_xE00030A4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE00030A4_Reserved_15_0_OFFSET                  0
+#define D0F0xBC_xE00030A4_Reserved_15_0_WIDTH                   16
+#define D0F0xBC_xE00030A4_Reserved_15_0_MASK                    0xffff
+#define D0F0xBC_xE00030A4_SmuProtectedMode_OFFSET               16
+#define D0F0xBC_xE00030A4_SmuProtectedMode_WIDTH                1
+#define D0F0xBC_xE00030A4_SmuProtectedMode_MASK                 0x10000
+#define D0F0xBC_xE00030A4_Reserved_31_17_OFFSET                 17
+#define D0F0xBC_xE00030A4_Reserved_31_17_WIDTH                  15
+#define D0F0xBC_xE00030A4_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xBC_xE00030A4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                         SmuProtectedMode:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE00030A4_STRUCT;
+
+// **** D0F0xBC_xE0104040 Register Definition ****
+// Address
+#define D0F0xBC_xE0104040_ADDRESS                               0xe0104040
+
+// Type
+#define D0F0xBC_xE0104040_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0104040_Reserved_6_0_OFFSET                   0
+#define D0F0xBC_xE0104040_Reserved_6_0_WIDTH                    7
+#define D0F0xBC_xE0104040_Reserved_6_0_MASK                     0x7f
+#define D0F0xBC_xE0104040_DeviceID_OFFSET                       7
+#define D0F0xBC_xE0104040_DeviceID_WIDTH                        16
+#define D0F0xBC_xE0104040_DeviceID_MASK                         0x7fff80
+#define D0F0xBC_xE0104040_Reserved_31_17_OFFSET                 23
+#define D0F0xBC_xE0104040_Reserved_31_17_WIDTH                  9
+#define D0F0xBC_xE0104040_Reserved_31_17_MASK                   0xff800000
+
+/// D0F0xBC_xE0104040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_6_0:7;  ///<
+    UINT32                                                DeviceID:16 ; ///<
+    UINT32                                           Reserved_31_23:9; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104040_STRUCT;
+
+// **** D0F0xBC_xE0104168 Register Definition ****
+// Address
+#define D0F0xBC_xE0104168_ADDRESS                               0xe0104168
+
+// Type
+#define D0F0xBC_xE0104168_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0104168_GnbLPML15_5_0_OFFSET                  0
+#define D0F0xBC_xE0104168_GnbLPML15_5_0_WIDTH                   6
+#define D0F0xBC_xE0104168_GnbLPML15_5_0_MASK                    0x3f
+#define D0F0xBC_xE0104168_MemClkVid0_7_0_OFFSET                 6
+#define D0F0xBC_xE0104168_MemClkVid0_7_0_WIDTH                  8
+#define D0F0xBC_xE0104168_MemClkVid0_7_0_MASK                   0x3fc0
+#define D0F0xBC_xE0104168_MemClkVid1_7_0_OFFSET                 14
+#define D0F0xBC_xE0104168_MemClkVid1_7_0_WIDTH                  8
+#define D0F0xBC_xE0104168_MemClkVid1_7_0_MASK                   0x3fc000
+#define D0F0xBC_xE0104168_MemClkVid2_7_0_OFFSET                 22
+#define D0F0xBC_xE0104168_MemClkVid2_7_0_WIDTH                  8
+#define D0F0xBC_xE0104168_MemClkVid2_7_0_MASK                   0x3fc00000
+#define D0F0xBC_xE0104168_MemClkVid3_1_0_OFFSET                 30
+#define D0F0xBC_xE0104168_MemClkVid3_1_0_WIDTH                  2
+#define D0F0xBC_xE0104168_MemClkVid3_1_0_MASK                   0xc0000000
+
+/// D0F0xBC_xE0104168
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            GnbLPML15_5_0:6 ; ///<
+    UINT32                                           MemClkVid0_7_0:8 ; ///<
+    UINT32                                           MemClkVid1_7_0:8 ; ///<
+    UINT32                                           MemClkVid2_7_0:8 ; ///<
+    UINT32                                           MemClkVid3_1_0:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104168_STRUCT;
+
+// **** D0F0xBC_xE010416C Register Definition ****
+// Address
+#define D0F0xBC_xE010416C_ADDRESS                               0xe010416c
+
+// Type
+#define D0F0xBC_xE010416C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE010416C_MemClkVid3_7_2_OFFSET                 0
+#define D0F0xBC_xE010416C_MemClkVid3_7_2_WIDTH                  6
+#define D0F0xBC_xE010416C_MemClkVid3_7_2_MASK                   0x3f
+#define D0F0xBC_xE010416C_MemClkVid4_7_0_OFFSET                 6
+#define D0F0xBC_xE010416C_MemClkVid4_7_0_WIDTH                  8
+#define D0F0xBC_xE010416C_MemClkVid4_7_0_MASK                   0x3fc0
+#define D0F0xBC_xE010416C_MemClkVid5_7_0_OFFSET                 14
+#define D0F0xBC_xE010416C_MemClkVid5_7_0_WIDTH                  8
+#define D0F0xBC_xE010416C_MemClkVid5_7_0_MASK                   0x3fc000
+#define D0F0xBC_xE010416C_MemClkVid6_7_0_OFFSET                 22
+#define D0F0xBC_xE010416C_MemClkVid6_7_0_WIDTH                  8
+#define D0F0xBC_xE010416C_MemClkVid6_7_0_MASK                   0x3fc00000
+#define D0F0xBC_xE010416C_MemClkVid7_1_0_OFFSET                 30
+#define D0F0xBC_xE010416C_MemClkVid7_1_0_WIDTH                  2
+#define D0F0xBC_xE010416C_MemClkVid7_1_0_MASK                   0xc0000000
+
+/// D0F0xBC_xE010416C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MemClkVid3_7_2:6 ; ///<
+    UINT32                                           MemClkVid4_7_0:8 ; ///<
+    UINT32                                           MemClkVid5_7_0:8 ; ///<
+    UINT32                                           MemClkVid6_7_0:8 ; ///<
+    UINT32                                           MemClkVid7_1_0:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010416C_STRUCT;
+
+// **** D0F0xBC_xE0104170 Register Definition ****
+// Address
+#define D0F0xBC_xE0104170_ADDRESS                               0xe0104170
+
+// Type
+#define D0F0xBC_xE0104170_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0104170_MemClkVid7_7_2_OFFSET                 0
+#define D0F0xBC_xE0104170_MemClkVid7_7_2_WIDTH                  6
+#define D0F0xBC_xE0104170_MemClkVid7_7_2_MASK                   0x3f
+#define D0F0xBC_xE0104170_MemClkVid8_7_0_OFFSET                 6
+#define D0F0xBC_xE0104170_MemClkVid8_7_0_WIDTH                  8
+#define D0F0xBC_xE0104170_MemClkVid8_7_0_MASK                   0x3fc0
+#define D0F0xBC_xE0104170_AmbientTempBase_7_0_OFFSET            14
+#define D0F0xBC_xE0104170_AmbientTempBase_7_0_WIDTH             8
+#define D0F0xBC_xE0104170_AmbientTempBase_7_0_MASK              0x3fc000
+#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_OFFSET                22
+#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_WIDTH                 10
+#define D0F0xBC_xE0104170_SMU_SPARE31_9_0_MASK                  0xffc00000
+
+/// D0F0xBC_xE0104170
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           MemClkVid7_7_2:6 ; ///<
+    UINT32                                           MemClkVid8_7_0:8 ; ///<
+    UINT32                                      AmbientTempBase_7_0:8 ; ///<
+    UINT32                                          SMU_SPARE31_9_0:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104170_STRUCT;
+
+// **** D0F0xBC_xE0300000 Register Definition ****
+// Address
+#define D0F0xBC_xE0300000_ADDRESS                               0xe0300000
+
+// Type
+#define D0F0xBC_xE0300000_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300000_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300000_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300000_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300000_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300000_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300000_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300000_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300000_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300000_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300000_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300000_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300000_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300000_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300000_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300000_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300000_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300000_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300000_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300000_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300000_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300000_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300000_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300000_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300000_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300000_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300000_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300000_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300000_STRUCT;
+
+// **** D0F0xBC_xE0300004 Register Definition ****
+// Address
+#define D0F0xBC_xE0300004_ADDRESS                               0xe0300004
+
+// Type
+#define D0F0xBC_xE0300004_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300004_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300004_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300004_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300004
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300004_STRUCT;
+
+// **** D0F0xBC_xE0300008 Register Definition ****
+// Address
+#define D0F0xBC_xE0300008_ADDRESS                               0xe0300008
+
+// Type
+#define D0F0xBC_xE0300008_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300008_ReadValue_OFFSET                      0
+#define D0F0xBC_xE0300008_ReadValue_WIDTH                       24
+#define D0F0xBC_xE0300008_ReadValue_MASK                        0xffffff
+#define D0F0xBC_xE0300008_ReadValid_OFFSET                      24
+#define D0F0xBC_xE0300008_ReadValid_WIDTH                       1
+#define D0F0xBC_xE0300008_ReadValid_MASK                        0x1000000
+#define D0F0xBC_xE0300008_Reserved_31_25_OFFSET                 25
+#define D0F0xBC_xE0300008_Reserved_31_25_WIDTH                  7
+#define D0F0xBC_xE0300008_Reserved_31_25_MASK                   0xfe000000
+
+/// D0F0xBC_xE0300008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ReadValue:24; ///<
+    UINT32                                                ReadValid:1 ; ///<
+    UINT32                                           Reserved_31_25:7 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300008_STRUCT;
+
+// **** D0F0xBC_xE030000C Register Definition ****
+// Address
+#define D0F0xBC_xE030000C_ADDRESS                               0xe030000c
+
+// Type
+#define D0F0xBC_xE030000C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030000C_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE030000C_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE030000C_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE030000C_PowerDown_OFFSET                      8
+#define D0F0xBC_xE030000C_PowerDown_WIDTH                       1
+#define D0F0xBC_xE030000C_PowerDown_MASK                        0x100
+#define D0F0xBC_xE030000C_PowerUp_OFFSET                        9
+#define D0F0xBC_xE030000C_PowerUp_WIDTH                         1
+#define D0F0xBC_xE030000C_PowerUp_MASK                          0x200
+#define D0F0xBC_xE030000C_P1Select_OFFSET                       10
+#define D0F0xBC_xE030000C_P1Select_WIDTH                        1
+#define D0F0xBC_xE030000C_P1Select_MASK                         0x400
+#define D0F0xBC_xE030000C_P2Select_OFFSET                       11
+#define D0F0xBC_xE030000C_P2Select_WIDTH                        1
+#define D0F0xBC_xE030000C_P2Select_MASK                         0x800
+#define D0F0xBC_xE030000C_WriteOp_OFFSET                        12
+#define D0F0xBC_xE030000C_WriteOp_WIDTH                         1
+#define D0F0xBC_xE030000C_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE030000C_ReadOp_OFFSET                         13
+#define D0F0xBC_xE030000C_ReadOp_WIDTH                          1
+#define D0F0xBC_xE030000C_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE030000C_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE030000C_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE030000C_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE030000C_RegAddr_OFFSET                        28
+#define D0F0xBC_xE030000C_RegAddr_WIDTH                         4
+#define D0F0xBC_xE030000C_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE030000C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030000C_STRUCT;
+
+// **** D0F0xBC_xE0300010 Register Definition ****
+// Address
+#define D0F0xBC_xE0300010_ADDRESS                               0xe0300010
+
+// Type
+#define D0F0xBC_xE0300010_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300010_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300010_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300010_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300010_STRUCT;
+
+// **** D0F0xBC_xE0300018 Register Definition ****
+// Address
+#define D0F0xBC_xE0300018_ADDRESS                               0xe0300018
+
+// Type
+#define D0F0xBC_xE0300018_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300018_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300018_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300018_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300018_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300018_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300018_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300018_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300018_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300018_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300018_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300018_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300018_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300018_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300018_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300018_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300018_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300018_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300018_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300018_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300018_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300018_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300018_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300018_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300018_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300018_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300018_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300018_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300018
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300018_STRUCT;
+
+// **** D0F0xBC_xE030001C Register Definition ****
+// Address
+#define D0F0xBC_xE030001C_ADDRESS                               0xe030001c
+
+// Type
+#define D0F0xBC_xE030001C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030001C_Write_value_OFFSET                    0
+#define D0F0xBC_xE030001C_Write_value_WIDTH                     32
+#define D0F0xBC_xE030001C_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE030001C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030001C_STRUCT;
+
+// **** D0F0xBC_xE0300024 Register Definition ****
+// Address
+#define D0F0xBC_xE0300024_ADDRESS                               0xe0300024
+
+// Type
+#define D0F0xBC_xE0300024_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300024_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300024_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300024_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300024_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300024_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300024_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300024_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300024_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300024_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300024_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300024_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300024_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300024_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300024_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300024_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300024_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300024_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300024_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300024_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300024_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300024_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300024_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300024_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300024_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300024_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300024_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300024_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300024_STRUCT;
+
+// **** D0F0xBC_xE0300028 Register Definition ****
+// Address
+#define D0F0xBC_xE0300028_ADDRESS                               0xe0300028
+
+// Type
+#define D0F0xBC_xE0300028_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300028_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300028_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300028_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300028
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300028_STRUCT;
+
+// **** D0F0xBC_xE0300030 Register Definition ****
+// Address
+#define D0F0xBC_xE0300030_ADDRESS                               0xe0300030
+
+// Type
+#define D0F0xBC_xE0300030_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300030_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300030_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300030_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300030_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300030_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300030_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300030_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300030_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300030_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300030_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300030_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300030_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300030_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300030_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300030_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300030_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300030_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300030_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300030_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300030_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300030_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300030_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300030_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300030_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300030_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300030_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300030_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300030
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300030_STRUCT;
+
+// **** D0F0xBC_xE0300034 Register Definition ****
+// Address
+#define D0F0xBC_xE0300034_ADDRESS                               0xe0300034
+
+// Type
+#define D0F0xBC_xE0300034_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300034_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300034_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300034_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300034
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300034_STRUCT;
+
+// **** D0F0xBC_xE030003C Register Definition ****
+// Address
+#define D0F0xBC_xE030003C_ADDRESS                               0xe030003c
+
+// Type
+#define D0F0xBC_xE030003C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030003C_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE030003C_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE030003C_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE030003C_PowerDown_OFFSET                      8
+#define D0F0xBC_xE030003C_PowerDown_WIDTH                       1
+#define D0F0xBC_xE030003C_PowerDown_MASK                        0x100
+#define D0F0xBC_xE030003C_PowerUp_OFFSET                        9
+#define D0F0xBC_xE030003C_PowerUp_WIDTH                         1
+#define D0F0xBC_xE030003C_PowerUp_MASK                          0x200
+#define D0F0xBC_xE030003C_P1Select_OFFSET                       10
+#define D0F0xBC_xE030003C_P1Select_WIDTH                        1
+#define D0F0xBC_xE030003C_P1Select_MASK                         0x400
+#define D0F0xBC_xE030003C_P2Select_OFFSET                       11
+#define D0F0xBC_xE030003C_P2Select_WIDTH                        1
+#define D0F0xBC_xE030003C_P2Select_MASK                         0x800
+#define D0F0xBC_xE030003C_WriteOp_OFFSET                        12
+#define D0F0xBC_xE030003C_WriteOp_WIDTH                         1
+#define D0F0xBC_xE030003C_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE030003C_ReadOp_OFFSET                         13
+#define D0F0xBC_xE030003C_ReadOp_WIDTH                          1
+#define D0F0xBC_xE030003C_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE030003C_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE030003C_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE030003C_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE030003C_RegAddr_OFFSET                        28
+#define D0F0xBC_xE030003C_RegAddr_WIDTH                         4
+#define D0F0xBC_xE030003C_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE030003C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030003C_STRUCT;
+
+// **** D0F0xBC_xE0300040 Register Definition ****
+// Address
+#define D0F0xBC_xE0300040_ADDRESS                               0xe0300040
+
+// Type
+#define D0F0xBC_xE0300040_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300040_Write_value_OFFSET                    0
+#define D0F0xBC_xE0300040_Write_value_WIDTH                     32
+#define D0F0xBC_xE0300040_Write_value_MASK                      0xffffffff
+
+/// D0F0xBC_xE0300040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Write_value:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300040_STRUCT;
+
+// **** D0F0xBC_xE0300054 Register Definition ****
+// Address
+#define D0F0xBC_xE0300054_ADDRESS                               0xe0300054
+
+// Type
+#define D0F0xBC_xE0300054_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300054_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300054_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300054_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300054_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300054_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300054_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300054_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300054_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300054_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300054_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300054_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300054_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300054_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300054_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300054_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300054_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300054_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300054_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300054_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300054_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300054_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300054_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300054_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300054_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300054_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300054_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300054_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300054
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300054_STRUCT;
+
+// **** D0F0xBC_xE0300058 Register Definition ****
+// Address
+#define D0F0xBC_xE0300058_ADDRESS                               0xe0300058
+
+// Type
+#define D0F0xBC_xE0300058_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300058_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300058_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300058_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300058
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300058_STRUCT;
+
+// **** D0F0xBC_xE0300070 Register Definition ****
+// Address
+#define D0F0xBC_xE0300070_ADDRESS                               0xe0300070
+
+// Type
+#define D0F0xBC_xE0300070_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300070_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE0300070_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE0300070_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE0300070_PowerDown_OFFSET                      8
+#define D0F0xBC_xE0300070_PowerDown_WIDTH                       1
+#define D0F0xBC_xE0300070_PowerDown_MASK                        0x100
+#define D0F0xBC_xE0300070_PowerUp_OFFSET                        9
+#define D0F0xBC_xE0300070_PowerUp_WIDTH                         1
+#define D0F0xBC_xE0300070_PowerUp_MASK                          0x200
+#define D0F0xBC_xE0300070_P1Select_OFFSET                       10
+#define D0F0xBC_xE0300070_P1Select_WIDTH                        1
+#define D0F0xBC_xE0300070_P1Select_MASK                         0x400
+#define D0F0xBC_xE0300070_P2Select_OFFSET                       11
+#define D0F0xBC_xE0300070_P2Select_WIDTH                        1
+#define D0F0xBC_xE0300070_P2Select_MASK                         0x800
+#define D0F0xBC_xE0300070_WriteOp_OFFSET                        12
+#define D0F0xBC_xE0300070_WriteOp_WIDTH                         1
+#define D0F0xBC_xE0300070_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE0300070_ReadOp_OFFSET                         13
+#define D0F0xBC_xE0300070_ReadOp_WIDTH                          1
+#define D0F0xBC_xE0300070_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE0300070_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE0300070_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE0300070_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE0300070_RegAddr_OFFSET                        28
+#define D0F0xBC_xE0300070_RegAddr_WIDTH                         4
+#define D0F0xBC_xE0300070_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE0300070
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300070_STRUCT;
+
+// **** D0F0xBC_xE0300074 Register Definition ****
+// Address
+#define D0F0xBC_xE0300074_ADDRESS                               0xe0300074
+
+// Type
+#define D0F0xBC_xE0300074_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300074_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300074_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300074_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300074
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300074_STRUCT;
+
+// **** D0F0xBC_xE030008C Register Definition ****
+// Address
+#define D0F0xBC_xE030008C_ADDRESS                               0xe030008c
+
+// Type
+#define D0F0xBC_xE030008C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030008C_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE030008C_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE030008C_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE030008C_PowerDown_OFFSET                      8
+#define D0F0xBC_xE030008C_PowerDown_WIDTH                       1
+#define D0F0xBC_xE030008C_PowerDown_MASK                        0x100
+#define D0F0xBC_xE030008C_PowerUp_OFFSET                        9
+#define D0F0xBC_xE030008C_PowerUp_WIDTH                         1
+#define D0F0xBC_xE030008C_PowerUp_MASK                          0x200
+#define D0F0xBC_xE030008C_P1Select_OFFSET                       10
+#define D0F0xBC_xE030008C_P1Select_WIDTH                        1
+#define D0F0xBC_xE030008C_P1Select_MASK                         0x400
+#define D0F0xBC_xE030008C_P2Select_OFFSET                       11
+#define D0F0xBC_xE030008C_P2Select_WIDTH                        1
+#define D0F0xBC_xE030008C_P2Select_MASK                         0x800
+#define D0F0xBC_xE030008C_WriteOp_OFFSET                        12
+#define D0F0xBC_xE030008C_WriteOp_WIDTH                         1
+#define D0F0xBC_xE030008C_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE030008C_ReadOp_OFFSET                         13
+#define D0F0xBC_xE030008C_ReadOp_WIDTH                          1
+#define D0F0xBC_xE030008C_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE030008C_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE030008C_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE030008C_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE030008C_RegAddr_OFFSET                        28
+#define D0F0xBC_xE030008C_RegAddr_WIDTH                         4
+#define D0F0xBC_xE030008C_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE030008C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030008C_STRUCT;
+
+// **** D0F0xBC_xE0300090 Register Definition ****
+// Address
+#define D0F0xBC_xE0300090_ADDRESS                               0xe0300090
+
+// Type
+#define D0F0xBC_xE0300090_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300090_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300090_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300090_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300090
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300090_STRUCT;
+
+// **** D0F0xBC_xE03000A8 Register Definition ****
+// Address
+#define D0F0xBC_xE03000A8_ADDRESS                               0xe03000a8
+
+// Type
+#define D0F0xBC_xE03000A8_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000A8_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000A8_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000A8_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000A8_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000A8_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000A8_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000A8_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000A8_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000A8_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000A8_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000A8_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000A8_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000A8_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000A8_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000A8_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000A8_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000A8_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000A8_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000A8_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000A8_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000A8_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000A8_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000A8_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000A8_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000A8_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000A8_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000A8_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000A8_STRUCT;
+
+// **** D0F0xBC_xE03000AC Register Definition ****
+// Address
+#define D0F0xBC_xE03000AC_ADDRESS                               0xe03000ac
+
+// Type
+#define D0F0xBC_xE03000AC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000AC_WriteValue_OFFSET                     0
+#define D0F0xBC_xE03000AC_WriteValue_WIDTH                      32
+#define D0F0xBC_xE03000AC_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE03000AC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000AC_STRUCT;
+
+// **** D0F0xBC_xE03000C4 Register Definition ****
+// Address
+#define D0F0xBC_xE03000C4_ADDRESS                               0xe03000c4
+
+// Type
+#define D0F0xBC_xE03000C4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000C4_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000C4_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000C4_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000C4_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000C4_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000C4_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000C4_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000C4_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000C4_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000C4_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000C4_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000C4_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000C4_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000C4_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000C4_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000C4_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000C4_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000C4_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000C4_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000C4_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000C4_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000C4_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000C4_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000C4_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000C4_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000C4_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000C4_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000C4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000C4_STRUCT;
+
+// **** D0F0xBC_xE03000C8 Register Definition ****
+// Address
+#define D0F0xBC_xE03000C8_ADDRESS                               0xe03000c8
+
+// Type
+#define D0F0xBC_xE03000C8_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000C8_WriteValue_OFFSET                     0
+#define D0F0xBC_xE03000C8_WriteValue_WIDTH                      32
+#define D0F0xBC_xE03000C8_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE03000C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000C8_STRUCT;
+
+// **** D0F0xBC_xE03000E0 Register Definition ****
+// Address
+#define D0F0xBC_xE03000E0_ADDRESS                               0xe03000e0
+
+// Type
+#define D0F0xBC_xE03000E0_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000E0_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000E0_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000E0_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000E0_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000E0_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000E0_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000E0_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000E0_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000E0_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000E0_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000E0_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000E0_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000E0_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000E0_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000E0_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000E0_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000E0_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000E0_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000E0_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000E0_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000E0_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000E0_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000E0_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000E0_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000E0_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000E0_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000E0_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000E0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000E0_STRUCT;
+
+// **** D0F0xBC_xE03000E4 Register Definition ****
+// Address
+#define D0F0xBC_xE03000E4_ADDRESS                               0xe03000e4
+
+// Type
+#define D0F0xBC_xE03000E4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000E4_WriteValue_OFFSET                     0
+#define D0F0xBC_xE03000E4_WriteValue_WIDTH                      32
+#define D0F0xBC_xE03000E4_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE03000E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000E4_STRUCT;
+
+// **** D0F0xBC_xE03000FC Register Definition ****
+// Address
+#define D0F0xBC_xE03000FC_ADDRESS                               0xe03000fc
+
+// Type
+#define D0F0xBC_xE03000FC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03000FC_FsmAddr_OFFSET                        0
+#define D0F0xBC_xE03000FC_FsmAddr_WIDTH                         8
+#define D0F0xBC_xE03000FC_FsmAddr_MASK                          0xff
+#define D0F0xBC_xE03000FC_PowerDown_OFFSET                      8
+#define D0F0xBC_xE03000FC_PowerDown_WIDTH                       1
+#define D0F0xBC_xE03000FC_PowerDown_MASK                        0x100
+#define D0F0xBC_xE03000FC_PowerUp_OFFSET                        9
+#define D0F0xBC_xE03000FC_PowerUp_WIDTH                         1
+#define D0F0xBC_xE03000FC_PowerUp_MASK                          0x200
+#define D0F0xBC_xE03000FC_P1Select_OFFSET                       10
+#define D0F0xBC_xE03000FC_P1Select_WIDTH                        1
+#define D0F0xBC_xE03000FC_P1Select_MASK                         0x400
+#define D0F0xBC_xE03000FC_P2Select_OFFSET                       11
+#define D0F0xBC_xE03000FC_P2Select_WIDTH                        1
+#define D0F0xBC_xE03000FC_P2Select_MASK                         0x800
+#define D0F0xBC_xE03000FC_WriteOp_OFFSET                        12
+#define D0F0xBC_xE03000FC_WriteOp_WIDTH                         1
+#define D0F0xBC_xE03000FC_WriteOp_MASK                          0x1000
+#define D0F0xBC_xE03000FC_ReadOp_OFFSET                         13
+#define D0F0xBC_xE03000FC_ReadOp_WIDTH                          1
+#define D0F0xBC_xE03000FC_ReadOp_MASK                           0x2000
+#define D0F0xBC_xE03000FC_Reserved_27_14_OFFSET                 14
+#define D0F0xBC_xE03000FC_Reserved_27_14_WIDTH                  14
+#define D0F0xBC_xE03000FC_Reserved_27_14_MASK                   0xfffc000
+#define D0F0xBC_xE03000FC_RegAddr_OFFSET                        28
+#define D0F0xBC_xE03000FC_RegAddr_WIDTH                         4
+#define D0F0xBC_xE03000FC_RegAddr_MASK                          0xf0000000
+
+/// D0F0xBC_xE03000FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FsmAddr:8 ; ///<
+    UINT32                                                PowerDown:1 ; ///<
+    UINT32                                                  PowerUp:1 ; ///<
+    UINT32                                                 P1Select:1 ; ///<
+    UINT32                                                 P2Select:1 ; ///<
+    UINT32                                                  WriteOp:1 ; ///<
+    UINT32                                                   ReadOp:1 ; ///<
+    UINT32                                           Reserved_27_14:14; ///<
+    UINT32                                                  RegAddr:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03000FC_STRUCT;
+
+// **** D0F0xBC_xE0300100 Register Definition ****
+// Address
+#define D0F0xBC_xE0300100_ADDRESS                               0xe0300100
+
+// Type
+#define D0F0xBC_xE0300100_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300100_WriteValue_OFFSET                     0
+#define D0F0xBC_xE0300100_WriteValue_WIDTH                      32
+#define D0F0xBC_xE0300100_WriteValue_MASK                       0xffffffff
+
+/// D0F0xBC_xE0300100
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               WriteValue:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300100_STRUCT;
+
+// **** D0F0xBC_xE0300200 Register Definition ****
+// Address
+#define D0F0xBC_xE0300200_ADDRESS                               0xe0300200
+
+// Type
+#define D0F0xBC_xE0300200_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300200_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300200_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300200_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300200_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300200_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300200_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300200_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE0300200_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE0300200_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE0300200
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300200_STRUCT;
+
+
+// Type
+#define D0F0xBC_xE0300208_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300208_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300208_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300208_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300208_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300208_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300208_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300208_Reserved_12_11_OFFSET                 11
+#define D0F0xBC_xE0300208_Reserved_12_11_WIDTH                  2
+#define D0F0xBC_xE0300208_Reserved_12_11_MASK                   0x1800
+#define D0F0xBC_xE0300208_P1PsoDaug_OFFSET                      13
+#define D0F0xBC_xE0300208_P1PsoDaug_WIDTH                       1
+#define D0F0xBC_xE0300208_P1PsoDaug_MASK                        0x2000
+#define D0F0xBC_xE0300208_Reserved_31_14_OFFSET                 14
+#define D0F0xBC_xE0300208_Reserved_31_14_WIDTH                  18
+#define D0F0xBC_xE0300208_Reserved_31_14_MASK                   0xffffc000
+
+/// D0F0xBC_xE0300208
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                :1 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300208_STRUCT;
+
+// **** D0F0xBC_xE030020C Register Definition ****
+// Address
+#define D0F0xBC_xE030020C_ADDRESS                               0xe030020c
+
+// Type
+#define D0F0xBC_xE030020C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE030020C_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE030020C_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE030020C_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE030020C_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE030020C_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE030020C_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE030020C_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE030020C_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE030020C_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE030020C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE030020C_STRUCT;
+
+// **** D0F0xBC_xE0300210 Register Definition ****
+// Address
+#define D0F0xBC_xE0300210_ADDRESS                               0xe0300210
+
+// Type
+#define D0F0xBC_xE0300210_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300210_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300210_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300210_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300210_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300210_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300210_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300210_Reserved_12_11_OFFSET                 11
+#define D0F0xBC_xE0300210_Reserved_12_11_WIDTH                  2
+#define D0F0xBC_xE0300210_Reserved_12_11_MASK                   0x1800
+#define D0F0xBC_xE0300210_Reserved_31_14_OFFSET                 14
+#define D0F0xBC_xE0300210_Reserved_31_14_WIDTH                  18
+#define D0F0xBC_xE0300210_Reserved_31_14_MASK                   0xffffc000
+
+/// D0F0xBC_xE0300210
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                :1 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300210_STRUCT;
+
+// **** D0F0xBC_xE0300218 Register Definition ****
+// Address
+#define D0F0xBC_xE0300218_ADDRESS                               0xe0300218
+
+// Type
+#define D0F0xBC_xE0300218_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300218_Reserved_9_0_OFFSET                   0
+#define D0F0xBC_xE0300218_Reserved_9_0_WIDTH                    10
+#define D0F0xBC_xE0300218_Reserved_9_0_MASK                     0x3ff
+#define D0F0xBC_xE0300218_P1IsoN_OFFSET                         10
+#define D0F0xBC_xE0300218_P1IsoN_WIDTH                          1
+#define D0F0xBC_xE0300218_P1IsoN_MASK                           0x400
+#define D0F0xBC_xE0300218_Reserved_31_11_OFFSET                 11
+#define D0F0xBC_xE0300218_Reserved_31_11_WIDTH                  21
+#define D0F0xBC_xE0300218_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xBC_xE0300218
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_9_0:10; ///<
+    UINT32                                                   P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300218_STRUCT;
+
+// **** D0F0xBC_xE03002DC Register Definition ****
+// Address
+#define D0F0xBC_xE03002DC_ADDRESS                               0xe03002dc
+
+// Type
+#define D0F0xBC_xE03002DC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET              0
+#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_WIDTH               1
+#define D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_MASK                0x1
+#define D0F0xBC_xE03002DC_Reserved_OFFSET                       1
+#define D0F0xBC_xE03002DC_Reserved_WIDTH                        31
+#define D0F0xBC_xE03002DC_Reserved_MASK                         0xfffffffe
+
+/// D0F0xBC_xE03002DC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DC2_PGFSM_CONTROL:1 ; ///<
+    UINT32                                                 Reserved:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002DC_STRUCT;
+
+// **** D0F0xBC_xE03002E4 Register Definition ****
+// Address
+#define D0F0xBC_xE03002E4_ADDRESS                               0xe03002e4
+
+// Type
+#define D0F0xBC_xE03002E4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_OFFSET                  0
+#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuCb0PsoDaug_MASK                    0x1
+#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_OFFSET                  1
+#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuCb1PsoDaug_MASK                    0x2
+#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_OFFSET                  2
+#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuDb0PsoDaug_MASK                    0x4
+#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_OFFSET                  3
+#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuDb1PsoDaug_MASK                    0x8
+#define D0F0xBC_xE03002E4_SmuPaPsoDaug_OFFSET                   4
+#define D0F0xBC_xE03002E4_SmuPaPsoDaug_WIDTH                    1
+#define D0F0xBC_xE03002E4_SmuPaPsoDaug_MASK                     0x10
+#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_OFFSET                  5
+#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSpmPsoDaug_MASK                    0x20
+#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_OFFSET                  6
+#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSpsPsoDaug_MASK                    0x40
+#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_OFFSET                  7
+#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSqbPsoDaug_MASK                    0x80
+#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_OFFSET                  8
+#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSxmPsoDaug_MASK                    0x100
+#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_OFFSET                 9
+#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_WIDTH                  1
+#define D0F0xBC_xE03002E4_SmuSxs0PsoDaug_MASK                   0x200
+#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_OFFSET                 10
+#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_WIDTH                  1
+#define D0F0xBC_xE03002E4_SmuSxs1PsoDaug_MASK                   0x400
+#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_OFFSET                  11
+#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuXbrPsoDaug_MASK                    0x800
+#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_OFFSET                  12
+#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuGdsPsoDaug_MASK                    0x1000
+#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_OFFSET                  13
+#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuVgtPsoDaug_MASK                    0x2000
+#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_OFFSET                  14
+#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSqaPsoDaug_MASK                    0x4000
+#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_OFFSET                  15
+#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_WIDTH                   1
+#define D0F0xBC_xE03002E4_SmuSqcPsoDaug_MASK                    0x8000
+#define D0F0xBC_xE03002E4_SmuTcPsoDaug_OFFSET                   16
+#define D0F0xBC_xE03002E4_SmuTcPsoDaug_WIDTH                    1
+#define D0F0xBC_xE03002E4_SmuTcPsoDaug_MASK                     0x10000
+#define D0F0xBC_xE03002E4_SmuScPsoDaug_OFFSET                   17
+#define D0F0xBC_xE03002E4_SmuScPsoDaug_WIDTH                    1
+#define D0F0xBC_xE03002E4_SmuScPsoDaug_MASK                     0x20000
+#define D0F0xBC_xE03002E4_Reserved_31_18_OFFSET                 18
+#define D0F0xBC_xE03002E4_Reserved_31_18_WIDTH                  14
+#define D0F0xBC_xE03002E4_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xBC_xE03002E4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            SmuCb0PsoDaug:1 ; ///<
+    UINT32                                            SmuCb1PsoDaug:1 ; ///<
+    UINT32                                            SmuDb0PsoDaug:1 ; ///<
+    UINT32                                            SmuDb1PsoDaug:1 ; ///<
+    UINT32                                             SmuPaPsoDaug:1 ; ///<
+    UINT32                                            SmuSpmPsoDaug:1 ; ///<
+    UINT32                                            SmuSpsPsoDaug:1 ; ///<
+    UINT32                                            SmuSqbPsoDaug:1 ; ///<
+    UINT32                                            SmuSxmPsoDaug:1 ; ///<
+    UINT32                                           SmuSxs0PsoDaug:1 ; ///<
+    UINT32                                           SmuSxs1PsoDaug:1 ; ///<
+    UINT32                                            SmuXbrPsoDaug:1 ; ///<
+    UINT32                                            SmuGdsPsoDaug:1 ; ///<
+    UINT32                                            SmuVgtPsoDaug:1 ; ///<
+    UINT32                                            SmuSqaPsoDaug:1 ; ///<
+    UINT32                                            SmuSqcPsoDaug:1 ; ///<
+    UINT32                                             SmuTcPsoDaug:1 ; ///<
+    UINT32                                             SmuScPsoDaug:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002E4_STRUCT;
+
+// **** D0F0xBC_xE03002F0 Register Definition ****
+// Address
+#define D0F0xBC_xE03002F0_ADDRESS                               0xe03002f0
+
+// Type
+#define D0F0xBC_xE03002F0_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_OFFSET                 0
+#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd0P1IsoN_MASK                   0x1
+#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_OFFSET                 1
+#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp000P1IsoN_MASK                   0x2
+#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_OFFSET                 2
+#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp002P1IsoN_MASK                   0x4
+#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_OFFSET                  3
+#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds0P1IsoN_MASK                    0x8
+#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_OFFSET                  4
+#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp0P1IsoN_MASK                    0x10
+#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_OFFSET                 5
+#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd1P1IsoN_MASK                   0x20
+#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_OFFSET                 6
+#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp010P1IsoN_MASK                   0x40
+#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_OFFSET                 7
+#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp012P1IsoN_MASK                   0x80
+#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_OFFSET                  8
+#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds1P1IsoN_MASK                    0x100
+#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_OFFSET                  9
+#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp1P1IsoN_MASK                    0x200
+#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_OFFSET                 10
+#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd2P1IsoN_MASK                   0x400
+#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_OFFSET                 11
+#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp020P1IsoN_MASK                   0x800
+#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_OFFSET                 12
+#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp022P1IsoN_MASK                   0x1000
+#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_OFFSET                  13
+#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds2P1IsoN_MASK                    0x2000
+#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_OFFSET                  14
+#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp2P1IsoN_MASK                    0x4000
+#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_OFFSET                 15
+#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd3P1IsoN_MASK                   0x8000
+#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_OFFSET                 16
+#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp030P1IsoN_MASK                   0x10000
+#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_OFFSET                 17
+#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp032P1IsoN_MASK                   0x20000
+#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_OFFSET                  18
+#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds3P1IsoN_MASK                    0x40000
+#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_OFFSET                  19
+#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp3P1IsoN_MASK                    0x80000
+#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_OFFSET                 20
+#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd4P1IsoN_MASK                   0x100000
+#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_OFFSET                 21
+#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp040P1IsoN_MASK                   0x200000
+#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_OFFSET                 22
+#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp042P1IsoN_MASK                   0x400000
+#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_OFFSET                  23
+#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds4P1IsoN_MASK                    0x800000
+#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_OFFSET                  24
+#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp4P1IsoN_MASK                    0x1000000
+#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_OFFSET                 25
+#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuTatd5P1IsoN_MASK                   0x2000000
+#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_OFFSET                 26
+#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp050P1IsoN_MASK                   0x4000000
+#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_OFFSET                 27
+#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F0_SmuSp052P1IsoN_MASK                   0x8000000
+#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_OFFSET                  28
+#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuLds5P1IsoN_MASK                    0x10000000
+#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_OFFSET                  29
+#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F0_SmuTcp5P1IsoN_MASK                    0x20000000
+#define D0F0xBC_xE03002F0_Reserved_31_30_OFFSET                 30
+#define D0F0xBC_xE03002F0_Reserved_31_30_WIDTH                  2
+#define D0F0xBC_xE03002F0_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xBC_xE03002F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SmuTatd0P1IsoN:1 ; ///<
+    UINT32                                           SmuSp000P1IsoN:1 ; ///<
+    UINT32                                           SmuSp002P1IsoN:1 ; ///<
+    UINT32                                            SmuLds0P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp0P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd1P1IsoN:1 ; ///<
+    UINT32                                           SmuSp010P1IsoN:1 ; ///<
+    UINT32                                           SmuSp012P1IsoN:1 ; ///<
+    UINT32                                            SmuLds1P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp1P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd2P1IsoN:1 ; ///<
+    UINT32                                           SmuSp020P1IsoN:1 ; ///<
+    UINT32                                           SmuSp022P1IsoN:1 ; ///<
+    UINT32                                            SmuLds2P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp2P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd3P1IsoN:1 ; ///<
+    UINT32                                           SmuSp030P1IsoN:1 ; ///<
+    UINT32                                           SmuSp032P1IsoN:1 ; ///<
+    UINT32                                            SmuLds3P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp3P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd4P1IsoN:1 ; ///<
+    UINT32                                           SmuSp040P1IsoN:1 ; ///<
+    UINT32                                           SmuSp042P1IsoN:1 ; ///<
+    UINT32                                            SmuLds4P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp4P1IsoN:1 ; ///<
+    UINT32                                           SmuTatd5P1IsoN:1 ; ///<
+    UINT32                                           SmuSp050P1IsoN:1 ; ///<
+    UINT32                                           SmuSp052P1IsoN:1 ; ///<
+    UINT32                                            SmuLds5P1IsoN:1 ; ///<
+    UINT32                                            SmuTcp5P1IsoN:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002F0_STRUCT;
+
+// **** D0F0xBC_xE03002F4 Register Definition ****
+// Address
+#define D0F0xBC_xE03002F4_ADDRESS                               0xe03002f4
+
+// Type
+#define D0F0xBC_xE03002F4_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002F4_SmuCb0IsoN_OFFSET                     0
+#define D0F0xBC_xE03002F4_SmuCb0IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuCb0IsoN_MASK                       0x1
+#define D0F0xBC_xE03002F4_SmuCb1IsoN_OFFSET                     1
+#define D0F0xBC_xE03002F4_SmuCb1IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuCb1IsoN_MASK                       0x2
+#define D0F0xBC_xE03002F4_SmuDb0IsoN_OFFSET                     2
+#define D0F0xBC_xE03002F4_SmuDb0IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuDb0IsoN_MASK                       0x4
+#define D0F0xBC_xE03002F4_SmuDb1IsoN_OFFSET                     3
+#define D0F0xBC_xE03002F4_SmuDb1IsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuDb1IsoN_MASK                       0x8
+#define D0F0xBC_xE03002F4_SmuPaIsoN_OFFSET                      4
+#define D0F0xBC_xE03002F4_SmuPaIsoN_WIDTH                       1
+#define D0F0xBC_xE03002F4_SmuPaIsoN_MASK                        0x10
+#define D0F0xBC_xE03002F4_SmuSpmIsoN_OFFSET                     5
+#define D0F0xBC_xE03002F4_SmuSpmIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSpmIsoN_MASK                       0x20
+#define D0F0xBC_xE03002F4_SmuSpsIsoN_OFFSET                     6
+#define D0F0xBC_xE03002F4_SmuSpsIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSpsIsoN_MASK                       0x40
+#define D0F0xBC_xE03002F4_SmuSqbIsoN_OFFSET                     7
+#define D0F0xBC_xE03002F4_SmuSqbIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSqbIsoN_MASK                       0x80
+#define D0F0xBC_xE03002F4_SmuSxmIsoN_OFFSET                     8
+#define D0F0xBC_xE03002F4_SmuSxmIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSxmIsoN_MASK                       0x100
+#define D0F0xBC_xE03002F4_SmuSxs0IsoN_OFFSET                    9
+#define D0F0xBC_xE03002F4_SmuSxs0IsoN_WIDTH                     1
+#define D0F0xBC_xE03002F4_SmuSxs0IsoN_MASK                      0x200
+#define D0F0xBC_xE03002F4_SmuSxs1IsoN_OFFSET                    10
+#define D0F0xBC_xE03002F4_SmuSxs1IsoN_WIDTH                     1
+#define D0F0xBC_xE03002F4_SmuSxs1IsoN_MASK                      0x400
+#define D0F0xBC_xE03002F4_SmuXbrIsoN_OFFSET                     11
+#define D0F0xBC_xE03002F4_SmuXbrIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuXbrIsoN_MASK                       0x800
+#define D0F0xBC_xE03002F4_SmuGdsIsoN_OFFSET                     12
+#define D0F0xBC_xE03002F4_SmuGdsIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuGdsIsoN_MASK                       0x1000
+#define D0F0xBC_xE03002F4_SmuVgtIsoN_OFFSET                     13
+#define D0F0xBC_xE03002F4_SmuVgtIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuVgtIsoN_MASK                       0x2000
+#define D0F0xBC_xE03002F4_SmuSqaIsoN_OFFSET                     14
+#define D0F0xBC_xE03002F4_SmuSqaIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSqaIsoN_MASK                       0x4000
+#define D0F0xBC_xE03002F4_SmuSqcIsoN_OFFSET                     15
+#define D0F0xBC_xE03002F4_SmuSqcIsoN_WIDTH                      1
+#define D0F0xBC_xE03002F4_SmuSqcIsoN_MASK                       0x8000
+#define D0F0xBC_xE03002F4_SmuTcIsoN_OFFSET                      16
+#define D0F0xBC_xE03002F4_SmuTcIsoN_WIDTH                       1
+#define D0F0xBC_xE03002F4_SmuTcIsoN_MASK                        0x10000
+#define D0F0xBC_xE03002F4_SmuScIsoN_OFFSET                      17
+#define D0F0xBC_xE03002F4_SmuScIsoN_WIDTH                       1
+#define D0F0xBC_xE03002F4_SmuScIsoN_MASK                        0x20000
+#define D0F0xBC_xE03002F4_Reserved_31_18_OFFSET                 18
+#define D0F0xBC_xE03002F4_Reserved_31_18_WIDTH                  14
+#define D0F0xBC_xE03002F4_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xBC_xE03002F4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               SmuCb0IsoN:1 ; ///<
+    UINT32                                               SmuCb1IsoN:1 ; ///<
+    UINT32                                               SmuDb0IsoN:1 ; ///<
+    UINT32                                               SmuDb1IsoN:1 ; ///<
+    UINT32                                                SmuPaIsoN:1 ; ///<
+    UINT32                                               SmuSpmIsoN:1 ; ///<
+    UINT32                                               SmuSpsIsoN:1 ; ///<
+    UINT32                                               SmuSqbIsoN:1 ; ///<
+    UINT32                                               SmuSxmIsoN:1 ; ///<
+    UINT32                                              SmuSxs0IsoN:1 ; ///<
+    UINT32                                              SmuSxs1IsoN:1 ; ///<
+    UINT32                                               SmuXbrIsoN:1 ; ///<
+    UINT32                                               SmuGdsIsoN:1 ; ///<
+    UINT32                                               SmuVgtIsoN:1 ; ///<
+    UINT32                                               SmuSqaIsoN:1 ; ///<
+    UINT32                                               SmuSqcIsoN:1 ; ///<
+    UINT32                                                SmuTcIsoN:1 ; ///<
+    UINT32                                                SmuScIsoN:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002F4_STRUCT;
+
+// **** D0F0xBC_xE03002F8 Register Definition ****
+// Address
+#define D0F0xBC_xE03002F8_ADDRESS                               0xe03002f8
+
+// Type
+#define D0F0xBC_xE03002F8_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_OFFSET                 0
+#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd0P2IsoN_MASK                   0x1
+#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_OFFSET                 1
+#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp000P2IsoN_MASK                   0x2
+#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_OFFSET                 2
+#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp002P2IsoN_MASK                   0x4
+#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_OFFSET                  3
+#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds0P2IsoN_MASK                    0x8
+#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_OFFSET                  4
+#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp0P2IsoN_MASK                    0x10
+#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_OFFSET                 5
+#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd1P2IsoN_MASK                   0x20
+#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_OFFSET                 6
+#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp010P2IsoN_MASK                   0x40
+#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_OFFSET                 7
+#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp012P2IsoN_MASK                   0x80
+#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_OFFSET                  8
+#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds1P2IsoN_MASK                    0x100
+#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_OFFSET                  9
+#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp1P2IsoN_MASK                    0x200
+#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_OFFSET                 10
+#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd2P2IsoN_MASK                   0x400
+#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_OFFSET                 11
+#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp020P2IsoN_MASK                   0x800
+#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_OFFSET                 12
+#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp022P2IsoN_MASK                   0x1000
+#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_OFFSET                  13
+#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds2P2IsoN_MASK                    0x2000
+#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_OFFSET                  14
+#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp2P2IsoN_MASK                    0x4000
+#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_OFFSET                 15
+#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd3P2IsoN_MASK                   0x8000
+#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_OFFSET                 16
+#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp030P2IsoN_MASK                   0x10000
+#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_OFFSET                 17
+#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp032P2IsoN_MASK                   0x20000
+#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_OFFSET                  18
+#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds3P2IsoN_MASK                    0x40000
+#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_OFFSET                  19
+#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp3P2IsoN_MASK                    0x80000
+#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_OFFSET                 20
+#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd4P2IsoN_MASK                   0x100000
+#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_OFFSET                 21
+#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp040P2IsoN_MASK                   0x200000
+#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_OFFSET                 22
+#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp042P2IsoN_MASK                   0x400000
+#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_OFFSET                  23
+#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds4P2IsoN_MASK                    0x800000
+#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_OFFSET                  24
+#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp4P2IsoN_MASK                    0x1000000
+#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_OFFSET                 25
+#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuTatd5P2IsoN_MASK                   0x2000000
+#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_OFFSET                 26
+#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp050P2IsoN_MASK                   0x4000000
+#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_OFFSET                 27
+#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_WIDTH                  1
+#define D0F0xBC_xE03002F8_SmuSp052P2IsoN_MASK                   0x8000000
+#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_OFFSET                  28
+#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuLds5P2IsoN_MASK                    0x10000000
+#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_OFFSET                  29
+#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_WIDTH                   1
+#define D0F0xBC_xE03002F8_SmuTcp5P2IsoN_MASK                    0x20000000
+#define D0F0xBC_xE03002F8_Reserved_31_30_OFFSET                 30
+#define D0F0xBC_xE03002F8_Reserved_31_30_WIDTH                  2
+#define D0F0xBC_xE03002F8_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xBC_xE03002F8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SmuTatd0P2IsoN:1 ; ///<
+    UINT32                                           SmuSp000P2IsoN:1 ; ///<
+    UINT32                                           SmuSp002P2IsoN:1 ; ///<
+    UINT32                                            SmuLds0P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp0P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd1P2IsoN:1 ; ///<
+    UINT32                                           SmuSp010P2IsoN:1 ; ///<
+    UINT32                                           SmuSp012P2IsoN:1 ; ///<
+    UINT32                                            SmuLds1P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp1P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd2P2IsoN:1 ; ///<
+    UINT32                                           SmuSp020P2IsoN:1 ; ///<
+    UINT32                                           SmuSp022P2IsoN:1 ; ///<
+    UINT32                                            SmuLds2P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp2P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd3P2IsoN:1 ; ///<
+    UINT32                                           SmuSp030P2IsoN:1 ; ///<
+    UINT32                                           SmuSp032P2IsoN:1 ; ///<
+    UINT32                                            SmuLds3P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp3P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd4P2IsoN:1 ; ///<
+    UINT32                                           SmuSp040P2IsoN:1 ; ///<
+    UINT32                                           SmuSp042P2IsoN:1 ; ///<
+    UINT32                                            SmuLds4P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp4P2IsoN:1 ; ///<
+    UINT32                                           SmuTatd5P2IsoN:1 ; ///<
+    UINT32                                           SmuSp050P2IsoN:1 ; ///<
+    UINT32                                           SmuSp052P2IsoN:1 ; ///<
+    UINT32                                            SmuLds5P2IsoN:1 ; ///<
+    UINT32                                            SmuTcp5P2IsoN:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002F8_STRUCT;
+
+// **** D0F0xBC_xE03002FC Register Definition ****
+// Address
+#define D0F0xBC_xE03002FC_ADDRESS                               0xe03002fc
+
+// Type
+#define D0F0xBC_xE03002FC_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_OFFSET              0
+#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd0P2PsoDaug_MASK                0x1
+#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_OFFSET              1
+#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp000P2PsoDaug_MASK                0x2
+#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_OFFSET              2
+#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp002P2PsoDaug_MASK                0x4
+#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_OFFSET               3
+#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds0P2PsoDaug_MASK                 0x8
+#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_OFFSET               4
+#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp0P2PsoDaug_MASK                 0x10
+#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_OFFSET              5
+#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd1P2PsoDaug_MASK                0x20
+#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_OFFSET              6
+#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp010P2PsoDaug_MASK                0x40
+#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_OFFSET              7
+#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp012P2PsoDaug_MASK                0x80
+#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_OFFSET               8
+#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds1P2PsoDaug_MASK                 0x100
+#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_OFFSET               9
+#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp1P2PsoDaug_MASK                 0x200
+#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_OFFSET              10
+#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd2P2PsoDaug_MASK                0x400
+#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_OFFSET              11
+#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp020P2PsoDaug_MASK                0x800
+#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_OFFSET              12
+#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp022P2PsoDaug_MASK                0x1000
+#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_OFFSET               13
+#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds2P2PsoDaug_MASK                 0x2000
+#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_OFFSET               14
+#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp2P2PsoDaug_MASK                 0x4000
+#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_OFFSET              15
+#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd3P2PsoDaug_MASK                0x8000
+#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_OFFSET              16
+#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp030P2PsoDaug_MASK                0x10000
+#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_OFFSET              17
+#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp032P2PsoDaug_MASK                0x20000
+#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_OFFSET               18
+#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds3P2PsoDaug_MASK                 0x40000
+#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_OFFSET               19
+#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp3P2PsoDaug_MASK                 0x80000
+#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_OFFSET              20
+#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd4P2PsoDaug_MASK                0x100000
+#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_OFFSET              21
+#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp040P2PsoDaug_MASK                0x200000
+#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_OFFSET              22
+#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp042P2PsoDaug_MASK                0x400000
+#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_OFFSET               23
+#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds4P2PsoDaug_MASK                 0x800000
+#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_OFFSET               24
+#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp4P2PsoDaug_MASK                 0x1000000
+#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_OFFSET              25
+#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuTatd5P2PsoDaug_MASK                0x2000000
+#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_OFFSET              26
+#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp050P2PsoDaug_MASK                0x4000000
+#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_OFFSET              27
+#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_WIDTH               1
+#define D0F0xBC_xE03002FC_SmuSp052P2PsoDaug_MASK                0x8000000
+#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_OFFSET               28
+#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuLds5P2PsoDaug_MASK                 0x10000000
+#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_OFFSET               29
+#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_WIDTH                1
+#define D0F0xBC_xE03002FC_SmuTcp5P2PsoDaug_MASK                 0x20000000
+#define D0F0xBC_xE03002FC_Reserved_31_30_OFFSET                 30
+#define D0F0xBC_xE03002FC_Reserved_31_30_WIDTH                  2
+#define D0F0xBC_xE03002FC_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xBC_xE03002FC
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SmuTatd0P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp000P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp002P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds0P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp0P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd1P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp010P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp012P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds1P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp1P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd2P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp020P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp022P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds2P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp2P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd3P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp030P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp032P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds3P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp3P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd4P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp040P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp042P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds4P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp4P2PsoDaug:1 ; ///<
+    UINT32                                        SmuTatd5P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp050P2PsoDaug:1 ; ///<
+    UINT32                                        SmuSp052P2PsoDaug:1 ; ///<
+    UINT32                                         SmuLds5P2PsoDaug:1 ; ///<
+    UINT32                                         SmuTcp5P2PsoDaug:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE03002FC_STRUCT;
+
+// **** D0F0xBC_xE0300320 Register Definition ****
+// Address
+#define D0F0xBC_xE0300320_ADDRESS                               0xe0300320
+
+// Type
+#define D0F0xBC_xE0300320_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300320_PgdPgfsmClockEn_OFFSET                0
+#define D0F0xBC_xE0300320_PgdPgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300320_PgdPgfsmClockEn_MASK                  0x1
+#define D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET              1
+#define D0F0xBC_xE0300320_IommuPgfsmClockEn_WIDTH               1
+#define D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK                0x2
+#define D0F0xBC_xE0300320_Reserved_31_2_OFFSET                  2
+#define D0F0xBC_xE0300320_Reserved_31_2_WIDTH                   30
+#define D0F0xBC_xE0300320_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xBC_xE0300320
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          PgdPgfsmClockEn:1 ; ///<
+    UINT32                                        IommuPgfsmClockEn:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300320_STRUCT;
+
+// **** D0F0xBC_xE0300324 Register Definition ****
+// Address
+#define D0F0xBC_xE0300324_ADDRESS                               0xe0300324
+
+// Type
+#define D0F0xBC_xE0300324_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE0300324_VcePgfsmClockEn_OFFSET                0
+#define D0F0xBC_xE0300324_VcePgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300324_VcePgfsmClockEn_MASK                  0x1
+#define D0F0xBC_xE0300324_UvdPgfsmClockEn_OFFSET                1
+#define D0F0xBC_xE0300324_UvdPgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK                  0x2
+#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET                2
+#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_WIDTH                 1
+#define D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK                  0x4
+#define D0F0xBC_xE0300324_Reserved_31_3_OFFSET                  3
+#define D0F0xBC_xE0300324_Reserved_31_3_WIDTH                   29
+#define D0F0xBC_xE0300324_Reserved_31_3_MASK                    0xfffffff8
+
+/// D0F0xBC_xE0300324
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          VcePgfsmClockEn:1 ; ///<
+    UINT32                                          UvdPgfsmClockEn:1 ; ///<
+    UINT32                                          Dc2PgfsmClockEn:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0300324_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        Simd0PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd1PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd2PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd3PgfsmClockEn:1 ; ///<
+    UINT32                                        Simd4PgfsmClockEn:1 ; ///<
+    UINT32        ex1009_0:1;
+    UINT32        ex1009_1:1;
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1009_STRUCT;
+
+// **** D0F0xBC_xFF000000 Register Definition ****
+// Address
+#define D0F0xBC_xFF000000_ADDRESS                               0xff000000
+
+// Type
+#define D0F0xBC_xFF000000_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xFF000000_GckFuseProg_OFFSET                    0
+#define D0F0xBC_xFF000000_GckFuseProg_WIDTH                     1
+#define D0F0xBC_xFF000000_GckFuseProg_MASK                      0x1
+#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET         1
+#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH          6
+#define D0F0xBC_xFF000000_MainPllOpFreqIdStartup_MASK           0x7e
+#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_OFFSET             7
+#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_WIDTH              6
+#define D0F0xBC_xFF000000_MainPllOpFreqIdMax_MASK               0x1f80
+#define D0F0xBC_xFF000000_MainPllRefAdj_OFFSET                  13
+#define D0F0xBC_xFF000000_MainPllRefAdj_WIDTH                   5
+#define D0F0xBC_xFF000000_MainPllRefAdj_MASK                    0x3e000
+#define D0F0xBC_xFF000000_PllMiscFuseCtl_OFFSET                 18
+#define D0F0xBC_xFF000000_PllMiscFuseCtl_WIDTH                  4
+#define D0F0xBC_xFF000000_PllMiscFuseCtl_MASK                   0x3c0000
+#define D0F0xBC_xFF000000_Reserved_31_22_OFFSET                 22
+#define D0F0xBC_xFF000000_Reserved_31_22_WIDTH                  10
+#define D0F0xBC_xFF000000_Reserved_31_22_MASK                   0xffc00000
+
+/// D0F0xBC_xFF000000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              GckFuseProg:1 ; ///<
+    UINT32                                   MainPllOpFreqIdStartup:6 ; ///<
+    UINT32                                       MainPllOpFreqIdMax:6 ; ///<
+    UINT32                                            MainPllRefAdj:5 ; ///<
+    UINT32                                           PllMiscFuseCtl:4 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xFF000000_STRUCT;
+
+// **** D0F0xE4_WRAP_0046 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0046_ADDRESS                               0x46
+
+// Type
+#define D0F0xE4_WRAP_0046_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0046_SubsystemVendorID_OFFSET              0
+#define D0F0xE4_WRAP_0046_SubsystemVendorID_WIDTH               16
+#define D0F0xE4_WRAP_0046_SubsystemVendorID_MASK                0xffff
+#define D0F0xE4_WRAP_0046_SubsystemID_OFFSET                    16
+#define D0F0xE4_WRAP_0046_SubsystemID_WIDTH                     16
+#define D0F0xE4_WRAP_0046_SubsystemID_MASK                      0xffff0000
+
+/// D0F0xE4_WRAP_0046
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        SubsystemVendorID:16; ///<
+    UINT32                                              SubsystemID:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0046_STRUCT;
+
+// **** D0F0xE4_WRAP_0080 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0080_ADDRESS                               0x80
+
+// Type
+#define D0F0xE4_WRAP_0080_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET             0
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH              4
+#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK               0xf
+#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET                  4
+#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH                   28
+#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK                    0xfffffff0
+
+/// D0F0xE4_WRAP_0080
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       StrapBifLinkConfig:4 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0080_STRUCT;
+
+// **** D0F0xE4_WRAP_0800 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0800_ADDRESS                               0x800
+
+// Type
+#define D0F0xE4_WRAP_0800_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET                   0
+#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH                    1
+#define D0F0xE4_WRAP_0800_HoldTraining_MASK                     0x1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_WRAP_0800
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HoldTraining:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0800_STRUCT;
+
+// **** D0F0xE4_WRAP_0803 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0803_ADDRESS                               0x803
+
+// Type
+#define D0F0xE4_WRAP_0803_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0803
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0803_STRUCT;
+
+// **** D0F0xE4_WRAP_0903 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0903_ADDRESS                               0x903
+
+// Type
+#define D0F0xE4_WRAP_0903_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET                   0
+#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH                    5
+#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK                     0x1f
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET          5
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH           1
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK            0x20
+#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_WRAP_0903
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                    StrapBifDeemphasisSel:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_0903_STRUCT;
+
+
+// **** D0F0xE4_WRAP_8011 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8011_ADDRESS                               0x8011
+
+// Type
+#define D0F0xE4_WRAP_8011_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET            0
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH             6
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK              0x3f
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET              6
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH               1
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK                0x40
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET             7
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH              1
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK               0x80
+#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET                  8
+#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH                   1
+#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK                    0x100
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET            9
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK              0x200
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET           10
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK             0xfc00
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET               16
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH                1
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK                 0x10000
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET           17
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK             0x7e0000
+#define D0F0xE4_WRAP_8011_DebugBusClkEnable_OFFSET              23
+#define D0F0xE4_WRAP_8011_DebugBusClkEnable_WIDTH               1
+#define D0F0xE4_WRAP_8011_DebugBusClkEnable_MASK                0x800000
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET            24
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK              0x1000000
+#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_OFFSET            25
+#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_WIDTH             1
+#define D0F0xE4_WRAP_8011_DdiDualLinkOverride_MASK              0x2000000
+#define D0F0xE4_WRAP_8011_Reserved_30_26_OFFSET                 26
+#define D0F0xE4_WRAP_8011_Reserved_30_26_WIDTH                  5
+#define D0F0xE4_WRAP_8011_Reserved_30_26_MASK                   0x7c000000
+#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET                  31
+#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH                   1
+#define D0F0xE4_WRAP_8011_StrapBifValid_MASK                    0x80000000
+
+/// D0F0xE4_WRAP_8011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      TxclkDynGateLatency:6 ; ///<
+    UINT32                                        TxclkPermGateEven:1 ; ///<
+    UINT32                                       TxclkDynGateEnable:1 ; ///<
+    UINT32                                            TxclkPermStop:1 ; ///<
+    UINT32                                      TxclkRegsGateEnable:1 ; ///<
+    UINT32                                     TxclkRegsGateLatency:6 ; ///<
+    UINT32                                         RcvrDetClkEnable:1 ; ///<
+    UINT32                                     TxclkPermGateLatency:6 ; ///<
+    UINT32                                        DebugBusClkEnable:1 ; ///<
+    UINT32                                      TxclkLcntGateEnable:1 ; ///<
+    UINT32                                      DdiDualLinkOverride:1 ; ///<
+    UINT32                                           Reserved_30_26:5 ; ///<
+    UINT32                                            StrapBifValid:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8011_STRUCT;
+
+// **** D0F0xE4_WRAP_8016 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8016_ADDRESS                               0x8016
+
+// Type
+#define D0F0xE4_WRAP_8016_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET                0
+#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH                 6
+#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK                  0x3f
+#define D0F0xE4_WRAP_8016_Reserved_15_6_OFFSET                  6
+#define D0F0xE4_WRAP_8016_Reserved_15_6_WIDTH                   10
+#define D0F0xE4_WRAP_8016_Reserved_15_6_MASK                    0xffc0
+#define D0F0xE4_WRAP_8016_LclkDynGateLatency_OFFSET             16
+#define D0F0xE4_WRAP_8016_LclkDynGateLatency_WIDTH              6
+#define D0F0xE4_WRAP_8016_LclkDynGateLatency_MASK               0x3f0000
+#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET                   22
+#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH                    1
+#define D0F0xE4_WRAP_8016_LclkGateFree_MASK                     0x400000
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET              23
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH               1
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK                0x800000
+#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET                 24
+#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH                  8
+#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK                   0xff000000
+
+/// D0F0xE4_WRAP_8016
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          CalibAckLatency:6 ; ///<
+    UINT32                                            Reserved_15_6:10; ///<
+    UINT32                                       LclkDynGateLatency:6 ; ///<
+    UINT32                                             LclkGateFree:1 ; ///<
+    UINT32                                        LclkDynGateEnable:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8016_STRUCT;
+
+// **** D0F0xE4_WRAP_8021 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8021_ADDRESS                               0x8021
+
+// Type
+#define D0F0xE4_WRAP_8021_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8021_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8021_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8021_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8021_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8021_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8021_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8021_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8021_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8021_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8021_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8021_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8021_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8021
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8021_STRUCT;
+
+// **** D0F0xE4_WRAP_8022 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8022_ADDRESS                               0x8022
+
+// Type
+#define D0F0xE4_WRAP_8022_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8022_Lanes10_OFFSET                        0
+#define D0F0xE4_WRAP_8022_Lanes10_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes10_MASK                          0xf
+#define D0F0xE4_WRAP_8022_Lanes32_OFFSET                        4
+#define D0F0xE4_WRAP_8022_Lanes32_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes32_MASK                          0xf0
+#define D0F0xE4_WRAP_8022_Lanes54_OFFSET                        8
+#define D0F0xE4_WRAP_8022_Lanes54_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes54_MASK                          0xf00
+#define D0F0xE4_WRAP_8022_Lanes76_OFFSET                        12
+#define D0F0xE4_WRAP_8022_Lanes76_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes76_MASK                          0xf000
+#define D0F0xE4_WRAP_8022_Lanes98_OFFSET                        16
+#define D0F0xE4_WRAP_8022_Lanes98_WIDTH                         4
+#define D0F0xE4_WRAP_8022_Lanes98_MASK                          0xf0000
+#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET                      20
+#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1110_MASK                        0xf00000
+#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET                      24
+#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1312_MASK                        0xf000000
+#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET                      28
+#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH                       4
+#define D0F0xE4_WRAP_8022_Lanes1514_MASK                        0xf0000000
+
+/// D0F0xE4_WRAP_8022
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Lanes10:4 ; ///<
+    UINT32                                                  Lanes32:4 ; ///<
+    UINT32                                                  Lanes54:4 ; ///<
+    UINT32                                                  Lanes76:4 ; ///<
+    UINT32                                                  Lanes98:4 ; ///<
+    UINT32                                                Lanes1110:4 ; ///<
+    UINT32                                                Lanes1312:4 ; ///<
+    UINT32                                                Lanes1514:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8022_STRUCT;
+
+// **** D0F0xE4_WRAP_8023 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8023_ADDRESS                               0x8023
+
+// Type
+#define D0F0xE4_WRAP_8023_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET                     0
+#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH                      16
+#define D0F0xE4_WRAP_8023_LaneEnable_MASK                       0xffff
+#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_WRAP_8023
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               LaneEnable:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8023_STRUCT;
+
+// **** D0F0xE4_WRAP_8031 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8031_ADDRESS                               0x8031
+
+// Type
+#define D0F0xE4_WRAP_8031_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET                 0
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH                  10
+#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK                   0x3ff
+#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET                 10
+#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH                  6
+#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK                   0xfc00
+#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET                     16
+#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH                      1
+#define D0F0xE4_WRAP_8031_LnCntValid_MASK                       0x10000
+#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET                 17
+#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH                  15
+#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK                   0xfffe0000
+
+/// D0F0xE4_WRAP_8031
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LnCntBandwidth:10; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                               LnCntValid:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8031_STRUCT;
+
+// **** D0F0xE4_WRAP_8040 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8040_ADDRESS                               0x8040
+
+// Type
+#define D0F0xE4_WRAP_8040_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8040_OwnSlice_OFFSET                       0
+#define D0F0xE4_WRAP_8040_OwnSlice_WIDTH                        1
+#define D0F0xE4_WRAP_8040_OwnSlice_MASK                         0x1
+#define D0F0xE4_WRAP_8040_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_WRAP_8040_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_WRAP_8040_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_WRAP_8040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 OwnSlice:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8040_STRUCT;
+
+
+
+
+
+
+
+
+
+
+
+// **** D0F0xE4_WRAP_8060 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8060_ADDRESS                               0x8060
+
+// Type
+#define D0F0xE4_WRAP_8060_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET                    0
+#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH                     1
+#define D0F0xE4_WRAP_8060_Reconfigure_MASK                      0x1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET                  2
+#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH                   1
+#define D0F0xE4_WRAP_8060_ResetComplete_MASK                    0x4
+#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET                  3
+#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH                   13
+#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK                    0xfff8
+#define D0F0xE4_WRAP_8060_Bif0GlobalReset_OFFSET                16
+#define D0F0xE4_WRAP_8060_Bif0GlobalReset_WIDTH                 1
+#define D0F0xE4_WRAP_8060_Bif0GlobalReset_MASK                  0x10000
+#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_OFFSET           17
+#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_WIDTH            1
+#define D0F0xE4_WRAP_8060_Bif0CalibrationReset_MASK             0x20000
+#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET                 18
+#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH                  14
+#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK                   0xfffc0000
+
+/// D0F0xE4_WRAP_8060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reconfigure:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                            ResetComplete:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                          Bif0GlobalReset:1 ; ///<
+    UINT32                                     Bif0CalibrationReset:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8060_STRUCT;
+
+// **** D0F0xE4_WRAP_8062 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8062_ADDRESS                               0x8062
+
+// Type
+#define D0F0xE4_WRAP_8062_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET                  0
+#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH                   1
+#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK                    0x1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET                   1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH                    1
+#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK                     0x2
+#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET                    2
+#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH                     3
+#define D0F0xE4_WRAP_8062_ResetPeriod_MASK                      0x1c
+#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET                   5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH                    5
+#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK                     0x3e0
+#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET                    10
+#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH                     1
+#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK                      0x400
+#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET                 11
+#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH                  1
+#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK                   0x800
+#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET                 12
+#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH                  20
+#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK                   0xfffff000
+
+/// D0F0xE4_WRAP_8062
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ReconfigureEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              ResetPeriod:3 ; ///<
+    UINT32                                             Reserved_9_5:5 ; ///<
+    UINT32                                              BlockOnIdle:1 ; ///<
+    UINT32                                           ConfigXferMode:1 ; ///<
+    UINT32                                           Reserved_31_12:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8062_STRUCT;
+
+// **** D0F0xE4_WRAP_80F0 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F0_ADDRESS                               0x80f0
+
+// Type
+#define D0F0xE4_WRAP_80F0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET                   0
+#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH                    32
+#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK                     0xffffffff
+
+/// D0F0xE4_WRAP_80F0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             MicroSeconds:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F0_STRUCT;
+
+// **** D0F0xE4_WRAP_80F1 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F1_ADDRESS                               0x80f1
+
+// Type
+#define D0F0xE4_WRAP_80F1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F1_ClockRate_OFFSET                      0
+#define D0F0xE4_WRAP_80F1_ClockRate_WIDTH                       8
+#define D0F0xE4_WRAP_80F1_ClockRate_MASK                        0xff
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET                  8
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH                   24
+#define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK                    0xffffff00
+
+/// D0F0xE4_WRAP_80F1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                ClockRate:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_80F1_STRUCT;
+
+// **** D0F0xE4_WRAP_FFF1 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_FFF1_ADDRESS                               0xfff1
+
+// Type
+#define D0F0xE4_WRAP_FFF1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_FFF1_Reserved_0_0_OFFSET                   0
+#define D0F0xE4_WRAP_FFF1_Reserved_0_0_WIDTH                    1
+#define D0F0xE4_WRAP_FFF1_Reserved_0_0_MASK                     0x1
+#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_OFFSET               1
+#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_WIDTH                4
+#define D0F0xE4_WRAP_FFF1_PcieSpareGppFch2_MASK                 0x1e
+#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_OFFSET       5
+#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_WIDTH        1
+#define D0F0xE4_WRAP_FFF1_CoreBphyRstPwrSnifferDis_MASK         0x20
+#define D0F0xE4_WRAP_FFF1_LcSupportGen2_OFFSET                  6
+#define D0F0xE4_WRAP_FFF1_LcSupportGen2_WIDTH                   1
+#define D0F0xE4_WRAP_FFF1_LcSupportGen2_MASK                    0x40
+#define D0F0xE4_WRAP_FFF1_ROSupportGen2_OFFSET                  7
+#define D0F0xE4_WRAP_FFF1_ROSupportGen2_WIDTH                   1
+#define D0F0xE4_WRAP_FFF1_ROSupportGen2_MASK                    0x80
+#define D0F0xE4_WRAP_FFF1_Reserved_31_8_OFFSET                  8
+#define D0F0xE4_WRAP_FFF1_Reserved_31_8_WIDTH                   24
+#define D0F0xE4_WRAP_FFF1_Reserved_31_8_MASK                    0xffffff00
+
+/// D0F0xE4_WRAP_FFF1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                         PcieSpareGppFch2:4 ; ///<
+    UINT32                                 CoreBphyRstPwrSnifferDis:1 ; ///<
+    UINT32                                            LcSupportGen2:1 ; ///<
+    UINT32                                            ROSupportGen2:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_FFF1_STRUCT;
+
+// **** D0F0xE4_PIF_0010 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0010_ADDRESS                                0x10
+
+// Type
+#define D0F0xE4_PIF_0010_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET                    0
+#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH                     4
+#define D0F0xE4_PIF_0010_Reserved_3_0_MASK                      0xf
+#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET                  4
+#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH                   1
+#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK                    0x10
+#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET                    5
+#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH                     1
+#define D0F0xE4_PIF_0010_Reserved_5_5_MASK                      0x20
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET           6
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH            1
+#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK             0x40
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET               7
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH                1
+#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK                 0x80
+#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET                   8
+#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH                    9
+#define D0F0xE4_PIF_0010_Reserved_16_8_MASK                     0x1ff00
+#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET                     17
+#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK                       0xe0000
+#define D0F0xE4_PIF_0010_Reserved_31_20_OFFSET                  20
+#define D0F0xE4_PIF_0010_Reserved_31_20_WIDTH                   12
+#define D0F0xE4_PIF_0010_Reserved_31_20_MASK                    0xfff00000
+
+/// D0F0xE4_PIF_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                           EiDetCycleMode:1 ; ///<
+    UINT32                                             Reserved_5_5:1 ; ///<
+    UINT32                                    RxDetectFifoResetMode:1 ; ///<
+    UINT32                                        RxDetectTxPwrMode:1 ; ///<
+    UINT32                                            Reserved_16_8:9 ; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0010_STRUCT;
+
+// **** D0F0xE4_PIF_0011 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0011_ADDRESS                                0x11
+
+// Type
+#define D0F0xE4_PIF_0011_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0011_X2Lane10_OFFSET                        0
+#define D0F0xE4_PIF_0011_X2Lane10_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane10_MASK                          0x1
+#define D0F0xE4_PIF_0011_X2Lane32_OFFSET                        1
+#define D0F0xE4_PIF_0011_X2Lane32_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane32_MASK                          0x2
+#define D0F0xE4_PIF_0011_X2Lane54_OFFSET                        2
+#define D0F0xE4_PIF_0011_X2Lane54_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane54_MASK                          0x4
+#define D0F0xE4_PIF_0011_X2Lane76_OFFSET                        3
+#define D0F0xE4_PIF_0011_X2Lane76_WIDTH                         1
+#define D0F0xE4_PIF_0011_X2Lane76_MASK                          0x8
+#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET                    4
+#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH                     4
+#define D0F0xE4_PIF_0011_Reserved_7_4_MASK                      0xf0
+#define D0F0xE4_PIF_0011_X4Lane30_OFFSET                        8
+#define D0F0xE4_PIF_0011_X4Lane30_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane30_MASK                          0x100
+#define D0F0xE4_PIF_0011_X4Lane74_OFFSET                        9
+#define D0F0xE4_PIF_0011_X4Lane74_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane74_MASK                          0x200
+#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET                  10
+#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH                   2
+#define D0F0xE4_PIF_0011_Reserved_11_10_MASK                    0xc00
+#define D0F0xE4_PIF_0011_X4Lane52_OFFSET                        12
+#define D0F0xE4_PIF_0011_X4Lane52_WIDTH                         1
+#define D0F0xE4_PIF_0011_X4Lane52_MASK                          0x1000
+#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0011_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0011_X8Lane70_OFFSET                        16
+#define D0F0xE4_PIF_0011_X8Lane70_WIDTH                         1
+#define D0F0xE4_PIF_0011_X8Lane70_MASK                          0x10000
+#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET                  17
+#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH                   8
+#define D0F0xE4_PIF_0011_Reserved_24_17_MASK                    0x1fe0000
+#define D0F0xE4_PIF_0011_MultiPif_OFFSET                        25
+#define D0F0xE4_PIF_0011_MultiPif_WIDTH                         1
+#define D0F0xE4_PIF_0011_MultiPif_MASK                          0x2000000
+#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET                  26
+#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH                   6
+#define D0F0xE4_PIF_0011_Reserved_31_26_MASK                    0xfc000000
+
+/// D0F0xE4_PIF_0011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 X2Lane10:1 ; ///<
+    UINT32                                                 X2Lane32:1 ; ///<
+    UINT32                                                 X2Lane54:1 ; ///<
+    UINT32                                                 X2Lane76:1 ; ///<
+    UINT32                                             Reserved_7_4:4 ; ///<
+    UINT32                                                 X4Lane30:1 ; ///<
+    UINT32                                                 X4Lane74:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                                                 X4Lane52:1 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                                 X8Lane70:1 ; ///<
+    UINT32                                           Reserved_24_17:8 ; ///<
+    UINT32                                                 MultiPif:1 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0011_STRUCT;
+
+// **** D0F0xE4_PIF_0012 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0012_ADDRESS                                0x12
+
+// Type
+#define D0F0xE4_PIF_0012_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0012_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0012_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0012_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0012_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0012_STRUCT;
+
+// **** D0F0xE4_PIF_0013 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0013_ADDRESS                                0x13
+
+// Type
+#define D0F0xE4_PIF_0013_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET              0
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK                0x7
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET                  3
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH                   1
+#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK                    0x8
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET              4
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH               3
+#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK                0x70
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET             7
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH              3
+#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK               0x380
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET              10
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH               3
+#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK                0x1c00
+#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET                  13
+#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH                   3
+#define D0F0xE4_PIF_0013_Reserved_15_13_MASK                    0xe000
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET           16
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH            1
+#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK             0x10000
+#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET                  17
+#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH                   7
+#define D0F0xE4_PIF_0013_Reserved_23_17_MASK                    0xfe0000
+#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET                   24
+#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH                    3
+#define D0F0xE4_PIF_0013_PllRampUpTime_MASK                     0x7000000
+#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET                  27
+#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH                   1
+#define D0F0xE4_PIF_0013_Reserved_27_27_MASK                    0x8000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET                28
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH                 1
+#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK                  0x10000000
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET               29
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH                3
+#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK                 0xe0000000
+
+/// D0F0xE4_PIF_0013
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       TxPowerStateInTxs2:3 ; ///<
+    UINT32                                           ForceRxEnInL0s:1 ; ///<
+    UINT32                                       RxPowerStateInRxs2:3 ; ///<
+    UINT32                                      PllPowerStateInTxs2:3 ; ///<
+    UINT32                                       PllPowerStateInOff:3 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                    Tx2p5clkClockGatingEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PllRampUpTime:3 ; ///<
+    UINT32                                           Reserved_27_27:1 ; ///<
+    UINT32                                         PllPwrOverrideEn:1 ; ///<
+    UINT32                                        PllPwrOverrideVal:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0013_STRUCT;
+
+// **** D0F0xE4_PIF_0015 Register Definition ****
+// Address
+#define D0F0xE4_PIF_0015_ADDRESS                                0x15
+
+// Type
+#define D0F0xE4_PIF_0015_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET                   0
+#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK                     0x1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET                   1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK                     0x2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET                   2
+#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK                     0x4
+#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET                   3
+#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK                     0x8
+#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET                   4
+#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK                     0x10
+#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET                   5
+#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK                     0x20
+#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET                   6
+#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK                     0x40
+#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET                   7
+#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH                    1
+#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK                     0x80
+#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PIF_0015_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PIF_0015
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            TxPhyStatus00:1 ; ///<
+    UINT32                                            TxPhyStatus01:1 ; ///<
+    UINT32                                            TxPhyStatus02:1 ; ///<
+    UINT32                                            TxPhyStatus03:1 ; ///<
+    UINT32                                            TxPhyStatus04:1 ; ///<
+    UINT32                                            TxPhyStatus05:1 ; ///<
+    UINT32                                            TxPhyStatus06:1 ; ///<
+    UINT32                                            TxPhyStatus07:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PIF_0015_STRUCT;
+
+// **** D0F0xE4_CORE_0002 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0002_ADDRESS                               0x2
+
+// Type
+#define D0F0xE4_CORE_0002_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET                     0
+#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH                      1
+#define D0F0xE4_CORE_0002_HwDebug_0__MASK                       0x1
+#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET                  1
+#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH                   31
+#define D0F0xE4_CORE_0002_Reserved_31_1_MASK                    0xfffffffe
+
+/// D0F0xE4_CORE_0002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               HwDebug_0_:1 ; ///<
+    UINT32                                            Reserved_31_1:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0002_STRUCT;
+
+// **** D0F0xE4_CORE_0010 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0010_ADDRESS                               0x10
+
+// Type
+#define D0F0xE4_CORE_0010_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET                   0
+#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH                    1
+#define D0F0xE4_CORE_0010_HwInitWrLock_MASK                     0x1
+#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET                   1
+#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH                    8
+#define D0F0xE4_CORE_0010_Reserved_8_1_MASK                     0x1fe
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET                  9
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH                   1
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK                    0x200
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET             10
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH              3
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK               0x1c00
+#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET                 13
+#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH                  19
+#define D0F0xE4_CORE_0010_Reserved_31_13_MASK                   0xffffe000
+
+/// D0F0xE4_CORE_0010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             HwInitWrLock:1 ; ///<
+    UINT32                                             Reserved_8_1:8 ; ///<
+    UINT32                                            UmiNpMemWrite:1 ; ///<
+    UINT32                                       RxSbAdjPayloadSize:3 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0010_STRUCT;
+
+// **** D0F0xE4_CORE_0011 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0011_ADDRESS                               0x11
+
+// Type
+#define D0F0xE4_CORE_0011_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET                  0
+#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH                   4
+#define D0F0xE4_CORE_0011_DynClkLatency_MASK                    0xf
+#define D0F0xE4_CORE_0011_Reserved_15_4_OFFSET                  4
+#define D0F0xE4_CORE_0011_Reserved_15_4_WIDTH                   12
+#define D0F0xE4_CORE_0011_Reserved_15_4_MASK                    0xfff0
+#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_OFFSET           16
+#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_WIDTH            1
+#define D0F0xE4_CORE_0011_CiMaxPayloadSizeMode_MASK             0x10000
+#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_OFFSET           17
+#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_WIDTH            3
+#define D0F0xE4_CORE_0011_CiPrivMaxPayloadSize_MASK             0xe0000
+#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_OFFSET       20
+#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_WIDTH        1
+#define D0F0xE4_CORE_0011_CiMaxReadRequestSizeMode_MASK         0x100000
+#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_OFFSET       21
+#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_WIDTH        3
+#define D0F0xE4_CORE_0011_CiPrivMaxReadRequestSize_MASK         0xe00000
+#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_OFFSET              24
+#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_WIDTH               1
+#define D0F0xE4_CORE_0011_CiMaxReadSafeMode_MASK                0x1000000
+#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_OFFSET        25
+#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_WIDTH         1
+#define D0F0xE4_CORE_0011_CiExtendedTagEnOverride_MASK          0x2000000
+#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_OFFSET        26
+#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_WIDTH         1
+#define D0F0xE4_CORE_0011_CiMaxCplPayloadSizeMode_MASK          0x4000000
+#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_OFFSET        27
+#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_WIDTH         3
+#define D0F0xE4_CORE_0011_CiPrivMaxCplPayloadSize_MASK          0x38000000
+#define D0F0xE4_CORE_0011_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_CORE_0011_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_CORE_0011_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_CORE_0011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DynClkLatency:4 ; ///<
+    UINT32                                            Reserved_15_4:12; ///<
+    UINT32                                     CiMaxPayloadSizeMode:1 ; ///<
+    UINT32                                     CiPrivMaxPayloadSize:3 ; ///<
+    UINT32                                 CiMaxReadRequestSizeMode:1 ; ///<
+    UINT32                                 CiPrivMaxReadRequestSize:3 ; ///<
+    UINT32                                        CiMaxReadSafeMode:1 ; ///<
+    UINT32                                  CiExtendedTagEnOverride:1 ; ///<
+    UINT32                                  CiMaxCplPayloadSizeMode:1 ; ///<
+    UINT32                                  CiPrivMaxCplPayloadSize:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0011_STRUCT;
+
+// **** D0F0xE4_CORE_001C Register Definition ****
+// Address
+#define D0F0xE4_CORE_001C_ADDRESS                               0x1c
+
+// Type
+#define D0F0xE4_CORE_001C_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET              0
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH               1
+#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK                0x1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET                  1
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK                    0x3e
+#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET                  6
+#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH                   5
+#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK                    0x7c0
+#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET                 11
+#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH                  21
+#define D0F0xE4_CORE_001C_Reserved_31_11_MASK                   0xfffff800
+
+/// D0F0xE4_CORE_001C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxArbRoundRobinEn:1 ; ///<
+    UINT32                                            TxArbSlvLimit:5 ; ///<
+    UINT32                                            TxArbMstLimit:5 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_001C_STRUCT;
+
+// **** D0F0xE4_CORE_0020 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0020_ADDRESS                               0x20
+
+// Type
+#define D0F0xE4_CORE_0020_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0020_Reserved_7_0_OFFSET                   0
+#define D0F0xE4_CORE_0020_Reserved_7_0_WIDTH                    8
+#define D0F0xE4_CORE_0020_Reserved_7_0_MASK                     0xff
+#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET               8
+#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH                1
+#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK                 0x100
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET                9
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH                 1
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK                  0x200
+#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET                 10
+#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH                  22
+#define D0F0xE4_CORE_0020_Reserved_31_10_MASK                   0xfffffc00
+
+/// D0F0xE4_CORE_0020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_7_0:8 ; ///<
+    UINT32                                         CiSlvOrderingDis:1 ; ///<
+    UINT32                                          CiRcOrderingDis:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0020_STRUCT;
+
+// **** D0F0xE4_CORE_0040 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0040_ADDRESS                               0x40
+
+// Type
+#define D0F0xE4_CORE_0040_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET                  0
+#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH                   14
+#define D0F0xE4_CORE_0040_Reserved_13_0_MASK                    0x3fff
+#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET                  14
+#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH                   2
+#define D0F0xE4_CORE_0040_PElecIdleMode_MASK                    0xc000
+#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET                 16
+#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH                  16
+#define D0F0xE4_CORE_0040_Reserved_31_16_MASK                   0xffff0000
+
+/// D0F0xE4_CORE_0040
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_13_0:14; ///<
+    UINT32                                            PElecIdleMode:2 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_0040_STRUCT;
+
+// **** D0F0xE4_CORE_00B0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00B0_ADDRESS                               0xb0
+
+// Type
+#define D0F0xE4_CORE_00B0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET                   0
+#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK                     0x3
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET                   2
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK                     0x4
+#define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET                   3
+#define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH                    2
+#define D0F0xE4_CORE_00B0_Reserved_4_3_MASK                     0x18
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET                   5
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH                    1
+#define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK                     0x20
+#define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET                  6
+#define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH                   26
+#define D0F0xE4_CORE_00B0_Reserved_31_6_MASK                    0xffffffc0
+
+/// D0F0xE4_CORE_00B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_1_0:2 ; ///<
+    UINT32                                             StrapF0MsiEn:1 ; ///<
+    UINT32                                             Reserved_4_3:2 ; ///<
+    UINT32                                             StrapF0AerEn:1 ; ///<
+    UINT32                                            Reserved_31_6:26; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00B0_STRUCT;
+
+// **** D0F0xE4_CORE_00C0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00C0_ADDRESS                               0xc0
+
+// Type
+#define D0F0xE4_CORE_00C0_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET                  0
+#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH                   28
+#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK                    0xfffffff
+#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET                28
+#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH                 1
+#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK                  0x10000000
+#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET                29
+#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH                 1
+#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK                  0x20000000
+#define D0F0xE4_CORE_00C0_StrapFlrEn_OFFSET                     30
+#define D0F0xE4_CORE_00C0_StrapFlrEn_WIDTH                      1
+#define D0F0xE4_CORE_00C0_StrapFlrEn_MASK                       0x40000000
+#define D0F0xE4_CORE_00C0_Reserved_31_31_OFFSET                 31
+#define D0F0xE4_CORE_00C0_Reserved_31_31_WIDTH                  1
+#define D0F0xE4_CORE_00C0_Reserved_31_31_MASK                   0x80000000
+
+/// D0F0xE4_CORE_00C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_27_0:28; ///<
+    UINT32                                          StrapReverseAll:1 ; ///<
+    UINT32                                          StrapMstAdr64En:1 ; ///<
+    UINT32                                               StrapFlrEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00C0_STRUCT;
+
+// **** D0F0xE4_CORE_00C1 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00C1_ADDRESS                               0xc1
+
+// Type
+#define D0F0xE4_CORE_00C1_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET   0
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH    1
+#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK     0x1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET            1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH             1
+#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK              0x2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET                  2
+#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH                   30
+#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK                    0xfffffffc
+
+/// D0F0xE4_CORE_00C1
+typedef union {
+  struct {                                                              ///<
+    UINT32                             StrapLinkBwNotificationCapEn:1 ; ///<
+    UINT32                                      StrapGen2Compliance:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_CORE_00C1_STRUCT;
+
+// **** D0F0xE4_PHY_0009 Register Definition ****
+// Address
+#define D0F0xE4_PHY_0009_ADDRESS                                0x9
+
+// Type
+#define D0F0xE4_PHY_0009_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_0009_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_0009_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_0009_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_0009_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_0009_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_0009_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_0009_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_0009_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_0009_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_0009_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_0009_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_0009_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_0009
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_0009_STRUCT;
+
+// **** D0F0xE4_PHY_000A Register Definition ****
+// Address
+#define D0F0xE4_PHY_000A_ADDRESS                                0xa
+
+// Type
+#define D0F0xE4_PHY_000A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET                   0
+#define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH                    24
+#define D0F0xE4_PHY_000A_Reserved_23_0_MASK                     0xffffff
+#define D0F0xE4_PHY_000A_ClkOff_OFFSET                          24
+#define D0F0xE4_PHY_000A_ClkOff_WIDTH                           1
+#define D0F0xE4_PHY_000A_ClkOff_MASK                            0x1000000
+#define D0F0xE4_PHY_000A_DisplayStream_OFFSET                   25
+#define D0F0xE4_PHY_000A_DisplayStream_WIDTH                    1
+#define D0F0xE4_PHY_000A_DisplayStream_MASK                     0x2000000
+#define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET                  26
+#define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_27_26_MASK                    0xc000000
+#define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET                  28
+#define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH                   1
+#define D0F0xE4_PHY_000A_CascadedPllSel_MASK                    0x10000000
+#define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET                  29
+#define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH                   2
+#define D0F0xE4_PHY_000A_Reserved_30_29_MASK                    0x60000000
+#define D0F0xE4_PHY_000A_PCIePllSel_OFFSET                      31
+#define D0F0xE4_PHY_000A_PCIePllSel_WIDTH                       1
+#define D0F0xE4_PHY_000A_PCIePllSel_MASK                        0x80000000
+
+/// D0F0xE4_PHY_000A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_23_0:24; ///<
+    UINT32                                                   ClkOff:1 ; ///<
+    UINT32                                            DisplayStream:1 ; ///<
+    UINT32                                           Reserved_27_26:2 ; ///<
+    UINT32                                           CascadedPllSel:1 ; ///<
+    UINT32                                           Reserved_30_29:2 ; ///<
+    UINT32                                               PCIePllSel:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000A_STRUCT;
+
+// **** D0F0xE4_PHY_000B Register Definition ****
+// Address
+#define D0F0xE4_PHY_000B_ADDRESS                                0xb
+
+// Type
+#define D0F0xE4_PHY_000B_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET                      0
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK                        0x1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET                      1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK                        0x2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET                   2
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH                    1
+#define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK                     0x4
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET                    3
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK                      0x8
+#define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET                    4
+#define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_DllLockSbiEn_MASK                      0x10
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET               5
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH                1
+#define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK                 0x20
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET                    6
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK                      0x40
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET              7
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH               1
+#define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK                0x80
+#define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET                      8
+#define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH                       1
+#define D0F0xE4_PHY_000B_EiDetSbiEn_MASK                        0x100
+#define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET                   9
+#define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH                    5
+#define D0F0xE4_PHY_000B_Reserved_13_9_MASK                     0x3e00
+#define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET                    14
+#define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH                     1
+#define D0F0xE4_PHY_000B_MargPktSbiEn_MASK                      0x4000
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET                  15
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH                   1
+#define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK                    0x8000
+#define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_000B_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_000B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               TxPwrSbiEn:1 ; ///<
+    UINT32                                               RxPwrSbiEn:1 ; ///<
+    UINT32                                            PcieModeSbiEn:1 ; ///<
+    UINT32                                             FreqDivSbiEn:1 ; ///<
+    UINT32                                             DllLockSbiEn:1 ; ///<
+    UINT32                                        OffsetCancelSbiEn:1 ; ///<
+    UINT32                                             SkipBitSbiEn:1 ; ///<
+    UINT32                                       IncoherentClkSbiEn:1 ; ///<
+    UINT32                                               EiDetSbiEn:1 ; ///<
+    UINT32                                            Reserved_13_9:5 ; ///<
+    UINT32                                             MargPktSbiEn:1 ; ///<
+    UINT32                                           PllCmpPktSbiEn:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_000B_STRUCT;
+
+// **** D0F0xE4_PHY_2000 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2000_ADDRESS                                0x2000
+
+// Type
+#define D0F0xE4_PHY_2000_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET                  0
+#define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH                   3
+#define D0F0xE4_PHY_2000_PllPowerDownEn_MASK                    0x7
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET               3
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH                1
+#define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK                 0x8
+#define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET                   4
+#define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH                    28
+#define D0F0xE4_PHY_2000_Reserved_31_4_MASK                     0xfffffff0
+
+/// D0F0xE4_PHY_2000
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PllPowerDownEn:3 ; ///<
+    UINT32                                        PllAutoPwrDownDis:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2000_STRUCT;
+
+// **** D0F0xE4_PHY_2002 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2002_ADDRESS                                0x2002
+
+// Type
+#define D0F0xE4_PHY_2002_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2002_Reserved_26_0_OFFSET                   0
+#define D0F0xE4_PHY_2002_Reserved_26_0_WIDTH                    27
+#define D0F0xE4_PHY_2002_Reserved_26_0_MASK                     0x7ffffff
+#define D0F0xE4_PHY_2002_RoCalEn_OFFSET                         27
+#define D0F0xE4_PHY_2002_RoCalEn_WIDTH                          1
+#define D0F0xE4_PHY_2002_RoCalEn_MASK                           0x8000000
+#define D0F0xE4_PHY_2002_Reserved_30_28_OFFSET                  28
+#define D0F0xE4_PHY_2002_Reserved_30_28_WIDTH                   3
+#define D0F0xE4_PHY_2002_Reserved_30_28_MASK                    0x70000000
+#define D0F0xE4_PHY_2002_IsLc_OFFSET                            31
+#define D0F0xE4_PHY_2002_IsLc_WIDTH                             1
+#define D0F0xE4_PHY_2002_IsLc_MASK                              0x80000000
+
+/// D0F0xE4_PHY_2002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_26_0:27; ///<
+    UINT32                                                  RoCalEn:1 ; ///<
+    UINT32                                           Reserved_30_28:3 ; ///<
+    UINT32                                                     IsLc:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2002_STRUCT;
+
+// **** D0F0xE4_PHY_2005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2005_ADDRESS                                0x2005
+
+// Type
+#define D0F0xE4_PHY_2005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2005_PllClkFreq_OFFSET                      0
+#define D0F0xE4_PHY_2005_PllClkFreq_WIDTH                       4
+#define D0F0xE4_PHY_2005_PllClkFreq_MASK                        0xf
+#define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET                    4
+#define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH                     5
+#define D0F0xE4_PHY_2005_Reserved_8_4_MASK                      0x1f0
+#define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET                   9
+#define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH                    2
+#define D0F0xE4_PHY_2005_PllClkFreqExt_MASK                     0x600
+#define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET                  11
+#define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH                   2
+#define D0F0xE4_PHY_2005_Reserved_12_11_MASK                    0x1800
+#define D0F0xE4_PHY_2005_PllMode_OFFSET                         13
+#define D0F0xE4_PHY_2005_PllMode_WIDTH                          2
+#define D0F0xE4_PHY_2005_PllMode_MASK                           0x6000
+#define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET                  15
+#define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH                   17
+#define D0F0xE4_PHY_2005_Reserved_31_15_MASK                    0xffff8000
+
+/// D0F0xE4_PHY_2005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               PllClkFreq:4 ; ///<
+    UINT32                                             Reserved_8_4:5 ; ///<
+    UINT32                                            PllClkFreqExt:2 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                  PllMode:2 ; ///<
+    UINT32                                           Reserved_31_15:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2005_STRUCT;
+
+// **** D0F0xE4_PHY_2008 Register Definition ****
+// Address
+#define D0F0xE4_PHY_2008_ADDRESS                                0x2008
+
+// Type
+#define D0F0xE4_PHY_2008_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET                0
+#define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH                 1
+#define D0F0xE4_PHY_2008_PllControlUpdate_MASK                  0x1
+#define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET                   1
+#define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH                    22
+#define D0F0xE4_PHY_2008_Reserved_22_1_MASK                     0x7ffffe
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET              23
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH               3
+#define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK                0x3800000
+#define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET                  26
+#define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH                   3
+#define D0F0xE4_PHY_2008_Reserved_28_26_MASK                    0x1c000000
+#define D0F0xE4_PHY_2008_VdDetectEn_OFFSET                      29
+#define D0F0xE4_PHY_2008_VdDetectEn_WIDTH                       1
+#define D0F0xE4_PHY_2008_VdDetectEn_MASK                        0x20000000
+#define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_2008_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_2008
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PllControlUpdate:1 ; ///<
+    UINT32                                            Reserved_22_1:22; ///<
+    UINT32                                       MeasCycCntVal_2_0_:3 ; ///<
+    UINT32                                           Reserved_28_26:3 ; ///<
+    UINT32                                               VdDetectEn:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_2008_STRUCT;
+
+// **** D0F0xE4_PHY_4001 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4001_ADDRESS                                0x4001
+
+// Type
+#define D0F0xE4_PHY_4001_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET                   0
+#define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH                    15
+#define D0F0xE4_PHY_4001_Reserved_14_0_MASK                     0x7fff
+#define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET                  15
+#define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH                   1
+#define D0F0xE4_PHY_4001_ForceDccRecalc_MASK                    0x8000
+#define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_4001_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_4001
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                           ForceDccRecalc:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4001_STRUCT;
+
+// **** D0F0xE4_PHY_4002 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4002_ADDRESS                                0x4002
+
+// Type
+#define D0F0xE4_PHY_4002_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET                    0
+#define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH                     3
+#define D0F0xE4_PHY_4002_Reserved_2_0_MASK                      0x7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET              3
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH               1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK                0x8
+#define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET                  4
+#define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH                   3
+#define D0F0xE4_PHY_4002_SamClkPiOffset_MASK                    0x70
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET                7
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH                 1
+#define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK                  0x80
+#define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET                   8
+#define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH                    6
+#define D0F0xE4_PHY_4002_Reserved_13_8_MASK                     0x3f00
+#define D0F0xE4_PHY_4002_LfcMin_OFFSET                          14
+#define D0F0xE4_PHY_4002_LfcMin_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMin_MASK                            0x3fc000
+#define D0F0xE4_PHY_4002_LfcMax_OFFSET                          22
+#define D0F0xE4_PHY_4002_LfcMax_WIDTH                           8
+#define D0F0xE4_PHY_4002_LfcMax_MASK                            0x3fc00000
+#define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET                  30
+#define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH                   2
+#define D0F0xE4_PHY_4002_Reserved_31_30_MASK                    0xc0000000
+
+/// D0F0xE4_PHY_4002
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                       SamClkPiOffsetSign:1 ; ///<
+    UINT32                                           SamClkPiOffset:3 ; ///<
+    UINT32                                         SamClkPiOffsetEn:1 ; ///<
+    UINT32                                            Reserved_13_8:6 ; ///<
+    UINT32                                                   LfcMin:8 ; ///<
+    UINT32                                                   LfcMax:8 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4002_STRUCT;
+
+// **** D0F0xE4_PHY_4005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4005_ADDRESS                                0x4005
+
+// Type
+#define D0F0xE4_PHY_4005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET                    0
+#define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH                     9
+#define D0F0xE4_PHY_4005_Reserved_8_0_MASK                      0x1ff
+#define D0F0xE4_PHY_4005_JitterInjHold_OFFSET                   9
+#define D0F0xE4_PHY_4005_JitterInjHold_WIDTH                    1
+#define D0F0xE4_PHY_4005_JitterInjHold_MASK                     0x200
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET                 10
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH                  6
+#define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK                   0xfc00
+#define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET                  16
+#define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH                   7
+#define D0F0xE4_PHY_4005_Reserved_22_16_MASK                    0x7f0000
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET                  23
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH                   6
+#define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK                    0x1f800000
+#define D0F0xE4_PHY_4005_JitterInjDir_OFFSET                    29
+#define D0F0xE4_PHY_4005_JitterInjDir_WIDTH                     1
+#define D0F0xE4_PHY_4005_JitterInjDir_MASK                      0x20000000
+#define D0F0xE4_PHY_4005_JitterInjEn_OFFSET                     30
+#define D0F0xE4_PHY_4005_JitterInjEn_WIDTH                      1
+#define D0F0xE4_PHY_4005_JitterInjEn_MASK                       0x40000000
+#define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET                  31
+#define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH                   1
+#define D0F0xE4_PHY_4005_Reserved_31_31_MASK                    0x80000000
+
+/// D0F0xE4_PHY_4005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                            JitterInjHold:1 ; ///<
+    UINT32                                          JitterInjOffCnt:6 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                           JitterInjOnCnt:6 ; ///<
+    UINT32                                             JitterInjDir:1 ; ///<
+    UINT32                                              JitterInjEn:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4005_STRUCT;
+
+// **** D0F0xE4_PHY_4006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4006_ADDRESS                                0x4006
+
+// Type
+#define D0F0xE4_PHY_4006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET                    0
+#define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH                     5
+#define D0F0xE4_PHY_4006_Reserved_4_0_MASK                      0x1f
+#define D0F0xE4_PHY_4006_DfeVoltage_OFFSET                      5
+#define D0F0xE4_PHY_4006_DfeVoltage_WIDTH                       2
+#define D0F0xE4_PHY_4006_DfeVoltage_MASK                        0x60
+#define D0F0xE4_PHY_4006_DfeEn_OFFSET                           7
+#define D0F0xE4_PHY_4006_DfeEn_WIDTH                            1
+#define D0F0xE4_PHY_4006_DfeEn_MASK                             0x80
+#define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET                   8
+#define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH                    24
+#define D0F0xE4_PHY_4006_Reserved_31_8_MASK                     0xffffff00
+
+/// D0F0xE4_PHY_4006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_4_0:5 ; ///<
+    UINT32                                               DfeVoltage:2 ; ///<
+    UINT32                                                    DfeEn:1 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4006_STRUCT;
+
+// **** D0F0xE4_PHY_400A Register Definition ****
+// Address
+#define D0F0xE4_PHY_400A_ADDRESS                                0x400a
+
+// Type
+#define D0F0xE4_PHY_400A_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET                 0
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH                  1
+#define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK                   0x1
+#define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET                    1
+#define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH                     3
+#define D0F0xE4_PHY_400A_Reserved_3_1_MASK                      0xe
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET                4
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH                 1
+#define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK                  0x10
+#define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET                    5
+#define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH                     2
+#define D0F0xE4_PHY_400A_Reserved_6_5_MASK                      0x60
+#define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET                    7
+#define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH                     1
+#define D0F0xE4_PHY_400A_BiasDisInLs2_MASK                      0x80
+#define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET                   8
+#define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH                    5
+#define D0F0xE4_PHY_400A_Reserved_12_8_MASK                     0x1f00
+#define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET                  13
+#define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH                   2
+#define D0F0xE4_PHY_400A_AnalogWaitTime_MASK                    0x6000
+#define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET                  15
+#define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH                   2
+#define D0F0xE4_PHY_400A_Reserved_16_15_MASK                    0x18000
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET               17
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH                1
+#define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK                 0x20000
+#define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET                  18
+#define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH                   11
+#define D0F0xE4_PHY_400A_Reserved_28_18_MASK                    0x1ffc0000
+#define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET                     29
+#define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH                      3
+#define D0F0xE4_PHY_400A_Ls2ExitTime_MASK                       0xe0000000
+
+/// D0F0xE4_PHY_400A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          EnCoreLoopFirst:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                         LockDetOnLs2Exit:1 ; ///<
+    UINT32                                             Reserved_6_5:2 ; ///<
+    UINT32                                             BiasDisInLs2:1 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           AnalogWaitTime:2 ; ///<
+    UINT32                                           Reserved_16_15:2 ; ///<
+    UINT32                                        DllLockFastModeEn:1 ; ///<
+    UINT32                                           Reserved_28_18:11; ///<
+    UINT32                                              Ls2ExitTime:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_400A_STRUCT;
+
+// **** D0F0xE4_PHY_4010 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4010_ADDRESS                               0x4010
+
+// Type
+#define D0F0xE4_PHY_4010_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4010_PhyFuseValid_OFFSET                   0
+#define D0F0xE4_PHY_4010_PhyFuseValid_WIDTH                    1
+#define D0F0xE4_PHY_4010_PhyFuseValid_MASK                     0x1
+#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_OFFSET    1
+#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_WIDTH     1
+#define D0F0xE4_PHY_4010_FuseFuncDllRCFilterOverride_MASK      0x2
+#define D0F0xE4_PHY_4010_Reserved_2_2_OFFSET                   2
+#define D0F0xE4_PHY_4010_Reserved_2_2_WIDTH                    1
+#define D0F0xE4_PHY_4010_Reserved_2_2_MASK                     0x4
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_OFFSET    3
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_WIDTH     1
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStepSize_MASK      0x8
+#define D0F0xE4_PHY_4010_Reserved_4_4_OFFSET                   4
+#define D0F0xE4_PHY_4010_Reserved_4_4_WIDTH                    1
+#define D0F0xE4_PHY_4010_Reserved_4_4_MASK                     0x10
+#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_OFFSET     5
+#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_WIDTH      1
+#define D0F0xE4_PHY_4010_FuseFuncDllMidLockStepSize_MASK       0x20
+#define D0F0xE4_PHY_4010_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_PHY_4010_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_PHY_4010_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_OFFSET        7
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_WIDTH         4
+#define D0F0xE4_PHY_4010_FuseFuncDllFastLockStop_MASK          0x780
+#define D0F0xE4_PHY_4010_Reserved_12_11_OFFSET                 11
+#define D0F0xE4_PHY_4010_Reserved_12_11_WIDTH                  2
+#define D0F0xE4_PHY_4010_Reserved_12_11_MASK                   0x1800
+#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_OFFSET         13
+#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_WIDTH          1
+#define D0F0xE4_PHY_4010_FuseFuncDllInputDccDis_MASK           0x2000
+#define D0F0xE4_PHY_4010_Reserved_14_14_OFFSET                 14
+#define D0F0xE4_PHY_4010_Reserved_14_14_WIDTH                  1
+#define D0F0xE4_PHY_4010_Reserved_14_14_MASK                   0x4000
+#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_OFFSET      15
+#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_WIDTH       2
+#define D0F0xE4_PHY_4010_FuseFuncDllProcessCompCtl_MASK        0x18000
+#define D0F0xE4_PHY_4010_Reserved_19_17_OFFSET                 17
+#define D0F0xE4_PHY_4010_Reserved_19_17_WIDTH                  3
+#define D0F0xE4_PHY_4010_Reserved_19_17_MASK                   0xe0000
+#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_OFFSET          20
+#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_WIDTH           1
+#define D0F0xE4_PHY_4010_FuseFuncDllRdacSupSel_MASK            0x100000
+#define D0F0xE4_PHY_4010_FuseFuncRxSpare_OFFSET                21
+#define D0F0xE4_PHY_4010_FuseFuncRxSpare_WIDTH                 1
+#define D0F0xE4_PHY_4010_FuseFuncRxSpare_MASK                  0x200000
+#define D0F0xE4_PHY_4010_Reserved_31_22_OFFSET                 22
+#define D0F0xE4_PHY_4010_Reserved_31_22_WIDTH                  10
+#define D0F0xE4_PHY_4010_Reserved_31_22_MASK                   0xffc00000
+
+/// D0F0xE4_PHY_4010
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhyFuseValid:1 ; ///<
+    UINT32                              FuseFuncDllRCFilterOverride:1 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                              FuseFuncDllFastLockStepSize:1 ; ///<
+    UINT32                                             Reserved_4_4:1 ; ///<
+    UINT32                               FuseFuncDllMidLockStepSize:1 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                  FuseFuncDllFastLockStop:4 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                   FuseFuncDllInputDccDis:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                FuseFuncDllProcessCompCtl:2 ; ///<
+    UINT32                                           Reserved_19_17:3 ; ///<
+    UINT32                                    FuseFuncDllRdacSupSel:1 ; ///<
+    UINT32                                          FuseFuncRxSpare:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4010_STRUCT;
+
+// **** D0F0xE4_PHY_4011 Register Definition ****
+// Address
+#define D0F0xE4_PHY_4011_ADDRESS                               0x4011
+
+// Type
+#define D0F0xE4_PHY_4011_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_4011_PhyFuseValid_OFFSET                   0
+#define D0F0xE4_PHY_4011_PhyFuseValid_WIDTH                    1
+#define D0F0xE4_PHY_4011_PhyFuseValid_MASK                     0x1
+#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_OFFSET             1
+#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_WIDTH              3
+#define D0F0xE4_PHY_4011_FuseProcDllVrefAdj_MASK               0xe
+#define D0F0xE4_PHY_4011_Reserved_5_4_OFFSET                   4
+#define D0F0xE4_PHY_4011_Reserved_5_4_WIDTH                    2
+#define D0F0xE4_PHY_4011_Reserved_5_4_MASK                     0x30
+#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_OFFSET             6
+#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_WIDTH              3
+#define D0F0xE4_PHY_4011_FuseProcDllIrefAdj_MASK               0x1c0
+#define D0F0xE4_PHY_4011_Reserved_10_9_OFFSET                  9
+#define D0F0xE4_PHY_4011_Reserved_10_9_WIDTH                   2
+#define D0F0xE4_PHY_4011_Reserved_10_9_MASK                    0x600
+#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_OFFSET         11
+#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_WIDTH          3
+#define D0F0xE4_PHY_4011_FuseProcDllProcessComp_MASK           0x3800
+#define D0F0xE4_PHY_4011_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_PHY_4011_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_PHY_4011_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_OFFSET         16
+#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_WIDTH          1
+#define D0F0xE4_PHY_4011_FuseProcDllRCFilterCtl_MASK           0x10000
+#define D0F0xE4_PHY_4011_Reserved_18_17_OFFSET                 17
+#define D0F0xE4_PHY_4011_Reserved_18_17_WIDTH                  2
+#define D0F0xE4_PHY_4011_Reserved_18_17_MASK                   0x60000
+#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_OFFSET            19
+#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_WIDTH             2
+#define D0F0xE4_PHY_4011_FuseProcEiDetThresh_MASK              0x180000
+#define D0F0xE4_PHY_4011_Reserved_22_21_OFFSET                 21
+#define D0F0xE4_PHY_4011_Reserved_22_21_WIDTH                  2
+#define D0F0xE4_PHY_4011_Reserved_22_21_MASK                   0x600000
+#define D0F0xE4_PHY_4011_FuseProcRxSpare_OFFSET                23
+#define D0F0xE4_PHY_4011_FuseProcRxSpare_WIDTH                 1
+#define D0F0xE4_PHY_4011_FuseProcRxSpare_MASK                  0x800000
+#define D0F0xE4_PHY_4011_Reserved_31_24_OFFSET                 24
+#define D0F0xE4_PHY_4011_Reserved_31_24_WIDTH                  8
+#define D0F0xE4_PHY_4011_Reserved_31_24_MASK                   0xff000000
+
+/// D0F0xE4_PHY_4011
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhyFuseValid:1 ; ///<
+    UINT32                                       FuseProcDllVrefAdj:3 ; ///<
+    UINT32                                             Reserved_5_4:2 ; ///<
+    UINT32                                       FuseProcDllIrefAdj:3 ; ///<
+    UINT32                                            Reserved_10_9:2 ; ///<
+    UINT32                                   FuseProcDllProcessComp:3 ; ///<
+    UINT32                                           Reserved_15_14:1 ; ///<
+    UINT32                                   FuseProcDllRCFilterCtl:1 ; ///<
+    UINT32                                           Reserved_18_17:2 ; ///<
+    UINT32                                      FuseProcEiDetThresh:2 ; ///<
+    UINT32                                           Reserved_22_21:2 ; ///<
+    UINT32                                          FuseProcRxSpare:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_4011_STRUCT;
+
+// **** D0F0xE4_PHY_500F Register Definition ****
+// Address
+#define D0F0xE4_PHY_500F_ADDRESS                               0x500F
+
+// Type
+#define D0F0xE4_PHY_500F_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_OFFSET        0
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_WIDTH         4
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex1_MASK          0xf
+#define D0F0xE4_PHY_500F_Reserved_6_4_OFFSET                   4
+#define D0F0xE4_PHY_500F_Reserved_6_4_WIDTH                    3
+#define D0F0xE4_PHY_500F_Reserved_6_4_MASK                     0x70
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_OFFSET        7
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_WIDTH         4
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlIndex2_MASK          0x780
+#define D0F0xE4_PHY_500F_Reserved_11_11_OFFSET                 11
+#define D0F0xE4_PHY_500F_Reserved_11_11_WIDTH                  1
+#define D0F0xE4_PHY_500F_Reserved_11_11_MASK                   0x800
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_OFFSET      12
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_WIDTH       1
+#define D0F0xE4_PHY_500F_DllProcessFreqCtlOverride_MASK        0x1000
+#define D0F0xE4_PHY_500F_Reserved_13_13_OFFSET                 13
+#define D0F0xE4_PHY_500F_Reserved_13_13_WIDTH                  1
+#define D0F0xE4_PHY_500F_Reserved_13_13_MASK                   0x2000
+
+/// D0F0xE4_PHY_500F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                  DllProcessFreqCtlIndex1:4 ; ///<
+    UINT32                                             Reserved_6_4:3 ; ///<
+    UINT32                                  DllProcessFreqCtlIndex2:4 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                DllProcessFreqCtlOverride:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32  :4 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :2 ; ///<
+    UINT32  :1 ; ///<
+    UINT32  :1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_500F_STRUCT;
+
+// **** D0F0xE4_PHY_6005 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6005_ADDRESS                                0x6005
+
+// Type
+#define D0F0xE4_PHY_6005_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET                   0
+#define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH                    29
+#define D0F0xE4_PHY_6005_Reserved_28_0_MASK                     0x1fffffff
+#define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET                       29
+#define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH                        1
+#define D0F0xE4_PHY_6005_IsOwnMstr_MASK                         0x20000000
+#define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET                  30
+#define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH                   1
+#define D0F0xE4_PHY_6005_Reserved_30_30_MASK                    0x40000000
+#define D0F0xE4_PHY_6005_GangedModeEn_OFFSET                    31
+#define D0F0xE4_PHY_6005_GangedModeEn_WIDTH                     1
+#define D0F0xE4_PHY_6005_GangedModeEn_MASK                      0x80000000
+
+/// D0F0xE4_PHY_6005
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_28_0:29; ///<
+    UINT32                                                IsOwnMstr:1 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                             GangedModeEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6005_STRUCT;
+
+// **** D0F0xE4_PHY_6006 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6006_ADDRESS                                0x6006
+
+// Type
+#define D0F0xE4_PHY_6006_TYPE                                   TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6006_TxMarginNom_OFFSET                     0
+#define D0F0xE4_PHY_6006_TxMarginNom_WIDTH                      8
+#define D0F0xE4_PHY_6006_TxMarginNom_MASK                       0xff
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET                   8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH                    8
+#define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK                     0xff00
+#define D0F0xE4_PHY_6006_Reserved_31_16_OFFSET                  16
+#define D0F0xE4_PHY_6006_Reserved_31_16_WIDTH                   16
+#define D0F0xE4_PHY_6006_Reserved_31_16_MASK                    0xffff0000
+
+/// D0F0xE4_PHY_6006
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              TxMarginNom:8 ; ///<
+    UINT32                                            DeemphGen1Nom:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_PHY_6006_STRUCT;
+
+// **** D0F2xF4_x00 Register Definition ****
+// Address
+#define D0F2xF4_x00_ADDRESS                                     0x0
+
+// Type
+#define D0F2xF4_x00_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x00_L2PerfEvent0_OFFSET                         0
+#define D0F2xF4_x00_L2PerfEvent0_WIDTH                          8
+#define D0F2xF4_x00_L2PerfEvent0_MASK                           0xff
+#define D0F2xF4_x00_L2PerfEvent1_OFFSET                         8
+#define D0F2xF4_x00_L2PerfEvent1_WIDTH                          8
+#define D0F2xF4_x00_L2PerfEvent1_MASK                           0xff00
+#define D0F2xF4_x00_L2PerfCountUpper0_OFFSET                    16
+#define D0F2xF4_x00_L2PerfCountUpper0_WIDTH                     8
+#define D0F2xF4_x00_L2PerfCountUpper0_MASK                      0xff0000
+#define D0F2xF4_x00_L2PerfCountUpper1_OFFSET                    24
+#define D0F2xF4_x00_L2PerfCountUpper1_WIDTH                     8
+#define D0F2xF4_x00_L2PerfCountUpper1_MASK                      0xff000000
+
+/// D0F2xF4_x00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent0:8 ; ///<
+    UINT32                                             L2PerfEvent1:8 ; ///<
+    UINT32                                        L2PerfCountUpper0:8 ; ///<
+    UINT32                                        L2PerfCountUpper1:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x00_STRUCT;
+
+// **** D0F2xF4_x01 Register Definition ****
+// Address
+#define D0F2xF4_x01_ADDRESS                                     0x1
+
+// Type
+#define D0F2xF4_x01_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x01_L2PerfCount0_OFFSET                         0
+#define D0F2xF4_x01_L2PerfCount0_WIDTH                          32
+#define D0F2xF4_x01_L2PerfCount0_MASK                           0xffffffff
+
+/// D0F2xF4_x01
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x01_STRUCT;
+
+// **** D0F2xF4_x02 Register Definition ****
+// Address
+#define D0F2xF4_x02_ADDRESS                                     0x2
+
+// Type
+#define D0F2xF4_x02_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x02_L2PerfCount1_OFFSET                         0
+#define D0F2xF4_x02_L2PerfCount1_WIDTH                          32
+#define D0F2xF4_x02_L2PerfCount1_MASK                           0xffffffff
+
+/// D0F2xF4_x02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x02_STRUCT;
+
+// **** D0F2xF4_x03 Register Definition ****
+// Address
+#define D0F2xF4_x03_ADDRESS                                     0x3
+
+// Type
+#define D0F2xF4_x03_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x03_L2PerfEvent2_OFFSET                         0
+#define D0F2xF4_x03_L2PerfEvent2_WIDTH                          8
+#define D0F2xF4_x03_L2PerfEvent2_MASK                           0xff
+#define D0F2xF4_x03_L2PerfEvent3_OFFSET                         8
+#define D0F2xF4_x03_L2PerfEvent3_WIDTH                          8
+#define D0F2xF4_x03_L2PerfEvent3_MASK                           0xff00
+#define D0F2xF4_x03_L2PerfCountUpper2_OFFSET                    16
+#define D0F2xF4_x03_L2PerfCountUpper2_WIDTH                     8
+#define D0F2xF4_x03_L2PerfCountUpper2_MASK                      0xff0000
+#define D0F2xF4_x03_L2PerfCountUpper3_OFFSET                    24
+#define D0F2xF4_x03_L2PerfCountUpper3_WIDTH                     8
+#define D0F2xF4_x03_L2PerfCountUpper3_MASK                      0xff000000
+
+/// D0F2xF4_x03
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent2:8 ; ///<
+    UINT32                                             L2PerfEvent3:8 ; ///<
+    UINT32                                        L2PerfCountUpper2:8 ; ///<
+    UINT32                                        L2PerfCountUpper3:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x03_STRUCT;
+
+// **** D0F2xF4_x04 Register Definition ****
+// Address
+#define D0F2xF4_x04_ADDRESS                                     0x4
+
+// Type
+#define D0F2xF4_x04_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x04_L2PerfCount2_OFFSET                         0
+#define D0F2xF4_x04_L2PerfCount2_WIDTH                          32
+#define D0F2xF4_x04_L2PerfCount2_MASK                           0xffffffff
+
+/// D0F2xF4_x04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount2:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x04_STRUCT;
+
+// **** D0F2xF4_x05 Register Definition ****
+// Address
+#define D0F2xF4_x05_ADDRESS                                     0x5
+
+// Type
+#define D0F2xF4_x05_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x05_L2PerfCount3_OFFSET                         0
+#define D0F2xF4_x05_L2PerfCount3_WIDTH                          32
+#define D0F2xF4_x05_L2PerfCount3_MASK                           0xffffffff
+
+/// D0F2xF4_x05
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount3:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x05_STRUCT;
+
+// **** D0F2xF4_x06 Register Definition ****
+// Address
+#define D0F2xF4_x06_ADDRESS                                     0x6
+
+// Type
+#define D0F2xF4_x06_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x06_L2DEBUG0_OFFSET                             0
+#define D0F2xF4_x06_L2DEBUG0_WIDTH                              32
+#define D0F2xF4_x06_L2DEBUG0_MASK                               0xffffffff
+
+/// D0F2xF4_x06
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L2DEBUG0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x06_STRUCT;
+
+// **** D0F2xF4_x07 Register Definition ****
+// Address
+#define D0F2xF4_x07_ADDRESS                                     0x7
+
+// Type
+#define D0F2xF4_x07_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x07_L2DEBUG1_OFFSET                             0
+#define D0F2xF4_x07_L2DEBUG1_WIDTH                              32
+#define D0F2xF4_x07_L2DEBUG1_MASK                               0xffffffff
+
+/// D0F2xF4_x07
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L2DEBUG1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x07_STRUCT;
+
+// **** D0F2xF4_x08 Register Definition ****
+// Address
+#define D0F2xF4_x08_ADDRESS                                     0x8
+
+// Type
+#define D0F2xF4_x08_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x08_L2STATUS0_OFFSET                            0
+#define D0F2xF4_x08_L2STATUS0_WIDTH                             32
+#define D0F2xF4_x08_L2STATUS0_MASK                              0xffffffff
+
+/// D0F2xF4_x08
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L2STATUS0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x08_STRUCT;
+
+// **** D0F2xF4_x0C Register Definition ****
+// Address
+#define D0F2xF4_x0C_ADDRESS                                     0xc
+
+// Type
+#define D0F2xF4_x0C_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x0C_PTCAddrTransReqCheck_OFFSET                 0
+#define D0F2xF4_x0C_PTCAddrTransReqCheck_WIDTH                  1
+#define D0F2xF4_x0C_PTCAddrTransReqCheck_MASK                   0x1
+#define D0F2xF4_x0C_AllowL1CacheVZero_OFFSET                    1
+#define D0F2xF4_x0C_AllowL1CacheVZero_WIDTH                     1
+#define D0F2xF4_x0C_AllowL1CacheVZero_MASK                      0x2
+#define D0F2xF4_x0C_AllowL1CacheATSRsp_OFFSET                   2
+#define D0F2xF4_x0C_AllowL1CacheATSRsp_WIDTH                    1
+#define D0F2xF4_x0C_AllowL1CacheATSRsp_MASK                     0x4
+#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_OFFSET                  3
+#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_WIDTH                   1
+#define D0F2xF4_x0C_DTCHitVZeroOrIVZero_MASK                    0x8
+#define D0F2xF4_x0C_IFifoTWCredits_OFFSET                       4
+#define D0F2xF4_x0C_IFifoTWCredits_WIDTH                        6
+#define D0F2xF4_x0C_IFifoTWCredits_MASK                         0x3f0
+#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_OFFSET                 10
+#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_WIDTH                  1
+#define D0F2xF4_x0C_SIDEPTEOnUntransExcl_MASK                   0x400
+#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_OFFSET               11
+#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_WIDTH                1
+#define D0F2xF4_x0C_SIDEPTEOnAddrTransExcl_MASK                 0x800
+#define D0F2xF4_x0C_IFifoCMBCredits_OFFSET                      12
+#define D0F2xF4_x0C_IFifoCMBCredits_WIDTH                       6
+#define D0F2xF4_x0C_IFifoCMBCredits_MASK                        0x3f000
+#define D0F2xF4_x0C_FLTCMBPriority_OFFSET                       18
+#define D0F2xF4_x0C_FLTCMBPriority_WIDTH                        1
+#define D0F2xF4_x0C_FLTCMBPriority_MASK                         0x40000
+#define D0F2xF4_x0C_Reserved_19_19_OFFSET                       19
+#define D0F2xF4_x0C_Reserved_19_19_WIDTH                        1
+#define D0F2xF4_x0C_Reserved_19_19_MASK                         0x80000
+#define D0F2xF4_x0C_IFifoBurstLength_OFFSET                     20
+#define D0F2xF4_x0C_IFifoBurstLength_WIDTH                      4
+#define D0F2xF4_x0C_IFifoBurstLength_MASK                       0xf00000
+#define D0F2xF4_x0C_IFifoClientPriority_OFFSET                  24
+#define D0F2xF4_x0C_IFifoClientPriority_WIDTH                   8
+#define D0F2xF4_x0C_IFifoClientPriority_MASK                    0xff000000
+
+/// D0F2xF4_x0C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     PTCAddrTransReqCheck:1 ; ///<
+    UINT32                                        AllowL1CacheVZero:1 ; ///<
+    UINT32                                       AllowL1CacheATSRsp:1 ; ///<
+    UINT32                                      DTCHitVZeroOrIVZero:1 ; ///<
+    UINT32                                           IFifoTWCredits:6 ; ///<
+    UINT32                                     SIDEPTEOnUntransExcl:1 ; ///<
+    UINT32                                   SIDEPTEOnAddrTransExcl:1 ; ///<
+    UINT32                                          IFifoCMBCredits:6 ; ///<
+    UINT32                                           FLTCMBPriority:1 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                         IFifoBurstLength:4 ; ///<
+    UINT32                                      IFifoClientPriority:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x0C_STRUCT;
+
+// **** D0F2xF4_x0D Register Definition ****
+// Address
+#define D0F2xF4_x0D_ADDRESS                                     0xd
+
+// Type
+#define D0F2xF4_x0D_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x0D_SeqInvBurstLimitInv_OFFSET                  0
+#define D0F2xF4_x0D_SeqInvBurstLimitInv_WIDTH                   8
+#define D0F2xF4_x0D_SeqInvBurstLimitInv_MASK                    0xff
+#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_OFFSET                8
+#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_WIDTH                 8
+#define D0F2xF4_x0D_SeqInvBurstLimitL2Req_MASK                  0xff00
+#define D0F2xF4_x0D_SeqInvBurstLimitEn_OFFSET                   16
+#define D0F2xF4_x0D_SeqInvBurstLimitEn_WIDTH                    1
+#define D0F2xF4_x0D_SeqInvBurstLimitEn_MASK                     0x10000
+#define D0F2xF4_x0D_Reserved_23_17_OFFSET                       17
+#define D0F2xF4_x0D_Reserved_23_17_WIDTH                        7
+#define D0F2xF4_x0D_Reserved_23_17_MASK                         0xfe0000
+#define D0F2xF4_x0D_PerfThreshold_OFFSET                        24
+#define D0F2xF4_x0D_PerfThreshold_WIDTH                         8
+#define D0F2xF4_x0D_PerfThreshold_MASK                          0xff000000
+
+/// D0F2xF4_x0D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      SeqInvBurstLimitInv:8 ; ///<
+    UINT32                                    SeqInvBurstLimitL2Req:8 ; ///<
+    UINT32                                       SeqInvBurstLimitEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                            PerfThreshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x0D_STRUCT;
+
+// **** D0F2xF4_x10 Register Definition ****
+// Address
+#define D0F2xF4_x10_ADDRESS                                     0x10
+
+// Type
+#define D0F2xF4_x10_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x10_DTCReplacementSel_OFFSET                    0
+#define D0F2xF4_x10_DTCReplacementSel_WIDTH                     2
+#define D0F2xF4_x10_DTCReplacementSel_MASK                      0x3
+#define D0F2xF4_x10_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x10_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x10_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x10_DTCLRUUpdatePri_OFFSET                      3
+#define D0F2xF4_x10_DTCLRUUpdatePri_WIDTH                       1
+#define D0F2xF4_x10_DTCLRUUpdatePri_MASK                        0x8
+#define D0F2xF4_x10_DTCParityEn_OFFSET                          4
+#define D0F2xF4_x10_DTCParityEn_WIDTH                           1
+#define D0F2xF4_x10_DTCParityEn_MASK                            0x10
+#define D0F2xF4_x10_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x10_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x10_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x10_DTCInvalidationSel_OFFSET                   8
+#define D0F2xF4_x10_DTCInvalidationSel_WIDTH                    2
+#define D0F2xF4_x10_DTCInvalidationSel_MASK                     0x300
+#define D0F2xF4_x10_DTCSoftInvalidate_OFFSET                    10
+#define D0F2xF4_x10_DTCSoftInvalidate_WIDTH                     1
+#define D0F2xF4_x10_DTCSoftInvalidate_MASK                      0x400
+#define D0F2xF4_x10_Reserved_12_11_OFFSET                       11
+#define D0F2xF4_x10_Reserved_12_11_WIDTH                        2
+#define D0F2xF4_x10_Reserved_12_11_MASK                         0x1800
+#define D0F2xF4_x10_DTCBypass_OFFSET                            13
+#define D0F2xF4_x10_DTCBypass_WIDTH                             1
+#define D0F2xF4_x10_DTCBypass_MASK                              0x2000
+#define D0F2xF4_x10_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x10_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x10_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x10_DTCParitySupport_OFFSET                     15
+#define D0F2xF4_x10_DTCParitySupport_WIDTH                      1
+#define D0F2xF4_x10_DTCParitySupport_MASK                       0x8000
+#define D0F2xF4_x10_DTCWays_OFFSET                              16
+#define D0F2xF4_x10_DTCWays_WIDTH                               8
+#define D0F2xF4_x10_DTCWays_MASK                                0xff0000
+#define D0F2xF4_x10_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x10_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x10_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x10_DTCEntries_OFFSET                           28
+#define D0F2xF4_x10_DTCEntries_WIDTH                            4
+#define D0F2xF4_x10_DTCEntries_MASK                             0xf0000000
+
+/// D0F2xF4_x10
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DTCReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          DTCLRUUpdatePri:1 ; ///<
+    UINT32                                              DTCParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                       DTCInvalidationSel:2 ; ///<
+    UINT32                                        DTCSoftInvalidate:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                DTCBypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                         DTCParitySupport:1 ; ///<
+    UINT32                                                  DTCWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                               DTCEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x10_STRUCT;
+
+// **** D0F2xF4_x11 Register Definition ****
+// Address
+#define D0F2xF4_x11_ADDRESS                                     0x11
+
+// Type
+#define D0F2xF4_x11_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x11_DTCFuncBits_OFFSET                          0
+#define D0F2xF4_x11_DTCFuncBits_WIDTH                           2
+#define D0F2xF4_x11_DTCFuncBits_MASK                            0x3
+#define D0F2xF4_x11_DTCDevBits_OFFSET                           2
+#define D0F2xF4_x11_DTCDevBits_WIDTH                            3
+#define D0F2xF4_x11_DTCDevBits_MASK                             0x1c
+#define D0F2xF4_x11_DTCBusBits_OFFSET                           5
+#define D0F2xF4_x11_DTCBusBits_WIDTH                            4
+#define D0F2xF4_x11_DTCBusBits_MASK                             0x1e0
+#define D0F2xF4_x11_Reserved_9_9_OFFSET                         9
+#define D0F2xF4_x11_Reserved_9_9_WIDTH                          1
+#define D0F2xF4_x11_Reserved_9_9_MASK                           0x200
+#define D0F2xF4_x11_DtcAltHashEn_OFFSET                         10
+#define D0F2xF4_x11_DtcAltHashEn_WIDTH                          1
+#define D0F2xF4_x11_DtcAltHashEn_MASK                           0x400
+#define D0F2xF4_x11_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x11_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x11_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x11_DtcAddressMask_OFFSET                       16
+#define D0F2xF4_x11_DtcAddressMask_WIDTH                        16
+#define D0F2xF4_x11_DtcAddressMask_MASK                         0xffff0000
+
+/// D0F2xF4_x11
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              DTCFuncBits:2 ; ///<
+    UINT32                                               DTCDevBits:3 ; ///<
+    UINT32                                               DTCBusBits:4 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             DtcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           DtcAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x11_STRUCT;
+
+// **** D0F2xF4_x12 Register Definition ****
+// Address
+#define D0F2xF4_x12_ADDRESS                                     0x12
+
+// Type
+#define D0F2xF4_x12_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x12_DTCWayDisable_OFFSET                        0
+#define D0F2xF4_x12_DTCWayDisable_WIDTH                         16
+#define D0F2xF4_x12_DTCWayDisable_MASK                          0xffff
+#define D0F2xF4_x12_DTCWayAccessDisable_OFFSET                  16
+#define D0F2xF4_x12_DTCWayAccessDisable_WIDTH                   16
+#define D0F2xF4_x12_DTCWayAccessDisable_MASK                    0xffff0000
+
+/// D0F2xF4_x12
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DTCWayDisable:16; ///<
+    UINT32                                      DTCWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x12_STRUCT;
+
+// **** D0F2xF4_x14 Register Definition ****
+// Address
+#define D0F2xF4_x14_ADDRESS                                     0x14
+
+// Type
+#define D0F2xF4_x14_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x14_ITCReplacementSel_OFFSET                    0
+#define D0F2xF4_x14_ITCReplacementSel_WIDTH                     2
+#define D0F2xF4_x14_ITCReplacementSel_MASK                      0x3
+#define D0F2xF4_x14_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x14_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x14_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x14_ITCLRUUpdatePri_OFFSET                      3
+#define D0F2xF4_x14_ITCLRUUpdatePri_WIDTH                       1
+#define D0F2xF4_x14_ITCLRUUpdatePri_MASK                        0x8
+#define D0F2xF4_x14_ITCParityEn_OFFSET                          4
+#define D0F2xF4_x14_ITCParityEn_WIDTH                           1
+#define D0F2xF4_x14_ITCParityEn_MASK                            0x10
+#define D0F2xF4_x14_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x14_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x14_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x14_ITCInvalidationSel_OFFSET                   8
+#define D0F2xF4_x14_ITCInvalidationSel_WIDTH                    2
+#define D0F2xF4_x14_ITCInvalidationSel_MASK                     0x300
+#define D0F2xF4_x14_ITCSoftInvalidate_OFFSET                    10
+#define D0F2xF4_x14_ITCSoftInvalidate_WIDTH                     1
+#define D0F2xF4_x14_ITCSoftInvalidate_MASK                      0x400
+#define D0F2xF4_x14_Reserved_12_11_OFFSET                       11
+#define D0F2xF4_x14_Reserved_12_11_WIDTH                        2
+#define D0F2xF4_x14_Reserved_12_11_MASK                         0x1800
+#define D0F2xF4_x14_ITCBypass_OFFSET                            13
+#define D0F2xF4_x14_ITCBypass_WIDTH                             1
+#define D0F2xF4_x14_ITCBypass_MASK                              0x2000
+#define D0F2xF4_x14_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x14_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x14_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x14_ITCParitySupport_OFFSET                     15
+#define D0F2xF4_x14_ITCParitySupport_WIDTH                      1
+#define D0F2xF4_x14_ITCParitySupport_MASK                       0x8000
+#define D0F2xF4_x14_ITCWays_OFFSET                              16
+#define D0F2xF4_x14_ITCWays_WIDTH                               8
+#define D0F2xF4_x14_ITCWays_MASK                                0xff0000
+#define D0F2xF4_x14_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x14_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x14_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x14_ITCEntries_OFFSET                           28
+#define D0F2xF4_x14_ITCEntries_WIDTH                            4
+#define D0F2xF4_x14_ITCEntries_MASK                             0xf0000000
+
+/// D0F2xF4_x14
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        ITCReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          ITCLRUUpdatePri:1 ; ///<
+    UINT32                                              ITCParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                       ITCInvalidationSel:2 ; ///<
+    UINT32                                        ITCSoftInvalidate:1 ; ///<
+    UINT32                                           Reserved_12_11:2 ; ///<
+    UINT32                                                ITCBypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                         ITCParitySupport:1 ; ///<
+    UINT32                                                  ITCWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                               ITCEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x14_STRUCT;
+
+// **** D0F2xF4_x15 Register Definition ****
+// Address
+#define D0F2xF4_x15_ADDRESS                                     0x15
+
+// Type
+#define D0F2xF4_x15_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x15_ITCFuncBits_OFFSET                          0
+#define D0F2xF4_x15_ITCFuncBits_WIDTH                           2
+#define D0F2xF4_x15_ITCFuncBits_MASK                            0x3
+#define D0F2xF4_x15_ITCDevBits_OFFSET                           2
+#define D0F2xF4_x15_ITCDevBits_WIDTH                            3
+#define D0F2xF4_x15_ITCDevBits_MASK                             0x1c
+#define D0F2xF4_x15_ITCBusBits_OFFSET                           5
+#define D0F2xF4_x15_ITCBusBits_WIDTH                            4
+#define D0F2xF4_x15_ITCBusBits_MASK                             0x1e0
+#define D0F2xF4_x15_Reserved_9_9_OFFSET                         9
+#define D0F2xF4_x15_Reserved_9_9_WIDTH                          1
+#define D0F2xF4_x15_Reserved_9_9_MASK                           0x200
+#define D0F2xF4_x15_ItcAltHashEn_OFFSET                         10
+#define D0F2xF4_x15_ItcAltHashEn_WIDTH                          1
+#define D0F2xF4_x15_ItcAltHashEn_MASK                           0x400
+#define D0F2xF4_x15_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x15_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x15_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x15_ITCAddressMask_OFFSET                       16
+#define D0F2xF4_x15_ITCAddressMask_WIDTH                        16
+#define D0F2xF4_x15_ITCAddressMask_MASK                         0xffff0000
+
+/// D0F2xF4_x15
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              ITCFuncBits:2 ; ///<
+    UINT32                                               ITCDevBits:3 ; ///<
+    UINT32                                               ITCBusBits:4 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             ItcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           ITCAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x15_STRUCT;
+
+// **** D0F2xF4_x16 Register Definition ****
+// Address
+#define D0F2xF4_x16_ADDRESS                                     0x16
+
+// Type
+#define D0F2xF4_x16_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x16_ITCWayDisable_OFFSET                        0
+#define D0F2xF4_x16_ITCWayDisable_WIDTH                         16
+#define D0F2xF4_x16_ITCWayDisable_MASK                          0xffff
+#define D0F2xF4_x16_ITCWayAccessDisable_OFFSET                  16
+#define D0F2xF4_x16_ITCWayAccessDisable_WIDTH                   16
+#define D0F2xF4_x16_ITCWayAccessDisable_MASK                    0xffff0000
+
+/// D0F2xF4_x16
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            ITCWayDisable:16; ///<
+    UINT32                                      ITCWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x16_STRUCT;
+
+// **** D0F2xF4_x18 Register Definition ****
+// Address
+#define D0F2xF4_x18_ADDRESS                                     0x18
+
+// Type
+#define D0F2xF4_x18_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x18_PTCAReplacementSel_OFFSET                   0
+#define D0F2xF4_x18_PTCAReplacementSel_WIDTH                    2
+#define D0F2xF4_x18_PTCAReplacementSel_MASK                     0x3
+#define D0F2xF4_x18_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x18_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x18_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x18_PTCALRUUpdatePri_OFFSET                     3
+#define D0F2xF4_x18_PTCALRUUpdatePri_WIDTH                      1
+#define D0F2xF4_x18_PTCALRUUpdatePri_MASK                       0x8
+#define D0F2xF4_x18_PTCAParityEn_OFFSET                         4
+#define D0F2xF4_x18_PTCAParityEn_WIDTH                          1
+#define D0F2xF4_x18_PTCAParityEn_MASK                           0x10
+#define D0F2xF4_x18_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x18_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x18_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x18_PTCAInvalidationSel_OFFSET                  8
+#define D0F2xF4_x18_PTCAInvalidationSel_WIDTH                   2
+#define D0F2xF4_x18_PTCAInvalidationSel_MASK                    0x300
+#define D0F2xF4_x18_PTCASoftInvalidate_OFFSET                   10
+#define D0F2xF4_x18_PTCASoftInvalidate_WIDTH                    1
+#define D0F2xF4_x18_PTCASoftInvalidate_MASK                     0x400
+#define D0F2xF4_x18_PTCA2MMode_OFFSET                           11
+#define D0F2xF4_x18_PTCA2MMode_WIDTH                            1
+#define D0F2xF4_x18_PTCA2MMode_MASK                             0x800
+#define D0F2xF4_x18_Reserved_12_12_OFFSET                       12
+#define D0F2xF4_x18_Reserved_12_12_WIDTH                        1
+#define D0F2xF4_x18_Reserved_12_12_MASK                         0x1000
+#define D0F2xF4_x18_PTCABypass_OFFSET                           13
+#define D0F2xF4_x18_PTCABypass_WIDTH                            1
+#define D0F2xF4_x18_PTCABypass_MASK                             0x2000
+#define D0F2xF4_x18_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x18_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x18_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x18_PTCAParitySupport_OFFSET                    15
+#define D0F2xF4_x18_PTCAParitySupport_WIDTH                     1
+#define D0F2xF4_x18_PTCAParitySupport_MASK                      0x8000
+#define D0F2xF4_x18_PTCAWays_OFFSET                             16
+#define D0F2xF4_x18_PTCAWays_WIDTH                              8
+#define D0F2xF4_x18_PTCAWays_MASK                               0xff0000
+#define D0F2xF4_x18_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x18_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x18_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x18_PTCAEntries_OFFSET                          28
+#define D0F2xF4_x18_PTCAEntries_WIDTH                           4
+#define D0F2xF4_x18_PTCAEntries_MASK                            0xf0000000
+
+/// D0F2xF4_x18
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       PTCAReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                         PTCALRUUpdatePri:1 ; ///<
+    UINT32                                             PTCAParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                      PTCAInvalidationSel:2 ; ///<
+    UINT32                                       PTCASoftInvalidate:1 ; ///<
+    UINT32                                               PTCA2MMode:1 ; ///<
+    UINT32                                           Reserved_12_12:1 ; ///<
+    UINT32                                               PTCABypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                        PTCAParitySupport:1 ; ///<
+    UINT32                                                 PTCAWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                              PTCAEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x18_STRUCT;
+
+// **** D0F2xF4_x19 Register Definition ****
+// Address
+#define D0F2xF4_x19_ADDRESS                                     0x19
+
+// Type
+#define D0F2xF4_x19_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x19_PTCAFuncBits_OFFSET                         0
+#define D0F2xF4_x19_PTCAFuncBits_WIDTH                          2
+#define D0F2xF4_x19_PTCAFuncBits_MASK                           0x3
+#define D0F2xF4_x19_PTCADevBits_OFFSET                          2
+#define D0F2xF4_x19_PTCADevBits_WIDTH                           3
+#define D0F2xF4_x19_PTCADevBits_MASK                            0x1c
+#define D0F2xF4_x19_PTCABusBits_OFFSET                          5
+#define D0F2xF4_x19_PTCABusBits_WIDTH                           4
+#define D0F2xF4_x19_PTCABusBits_MASK                            0x1e0
+#define D0F2xF4_x19_Reserved_9_9_OFFSET                         9
+#define D0F2xF4_x19_Reserved_9_9_WIDTH                          1
+#define D0F2xF4_x19_Reserved_9_9_MASK                           0x200
+#define D0F2xF4_x19_PtcAltHashEn_OFFSET                         10
+#define D0F2xF4_x19_PtcAltHashEn_WIDTH                          1
+#define D0F2xF4_x19_PtcAltHashEn_MASK                           0x400
+#define D0F2xF4_x19_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x19_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x19_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x19_PTCAAddressMask_OFFSET                      16
+#define D0F2xF4_x19_PTCAAddressMask_WIDTH                       16
+#define D0F2xF4_x19_PTCAAddressMask_MASK                        0xffff0000
+
+/// D0F2xF4_x19
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PTCAFuncBits:2 ; ///<
+    UINT32                                              PTCADevBits:3 ; ///<
+    UINT32                                              PTCABusBits:4 ; ///<
+    UINT32                                             Reserved_9_9:1 ; ///<
+    UINT32                                             PtcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                          PTCAAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x19_STRUCT;
+
+// **** D0F2xF4_x1A Register Definition ****
+// Address
+#define D0F2xF4_x1A_ADDRESS                                     0x1a
+
+// Type
+#define D0F2xF4_x1A_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x1A_PTCAWayDisable_OFFSET                       0
+#define D0F2xF4_x1A_PTCAWayDisable_WIDTH                        16
+#define D0F2xF4_x1A_PTCAWayDisable_MASK                         0xffff
+#define D0F2xF4_x1A_PTCAWayAccessDisable_OFFSET                 16
+#define D0F2xF4_x1A_PTCAWayAccessDisable_WIDTH                  16
+#define D0F2xF4_x1A_PTCAWayAccessDisable_MASK                   0xffff0000
+
+/// D0F2xF4_x1A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           PTCAWayDisable:16; ///<
+    UINT32                                     PTCAWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x1A_STRUCT;
+
+// **** D0F2xF4_x20 Register Definition ****
+// Address
+#define D0F2xF4_x20_ADDRESS                                     0x20
+
+// Type
+#define D0F2xF4_x20_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x20_QUEUECredits_OFFSET                         0
+#define D0F2xF4_x20_QUEUECredits_WIDTH                          6
+#define D0F2xF4_x20_QUEUECredits_MASK                           0x3f
+#define D0F2xF4_x20_Reserved_6_6_OFFSET                         6
+#define D0F2xF4_x20_Reserved_6_6_WIDTH                          1
+#define D0F2xF4_x20_Reserved_6_6_MASK                           0x40
+#define D0F2xF4_x20_QUEUEOverride_OFFSET                        7
+#define D0F2xF4_x20_QUEUEOverride_WIDTH                         1
+#define D0F2xF4_x20_QUEUEOverride_MASK                          0x80
+#define D0F2xF4_x20_FLTCMBCredits_OFFSET                        8
+#define D0F2xF4_x20_FLTCMBCredits_WIDTH                         6
+#define D0F2xF4_x20_FLTCMBCredits_MASK                          0x3f00
+#define D0F2xF4_x20_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x20_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x20_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x20_FLTCMBOverride_OFFSET                       15
+#define D0F2xF4_x20_FLTCMBOverride_WIDTH                        1
+#define D0F2xF4_x20_FLTCMBOverride_MASK                         0x8000
+#define D0F2xF4_x20_FCELCredits_OFFSET                          16
+#define D0F2xF4_x20_FCELCredits_WIDTH                           6
+#define D0F2xF4_x20_FCELCredits_MASK                            0x3f0000
+#define D0F2xF4_x20_Reserved_22_22_OFFSET                       22
+#define D0F2xF4_x20_Reserved_22_22_WIDTH                        1
+#define D0F2xF4_x20_Reserved_22_22_MASK                         0x400000
+#define D0F2xF4_x20_FCELOverride_OFFSET                         23
+#define D0F2xF4_x20_FCELOverride_WIDTH                          1
+#define D0F2xF4_x20_FCELOverride_MASK                           0x800000
+#define D0F2xF4_x20_PprLoggerCredits_OFFSET                     24
+#define D0F2xF4_x20_PprLoggerCredits_WIDTH                      4
+#define D0F2xF4_x20_PprLoggerCredits_MASK                       0xf000000
+#define D0F2xF4_x20_Reserved_31_28_OFFSET                       28
+#define D0F2xF4_x20_Reserved_31_28_WIDTH                        4
+#define D0F2xF4_x20_Reserved_31_28_MASK                         0xf0000000
+
+/// D0F2xF4_x20
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             QUEUECredits:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                            QUEUEOverride:1 ; ///<
+    UINT32                                            FLTCMBCredits:6 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                           FLTCMBOverride:1 ; ///<
+    UINT32                                              FCELCredits:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                             FCELOverride:1 ; ///<
+    UINT32                                         PprLoggerCredits:4 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x20_STRUCT;
+
+// **** D0F2xF4_x22 Register Definition ****
+// Address
+#define D0F2xF4_x22_ADDRESS                                     0x22
+
+// Type
+#define D0F2xF4_x22_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x22_L2aUpdateFilterBypass_OFFSET                0
+#define D0F2xF4_x22_L2aUpdateFilterBypass_WIDTH                 1
+#define D0F2xF4_x22_L2aUpdateFilterBypass_MASK                  0x1
+#define D0F2xF4_x22_L2aUpdateFilterRdlatency_OFFSET             1
+#define D0F2xF4_x22_L2aUpdateFilterRdlatency_WIDTH              4
+#define D0F2xF4_x22_L2aUpdateFilterRdlatency_MASK               0x1e
+#define D0F2xF4_x22_Reserved_31_5_OFFSET                        5
+#define D0F2xF4_x22_Reserved_31_5_WIDTH                         27
+#define D0F2xF4_x22_Reserved_31_5_MASK                          0xffffffe0
+
+/// D0F2xF4_x22
+typedef union {
+  struct {                                                              ///<
+    UINT32                                    L2aUpdateFilterBypass:1 ; ///<
+    UINT32                                 L2aUpdateFilterRdlatency:4 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x22_STRUCT;
+
+
+
+
+
+
+
+// **** D0F2xF4_x30 Register Definition ****
+// Address
+#define D0F2xF4_x30_ADDRESS                                     0x30
+
+// Type
+#define D0F2xF4_x30_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x30_ERRRuleLock1_OFFSET                         0
+#define D0F2xF4_x30_ERRRuleLock1_WIDTH                          1
+#define D0F2xF4_x30_ERRRuleLock1_MASK                           0x1
+#define D0F2xF4_x30_Reserved_3_1_OFFSET                         1
+#define D0F2xF4_x30_Reserved_3_1_WIDTH                          3
+#define D0F2xF4_x30_Reserved_3_1_MASK                           0xe
+#define D0F2xF4_x30_ERRRuleDisable3_OFFSET                      4
+#define D0F2xF4_x30_ERRRuleDisable3_WIDTH                       28
+#define D0F2xF4_x30_ERRRuleDisable3_MASK                        0xfffffff0
+
+/// D0F2xF4_x30
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             ERRRuleLock1:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                          ERRRuleDisable3:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x30_STRUCT;
+
+// **** D0F2xF4_x31 Register Definition ****
+// Address
+#define D0F2xF4_x31_ADDRESS                                     0x31
+
+// Type
+#define D0F2xF4_x31_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x31_ERRRuleDisable4_OFFSET                      0
+#define D0F2xF4_x31_ERRRuleDisable4_WIDTH                       32
+#define D0F2xF4_x31_ERRRuleDisable4_MASK                        0xffffffff
+
+/// D0F2xF4_x31
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable4:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x31_STRUCT;
+
+// **** D0F2xF4_x32 Register Definition ****
+// Address
+#define D0F2xF4_x32_ADDRESS                                     0x32
+
+// Type
+#define D0F2xF4_x32_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x32_ERRRuleDisable5_OFFSET                      0
+#define D0F2xF4_x32_ERRRuleDisable5_WIDTH                       32
+#define D0F2xF4_x32_ERRRuleDisable5_MASK                        0xffffffff
+
+/// D0F2xF4_x32
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable5:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x32_STRUCT;
+
+// **** D0F2xF4_x33 Register Definition ****
+// Address
+#define D0F2xF4_x33_ADDRESS                                     0x33
+
+// Type
+#define D0F2xF4_x33_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x33_CKGateL2ARegsDisable_OFFSET                 0
+#define D0F2xF4_x33_CKGateL2ARegsDisable_WIDTH                  1
+#define D0F2xF4_x33_CKGateL2ARegsDisable_MASK                   0x1
+#define D0F2xF4_x33_CKGateL2ADynamicDisable_OFFSET              1
+#define D0F2xF4_x33_CKGateL2ADynamicDisable_WIDTH               1
+#define D0F2xF4_x33_CKGateL2ADynamicDisable_MASK                0x2
+#define D0F2xF4_x33_CKGateL2ACacheDisable_OFFSET                2
+#define D0F2xF4_x33_CKGateL2ACacheDisable_WIDTH                 1
+#define D0F2xF4_x33_CKGateL2ACacheDisable_MASK                  0x4
+#define D0F2xF4_x33_CKGateL2ASpare_OFFSET                       3
+#define D0F2xF4_x33_CKGateL2ASpare_WIDTH                        1
+#define D0F2xF4_x33_CKGateL2ASpare_MASK                         0x8
+#define D0F2xF4_x33_CKGateL2ALength_OFFSET                      4
+#define D0F2xF4_x33_CKGateL2ALength_WIDTH                       2
+#define D0F2xF4_x33_CKGateL2ALength_MASK                        0x30
+#define D0F2xF4_x33_CKGateL2AStop_OFFSET                        6
+#define D0F2xF4_x33_CKGateL2AStop_WIDTH                         2
+#define D0F2xF4_x33_CKGateL2AStop_MASK                          0xc0
+#define D0F2xF4_x33_Reserved_31_8_OFFSET                        8
+#define D0F2xF4_x33_Reserved_31_8_WIDTH                         24
+#define D0F2xF4_x33_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F2xF4_x33
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     CKGateL2ARegsDisable:1 ; ///<
+    UINT32                                  CKGateL2ADynamicDisable:1 ; ///<
+    UINT32                                    CKGateL2ACacheDisable:1 ; ///<
+    UINT32                                           CKGateL2ASpare:1 ; ///<
+    UINT32                                          CKGateL2ALength:2 ; ///<
+    UINT32                                            CKGateL2AStop:2 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x33_STRUCT;
+
+// **** D0F2xF4_x34 Register Definition ****
+// Address
+#define D0F2xF4_x34_ADDRESS                                     0x34
+
+// Type
+#define D0F2xF4_x34_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x34_L2aregGstPgsize_OFFSET                      0
+#define D0F2xF4_x34_L2aregGstPgsize_WIDTH                       2
+#define D0F2xF4_x34_L2aregGstPgsize_MASK                        0x3
+#define D0F2xF4_x34_L2aregHostPgsize_OFFSET                     2
+#define D0F2xF4_x34_L2aregHostPgsize_WIDTH                      2
+#define D0F2xF4_x34_L2aregHostPgsize_MASK                       0xc
+#define D0F2xF4_x34_Reserved_31_4_OFFSET                        4
+#define D0F2xF4_x34_Reserved_31_4_WIDTH                         28
+#define D0F2xF4_x34_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F2xF4_x34
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L2aregGstPgsize:2 ; ///<
+    UINT32                                         L2aregHostPgsize:2 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x34_STRUCT;
+
+// **** D0F2xF4_x40 Register Definition ****
+// Address
+#define D0F2xF4_x40_ADDRESS                                     0x40
+
+// Type
+#define D0F2xF4_x40_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x40_L2PerfEvent4_OFFSET                         0
+#define D0F2xF4_x40_L2PerfEvent4_WIDTH                          8
+#define D0F2xF4_x40_L2PerfEvent4_MASK                           0xff
+#define D0F2xF4_x40_L2PerfEvent5_OFFSET                         8
+#define D0F2xF4_x40_L2PerfEvent5_WIDTH                          8
+#define D0F2xF4_x40_L2PerfEvent5_MASK                           0xff00
+#define D0F2xF4_x40_L2PerfCountUpper4_OFFSET                    16
+#define D0F2xF4_x40_L2PerfCountUpper4_WIDTH                     8
+#define D0F2xF4_x40_L2PerfCountUpper4_MASK                      0xff0000
+#define D0F2xF4_x40_L2PerfCountUpper5_OFFSET                    24
+#define D0F2xF4_x40_L2PerfCountUpper5_WIDTH                     8
+#define D0F2xF4_x40_L2PerfCountUpper5_MASK                      0xff000000
+
+/// D0F2xF4_x40
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent4:8 ; ///<
+    UINT32                                             L2PerfEvent5:8 ; ///<
+    UINT32                                        L2PerfCountUpper4:8 ; ///<
+    UINT32                                        L2PerfCountUpper5:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x40_STRUCT;
+
+// **** D0F2xF4_x41 Register Definition ****
+// Address
+#define D0F2xF4_x41_ADDRESS                                     0x41
+
+// Type
+#define D0F2xF4_x41_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x41_L2PerfCount4_OFFSET                         0
+#define D0F2xF4_x41_L2PerfCount4_WIDTH                          32
+#define D0F2xF4_x41_L2PerfCount4_MASK                           0xffffffff
+
+/// D0F2xF4_x41
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount4:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x41_STRUCT;
+
+// **** D0F2xF4_x42 Register Definition ****
+// Address
+#define D0F2xF4_x42_ADDRESS                                     0x42
+
+// Type
+#define D0F2xF4_x42_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x42_L2PerfCount5_OFFSET                         0
+#define D0F2xF4_x42_L2PerfCount5_WIDTH                          32
+#define D0F2xF4_x42_L2PerfCount5_MASK                           0xffffffff
+
+/// D0F2xF4_x42
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount5:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x42_STRUCT;
+
+// **** D0F2xF4_x43 Register Definition ****
+// Address
+#define D0F2xF4_x43_ADDRESS                                     0x43
+
+// Type
+#define D0F2xF4_x43_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x43_L2PerfEvent6_OFFSET                         0
+#define D0F2xF4_x43_L2PerfEvent6_WIDTH                          8
+#define D0F2xF4_x43_L2PerfEvent6_MASK                           0xff
+#define D0F2xF4_x43_L2PerfEvent7_OFFSET                         8
+#define D0F2xF4_x43_L2PerfEvent7_WIDTH                          8
+#define D0F2xF4_x43_L2PerfEvent7_MASK                           0xff00
+#define D0F2xF4_x43_L2PerfCountUpper6_OFFSET                    16
+#define D0F2xF4_x43_L2PerfCountUpper6_WIDTH                     8
+#define D0F2xF4_x43_L2PerfCountUpper6_MASK                      0xff0000
+#define D0F2xF4_x43_L2PerfCountUpper7_OFFSET                    24
+#define D0F2xF4_x43_L2PerfCountUpper7_WIDTH                     8
+#define D0F2xF4_x43_L2PerfCountUpper7_MASK                      0xff000000
+
+/// D0F2xF4_x43
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfEvent6:8 ; ///<
+    UINT32                                             L2PerfEvent7:8 ; ///<
+    UINT32                                        L2PerfCountUpper6:8 ; ///<
+    UINT32                                        L2PerfCountUpper7:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x43_STRUCT;
+
+// **** D0F2xF4_x44 Register Definition ****
+// Address
+#define D0F2xF4_x44_ADDRESS                                     0x44
+
+// Type
+#define D0F2xF4_x44_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x44_L2PerfCount6_OFFSET                         0
+#define D0F2xF4_x44_L2PerfCount6_WIDTH                          32
+#define D0F2xF4_x44_L2PerfCount6_MASK                           0xffffffff
+
+/// D0F2xF4_x44
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount6:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x44_STRUCT;
+
+// **** D0F2xF4_x45 Register Definition ****
+// Address
+#define D0F2xF4_x45_ADDRESS                                     0x45
+
+// Type
+#define D0F2xF4_x45_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x45_L2PerfCount7_OFFSET                         0
+#define D0F2xF4_x45_L2PerfCount7_WIDTH                          32
+#define D0F2xF4_x45_L2PerfCount7_MASK                           0xffffffff
+
+/// D0F2xF4_x45
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L2PerfCount7:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x45_STRUCT;
+
+// **** D0F2xF4_x46 Register Definition ****
+// Address
+#define D0F2xF4_x46_ADDRESS                                     0x46
+
+// Type
+#define D0F2xF4_x46_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x46_L2DEBUG2_OFFSET                             0
+#define D0F2xF4_x46_L2DEBUG2_WIDTH                              32
+#define D0F2xF4_x46_L2DEBUG2_MASK                               0xffffffff
+
+/// D0F2xF4_x46
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L2DEBUG2:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x46_STRUCT;
+
+// **** D0F2xF4_x47 Register Definition ****
+// Address
+#define D0F2xF4_x47_ADDRESS                                     0x47
+
+// Type
+#define D0F2xF4_x47_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x47_Reserved_0_0_OFFSET                         0
+#define D0F2xF4_x47_Reserved_0_0_WIDTH                          1
+#define D0F2xF4_x47_Reserved_0_0_MASK                           0x1
+#define D0F2xF4_x47_TwNwEn_OFFSET                               1
+#define D0F2xF4_x47_TwNwEn_WIDTH                                1
+#define D0F2xF4_x47_TwNwEn_MASK                                 0x2
+#define D0F2xF4_x47_TwAtomicFilterEn_OFFSET                     2
+#define D0F2xF4_x47_TwAtomicFilterEn_WIDTH                      1
+#define D0F2xF4_x47_TwAtomicFilterEn_MASK                       0x4
+#define D0F2xF4_x47_Reserved_31_3_OFFSET                        3
+#define D0F2xF4_x47_Reserved_31_3_WIDTH                         29
+#define D0F2xF4_x47_Reserved_31_3_MASK                          0xfffffff8
+
+/// D0F2xF4_x47
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                   TwNwEn:1 ; ///<
+    UINT32                                         TwAtomicFilterEn:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x47_STRUCT;
+
+// **** D0F2xF4_x48 Register Definition ****
+// Address
+#define D0F2xF4_x48_ADDRESS                                     0x48
+
+// Type
+#define D0F2xF4_x48_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x48_L2STATUS1_OFFSET                            0
+#define D0F2xF4_x48_L2STATUS1_WIDTH                             32
+#define D0F2xF4_x48_L2STATUS1_MASK                              0xffffffff
+
+/// D0F2xF4_x48
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                L2STATUS1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x48_STRUCT;
+
+// **** D0F2xF4_x4C Register Definition ****
+// Address
+#define D0F2xF4_x4C_ADDRESS                                     0x4c
+
+// Type
+#define D0F2xF4_x4C_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x4C_QueueArbFBPri_OFFSET                        0
+#define D0F2xF4_x4C_QueueArbFBPri_WIDTH                         1
+#define D0F2xF4_x4C_QueueArbFBPri_MASK                          0x1
+#define D0F2xF4_x4C_PTCAddrTransReqUpdate_OFFSET                1
+#define D0F2xF4_x4C_PTCAddrTransReqUpdate_WIDTH                 1
+#define D0F2xF4_x4C_PTCAddrTransReqUpdate_MASK                  0x2
+#define D0F2xF4_x4C_FC1Dis_OFFSET                               2
+#define D0F2xF4_x4C_FC1Dis_WIDTH                                1
+#define D0F2xF4_x4C_FC1Dis_MASK                                 0x4
+#define D0F2xF4_x4C_DTCUpdateVOneIVZero_OFFSET                  3
+#define D0F2xF4_x4C_DTCUpdateVOneIVZero_WIDTH                   1
+#define D0F2xF4_x4C_DTCUpdateVOneIVZero_MASK                    0x8
+#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_OFFSET                  4
+#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_WIDTH                   1
+#define D0F2xF4_x4C_DTCUpdateVZeroIVOne_MASK                    0x10
+#define D0F2xF4_x4C_FC2Dis_OFFSET                               5
+#define D0F2xF4_x4C_FC2Dis_WIDTH                                1
+#define D0F2xF4_x4C_FC2Dis_MASK                                 0x20
+#define D0F2xF4_x4C_FC3Dis_OFFSET                               6
+#define D0F2xF4_x4C_FC3Dis_WIDTH                                1
+#define D0F2xF4_x4C_FC3Dis_MASK                                 0x40
+#define D0F2xF4_x4C_FC2AltMode_OFFSET                           7
+#define D0F2xF4_x4C_FC2AltMode_WIDTH                            1
+#define D0F2xF4_x4C_FC2AltMode_MASK                             0x80
+#define D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET                   8
+#define D0F2xF4_x4C_GstPartialPtcCntrl_WIDTH                    2
+#define D0F2xF4_x4C_GstPartialPtcCntrl_MASK                     0x300
+#define D0F2xF4_x4C_Reserved_31_10_OFFSET                       10
+#define D0F2xF4_x4C_Reserved_31_10_WIDTH                        22
+#define D0F2xF4_x4C_Reserved_31_10_MASK                         0xfffffc00
+
+/// D0F2xF4_x4C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            QueueArbFBPri:1 ; ///<
+    UINT32                                    PTCAddrTransReqUpdate:1 ; ///<
+    UINT32                                                   FC1Dis:1 ; ///<
+    UINT32                                      DTCUpdateVOneIVZero:1 ; ///<
+    UINT32                                      DTCUpdateVZeroIVOne:1 ; ///<
+    UINT32                                                   FC2Dis:1 ; ///<
+    UINT32                                                   FC3Dis:1 ; ///<
+    UINT32                                               FC2AltMode:1 ; ///<
+    UINT32                                       GstPartialPtcCntrl:2 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x4C_STRUCT;
+
+// **** D0F2xF4_x4D Register Definition ****
+// Address
+#define D0F2xF4_x4D_ADDRESS                                     0x4d
+
+// Type
+#define D0F2xF4_x4D_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x4D_SeqInvBurstLimitInv_OFFSET                  0
+#define D0F2xF4_x4D_SeqInvBurstLimitInv_WIDTH                   8
+#define D0F2xF4_x4D_SeqInvBurstLimitInv_MASK                    0xff
+#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_OFFSET               8
+#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_WIDTH                8
+#define D0F2xF4_x4D_SeqInvBurstLimitPDCReq_MASK                 0xff00
+#define D0F2xF4_x4D_SeqInvBurstLimitEn_OFFSET                   16
+#define D0F2xF4_x4D_SeqInvBurstLimitEn_WIDTH                    1
+#define D0F2xF4_x4D_SeqInvBurstLimitEn_MASK                     0x10000
+#define D0F2xF4_x4D_Reserved_23_17_OFFSET                       17
+#define D0F2xF4_x4D_Reserved_23_17_WIDTH                        7
+#define D0F2xF4_x4D_Reserved_23_17_MASK                         0xfe0000
+#define D0F2xF4_x4D_Perf2Threshold_OFFSET                       24
+#define D0F2xF4_x4D_Perf2Threshold_WIDTH                        8
+#define D0F2xF4_x4D_Perf2Threshold_MASK                         0xff000000
+
+/// D0F2xF4_x4D
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      SeqInvBurstLimitInv:8 ; ///<
+    UINT32                                   SeqInvBurstLimitPDCReq:8 ; ///<
+    UINT32                                       SeqInvBurstLimitEn:1 ; ///<
+    UINT32                                           Reserved_23_17:7 ; ///<
+    UINT32                                           Perf2Threshold:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x4D_STRUCT;
+
+// **** D0F2xF4_x50 Register Definition ****
+// Address
+#define D0F2xF4_x50_ADDRESS                                     0x50
+
+// Type
+#define D0F2xF4_x50_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x50_PDCReplacementSel_OFFSET                    0
+#define D0F2xF4_x50_PDCReplacementSel_WIDTH                     2
+#define D0F2xF4_x50_PDCReplacementSel_MASK                      0x3
+#define D0F2xF4_x50_Reserved_2_2_OFFSET                         2
+#define D0F2xF4_x50_Reserved_2_2_WIDTH                          1
+#define D0F2xF4_x50_Reserved_2_2_MASK                           0x4
+#define D0F2xF4_x50_PDCLRUUpdatePri_OFFSET                      3
+#define D0F2xF4_x50_PDCLRUUpdatePri_WIDTH                       1
+#define D0F2xF4_x50_PDCLRUUpdatePri_MASK                        0x8
+#define D0F2xF4_x50_PDCParityEn_OFFSET                          4
+#define D0F2xF4_x50_PDCParityEn_WIDTH                           1
+#define D0F2xF4_x50_PDCParityEn_MASK                            0x10
+#define D0F2xF4_x50_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x50_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x50_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x50_PDCInvalidationSel_OFFSET                   8
+#define D0F2xF4_x50_PDCInvalidationSel_WIDTH                    2
+#define D0F2xF4_x50_PDCInvalidationSel_MASK                     0x300
+#define D0F2xF4_x50_PDCSoftInvalidate_OFFSET                    10
+#define D0F2xF4_x50_PDCSoftInvalidate_WIDTH                     1
+#define D0F2xF4_x50_PDCSoftInvalidate_MASK                      0x400
+#define D0F2xF4_x50_Reserved_11_11_OFFSET                       11
+#define D0F2xF4_x50_Reserved_11_11_WIDTH                        1
+#define D0F2xF4_x50_Reserved_11_11_MASK                         0x800
+#define D0F2xF4_x50_PDCSearchDirection_OFFSET                   12
+#define D0F2xF4_x50_PDCSearchDirection_WIDTH                    1
+#define D0F2xF4_x50_PDCSearchDirection_MASK                     0x1000
+#define D0F2xF4_x50_PDCBypass_OFFSET                            13
+#define D0F2xF4_x50_PDCBypass_WIDTH                             1
+#define D0F2xF4_x50_PDCBypass_MASK                              0x2000
+#define D0F2xF4_x50_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x50_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x50_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x50_PDCParitySupport_OFFSET                     15
+#define D0F2xF4_x50_PDCParitySupport_WIDTH                      1
+#define D0F2xF4_x50_PDCParitySupport_MASK                       0x8000
+#define D0F2xF4_x50_PDCWays_OFFSET                              16
+#define D0F2xF4_x50_PDCWays_WIDTH                               8
+#define D0F2xF4_x50_PDCWays_MASK                                0xff0000
+#define D0F2xF4_x50_Reserved_27_24_OFFSET                       24
+#define D0F2xF4_x50_Reserved_27_24_WIDTH                        4
+#define D0F2xF4_x50_Reserved_27_24_MASK                         0xf000000
+#define D0F2xF4_x50_PDCEntries_OFFSET                           28
+#define D0F2xF4_x50_PDCEntries_WIDTH                            4
+#define D0F2xF4_x50_PDCEntries_MASK                             0xf0000000
+
+/// D0F2xF4_x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        PDCReplacementSel:2 ; ///<
+    UINT32                                             Reserved_2_2:1 ; ///<
+    UINT32                                          PDCLRUUpdatePri:1 ; ///<
+    UINT32                                              PDCParityEn:1 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                       PDCInvalidationSel:2 ; ///<
+    UINT32                                        PDCSoftInvalidate:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                       PDCSearchDirection:1 ; ///<
+    UINT32                                                PDCBypass:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                         PDCParitySupport:1 ; ///<
+    UINT32                                                  PDCWays:8 ; ///<
+    UINT32                                           Reserved_27_24:4 ; ///<
+    UINT32                                               PDCEntries:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x50_STRUCT;
+
+// **** D0F2xF4_x51 Register Definition ****
+// Address
+#define D0F2xF4_x51_ADDRESS                                     0x51
+
+// Type
+#define D0F2xF4_x51_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x51_PDCDomainBits_OFFSET                        0
+#define D0F2xF4_x51_PDCDomainBits_WIDTH                         6
+#define D0F2xF4_x51_PDCDomainBits_MASK                          0x3f
+#define D0F2xF4_x51_Reserved_7_6_OFFSET                         6
+#define D0F2xF4_x51_Reserved_7_6_WIDTH                          2
+#define D0F2xF4_x51_Reserved_7_6_MASK                           0xc0
+#define D0F2xF4_x51_PDCLvlHash_OFFSET                           8
+#define D0F2xF4_x51_PDCLvlHash_WIDTH                            1
+#define D0F2xF4_x51_PDCLvlHash_MASK                             0x100
+#define D0F2xF4_x51_PDCUpperLvlAddrHash_OFFSET                  9
+#define D0F2xF4_x51_PDCUpperLvlAddrHash_WIDTH                   1
+#define D0F2xF4_x51_PDCUpperLvlAddrHash_MASK                    0x200
+#define D0F2xF4_x51_PdcAltHashEn_OFFSET                         10
+#define D0F2xF4_x51_PdcAltHashEn_WIDTH                          1
+#define D0F2xF4_x51_PdcAltHashEn_MASK                           0x400
+#define D0F2xF4_x51_Reserved_15_11_OFFSET                       11
+#define D0F2xF4_x51_Reserved_15_11_WIDTH                        5
+#define D0F2xF4_x51_Reserved_15_11_MASK                         0xf800
+#define D0F2xF4_x51_PDCAddressMask_OFFSET                       16
+#define D0F2xF4_x51_PDCAddressMask_WIDTH                        16
+#define D0F2xF4_x51_PDCAddressMask_MASK                         0xffff0000
+
+/// D0F2xF4_x51
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PDCDomainBits:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                               PDCLvlHash:1 ; ///<
+    UINT32                                      PDCUpperLvlAddrHash:1 ; ///<
+    UINT32                                             PdcAltHashEn:1 ; ///<
+    UINT32                                           Reserved_15_11:5 ; ///<
+    UINT32                                           PDCAddressMask:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x51_STRUCT;
+
+// **** D0F2xF4_x52 Register Definition ****
+// Address
+#define D0F2xF4_x52_ADDRESS                                     0x52
+
+// Type
+#define D0F2xF4_x52_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x52_PDCWayDisable_OFFSET                        0
+#define D0F2xF4_x52_PDCWayDisable_WIDTH                         16
+#define D0F2xF4_x52_PDCWayDisable_MASK                          0xffff
+#define D0F2xF4_x52_PDCWayAccessDisable_OFFSET                  16
+#define D0F2xF4_x52_PDCWayAccessDisable_WIDTH                   16
+#define D0F2xF4_x52_PDCWayAccessDisable_MASK                    0xffff0000
+
+/// D0F2xF4_x52
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PDCWayDisable:16; ///<
+    UINT32                                      PDCWayAccessDisable:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x52_STRUCT;
+
+// **** D0F2xF4_x53 Register Definition ****
+// Address
+#define D0F2xF4_x53_ADDRESS                                     0x53
+
+// Type
+#define D0F2xF4_x53_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x53_L2bUpdateFilterBypass_OFFSET                0
+#define D0F2xF4_x53_L2bUpdateFilterBypass_WIDTH                 1
+#define D0F2xF4_x53_L2bUpdateFilterBypass_MASK                  0x1
+#define D0F2xF4_x53_L2bUpdateFilterRdlatency_OFFSET             1
+#define D0F2xF4_x53_L2bUpdateFilterRdlatency_WIDTH              4
+#define D0F2xF4_x53_L2bUpdateFilterRdlatency_MASK               0x1e
+#define D0F2xF4_x53_Reserved_31_5_OFFSET                        5
+#define D0F2xF4_x53_Reserved_31_5_WIDTH                         27
+#define D0F2xF4_x53_Reserved_31_5_MASK                          0xffffffe0
+
+/// D0F2xF4_x53
+typedef union {
+  struct {                                                              ///<
+    UINT32                                    L2bUpdateFilterBypass:1 ; ///<
+    UINT32                                 L2bUpdateFilterRdlatency:4 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x53_STRUCT;
+
+// **** D0F2xF4_x54 Register Definition ****
+// Address
+#define D0F2xF4_x54_ADDRESS                                     0x54
+
+// Type
+#define D0F2xF4_x54_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x54_TWQueueLimit_OFFSET                         0
+#define D0F2xF4_x54_TWQueueLimit_WIDTH                          6
+#define D0F2xF4_x54_TWQueueLimit_MASK                           0x3f
+#define D0F2xF4_x54_TWForceCoherent_OFFSET                      6
+#define D0F2xF4_x54_TWForceCoherent_WIDTH                       1
+#define D0F2xF4_x54_TWForceCoherent_MASK                        0x40
+#define D0F2xF4_x54_Reserved_7_7_OFFSET                         7
+#define D0F2xF4_x54_Reserved_7_7_WIDTH                          1
+#define D0F2xF4_x54_Reserved_7_7_MASK                           0x80
+#define D0F2xF4_x54_TWPrefetchEn_OFFSET                         8
+#define D0F2xF4_x54_TWPrefetchEn_WIDTH                          1
+#define D0F2xF4_x54_TWPrefetchEn_MASK                           0x100
+#define D0F2xF4_x54_TWPrefetchOnly4KDis_OFFSET                  9
+#define D0F2xF4_x54_TWPrefetchOnly4KDis_WIDTH                   1
+#define D0F2xF4_x54_TWPrefetchOnly4KDis_MASK                    0x200
+#define D0F2xF4_x54_TWPTEOnUntransExcl_OFFSET                   10
+#define D0F2xF4_x54_TWPTEOnUntransExcl_WIDTH                    1
+#define D0F2xF4_x54_TWPTEOnUntransExcl_MASK                     0x400
+#define D0F2xF4_x54_TWPTEOnAddrTransExcl_OFFSET                 11
+#define D0F2xF4_x54_TWPTEOnAddrTransExcl_WIDTH                  1
+#define D0F2xF4_x54_TWPTEOnAddrTransExcl_MASK                   0x800
+#define D0F2xF4_x54_TWPrefetchRange_OFFSET                      12
+#define D0F2xF4_x54_TWPrefetchRange_WIDTH                       3
+#define D0F2xF4_x54_TWPrefetchRange_MASK                        0x7000
+#define D0F2xF4_x54_Reserved_15_15_OFFSET                       15
+#define D0F2xF4_x54_Reserved_15_15_WIDTH                        1
+#define D0F2xF4_x54_Reserved_15_15_MASK                         0x8000
+#define D0F2xF4_x54_TwfilterDis_OFFSET                          16
+#define D0F2xF4_x54_TwfilterDis_WIDTH                           1
+#define D0F2xF4_x54_TwfilterDis_MASK                            0x10000
+#define D0F2xF4_x54_Twfilter64bDis_OFFSET                       17
+#define D0F2xF4_x54_Twfilter64bDis_WIDTH                        1
+#define D0F2xF4_x54_Twfilter64bDis_MASK                         0x20000
+#define D0F2xF4_x54_Reserved_31_18_OFFSET                       18
+#define D0F2xF4_x54_Reserved_31_18_WIDTH                        14
+#define D0F2xF4_x54_Reserved_31_18_MASK                         0xfffc0000
+
+/// D0F2xF4_x54
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             TWQueueLimit:6 ; ///<
+    UINT32                                          TWForceCoherent:1 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                             TWPrefetchEn:1 ; ///<
+    UINT32                                      TWPrefetchOnly4KDis:1 ; ///<
+    UINT32                                       TWPTEOnUntransExcl:1 ; ///<
+    UINT32                                     TWPTEOnAddrTransExcl:1 ; ///<
+    UINT32                                          TWPrefetchRange:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                              TwfilterDis:1 ; ///<
+    UINT32                                           Twfilter64bDis:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x54_STRUCT;
+
+// **** D0F2xF4_x56 Register Definition ****
+// Address
+#define D0F2xF4_x56_ADDRESS                                     0x56
+
+// Type
+#define D0F2xF4_x56_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x56_CPPrefetchDis_OFFSET                        0
+#define D0F2xF4_x56_CPPrefetchDis_WIDTH                         1
+#define D0F2xF4_x56_CPPrefetchDis_MASK                          0x1
+#define D0F2xF4_x56_CPFlushOnWait_OFFSET                        1
+#define D0F2xF4_x56_CPFlushOnWait_WIDTH                         1
+#define D0F2xF4_x56_CPFlushOnWait_MASK                          0x2
+#define D0F2xF4_x56_CPFlushOnInv_OFFSET                         2
+#define D0F2xF4_x56_CPFlushOnInv_WIDTH                          1
+#define D0F2xF4_x56_CPFlushOnInv_MASK                           0x4
+#define D0F2xF4_x56_Reserved_15_3_OFFSET                        3
+#define D0F2xF4_x56_Reserved_15_3_WIDTH                         13
+#define D0F2xF4_x56_Reserved_15_3_MASK                          0xfff8
+#define D0F2xF4_x56_CPRdDelay_OFFSET                            16
+#define D0F2xF4_x56_CPRdDelay_WIDTH                             16
+#define D0F2xF4_x56_CPRdDelay_MASK                              0xffff0000
+
+/// D0F2xF4_x56
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            CPPrefetchDis:1 ; ///<
+    UINT32                                            CPFlushOnWait:1 ; ///<
+    UINT32                                             CPFlushOnInv:1 ; ///<
+    UINT32                                            Reserved_15_3:13; ///<
+    UINT32                                                CPRdDelay:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x56_STRUCT;
+
+// **** D0F2xF4_x57 Register Definition ****
+// Address
+#define D0F2xF4_x57_ADDRESS                                     0x57
+
+// Type
+#define D0F2xF4_x57_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x57_L1ImuPcieGfxDis_OFFSET                      0
+#define D0F2xF4_x57_L1ImuPcieGfxDis_WIDTH                       1
+#define D0F2xF4_x57_L1ImuPcieGfxDis_MASK                        0x1
+#define D0F2xF4_x57_Reserved_1_1_OFFSET                         1
+#define D0F2xF4_x57_Reserved_1_1_WIDTH                          1
+#define D0F2xF4_x57_Reserved_1_1_MASK                           0x2
+#define D0F2xF4_x57_L1ImuIntGfxDis_OFFSET                       2
+#define D0F2xF4_x57_L1ImuIntGfxDis_WIDTH                        1
+#define D0F2xF4_x57_L1ImuIntGfxDis_MASK                         0x4
+#define D0F2xF4_x57_Reserved_31_3_OFFSET                        3
+#define D0F2xF4_x57_Reserved_31_3_WIDTH                         29
+#define D0F2xF4_x57_Reserved_31_3_MASK                          0xfffffff8
+
+/// D0F2xF4_x57
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L1ImuPcieGfxDis:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                           L1ImuIntGfxDis:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x57_STRUCT;
+
+// **** D0F2xF4_x58 Register Definition ****
+// Address
+#define D0F2xF4_x58_ADDRESS                                     0x58
+
+// Type
+#define D0F2xF4_x58_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x58_IommuL2GuestAddrMask_OFFSET                 0
+#define D0F2xF4_x58_IommuL2GuestAddrMask_WIDTH                  24
+#define D0F2xF4_x58_IommuL2GuestAddrMask_MASK                   0xffffff
+#define D0F2xF4_x58_Reserved_31_24_OFFSET                       24
+#define D0F2xF4_x58_Reserved_31_24_WIDTH                        8
+#define D0F2xF4_x58_Reserved_31_24_MASK                         0xff000000
+
+/// D0F2xF4_x58
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     IommuL2GuestAddrMask:24; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x58_STRUCT;
+
+// **** D0F2xF4_x60 Register Definition ****
+// Address
+#define D0F2xF4_x60_ADDRESS                                     0x60
+
+// Type
+#define D0F2xF4_x60_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x60_TWDebugEn_OFFSET                            0
+#define D0F2xF4_x60_TWDebugEn_WIDTH                             1
+#define D0F2xF4_x60_TWDebugEn_MASK                              0x1
+#define D0F2xF4_x60_TWDebugNoWrap_OFFSET                        1
+#define D0F2xF4_x60_TWDebugNoWrap_WIDTH                         1
+#define D0F2xF4_x60_TWDebugNoWrap_MASK                          0x2
+#define D0F2xF4_x60_TWDebugForceDisable_OFFSET                  2
+#define D0F2xF4_x60_TWDebugForceDisable_WIDTH                   1
+#define D0F2xF4_x60_TWDebugForceDisable_MASK                    0x4
+#define D0F2xF4_x60_Reserved_14_3_OFFSET                        3
+#define D0F2xF4_x60_Reserved_14_3_WIDTH                         12
+#define D0F2xF4_x60_Reserved_14_3_MASK                          0x7ff8
+#define D0F2xF4_x60_TWDebugMask_OFFSET                          15
+#define D0F2xF4_x60_TWDebugMask_WIDTH                           17
+#define D0F2xF4_x60_TWDebugMask_MASK                            0xffff8000
+
+/// D0F2xF4_x60
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                TWDebugEn:1 ; ///<
+    UINT32                                            TWDebugNoWrap:1 ; ///<
+    UINT32                                      TWDebugForceDisable:1 ; ///<
+    UINT32                                            Reserved_14_3:12; ///<
+    UINT32                                              TWDebugMask:17; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x60_STRUCT;
+
+// **** D0F2xF4_x61 Register Definition ****
+// Address
+#define D0F2xF4_x61_ADDRESS                                     0x61
+
+// Type
+#define D0F2xF4_x61_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x61_Reserved_11_0_OFFSET                        0
+#define D0F2xF4_x61_Reserved_11_0_WIDTH                         12
+#define D0F2xF4_x61_Reserved_11_0_MASK                          0xfff
+#define D0F2xF4_x61_TWDebugAddrLo_OFFSET                        12
+#define D0F2xF4_x61_TWDebugAddrLo_WIDTH                         20
+#define D0F2xF4_x61_TWDebugAddrLo_MASK                          0xfffff000
+
+/// D0F2xF4_x61
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_11_0:12; ///<
+    UINT32                                            TWDebugAddrLo:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x61_STRUCT;
+
+// **** D0F2xF4_x62 Register Definition ****
+// Address
+#define D0F2xF4_x62_ADDRESS                                     0x62
+
+// Type
+#define D0F2xF4_x62_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x62_TWDebugAddrHi_OFFSET                        0
+#define D0F2xF4_x62_TWDebugAddrHi_WIDTH                         32
+#define D0F2xF4_x62_TWDebugAddrHi_MASK                          0xffffffff
+
+/// D0F2xF4_x62
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            TWDebugAddrHi:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x62_STRUCT;
+
+// **** D0F2xF4_x6A Register Definition ****
+// Address
+#define D0F2xF4_x6A_ADDRESS                                     0x6a
+
+// Type
+#define D0F2xF4_x6A_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x6A_IntEventOrderEn_OFFSET                      0
+#define D0F2xF4_x6A_IntEventOrderEn_WIDTH                       1
+#define D0F2xF4_x6A_IntEventOrderEn_MASK                        0x1
+#define D0F2xF4_x6A_IntCPOrderEn_OFFSET                         1
+#define D0F2xF4_x6A_IntCPOrderEn_WIDTH                          1
+#define D0F2xF4_x6A_IntCPOrderEn_MASK                           0x2
+#define D0F2xF4_x6A_IntPPROrderEn_OFFSET                        2
+#define D0F2xF4_x6A_IntPPROrderEn_WIDTH                         1
+#define D0F2xF4_x6A_IntPPROrderEn_MASK                          0x4
+#define D0F2xF4_x6A_Reserved_31_3_OFFSET                        3
+#define D0F2xF4_x6A_Reserved_31_3_WIDTH                         29
+#define D0F2xF4_x6A_Reserved_31_3_MASK                          0xfffffff8
+
+/// D0F2xF4_x6A
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          IntEventOrderEn:1 ; ///<
+    UINT32                                             IntCPOrderEn:1 ; ///<
+    UINT32                                            IntPPROrderEn:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x6A_STRUCT;
+
+// **** D0F2xF4_x70 Register Definition ****
+// Address
+#define D0F2xF4_x70_ADDRESS                                     0x70
+
+// Type
+#define D0F2xF4_x70_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x70_FC1Credits_OFFSET                           0
+#define D0F2xF4_x70_FC1Credits_WIDTH                            6
+#define D0F2xF4_x70_FC1Credits_MASK                             0x3f
+#define D0F2xF4_x70_Reserved_6_6_OFFSET                         6
+#define D0F2xF4_x70_Reserved_6_6_WIDTH                          1
+#define D0F2xF4_x70_Reserved_6_6_MASK                           0x40
+#define D0F2xF4_x70_FC1Override_OFFSET                          7
+#define D0F2xF4_x70_FC1Override_WIDTH                           1
+#define D0F2xF4_x70_FC1Override_MASK                            0x80
+#define D0F2xF4_x70_FC2Credits_OFFSET                           8
+#define D0F2xF4_x70_FC2Credits_WIDTH                            6
+#define D0F2xF4_x70_FC2Credits_MASK                             0x3f00
+#define D0F2xF4_x70_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x70_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x70_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x70_FC2Override_OFFSET                          15
+#define D0F2xF4_x70_FC2Override_WIDTH                           1
+#define D0F2xF4_x70_FC2Override_MASK                            0x8000
+#define D0F2xF4_x70_FC3Credits_OFFSET                           16
+#define D0F2xF4_x70_FC3Credits_WIDTH                            6
+#define D0F2xF4_x70_FC3Credits_MASK                             0x3f0000
+#define D0F2xF4_x70_Reserved_22_22_OFFSET                       22
+#define D0F2xF4_x70_Reserved_22_22_WIDTH                        1
+#define D0F2xF4_x70_Reserved_22_22_MASK                         0x400000
+#define D0F2xF4_x70_FC3Override_OFFSET                          23
+#define D0F2xF4_x70_FC3Override_WIDTH                           1
+#define D0F2xF4_x70_FC3Override_MASK                            0x800000
+#define D0F2xF4_x70_DTECredits_OFFSET                           24
+#define D0F2xF4_x70_DTECredits_WIDTH                            6
+#define D0F2xF4_x70_DTECredits_MASK                             0x3f000000
+#define D0F2xF4_x70_Reserved_30_30_OFFSET                       30
+#define D0F2xF4_x70_Reserved_30_30_WIDTH                        1
+#define D0F2xF4_x70_Reserved_30_30_MASK                         0x40000000
+#define D0F2xF4_x70_DTEOverride_OFFSET                          31
+#define D0F2xF4_x70_DTEOverride_WIDTH                           1
+#define D0F2xF4_x70_DTEOverride_MASK                            0x80000000
+
+/// D0F2xF4_x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               FC1Credits:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                              FC1Override:1 ; ///<
+    UINT32                                               FC2Credits:6 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                              FC2Override:1 ; ///<
+    UINT32                                               FC3Credits:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                              FC3Override:1 ; ///<
+    UINT32                                               DTECredits:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                              DTEOverride:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x70_STRUCT;
+
+// **** D0F2xF4_x71 Register Definition ****
+// Address
+#define D0F2xF4_x71_ADDRESS                                     0x71
+
+// Type
+#define D0F2xF4_x71_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x71_PDTIECredits_OFFSET                         0
+#define D0F2xF4_x71_PDTIECredits_WIDTH                          6
+#define D0F2xF4_x71_PDTIECredits_MASK                           0x3f
+#define D0F2xF4_x71_Reserved_6_6_OFFSET                         6
+#define D0F2xF4_x71_Reserved_6_6_WIDTH                          1
+#define D0F2xF4_x71_Reserved_6_6_MASK                           0x40
+#define D0F2xF4_x71_PDTIEOverride_OFFSET                        7
+#define D0F2xF4_x71_PDTIEOverride_WIDTH                         1
+#define D0F2xF4_x71_PDTIEOverride_MASK                          0x80
+#define D0F2xF4_x71_TWELCredits_OFFSET                          8
+#define D0F2xF4_x71_TWELCredits_WIDTH                           6
+#define D0F2xF4_x71_TWELCredits_MASK                            0x3f00
+#define D0F2xF4_x71_Reserved_14_14_OFFSET                       14
+#define D0F2xF4_x71_Reserved_14_14_WIDTH                        1
+#define D0F2xF4_x71_Reserved_14_14_MASK                         0x4000
+#define D0F2xF4_x71_TWELOverride_OFFSET                         15
+#define D0F2xF4_x71_TWELOverride_WIDTH                          1
+#define D0F2xF4_x71_TWELOverride_MASK                           0x8000
+#define D0F2xF4_x71_CpPrefetchCredits_OFFSET                    16
+#define D0F2xF4_x71_CpPrefetchCredits_WIDTH                     4
+#define D0F2xF4_x71_CpPrefetchCredits_MASK                      0xf0000
+#define D0F2xF4_x71_PprMcifCredits_OFFSET                       20
+#define D0F2xF4_x71_PprMcifCredits_WIDTH                        4
+#define D0F2xF4_x71_PprMcifCredits_MASK                         0xf00000
+#define D0F2xF4_x71_Reserved_31_24_OFFSET                       24
+#define D0F2xF4_x71_Reserved_31_24_WIDTH                        8
+#define D0F2xF4_x71_Reserved_31_24_MASK                         0xff000000
+
+/// D0F2xF4_x71
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PDTIECredits:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                            PDTIEOverride:1 ; ///<
+    UINT32                                              TWELCredits:6 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                                             TWELOverride:1 ; ///<
+    UINT32                                        CpPrefetchCredits:4 ; ///<
+    UINT32                                           PprMcifCredits:4 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x71_STRUCT;
+
+// **** D0F2xF4_x78 Register Definition ****
+// Address
+#define D0F2xF4_x78_ADDRESS                                     0x78
+
+// Type
+#define D0F2xF4_x78_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x78_MCIFBaseReadCredits_OFFSET                  0
+#define D0F2xF4_x78_MCIFBaseReadCredits_WIDTH                   5
+#define D0F2xF4_x78_MCIFBaseReadCredits_MASK                    0x1f
+#define D0F2xF4_x78_Reserved_7_5_OFFSET                         5
+#define D0F2xF4_x78_Reserved_7_5_WIDTH                          3
+#define D0F2xF4_x78_Reserved_7_5_MASK                           0xe0
+#define D0F2xF4_x78_MCIFIsocReadCredits_OFFSET                  8
+#define D0F2xF4_x78_MCIFIsocReadCredits_WIDTH                   5
+#define D0F2xF4_x78_MCIFIsocReadCredits_MASK                    0x1f00
+#define D0F2xF4_x78_Reserved_15_13_OFFSET                       13
+#define D0F2xF4_x78_Reserved_15_13_WIDTH                        3
+#define D0F2xF4_x78_Reserved_15_13_MASK                         0xe000
+#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_OFFSET              16
+#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_WIDTH               5
+#define D0F2xF4_x78_MCIFBaseWriteHdrCredits_MASK                0x1f0000
+#define D0F2xF4_x78_Reserved_23_21_OFFSET                       21
+#define D0F2xF4_x78_Reserved_23_21_WIDTH                        3
+#define D0F2xF4_x78_Reserved_23_21_MASK                         0xe00000
+#define D0F2xF4_x78_MCIFBaseWriteDataCredits_OFFSET             24
+#define D0F2xF4_x78_MCIFBaseWriteDataCredits_WIDTH              5
+#define D0F2xF4_x78_MCIFBaseWriteDataCredits_MASK               0x1f000000
+#define D0F2xF4_x78_Reserved_31_29_OFFSET                       29
+#define D0F2xF4_x78_Reserved_31_29_WIDTH                        3
+#define D0F2xF4_x78_Reserved_31_29_MASK                         0xe0000000
+
+/// D0F2xF4_x78
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      MCIFBaseReadCredits:5 ; ///<
+    UINT32                                             Reserved_7_5:3 ; ///<
+    UINT32                                      MCIFIsocReadCredits:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                  MCIFBaseWriteHdrCredits:5 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                 MCIFBaseWriteDataCredits:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x78_STRUCT;
+
+
+
+
+
+
+
+// **** D0F2xF4_x80 Register Definition ****
+// Address
+#define D0F2xF4_x80_ADDRESS                                     0x80
+
+// Type
+#define D0F2xF4_x80_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x80_ERRRuleLock0_OFFSET                         0
+#define D0F2xF4_x80_ERRRuleLock0_WIDTH                          1
+#define D0F2xF4_x80_ERRRuleLock0_MASK                           0x1
+#define D0F2xF4_x80_Reserved_3_1_OFFSET                         1
+#define D0F2xF4_x80_Reserved_3_1_WIDTH                          3
+#define D0F2xF4_x80_Reserved_3_1_MASK                           0xe
+#define D0F2xF4_x80_ERRRuleDisable0_OFFSET                      4
+#define D0F2xF4_x80_ERRRuleDisable0_WIDTH                       28
+#define D0F2xF4_x80_ERRRuleDisable0_MASK                        0xfffffff0
+
+/// D0F2xF4_x80
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             ERRRuleLock0:1 ; ///<
+    UINT32                                             Reserved_3_1:3 ; ///<
+    UINT32                                          ERRRuleDisable0:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x80_STRUCT;
+
+// **** D0F2xF4_x81 Register Definition ****
+// Address
+#define D0F2xF4_x81_ADDRESS                                     0x81
+
+// Type
+#define D0F2xF4_x81_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x81_ERRRuleDisable1_OFFSET                      0
+#define D0F2xF4_x81_ERRRuleDisable1_WIDTH                       32
+#define D0F2xF4_x81_ERRRuleDisable1_MASK                        0xffffffff
+
+/// D0F2xF4_x81
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x81_STRUCT;
+
+// **** D0F2xF4_x82 Register Definition ****
+// Address
+#define D0F2xF4_x82_ADDRESS                                     0x82
+
+// Type
+#define D0F2xF4_x82_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x82_ERRRuleDisable2_OFFSET                      0
+#define D0F2xF4_x82_ERRRuleDisable2_WIDTH                       32
+#define D0F2xF4_x82_ERRRuleDisable2_MASK                        0xffffffff
+
+/// D0F2xF4_x82
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          ERRRuleDisable2:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x82_STRUCT;
+
+// **** D0F2xF4_x90 Register Definition ****
+// Address
+#define D0F2xF4_x90_ADDRESS                                     0x90
+
+// Type
+#define D0F2xF4_x90_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET                 0
+#define D0F2xF4_x90_CKGateL2BRegsDisable_WIDTH                  1
+#define D0F2xF4_x90_CKGateL2BRegsDisable_MASK                   0x1
+#define D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET              1
+#define D0F2xF4_x90_CKGateL2BDynamicDisable_WIDTH               1
+#define D0F2xF4_x90_CKGateL2BDynamicDisable_MASK                0x2
+#define D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET                 2
+#define D0F2xF4_x90_CKGateL2BMiscDisable_WIDTH                  1
+#define D0F2xF4_x90_CKGateL2BMiscDisable_MASK                   0x4
+#define D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET                3
+#define D0F2xF4_x90_CKGateL2BCacheDisable_WIDTH                 1
+#define D0F2xF4_x90_CKGateL2BCacheDisable_MASK                  0x8
+#define D0F2xF4_x90_CKGateL2BLength_OFFSET                      4
+#define D0F2xF4_x90_CKGateL2BLength_WIDTH                       2
+#define D0F2xF4_x90_CKGateL2BLength_MASK                        0x30
+#define D0F2xF4_x90_CKGateL2BStop_OFFSET                        6
+#define D0F2xF4_x90_CKGateL2BStop_WIDTH                         2
+#define D0F2xF4_x90_CKGateL2BStop_MASK                          0xc0
+#define D0F2xF4_x90_Reserved_31_8_OFFSET                        8
+#define D0F2xF4_x90_Reserved_31_8_WIDTH                         24
+#define D0F2xF4_x90_Reserved_31_8_MASK                          0xffffff00
+
+/// D0F2xF4_x90
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     CKGateL2BRegsDisable:1 ; ///<
+    UINT32                                  CKGateL2BDynamicDisable:1 ; ///<
+    UINT32                                     CKGateL2BMiscDisable:1 ; ///<
+    UINT32                                    CKGateL2BCacheDisable:1 ; ///<
+    UINT32                                          CKGateL2BLength:2 ; ///<
+    UINT32                                            CKGateL2BStop:2 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x90_STRUCT;
+
+// **** D0F2xF4_x92 Register Definition ****
+// Address
+#define D0F2xF4_x92_ADDRESS                                     0x92
+
+// Type
+#define D0F2xF4_x92_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x92_PprInttimedelay_OFFSET                      0
+#define D0F2xF4_x92_PprInttimedelay_WIDTH                       8
+#define D0F2xF4_x92_PprInttimedelay_MASK                        0xff
+#define D0F2xF4_x92_PprIntreqdelay_OFFSET                       8
+#define D0F2xF4_x92_PprIntreqdelay_WIDTH                        8
+#define D0F2xF4_x92_PprIntreqdelay_MASK                         0xff00
+#define D0F2xF4_x92_PprIntcoallesceEn_OFFSET                    16
+#define D0F2xF4_x92_PprIntcoallesceEn_WIDTH                     1
+#define D0F2xF4_x92_PprIntcoallesceEn_MASK                      0x10000
+#define D0F2xF4_x92_Reserved_31_17_OFFSET                       17
+#define D0F2xF4_x92_Reserved_31_17_WIDTH                        15
+#define D0F2xF4_x92_Reserved_31_17_MASK                         0xfffe0000
+
+/// D0F2xF4_x92
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          PprInttimedelay:8 ; ///<
+    UINT32                                           PprIntreqdelay:8 ; ///<
+    UINT32                                        PprIntcoallesceEn:1 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x92_STRUCT;
+
+// **** D0F2xF4_x94 Register Definition ****
+// Address
+#define D0F2xF4_x94_ADDRESS                                     0x94
+
+// Type
+#define D0F2xF4_x94_TYPE                                        TYPE_D0F2xF4
+// Field Data
+#define D0F2xF4_x94_L2bregGstPgsize_OFFSET                      0
+#define D0F2xF4_x94_L2bregGstPgsize_WIDTH                       2
+#define D0F2xF4_x94_L2bregGstPgsize_MASK                        0x3
+#define D0F2xF4_x94_L2bregHostPgsize_OFFSET                     2
+#define D0F2xF4_x94_L2bregHostPgsize_WIDTH                      2
+#define D0F2xF4_x94_L2bregHostPgsize_MASK                       0xc
+#define D0F2xF4_x94_Reserved_31_4_OFFSET                        4
+#define D0F2xF4_x94_Reserved_31_4_WIDTH                         28
+#define D0F2xF4_x94_Reserved_31_4_MASK                          0xfffffff0
+
+/// D0F2xF4_x94
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L2bregGstPgsize:2 ; ///<
+    UINT32                                         L2bregHostPgsize:2 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xF4_x94_STRUCT;
+
+// **** D0F2xFC_x32_L1 Register Definition ****
+// Address
+#define D0F2xFC_x32_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x32)
+
+// Type
+#define D0F2xFC_x32_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET                 0
+#define D0F2xFC_x32_L1_AtsMultipleRespEn_WIDTH                  1
+#define D0F2xFC_x32_L1_AtsMultipleRespEn_MASK                   0x1
+#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET               1
+#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_WIDTH                1
+#define D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK                 0x2
+#define D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET                 2
+#define D0F2xFC_x32_L1_TimeoutPulseExtEn_WIDTH                  1
+#define D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK                   0x4
+#define D0F2xFC_x32_L1_TlpprefixerrEn_OFFSET                    3
+#define D0F2xFC_x32_L1_TlpprefixerrEn_WIDTH                     1
+#define D0F2xFC_x32_L1_TlpprefixerrEn_MASK                      0x8
+#define D0F2xFC_x32_L1_Reserved_31_4_OFFSET                     4
+#define D0F2xFC_x32_L1_Reserved_31_4_WIDTH                      28
+#define D0F2xFC_x32_L1_Reserved_31_4_MASK                       0xfffffff0
+
+/// D0F2xFC_x32_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        AtsMultipleRespEn:1 ; ///<
+    UINT32                                      AtsMultipleL1toL2En:1 ; ///<
+    UINT32                                        TimeoutPulseExtEn:1 ; ///<
+    UINT32                                           TlpprefixerrEn:1 ; ///<
+    UINT32                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x32_L1_STRUCT;
+
+// **** D0F2xFC_x11_L1 Register Definition ****
+// Address
+#define D0F2xFC_x11_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x11)
+
+// Type
+#define D0F2xFC_x11_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x11_L1_L1cachelinedis0_OFFSET                   0
+#define D0F2xFC_x11_L1_L1cachelinedis0_WIDTH                    6
+#define D0F2xFC_x11_L1_L1cachelinedis0_MASK                     0x3f
+#define D0F2xFC_x11_L1_Reserved_7_6_OFFSET                      6
+#define D0F2xFC_x11_L1_Reserved_7_6_WIDTH                       2
+#define D0F2xFC_x11_L1_Reserved_7_6_MASK                        0xc0
+#define D0F2xFC_x11_L1_L1cachelinedis1_OFFSET                   8
+#define D0F2xFC_x11_L1_L1cachelinedis1_WIDTH                    6
+#define D0F2xFC_x11_L1_L1cachelinedis1_MASK                     0x3f00
+#define D0F2xFC_x11_L1_Reserved_31_14_OFFSET                    14
+#define D0F2xFC_x11_L1_Reserved_31_14_WIDTH                     18
+#define D0F2xFC_x11_L1_Reserved_31_14_MASK                      0xffffc000
+
+/// D0F2xFC_x11_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L1cachelinedis0:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                          L1cachelinedis1:6 ; ///<
+    UINT32                                           Reserved_31_14:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x11_L1_STRUCT;
+
+// **** D0F2xFC_x34_L1 Register Definition ****
+// Address
+#define D0F2xFC_x34_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x34)
+
+// Type
+#define D0F2xFC_x34_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x34_L1_L1MempwrEn_OFFSET                        0
+#define D0F2xFC_x34_L1_L1MempwrEn_WIDTH                         1
+#define D0F2xFC_x34_L1_L1MempwrEn_MASK                          0x1
+#define D0F2xFC_x34_L1_Reserved_7_1_OFFSET                      1
+#define D0F2xFC_x34_L1_Reserved_7_1_WIDTH                       7
+#define D0F2xFC_x34_L1_Reserved_7_1_MASK                        0xfe
+#define D0F2xFC_x34_L1_L1MempwrTimer0_OFFSET                    8
+#define D0F2xFC_x34_L1_L1MempwrTimer0_WIDTH                     8
+#define D0F2xFC_x34_L1_L1MempwrTimer0_MASK                      0xff00
+#define D0F2xFC_x34_L1_L1MempwrTimer1_OFFSET                    16
+#define D0F2xFC_x34_L1_L1MempwrTimer1_WIDTH                     8
+#define D0F2xFC_x34_L1_L1MempwrTimer1_MASK                      0xff0000
+#define D0F2xFC_x34_L1_L1MempwrTimer2_OFFSET                    24
+#define D0F2xFC_x34_L1_L1MempwrTimer2_WIDTH                     8
+#define D0F2xFC_x34_L1_L1MempwrTimer2_MASK                      0xff000000
+
+/// D0F2xFC_x34_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               L1MempwrEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                           L1MempwrTimer0:8 ; ///<
+    UINT32                                           L1MempwrTimer1:8 ; ///<
+    UINT32                                           L1MempwrTimer2:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x34_L1_STRUCT;
+
+// **** D0F2xFC_x0F_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0F_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0F)
+
+// Type
+#define D0F2xFC_x0F_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_OFFSET               0
+#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_WIDTH                32
+#define D0F2xFC_x0F_L1_AtsTlbinvPulseWidth_MASK                 0xffffffff
+
+/// D0F2xFC_x0F_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      AtsTlbinvPulseWidth:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0F_L1_STRUCT;
+
+// **** D0F2xFC_x0E_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0E_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0E)
+
+// Type
+#define D0F2xFC_x0E_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0E_L1_Reserved_0_0_OFFSET                      0
+#define D0F2xFC_x0E_L1_Reserved_0_0_WIDTH                       1
+#define D0F2xFC_x0E_L1_Reserved_0_0_MASK                        0x1
+#define D0F2xFC_x0E_L1_MsiToHtRemapDis_OFFSET                   1
+#define D0F2xFC_x0E_L1_MsiToHtRemapDis_WIDTH                    1
+#define D0F2xFC_x0E_L1_MsiToHtRemapDis_MASK                     0x2
+#define D0F2xFC_x0E_L1_L1AbrtAtsDis_OFFSET                      2
+#define D0F2xFC_x0E_L1_L1AbrtAtsDis_WIDTH                       1
+#define D0F2xFC_x0E_L1_L1AbrtAtsDis_MASK                        0x4
+#define D0F2xFC_x0E_L1_Reserved_5_3_OFFSET                      3
+#define D0F2xFC_x0E_L1_Reserved_5_3_WIDTH                       3
+#define D0F2xFC_x0E_L1_Reserved_5_3_MASK                        0x38
+#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_OFFSET                     6
+#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_WIDTH                      3
+#define D0F2xFC_x0E_L1_MsiHtRsvIntMt_MASK                       0x1c0
+#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_OFFSET                  9
+#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_WIDTH                   1
+#define D0F2xFC_x0E_L1_MsiHtRsvIntRqEio_MASK                    0x200
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_OFFSET                     10
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_WIDTH                      1
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDM_MASK                       0x400
+#define D0F2xFC_x0E_L1_Reserved_11_11_OFFSET                    11
+#define D0F2xFC_x0E_L1_Reserved_11_11_WIDTH                     1
+#define D0F2xFC_x0E_L1_Reserved_11_11_MASK                      0x800
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_OFFSET            12
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_WIDTH             8
+#define D0F2xFC_x0E_L1_MsiHtRsvIntDestination_MASK              0xff000
+#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_OFFSET                 20
+#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_WIDTH                  8
+#define D0F2xFC_x0E_L1_MsiHtRsvIntVector_MASK                   0xff00000
+#define D0F2xFC_x0E_L1_Reserved_31_28_OFFSET                    28
+#define D0F2xFC_x0E_L1_Reserved_31_28_WIDTH                     4
+#define D0F2xFC_x0E_L1_Reserved_31_28_MASK                      0xf0000000
+
+/// D0F2xFC_x0E_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                          MsiToHtRemapDis:1 ; ///<
+    UINT32                                             L1AbrtAtsDis:1 ; ///<
+    UINT32                                             Reserved_5_3:3 ; ///<
+    UINT32                                            MsiHtRsvIntMt:3 ; ///<
+    UINT32                                         MsiHtRsvIntRqEio:1 ; ///<
+    UINT32                                            MsiHtRsvIntDM:1 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                   MsiHtRsvIntDestination:8 ; ///<
+    UINT32                                        MsiHtRsvIntVector:8 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0E_L1_STRUCT;
+
+
+// **** D0F2xFC_x37_L1 Register Definition ****
+// Address
+#define D0F2xFC_x37_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x37)
+
+// Type
+#define D0F2xFC_x37_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x37_L1_L1EfrSup_OFFSET                          0
+#define D0F2xFC_x37_L1_L1EfrSup_WIDTH                           1
+#define D0F2xFC_x37_L1_L1EfrSup_MASK                            0x1
+#define D0F2xFC_x37_L1_L1PprSup_OFFSET                          1
+#define D0F2xFC_x37_L1_L1PprSup_WIDTH                           1
+#define D0F2xFC_x37_L1_L1PprSup_MASK                            0x2
+#define D0F2xFC_x37_L1_Reserved_31_2_OFFSET                     2
+#define D0F2xFC_x37_L1_Reserved_31_2_WIDTH                      30
+#define D0F2xFC_x37_L1_Reserved_31_2_MASK                       0xfffffffc
+
+/// D0F2xFC_x37_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 L1EfrSup:1 ; ///<
+    UINT32                                                 L1PprSup:1 ; ///<
+    UINT32                                            Reserved_31_2:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x37_L1_STRUCT;
+
+
+// **** D0F2xFC_x20_L1 Register Definition ****
+// Address
+#define D0F2xFC_x20_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x20)
+
+// Type
+#define D0F2xFC_x20_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x20_L1_EntryStatus0_OFFSET                      0
+#define D0F2xFC_x20_L1_EntryStatus0_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus0_MASK                        0x7
+#define D0F2xFC_x20_L1_EntryStatus1_OFFSET                      3
+#define D0F2xFC_x20_L1_EntryStatus1_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus1_MASK                        0x38
+#define D0F2xFC_x20_L1_EntryStatus2_OFFSET                      6
+#define D0F2xFC_x20_L1_EntryStatus2_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus2_MASK                        0x1c0
+#define D0F2xFC_x20_L1_EntryStatus3_OFFSET                      9
+#define D0F2xFC_x20_L1_EntryStatus3_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus3_MASK                        0xe00
+#define D0F2xFC_x20_L1_EntryStatus4_OFFSET                      12
+#define D0F2xFC_x20_L1_EntryStatus4_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus4_MASK                        0x7000
+#define D0F2xFC_x20_L1_EntryStatus5_OFFSET                      15
+#define D0F2xFC_x20_L1_EntryStatus5_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus5_MASK                        0x38000
+#define D0F2xFC_x20_L1_EntryStatus6_OFFSET                      18
+#define D0F2xFC_x20_L1_EntryStatus6_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus6_MASK                        0x1c0000
+#define D0F2xFC_x20_L1_EntryStatus7_OFFSET                      21
+#define D0F2xFC_x20_L1_EntryStatus7_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus7_MASK                        0xe00000
+#define D0F2xFC_x20_L1_EntryStatus8_OFFSET                      24
+#define D0F2xFC_x20_L1_EntryStatus8_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus8_MASK                        0x7000000
+#define D0F2xFC_x20_L1_EntryStatus9_OFFSET                      27
+#define D0F2xFC_x20_L1_EntryStatus9_WIDTH                       3
+#define D0F2xFC_x20_L1_EntryStatus9_MASK                        0x38000000
+#define D0F2xFC_x20_L1_Reserved_31_30_OFFSET                    30
+#define D0F2xFC_x20_L1_Reserved_31_30_WIDTH                     2
+#define D0F2xFC_x20_L1_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F2xFC_x20_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             EntryStatus0:3 ; ///<
+    UINT32                                             EntryStatus1:3 ; ///<
+    UINT32                                             EntryStatus2:3 ; ///<
+    UINT32                                             EntryStatus3:3 ; ///<
+    UINT32                                             EntryStatus4:3 ; ///<
+    UINT32                                             EntryStatus5:3 ; ///<
+    UINT32                                             EntryStatus6:3 ; ///<
+    UINT32                                             EntryStatus7:3 ; ///<
+    UINT32                                             EntryStatus8:3 ; ///<
+    UINT32                                             EntryStatus9:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x20_L1_STRUCT;
+
+// **** D0F2xFC_x35_L1 Register Definition ****
+// Address
+#define D0F2xFC_x35_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x35)
+
+// Type
+#define D0F2xFC_x35_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x35_L1_L1MempwrTimer3_OFFSET                    0
+#define D0F2xFC_x35_L1_L1MempwrTimer3_WIDTH                     8
+#define D0F2xFC_x35_L1_L1MempwrTimer3_MASK                      0xff
+#define D0F2xFC_x35_L1_Reserved_31_8_OFFSET                     8
+#define D0F2xFC_x35_L1_Reserved_31_8_WIDTH                      24
+#define D0F2xFC_x35_L1_Reserved_31_8_MASK                       0xffffff00
+
+/// D0F2xFC_x35_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           L1MempwrTimer3:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x35_L1_STRUCT;
+
+
+// **** D0F2xFC_x0C_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0C_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0C)
+
+// Type
+#define D0F2xFC_x0C_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0C_L1_UnfilterDis_OFFSET                       0
+#define D0F2xFC_x0C_L1_UnfilterDis_WIDTH                        1
+#define D0F2xFC_x0C_L1_UnfilterDis_MASK                         0x1
+#define D0F2xFC_x0C_L1_FragmentDis_OFFSET                       1
+#define D0F2xFC_x0C_L1_FragmentDis_WIDTH                        1
+#define D0F2xFC_x0C_L1_FragmentDis_MASK                         0x2
+#define D0F2xFC_x0C_L1_CacheirOnly_OFFSET                       2
+#define D0F2xFC_x0C_L1_CacheirOnly_WIDTH                        1
+#define D0F2xFC_x0C_L1_CacheirOnly_MASK                         0x4
+#define D0F2xFC_x0C_L1_CacheiwOnly_OFFSET                       3
+#define D0F2xFC_x0C_L1_CacheiwOnly_WIDTH                        1
+#define D0F2xFC_x0C_L1_CacheiwOnly_MASK                         0x8
+#define D0F2xFC_x0C_L1_Reserved0_OFFSET                         4
+#define D0F2xFC_x0C_L1_Reserved0_WIDTH                          1
+#define D0F2xFC_x0C_L1_Reserved0_MASK                           0x10
+#define D0F2xFC_x0C_L1_ReplacementSel_OFFSET                    5
+#define D0F2xFC_x0C_L1_ReplacementSel_WIDTH                     1
+#define D0F2xFC_x0C_L1_ReplacementSel_MASK                      0x20
+#define D0F2xFC_x0C_L1_Reserved_7_6_OFFSET                      6
+#define D0F2xFC_x0C_L1_Reserved_7_6_WIDTH                       2
+#define D0F2xFC_x0C_L1_Reserved_7_6_MASK                        0xc0
+#define D0F2xFC_x0C_L1_L2Credits_OFFSET                         8
+#define D0F2xFC_x0C_L1_L2Credits_WIDTH                          6
+#define D0F2xFC_x0C_L1_L2Credits_MASK                           0x3f00
+#define D0F2xFC_x0C_L1_Reserved1_OFFSET                         14
+#define D0F2xFC_x0C_L1_Reserved1_WIDTH                          6
+#define D0F2xFC_x0C_L1_Reserved1_MASK                           0xfc000
+#define D0F2xFC_x0C_L1_L1Banks_OFFSET                           20
+#define D0F2xFC_x0C_L1_L1Banks_WIDTH                            2
+#define D0F2xFC_x0C_L1_L1Banks_MASK                             0x300000
+#define D0F2xFC_x0C_L1_Reserved_23_22_OFFSET                    22
+#define D0F2xFC_x0C_L1_Reserved_23_22_WIDTH                     2
+#define D0F2xFC_x0C_L1_Reserved_23_22_MASK                      0xc00000
+#define D0F2xFC_x0C_L1_L1Entries_OFFSET                         24
+#define D0F2xFC_x0C_L1_L1Entries_WIDTH                          4
+#define D0F2xFC_x0C_L1_L1Entries_MASK                           0xf000000
+#define D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET                 28
+#define D0F2xFC_x0C_L1_L1VirtOrderQueues_WIDTH                  3
+#define D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK                   0x70000000
+#define D0F2xFC_x0C_L1_Reserved_31_31_OFFSET                    31
+#define D0F2xFC_x0C_L1_Reserved_31_31_WIDTH                     1
+#define D0F2xFC_x0C_L1_Reserved_31_31_MASK                      0x80000000
+
+/// D0F2xFC_x0C_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              UnfilterDis:1 ; ///<
+    UINT32                                              FragmentDis:1 ; ///<
+    UINT32                                              CacheirOnly:1 ; ///<
+    UINT32                                              CacheiwOnly:1 ; ///<
+    UINT32                                                Reserved0:1 ; ///<
+    UINT32                                           ReplacementSel:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                                L2Credits:6 ; ///<
+    UINT32                                                Reserved1:6 ; ///<
+    UINT32                                                  L1Banks:2 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                                L1Entries:4 ; ///<
+    UINT32                                        L1VirtOrderQueues:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0C_L1_STRUCT;
+
+
+// **** D0F2xFC_x08_L1 Register Definition ****
+// Address
+#define D0F2xFC_x08_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x08)
+
+// Type
+#define D0F2xFC_x08_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x08_L1_L1debugStatus_OFFSET                     0
+#define D0F2xFC_x08_L1_L1debugStatus_WIDTH                      32
+#define D0F2xFC_x08_L1_L1debugStatus_MASK                       0xffffffff
+
+/// D0F2xFC_x08_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            L1debugStatus:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x08_L1_STRUCT;
+
+
+// **** D0F2xFC_x10_L1 Register Definition ****
+// Address
+#define D0F2xFC_x10_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x10)
+
+// Type
+#define D0F2xFC_x10_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x10_L1_L1cachebanksel0_OFFSET                   0
+#define D0F2xFC_x10_L1_L1cachebanksel0_WIDTH                    16
+#define D0F2xFC_x10_L1_L1cachebanksel0_MASK                     0xffff
+#define D0F2xFC_x10_L1_Reserved_31_16_OFFSET                    16
+#define D0F2xFC_x10_L1_Reserved_31_16_WIDTH                     16
+#define D0F2xFC_x10_L1_Reserved_31_16_MASK                      0xffff0000
+
+/// D0F2xFC_x10_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                          L1cachebanksel0:16; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x10_L1_STRUCT;
+
+// **** D0F2xFC_x23_L1 Register Definition ****
+// Address
+#define D0F2xFC_x23_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x23)
+
+// Type
+#define D0F2xFC_x23_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x23_L1_EntryStatus30_OFFSET                     0
+#define D0F2xFC_x23_L1_EntryStatus30_WIDTH                      3
+#define D0F2xFC_x23_L1_EntryStatus30_MASK                       0x7
+#define D0F2xFC_x23_L1_EntryStatus31_OFFSET                     3
+#define D0F2xFC_x23_L1_EntryStatus31_WIDTH                      3
+#define D0F2xFC_x23_L1_EntryStatus31_MASK                       0x38
+#define D0F2xFC_x23_L1_Reserved_7_6_OFFSET                      6
+#define D0F2xFC_x23_L1_Reserved_7_6_WIDTH                       2
+#define D0F2xFC_x23_L1_Reserved_7_6_MASK                        0xc0
+#define D0F2xFC_x23_L1_InvalidationStatus_OFFSET                8
+#define D0F2xFC_x23_L1_InvalidationStatus_WIDTH                 8
+#define D0F2xFC_x23_L1_InvalidationStatus_MASK                  0xff00
+#define D0F2xFC_x23_L1_Reserved_31_16_OFFSET                    16
+#define D0F2xFC_x23_L1_Reserved_31_16_WIDTH                     16
+#define D0F2xFC_x23_L1_Reserved_31_16_MASK                      0xffff0000
+
+/// D0F2xFC_x23_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            EntryStatus30:3 ; ///<
+    UINT32                                            EntryStatus31:3 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                       InvalidationStatus:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x23_L1_STRUCT;
+
+// **** D0F2xFC_x22_L1 Register Definition ****
+// Address
+#define D0F2xFC_x22_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x22)
+
+// Type
+#define D0F2xFC_x22_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x22_L1_EntryStatus20_OFFSET                     0
+#define D0F2xFC_x22_L1_EntryStatus20_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus20_MASK                       0x7
+#define D0F2xFC_x22_L1_EntryStatus21_OFFSET                     3
+#define D0F2xFC_x22_L1_EntryStatus21_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus21_MASK                       0x38
+#define D0F2xFC_x22_L1_EntryStatus22_OFFSET                     6
+#define D0F2xFC_x22_L1_EntryStatus22_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus22_MASK                       0x1c0
+#define D0F2xFC_x22_L1_EntryStatus23_OFFSET                     9
+#define D0F2xFC_x22_L1_EntryStatus23_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus23_MASK                       0xe00
+#define D0F2xFC_x22_L1_EntryStatus24_OFFSET                     12
+#define D0F2xFC_x22_L1_EntryStatus24_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus24_MASK                       0x7000
+#define D0F2xFC_x22_L1_EntryStatus25_OFFSET                     15
+#define D0F2xFC_x22_L1_EntryStatus25_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus25_MASK                       0x38000
+#define D0F2xFC_x22_L1_EntryStatus26_OFFSET                     18
+#define D0F2xFC_x22_L1_EntryStatus26_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus26_MASK                       0x1c0000
+#define D0F2xFC_x22_L1_EntryStatus27_OFFSET                     21
+#define D0F2xFC_x22_L1_EntryStatus27_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus27_MASK                       0xe00000
+#define D0F2xFC_x22_L1_EntryStatus28_OFFSET                     24
+#define D0F2xFC_x22_L1_EntryStatus28_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus28_MASK                       0x7000000
+#define D0F2xFC_x22_L1_EntryStatus29_OFFSET                     27
+#define D0F2xFC_x22_L1_EntryStatus29_WIDTH                      3
+#define D0F2xFC_x22_L1_EntryStatus29_MASK                       0x38000000
+#define D0F2xFC_x22_L1_Reserved_31_30_OFFSET                    30
+#define D0F2xFC_x22_L1_Reserved_31_30_WIDTH                     2
+#define D0F2xFC_x22_L1_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F2xFC_x22_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            EntryStatus20:3 ; ///<
+    UINT32                                            EntryStatus21:3 ; ///<
+    UINT32                                            EntryStatus22:3 ; ///<
+    UINT32                                            EntryStatus23:3 ; ///<
+    UINT32                                            EntryStatus24:3 ; ///<
+    UINT32                                            EntryStatus25:3 ; ///<
+    UINT32                                            EntryStatus26:3 ; ///<
+    UINT32                                            EntryStatus27:3 ; ///<
+    UINT32                                            EntryStatus28:3 ; ///<
+    UINT32                                            EntryStatus29:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x22_L1_STRUCT;
+
+// **** D0F2xFC_x01_L1 Register Definition ****
+// Address
+#define D0F2xFC_x01_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x01)
+
+// Type
+#define D0F2xFC_x01_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x01_L1_L1PerfCount0_OFFSET                      0
+#define D0F2xFC_x01_L1_L1PerfCount0_WIDTH                       32
+#define D0F2xFC_x01_L1_L1PerfCount0_MASK                        0xffffffff
+
+/// D0F2xFC_x01_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1PerfCount0:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x01_L1_STRUCT;
+
+// **** D0F2xFC_x36_L1 Register Definition ****
+// Address
+#define D0F2xFC_x36_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x36)
+
+// Type
+#define D0F2xFC_x36_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x36_L1_L1CanonicalErrEn_OFFSET                  0
+#define D0F2xFC_x36_L1_L1CanonicalErrEn_WIDTH                   1
+#define D0F2xFC_x36_L1_L1CanonicalErrEn_MASK                    0x1
+#define D0F2xFC_x36_L1_Reserved_7_1_OFFSET                      1
+#define D0F2xFC_x36_L1_Reserved_7_1_WIDTH                       7
+#define D0F2xFC_x36_L1_Reserved_7_1_MASK                        0xfe
+#define D0F2xFC_x36_L1_L1GuestAddrMsk_OFFSET                    8
+#define D0F2xFC_x36_L1_L1GuestAddrMsk_WIDTH                     24
+#define D0F2xFC_x36_L1_L1GuestAddrMsk_MASK                      0xffffff00
+
+/// D0F2xFC_x36_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         L1CanonicalErrEn:1 ; ///<
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                           L1GuestAddrMsk:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x36_L1_STRUCT;
+
+// **** D0F2xFC_x0D_L1 Register Definition ****
+// Address
+#define D0F2xFC_x0D_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x0D)
+
+// Type
+#define D0F2xFC_x0D_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x0D_L1_VOQPortBits_OFFSET                       0
+#define D0F2xFC_x0D_L1_VOQPortBits_WIDTH                        3
+#define D0F2xFC_x0D_L1_VOQPortBits_MASK                         0x7
+#define D0F2xFC_x0D_L1_Reserved_3_3_OFFSET                      3
+#define D0F2xFC_x0D_L1_Reserved_3_3_WIDTH                       1
+#define D0F2xFC_x0D_L1_Reserved_3_3_MASK                        0x8
+#define D0F2xFC_x0D_L1_VOQFuncBits_OFFSET                       4
+#define D0F2xFC_x0D_L1_VOQFuncBits_WIDTH                        3
+#define D0F2xFC_x0D_L1_VOQFuncBits_MASK                         0x70
+#define D0F2xFC_x0D_L1_Reserved_7_7_OFFSET                      7
+#define D0F2xFC_x0D_L1_Reserved_7_7_WIDTH                       1
+#define D0F2xFC_x0D_L1_Reserved_7_7_MASK                        0x80
+#define D0F2xFC_x0D_L1_VOQXorMode_OFFSET                        8
+#define D0F2xFC_x0D_L1_VOQXorMode_WIDTH                         1
+#define D0F2xFC_x0D_L1_VOQXorMode_MASK                          0x100
+#define D0F2xFC_x0D_L1_CacheByPass_OFFSET                       9
+#define D0F2xFC_x0D_L1_CacheByPass_WIDTH                        1
+#define D0F2xFC_x0D_L1_CacheByPass_MASK                         0x200
+#define D0F2xFC_x0D_L1_L1CacheParityEn_OFFSET                   10
+#define D0F2xFC_x0D_L1_L1CacheParityEn_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1CacheParityEn_MASK                     0x400
+#define D0F2xFC_x0D_L1_L1ParityEn_OFFSET                        11
+#define D0F2xFC_x0D_L1_L1ParityEn_WIDTH                         1
+#define D0F2xFC_x0D_L1_L1ParityEn_MASK                          0x800
+#define D0F2xFC_x0D_L1_L1DTEDis_OFFSET                          12
+#define D0F2xFC_x0D_L1_L1DTEDis_WIDTH                           1
+#define D0F2xFC_x0D_L1_L1DTEDis_MASK                            0x1000
+#define D0F2xFC_x0D_L1_BlockL1Dis_OFFSET                        13
+#define D0F2xFC_x0D_L1_BlockL1Dis_WIDTH                         1
+#define D0F2xFC_x0D_L1_BlockL1Dis_MASK                          0x2000
+#define D0F2xFC_x0D_L1_WqEntrydis_OFFSET                        14
+#define D0F2xFC_x0D_L1_WqEntrydis_WIDTH                         5
+#define D0F2xFC_x0D_L1_WqEntrydis_MASK                          0x7c000
+#define D0F2xFC_x0D_L1_AtsNobufferInsert_OFFSET                 19
+#define D0F2xFC_x0D_L1_AtsNobufferInsert_WIDTH                  1
+#define D0F2xFC_x0D_L1_AtsNobufferInsert_MASK                   0x80000
+#define D0F2xFC_x0D_L1_SndFilterDis_OFFSET                      20
+#define D0F2xFC_x0D_L1_SndFilterDis_WIDTH                       1
+#define D0F2xFC_x0D_L1_SndFilterDis_MASK                        0x100000
+#define D0F2xFC_x0D_L1_L1orderEn_OFFSET                         21
+#define D0F2xFC_x0D_L1_L1orderEn_WIDTH                          1
+#define D0F2xFC_x0D_L1_L1orderEn_MASK                           0x200000
+#define D0F2xFC_x0D_L1_L1CacheInvAllEn_OFFSET                   22
+#define D0F2xFC_x0D_L1_L1CacheInvAllEn_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1CacheInvAllEn_MASK                     0x400000
+#define D0F2xFC_x0D_L1_SelectTimeoutPulse_OFFSET                23
+#define D0F2xFC_x0D_L1_SelectTimeoutPulse_WIDTH                 3
+#define D0F2xFC_x0D_L1_SelectTimeoutPulse_MASK                  0x3800000
+#define D0F2xFC_x0D_L1_L1CacheSelReqid_OFFSET                   26
+#define D0F2xFC_x0D_L1_L1CacheSelReqid_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1CacheSelReqid_MASK                     0x4000000
+#define D0F2xFC_x0D_L1_L1CacheSelInterleave_OFFSET              27
+#define D0F2xFC_x0D_L1_L1CacheSelInterleave_WIDTH               1
+#define D0F2xFC_x0D_L1_L1CacheSelInterleave_MASK                0x8000000
+#define D0F2xFC_x0D_L1_PretransNovaFilteren_OFFSET              28
+#define D0F2xFC_x0D_L1_PretransNovaFilteren_WIDTH               1
+#define D0F2xFC_x0D_L1_PretransNovaFilteren_MASK                0x10000000
+#define D0F2xFC_x0D_L1_Untrans2mFilteren_OFFSET                 29
+#define D0F2xFC_x0D_L1_Untrans2mFilteren_WIDTH                  1
+#define D0F2xFC_x0D_L1_Untrans2mFilteren_MASK                   0x20000000
+#define D0F2xFC_x0D_L1_L1DebugCntrMode_OFFSET                   30
+#define D0F2xFC_x0D_L1_L1DebugCntrMode_WIDTH                    1
+#define D0F2xFC_x0D_L1_L1DebugCntrMode_MASK                     0x40000000
+#define D0F2xFC_x0D_L1_Reserved_31_31_OFFSET                    31
+#define D0F2xFC_x0D_L1_Reserved_31_31_WIDTH                     1
+#define D0F2xFC_x0D_L1_Reserved_31_31_MASK                      0x80000000
+
+/// D0F2xFC_x0D_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              VOQPortBits:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                              VOQFuncBits:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                               VOQXorMode:1 ; ///<
+    UINT32                                              CacheByPass:1 ; ///<
+    UINT32                                          L1CacheParityEn:1 ; ///<
+    UINT32                                               L1ParityEn:1 ; ///<
+    UINT32                                                 L1DTEDis:1 ; ///<
+    UINT32                                               BlockL1Dis:1 ; ///<
+    UINT32                                               WqEntrydis:5 ; ///<
+    UINT32                                        AtsNobufferInsert:1 ; ///<
+    UINT32                                             SndFilterDis:1 ; ///<
+    UINT32                                                L1orderEn:1 ; ///<
+    UINT32                                          L1CacheInvAllEn:1 ; ///<
+    UINT32                                       SelectTimeoutPulse:3 ; ///<
+    UINT32                                          L1CacheSelReqid:1 ; ///<
+    UINT32                                     L1CacheSelInterleave:1 ; ///<
+    UINT32                                     PretransNovaFilteren:1 ; ///<
+    UINT32                                        Untrans2mFilteren:1 ; ///<
+    UINT32                                          L1DebugCntrMode:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x0D_L1_STRUCT;
+
+// **** D0F2xFC_x33_L1 Register Definition ****
+// Address
+#define D0F2xFC_x33_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x33)
+
+// Type
+#define D0F2xFC_x33_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x33_L1_L1ClkgateLen_OFFSET                      0
+#define D0F2xFC_x33_L1_L1ClkgateLen_WIDTH                       2
+#define D0F2xFC_x33_L1_L1ClkgateLen_MASK                        0x3
+#define D0F2xFC_x33_L1_Reserved_3_2_OFFSET                      2
+#define D0F2xFC_x33_L1_Reserved_3_2_WIDTH                       2
+#define D0F2xFC_x33_L1_Reserved_3_2_MASK                        0xc
+#define D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET                    4
+#define D0F2xFC_x33_L1_L1DmaClkgateEn_WIDTH                     1
+#define D0F2xFC_x33_L1_L1DmaClkgateEn_MASK                      0x10
+#define D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET                  5
+#define D0F2xFC_x33_L1_L1CacheClkgateEn_WIDTH                   1
+#define D0F2xFC_x33_L1_L1CacheClkgateEn_MASK                    0x20
+#define D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET                  6
+#define D0F2xFC_x33_L1_L1CpslvClkgateEn_WIDTH                   1
+#define D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK                    0x40
+#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET               7
+#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_WIDTH                1
+#define D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK                 0x80
+#define D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET                   8
+#define D0F2xFC_x33_L1_L1PerfClkgateEn_WIDTH                    1
+#define D0F2xFC_x33_L1_L1PerfClkgateEn_MASK                     0x100
+#define D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET                 9
+#define D0F2xFC_x33_L1_L1MemoryClkgateEn_WIDTH                  1
+#define D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK                   0x200
+#define D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET                    10
+#define D0F2xFC_x33_L1_L1RegClkgateEn_WIDTH                     1
+#define D0F2xFC_x33_L1_L1RegClkgateEn_MASK                      0x400
+#define D0F2xFC_x33_L1_L1HostreqClkgateEn_OFFSET                11
+#define D0F2xFC_x33_L1_L1HostreqClkgateEn_WIDTH                 1
+#define D0F2xFC_x33_L1_L1HostreqClkgateEn_MASK                  0x800
+#define D0F2xFC_x33_L1_Reserved_30_12_OFFSET                    12
+#define D0F2xFC_x33_L1_Reserved_30_12_WIDTH                     19
+#define D0F2xFC_x33_L1_Reserved_30_12_MASK                      0x7ffff000
+#define D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET                     31
+#define D0F2xFC_x33_L1_L1L2ClkgateEn_WIDTH                      1
+#define D0F2xFC_x33_L1_L1L2ClkgateEn_MASK                       0x80000000
+
+/// D0F2xFC_x33_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1ClkgateLen:2 ; ///<
+    UINT32                                             Reserved_3_2:2 ; ///<
+    UINT32                                           L1DmaClkgateEn:1 ; ///<
+    UINT32                                         L1CacheClkgateEn:1 ; ///<
+    UINT32                                         L1CpslvClkgateEn:1 ; ///<
+    UINT32                                      L1DmaInputClkgateEn:1 ; ///<
+    UINT32                                          L1PerfClkgateEn:1 ; ///<
+    UINT32                                        L1MemoryClkgateEn:1 ; ///<
+    UINT32                                           L1RegClkgateEn:1 ; ///<
+    UINT32                                       L1HostreqClkgateEn:1 ; ///<
+    UINT32                                           Reserved_30_12:19; ///<
+    UINT32                                            L1L2ClkgateEn:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x33_L1_STRUCT;
+
+
+// **** D0F2xFC_x21_L1 Register Definition ****
+// Address
+#define D0F2xFC_x21_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x21)
+
+// Type
+#define D0F2xFC_x21_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x21_L1_EntryStatus10_OFFSET                     0
+#define D0F2xFC_x21_L1_EntryStatus10_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus10_MASK                       0x7
+#define D0F2xFC_x21_L1_EntryStatus11_OFFSET                     3
+#define D0F2xFC_x21_L1_EntryStatus11_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus11_MASK                       0x38
+#define D0F2xFC_x21_L1_EntryStatus12_OFFSET                     6
+#define D0F2xFC_x21_L1_EntryStatus12_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus12_MASK                       0x1c0
+#define D0F2xFC_x21_L1_EntryStatus13_OFFSET                     9
+#define D0F2xFC_x21_L1_EntryStatus13_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus13_MASK                       0xe00
+#define D0F2xFC_x21_L1_EntryStatus14_OFFSET                     12
+#define D0F2xFC_x21_L1_EntryStatus14_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus14_MASK                       0x7000
+#define D0F2xFC_x21_L1_EntryStatus15_OFFSET                     15
+#define D0F2xFC_x21_L1_EntryStatus15_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus15_MASK                       0x38000
+#define D0F2xFC_x21_L1_EntryStatus16_OFFSET                     18
+#define D0F2xFC_x21_L1_EntryStatus16_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus16_MASK                       0x1c0000
+#define D0F2xFC_x21_L1_EntryStatus17_OFFSET                     21
+#define D0F2xFC_x21_L1_EntryStatus17_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus17_MASK                       0xe00000
+#define D0F2xFC_x21_L1_EntryStatus18_OFFSET                     24
+#define D0F2xFC_x21_L1_EntryStatus18_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus18_MASK                       0x7000000
+#define D0F2xFC_x21_L1_EntryStatus19_OFFSET                     27
+#define D0F2xFC_x21_L1_EntryStatus19_WIDTH                      3
+#define D0F2xFC_x21_L1_EntryStatus19_MASK                       0x38000000
+#define D0F2xFC_x21_L1_Reserved_31_30_OFFSET                    30
+#define D0F2xFC_x21_L1_Reserved_31_30_WIDTH                     2
+#define D0F2xFC_x21_L1_Reserved_31_30_MASK                      0xc0000000
+
+/// D0F2xFC_x21_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            EntryStatus10:3 ; ///<
+    UINT32                                            EntryStatus11:3 ; ///<
+    UINT32                                            EntryStatus12:3 ; ///<
+    UINT32                                            EntryStatus13:3 ; ///<
+    UINT32                                            EntryStatus14:3 ; ///<
+    UINT32                                            EntryStatus15:3 ; ///<
+    UINT32                                            EntryStatus16:3 ; ///<
+    UINT32                                            EntryStatus17:3 ; ///<
+    UINT32                                            EntryStatus18:3 ; ///<
+    UINT32                                            EntryStatus19:3 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x21_L1_STRUCT;
+
+// **** D0F2xFC_x00_L1 Register Definition ****
+// Address
+#define D0F2xFC_x00_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x00)
+
+// Type
+#define D0F2xFC_x00_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x00_L1_L1PerfEvent0_OFFSET                      0
+#define D0F2xFC_x00_L1_L1PerfEvent0_WIDTH                       8
+#define D0F2xFC_x00_L1_L1PerfEvent0_MASK                        0xff
+#define D0F2xFC_x00_L1_L1PerfEvent1_OFFSET                      8
+#define D0F2xFC_x00_L1_L1PerfEvent1_WIDTH                       8
+#define D0F2xFC_x00_L1_L1PerfEvent1_MASK                        0xff00
+#define D0F2xFC_x00_L1_L1PerfCountHi0_OFFSET                    16
+#define D0F2xFC_x00_L1_L1PerfCountHi0_WIDTH                     8
+#define D0F2xFC_x00_L1_L1PerfCountHi0_MASK                      0xff0000
+#define D0F2xFC_x00_L1_L1PerfCountHi1_OFFSET                    24
+#define D0F2xFC_x00_L1_L1PerfCountHi1_WIDTH                     8
+#define D0F2xFC_x00_L1_L1PerfCountHi1_MASK                      0xff000000
+
+/// D0F2xFC_x00_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1PerfEvent0:8 ; ///<
+    UINT32                                             L1PerfEvent1:8 ; ///<
+    UINT32                                           L1PerfCountHi0:8 ; ///<
+    UINT32                                           L1PerfCountHi1:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x00_L1_STRUCT;
+
+// **** D0F2xFC_x02_L1 Register Definition ****
+// Address
+#define D0F2xFC_x02_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x02)
+
+// Type
+#define D0F2xFC_x02_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x02_L1_L1PerfCount1_OFFSET                      0
+#define D0F2xFC_x02_L1_L1PerfCount1_WIDTH                       32
+#define D0F2xFC_x02_L1_L1PerfCount1_MASK                        0xffffffff
+
+/// D0F2xFC_x02_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             L1PerfCount1:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x02_L1_STRUCT;
+
+
+
+// **** D0F2xFC_x07_L1 Register Definition ****
+// Address
+#define D0F2xFC_x07_L1_ADDRESS(Sel)                             ((Sel << 16) | 0x07)
+
+// Type
+#define D0F2xFC_x07_L1_TYPE                                     TYPE_D0F2xFC
+// Field Data
+#define D0F2xFC_x07_L1_PhantomFuncEn_OFFSET                     0
+#define D0F2xFC_x07_L1_PhantomFuncEn_WIDTH                      1
+#define D0F2xFC_x07_L1_PhantomFuncEn_MASK                       0x1
+#define D0F2xFC_x07_L1_Reserved_10_1_OFFSET                     1
+#define D0F2xFC_x07_L1_Reserved_10_1_WIDTH                      10
+#define D0F2xFC_x07_L1_Reserved_10_1_MASK                       0x7fe
+#define D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET                   11
+#define D0F2xFC_x07_L1_SpecReqFilterEn_WIDTH                    1
+#define D0F2xFC_x07_L1_SpecReqFilterEn_MASK                     0x800
+#define D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET                       12
+#define D0F2xFC_x07_L1_AtsSeqNumEn_WIDTH                        1
+#define D0F2xFC_x07_L1_AtsSeqNumEn_MASK                         0x1000
+#define D0F2xFC_x07_L1_Reserved_13_13_OFFSET                    13
+#define D0F2xFC_x07_L1_Reserved_13_13_WIDTH                     1
+#define D0F2xFC_x07_L1_Reserved_13_13_MASK                      0x2000
+#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET             14
+#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_WIDTH              1
+#define D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK               0x4000
+#define D0F2xFC_x07_L1_Reserved_16_15_OFFSET                    15
+#define D0F2xFC_x07_L1_Reserved_16_15_WIDTH                     2
+#define D0F2xFC_x07_L1_Reserved_16_15_MASK                      0x18000
+#define D0F2xFC_x07_L1_L1NwEn_OFFSET                            17
+#define D0F2xFC_x07_L1_L1NwEn_WIDTH                             1
+#define D0F2xFC_x07_L1_L1NwEn_MASK                              0x20000
+#define D0F2xFC_x07_L1_Reserved_31_18_OFFSET                    18
+#define D0F2xFC_x07_L1_Reserved_31_18_WIDTH                     14
+#define D0F2xFC_x07_L1_Reserved_31_18_MASK                      0xfffc0000
+
+/// D0F2xFC_x07_L1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            PhantomFuncEn:1 ; ///<
+    UINT32                                            Reserved_10_1:10; ///<
+    UINT32                                          SpecReqFilterEn:1 ; ///<
+    UINT32                                              AtsSeqNumEn:1 ; ///<
+    UINT32                                           Reserved_13_13:1 ; ///<
+    UINT32                                    AtsPhysPageOverlapDis:1 ; ///<
+    UINT32                                           Reserved_16_15:2 ; ///<
+    UINT32                                                   L1NwEn:1 ; ///<
+    UINT32                                           Reserved_31_18:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F2xFC_x07_L1_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct1_mp0_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp0_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct1_mp0_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct1_mp0_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp0_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct1_mp0_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp0_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct1_mp0_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct0_mp0_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp0_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct0_mp0_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct0_mp0_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp0_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct0_mp0_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp0_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct0_mp0_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct1_mp1_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp1_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct1_mp1_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct1_mp1_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp1_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct1_mp1_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct1_mp1_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct1_mp1_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct1_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0000_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0000_dct0_mp1_ADDRESS                    0x0
+
+// Type
+#define D18F2x9C_x0000_0000_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_OFFSET         0
+#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp1_CkeDrvStren_MASK           0x7
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_OFFSET        3
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_3_3_MASK          0x8
+#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_OFFSET       4
+#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_WIDTH        3
+#define D18F2x9C_x0000_0000_dct0_mp1_CsOdtDrvStren_MASK         0x70
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_OFFSET     8
+#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_WIDTH      3
+#define D18F2x9C_x0000_0000_dct0_mp1_AddrCmdDrvStren_MASK       0x700
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_OFFSET      11
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_11_11_MASK        0x800
+#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_OFFSET         12
+#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp1_ClkDrvStren_MASK           0x7000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_OFFSET      15
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_15_15_MASK        0x8000
+#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_OFFSET        16
+#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_WIDTH         3
+#define D18F2x9C_x0000_0000_dct0_mp1_DataDrvStren_MASK          0x70000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_OFFSET      19
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_19_19_MASK        0x80000
+#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_OFFSET         20
+#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_WIDTH          3
+#define D18F2x9C_x0000_0000_dct0_mp1_DqsDrvStren_MASK           0x700000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_OFFSET      23
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_WIDTH       5
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_27_23_MASK        0xf800000
+#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_OFFSET             28
+#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_WIDTH              3
+#define D18F2x9C_x0000_0000_dct0_mp1_ProcOdt_MASK               0x70000000
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0000_dct0_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0000_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              CkeDrvStren:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            CsOdtDrvStren:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          AddrCmdDrvStren:3 ; ///<
+    UINT32                                           Reserved_11_11:1 ; ///<
+    UINT32                                              ClkDrvStren:3 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                             DataDrvStren:3 ; ///<
+    UINT32                                           Reserved_19_19:1 ; ///<
+    UINT32                                              DqsDrvStren:3 ; ///<
+    UINT32                                           Reserved_27_23:5 ; ///<
+    UINT32                                                  ProcOdt:3 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0000_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct1_mp0_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct0_mp0_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct1_mp1_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0001_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0001_dct0_mp1_ADDRESS                    0x1
+
+// Type
+#define D18F2x9C_x0000_0001_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0001_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0001_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0001_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct1_mp1_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct1_mp0_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct0_mp1_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0002_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0002_dct0_mp0_ADDRESS                    0x2
+
+// Type
+#define D18F2x9C_x0000_0002_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0002_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0002_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0002_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct1_mp1_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct1_mp1_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct1_mp1_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct1_mp1_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct1_mp1_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct0_mp0_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct0_mp0_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct0_mp0_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct0_mp0_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct0_mp0_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct0_mp1_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct0_mp1_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct0_mp1_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct0_mp1_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct0_mp1_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0004_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0004_dct1_mp0_ADDRESS                    0x4
+
+// Type
+#define D18F2x9C_x0000_0004_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_OFFSET        0
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_WIDTH         5
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeFineDelay_MASK          0x1f
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_OFFSET            5
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_WIDTH             1
+#define D18F2x9C_x0000_0004_dct1_mp0_CkeSetup_MASK              0x20
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_OFFSET        6
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_WIDTH         2
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_7_6_MASK          0xc0
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_OFFSET      8
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_WIDTH       5
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtFineDelay_MASK        0x1f00
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_OFFSET          13
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_WIDTH           1
+#define D18F2x9C_x0000_0004_dct1_mp0_CsOdtSetup_MASK            0x2000
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_OFFSET      14
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_WIDTH       2
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_15_14_MASK        0xc000
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_OFFSET    16
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_WIDTH     5
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdFineDelay_MASK      0x1f0000
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_OFFSET        21
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_WIDTH         1
+#define D18F2x9C_x0000_0004_dct1_mp0_AddrCmdSetup_MASK          0x200000
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_OFFSET      22
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_WIDTH       10
+#define D18F2x9C_x0000_0004_dct1_mp0_Reserved_31_22_MASK        0xffc00000
+
+/// D18F2x9C_x0000_0004_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             CkeFineDelay:5 ; ///<
+    UINT32                                                 CkeSetup:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                           CsOdtFineDelay:5 ; ///<
+    UINT32                                               CsOdtSetup:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                         AddrCmdFineDelay:5 ; ///<
+    UINT32                                             AddrCmdSetup:1 ; ///<
+    UINT32                                           Reserved_31_22:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0004_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct0_mp0_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct1_mp0_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct1_mp1_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0005_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0005_dct0_mp1_ADDRESS                    0x5
+
+// Type
+#define D18F2x9C_x0000_0005_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0005_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0005_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0005_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0005_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct1_mp0_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct0_mp1_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct1_mp1_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0006_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0006_dct0_mp0_ADDRESS                    0x6
+
+// Type
+#define D18F2x9C_x0000_0006_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0006_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0006_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0006_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0006_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct0_mp1_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp1_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp1_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp1_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct0_mp1_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct0_mp1_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp1_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct0_mp1_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct0_mp1_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp1_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct0_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct0_mp0_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp0_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp0_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct0_mp0_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct0_mp0_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct0_mp0_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct0_mp0_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct0_mp0_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct0_mp0_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct0_mp0_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct0_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct1_mp0_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp0_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp0_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp0_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct1_mp0_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct1_mp0_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp0_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct1_mp0_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct1_mp0_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp0_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct1_mp0_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0008_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0008_dct1_mp1_ADDRESS                    0x8
+
+// Type
+#define D18F2x9C_x0000_0008_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_OFFSET           0
+#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp1_WrtLvTrEn_MASK             0x1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_OFFSET        1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_1_1_MASK          0x2
+#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_OFFSET         2
+#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp1_TrNibbleSel_MASK           0x4
+#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_OFFSET        3
+#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_WIDTH         1
+#define D18F2x9C_x0000_0008_dct1_mp1_PhyFenceTrEn_MASK          0x8
+#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_OFFSET           4
+#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_WIDTH            2
+#define D18F2x9C_x0000_0008_dct1_mp1_TrChipSel_MASK             0x30
+#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_OFFSET          6
+#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_WIDTH           2
+#define D18F2x9C_x0000_0008_dct1_mp1_FenceTrSel_MASK            0xc0
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_OFFSET             8
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_WIDTH              4
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdt_MASK               0xf00
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_OFFSET           12
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_WIDTH            1
+#define D18F2x9C_x0000_0008_dct1_mp1_WrLvOdtEn_MASK             0x1000
+#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_OFFSET          13
+#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_WIDTH           1
+#define D18F2x9C_x0000_0008_dct1_mp1_DqsRcvTrEn_MASK            0x2000
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_OFFSET      14
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_WIDTH       15
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_28_14_MASK        0x1fffc000
+#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_OFFSET 29
+#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_WIDTH  1
+#define D18F2x9C_x0000_0008_dct1_mp1_DisablePredriverCal_MASK   0x20000000
+#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_OFFSET         30
+#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_WIDTH          1
+#define D18F2x9C_x0000_0008_dct1_mp1_DisAutoComp_MASK           0x40000000
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_OFFSET      31
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_WIDTH       1
+#define D18F2x9C_x0000_0008_dct1_mp1_Reserved_31_31_MASK        0x80000000
+
+/// D18F2x9C_x0000_0008_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                WrtLvTrEn:1 ; ///<
+    UINT32                                             Reserved_1_1:1 ; ///<
+    UINT32                                              TrNibbleSel:1 ; ///<
+    UINT32                                             PhyFenceTrEn:1 ; ///<
+    UINT32                                                TrChipSel:2 ; ///<
+    UINT32                                               FenceTrSel:2 ; ///<
+    UINT32                                                  WrLvOdt:4 ; ///<
+    UINT32                                                WrLvOdtEn:1 ; ///<
+    UINT32                                               DqsRcvTrEn:1 ; ///<
+    UINT32                                           Reserved_28_14:15; ///<
+    UINT32                                      DisablePredriverCal:1 ; ///<
+    UINT32                                              DisAutoComp:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0008_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_000B_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000B_dct0_ADDRESS                        0xb
+
+// Type
+#define D18F2x9C_x0000_000B_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_OFFSET           0
+#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_WIDTH            23
+#define D18F2x9C_x0000_000B_dct0_Reserved_22_0_MASK             0x7fffff
+#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_OFFSET      23
+#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_WIDTH       1
+#define D18F2x9C_x0000_000B_dct0_PhySelfRefreshMode_MASK        0x800000
+#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_OFFSET          24
+#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_WIDTH           2
+#define D18F2x9C_x0000_000B_dct0_Reserved_25_24_MASK            0x3000000
+#define D18F2x9C_x0000_000B_dct0_PhyPS_OFFSET                   26
+#define D18F2x9C_x0000_000B_dct0_PhyPS_WIDTH                    1
+#define D18F2x9C_x0000_000B_dct0_PhyPS_MASK                     0x4000000
+#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_OFFSET          27
+#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_WIDTH           3
+#define D18F2x9C_x0000_000B_dct0_Reserved_29_27_MASK            0x38000000
+#define D18F2x9C_x0000_000B_dct0_PhyPSReq_OFFSET                30
+#define D18F2x9C_x0000_000B_dct0_PhyPSReq_WIDTH                 1
+#define D18F2x9C_x0000_000B_dct0_PhyPSReq_MASK                  0x40000000
+#define D18F2x9C_x0000_000B_dct0_DynModeChange_OFFSET           31
+#define D18F2x9C_x0000_000B_dct0_DynModeChange_WIDTH            1
+#define D18F2x9C_x0000_000B_dct0_DynModeChange_MASK             0x80000000
+
+/// D18F2x9C_x0000_000B_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                       PhySelfRefreshMode:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    PhyPS:1 ; ///<
+    UINT32                                           Reserved_29_27:3 ; ///<
+    UINT32                                                 PhyPSReq:1 ; ///<
+    UINT32                                            DynModeChange:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000B_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_000B_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000B_dct1_ADDRESS                        0xb
+
+// Type
+#define D18F2x9C_x0000_000B_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_OFFSET           0
+#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_WIDTH            23
+#define D18F2x9C_x0000_000B_dct1_Reserved_22_0_MASK             0x7fffff
+#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_OFFSET      23
+#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_WIDTH       1
+#define D18F2x9C_x0000_000B_dct1_PhySelfRefreshMode_MASK        0x800000
+#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_OFFSET          24
+#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_WIDTH           2
+#define D18F2x9C_x0000_000B_dct1_Reserved_25_24_MASK            0x3000000
+#define D18F2x9C_x0000_000B_dct1_PhyPS_OFFSET                   26
+#define D18F2x9C_x0000_000B_dct1_PhyPS_WIDTH                    1
+#define D18F2x9C_x0000_000B_dct1_PhyPS_MASK                     0x4000000
+#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_OFFSET          27
+#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_WIDTH           3
+#define D18F2x9C_x0000_000B_dct1_Reserved_29_27_MASK            0x38000000
+#define D18F2x9C_x0000_000B_dct1_PhyPSReq_OFFSET                30
+#define D18F2x9C_x0000_000B_dct1_PhyPSReq_WIDTH                 1
+#define D18F2x9C_x0000_000B_dct1_PhyPSReq_MASK                  0x40000000
+#define D18F2x9C_x0000_000B_dct1_DynModeChange_OFFSET           31
+#define D18F2x9C_x0000_000B_dct1_DynModeChange_WIDTH            1
+#define D18F2x9C_x0000_000B_dct1_DynModeChange_MASK             0x80000000
+
+/// D18F2x9C_x0000_000B_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_22_0:23; ///<
+    UINT32                                       PhySelfRefreshMode:1 ; ///<
+    UINT32                                           Reserved_25_24:2 ; ///<
+    UINT32                                                    PhyPS:1 ; ///<
+    UINT32                                           Reserved_29_27:3 ; ///<
+    UINT32                                                 PhyPSReq:1 ; ///<
+    UINT32                                            DynModeChange:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000B_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_000C_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000C_dct1_ADDRESS                        0xc
+
+// Type
+#define D18F2x9C_x0000_000C_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_000C_dct1_ChipSelTri_OFFSET              0
+#define D18F2x9C_x0000_000C_dct1_ChipSelTri_WIDTH               8
+#define D18F2x9C_x0000_000C_dct1_ChipSelTri_MASK                0xff
+#define D18F2x9C_x0000_000C_dct1_ODTTri_OFFSET                  8
+#define D18F2x9C_x0000_000C_dct1_ODTTri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct1_ODTTri_MASK                    0xf00
+#define D18F2x9C_x0000_000C_dct1_CKETri_OFFSET                  12
+#define D18F2x9C_x0000_000C_dct1_CKETri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct1_CKETri_MASK                    0xf000
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_OFFSET     16
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_WIDTH      5
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxPad_MASK       0x1f0000
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_OFFSET     21
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdRxDll_MASK       0x3e00000
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_OFFSET     26
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct1_FenceThresholdTxDll_MASK       0x7c000000
+#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_000C_dct1_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_000C_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               ChipSelTri:8 ; ///<
+    UINT32                                                   ODTTri:4 ; ///<
+    UINT32                                                   CKETri:4 ; ///<
+    UINT32                                      FenceThresholdTxPad:5 ; ///<
+    UINT32                                      FenceThresholdRxDll:5 ; ///<
+    UINT32                                      FenceThresholdTxDll:5 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000C_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_000C_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000C_dct0_ADDRESS                        0xc
+
+// Type
+#define D18F2x9C_x0000_000C_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_000C_dct0_ChipSelTri_OFFSET              0
+#define D18F2x9C_x0000_000C_dct0_ChipSelTri_WIDTH               8
+#define D18F2x9C_x0000_000C_dct0_ChipSelTri_MASK                0xff
+#define D18F2x9C_x0000_000C_dct0_ODTTri_OFFSET                  8
+#define D18F2x9C_x0000_000C_dct0_ODTTri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct0_ODTTri_MASK                    0xf00
+#define D18F2x9C_x0000_000C_dct0_CKETri_OFFSET                  12
+#define D18F2x9C_x0000_000C_dct0_CKETri_WIDTH                   4
+#define D18F2x9C_x0000_000C_dct0_CKETri_MASK                    0xf000
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_OFFSET     16
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_WIDTH      5
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxPad_MASK       0x1f0000
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_OFFSET     21
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdRxDll_MASK       0x3e00000
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_OFFSET     26
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_WIDTH      5
+#define D18F2x9C_x0000_000C_dct0_FenceThresholdTxDll_MASK       0x7c000000
+#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_000C_dct0_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_000C_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               ChipSelTri:8 ; ///<
+    UINT32                                                   ODTTri:4 ; ///<
+    UINT32                                                   CKETri:4 ; ///<
+    UINT32                                      FenceThresholdTxPad:5 ; ///<
+    UINT32                                      FenceThresholdRxDll:5 ; ///<
+    UINT32                                      FenceThresholdTxDll:5 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000C_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct0_mp1_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp1_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp1_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp1_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp1_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp1_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp1_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct1_mp1_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp1_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp1_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp1_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp1_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp1_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp1_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct0_mp0_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp0_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp0_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp0_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct0_mp0_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct0_mp0_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct0_mp0_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_000D_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_000D_dct1_mp0_ADDRESS                    0xd
+
+// Type
+#define D18F2x9C_x0000_000D_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_OFFSET   0
+#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp0_TxMaxDurDllNoLock_MASK     0xf
+#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_OFFSET       4
+#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp0_TxCPUpdPeriod_MASK         0x70
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_OFFSET        7
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_WIDTH         1
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_7_7_MASK          0x80
+#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_OFFSET     8
+#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp0_TxDLLWakeupTime_MASK       0x300
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_OFFSET   16
+#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_WIDTH    4
+#define D18F2x9C_x0000_000D_dct1_mp0_RxMaxDurDllNoLock_MASK     0xf0000
+#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_OFFSET       20
+#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_WIDTH        3
+#define D18F2x9C_x0000_000D_dct1_mp0_RxCPUpdPeriod_MASK         0x700000
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_OFFSET      23
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_WIDTH       1
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_23_23_MASK        0x800000
+#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_OFFSET     24
+#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_WIDTH      2
+#define D18F2x9C_x0000_000D_dct1_mp0_RxDLLWakeupTime_MASK       0x3000000
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_000D_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_000D_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        TxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            TxCPUpdPeriod:3 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                          TxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                        RxMaxDurDllNoLock:4 ; ///<
+    UINT32                                            RxCPUpdPeriod:3 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                          RxDLLWakeupTime:2 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_000D_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct0_mp1_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct1_mp0_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct0_mp0_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0010_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0010_dct1_mp1_ADDRESS                    0x10
+
+// Type
+#define D18F2x9C_x0000_0010_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0010_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0010_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0010_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0010_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct1_mp0_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct1_mp1_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct0_mp0_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0011_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0011_dct0_mp1_ADDRESS                    0x11
+
+// Type
+#define D18F2x9C_x0000_0011_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0011_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0011_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0011_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0011_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct1_mp1_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct1_mp0_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct0_mp0_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0013_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0013_dct0_mp1_ADDRESS                    0x13
+
+// Type
+#define D18F2x9C_x0000_0013_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0013_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0013_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0013_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0013_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct1_mp0_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct0_mp1_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct0_mp0_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0014_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0014_dct1_mp1_ADDRESS                    0x14
+
+// Type
+#define D18F2x9C_x0000_0014_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0014_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0014_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0014_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0014_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct0_mp0_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct1_mp1_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct1_mp0_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0016_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0016_dct0_mp1_ADDRESS                    0x16
+
+// Type
+#define D18F2x9C_x0000_0016_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0016_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0016_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0016_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0016_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct0_mp1_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct0_mp0_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct1_mp1_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0017_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0017_dct1_mp0_ADDRESS                    0x17
+
+// Type
+#define D18F2x9C_x0000_0017_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0017_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0017_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0017_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0017_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct1_mp0_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct0_mp0_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct0_mp1_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0019_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0019_dct1_mp1_ADDRESS                    0x19
+
+// Type
+#define D18F2x9C_x0000_0019_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0019_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0019_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0019_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0019_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct1_mp1_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct1_mp0_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct0_mp1_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_001A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_001A_dct0_mp0_ADDRESS                    0x1a
+
+// Type
+#define D18F2x9C_x0000_001A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_001A_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_001A_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_001A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_001A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct0_mp1_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct1_mp0_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct1_mp1_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0020_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0020_dct0_mp0_ADDRESS                    0x20
+
+// Type
+#define D18F2x9C_x0000_0020_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0020_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0020_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0020_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0020_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct0_mp1_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct1_mp0_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct1_mp1_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0021_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0021_dct0_mp0_ADDRESS                    0x21
+
+// Type
+#define D18F2x9C_x0000_0021_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0021_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0021_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0021_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0021_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct0_mp1_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct1_mp0_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct1_mp1_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0023_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0023_dct0_mp0_ADDRESS                    0x23
+
+// Type
+#define D18F2x9C_x0000_0023_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0023_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0023_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0023_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0023_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct1_mp1_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct1_mp0_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct0_mp1_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0024_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0024_dct0_mp0_ADDRESS                    0x24
+
+// Type
+#define D18F2x9C_x0000_0024_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0024_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0024_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0024_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0024_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct1_mp0_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct0_mp0_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct1_mp1_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0026_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0026_dct0_mp1_ADDRESS                    0x26
+
+// Type
+#define D18F2x9C_x0000_0026_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0026_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0026_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0026_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0026_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct0_mp1_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct1_mp0_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct0_mp0_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0027_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0027_dct1_mp1_ADDRESS                    0x27
+
+// Type
+#define D18F2x9C_x0000_0027_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0027_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0027_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0027_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0027_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct0_mp0_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct0_mp1_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct1_mp0_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0029_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0029_dct1_mp1_ADDRESS                    0x29
+
+// Type
+#define D18F2x9C_x0000_0029_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_0029_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_0029_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_0029_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0029_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct1_mp1_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct1_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct0_mp0_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct0_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct1_mp0_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct1_mp0_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct1_mp0_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_002A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_002A_dct0_mp1_ADDRESS                    0x2a
+
+// Type
+#define D18F2x9C_x0000_002A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_OFFSET   0
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_WIDTH    5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay_MASK     0x1f
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_OFFSET  5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay_MASK    0x3e0
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_OFFSET      10
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_15_10_MASK        0xfc00
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_OFFSET  16
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_WIDTH   5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnFineDelay1_MASK    0x1f0000
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_OFFSET 21
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_WIDTH  5
+#define D18F2x9C_x0000_002A_dct0_mp1_DqsRcvEnGrossDelay1_MASK   0x3e00000
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_OFFSET      26
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_WIDTH       6
+#define D18F2x9C_x0000_002A_dct0_mp1_Reserved_31_26_MASK        0xfc000000
+
+/// D18F2x9C_x0000_002A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        DqsRcvEnFineDelay:5 ; ///<
+    UINT32                                       DqsRcvEnGrossDelay:5 ; ///<
+    UINT32                                           Reserved_15_10:6 ; ///<
+    UINT32                                       DqsRcvEnFineDelay1:5 ; ///<
+    UINT32                                      DqsRcvEnGrossDelay1:5 ; ///<
+    UINT32                                           Reserved_31_26:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_002A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct1_mp1_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct0_mp1_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct0_mp0_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0030_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0030_dct1_mp0_ADDRESS                    0x30
+
+// Type
+#define D18F2x9C_x0000_0030_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0030_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0030_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0030_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct0_mp0_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct0_mp1_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct1_mp0_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0031_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0031_dct1_mp1_ADDRESS                    0x31
+
+// Type
+#define D18F2x9C_x0000_0031_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0031_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0031_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0031_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct1_mp1_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct1_mp0_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct0_mp0_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0033_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0033_dct0_mp1_ADDRESS                    0x33
+
+// Type
+#define D18F2x9C_x0000_0033_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0033_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0033_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0033_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct0_mp0_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct1_mp1_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct1_mp0_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0034_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0034_dct0_mp1_ADDRESS                    0x34
+
+// Type
+#define D18F2x9C_x0000_0034_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0034_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0034_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0034_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct1_mp1_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct0_mp1_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct1_mp0_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0036_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0036_dct0_mp0_ADDRESS                    0x36
+
+// Type
+#define D18F2x9C_x0000_0036_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0036_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0036_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0036_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct1_mp1_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct0_mp1_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct0_mp0_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0037_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0037_dct1_mp0_ADDRESS                    0x37
+
+// Type
+#define D18F2x9C_x0000_0037_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0037_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0037_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0037_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct0_mp1_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct0_mp0_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct1_mp0_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0039_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0039_dct1_mp1_ADDRESS                    0x39
+
+// Type
+#define D18F2x9C_x0000_0039_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0039_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0039_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0039_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct1_mp0_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct0_mp1_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct0_mp0_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_003A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_003A_dct1_mp1_ADDRESS                    0x3a
+
+// Type
+#define D18F2x9C_x0000_003A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_003A_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_003A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_003A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct0_mp1_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct1_mp1_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct1_mp0_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0040_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0040_dct0_mp0_ADDRESS                    0x40
+
+// Type
+#define D18F2x9C_x0000_0040_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0040_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0040_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0040_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct1_mp1_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct0_mp0_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct1_mp0_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0041_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0041_dct0_mp1_ADDRESS                    0x41
+
+// Type
+#define D18F2x9C_x0000_0041_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0041_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0041_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0041_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct1_mp0_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct0_mp1_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct1_mp1_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0043_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0043_dct0_mp0_ADDRESS                    0x43
+
+// Type
+#define D18F2x9C_x0000_0043_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0043_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0043_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0043_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct0_mp0_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct1_mp0_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct1_mp1_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0044_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0044_dct0_mp1_ADDRESS                    0x44
+
+// Type
+#define D18F2x9C_x0000_0044_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0044_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0044_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0044_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct1_mp1_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct1_mp0_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct0_mp1_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0046_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0046_dct0_mp0_ADDRESS                    0x46
+
+// Type
+#define D18F2x9C_x0000_0046_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0046_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0046_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0046_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct1_mp1_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct1_mp0_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct0_mp1_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0047_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0047_dct0_mp0_ADDRESS                    0x47
+
+// Type
+#define D18F2x9C_x0000_0047_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0047_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0047_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0047_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct0_mp1_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct0_mp0_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct1_mp1_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0049_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0049_dct1_mp0_ADDRESS                    0x49
+
+// Type
+#define D18F2x9C_x0000_0049_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_0049_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0049_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0049_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct0_mp0_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct1_mp1_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct1_mp0_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp0_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct1_mp0_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_004A_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_004A_dct0_mp1_ADDRESS                    0x4a
+
+// Type
+#define D18F2x9C_x0000_004A_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_OFFSET        0
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_WIDTH         5
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly_MASK          0x1f
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_OFFSET       5
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_WIDTH        3
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_OFFSET       8
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_12_8_MASK         0x1f00
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_OFFSET      13
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_15_13_MASK        0xe000
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_OFFSET       16
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_WIDTH        5
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsFineDly1_MASK         0x1f0000
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_OFFSET      21
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp1_WrDqsGrossDly1_MASK        0xe00000
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_OFFSET      24
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_WIDTH       5
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_28_24_MASK        0x1f000000
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_OFFSET      29
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_WIDTH       3
+#define D18F2x9C_x0000_004A_dct0_mp1_Reserved_31_29_MASK        0xe0000000
+
+/// D18F2x9C_x0000_004A_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDqsFineDly:5 ; ///<
+    UINT32                                            WrDqsGrossDly:3 ; ///<
+    UINT32                                            Reserved_12_8:5 ; ///<
+    UINT32                                           Reserved_15_13:3 ; ///<
+    UINT32                                            WrDqsFineDly1:5 ; ///<
+    UINT32                                           WrDqsGrossDly1:3 ; ///<
+    UINT32                                           Reserved_28_24:5 ; ///<
+    UINT32                                           Reserved_31_29:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_004A_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0050_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0050_dct0_ADDRESS                        0x50
+
+// Type
+#define D18F2x9C_x0000_0050_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0050_dct0_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0050_dct0_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0050_dct0_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0050_dct0_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0050_dct0_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0050_dct0_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0050_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0050_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_0050_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0050_dct1_ADDRESS                        0x50
+
+// Type
+#define D18F2x9C_x0000_0050_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0050_dct1_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0050_dct1_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0050_dct1_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0050_dct1_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0050_dct1_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0050_dct1_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0050_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0050_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_0051_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0051_dct1_ADDRESS                        0x51
+
+// Type
+#define D18F2x9C_x0000_0051_dct1_TYPE                           TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0051_dct1_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0051_dct1_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0051_dct1_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0051_dct1_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0051_dct1_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0051_dct1_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0051_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0051_dct1_STRUCT;
+
+// **** D18F2x9C_x0000_0051_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0051_dct0_ADDRESS                        0x51
+
+// Type
+#define D18F2x9C_x0000_0051_dct0_TYPE                           TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_OFFSET            0
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_WIDTH             5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly_MASK              0x1f
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_OFFSET           5
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_WIDTH            2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly_MASK             0x60
+#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_OFFSET            7
+#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_WIDTH             1
+#define D18F2x9C_x0000_0051_dct0_Reserved_7_7_MASK              0x80
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_OFFSET        8
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_WIDTH         5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly8_12_MASK          0x1f00
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_OFFSET      13
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_WIDTH       2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly13_14_MASK        0x6000
+#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_OFFSET          15
+#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_WIDTH           1
+#define D18F2x9C_x0000_0051_dct0_Reserved_15_15_MASK            0x8000
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_OFFSET       16
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_WIDTH        5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly16_20_MASK         0x1f0000
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_OFFSET      21
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_WIDTH       2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly21_22_MASK        0x600000
+#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_OFFSET          23
+#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_WIDTH           1
+#define D18F2x9C_x0000_0051_dct0_Reserved_23_23_MASK            0x800000
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_OFFSET       24
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_WIDTH        5
+#define D18F2x9C_x0000_0051_dct0_PhRecFineDly24_28_MASK         0x1f000000
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_OFFSET      29
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_WIDTH       2
+#define D18F2x9C_x0000_0051_dct0_PhRecGrossDly29_30_MASK        0x60000000
+#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_OFFSET          31
+#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_WIDTH           1
+#define D18F2x9C_x0000_0051_dct0_Reserved_31_31_MASK            0x80000000
+
+/// D18F2x9C_x0000_0051_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             PhRecFineDly:5 ; ///<
+    UINT32                                            PhRecGrossDly:2 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                         PhRecFineDly8_12:5 ; ///<
+    UINT32                                       PhRecGrossDly13_14:2 ; ///<
+    UINT32                                           Reserved_15_15:1 ; ///<
+    UINT32                                        PhRecFineDly16_20:5 ; ///<
+    UINT32                                       PhRecGrossDly21_22:2 ; ///<
+    UINT32                                           Reserved_23_23:1 ; ///<
+    UINT32                                        PhRecFineDly24_28:5 ; ///<
+    UINT32                                       PhRecGrossDly29_30:2 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0051_dct0_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct0_mp1_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct1_mp1_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct1_mp0_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0101_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0101_dct0_mp0_ADDRESS                    0x101
+
+// Type
+#define D18F2x9C_x0000_0101_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0101_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0101_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0101_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct1_mp1_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct1_mp0_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct0_mp0_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0102_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0102_dct0_mp1_ADDRESS                    0x102
+
+// Type
+#define D18F2x9C_x0000_0102_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0102_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0102_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0102_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct1_mp1_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct0_mp1_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct0_mp0_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0105_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0105_dct1_mp0_ADDRESS                    0x105
+
+// Type
+#define D18F2x9C_x0000_0105_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0105_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0105_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0105_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0105_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct0_mp1_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct1_mp0_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct0_mp0_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0106_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0106_dct1_mp1_ADDRESS                    0x106
+
+// Type
+#define D18F2x9C_x0000_0106_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0106_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0106_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0106_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0106_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct0_mp1_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct1_mp0_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct1_mp1_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0201_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0201_dct0_mp0_ADDRESS                    0x201
+
+// Type
+#define D18F2x9C_x0000_0201_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0201_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0201_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0201_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct1_mp1_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct1_mp0_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct0_mp1_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0202_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0202_dct0_mp0_ADDRESS                    0x202
+
+// Type
+#define D18F2x9C_x0000_0202_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0202_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0202_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0202_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct1_mp1_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct1_mp0_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct0_mp1_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0205_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0205_dct0_mp0_ADDRESS                    0x205
+
+// Type
+#define D18F2x9C_x0000_0205_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0205_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0205_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0205_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0205_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct0_mp0_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct1_mp0_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct0_mp1_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0206_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0206_dct1_mp1_ADDRESS                    0x206
+
+// Type
+#define D18F2x9C_x0000_0206_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0206_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0206_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0206_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0206_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct1_mp0_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct1_mp1_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct0_mp0_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0301_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0301_dct0_mp1_ADDRESS                    0x301
+
+// Type
+#define D18F2x9C_x0000_0301_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0301_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0301_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0301_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct1_mp1_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct0_mp1_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp1_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct1_mp0_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct1_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0302_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0302_dct0_mp0_ADDRESS                    0x302
+
+// Type
+#define D18F2x9C_x0000_0302_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_OFFSET        0
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_WIDTH         5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly_MASK          0x1f
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_OFFSET       5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_WIDTH        3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly_MASK         0xe0
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_OFFSET       8
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly1_MASK         0x1f00
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_OFFSET      13
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly1_MASK        0xe000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_OFFSET       16
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly2_MASK         0x1f0000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_OFFSET      21
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly2_MASK        0xe00000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_OFFSET       24
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_WIDTH        5
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatFineDly3_MASK         0x1f000000
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_OFFSET      29
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_WIDTH       3
+#define D18F2x9C_x0000_0302_dct0_mp0_WrDatGrossDly3_MASK        0xe0000000
+
+/// D18F2x9C_x0000_0302_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             WrDatFineDly:5 ; ///<
+    UINT32                                            WrDatGrossDly:3 ; ///<
+    UINT32                                            WrDatFineDly1:5 ; ///<
+    UINT32                                           WrDatGrossDly1:3 ; ///<
+    UINT32                                            WrDatFineDly2:5 ; ///<
+    UINT32                                           WrDatGrossDly2:3 ; ///<
+    UINT32                                            WrDatFineDly3:5 ; ///<
+    UINT32                                           WrDatGrossDly3:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0302_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct0_mp0_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct1_mp1_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct0_mp1_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0305_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0305_dct1_mp0_ADDRESS                    0x305
+
+// Type
+#define D18F2x9C_x0000_0305_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0305_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0305_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0305_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0305_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct0_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct0_mp0_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct0_mp0_TYPE                       TYPE_D18F2x9C_dct0_mp0
+// Field Data
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct0_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct0_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct0_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct0_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct0_mp1_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct0_mp1_TYPE                       TYPE_D18F2x9C_dct0_mp1
+// Field Data
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct0_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct0_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct0_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct0_mp1_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct1_mp0 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct1_mp0_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct1_mp0_TYPE                       TYPE_D18F2x9C_dct1_mp0
+// Field Data
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp0_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct1_mp0_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct1_mp0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct1_mp0_STRUCT;
+
+// **** D18F2x9C_x0000_0306_dct1_mp1 Register Definition ****
+// Address
+#define D18F2x9C_x0000_0306_dct1_mp1_ADDRESS                    0x306
+
+// Type
+#define D18F2x9C_x0000_0306_dct1_mp1_TYPE                       TYPE_D18F2x9C_dct1_mp1
+// Field Data
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_OFFSET        0
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_WIDTH         1
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_0_0_MASK          0x1
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_OFFSET           1
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_WIDTH            5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime_MASK             0x3e
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_OFFSET        6
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_WIDTH         3
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_8_6_MASK          0x1c0
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_OFFSET          9
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime1_MASK            0x3e00
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_OFFSET      14
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_16_14_MASK        0x1c000
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_OFFSET          17
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime2_MASK            0x3e0000
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_OFFSET      22
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_WIDTH       3
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_24_22_MASK        0x1c00000
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_OFFSET          25
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_WIDTH           5
+#define D18F2x9C_x0000_0306_dct1_mp1_RdDqsTime3_MASK            0x3e000000
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_OFFSET      30
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_WIDTH       2
+#define D18F2x9C_x0000_0306_dct1_mp1_Reserved_31_30_MASK        0xc0000000
+
+/// D18F2x9C_x0000_0306_dct1_mp1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                                RdDqsTime:5 ; ///<
+    UINT32                                             Reserved_8_6:3 ; ///<
+    UINT32                                               RdDqsTime1:5 ; ///<
+    UINT32                                           Reserved_16_14:3 ; ///<
+    UINT32                                               RdDqsTime2:5 ; ///<
+    UINT32                                           Reserved_24_22:3 ; ///<
+    UINT32                                               RdDqsTime3:5 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0000_0306_dct1_mp1_STRUCT;
+
+// **** D18F2x9C_x0D0F_E00A_dct0 Register Definition ****
+// Address
+#define D18F2x9C_x0D0F_E00A_dct0_ADDRESS                    0x0d0fe00a
+
+// Type
+#define D18F2x9C_x0D0F_E00A_dct0_TYPE                       TYPE_D18F2x9C_dct0
+// Field Data
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_OFFSET        0
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_WIDTH         4
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_3_0_MASK          0xf
+#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_OFFSET          4
+#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_WIDTH           1
+#define D18F2x9C_x0D0F_E00A_dct0_SkewMemClk_MASK            0x10
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_OFFSET       5
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_WIDTH        7
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_11_5_MASK         0xfe0
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_OFFSET      15
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_WIDTH       17
+#define D18F2x9C_x0D0F_E00A_dct0_Reserved_31_15_MASK        0xffff8000
+
+/// D18F2x9C_x0D0F_E00A_dct0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                               SkewMemClk:1 ; ///<
+    UINT32                                            Reserved_11_5:7 ; ///<
+    UINT32                                        :2 ; ///<
+    UINT32                                          :1 ; ///<
+    UINT32                                          Reserved_31_15:17 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0D0F_E00A_dct0_STRUCT;
+
+// **** D18F2x9C_x0D0F_E00A_dct1 Register Definition ****
+// Address
+#define D18F2x9C_x0D0F_E00A_dct1_ADDRESS                    0x0d0fe00a
+
+// Type
+#define D18F2x9C_x0D0F_E00A_dct1_TYPE                       TYPE_D18F2x9C_dct1
+// Field Data
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_OFFSET        0
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_WIDTH         4
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_3_0_MASK          0xf
+#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_OFFSET          4
+#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_WIDTH           1
+#define D18F2x9C_x0D0F_E00A_dct1_SkewMemClk_MASK            0x10
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_OFFSET       5
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_WIDTH        7
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_11_5_MASK         0xfe0
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_OFFSET      15
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_WIDTH       17
+#define D18F2x9C_x0D0F_E00A_dct1_Reserved_31_15_MASK        0xffff8000
+
+/// D18F2x9C_x0D0F_E00A_dct1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                               SkewMemClk:1 ; ///<
+    UINT32                                            Reserved_11_5:7 ; ///<
+    UINT32                                        :2 ; ///<
+    UINT32                                          :1 ; ///<
+    UINT32                                          Reserved_31_15:17 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D18F2x9C_x0D0F_E00A_dct1_STRUCT;
+
+
+// **** DxF0xE4_x01 Register Definition ****
+// Address
+#define DxF0xE4_x01_ADDRESS                                     0x1
+
+// Type
+#define DxF0xE4_x01_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x01_Scratch_OFFSET                              0
+#define DxF0xE4_x01_Scratch_WIDTH                               32
+#define DxF0xE4_x01_Scratch_MASK                                0xffffffff
+
+/// DxF0xE4_x01
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  Scratch:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x01_STRUCT;
+
+// **** DxF0xE4_x02 Register Definition ****
+// Address
+#define DxF0xE4_x02_ADDRESS                                     0x2
+
+// Type
+#define DxF0xE4_x02_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x02_Reserved_14_0_OFFSET                        0
+#define DxF0xE4_x02_Reserved_14_0_WIDTH                         15
+#define DxF0xE4_x02_Reserved_14_0_MASK                          0x7fff
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET               15
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH                1
+#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK                 0x8000
+#define DxF0xE4_x02_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_x02_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_x02_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_x02
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_14_0:15; ///<
+    UINT32                                   RegsLcAllowTxL1Control:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x02_STRUCT;
+
+// **** DxF0xE4_x50 Register Definition ****
+// Address
+#define DxF0xE4_x50_ADDRESS                                     0x50
+
+// Type
+#define DxF0xE4_x50_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x50_PortLaneReversal_OFFSET                     0
+#define DxF0xE4_x50_PortLaneReversal_WIDTH                      1
+#define DxF0xE4_x50_PortLaneReversal_MASK                       0x1
+#define DxF0xE4_x50_PhyLinkWidth_OFFSET                         1
+#define DxF0xE4_x50_PhyLinkWidth_WIDTH                          6
+#define DxF0xE4_x50_PhyLinkWidth_MASK                           0x7e
+#define DxF0xE4_x50_Reserved_31_7_OFFSET                        7
+#define DxF0xE4_x50_Reserved_31_7_WIDTH                         25
+#define DxF0xE4_x50_Reserved_31_7_MASK                          0xffffff80
+
+/// DxF0xE4_x50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PortLaneReversal:1 ; ///<
+    UINT32                                             PhyLinkWidth:6 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x50_STRUCT;
+
+// **** DxF0xE4_x70 Register Definition ****
+// Address
+#define DxF0xE4_x70_ADDRESS                                     0x70
+
+// Type
+#define DxF0xE4_x70_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_x70_Reserved_15_0_OFFSET                        0
+#define DxF0xE4_x70_Reserved_15_0_WIDTH                         16
+#define DxF0xE4_x70_Reserved_15_0_MASK                          0xffff
+#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET                      16
+#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH                       3
+#define DxF0xE4_x70_RxRcbCplTimeout_MASK                        0x70000
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET                  19
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH                   1
+#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK                    0x80000
+#define DxF0xE4_x70_Reserved_31_20_OFFSET                       20
+#define DxF0xE4_x70_Reserved_31_20_WIDTH                        12
+#define DxF0xE4_x70_Reserved_31_20_MASK                         0xfff00000
+
+/// DxF0xE4_x70
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_15_0:16; ///<
+    UINT32                                          RxRcbCplTimeout:3 ; ///<
+    UINT32                                      RxRcbCplTimeoutMode:1 ; ///<
+    UINT32                                           Reserved_31_20:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_x70_STRUCT;
+
+// **** DxF0xE4_xA0 Register Definition ****
+// Address
+#define DxF0xE4_xA0_ADDRESS                                     0xa0
+
+// Type
+#define DxF0xE4_xA0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA0_Reserved_3_0_OFFSET                         0
+#define DxF0xE4_xA0_Reserved_3_0_WIDTH                          4
+#define DxF0xE4_xA0_Reserved_3_0_MASK                           0xf
+#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET                     4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH                      4
+#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK                       0xf0
+#define DxF0xE4_xA0_LcL0sInactivity_OFFSET                      8
+#define DxF0xE4_xA0_LcL0sInactivity_WIDTH                       4
+#define DxF0xE4_xA0_LcL0sInactivity_MASK                        0xf00
+#define DxF0xE4_xA0_LcL1Inactivity_OFFSET                       12
+#define DxF0xE4_xA0_LcL1Inactivity_WIDTH                        4
+#define DxF0xE4_xA0_LcL1Inactivity_MASK                         0xf000
+#define DxF0xE4_xA0_Reserved_22_16_OFFSET                       16
+#define DxF0xE4_xA0_Reserved_22_16_WIDTH                        7
+#define DxF0xE4_xA0_Reserved_22_16_MASK                         0x7f0000
+#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET                     23
+#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH                      1
+#define DxF0xE4_xA0_LcL1ImmediateAck_MASK                       0x800000
+#define DxF0xE4_xA0_Reserved_31_24_OFFSET                       24
+#define DxF0xE4_xA0_Reserved_31_24_WIDTH                        8
+#define DxF0xE4_xA0_Reserved_31_24_MASK                         0xff000000
+
+/// DxF0xE4_xA0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_3_0:4 ; ///<
+    UINT32                                         Lc16xClearTxPipe:4 ; ///<
+    UINT32                                          LcL0sInactivity:4 ; ///<
+    UINT32                                           LcL1Inactivity:4 ; ///<
+    UINT32                                           Reserved_22_16:7 ; ///<
+    UINT32                                         LcL1ImmediateAck:1 ; ///<
+    UINT32                                           Reserved_31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA0_STRUCT;
+
+// **** DxF0xE4_xA1 Register Definition ****
+// Address
+#define DxF0xE4_xA1_ADDRESS                                     0xa1
+
+// Type
+#define DxF0xE4_xA1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA1_Reserved_10_0_OFFSET                        0
+#define DxF0xE4_xA1_Reserved_10_0_WIDTH                         11
+#define DxF0xE4_xA1_Reserved_10_0_MASK                          0x7ff
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET               11
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH                1
+#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK                 0x800
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET                12
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH                 1
+#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK                  0x1000
+#define DxF0xE4_xA1_Reserved_31_13_OFFSET                       13
+#define DxF0xE4_xA1_Reserved_31_13_WIDTH                        19
+#define DxF0xE4_xA1_Reserved_31_13_MASK                         0xffffe000
+
+/// DxF0xE4_xA1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_10_0:11; ///<
+    UINT32                                   LcDontGotoL0sifL1Armed:1 ; ///<
+    UINT32                                    LcInitSpdChgWithCsrEn:1 ; ///<
+    UINT32                                           Reserved_31_13:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA1_STRUCT;
+
+// **** DxF0xE4_xA2 Register Definition ****
+// Address
+#define DxF0xE4_xA2_ADDRESS                                     0xa2
+
+// Type
+#define DxF0xE4_xA2_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA2_LcLinkWidth_OFFSET                          0
+#define DxF0xE4_xA2_LcLinkWidth_WIDTH                           3
+#define DxF0xE4_xA2_LcLinkWidth_MASK                            0x7
+#define DxF0xE4_xA2_Reserved_3_3_OFFSET                         3
+#define DxF0xE4_xA2_Reserved_3_3_WIDTH                          1
+#define DxF0xE4_xA2_Reserved_3_3_MASK                           0x8
+#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET                        4
+#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH                         3
+#define DxF0xE4_xA2_LcLinkWidthRd_MASK                          0x70
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET           7
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH            1
+#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK             0x80
+#define DxF0xE4_xA2_LcReconfigNow_OFFSET                        8
+#define DxF0xE4_xA2_LcReconfigNow_WIDTH                         1
+#define DxF0xE4_xA2_LcReconfigNow_MASK                          0x100
+#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET               9
+#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH                1
+#define DxF0xE4_xA2_LcRenegotiationSupport_MASK                 0x200
+#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET                      10
+#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH                       1
+#define DxF0xE4_xA2_LcRenegotiateEn_MASK                        0x400
+#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET                    11
+#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH                     1
+#define DxF0xE4_xA2_LcShortReconfigEn_MASK                      0x800
+#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET                 12
+#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH                  1
+#define DxF0xE4_xA2_LcUpconfigureSupport_MASK                   0x1000
+#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET                     13
+#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH                      1
+#define DxF0xE4_xA2_LcUpconfigureDis_MASK                       0x2000
+#define DxF0xE4_xA2_Reserved_19_14_OFFSET                       14
+#define DxF0xE4_xA2_Reserved_19_14_WIDTH                        6
+#define DxF0xE4_xA2_Reserved_19_14_MASK                         0xfc000
+#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET                    20
+#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH                     1
+#define DxF0xE4_xA2_LcUpconfigCapable_MASK                      0x100000
+#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET                   21
+#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH                    2
+#define DxF0xE4_xA2_LcDynLanesPwrState_MASK                     0x600000
+#define DxF0xE4_xA2_Reserved_31_23_OFFSET                       23
+#define DxF0xE4_xA2_Reserved_31_23_WIDTH                        9
+#define DxF0xE4_xA2_Reserved_31_23_MASK                         0xff800000
+
+/// DxF0xE4_xA2
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LcLinkWidth:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                                            LcLinkWidthRd:3 ; ///<
+    UINT32                               LcReconfigArcMissingEscape:1 ; ///<
+    UINT32                                            LcReconfigNow:1 ; ///<
+    UINT32                                   LcRenegotiationSupport:1 ; ///<
+    UINT32                                          LcRenegotiateEn:1 ; ///<
+    UINT32                                        LcShortReconfigEn:1 ; ///<
+    UINT32                                     LcUpconfigureSupport:1 ; ///<
+    UINT32                                         LcUpconfigureDis:1 ; ///<
+    UINT32                                           Reserved_19_14:6 ; ///<
+    UINT32                                        LcUpconfigCapable:1 ; ///<
+    UINT32                                       LcDynLanesPwrState:2 ; ///<
+    UINT32                                           Reserved_31_23:9 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA2_STRUCT;
+
+// **** DxF0xE4_xA3 Register Definition ****
+// Address
+#define DxF0xE4_xA3_ADDRESS                                     0xa3
+
+// Type
+#define DxF0xE4_xA3_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA3_Reserved_8_0_OFFSET                         0
+#define DxF0xE4_xA3_Reserved_8_0_WIDTH                          9
+#define DxF0xE4_xA3_Reserved_8_0_MASK                           0x1ff
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET              9
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH               1
+#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK                0x200
+#define DxF0xE4_xA3_Reserved_31_10_OFFSET                       10
+#define DxF0xE4_xA3_Reserved_31_10_WIDTH                        22
+#define DxF0xE4_xA3_Reserved_31_10_MASK                         0xfffffc00
+
+/// DxF0xE4_xA3
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_8_0:9 ; ///<
+    UINT32                                  LcXmitFtsBeforeRecovery:1 ; ///<
+    UINT32                                           Reserved_31_10:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA3_STRUCT;
+
+// **** DxF0xE4_xA4 Register Definition ****
+// Address
+#define DxF0xE4_xA4_ADDRESS                                     0xa4
+
+// Type
+#define DxF0xE4_xA4_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET                        0
+#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH                         1
+#define DxF0xE4_xA4_LcGen2EnStrap_MASK                          0x1
+#define DxF0xE4_xA4_Reserved_5_1_OFFSET                         1
+#define DxF0xE4_xA4_Reserved_5_1_WIDTH                          5
+#define DxF0xE4_xA4_Reserved_5_1_MASK                           0x3e
+#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET              6
+#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH               1
+#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK                0x40
+#define DxF0xE4_xA4_Reserved_8_7_OFFSET                         7
+#define DxF0xE4_xA4_Reserved_8_7_WIDTH                          2
+#define DxF0xE4_xA4_Reserved_8_7_MASK                           0x180
+#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET            9
+#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH             1
+#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK              0x200
+#define DxF0xE4_xA4_Reserved_11_10_OFFSET                       10
+#define DxF0xE4_xA4_Reserved_11_10_WIDTH                        2
+#define DxF0xE4_xA4_Reserved_11_10_MASK                         0xc00
+#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET           12
+#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH            1
+#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK             0x1000
+#define DxF0xE4_xA4_Reserved_18_13_OFFSET                       13
+#define DxF0xE4_xA4_Reserved_18_13_WIDTH                        6
+#define DxF0xE4_xA4_Reserved_18_13_MASK                         0x7e000
+#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET              19
+#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH               1
+#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK                0x80000
+#define DxF0xE4_xA4_Reserved_26_20_OFFSET                       20
+#define DxF0xE4_xA4_Reserved_26_20_WIDTH                        7
+#define DxF0xE4_xA4_Reserved_26_20_MASK                         0x7f00000
+#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET          27
+#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH           1
+#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK            0x8000000
+#define DxF0xE4_xA4_Reserved_31_28_OFFSET                       28
+#define DxF0xE4_xA4_Reserved_31_28_WIDTH                        4
+#define DxF0xE4_xA4_Reserved_31_28_MASK                         0xf0000000
+
+/// DxF0xE4_xA4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            LcGen2EnStrap:1 ; ///<
+    UINT32                                             Reserved_5_1:5 ; ///<
+    UINT32                                  LcForceDisSwSpeedChange:1 ; ///<
+    UINT32                                             Reserved_8_7:2 ; ///<
+    UINT32                                LcInitiateLinkSpeedChange:1 ; ///<
+    UINT32                                           Reserved_11_10:2 ; ///<
+    UINT32                               LcSpeedChangeAttemptFailed:1 ; ///<
+    UINT32                                           Reserved_18_13:6 ; ///<
+    UINT32                                  LcOtherSideSupportsGen2:1 ; ///<
+    UINT32                                           Reserved_26_20:7 ; ///<
+    UINT32                              LcMultUpstreamAutoSpdChngEn:1 ; ///<
+    UINT32                                           Reserved_31_28:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA4_STRUCT;
+
+// **** DxF0xE4_xA5 Register Definition ****
+// Address
+#define DxF0xE4_xA5_ADDRESS                                     0xa5
+
+// Type
+#define DxF0xE4_xA5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA5_LcCurrentState_OFFSET                       0
+#define DxF0xE4_xA5_LcCurrentState_WIDTH                        6
+#define DxF0xE4_xA5_LcCurrentState_MASK                         0x3f
+#define DxF0xE4_xA5_Reserved_7_6_OFFSET                         6
+#define DxF0xE4_xA5_Reserved_7_6_WIDTH                          2
+#define DxF0xE4_xA5_Reserved_7_6_MASK                           0xc0
+#define DxF0xE4_xA5_LcPrevState1_OFFSET                         8
+#define DxF0xE4_xA5_LcPrevState1_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState1_MASK                           0x3f00
+#define DxF0xE4_xA5_Reserved_15_14_OFFSET                       14
+#define DxF0xE4_xA5_Reserved_15_14_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_15_14_MASK                         0xc000
+#define DxF0xE4_xA5_LcPrevState2_OFFSET                         16
+#define DxF0xE4_xA5_LcPrevState2_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState2_MASK                           0x3f0000
+#define DxF0xE4_xA5_Reserved_23_22_OFFSET                       22
+#define DxF0xE4_xA5_Reserved_23_22_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_23_22_MASK                         0xc00000
+#define DxF0xE4_xA5_LcPrevState3_OFFSET                         24
+#define DxF0xE4_xA5_LcPrevState3_WIDTH                          6
+#define DxF0xE4_xA5_LcPrevState3_MASK                           0x3f000000
+#define DxF0xE4_xA5_Reserved_31_30_OFFSET                       30
+#define DxF0xE4_xA5_Reserved_31_30_WIDTH                        2
+#define DxF0xE4_xA5_Reserved_31_30_MASK                         0xc0000000
+
+/// DxF0xE4_xA5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           LcCurrentState:6 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                             LcPrevState1:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                             LcPrevState2:6 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                             LcPrevState3:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xA5_STRUCT;
+
+// **** DxF0xE4_xB1 Register Definition ****
+// Address
+#define DxF0xE4_xB1_ADDRESS                                     0xb1
+
+// Type
+#define DxF0xE4_xB1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB1_Reserved_18_0_OFFSET                        0
+#define DxF0xE4_xB1_Reserved_18_0_WIDTH                         19
+#define DxF0xE4_xB1_Reserved_18_0_MASK                          0x7ffff
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET                  19
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH                   1
+#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK                    0x80000
+#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET                    20
+#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH                     1
+#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK                      0x100000
+#define DxF0xE4_xB1_Reserved_31_21_OFFSET                       21
+#define DxF0xE4_xB1_Reserved_31_21_WIDTH                        11
+#define DxF0xE4_xB1_Reserved_31_21_MASK                         0xffe00000
+
+/// DxF0xE4_xB1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_18_0:19; ///<
+    UINT32                                      LcDeassertRxEnInL0s:1 ; ///<
+    UINT32                                        LcBlockElIdleinL0:1 ; ///<
+    UINT32                                           Reserved_31_21:11; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB1_STRUCT;
+
+// **** DxF0xE4_xB5 Register Definition ****
+// Address
+#define DxF0xE4_xB5_ADDRESS                                     0xb5
+
+// Type
+#define DxF0xE4_xB5_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET                   0
+#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH                    1
+#define DxF0xE4_xB5_LcSelectDeemphasis_MASK                     0x1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET               1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH                2
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK                 0x6
+#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET                     3
+#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH                      1
+#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK                       0x8
+#define DxF0xE4_xB5_Reserved_29_4_OFFSET                        4
+#define DxF0xE4_xB5_Reserved_29_4_WIDTH                         26
+#define DxF0xE4_xB5_Reserved_29_4_MASK                          0x3ffffff0
+#define DxF0xE4_xB5_LcGoToRecovery_OFFSET                       30
+#define DxF0xE4_xB5_LcGoToRecovery_WIDTH                        1
+#define DxF0xE4_xB5_LcGoToRecovery_MASK                         0x40000000
+#define DxF0xE4_xB5_Reserved_31_31_OFFSET                       31
+#define DxF0xE4_xB5_Reserved_31_31_WIDTH                        1
+#define DxF0xE4_xB5_Reserved_31_31_MASK                         0x80000000
+
+/// DxF0xE4_xB5
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       LcSelectDeemphasis:1 ; ///<
+    UINT32                                   LcSelectDeemphasisCntl:2 ; ///<
+    UINT32                                         LcRcvdDeemphasis:1 ; ///<
+    UINT32                                            Reserved_29_4:26; ///<
+    UINT32                                           LcGoToRecovery:1 ; ///<
+    UINT32                                           Reserved_31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xB5_STRUCT;
+
+// **** DxF0xE4_xC0 Register Definition ****
+// Address
+#define DxF0xE4_xC0_ADDRESS                                     0xc0
+
+// Type
+#define DxF0xE4_xC0_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xC0_Reserved_12_0_OFFSET                        0
+#define DxF0xE4_xC0_Reserved_12_0_WIDTH                         13
+#define DxF0xE4_xC0_Reserved_12_0_MASK                          0x1fff
+#define DxF0xE4_xC0_StrapForceCompliance_OFFSET                 13
+#define DxF0xE4_xC0_StrapForceCompliance_WIDTH                  1
+#define DxF0xE4_xC0_StrapForceCompliance_MASK                   0x2000
+#define DxF0xE4_xC0_Reserved_14_14_OFFSET                       14
+#define DxF0xE4_xC0_Reserved_14_14_WIDTH                        1
+#define DxF0xE4_xC0_Reserved_14_14_MASK                         0x4000
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET       15
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH        1
+#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK         0x8000
+#define DxF0xE4_xC0_Reserved_31_16_OFFSET                       16
+#define DxF0xE4_xC0_Reserved_31_16_WIDTH                        16
+#define DxF0xE4_xC0_Reserved_31_16_MASK                         0xffff0000
+
+/// DxF0xE4_xC0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            Reserved_12_0:13; ///<
+    UINT32                                     StrapForceCompliance:1 ; ///<
+    UINT32                                           Reserved_14_14:1 ; ///<
+    UINT32                           StrapAutoRcSpeedNegotiationDis:1 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xC0_STRUCT;
+
+// **** DxF0xE4_xC1 Register Definition ****
+// Address
+#define DxF0xE4_xC1_ADDRESS                                     0xc1
+
+// Type
+#define DxF0xE4_xC1_TYPE                                        TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xC1_StrapReverseLanes_OFFSET                    0
+#define DxF0xE4_xC1_StrapReverseLanes_WIDTH                     1
+#define DxF0xE4_xC1_StrapReverseLanes_MASK                      0x1
+#define DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET                     1
+#define DxF0xE4_xC1_StrapE2EPrefixEn_WIDTH                      1
+#define DxF0xE4_xC1_StrapE2EPrefixEn_MASK                       0x2
+#define DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET            2
+#define DxF0xE4_xC1_StrapExtendedFmtSupported_WIDTH             1
+#define DxF0xE4_xC1_StrapExtendedFmtSupported_MASK              0x4
+#define DxF0xE4_xC1_Reserved_31_3_OFFSET                        3
+#define DxF0xE4_xC1_Reserved_31_3_WIDTH                         29
+#define DxF0xE4_xC1_Reserved_31_3_MASK                          0xfffffff8
+
+/// DxF0xE4_xC1
+typedef union {
+  struct {                                                              ///<
+    UINT32                                        StrapReverseLanes:1 ; ///<
+    UINT32                                         StrapE2EPrefixEn:1 ; ///<
+    UINT32                                StrapExtendedFmtSupported:1 ; ///<
+    UINT32                                            Reserved_31_3:29; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} DxF0xE4_xC1_STRUCT;
+
+// **** GMMx00 Register Definition ****
+// Address
+#define GMMx00_ADDRESS                                          0x0
+
+// Type
+#define GMMx00_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx00_MM_OFFSET_OFFSET                                 0
+#define GMMx00_MM_OFFSET_WIDTH                                  31
+#define GMMx00_MM_OFFSET_MASK                                   0x7fffffff
+#define GMMx00_MM_APER_OFFSET                                   31
+#define GMMx00_MM_APER_WIDTH                                    1
+#define GMMx00_MM_APER_MASK                                     0x80000000
+
+/// GMMx00
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                MM_OFFSET:31; ///<
+    UINT32                                                  MM_APER:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx00_STRUCT;
+
+// **** GMMx04 Register Definition ****
+// Address
+#define GMMx04_ADDRESS                                          0x4
+
+// Type
+#define GMMx04_TYPE                                             TYPE_GMM
+// Field Data
+#define GMMx04_MM_DATA_OFFSET                                   0
+#define GMMx04_MM_DATA_WIDTH                                    32
+#define GMMx04_MM_DATA_MASK                                     0xffffffff
+
+/// GMMx04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  MM_DATA:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx04_STRUCT;
+
+// **** GMMx63C Register Definition ****
+// Address
+#define GMMx63C_ADDRESS                                         0x63c
+
+// Type
+#define GMMx63C_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx63C_VoltageForceEn_OFFSET                           0
+#define GMMx63C_VoltageForceEn_WIDTH                            1
+#define GMMx63C_VoltageForceEn_MASK                             0x1
+#define GMMx63C_VoltageChangeEn_OFFSET                          1
+#define GMMx63C_VoltageChangeEn_WIDTH                           1
+#define GMMx63C_VoltageChangeEn_MASK                            0x2
+#define GMMx63C_VoltageChangeReq_OFFSET                         2
+#define GMMx63C_VoltageChangeReq_WIDTH                          1
+#define GMMx63C_VoltageChangeReq_MASK                           0x4
+#define GMMx63C_Reserved_7_3_OFFSET                             3
+#define GMMx63C_Reserved_7_3_WIDTH                              5
+#define GMMx63C_Reserved_7_3_MASK                               0xf8
+#define GMMx63C_VoltageLevel_OFFSET                             8
+#define GMMx63C_VoltageLevel_WIDTH                              8
+#define GMMx63C_VoltageLevel_MASK                               0xff00
+#define GMMx63C_Reserved_31_16_OFFSET                           16
+#define GMMx63C_Reserved_31_16_WIDTH                            16
+#define GMMx63C_Reserved_31_16_MASK                             0xffff0000
+
+/// GMMx63C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             Reserved_7_3:5 ; ///<
+    UINT32                                             VoltageLevel:8 ; ///<
+    UINT32                                           Reserved_31_16:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx63C_STRUCT;
+
+// **** GMMx640 Register Definition ****
+// Address
+#define GMMx640_ADDRESS                                         0x640
+
+// Type
+#define GMMx640_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx640_VoltageChangeAck_OFFSET                         0
+#define GMMx640_VoltageChangeAck_WIDTH                          1
+#define GMMx640_VoltageChangeAck_MASK                           0x1
+#define GMMx640_CurrentVoltageLevel_OFFSET                      1
+#define GMMx640_CurrentVoltageLevel_WIDTH                       8
+#define GMMx640_CurrentVoltageLevel_MASK                        0x1fe
+#define GMMx640_Reserved_31_9_OFFSET                            9
+#define GMMx640_Reserved_31_9_WIDTH                             23
+#define GMMx640_Reserved_31_9_MASK                              0xfffffe00
+
+/// GMMx640
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:8 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx640_STRUCT;
+
+
+
+// **** GMMx770 Register Definition ****
+// Address
+#define GMMx770_ADDRESS                                         0x770
+
+// Type
+#define GMMx770_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx770_VoltageChangeReq_OFFSET                         0
+#define GMMx770_VoltageChangeReq_WIDTH                          1
+#define GMMx770_VoltageChangeReq_MASK                           0x1
+#define GMMx770_VoltageLevel_OFFSET                             1
+#define GMMx770_VoltageLevel_WIDTH                              8
+#define GMMx770_VoltageLevel_MASK                               0x1fe
+#define GMMx770_VoltageChangeEn_OFFSET                          9
+#define GMMx770_VoltageChangeEn_WIDTH                           1
+#define GMMx770_VoltageChangeEn_MASK                            0x200
+#define GMMx770_VoltageForceEn_OFFSET                           10
+#define GMMx770_VoltageForceEn_WIDTH                            1
+#define GMMx770_VoltageForceEn_MASK                             0x400
+#define GMMx770_Reserved_31_11_OFFSET                           11
+#define GMMx770_Reserved_31_11_WIDTH                            21
+#define GMMx770_Reserved_31_11_MASK                             0xfffff800
+
+/// GMMx770
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeReq:1 ; ///<
+    UINT32                                             VoltageLevel:8 ; ///<
+    UINT32                                          VoltageChangeEn:1 ; ///<
+    UINT32                                           VoltageForceEn:1 ; ///<
+    UINT32                                           Reserved_31_11:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx770_STRUCT;
+
+// **** GMMx774 Register Definition ****
+// Address
+#define GMMx774_ADDRESS                                         0x774
+
+// Type
+#define GMMx774_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx774_VoltageChangeAck_OFFSET                         0
+#define GMMx774_VoltageChangeAck_WIDTH                          1
+#define GMMx774_VoltageChangeAck_MASK                           0x1
+#define GMMx774_CurrentVoltageLevel_OFFSET                      1
+#define GMMx774_CurrentVoltageLevel_WIDTH                       8
+#define GMMx774_CurrentVoltageLevel_MASK                        0x1fe
+#define GMMx774_Reserved_31_9_OFFSET                            9
+#define GMMx774_Reserved_31_9_WIDTH                             23
+#define GMMx774_Reserved_31_9_MASK                              0xfffffe00
+
+/// GMMx774
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         VoltageChangeAck:1 ; ///<
+    UINT32                                      CurrentVoltageLevel:8 ; ///<
+    UINT32                                            Reserved_31_9:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx774_STRUCT;
+
+// **** GMMx7A0 Register Definition ****
+// Address
+#define GMMx7A0_ADDRESS                                         0x7a0
+
+// Type
+#define GMMx7A0_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx7A0_DivId_OFFSET                                    0
+#define GMMx7A0_DivId_WIDTH                                     3
+#define GMMx7A0_DivId_MASK                                      0x7
+#define GMMx7A0_RampDis_OFFSET                                  3
+#define GMMx7A0_RampDis_WIDTH                                   1
+#define GMMx7A0_RampDis_MASK                                    0x8
+#define GMMx7A0_Hysteresis_OFFSET                               4
+#define GMMx7A0_Hysteresis_WIDTH                                12
+#define GMMx7A0_Hysteresis_MASK                                 0xfff0
+#define GMMx7A0_SclkRunningMask_OFFSET                          16
+#define GMMx7A0_SclkRunningMask_WIDTH                           1
+#define GMMx7A0_SclkRunningMask_MASK                            0x10000
+#define GMMx7A0_SmuBusyMask_OFFSET                              17
+#define GMMx7A0_SmuBusyMask_WIDTH                               1
+#define GMMx7A0_SmuBusyMask_MASK                                0x20000
+#define GMMx7A0_PcieLclkIdle1Mask_OFFSET                        18
+#define GMMx7A0_PcieLclkIdle1Mask_WIDTH                         1
+#define GMMx7A0_PcieLclkIdle1Mask_MASK                          0x40000
+#define GMMx7A0_PcieLclkIdle2Mask_OFFSET                        19
+#define GMMx7A0_PcieLclkIdle2Mask_WIDTH                         1
+#define GMMx7A0_PcieLclkIdle2Mask_MASK                          0x80000
+#define GMMx7A0_L1imugfxIdleMask_OFFSET                         20
+#define GMMx7A0_L1imugfxIdleMask_WIDTH                          1
+#define GMMx7A0_L1imugfxIdleMask_MASK                           0x100000
+#define GMMx7A0_L1imugppsbIdleMask_OFFSET                       21
+#define GMMx7A0_L1imugppsbIdleMask_WIDTH                        1
+#define GMMx7A0_L1imugppsbIdleMask_MASK                         0x200000
+#define GMMx7A0_L1imubifIdleMask_OFFSET                         22
+#define GMMx7A0_L1imubifIdleMask_WIDTH                          1
+#define GMMx7A0_L1imubifIdleMask_MASK                           0x400000
+#define GMMx7A0_L1imuintgenIdleMask_OFFSET                      23
+#define GMMx7A0_L1imuintgenIdleMask_WIDTH                       1
+#define GMMx7A0_L1imuintgenIdleMask_MASK                        0x800000
+#define GMMx7A0_L2imuIdleMask_OFFSET                            24
+#define GMMx7A0_L2imuIdleMask_WIDTH                             1
+#define GMMx7A0_L2imuIdleMask_MASK                              0x1000000
+#define GMMx7A0_OrbIdleMask_OFFSET                              25
+#define GMMx7A0_OrbIdleMask_WIDTH                               1
+#define GMMx7A0_OrbIdleMask_MASK                                0x2000000
+#define GMMx7A0_OnInbWakeMask_OFFSET                            26
+#define GMMx7A0_OnInbWakeMask_WIDTH                             1
+#define GMMx7A0_OnInbWakeMask_MASK                              0x4000000
+#define GMMx7A0_OnInbWakeAckMask_OFFSET                         27
+#define GMMx7A0_OnInbWakeAckMask_WIDTH                          1
+#define GMMx7A0_OnInbWakeAckMask_MASK                           0x8000000
+#define GMMx7A0_OnOutbWakeMask_OFFSET                           28
+#define GMMx7A0_OnOutbWakeMask_WIDTH                            1
+#define GMMx7A0_OnOutbWakeMask_MASK                             0x10000000
+#define GMMx7A0_OnOutbWakeAckMask_OFFSET                        29
+#define GMMx7A0_OnOutbWakeAckMask_WIDTH                         1
+#define GMMx7A0_OnOutbWakeAckMask_MASK                          0x20000000
+#define GMMx7A0_DmaactiveMask_OFFSET                            30
+#define GMMx7A0_DmaactiveMask_WIDTH                             1
+#define GMMx7A0_DmaactiveMask_MASK                              0x40000000
+#define GMMx7A0_EnableDs_OFFSET                                 31
+#define GMMx7A0_EnableDs_WIDTH                                  1
+#define GMMx7A0_EnableDs_MASK                                   0x80000000
+
+/// GMMx7A0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    DivId:3 ; ///<
+    UINT32                                                  RampDis:1 ; ///<
+    UINT32                                               Hysteresis:12; ///<
+    UINT32                                          SclkRunningMask:1 ; ///<
+    UINT32                                              SmuBusyMask:1 ; ///<
+    UINT32                                        PcieLclkIdle1Mask:1 ; ///<
+    UINT32                                        PcieLclkIdle2Mask:1 ; ///<
+    UINT32                                         L1imugfxIdleMask:1 ; ///<
+    UINT32                                       L1imugppsbIdleMask:1 ; ///<
+    UINT32                                         L1imubifIdleMask:1 ; ///<
+    UINT32                                      L1imuintgenIdleMask:1 ; ///<
+    UINT32                                            L2imuIdleMask:1 ; ///<
+    UINT32                                              OrbIdleMask:1 ; ///<
+    UINT32                                            OnInbWakeMask:1 ; ///<
+    UINT32                                         OnInbWakeAckMask:1 ; ///<
+    UINT32                                           OnOutbWakeMask:1 ; ///<
+    UINT32                                        OnOutbWakeAckMask:1 ; ///<
+    UINT32                                            DmaactiveMask:1 ; ///<
+    UINT32                                                 EnableDs:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx7A0_STRUCT;
+
+// **** GMMx7B0 Register Definition ****
+// Address
+#define GMMx7B0_ADDRESS                                         0x7b0
+
+// Type
+#define GMMx7B0_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx7B0_SMU_VOLTAGE_EN_OFFSET                           0
+#define GMMx7B0_SMU_VOLTAGE_EN_WIDTH                            1
+#define GMMx7B0_SMU_VOLTAGE_EN_MASK                             0x1
+#define GMMx7B0_SMU_VOLTAGE_LEVEL_OFFSET                        1
+#define GMMx7B0_SMU_VOLTAGE_LEVEL_WIDTH                         8
+#define GMMx7B0_SMU_VOLTAGE_LEVEL_MASK                          0x1fe
+#define GMMx7B0_Reserved_OFFSET                                 9
+#define GMMx7B0_Reserved_WIDTH                                  23
+#define GMMx7B0_Reserved_MASK                                   0xfffffe00
+
+/// GMMx7B0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           SMU_VOLTAGE_EN:1 ; ///<
+    UINT32                                        SMU_VOLTAGE_LEVEL:8 ; ///<
+    UINT32                                                 Reserved:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx7B0_STRUCT;
+
+// **** GMMx898 Register Definition ****
+// Address
+#define GMMx898_ADDRESS                                         0x898
+
+// Type
+#define GMMx898_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx898_Threshold_OFFSET                                0
+#define GMMx898_Threshold_WIDTH                                 8
+#define GMMx898_Threshold_MASK                                  0xff
+#define GMMx898_Reserved_31_8_OFFSET                            8
+#define GMMx898_Reserved_31_8_WIDTH                             24
+#define GMMx898_Reserved_31_8_MASK                              0xffffff00
+
+/// GMMx898
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                Threshold:8 ; ///<
+    UINT32                                            Reserved_31_8:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx898_STRUCT;
+
+// **** GMMxC64 Register Definition ****
+// Address
+#define GMMxC64_ADDRESS                                         0xc64
+
+// Type
+#define GMMxC64_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET                   0
+#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_WIDTH                    1
+#define GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK                     0x1
+#define GMMxC64_Reserved_OFFSET                                 1
+#define GMMxC64_Reserved_WIDTH                                  31
+#define GMMxC64_Reserved_MASK                                   0xfffffffe
+
+/// GMMxC64
+typedef union {
+  struct {                                                              ///<
+    UINT32                                   MCIFMEM_CACHE_MODE_DIS:1 ; ///<
+    UINT32                                                 Reserved:31; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMxC64_STRUCT;
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                    CHAN0:4 ; ///<
+    UINT32                                                    CHAN1:4 ; ///<
+    UINT32                                                    CHAN2:4 ; ///<
+    UINT32                                                 NOOFCHAN:2 ; ///<
+    UINT32                                                 Reserved:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1012_STRUCT;
+
+
+
+
+
+// **** GMMx2024 Register Definition ****
+// Address
+#define GMMx2024_ADDRESS                                        0x2024
+
+// Type
+#define GMMx2024_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2024_FB_BASE_OFFSET                                 0
+#define GMMx2024_FB_BASE_WIDTH                                  16
+#define GMMx2024_FB_BASE_MASK                                   0xffff
+#define GMMx2024_FB_TOP_OFFSET                                  16
+#define GMMx2024_FB_TOP_WIDTH                                   16
+#define GMMx2024_FB_TOP_MASK                                    0xffff0000
+
+/// GMMx2024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  FB_BASE:16; ///<
+    UINT32                                                   FB_TOP:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2024_STRUCT;
+
+// **** GMMx2068 Register Definition ****
+// Address
+#define GMMx2068_ADDRESS                                        0x2068
+
+// Type
+#define GMMx2068_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2068_FB_OFFSET_OFFSET                               0
+#define GMMx2068_FB_OFFSET_WIDTH                                18
+#define GMMx2068_FB_OFFSET_MASK                                 0x3ffff
+#define GMMx2068_Reserved_OFFSET                                18
+#define GMMx2068_Reserved_WIDTH                                 14
+#define GMMx2068_Reserved_MASK                                  0xfffc0000
+
+/// GMMx2068
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                FB_OFFSET:18; ///<
+    UINT32                                                 Reserved:14; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2068_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         DEFAULT_STEERING:2 ; ///<
+    UINT32                                          CLIENT_STEERING:2 ; ///<
+    UINT32                                                 Reserved:28; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1017_STRUCT;
+
+
+
+
+
+
+
+// **** GMMx20EC Register Definition ****
+// Address
+
+// **** GMMx2114 Register Definition ****
+// Address
+#define GMMx2114_ADDRESS                                        0x2114
+
+// Type
+#define GMMx2114_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2114_STOR1_PRI_OFFSET                               0
+#define GMMx2114_STOR1_PRI_WIDTH                                8
+#define GMMx2114_STOR1_PRI_MASK                                 0xff
+#define GMMx2114_Reserved_OFFSET                                8
+#define GMMx2114_Reserved_WIDTH                                 24
+#define GMMx2114_Reserved_MASK                                  0xffffff00
+
+/// GMMx2114
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                STOR1_PRI:8 ; ///<
+    UINT32                                                 Reserved:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2114_STRUCT;
+
+
+// **** GMMx2188 Register Definition ****
+// Address
+#define GMMx2188_ADDRESS                                        0x2188
+
+// Type
+#define GMMx2188_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2188_ENABLE_OFFSET                                  0
+#define GMMx2188_ENABLE_WIDTH                                   1
+#define GMMx2188_ENABLE_MASK                                    0x1
+#define GMMx2188_PRESCALE_OFFSET                                1
+#define GMMx2188_PRESCALE_WIDTH                                 2
+#define GMMx2188_PRESCALE_MASK                                  0x6
+#define GMMx2188_BLACKOUT_EXEMPT_OFFSET                         3
+#define GMMx2188_BLACKOUT_EXEMPT_WIDTH                          1
+#define GMMx2188_BLACKOUT_EXEMPT_MASK                           0x8
+#define GMMx2188_STALL_MODE_OFFSET                              4
+#define GMMx2188_STALL_MODE_WIDTH                               2
+#define GMMx2188_STALL_MODE_MASK                                0x30
+#define GMMx2188_STALL_OVERRIDE_OFFSET                          6
+#define GMMx2188_STALL_OVERRIDE_WIDTH                           1
+#define GMMx2188_STALL_OVERRIDE_MASK                            0x40
+#define GMMx2188_MAXBURST_OFFSET                                7
+#define GMMx2188_MAXBURST_WIDTH                                 4
+#define GMMx2188_MAXBURST_MASK                                  0x780
+#define GMMx2188_LAZY_TIMER_OFFSET                              11
+#define GMMx2188_LAZY_TIMER_WIDTH                               4
+#define GMMx2188_LAZY_TIMER_MASK                                0x7800
+#define GMMx2188_STALL_OVERRIDE_WTM_OFFSET                      15
+#define GMMx2188_STALL_OVERRIDE_WTM_WIDTH                       1
+#define GMMx2188_STALL_OVERRIDE_WTM_MASK                        0x8000
+#define GMMx2188_Reserved_OFFSET                                16
+#define GMMx2188_Reserved_WIDTH                                 16
+#define GMMx2188_Reserved_MASK                                  0xffff0000
+
+/// GMMx2188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                   ENABLE:1 ; ///<
+    UINT32                                                 PRESCALE:2 ; ///<
+    UINT32                                          BLACKOUT_EXEMPT:1 ; ///<
+    UINT32                                               STALL_MODE:2 ; ///<
+    UINT32                                           STALL_OVERRIDE:1 ; ///<
+    UINT32                                                 MAXBURST:4 ; ///<
+    UINT32                                               LAZY_TIMER:4 ; ///<
+    UINT32                                       STALL_OVERRIDE_WTM:1 ; ///<
+    UINT32                                                 Reserved:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2188_STRUCT;
+
+
+
+
+#define GMMx21F4_STALL_OVERRIDE_OFFSET                          6
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             UVD_OPTIMIZE:1 ; ///<
+    UINT32                                             VCE_OPTIMIZE:1 ; ///<
+    UINT32                                          XB_UVD_OPTIMIZE:1 ; ///<
+    UINT32                                          XB_VCE_OPTIMIZE:1 ; ///<
+    UINT32                                   CITF_UVD_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                   CITF_UMC_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                   CITF_VCE_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                  CITF_VCEU_OPPOSITE_CHAN:1 ; ///<
+    UINT32                                                 Reserved:24; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1034_STRUCT;
+
+
+// **** GMMx25C0 Register Definition ****
+// Address
+#define GMMx25C0_ADDRESS                                        0x25c0
+
+// Type
+#define GMMx25C0_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx25C0_Reserved_OFFSET                                0
+#define GMMx25C0_Reserved_WIDTH                                 2
+#define GMMx25C0_Reserved_MASK                                  0x3
+#define GMMx25C0_IGNOREPM_OFFSET                                2
+#define GMMx25C0_IGNOREPM_WIDTH                                 1
+#define GMMx25C0_IGNOREPM_MASK                                  0x4
+#define GMMx25C0_EXEMPTPM_OFFSET                                3
+#define GMMx25C0_EXEMPTPM_WIDTH                                 1
+#define GMMx25C0_EXEMPTPM_MASK                                  0x8
+#define GMMx25C0_GFX_IDLE_OVERRIDE_OFFSET                       4
+#define GMMx25C0_GFX_IDLE_OVERRIDE_WIDTH                        2
+#define GMMx25C0_GFX_IDLE_OVERRIDE_MASK                         0x30
+#define GMMx25C0_MCD_SRBM_MASK_ENABLE_OFFSET                    6
+#define GMMx25C0_MCD_SRBM_MASK_ENABLE_WIDTH                     1
+#define GMMx25C0_MCD_SRBM_MASK_ENABLE_MASK                      0x40
+#define GMMx25C0_DUMMY_OFFSET                                   7
+#define GMMx25C0_DUMMY_WIDTH                                    7
+#define GMMx25C0_DUMMY_MASK                                     0x3f80
+#define GMMx25C0_Reserved14_31_OFFSET                           14
+#define GMMx25C0_Reserved14_31_WIDTH                            18
+#define GMMx25C0_Reserved14_31_MASK                             0xffffc000
+
+/// GMMx25C0
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:2 ; ///<
+    UINT32                                                 IGNOREPM:1 ; ///<
+    UINT32                                                 EXEMPTPM:1 ; ///<
+    UINT32                                        GFX_IDLE_OVERRIDE:2 ; ///<
+    UINT32                                     MCD_SRBM_MASK_ENABLE:1 ; ///<
+    UINT32                                                    DUMMY:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx25C0_STRUCT;
+
+// **** GMMx25C8 Register Definition ****
+// Address
+#define GMMx25C8_ADDRESS                                        0x25c8
+
+// Type
+#define GMMx25C8_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx25C8_READ_LCL_OFFSET                                0
+#define GMMx25C8_READ_LCL_WIDTH                                 8
+#define GMMx25C8_READ_LCL_MASK                                  0xff
+#define GMMx25C8_READ_HUB_OFFSET                                8
+#define GMMx25C8_READ_HUB_WIDTH                                 8
+#define GMMx25C8_READ_HUB_MASK                                  0xff00
+#define GMMx25C8_READ_PRI_OFFSET                                16
+#define GMMx25C8_READ_PRI_WIDTH                                 8
+#define GMMx25C8_READ_PRI_MASK                                  0xff0000
+#define GMMx25C8_LCL_PRI_OFFSET                                 24
+#define GMMx25C8_LCL_PRI_WIDTH                                  1
+#define GMMx25C8_LCL_PRI_MASK                                   0x1000000
+#define GMMx25C8_HUB_PRI_OFFSET                                 25
+#define GMMx25C8_HUB_PRI_WIDTH                                  1
+#define GMMx25C8_HUB_PRI_MASK                                   0x2000000
+#define GMMx25C8_Reserved_OFFSET                                26
+#define GMMx25C8_Reserved_WIDTH                                 6
+#define GMMx25C8_Reserved_MASK                                  0xfc000000
+
+/// GMMx25C8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 READ_LCL:8 ; ///<
+    UINT32                                                 READ_HUB:8 ; ///<
+    UINT32                                                 READ_PRI:8 ; ///<
+    UINT32                                                  LCL_PRI:1 ; ///<
+    UINT32                                                  HUB_PRI:1 ; ///<
+    UINT32                                                 Reserved:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx25C8_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1047_0:8;
+    UINT32            ex1047_1:8;
+    UINT32            ex1047_2:8;
+    UINT32            ex1047_3:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1047_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1048_0:8;
+    UINT32            ex1048_1:8;
+    UINT32            ex1048_2:8;
+    UINT32            ex1048_3:5;
+    UINT32                                                 Reserved:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1048_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1060_0:8;
+    UINT32            ex1060_1:8;
+    UINT32            ex1060_2:8;
+    UINT32            ex1060_3:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1060_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1061_0:8;
+    UINT32            ex1061_1:8;
+    UINT32            ex1061_2:8;
+    UINT32            ex1061_3:5;
+    UINT32                                                 Reserved:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1061_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1062_0:5;
+    UINT32            ex1062_1:5;
+    UINT32                                                   STATE2:5 ; ///<
+    UINT32                                                   STATE3:5 ; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1062_STRUCT;
+
+// **** GMMx2814 Register Definition ****
+// Address
+#define GMMx2814_ADDRESS                                        0x2814
+
+// Type
+#define GMMx2814_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2814_CSENABLE_OFFSET                                0
+#define GMMx2814_CSENABLE_WIDTH                                 1
+#define GMMx2814_CSENABLE_MASK                                  0x1
+#define GMMx2814_Reserved_OFFSET                                1
+#define GMMx2814_Reserved_WIDTH                                 4
+#define GMMx2814_Reserved_MASK                                  0x1e
+#define GMMx2814_BASEADDR21_11_OFFSET                           5
+#define GMMx2814_BASEADDR21_11_WIDTH                            11
+#define GMMx2814_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2814_Reserved16_18_OFFSET                           16
+#define GMMx2814_Reserved16_18_WIDTH                            3
+#define GMMx2814_Reserved16_18_MASK                             0x70000
+#define GMMx2814_BASEADDR38_27_OFFSET                           19
+#define GMMx2814_BASEADDR38_27_WIDTH                            12
+#define GMMx2814_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2814_Reserved31_31_OFFSET                           31
+#define GMMx2814_Reserved31_31_WIDTH                            1
+#define GMMx2814_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2814
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2814_STRUCT;
+
+// **** GMMx2818 Register Definition ****
+// Address
+#define GMMx2818_ADDRESS                                        0x2818
+
+// Type
+#define GMMx2818_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2818_CSENABLE_OFFSET                                0
+#define GMMx2818_CSENABLE_WIDTH                                 1
+#define GMMx2818_CSENABLE_MASK                                  0x1
+#define GMMx2818_Reserved_OFFSET                                1
+#define GMMx2818_Reserved_WIDTH                                 4
+#define GMMx2818_Reserved_MASK                                  0x1e
+#define GMMx2818_BASEADDR21_11_OFFSET                           5
+#define GMMx2818_BASEADDR21_11_WIDTH                            11
+#define GMMx2818_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2818_Reserved16_18_OFFSET                           16
+#define GMMx2818_Reserved16_18_WIDTH                            3
+#define GMMx2818_Reserved16_18_MASK                             0x70000
+#define GMMx2818_BASEADDR38_27_OFFSET                           19
+#define GMMx2818_BASEADDR38_27_WIDTH                            12
+#define GMMx2818_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2818_Reserved31_31_OFFSET                           31
+#define GMMx2818_Reserved31_31_WIDTH                            1
+#define GMMx2818_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2818
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2818_STRUCT;
+
+// **** GMMx281C Register Definition ****
+// Address
+#define GMMx281C_ADDRESS                                        0x281c
+
+// Type
+#define GMMx281C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx281C_CSENABLE_OFFSET                                0
+#define GMMx281C_CSENABLE_WIDTH                                 1
+#define GMMx281C_CSENABLE_MASK                                  0x1
+#define GMMx281C_Reserved_OFFSET                                1
+#define GMMx281C_Reserved_WIDTH                                 4
+#define GMMx281C_Reserved_MASK                                  0x1e
+#define GMMx281C_BASEADDR21_11_OFFSET                           5
+#define GMMx281C_BASEADDR21_11_WIDTH                            11
+#define GMMx281C_BASEADDR21_11_MASK                             0xffe0
+#define GMMx281C_Reserved16_18_OFFSET                           16
+#define GMMx281C_Reserved16_18_WIDTH                            3
+#define GMMx281C_Reserved16_18_MASK                             0x70000
+#define GMMx281C_BASEADDR38_27_OFFSET                           19
+#define GMMx281C_BASEADDR38_27_WIDTH                            12
+#define GMMx281C_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx281C_Reserved31_31_OFFSET                           31
+#define GMMx281C_Reserved31_31_WIDTH                            1
+#define GMMx281C_Reserved31_31_MASK                             0x80000000
+
+/// GMMx281C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx281C_STRUCT;
+
+// **** GMMx2820 Register Definition ****
+// Address
+#define GMMx2820_ADDRESS                                        0x2820
+
+// Type
+#define GMMx2820_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2820_CSENABLE_OFFSET                                0
+#define GMMx2820_CSENABLE_WIDTH                                 1
+#define GMMx2820_CSENABLE_MASK                                  0x1
+#define GMMx2820_Reserved_OFFSET                                1
+#define GMMx2820_Reserved_WIDTH                                 4
+#define GMMx2820_Reserved_MASK                                  0x1e
+#define GMMx2820_BASEADDR21_11_OFFSET                           5
+#define GMMx2820_BASEADDR21_11_WIDTH                            11
+#define GMMx2820_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2820_Reserved16_18_OFFSET                           16
+#define GMMx2820_Reserved16_18_WIDTH                            3
+#define GMMx2820_Reserved16_18_MASK                             0x70000
+#define GMMx2820_BASEADDR38_27_OFFSET                           19
+#define GMMx2820_BASEADDR38_27_WIDTH                            12
+#define GMMx2820_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2820_Reserved31_31_OFFSET                           31
+#define GMMx2820_Reserved31_31_WIDTH                            1
+#define GMMx2820_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2820
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2820_STRUCT;
+
+// **** GMMx2824 Register Definition ****
+// Address
+#define GMMx2824_ADDRESS                                        0x2824
+
+// Type
+#define GMMx2824_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2824_CSENABLE_OFFSET                                0
+#define GMMx2824_CSENABLE_WIDTH                                 1
+#define GMMx2824_CSENABLE_MASK                                  0x1
+#define GMMx2824_Reserved_OFFSET                                1
+#define GMMx2824_Reserved_WIDTH                                 4
+#define GMMx2824_Reserved_MASK                                  0x1e
+#define GMMx2824_BASEADDR21_11_OFFSET                           5
+#define GMMx2824_BASEADDR21_11_WIDTH                            11
+#define GMMx2824_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2824_Reserved16_18_OFFSET                           16
+#define GMMx2824_Reserved16_18_WIDTH                            3
+#define GMMx2824_Reserved16_18_MASK                             0x70000
+#define GMMx2824_BASEADDR38_27_OFFSET                           19
+#define GMMx2824_BASEADDR38_27_WIDTH                            12
+#define GMMx2824_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2824_Reserved31_31_OFFSET                           31
+#define GMMx2824_Reserved31_31_WIDTH                            1
+#define GMMx2824_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2824
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2824_STRUCT;
+
+// **** GMMx2828 Register Definition ****
+// Address
+#define GMMx2828_ADDRESS                                        0x2828
+
+// Type
+#define GMMx2828_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2828_CSENABLE_OFFSET                                0
+#define GMMx2828_CSENABLE_WIDTH                                 1
+#define GMMx2828_CSENABLE_MASK                                  0x1
+#define GMMx2828_Reserved_OFFSET                                1
+#define GMMx2828_Reserved_WIDTH                                 4
+#define GMMx2828_Reserved_MASK                                  0x1e
+#define GMMx2828_BASEADDR21_11_OFFSET                           5
+#define GMMx2828_BASEADDR21_11_WIDTH                            11
+#define GMMx2828_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2828_Reserved16_18_OFFSET                           16
+#define GMMx2828_Reserved16_18_WIDTH                            3
+#define GMMx2828_Reserved16_18_MASK                             0x70000
+#define GMMx2828_BASEADDR38_27_OFFSET                           19
+#define GMMx2828_BASEADDR38_27_WIDTH                            12
+#define GMMx2828_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2828_Reserved31_31_OFFSET                           31
+#define GMMx2828_Reserved31_31_WIDTH                            1
+#define GMMx2828_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2828
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2828_STRUCT;
+
+// **** GMMx282C Register Definition ****
+// Address
+#define GMMx282C_ADDRESS                                        0x282c
+
+// Type
+#define GMMx282C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx282C_CSENABLE_OFFSET                                0
+#define GMMx282C_CSENABLE_WIDTH                                 1
+#define GMMx282C_CSENABLE_MASK                                  0x1
+#define GMMx282C_Reserved_OFFSET                                1
+#define GMMx282C_Reserved_WIDTH                                 4
+#define GMMx282C_Reserved_MASK                                  0x1e
+#define GMMx282C_BASEADDR21_11_OFFSET                           5
+#define GMMx282C_BASEADDR21_11_WIDTH                            11
+#define GMMx282C_BASEADDR21_11_MASK                             0xffe0
+#define GMMx282C_Reserved16_18_OFFSET                           16
+#define GMMx282C_Reserved16_18_WIDTH                            3
+#define GMMx282C_Reserved16_18_MASK                             0x70000
+#define GMMx282C_BASEADDR38_27_OFFSET                           19
+#define GMMx282C_BASEADDR38_27_WIDTH                            12
+#define GMMx282C_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx282C_Reserved31_31_OFFSET                           31
+#define GMMx282C_Reserved31_31_WIDTH                            1
+#define GMMx282C_Reserved31_31_MASK                             0x80000000
+
+/// GMMx282C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx282C_STRUCT;
+
+// **** GMMx2830 Register Definition ****
+// Address
+#define GMMx2830_ADDRESS                                        0x2830
+
+// Type
+#define GMMx2830_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2830_CSENABLE_OFFSET                                0
+#define GMMx2830_CSENABLE_WIDTH                                 1
+#define GMMx2830_CSENABLE_MASK                                  0x1
+#define GMMx2830_Reserved_OFFSET                                1
+#define GMMx2830_Reserved_WIDTH                                 4
+#define GMMx2830_Reserved_MASK                                  0x1e
+#define GMMx2830_BASEADDR21_11_OFFSET                           5
+#define GMMx2830_BASEADDR21_11_WIDTH                            11
+#define GMMx2830_BASEADDR21_11_MASK                             0xffe0
+#define GMMx2830_Reserved16_18_OFFSET                           16
+#define GMMx2830_Reserved16_18_WIDTH                            3
+#define GMMx2830_Reserved16_18_MASK                             0x70000
+#define GMMx2830_BASEADDR38_27_OFFSET                           19
+#define GMMx2830_BASEADDR38_27_WIDTH                            12
+#define GMMx2830_BASEADDR38_27_MASK                             0x7ff80000
+#define GMMx2830_Reserved31_31_OFFSET                           31
+#define GMMx2830_Reserved31_31_WIDTH                            1
+#define GMMx2830_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2830
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 CSENABLE:1 ; ///<
+    UINT32                                                 Reserved:4 ; ///<
+    UINT32                                            BASEADDR21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            BASEADDR38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2830_STRUCT;
+
+// **** GMMx2834 Register Definition ****
+// Address
+#define GMMx2834_ADDRESS                                        0x2834
+
+// Type
+#define GMMx2834_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2834_Reserved_OFFSET                                0
+#define GMMx2834_Reserved_WIDTH                                 5
+#define GMMx2834_Reserved_MASK                                  0x1f
+#define GMMx2834_ADDRMASK21_11_OFFSET                           5
+#define GMMx2834_ADDRMASK21_11_WIDTH                            11
+#define GMMx2834_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx2834_Reserved16_18_OFFSET                           16
+#define GMMx2834_Reserved16_18_WIDTH                            3
+#define GMMx2834_Reserved16_18_MASK                             0x70000
+#define GMMx2834_ADDRMASK38_27_OFFSET                           19
+#define GMMx2834_ADDRMASK38_27_WIDTH                            12
+#define GMMx2834_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx2834_Reserved31_31_OFFSET                           31
+#define GMMx2834_Reserved31_31_WIDTH                            1
+#define GMMx2834_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2834
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2834_STRUCT;
+
+// **** GMMx2838 Register Definition ****
+// Address
+#define GMMx2838_ADDRESS                                        0x2838
+
+// Type
+#define GMMx2838_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2838_Reserved_OFFSET                                0
+#define GMMx2838_Reserved_WIDTH                                 5
+#define GMMx2838_Reserved_MASK                                  0x1f
+#define GMMx2838_ADDRMASK21_11_OFFSET                           5
+#define GMMx2838_ADDRMASK21_11_WIDTH                            11
+#define GMMx2838_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx2838_Reserved16_18_OFFSET                           16
+#define GMMx2838_Reserved16_18_WIDTH                            3
+#define GMMx2838_Reserved16_18_MASK                             0x70000
+#define GMMx2838_ADDRMASK38_27_OFFSET                           19
+#define GMMx2838_ADDRMASK38_27_WIDTH                            12
+#define GMMx2838_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx2838_Reserved31_31_OFFSET                           31
+#define GMMx2838_Reserved31_31_WIDTH                            1
+#define GMMx2838_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2838
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2838_STRUCT;
+
+// **** GMMx283C Register Definition ****
+// Address
+#define GMMx283C_ADDRESS                                        0x283c
+
+// Type
+#define GMMx283C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx283C_Reserved_OFFSET                                0
+#define GMMx283C_Reserved_WIDTH                                 5
+#define GMMx283C_Reserved_MASK                                  0x1f
+#define GMMx283C_ADDRMASK21_11_OFFSET                           5
+#define GMMx283C_ADDRMASK21_11_WIDTH                            11
+#define GMMx283C_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx283C_Reserved16_18_OFFSET                           16
+#define GMMx283C_Reserved16_18_WIDTH                            3
+#define GMMx283C_Reserved16_18_MASK                             0x70000
+#define GMMx283C_ADDRMASK38_27_OFFSET                           19
+#define GMMx283C_ADDRMASK38_27_WIDTH                            12
+#define GMMx283C_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx283C_Reserved31_31_OFFSET                           31
+#define GMMx283C_Reserved31_31_WIDTH                            1
+#define GMMx283C_Reserved31_31_MASK                             0x80000000
+
+/// GMMx283C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx283C_STRUCT;
+
+// **** GMMx2840 Register Definition ****
+// Address
+#define GMMx2840_ADDRESS                                        0x2840
+
+// Type
+#define GMMx2840_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2840_Reserved_OFFSET                                0
+#define GMMx2840_Reserved_WIDTH                                 5
+#define GMMx2840_Reserved_MASK                                  0x1f
+#define GMMx2840_ADDRMASK21_11_OFFSET                           5
+#define GMMx2840_ADDRMASK21_11_WIDTH                            11
+#define GMMx2840_ADDRMASK21_11_MASK                             0xffe0
+#define GMMx2840_Reserved16_18_OFFSET                           16
+#define GMMx2840_Reserved16_18_WIDTH                            3
+#define GMMx2840_Reserved16_18_MASK                             0x70000
+#define GMMx2840_ADDRMASK38_27_OFFSET                           19
+#define GMMx2840_ADDRMASK38_27_WIDTH                            12
+#define GMMx2840_ADDRMASK38_27_MASK                             0x7ff80000
+#define GMMx2840_Reserved31_31_OFFSET                           31
+#define GMMx2840_Reserved31_31_WIDTH                            1
+#define GMMx2840_Reserved31_31_MASK                             0x80000000
+
+/// GMMx2840
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:5 ; ///<
+    UINT32                                            ADDRMASK21_11:11; ///<
+    UINT32                                            Reserved16_18:3 ; ///<
+    UINT32                                            ADDRMASK38_27:12; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2840_STRUCT;
+
+// **** GMMx2844 Register Definition ****
+// Address
+#define GMMx2844_ADDRESS                                        0x2844
+
+// Type
+#define GMMx2844_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2844_DIMM0ADDRMAP_OFFSET                            0
+#define GMMx2844_DIMM0ADDRMAP_WIDTH                             4
+#define GMMx2844_DIMM0ADDRMAP_MASK                              0xf
+#define GMMx2844_DIMM1ADDRMAP_OFFSET                            4
+#define GMMx2844_DIMM1ADDRMAP_WIDTH                             4
+#define GMMx2844_DIMM1ADDRMAP_MASK                              0xf0
+#define GMMx2844_Reserved_OFFSET                                8
+#define GMMx2844_Reserved_WIDTH                                 8
+#define GMMx2844_Reserved_MASK                                  0xff00
+#define GMMx2844_BANKSWIZZLEMODE_OFFSET                         16
+#define GMMx2844_BANKSWIZZLEMODE_WIDTH                          1
+#define GMMx2844_BANKSWIZZLEMODE_MASK                           0x10000
+#define GMMx2844_DDR3MODE_OFFSET                                17
+#define GMMx2844_DDR3MODE_WIDTH                                 1
+#define GMMx2844_DDR3MODE_MASK                                  0x20000
+#define GMMx2844_BURSTLENGTH32_OFFSET                           18
+#define GMMx2844_BURSTLENGTH32_WIDTH                            1
+#define GMMx2844_BURSTLENGTH32_MASK                             0x40000
+#define GMMx2844_BANKSWAP_OFFSET                                19
+#define GMMx2844_BANKSWAP_WIDTH                                 1
+#define GMMx2844_BANKSWAP_MASK                                  0x80000
+#define GMMx2844_Reserved20_31_OFFSET                           20
+#define GMMx2844_Reserved20_31_WIDTH                            12
+#define GMMx2844_Reserved20_31_MASK                             0xfff00000
+
+/// GMMx2844
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DIMM0ADDRMAP:4 ; ///<
+    UINT32                                             DIMM1ADDRMAP:4 ; ///<
+    UINT32                                                 Reserved:8 ; ///<
+    UINT32                                          BANKSWIZZLEMODE:1 ; ///<
+    UINT32                                                 DDR3MODE:1 ; ///<
+    UINT32                                            BURSTLENGTH32:1 ; ///<
+    UINT32                                                 BANKSWAP:1 ; ///<
+    UINT32                                            Reserved20_31:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2844_STRUCT;
+
+// **** GMMx2848 Register Definition ****
+// Address
+#define GMMx2848_ADDRESS                                        0x2848
+
+// Type
+#define GMMx2848_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2848_DIMM0ADDRMAP_OFFSET                            0
+#define GMMx2848_DIMM0ADDRMAP_WIDTH                             4
+#define GMMx2848_DIMM0ADDRMAP_MASK                              0xf
+#define GMMx2848_DIMM1ADDRMAP_OFFSET                            4
+#define GMMx2848_DIMM1ADDRMAP_WIDTH                             4
+#define GMMx2848_DIMM1ADDRMAP_MASK                              0xf0
+#define GMMx2848_Reserved_OFFSET                                8
+#define GMMx2848_Reserved_WIDTH                                 8
+#define GMMx2848_Reserved_MASK                                  0xff00
+#define GMMx2848_BANKSWIZZLEMODE_OFFSET                         16
+#define GMMx2848_BANKSWIZZLEMODE_WIDTH                          1
+#define GMMx2848_BANKSWIZZLEMODE_MASK                           0x10000
+#define GMMx2848_DDR3MODE_OFFSET                                17
+#define GMMx2848_DDR3MODE_WIDTH                                 1
+#define GMMx2848_DDR3MODE_MASK                                  0x20000
+#define GMMx2848_BURSTLENGTH32_OFFSET                           18
+#define GMMx2848_BURSTLENGTH32_WIDTH                            1
+#define GMMx2848_BURSTLENGTH32_MASK                             0x40000
+#define GMMx2848_BANKSWAP_OFFSET                                19
+#define GMMx2848_BANKSWAP_WIDTH                                 1
+#define GMMx2848_BANKSWAP_MASK                                  0x80000
+#define GMMx2848_Reserved20_31_OFFSET                           20
+#define GMMx2848_Reserved20_31_WIDTH                            12
+#define GMMx2848_Reserved20_31_MASK                             0xfff00000
+
+/// GMMx2848
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             DIMM0ADDRMAP:4 ; ///<
+    UINT32                                             DIMM1ADDRMAP:4 ; ///<
+    UINT32                                                 Reserved:8 ; ///<
+    UINT32                                          BANKSWIZZLEMODE:1 ; ///<
+    UINT32                                                 DDR3MODE:1 ; ///<
+    UINT32                                            BURSTLENGTH32:1 ; ///<
+    UINT32                                                 BANKSWAP:1 ; ///<
+    UINT32                                            Reserved20_31:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2848_STRUCT;
+
+// **** GMMx284C Register Definition ****
+// Address
+#define GMMx284C_ADDRESS                                        0x284c
+
+// Type
+#define GMMx284C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx284C_DCTSELHIRNGEN_OFFSET                           0
+#define GMMx284C_DCTSELHIRNGEN_WIDTH                            1
+#define GMMx284C_DCTSELHIRNGEN_MASK                             0x1
+#define GMMx284C_DCTSELHI_OFFSET                                1
+#define GMMx284C_DCTSELHI_WIDTH                                 1
+#define GMMx284C_DCTSELHI_MASK                                  0x2
+#define GMMx284C_DCTSELINTLVEN_OFFSET                           2
+#define GMMx284C_DCTSELINTLVEN_WIDTH                            1
+#define GMMx284C_DCTSELINTLVEN_MASK                             0x4
+#define GMMx284C_Reserved_OFFSET                                3
+#define GMMx284C_Reserved_WIDTH                                 3
+#define GMMx284C_Reserved_MASK                                  0x38
+#define GMMx284C_DCTSELINTLVADDR_1_0_OFFSET                     6
+#define GMMx284C_DCTSELINTLVADDR_1_0_WIDTH                      2
+#define GMMx284C_DCTSELINTLVADDR_1_0_MASK                       0xc0
+#define GMMx284C_Reserved8_10_OFFSET                            8
+#define GMMx284C_Reserved8_10_WIDTH                             3
+#define GMMx284C_Reserved8_10_MASK                              0x700
+#define GMMx284C_DCTSELBASEADDR39_27_OFFSET                     11
+#define GMMx284C_DCTSELBASEADDR39_27_WIDTH                      13
+#define GMMx284C_DCTSELBASEADDR39_27_MASK                       0xfff800
+#define GMMx284C_Reserved24_31_OFFSET                           24
+#define GMMx284C_Reserved24_31_WIDTH                            8
+#define GMMx284C_Reserved24_31_MASK                             0xff000000
+
+/// GMMx284C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DCTSELHIRNGEN:1 ; ///<
+    UINT32                                                 DCTSELHI:1 ; ///<
+    UINT32                                            DCTSELINTLVEN:1 ; ///<
+    UINT32                                                 Reserved:3 ; ///<
+    UINT32                                      DCTSELINTLVADDR_1_0:2 ; ///<
+    UINT32                                             Reserved8_10:3 ; ///<
+    UINT32                                      DCTSELBASEADDR39_27:13; ///<
+    UINT32                                            Reserved24_31:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx284C_STRUCT;
+
+// **** GMMx2850 Register Definition ****
+// Address
+#define GMMx2850_ADDRESS                                        0x2850
+
+// Type
+#define GMMx2850_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2850_Reserved_OFFSET                                0
+#define GMMx2850_Reserved_WIDTH                                 9
+#define GMMx2850_Reserved_MASK                                  0x1ff
+#define GMMx2850_DCTSELINTLVADDR_2_OFFSET                       9
+#define GMMx2850_DCTSELINTLVADDR_2_WIDTH                        1
+#define GMMx2850_DCTSELINTLVADDR_2_MASK                         0x200
+#define GMMx2850_DCTSELBASEOFFSET_39_26_OFFSET                  10
+#define GMMx2850_DCTSELBASEOFFSET_39_26_WIDTH                   14
+#define GMMx2850_DCTSELBASEOFFSET_39_26_MASK                    0xfffc00
+#define GMMx2850_Reserved24_31_OFFSET                           24
+#define GMMx2850_Reserved24_31_WIDTH                            8
+#define GMMx2850_Reserved24_31_MASK                             0xff000000
+
+/// GMMx2850
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                 Reserved:9 ; ///<
+    UINT32                                        DCTSELINTLVADDR_2:1 ; ///<
+    UINT32                                   DCTSELBASEOFFSET_39_26:14; ///<
+    UINT32                                            Reserved24_31:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2850_STRUCT;
+
+// **** GMMx2854 Register Definition ****
+// Address
+#define GMMx2854_ADDRESS                                        0x2854
+
+// Type
+#define GMMx2854_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2854_DRAMHOLEVALID_OFFSET                           0
+#define GMMx2854_DRAMHOLEVALID_WIDTH                            1
+#define GMMx2854_DRAMHOLEVALID_MASK                             0x1
+#define GMMx2854_Reserved_OFFSET                                1
+#define GMMx2854_Reserved_WIDTH                                 1
+#define GMMx2854_Reserved_MASK                                  0x2
+#define GMMx2854_DRAMHTHOLEVALID_OFFSET                         2
+#define GMMx2854_DRAMHTHOLEVALID_WIDTH                          1
+#define GMMx2854_DRAMHTHOLEVALID_MASK                           0x4
+#define GMMx2854_Reserved3_6_OFFSET                             3
+#define GMMx2854_Reserved3_6_WIDTH                              4
+#define GMMx2854_Reserved3_6_MASK                               0x78
+#define GMMx2854_DRAMHOLEOFFSET31_23_OFFSET                     7
+#define GMMx2854_DRAMHOLEOFFSET31_23_WIDTH                      9
+#define GMMx2854_DRAMHOLEOFFSET31_23_MASK                       0xff80
+#define GMMx2854_Reserved16_23_OFFSET                           16
+#define GMMx2854_Reserved16_23_WIDTH                            8
+#define GMMx2854_Reserved16_23_MASK                             0xff0000
+#define GMMx2854_DRAMHOLEBASE31_24_OFFSET                       24
+#define GMMx2854_DRAMHOLEBASE31_24_WIDTH                        8
+#define GMMx2854_DRAMHOLEBASE31_24_MASK                         0xff000000
+
+/// GMMx2854
+typedef union {
+  struct {                                                              ///<
+    UINT32                                            DRAMHOLEVALID:1 ; ///<
+    UINT32                                                 Reserved:1 ; ///<
+    UINT32                                          DRAMHTHOLEVALID:1 ; ///<
+    UINT32                                              Reserved3_6:4 ; ///<
+    UINT32                                      DRAMHOLEOFFSET31_23:9 ; ///<
+    UINT32                                            Reserved16_23:8 ; ///<
+    UINT32                                        DRAMHOLEBASE31_24:8 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2854_STRUCT;
+
+// **** GMMx285C Register Definition ****
+// Address
+#define GMMx285C_ADDRESS                                        0x285c
+
+// Type
+#define GMMx285C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx285C_INTLVRGNSWAPEN_OFFSET                          0
+#define GMMx285C_INTLVRGNSWAPEN_WIDTH                           1
+#define GMMx285C_INTLVRGNSWAPEN_MASK                            0x1
+#define GMMx285C_Reserved_OFFSET                                1
+#define GMMx285C_Reserved_WIDTH                                 2
+#define GMMx285C_Reserved_MASK                                  0x6
+#define GMMx285C_INTLVRGNBASEADDR33_27_OFFSET                   3
+#define GMMx285C_INTLVRGNBASEADDR33_27_WIDTH                    7
+#define GMMx285C_INTLVRGNBASEADDR33_27_MASK                     0x3f8
+#define GMMx285C_Reserved10_10_OFFSET                           10
+#define GMMx285C_Reserved10_10_WIDTH                            1
+#define GMMx285C_Reserved10_10_MASK                             0x400
+#define GMMx285C_INTLVRGNLMTADDR33_27_OFFSET                    11
+#define GMMx285C_INTLVRGNLMTADDR33_27_WIDTH                     7
+#define GMMx285C_INTLVRGNLMTADDR33_27_MASK                      0x3f800
+#define GMMx285C_Reserved18_19_OFFSET                           18
+#define GMMx285C_Reserved18_19_WIDTH                            2
+#define GMMx285C_Reserved18_19_MASK                             0xc0000
+#define GMMx285C_INTLVRGNSIZE33_27_OFFSET                       20
+#define GMMx285C_INTLVRGNSIZE33_27_WIDTH                        7
+#define GMMx285C_INTLVRGNSIZE33_27_MASK                         0x7f00000
+#define GMMx285C_Reserved27_31_OFFSET                           27
+#define GMMx285C_Reserved27_31_WIDTH                            5
+#define GMMx285C_Reserved27_31_MASK                             0xf8000000
+
+/// GMMx285C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           INTLVRGNSWAPEN:1 ; ///<
+    UINT32                                                 Reserved:2 ; ///<
+    UINT32                                    INTLVRGNBASEADDR33_27:7 ; ///<
+    UINT32                                            Reserved10_10:1 ; ///<
+    UINT32                                     INTLVRGNLMTADDR33_27:7 ; ///<
+    UINT32                                            Reserved18_19:2 ; ///<
+    UINT32                                        INTLVRGNSIZE33_27:7 ; ///<
+    UINT32                                            Reserved27_31:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx285C_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     BASE:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1064_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      TOP:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1065_STRUCT;
+
+// **** GMMx2870 Register Definition ****
+// Address
+#define GMMx2870_ADDRESS                                        0x2870
+
+// Type
+#define GMMx2870_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2870_BASE_OFFSET                                    0
+#define GMMx2870_BASE_WIDTH                                     20
+#define GMMx2870_BASE_MASK                                      0xfffff
+#define GMMx2870_Reserved_OFFSET                                20
+#define GMMx2870_Reserved_WIDTH                                 12
+#define GMMx2870_Reserved_MASK                                  0xfff00000
+
+/// GMMx2870
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                     BASE:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2870_STRUCT;
+
+// **** GMMx2874 Register Definition ****
+// Address
+#define GMMx2874_ADDRESS                                        0x2874
+
+// Type
+#define GMMx2874_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2874_TOP_OFFSET                                     0
+#define GMMx2874_TOP_WIDTH                                      20
+#define GMMx2874_TOP_MASK                                       0xfffff
+#define GMMx2874_Reserved_OFFSET                                20
+#define GMMx2874_Reserved_WIDTH                                 12
+#define GMMx2874_Reserved_MASK                                  0xfff00000
+
+/// GMMx2874
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      TOP:20; ///<
+    UINT32                                                 Reserved:12; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2874_STRUCT;
+
+
+// **** GMMx287C Register Definition ****
+// Address
+#define GMMx287C_ADDRESS                                        0x287c
+
+// Type
+#define GMMx287C_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx287C_DEF_OFFSET                                     0
+#define GMMx287C_DEF_WIDTH                                      28
+#define GMMx287C_DEF_MASK                                       0xfffffff
+#define GMMx287C_Reserved_OFFSET                                28
+#define GMMx287C_Reserved_WIDTH                                 4
+#define GMMx287C_Reserved_MASK                                  0xf0000000
+
+/// GMMx287C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                      DEF:28; ///<
+    UINT32                                                 Reserved:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx287C_STRUCT;
+
+// **** GMMx2888 Register Definition ****
+// Address
+#define GMMx2888_ADDRESS                                        0x2888
+
+// Type
+#define GMMx2888_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2888_NO_XBAR_OFFSET                                 0
+#define GMMx2888_NO_XBAR_WIDTH                                  1
+#define GMMx2888_NO_XBAR_MASK                                   0x1
+#define GMMx2888_XBAR_UVD_HP_RD_OFFSET                          1
+#define GMMx2888_XBAR_UVD_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_UVD_HP_RD_MASK                            0x2
+#define GMMx2888_XBAR_UMC_HP_RD_OFFSET                          2
+#define GMMx2888_XBAR_UMC_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_UMC_HP_RD_MASK                            0x4
+#define GMMx2888_XBAR_VCE_HP_RD_OFFSET                          3
+#define GMMx2888_XBAR_VCE_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_VCE_HP_RD_MASK                            0x8
+#define GMMx2888_XBAR_VCEU_HP_RD_OFFSET                         4
+#define GMMx2888_XBAR_VCEU_HP_RD_WIDTH                          1
+#define GMMx2888_XBAR_VCEU_HP_RD_MASK                           0x10
+#define GMMx2888_XBAR_VMC_HP_RD_OFFSET                          5
+#define GMMx2888_XBAR_VMC_HP_RD_WIDTH                           1
+#define GMMx2888_XBAR_VMC_HP_RD_MASK                            0x20
+#define GMMx2888_XBAR_DMIF_HP_RD_OFFSET                         6
+#define GMMx2888_XBAR_DMIF_HP_RD_WIDTH                          1
+#define GMMx2888_XBAR_DMIF_HP_RD_MASK                           0x40
+#define GMMx2888_XBAR_UVD_HP_WR_OFFSET                          7
+#define GMMx2888_XBAR_UVD_HP_WR_WIDTH                           1
+#define GMMx2888_XBAR_UVD_HP_WR_MASK                            0x80
+#define GMMx2888_XBAR_UMC_HP_WR_OFFSET                          8
+#define GMMx2888_XBAR_UMC_HP_WR_WIDTH                           1
+#define GMMx2888_XBAR_UMC_HP_WR_MASK                            0x100
+#define GMMx2888_XBAR_VCE_HP_WR_OFFSET                          9
+#define GMMx2888_XBAR_VCE_HP_WR_WIDTH                           1
+#define GMMx2888_XBAR_VCE_HP_WR_MASK                            0x200
+#define GMMx2888_XBAR_VCEU_HP_WR_OFFSET                         10
+#define GMMx2888_XBAR_VCEU_HP_WR_WIDTH                          1
+#define GMMx2888_XBAR_VCEU_HP_WR_MASK                           0x400
+#define GMMx2888_Reserved_OFFSET                                11
+#define GMMx2888_Reserved_WIDTH                                 21
+#define GMMx2888_Reserved_MASK                                  0xfffff800
+
+/// GMMx2888
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                  NO_XBAR:1 ; ///<
+    UINT32                                           XBAR_UVD_HP_RD:1 ; ///<
+    UINT32                                           XBAR_UMC_HP_RD:1 ; ///<
+    UINT32                                           XBAR_VCE_HP_RD:1 ; ///<
+    UINT32                                          XBAR_VCEU_HP_RD:1 ; ///<
+    UINT32                                           XBAR_VMC_HP_RD:1 ; ///<
+    UINT32                                          XBAR_DMIF_HP_RD:1 ; ///<
+    UINT32                                           XBAR_UVD_HP_WR:1 ; ///<
+    UINT32                                           XBAR_UMC_HP_WR:1 ; ///<
+    UINT32                                           XBAR_VCE_HP_WR:1 ; ///<
+    UINT32                                          XBAR_VCEU_HP_WR:1 ; ///<
+    UINT32                                                 Reserved:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2888_STRUCT;
+
+
+// **** GMMx28D4 Register Definition ****
+// Address
+#define GMMx28D4_ADDRESS                                        0x28d4
+
+// Type
+#define GMMx28D4_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_OFFSET                  0
+#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_WIDTH                   1
+#define GMMx28D4_RENG_EXECUTE_ON_PWR_UP_MASK                    0x1
+#define GMMx28D4_RENG_EXECUTE_NOW_OFFSET                        1
+#define GMMx28D4_RENG_EXECUTE_NOW_WIDTH                         1
+#define GMMx28D4_RENG_EXECUTE_NOW_MASK                          0x2
+#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_OFFSET              2
+#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_WIDTH               10
+#define GMMx28D4_RENG_EXECUTE_NOW_START_PTR_MASK                0xffc
+#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_OFFSET                12
+#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_WIDTH                 10
+#define GMMx28D4_RENG_EXECUTE_DSP_END_PTR_MASK                  0x3ff000
+#define GMMx28D4_RENG_EXECUTE_END_PTR_OFFSET                    22
+#define GMMx28D4_RENG_EXECUTE_END_PTR_WIDTH                     10
+#define GMMx28D4_RENG_EXECUTE_END_PTR_MASK                      0xffc00000
+
+/// GMMx28D4
+typedef union {
+  struct {                                                              ///<
+    UINT32                                   RENG_EXECUTE_ON_PWR_UP:1 ; ///<
+    UINT32                                         RENG_EXECUTE_NOW:1 ; ///<
+    UINT32                               RENG_EXECUTE_NOW_START_PTR:10; ///<
+    UINT32                                 RENG_EXECUTE_DSP_END_PTR:10; ///<
+    UINT32                                     RENG_EXECUTE_END_PTR:10; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx28D4_STRUCT;
+
+// **** GMMx28D8 Register Definition ****
+// Address
+#define GMMx28D8_ADDRESS                                        0x28d8
+
+// Type
+#define GMMx28D8_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_OFFSET        0
+#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_WIDTH         10
+#define GMMx28D8_RENG_EXECUTE_NONSECURE_START_PTR_MASK          0x3ff
+#define GMMx28D8_RENG_EXECUTE_NOW_MODE_OFFSET                   10
+#define GMMx28D8_RENG_EXECUTE_NOW_MODE_WIDTH                    1
+#define GMMx28D8_RENG_EXECUTE_NOW_MODE_MASK                     0x400
+#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_OFFSET              11
+#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_WIDTH               1
+#define GMMx28D8_RENG_EXECUTE_ON_REG_UPDATE_MASK                0x800
+#define GMMx28D8_RENG_SRBM_CREDITS_MCD_OFFSET                   12
+#define GMMx28D8_RENG_SRBM_CREDITS_MCD_WIDTH                    4
+#define GMMx28D8_RENG_SRBM_CREDITS_MCD_MASK                     0xf000
+#define GMMx28D8_STCTRL_STUTTER_EN_OFFSET                       16
+#define GMMx28D8_STCTRL_STUTTER_EN_WIDTH                        1
+#define GMMx28D8_STCTRL_STUTTER_EN_MASK                         0x10000
+#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_OFFSET               17
+#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_WIDTH                2
+#define GMMx28D8_STCTRL_GMC_IDLE_THRESHOLD_MASK                 0x60000
+#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_OFFSET              19
+#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_WIDTH               2
+#define GMMx28D8_STCTRL_SRBM_IDLE_THRESHOLD_MASK                0x180000
+#define GMMx28D8_STCTRL_IGNORE_PRE_SR_OFFSET                    21
+#define GMMx28D8_STCTRL_IGNORE_PRE_SR_WIDTH                     1
+#define GMMx28D8_STCTRL_IGNORE_PRE_SR_MASK                      0x200000
+#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_OFFSET                22
+#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_WIDTH                 1
+#define GMMx28D8_STCTRL_IGNORE_ALLOW_STOP_MASK                  0x400000
+#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_OFFSET                 23
+#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_WIDTH                  1
+#define GMMx28D8_STCTRL_IGNORE_SR_COMMIT_MASK                   0x800000
+#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_OFFSET          24
+#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_WIDTH           1
+#define GMMx28D8_STCTRL_IGNORE_PROTECTION_FAULT_MASK            0x1000000
+#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_OFFSET                 25
+#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_WIDTH                  1
+#define GMMx28D8_STCTRL_DISABLE_ALLOW_SR_MASK                   0x2000000
+#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_OFFSET              26
+#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_WIDTH               1
+#define GMMx28D8_STCTRL_DISABLE_GMC_OFFLINE_MASK                0x4000000
+#define GMMx28D8_CRITICAL_REGS_LOCK_OFFSET                      27
+#define GMMx28D8_CRITICAL_REGS_LOCK_WIDTH                       1
+#define GMMx28D8_CRITICAL_REGS_LOCK_MASK                        0x8000000
+#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_OFFSET                   28
+#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_WIDTH                    2
+#define GMMx28D8_ALLOW_DEEP_SLEEP_MODE_MASK                     0x30000000
+#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_OFFSET                   30
+#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_WIDTH                    1
+#define GMMx28D8_STCTRL_FORCE_ALLOW_SR_MASK                     0x40000000
+#define GMMx28D8_Reserved_OFFSET                                31
+#define GMMx28D8_Reserved_WIDTH                                 1
+#define GMMx28D8_Reserved_MASK                                  0x80000000
+
+/// GMMx28D8
+typedef union {
+  struct {                                                              ///<
+    UINT32                         RENG_EXECUTE_NONSECURE_START_PTR:10; ///<
+    UINT32                                    RENG_EXECUTE_NOW_MODE:1 ; ///<
+    UINT32                               RENG_EXECUTE_ON_REG_UPDATE:1 ; ///<
+    UINT32                                    RENG_SRBM_CREDITS_MCD:4 ; ///<
+    UINT32                                        STCTRL_STUTTER_EN:1 ; ///<
+    UINT32                                STCTRL_GMC_IDLE_THRESHOLD:2 ; ///<
+    UINT32                               STCTRL_SRBM_IDLE_THRESHOLD:2 ; ///<
+    UINT32                                     STCTRL_IGNORE_PRE_SR:1 ; ///<
+    UINT32                                 STCTRL_IGNORE_ALLOW_STOP:1 ; ///<
+    UINT32                                  STCTRL_IGNORE_SR_COMMIT:1 ; ///<
+    UINT32                           STCTRL_IGNORE_PROTECTION_FAULT:1 ; ///<
+    UINT32                                  STCTRL_DISABLE_ALLOW_SR:1 ; ///<
+    UINT32                               STCTRL_DISABLE_GMC_OFFLINE:1 ; ///<
+    UINT32                                       CRITICAL_REGS_LOCK:1 ; ///<
+    UINT32                                    ALLOW_DEEP_SLEEP_MODE:2 ; ///<
+    UINT32                                    STCTRL_FORCE_ALLOW_SR:1 ; ///<
+    UINT32                                                 Reserved:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx28D8_STRUCT;
+
+// **** GMMx2C04 Register Definition ****
+// Address
+#define GMMx2C04_ADDRESS                                        0x2c04
+
+// Type
+#define GMMx2C04_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx2C04_NONSURF_BASE_OFFSET                            0
+#define GMMx2C04_NONSURF_BASE_WIDTH                             32
+#define GMMx2C04_NONSURF_BASE_MASK                              0xffffffff
+
+/// GMMx2C04
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             NONSURF_BASE:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx2C04_STRUCT;
+
+// **** GMMx5428 Register Definition ****
+// Address
+#define GMMx5428_ADDRESS                                        0x5428
+
+// Type
+#define GMMx5428_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5428_CONFIG_MEMSIZE_OFFSET                          0
+#define GMMx5428_CONFIG_MEMSIZE_WIDTH                           32
+#define GMMx5428_CONFIG_MEMSIZE_MASK                            0xffffffff
+
+/// GMMx5428
+typedef union {
+  struct {                                                              ///<
+    UINT32                                           CONFIG_MEMSIZE:32; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5428_STRUCT;
+
+// **** GMMx5490 Register Definition ****
+// Address
+#define GMMx5490_ADDRESS                                        0x5490
+
+// Type
+#define GMMx5490_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5490_FB_READ_EN_OFFSET                              0
+#define GMMx5490_FB_READ_EN_WIDTH                               1
+#define GMMx5490_FB_READ_EN_MASK                                0x1
+#define GMMx5490_FB_WRITE_EN_OFFSET                             1
+#define GMMx5490_FB_WRITE_EN_WIDTH                              1
+#define GMMx5490_FB_WRITE_EN_MASK                               0x2
+#define GMMx5490_Reserved_OFFSET                                2
+#define GMMx5490_Reserved_WIDTH                                 30
+#define GMMx5490_Reserved_MASK                                  0xfffffffc
+
+/// GMMx5490
+typedef union {
+  struct {                                                              ///<
+    UINT32                                               FB_READ_EN:1 ; ///<
+    UINT32                                              FB_WRITE_EN:1 ; ///<
+    UINT32                                                 Reserved:30; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5490_STRUCT;
+
+// **** MSRC001_0010 Register Definition ****
+// Address
+#define MSRC001_0010_ADDRESS                                    0xc0010010
+
+// Type
+#define MSRC001_0010_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_0010_Reserved_15_0_OFFSET                       0
+#define MSRC001_0010_Reserved_15_0_WIDTH                        16
+#define MSRC001_0010_Reserved_15_0_MASK                         0xffff
+#define MSRC001_0010_ChgToDirtyDis_OFFSET                       16
+#define MSRC001_0010_ChgToDirtyDis_WIDTH                        1
+#define MSRC001_0010_ChgToDirtyDis_MASK                         0x10000
+#define MSRC001_0010_Reserved_17_17_OFFSET                      17
+#define MSRC001_0010_Reserved_17_17_WIDTH                       1
+#define MSRC001_0010_Reserved_17_17_MASK                        0x20000
+#define MSRC001_0010_MtrrFixDramEn_OFFSET                       18
+#define MSRC001_0010_MtrrFixDramEn_WIDTH                        1
+#define MSRC001_0010_MtrrFixDramEn_MASK                         0x40000
+#define MSRC001_0010_MtrrFixDramModEn_OFFSET                    19
+#define MSRC001_0010_MtrrFixDramModEn_WIDTH                     1
+#define MSRC001_0010_MtrrFixDramModEn_MASK                      0x80000
+#define MSRC001_0010_MtrrVarDramEn_OFFSET                       20
+#define MSRC001_0010_MtrrVarDramEn_WIDTH                        1
+#define MSRC001_0010_MtrrVarDramEn_MASK                         0x100000
+#define MSRC001_0010_MtrrTom2En_OFFSET                          21
+#define MSRC001_0010_MtrrTom2En_WIDTH                           1
+#define MSRC001_0010_MtrrTom2En_MASK                            0x200000
+#define MSRC001_0010_Tom2ForceMemTypeWB_OFFSET                  22
+#define MSRC001_0010_Tom2ForceMemTypeWB_WIDTH                   1
+#define MSRC001_0010_Tom2ForceMemTypeWB_MASK                    0x400000
+#define MSRC001_0010_Reserved_63_23_OFFSET                      23
+#define MSRC001_0010_Reserved_63_23_WIDTH                       41
+#define MSRC001_0010_Reserved_63_23_MASK                        0xffffffffff800000
+
+/// MSRC001_0010
+typedef union {
+  struct {                                                              ///<
+    UINT64                                            Reserved_15_0:16; ///<
+    UINT64                                            ChgToDirtyDis:1 ; ///<
+    UINT64                                           Reserved_17_17:1 ; ///<
+    UINT64                                            MtrrFixDramEn:1 ; ///<
+    UINT64                                         MtrrFixDramModEn:1 ; ///<
+    UINT64                                            MtrrVarDramEn:1 ; ///<
+    UINT64                                               MtrrTom2En:1 ; ///<
+    UINT64                                       Tom2ForceMemTypeWB:1 ; ///<
+    UINT64                                           Reserved_63_23:41; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_0010_STRUCT;
+
+// **** MSRC001_001A Register Definition ****
+// Address
+#define MSRC001_001A_ADDRESS                                    0xc001001a
+
+// Type
+#define MSRC001_001A_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_001A_RAZ_22_0_OFFSET                            0
+#define MSRC001_001A_RAZ_22_0_WIDTH                             23
+#define MSRC001_001A_RAZ_22_0_MASK                              0x7fffff
+#define MSRC001_001A_TOM_47_23__OFFSET                          23
+#define MSRC001_001A_TOM_47_23__WIDTH                           25
+#define MSRC001_001A_TOM_47_23__MASK                            0xffffff800000
+#define MSRC001_001A_RAZ_63_48_OFFSET                           48
+#define MSRC001_001A_RAZ_63_48_WIDTH                            16
+#define MSRC001_001A_RAZ_63_48_MASK                             0xffff000000000000
+
+/// MSRC001_001A
+typedef union {
+  struct {                                                              ///<
+    UINT64                                                 RAZ_22_0:23; ///<
+    UINT64                                               TOM_47_23_:25; ///<
+    UINT64                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_001A_STRUCT;
+
+// **** MSRC001_001D Register Definition ****
+// Address
+#define MSRC001_001D_ADDRESS                                    0xc001001d
+
+// Type
+#define MSRC001_001D_TYPE                                       TYPE_MSR
+// Field Data
+#define MSRC001_001D_RAZ_22_0_OFFSET                            0
+#define MSRC001_001D_RAZ_22_0_WIDTH                             23
+#define MSRC001_001D_RAZ_22_0_MASK                              0x7fffff
+#define MSRC001_001D_TOM2_47_23__OFFSET                         23
+#define MSRC001_001D_TOM2_47_23__WIDTH                          25
+#define MSRC001_001D_TOM2_47_23__MASK                           0xffffff800000
+#define MSRC001_001D_RAZ_63_48_OFFSET                           48
+#define MSRC001_001D_RAZ_63_48_WIDTH                            16
+#define MSRC001_001D_RAZ_63_48_MASK                             0xffff000000000000
+
+/// MSRC001_001D
+typedef union {
+  struct {                                                              ///<
+    UINT64                                                 RAZ_22_0:23; ///<
+    UINT64                                              TOM2_47_23_:25; ///<
+    UINT64                                                RAZ_63_48:16; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} MSRC001_001D_STRUCT;
+
+// **** D0F0xBC_xE01040A8 Field Definition ****
+// Address
+#define D0F0xBC_xE01040A8_ADDRESS                               0xe01040a8
+
+// Type
+#define D0F0xBC_xE01040A8_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE01040A8_Reserved0_14_OFFSET                   0
+#define D0F0xBC_xE01040A8_Reserved0_14_WIDTH                    15
+#define D0F0xBC_xE01040A8_Reserved0_14_MASK                     0x7fff
+#define D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET                 15
+#define D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH                  7
+#define D0F0xBC_xE01040A8_SviLoadLineVdd_MASK                   0x3f8000
+#define D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET               22
+#define D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH                7
+#define D0F0xBC_xE01040A8_SviLoadLineVddNb_MASK                 0x1fc00000
+#define D0F0xBC_xE01040A8_Reserved29_31_OFFSET                  29
+#define D0F0xBC_xE01040A8_Reserved29_31_WIDTH                   3
+#define D0F0xBC_xE01040A8_Reserved29_31_MASK                    0xe0000000
+
+/// D0F0xBC_xE01040A8
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved0_14:15; ///<
+    UINT32                                           SviLoadLineVdd:7 ; ///<
+    UINT32                                         SviLoadLineVddNb:7 ; ///<
+    UINT32                                            Reserved29_31:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE01040A8_STRUCT;
+
+// **** D0F0xBC_xE0104158 Field Definition ****
+// Address
+#define D0F0xBC_xE0104158_ADDRESS                               0xe0104158
+
+// Type
+#define D0F0xBC_xE0104158_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104158_Reserved0_9_OFFSET                    0
+#define D0F0xBC_xE0104158_Reserved0_9_WIDTH                     10
+#define D0F0xBC_xE0104158_Reserved0_9_MASK                      0x3ff
+#define D0F0xBC_xE0104158_EClkDid0_OFFSET                       10
+#define D0F0xBC_xE0104158_EClkDid0_WIDTH                        7
+#define D0F0xBC_xE0104158_EClkDid0_MASK                         0x1fc00
+#define D0F0xBC_xE0104158_EClkDid1_OFFSET                       17
+#define D0F0xBC_xE0104158_EClkDid1_WIDTH                        7
+#define D0F0xBC_xE0104158_EClkDid1_MASK                         0xfe0000
+#define D0F0xBC_xE0104158_EClkDid2_OFFSET                       24
+#define D0F0xBC_xE0104158_EClkDid2_WIDTH                        7
+#define D0F0xBC_xE0104158_EClkDid2_MASK                         0x7f000000
+#define D0F0xBC_xE0104158_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0104158_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0104158_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0104158
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_9:10; ///<
+    UINT32                                                 EClkDid0:7 ; ///<
+    UINT32                                                 EClkDid1:7 ; ///<
+    UINT32                                                 EClkDid2:7 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104158_STRUCT;
+
+// **** D0F0xBC_xE010415B Field Definition ****
+// Address
+#define D0F0xBC_xE010415B_ADDRESS                               0xe010415b
+
+// Type
+#define D0F0xBC_xE010415B_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010415B_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010415B_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010415B_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010415B_EClkDid3_OFFSET                       7
+#define D0F0xBC_xE010415B_EClkDid3_WIDTH                        7
+#define D0F0xBC_xE010415B_EClkDid3_MASK                         0x3f80
+#define D0F0xBC_xE010415B_Reserved14_31_OFFSET                  14
+#define D0F0xBC_xE010415B_Reserved14_31_WIDTH                   18
+#define D0F0xBC_xE010415B_Reserved14_31_MASK                    0xffffc000
+
+/// D0F0xBC_xE010415B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                                 EClkDid3:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010415B_STRUCT;
+
+// **** D0F0xBC_xE0104184 Field Definition ****
+// Address
+#define D0F0xBC_xE0104184_ADDRESS                               0xe0104184
+
+// Type
+#define D0F0xBC_xE0104184_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET             0
+#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH              3
+#define D0F0xBC_xE0104184_SviLoadLineTrimVdd_MASK               0x7
+#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET           3
+#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH            3
+#define D0F0xBC_xE0104184_SviLoadLineTrimVddNb_MASK             0x38
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET           6
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH            2
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVdd_MASK             0xc0
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET         8
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH          2
+#define D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_MASK           0x300
+#define D0F0xBC_xE0104184_VCEFlag0_OFFSET                       10
+#define D0F0xBC_xE0104184_VCEFlag0_WIDTH                        8
+#define D0F0xBC_xE0104184_VCEFlag0_MASK                         0x3fc00
+#define D0F0xBC_xE0104184_VCEFlag1_OFFSET                       18
+#define D0F0xBC_xE0104184_VCEFlag1_WIDTH                        8
+#define D0F0xBC_xE0104184_VCEFlag1_MASK                         0x3fc0000
+#define D0F0xBC_xE0104184_Reserved26_31_OFFSET                  26
+#define D0F0xBC_xE0104184_Reserved26_31_WIDTH                   6
+#define D0F0xBC_xE0104184_Reserved26_31_MASK                    0xfc000000
+
+/// D0F0xBC_xE0104184
+typedef union {
+  struct {                                                              ///<
+    UINT32                                       SviLoadLineTrimVdd:3 ; ///<
+    UINT32                                     SviLoadLineTrimVddNb:3 ; ///<
+    UINT32                                     SviLoadLineOffsetVdd:2 ; ///<
+    UINT32                                   SviLoadLineOffsetVddNb:2 ; ///<
+    UINT32                                                 VCEFlag0:8 ; ///<
+    UINT32                                                 VCEFlag1:8 ; ///<
+    UINT32                                            Reserved26_31:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104184_STRUCT;
+
+// **** D0F0xBC_xE0104187 Field Definition ****
+// Address
+#define D0F0xBC_xE0104187_ADDRESS                               0xe0104187
+
+// Type
+#define D0F0xBC_xE0104187_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104187_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE0104187_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE0104187_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE0104187_VCEFlag2_OFFSET                       2
+#define D0F0xBC_xE0104187_VCEFlag2_WIDTH                        8
+#define D0F0xBC_xE0104187_VCEFlag2_MASK                         0x3fc
+#define D0F0xBC_xE0104187_Reserved10_31_OFFSET                  10
+#define D0F0xBC_xE0104187_Reserved10_31_WIDTH                   22
+#define D0F0xBC_xE0104187_Reserved10_31_MASK                    0xfffffc00
+
+/// D0F0xBC_xE0104187
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                                 VCEFlag2:8 ; ///<
+    UINT32                                            Reserved10_31:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104187_STRUCT;
+
+// **** D0F0xBC_xE0104188 Field Definition ****
+// Address
+#define D0F0xBC_xE0104188_ADDRESS                               0xe0104188
+
+// Type
+#define D0F0xBC_xE0104188_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0104188_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE0104188_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE0104188_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE0104188_VCEFlag3_OFFSET                       2
+#define D0F0xBC_xE0104188_VCEFlag3_WIDTH                        8
+#define D0F0xBC_xE0104188_VCEFlag3_MASK                         0x3fc
+#define D0F0xBC_xE0104188_ReqSclkSel0_OFFSET                    10
+#define D0F0xBC_xE0104188_ReqSclkSel0_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel0_MASK                      0x1c00
+#define D0F0xBC_xE0104188_ReqSclkSel1_OFFSET                    13
+#define D0F0xBC_xE0104188_ReqSclkSel1_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel1_MASK                      0xe000
+#define D0F0xBC_xE0104188_ReqSclkSel2_OFFSET                    16
+#define D0F0xBC_xE0104188_ReqSclkSel2_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel2_MASK                      0x70000
+#define D0F0xBC_xE0104188_ReqSclkSel3_OFFSET                    19
+#define D0F0xBC_xE0104188_ReqSclkSel3_WIDTH                     3
+#define D0F0xBC_xE0104188_ReqSclkSel3_MASK                      0x380000
+#define D0F0xBC_xE0104188_VCEMclk_OFFSET                        22
+#define D0F0xBC_xE0104188_VCEMclk_WIDTH                         4
+#define D0F0xBC_xE0104188_VCEMclk_MASK                          0x3c00000
+#define D0F0xBC_xE0104188_LhtcPstateLimit_OFFSET                26
+#define D0F0xBC_xE0104188_LhtcPstateLimit_WIDTH                 3
+#define D0F0xBC_xE0104188_LhtcPstateLimit_MASK                  0x1c000000
+#define D0F0xBC_xE0104188_BapmMeasuredTemp_OFFSET               29
+#define D0F0xBC_xE0104188_BapmMeasuredTemp_WIDTH                1
+#define D0F0xBC_xE0104188_BapmMeasuredTemp_MASK                 0x20000000
+#define D0F0xBC_xE0104188_BapmDisable_OFFSET                    30
+#define D0F0xBC_xE0104188_BapmDisable_WIDTH                     1
+#define D0F0xBC_xE0104188_BapmDisable_MASK                      0x40000000
+#define D0F0xBC_xE0104188_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0104188_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0104188_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0104188
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                                 VCEFlag3:8 ; ///<
+    UINT32                                              ReqSclkSel0:3 ; ///<
+    UINT32                                              ReqSclkSel1:3 ; ///<
+    UINT32                                              ReqSclkSel2:3 ; ///<
+    UINT32                                              ReqSclkSel3:3 ; ///<
+    UINT32                                                  VCEMclk:4 ; ///<
+    UINT32                                          LhtcPstateLimit:3 ; ///<
+    UINT32                                         BapmMeasuredTemp:1 ; ///<
+    UINT32                                              BapmDisable:1 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0104188_STRUCT;
+
+// **** D0F0xBC_xE0106020 Field Definition ****
+// Address
+#define D0F0xBC_xE0106020_ADDRESS                               0xe0106020
+
+// Type
+#define D0F0xBC_xE0106020_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0106020_Reserved0_24_OFFSET                   0
+#define D0F0xBC_xE0106020_Reserved0_24_WIDTH                    25
+#define D0F0xBC_xE0106020_Reserved0_24_MASK                     0x1ffffff
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET          25
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH           2
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel0_MASK            0x6000000
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET          27
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH           2
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel1_MASK            0x18000000
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET          29
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH           2
+#define D0F0xBC_xE0106020_PowerplayDClkVClkSel2_MASK            0x60000000
+#define D0F0xBC_xE0106020_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0106020_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0106020_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0106020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved0_24:25; ///<
+    UINT32                                    PowerplayDClkVClkSel0:2 ; ///<
+    UINT32                                    PowerplayDClkVClkSel1:2 ; ///<
+    UINT32                                    PowerplayDClkVClkSel2:2 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0106020_STRUCT;
+
+// **** D0F0xBC_xE0106023 Field Definition ****
+// Address
+#define D0F0xBC_xE0106023_ADDRESS                               0xe0106023
+
+// Type
+#define D0F0xBC_xE0106023_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0106023_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE0106023_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE0106023_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET          7
+#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH           2
+#define D0F0xBC_xE0106023_PowerplayDClkVClkSel3_MASK            0x180
+#define D0F0xBC_xE0106023_Reserved9_31_OFFSET                   9
+#define D0F0xBC_xE0106023_Reserved9_31_WIDTH                    23
+#define D0F0xBC_xE0106023_Reserved9_31_MASK                     0xfffffe00
+
+/// D0F0xBC_xE0106023
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                    PowerplayDClkVClkSel3:2 ; ///<
+    UINT32                                             Reserved9_31:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0106023_STRUCT;
+
+// **** D0F0xBC_xE0106024 Field Definition ****
+// Address
+#define D0F0xBC_xE0106024_ADDRESS                               0xe0106024
+
+// Type
+#define D0F0xBC_xE0106024_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0106024_Reserved0_0_OFFSET                    0
+#define D0F0xBC_xE0106024_Reserved0_0_WIDTH                     1
+#define D0F0xBC_xE0106024_Reserved0_0_MASK                      0x1
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET          1
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH           2
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel4_MASK            0x6
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET          3
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH           2
+#define D0F0xBC_xE0106024_PowerplayDClkVClkSel5_MASK            0x18
+#define D0F0xBC_xE0106024_Reserved5_31_OFFSET                   5
+#define D0F0xBC_xE0106024_Reserved5_31_WIDTH                    27
+#define D0F0xBC_xE0106024_Reserved5_31_MASK                     0xffffffe0
+
+/// D0F0xBC_xE0106024
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_0:1 ; ///<
+    UINT32                                    PowerplayDClkVClkSel4:2 ; ///<
+    UINT32                                    PowerplayDClkVClkSel5:2 ; ///<
+    UINT32                                             Reserved5_31:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0106024_STRUCT;
+
+
+// **** D0F0xBC_xE010705C Field Definition ****
+// Address
+#define D0F0xBC_xE010705C_ADDRESS                               0xe010705c
+
+// Type
+#define D0F0xBC_xE010705C_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010705C_Reserved0_17_OFFSET                   0
+#define D0F0xBC_xE010705C_Reserved0_17_WIDTH                    18
+#define D0F0xBC_xE010705C_Reserved0_17_MASK                     0x3ffff
+#define D0F0xBC_xE010705C_PowerplayTableRev_OFFSET              18
+#define D0F0xBC_xE010705C_PowerplayTableRev_WIDTH               4
+#define D0F0xBC_xE010705C_PowerplayTableRev_MASK                0x3c0000
+#define D0F0xBC_xE010705C_SClkThermDid_OFFSET                   22
+#define D0F0xBC_xE010705C_SClkThermDid_WIDTH                    7
+#define D0F0xBC_xE010705C_SClkThermDid_MASK                     0x1fc00000
+#define D0F0xBC_xE010705C_PcieGen2Vid_OFFSET                    29
+#define D0F0xBC_xE010705C_PcieGen2Vid_WIDTH                     2
+#define D0F0xBC_xE010705C_PcieGen2Vid_MASK                      0x60000000
+#define D0F0xBC_xE010705C_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE010705C_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE010705C_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE010705C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved0_17:18; ///<
+    UINT32                                        PowerplayTableRev:4 ; ///<
+    UINT32                                             SClkThermDid:7 ; ///<
+    UINT32                                              PcieGen2Vid:2 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010705C_STRUCT;
+
+// **** D0F0xBC_xE010705F Field Definition ****
+// Address
+#define D0F0xBC_xE010705F_ADDRESS                               0xe010705f
+
+// Type
+#define D0F0xBC_xE010705F_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010705F_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010705F_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010705F_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010705F_SClkDpmVid0_OFFSET                    7
+#define D0F0xBC_xE010705F_SClkDpmVid0_WIDTH                     2
+#define D0F0xBC_xE010705F_SClkDpmVid0_MASK                      0x180
+#define D0F0xBC_xE010705F_Reserved9_31_OFFSET                   9
+#define D0F0xBC_xE010705F_Reserved9_31_WIDTH                    23
+#define D0F0xBC_xE010705F_Reserved9_31_MASK                     0xfffffe00
+
+/// D0F0xBC_xE010705F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                              SClkDpmVid0:2 ; ///<
+    UINT32                                             Reserved9_31:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010705F_STRUCT;
+
+// **** D0F0xBC_xE0107060 Field Definition ****
+// Address
+#define D0F0xBC_xE0107060_ADDRESS                               0xe0107060
+
+// Type
+#define D0F0xBC_xE0107060_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107060_Reserved0_0_OFFSET                    0
+#define D0F0xBC_xE0107060_Reserved0_0_WIDTH                     1
+#define D0F0xBC_xE0107060_Reserved0_0_MASK                      0x1
+#define D0F0xBC_xE0107060_SClkDpmVid1_OFFSET                    1
+#define D0F0xBC_xE0107060_SClkDpmVid1_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid1_MASK                      0x6
+#define D0F0xBC_xE0107060_SClkDpmVid2_OFFSET                    3
+#define D0F0xBC_xE0107060_SClkDpmVid2_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid2_MASK                      0x18
+#define D0F0xBC_xE0107060_SClkDpmVid3_OFFSET                    5
+#define D0F0xBC_xE0107060_SClkDpmVid3_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid3_MASK                      0x60
+#define D0F0xBC_xE0107060_SClkDpmVid4_OFFSET                    7
+#define D0F0xBC_xE0107060_SClkDpmVid4_WIDTH                     2
+#define D0F0xBC_xE0107060_SClkDpmVid4_MASK                      0x180
+#define D0F0xBC_xE0107060_SClkDpmDid0_OFFSET                    9
+#define D0F0xBC_xE0107060_SClkDpmDid0_WIDTH                     7
+#define D0F0xBC_xE0107060_SClkDpmDid0_MASK                      0xfe00
+#define D0F0xBC_xE0107060_SClkDpmDid1_OFFSET                    16
+#define D0F0xBC_xE0107060_SClkDpmDid1_WIDTH                     7
+#define D0F0xBC_xE0107060_SClkDpmDid1_MASK                      0x7f0000
+#define D0F0xBC_xE0107060_SClkDpmDid2_OFFSET                    23
+#define D0F0xBC_xE0107060_SClkDpmDid2_WIDTH                     7
+#define D0F0xBC_xE0107060_SClkDpmDid2_MASK                      0x3f800000
+#define D0F0xBC_xE0107060_Reserved30_31_OFFSET                  30
+#define D0F0xBC_xE0107060_Reserved30_31_WIDTH                   2
+#define D0F0xBC_xE0107060_Reserved30_31_MASK                    0xc0000000
+
+/// D0F0xBC_xE0107060
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_0:1 ; ///<
+    UINT32                                              SClkDpmVid1:2 ; ///<
+    UINT32                                              SClkDpmVid2:2 ; ///<
+    UINT32                                              SClkDpmVid3:2 ; ///<
+    UINT32                                              SClkDpmVid4:2 ; ///<
+    UINT32                                              SClkDpmDid0:7 ; ///<
+    UINT32                                              SClkDpmDid1:7 ; ///<
+    UINT32                                              SClkDpmDid2:7 ; ///<
+    UINT32                                            Reserved30_31:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107060_STRUCT;
+
+// **** D0F0xBC_xE0107063 Field Definition ****
+// Address
+#define D0F0xBC_xE0107063_ADDRESS                               0xe0107063
+
+// Type
+#define D0F0xBC_xE0107063_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107063_Reserved0_5_OFFSET                    0
+#define D0F0xBC_xE0107063_Reserved0_5_WIDTH                     6
+#define D0F0xBC_xE0107063_Reserved0_5_MASK                      0x3f
+#define D0F0xBC_xE0107063_SClkDpmDid3_OFFSET                    6
+#define D0F0xBC_xE0107063_SClkDpmDid3_WIDTH                     7
+#define D0F0xBC_xE0107063_SClkDpmDid3_MASK                      0x1fc0
+#define D0F0xBC_xE0107063_Reserved13_31_OFFSET                  13
+#define D0F0xBC_xE0107063_Reserved13_31_WIDTH                   19
+#define D0F0xBC_xE0107063_Reserved13_31_MASK                    0xffffe000
+
+/// D0F0xBC_xE0107063
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_5:6 ; ///<
+    UINT32                                              SClkDpmDid3:7 ; ///<
+    UINT32                                            Reserved13_31:19; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107063_STRUCT;
+
+// **** D0F0xBC_xE0107064 Field Definition ****
+// Address
+#define D0F0xBC_xE0107064_ADDRESS                               0xe0107064
+
+// Type
+#define D0F0xBC_xE0107064_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107064_Reserved0_4_OFFSET                    0
+#define D0F0xBC_xE0107064_Reserved0_4_WIDTH                     5
+#define D0F0xBC_xE0107064_Reserved0_4_MASK                      0x1f
+#define D0F0xBC_xE0107064_SClkDpmDid4_OFFSET                    5
+#define D0F0xBC_xE0107064_SClkDpmDid4_WIDTH                     7
+#define D0F0xBC_xE0107064_SClkDpmDid4_MASK                      0xfe0
+#define D0F0xBC_xE0107064_Reserved12_31_OFFSET                  12
+#define D0F0xBC_xE0107064_Reserved12_31_WIDTH                   20
+#define D0F0xBC_xE0107064_Reserved12_31_MASK                    0xfffff000
+
+/// D0F0xBC_xE0107064
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_4:5 ; ///<
+    UINT32                                              SClkDpmDid4:7 ; ///<
+    UINT32                                            Reserved12_31:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107064_STRUCT;
+
+// **** D0F0xBC_xE0107067 Field Definition ****
+// Address
+#define D0F0xBC_xE0107067_ADDRESS                               0xe0107067
+
+// Type
+#define D0F0xBC_xE0107067_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107067_Reserved0_3_OFFSET                    0
+#define D0F0xBC_xE0107067_Reserved0_3_WIDTH                     4
+#define D0F0xBC_xE0107067_Reserved0_3_MASK                      0xf
+#define D0F0xBC_xE0107067_DispClkDid0_OFFSET                    4
+#define D0F0xBC_xE0107067_DispClkDid0_WIDTH                     7
+#define D0F0xBC_xE0107067_DispClkDid0_MASK                      0x7f0
+#define D0F0xBC_xE0107067_Reserved11_31_OFFSET                  11
+#define D0F0xBC_xE0107067_Reserved11_31_WIDTH                   21
+#define D0F0xBC_xE0107067_Reserved11_31_MASK                    0xfffff800
+
+/// D0F0xBC_xE0107067
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_3:4 ; ///<
+    UINT32                                              DispClkDid0:7 ; ///<
+    UINT32                                            Reserved11_31:21; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107067_STRUCT;
+
+// **** D0F0xBC_xE0107068 Field Definition ****
+// Address
+#define D0F0xBC_xE0107068_ADDRESS                               0xe0107068
+
+// Type
+#define D0F0xBC_xE0107068_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107068_Reserved0_2_OFFSET                    0
+#define D0F0xBC_xE0107068_Reserved0_2_WIDTH                     3
+#define D0F0xBC_xE0107068_Reserved0_2_MASK                      0x7
+#define D0F0xBC_xE0107068_DispClkDid1_OFFSET                    3
+#define D0F0xBC_xE0107068_DispClkDid1_WIDTH                     7
+#define D0F0xBC_xE0107068_DispClkDid1_MASK                      0x3f8
+#define D0F0xBC_xE0107068_DispClkDid2_OFFSET                    10
+#define D0F0xBC_xE0107068_DispClkDid2_WIDTH                     7
+#define D0F0xBC_xE0107068_DispClkDid2_MASK                      0x1fc00
+#define D0F0xBC_xE0107068_DispClkDid3_OFFSET                    17
+#define D0F0xBC_xE0107068_DispClkDid3_WIDTH                     7
+#define D0F0xBC_xE0107068_DispClkDid3_MASK                      0xfe0000
+#define D0F0xBC_xE0107068_LClkDpmDid0_OFFSET                    24
+#define D0F0xBC_xE0107068_LClkDpmDid0_WIDTH                     7
+#define D0F0xBC_xE0107068_LClkDpmDid0_MASK                      0x7f000000
+#define D0F0xBC_xE0107068_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0107068_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0107068_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0107068
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_2:3 ; ///<
+    UINT32                                              DispClkDid1:7 ; ///<
+    UINT32                                              DispClkDid2:7 ; ///<
+    UINT32                                              DispClkDid3:7 ; ///<
+    UINT32                                              LClkDpmDid0:7 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107068_STRUCT;
+
+// **** D0F0xBC_xE010706B Field Definition ****
+// Address
+#define D0F0xBC_xE010706B_ADDRESS                               0xe010706b
+
+// Type
+#define D0F0xBC_xE010706B_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010706B_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010706B_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010706B_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010706B_LClkDpmDid1_OFFSET                    7
+#define D0F0xBC_xE010706B_LClkDpmDid1_WIDTH                     7
+#define D0F0xBC_xE010706B_LClkDpmDid1_MASK                      0x3f80
+#define D0F0xBC_xE010706B_Reserved14_31_OFFSET                  14
+#define D0F0xBC_xE010706B_Reserved14_31_WIDTH                   18
+#define D0F0xBC_xE010706B_Reserved14_31_MASK                    0xffffc000
+
+/// D0F0xBC_xE010706B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                              LClkDpmDid1:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010706B_STRUCT;
+
+// **** D0F0xBC_xE010706C Field Definition ****
+// Address
+#define D0F0xBC_xE010706C_ADDRESS                               0xe010706c
+
+// Type
+#define D0F0xBC_xE010706C_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010706C_Reserved0_5_OFFSET                    0
+#define D0F0xBC_xE010706C_Reserved0_5_WIDTH                     6
+#define D0F0xBC_xE010706C_Reserved0_5_MASK                      0x3f
+#define D0F0xBC_xE010706C_LClkDpmDid2_OFFSET                    6
+#define D0F0xBC_xE010706C_LClkDpmDid2_WIDTH                     7
+#define D0F0xBC_xE010706C_LClkDpmDid2_MASK                      0x1fc0
+#define D0F0xBC_xE010706C_LClkDpmDid3_OFFSET                    13
+#define D0F0xBC_xE010706C_LClkDpmDid3_WIDTH                     7
+#define D0F0xBC_xE010706C_LClkDpmDid3_MASK                      0xfe000
+#define D0F0xBC_xE010706C_LClkDpmValid_OFFSET                   20
+#define D0F0xBC_xE010706C_LClkDpmValid_WIDTH                    4
+#define D0F0xBC_xE010706C_LClkDpmValid_MASK                     0xf00000
+#define D0F0xBC_xE010706C_DClkDid0_OFFSET                       24
+#define D0F0xBC_xE010706C_DClkDid0_WIDTH                        7
+#define D0F0xBC_xE010706C_DClkDid0_MASK                         0x7f000000
+#define D0F0xBC_xE010706C_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE010706C_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE010706C_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE010706C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_5:6 ; ///<
+    UINT32                                              LClkDpmDid2:7 ; ///<
+    UINT32                                              LClkDpmDid3:7 ; ///<
+    UINT32                                             LClkDpmValid:4 ; ///<
+    UINT32                                                 DClkDid0:7 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010706C_STRUCT;
+
+// **** D0F0xBC_xE010706F Field Definition ****
+// Address
+#define D0F0xBC_xE010706F_ADDRESS                               0xe010706f
+
+// Type
+#define D0F0xBC_xE010706F_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010706F_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE010706F_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE010706F_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE010706F_DClkDid1_OFFSET                       7
+#define D0F0xBC_xE010706F_DClkDid1_WIDTH                        7
+#define D0F0xBC_xE010706F_DClkDid1_MASK                         0x3f80
+#define D0F0xBC_xE010706F_Reserved14_31_OFFSET                  14
+#define D0F0xBC_xE010706F_Reserved14_31_WIDTH                   18
+#define D0F0xBC_xE010706F_Reserved14_31_MASK                    0xffffc000
+
+/// D0F0xBC_xE010706F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                                 DClkDid1:7 ; ///<
+    UINT32                                            Reserved14_31:18; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010706F_STRUCT;
+
+// **** D0F0xBC_xE0107070 Field Definition ****
+// Address
+#define D0F0xBC_xE0107070_ADDRESS                               0xe0107070
+
+// Type
+#define D0F0xBC_xE0107070_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107070_Reserved0_5_OFFSET                    0
+#define D0F0xBC_xE0107070_Reserved0_5_WIDTH                     6
+#define D0F0xBC_xE0107070_Reserved0_5_MASK                      0x3f
+#define D0F0xBC_xE0107070_DClkDid2_OFFSET                       6
+#define D0F0xBC_xE0107070_DClkDid2_WIDTH                        7
+#define D0F0xBC_xE0107070_DClkDid2_MASK                         0x1fc0
+#define D0F0xBC_xE0107070_DClkDid3_OFFSET                       13
+#define D0F0xBC_xE0107070_DClkDid3_WIDTH                        7
+#define D0F0xBC_xE0107070_DClkDid3_MASK                         0xfe000
+#define D0F0xBC_xE0107070_VClkDid0_OFFSET                       20
+#define D0F0xBC_xE0107070_VClkDid0_WIDTH                        7
+#define D0F0xBC_xE0107070_VClkDid0_MASK                         0x7f00000
+#define D0F0xBC_xE0107070_Reserved27_31_OFFSET                  27
+#define D0F0xBC_xE0107070_Reserved27_31_WIDTH                   5
+#define D0F0xBC_xE0107070_Reserved27_31_MASK                    0xf8000000
+
+/// D0F0xBC_xE0107070
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_5:6 ; ///<
+    UINT32                                                 DClkDid2:7 ; ///<
+    UINT32                                                 DClkDid3:7 ; ///<
+    UINT32                                                 VClkDid0:7 ; ///<
+    UINT32                                            Reserved27_31:5 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107070_STRUCT;
+
+// **** D0F0xBC_xE0107073 Field Definition ****
+// Address
+#define D0F0xBC_xE0107073_ADDRESS                               0xe0107073
+
+// Type
+#define D0F0xBC_xE0107073_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107073_Reserved0_2_OFFSET                    0
+#define D0F0xBC_xE0107073_Reserved0_2_WIDTH                     3
+#define D0F0xBC_xE0107073_Reserved0_2_MASK                      0x7
+#define D0F0xBC_xE0107073_VClkDid1_OFFSET                       3
+#define D0F0xBC_xE0107073_VClkDid1_WIDTH                        7
+#define D0F0xBC_xE0107073_VClkDid1_MASK                         0x3f8
+#define D0F0xBC_xE0107073_Reserved10_31_OFFSET                  10
+#define D0F0xBC_xE0107073_Reserved10_31_WIDTH                   22
+#define D0F0xBC_xE0107073_Reserved10_31_MASK                    0xfffffc00
+
+/// D0F0xBC_xE0107073
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_2:3 ; ///<
+    UINT32                                                 VClkDid1:7 ; ///<
+    UINT32                                            Reserved10_31:22; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107073_STRUCT;
+
+// **** D0F0xBC_xE0107074 Field Definition ****
+// Address
+#define D0F0xBC_xE0107074_ADDRESS                               0xe0107074
+
+// Type
+#define D0F0xBC_xE0107074_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107074_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE0107074_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE0107074_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE0107074_VClkDid2_OFFSET                       2
+#define D0F0xBC_xE0107074_VClkDid2_WIDTH                        7
+#define D0F0xBC_xE0107074_VClkDid2_MASK                         0x1fc
+#define D0F0xBC_xE0107074_VClkDid3_OFFSET                       9
+#define D0F0xBC_xE0107074_VClkDid3_WIDTH                        7
+#define D0F0xBC_xE0107074_VClkDid3_MASK                         0xfe00
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET         16
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH          5
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid0_MASK           0x1f0000
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET         21
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH          5
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid1_MASK           0x3e00000
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET         26
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH          5
+#define D0F0xBC_xE0107074_PowerplaySclkDpmValid2_MASK           0x7c000000
+#define D0F0xBC_xE0107074_Reserved31_31_OFFSET                  31
+#define D0F0xBC_xE0107074_Reserved31_31_WIDTH                   1
+#define D0F0xBC_xE0107074_Reserved31_31_MASK                    0x80000000
+
+/// D0F0xBC_xE0107074
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                                 VClkDid2:7 ; ///<
+    UINT32                                                 VClkDid3:7 ; ///<
+    UINT32                                   PowerplaySclkDpmValid0:5 ; ///<
+    UINT32                                   PowerplaySclkDpmValid1:5 ; ///<
+    UINT32                                   PowerplaySclkDpmValid2:5 ; ///<
+    UINT32                                            Reserved31_31:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107074_STRUCT;
+
+// **** D0F0xBC_xE0107077 Field Definition ****
+// Address
+#define D0F0xBC_xE0107077_ADDRESS                               0xe0107077
+
+// Type
+#define D0F0xBC_xE0107077_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107077_Reserved0_6_OFFSET                    0
+#define D0F0xBC_xE0107077_Reserved0_6_WIDTH                     7
+#define D0F0xBC_xE0107077_Reserved0_6_MASK                      0x7f
+#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET         7
+#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH          5
+#define D0F0xBC_xE0107077_PowerplaySclkDpmValid3_MASK           0xf80
+#define D0F0xBC_xE0107077_Reserved12_31_OFFSET                  12
+#define D0F0xBC_xE0107077_Reserved12_31_WIDTH                   20
+#define D0F0xBC_xE0107077_Reserved12_31_MASK                    0xfffff000
+
+/// D0F0xBC_xE0107077
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_6:7 ; ///<
+    UINT32                                   PowerplaySclkDpmValid3:5 ; ///<
+    UINT32                                            Reserved12_31:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107077_STRUCT;
+
+// **** D0F0xBC_xE0107078 Field Definition ****
+// Address
+#define D0F0xBC_xE0107078_ADDRESS                               0xe0107078
+
+// Type
+#define D0F0xBC_xE0107078_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE0107078_Reserved0_3_OFFSET                    0
+#define D0F0xBC_xE0107078_Reserved0_3_WIDTH                     4
+#define D0F0xBC_xE0107078_Reserved0_3_MASK                      0xf
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET         4
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH          5
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid4_MASK           0x1f0
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET         9
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH          5
+#define D0F0xBC_xE0107078_PowerplaySclkDpmValid5_MASK           0x3e00
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET          14
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel0_MASK            0xc000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET          16
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel1_MASK            0x30000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET          18
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel2_MASK            0xc0000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET          20
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel3_MASK            0x300000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET          22
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel4_MASK            0xc00000
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET          24
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH           2
+#define D0F0xBC_xE0107078_PowerplayPolicyLabel5_MASK            0x3000000
+#define D0F0xBC_xE0107078_Reserved26_31_OFFSET                  26
+#define D0F0xBC_xE0107078_Reserved26_31_WIDTH                   6
+#define D0F0xBC_xE0107078_Reserved26_31_MASK                    0xfc000000
+
+/// D0F0xBC_xE0107078
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_3:4 ; ///<
+    UINT32                                   PowerplaySclkDpmValid4:5 ; ///<
+    UINT32                                   PowerplaySclkDpmValid5:5 ; ///<
+    UINT32                                    PowerplayPolicyLabel0:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel1:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel2:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel3:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel4:2 ; ///<
+    UINT32                                    PowerplayPolicyLabel5:2 ; ///<
+    UINT32                                            Reserved26_31:6 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE0107078_STRUCT;
+
+// **** D0F0xBC_xE010707B Field Definition ****
+// Address
+#define D0F0xBC_xE010707B_ADDRESS                               0xe010707b
+
+// Type
+#define D0F0xBC_xE010707B_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010707B_Reserved0_1_OFFSET                    0
+#define D0F0xBC_xE010707B_Reserved0_1_WIDTH                     2
+#define D0F0xBC_xE010707B_Reserved0_1_MASK                      0x3
+#define D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET            2
+#define D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH             7
+#define D0F0xBC_xE010707B_PowerplayStateFlag0_MASK              0x1fc
+#define D0F0xBC_xE010707B_Reserved9_31_OFFSET                   9
+#define D0F0xBC_xE010707B_Reserved9_31_WIDTH                    23
+#define D0F0xBC_xE010707B_Reserved9_31_MASK                     0xfffffe00
+
+/// D0F0xBC_xE010707B
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_1:2 ; ///<
+    UINT32                                      PowerplayStateFlag0:7 ; ///<
+    UINT32                                             Reserved9_31:23; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010707B_STRUCT;
+
+// **** D0F0xBC_xE010707C Field Definition ****
+// Address
+#define D0F0xBC_xE010707C_ADDRESS                               0xe010707c
+
+// Type
+#define D0F0xBC_xE010707C_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010707C_Reserved0_0_OFFSET                    0
+#define D0F0xBC_xE010707C_Reserved0_0_WIDTH                     1
+#define D0F0xBC_xE010707C_Reserved0_0_MASK                      0x1
+#define D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET            1
+#define D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag1_MASK              0xfe
+#define D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET            8
+#define D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag2_MASK              0x7f00
+#define D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET            15
+#define D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag3_MASK              0x3f8000
+#define D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET            22
+#define D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH             7
+#define D0F0xBC_xE010707C_PowerplayStateFlag4_MASK              0x1fc00000
+#define D0F0xBC_xE010707C_Reserved29_31_OFFSET                  29
+#define D0F0xBC_xE010707C_Reserved29_31_WIDTH                   3
+#define D0F0xBC_xE010707C_Reserved29_31_MASK                    0xe0000000
+
+/// D0F0xBC_xE010707C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_0:1 ; ///<
+    UINT32                                      PowerplayStateFlag1:7 ; ///<
+    UINT32                                      PowerplayStateFlag2:7 ; ///<
+    UINT32                                      PowerplayStateFlag3:7 ; ///<
+    UINT32                                      PowerplayStateFlag4:7 ; ///<
+    UINT32                                            Reserved29_31:3 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010707C_STRUCT;
+
+// **** D0F0xBC_xE010707F Field Definition ****
+// Address
+#define D0F0xBC_xE010707F_ADDRESS                               0xe010707f
+
+// Type
+#define D0F0xBC_xE010707F_TYPE                                  TYPE_D0F0xBC
+#define D0F0xBC_xE010707F_Reserved0_4_OFFSET                    0
+#define D0F0xBC_xE010707F_Reserved0_4_WIDTH                     5
+#define D0F0xBC_xE010707F_Reserved0_4_MASK                      0x1f
+#define D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET            5
+#define D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH             7
+#define D0F0xBC_xE010707F_PowerplayStateFlag5_MASK              0xfe0
+#define D0F0xBC_xE010707F_Reserved12_31_OFFSET                  12
+#define D0F0xBC_xE010707F_Reserved12_31_WIDTH                   20
+#define D0F0xBC_xE010707F_Reserved12_31_MASK                    0xfffff000
+
+/// D0F0xBC_xE010707F
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              Reserved0_4:5 ; ///<
+    UINT32                                      PowerplayStateFlag5:7 ; ///<
+    UINT32                                            Reserved12_31:20; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010707F_STRUCT;
+
+// **** D0F0xBC_x1F630 Register Definition ****
+// Address
+#define D0F0xBC_x1F630_ADDRESS                                  0x1f630
+
+// Type
+#define D0F0xBC_x1F630_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F630_RECONF_WAIT_OFFSET                       0
+#define D0F0xBC_x1F630_RECONF_WAIT_WIDTH                        8
+#define D0F0xBC_x1F630_RECONF_WAIT_MASK                         0xff
+#define D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET                    8
+#define D0F0xBC_x1F630_RECONF_WRAPPER_WIDTH                     8
+#define D0F0xBC_x1F630_RECONF_WRAPPER_MASK                      0x00ff00
+
+/// D0F0xBC_x1F630
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              RECONF_WAIT:8;  ///<
+    UINT32                                           RECONF_WRAPPER:8;  ///<
+    UINT32                                                Reserved:16;  ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F630_STRUCT;
+
+// **** D0F0xE4_WRAP_8012 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8012_ADDRESS                               0x8012
+
+// Type
+#define D0F0xE4_WRAP_8012_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET           0
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH            6
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK             0x3f
+#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET                   6
+#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH                    1
+#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK                     0x40
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET            7
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK              0x80
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET         8
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK           0x3f00
+#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET         16
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH          6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK           0x3f0000
+#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET          23
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH           1
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK            0x800000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET       24
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH        6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK         0x3f000000
+#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8012
+typedef union {
+  struct {                                                              ///<
+    UINT32                                     Pif1xIdleGateLatency:6 ; ///<
+    UINT32                                             Reserved_6_6:1 ; ///<
+    UINT32                                      Pif1xIdleGateEnable:1 ; ///<
+    UINT32                                   Pif1xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                   Pif2p5xIdleGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                    Pif2p5xIdleGateEnable:1 ; ///<
+    UINT32                                 Pif2p5xIdleResumeLatency:6 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8012_STRUCT;
+
+// **** D0F0xE4_WRAP_8014 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8014_ADDRESS                               0x8014
+
+// Type
+#define D0F0xE4_WRAP_8014_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET            0
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK              0x1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET            1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK              0x2
+#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_OFFSET            2
+#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifA1xEnable_MASK              0x4
+#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_OFFSET            3
+#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifB1xEnable_MASK              0x8
+#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_OFFSET            4
+#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifC1xEnable_MASK              0x10
+#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_OFFSET            5
+#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_WIDTH             1
+#define D0F0xE4_WRAP_8014_DdiGatePifD1xEnable_MASK              0x20
+#define D0F0xE4_WRAP_8014_Reserved_7_6_OFFSET                   6
+#define D0F0xE4_WRAP_8014_Reserved_7_6_WIDTH                    2
+#define D0F0xE4_WRAP_8014_Reserved_7_6_MASK                     0xc0
+#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_OFFSET          8
+#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifA2p5xEnable_MASK            0x100
+#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_OFFSET          9
+#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifB2p5xEnable_MASK            0x200
+#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_OFFSET          10
+#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifC2p5xEnable_MASK            0x400
+#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_OFFSET          11
+#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_WIDTH           1
+#define D0F0xE4_WRAP_8014_DdiGatePifD2p5xEnable_MASK            0x800
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET           12
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK             0x1000
+#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_OFFSET           13
+#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifB1xEnable_MASK             0x2000
+#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_OFFSET           14
+#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifC1xEnable_MASK             0x4000
+#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_OFFSET           15
+#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_WIDTH            1
+#define D0F0xE4_WRAP_8014_PcieGatePifD1xEnable_MASK             0x8000
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET         16
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK           0x10000
+#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_OFFSET         17
+#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifB2p5xEnable_MASK           0x20000
+#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_OFFSET         18
+#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifC2p5xEnable_MASK           0x40000
+#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_OFFSET         19
+#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_WIDTH          1
+#define D0F0xE4_WRAP_8014_PcieGatePifD2p5xEnable_MASK           0x80000
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET  20
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH   1
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK    0x100000
+#define D0F0xE4_WRAP_8014_Reserved_23_21_OFFSET                 21
+#define D0F0xE4_WRAP_8014_Reserved_23_21_WIDTH                  3
+#define D0F0xE4_WRAP_8014_Reserved_23_21_MASK                   0xe00000
+#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_OFFSET              24
+#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigAEnable_MASK                0x1000000
+#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_OFFSET              25
+#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigBEnable_MASK                0x2000000
+#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_OFFSET              26
+#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigCEnable_MASK                0x4000000
+#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_OFFSET              27
+#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_WIDTH               1
+#define D0F0xE4_WRAP_8014_DdiGateDigDEnable_MASK                0x8000000
+#define D0F0xE4_WRAP_8014_SpareRegRw_OFFSET                     28
+#define D0F0xE4_WRAP_8014_SpareRegRw_WIDTH                      4
+#define D0F0xE4_WRAP_8014_SpareRegRw_MASK                       0xf0000000
+
+/// D0F0xE4_WRAP_8014
+typedef union {
+  struct {                                                              ///<
+    UINT32                                      TxclkPermGateEnable:1 ; ///<
+    UINT32                                      TxclkPrbsGateEnable:1 ; ///<
+    UINT32                                      DdiGatePifA1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifB1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifC1xEnable:1 ; ///<
+    UINT32                                      DdiGatePifD1xEnable:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                    DdiGatePifA2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifB2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifC2p5xEnable:1 ; ///<
+    UINT32                                    DdiGatePifD2p5xEnable:1 ; ///<
+    UINT32                                     PcieGatePifA1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifB1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifC1xEnable:1 ; ///<
+    UINT32                                     PcieGatePifD1xEnable:1 ; ///<
+    UINT32                                   PcieGatePifA2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifB2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifC2p5xEnable:1 ; ///<
+    UINT32                                   PcieGatePifD2p5xEnable:1 ; ///<
+    UINT32                            TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
+    UINT32                                           Reserved_23_21:3 ; ///<
+    UINT32                                        DdiGateDigAEnable:1 ; ///<
+    UINT32                                        DdiGateDigBEnable:1 ; ///<
+    UINT32                                        DdiGateDigCEnable:1 ; ///<
+    UINT32                                        DdiGateDigDEnable:1 ; ///<
+    UINT32                                               SpareRegRw:4 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8014_STRUCT;
+
+// **** D0F0xE4_WRAP_8015 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8015_ADDRESS                               0x8015
+
+// Type
+#define D0F0xE4_WRAP_8015_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET          16
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK            0x3f0000
+#define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET                 22
+#define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_22_22_MASK                   0x400000
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET           23
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK             0x800000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET          24
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH           6
+#define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK            0x3f000000
+#define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET                 30
+#define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH                  1
+#define D0F0xE4_WRAP_8015_Reserved_30_30_MASK                   0x40000000
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET           31
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH            1
+#define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK             0x80000000
+
+/// D0F0xE4_WRAP_8015
+typedef union {
+  struct {                                                              ///<
+    UINT32  /*                                      EnableD0StateReport*/:1 ; ///<
+    UINT32  /*                                             Reserved_1_1*/:1 ; ///<
+    UINT32  line477/*                               SlowRefclkThroughTxclk2p5x*/:1 ; ///<
+    UINT32  line478/*                                SlowRefclkEnableTxclk2p5x*/:1 ; ///<
+    UINT32  line479/*                                SlowRefclkDivideTxclk2p5x*/:2 ; ///<
+    UINT32  line480/*                                 SlowRefclkBurstTxclk2p5x*/:2 ; ///<
+    UINT32  /*                                             Reserved_8_8*/:1 ; ///<
+    UINT32  line482/*                                  SlowRefclkLcntGateForce*/:1 ; ///<
+    UINT32  line483/*                                 SlowRefclkThroughTxclk1x*/:1 ; ///<
+    UINT32  line484/*                                  SlowRefclkEnableTxclk1x*/:1 ; ///<
+    UINT32  line485/*                                  SlowRefclkDivideTxclk1x*/:2 ; ///<
+    UINT32  line486/*                                   SlowRefclkBurstTxclk1x*/:2 ; ///<
+    UINT32                                    RefclkRegsGateLatency:6 ; ///<
+    UINT32                                           Reserved_22_22:1 ; ///<
+    UINT32                                     RefclkRegsGateEnable:1 ; ///<
+    UINT32                                    RefclkBphyGateLatency:6 ; ///<
+    UINT32                                           Reserved_30_30:1 ; ///<
+    UINT32                                     RefclkBphyGateEnable:1 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8015_STRUCT;
+
+// **** PGFSM_Delay_Reg_0 Register Definition ****
+// Address
+
+// **** GMMx670 Register Definition ****
+// Address
+#define GMMx670_ADDRESS                                         0x670
+
+// Type
+#define GMMx670_TYPE                                            TYPE_GMM
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1071_0:1;
+    UINT32                                             Reserved_7_1:7 ; ///<
+    UINT32                                             TdpClampMode:8 ; ///<
+    UINT32            ex1071_3:8;
+    UINT32            ex1071_4:8;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1071_STRUCT;
+
+
+
+// **** GMMx600 Register Definition ****
+// Address
+#define GMMx600_ADDRESS                                         0x600
+
+// Type
+#define GMMx600_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx600_IndClkDiv_OFFSET                                0
+#define GMMx600_IndClkDiv_WIDTH                                 7
+#define GMMx600_IndClkDiv_MASK                                  0x7f
+#define GMMx600_Reserved_7_7_OFFSET                             7
+#define GMMx600_Reserved_7_7_WIDTH                              1
+#define GMMx600_Reserved_7_7_MASK                               0x80
+#define GMMx600_ClkDirCntlEn_OFFSET                             8
+#define GMMx600_ClkDirCntlEn_WIDTH                              1
+#define GMMx600_ClkDirCntlEn_MASK                               0x100
+#define GMMx600_ClkDirCntlTog_OFFSET                            9
+#define GMMx600_ClkDirCntlTog_WIDTH                             1
+#define GMMx600_ClkDirCntlTog_MASK                              0x200
+#define GMMx600_ClkDirCntlDiv_OFFSET                            10
+#define GMMx600_ClkDirCntlDiv_WIDTH                             7
+#define GMMx600_ClkDirCntlDiv_MASK                              0x1fc00
+#define GMMx600_Reserved_31_17_OFFSET                           17
+#define GMMx600_Reserved_31_17_WIDTH                            15
+#define GMMx600_Reserved_31_17_MASK                             0xfffe0000
+
+/// GMMx600
+typedef union {
+  struct {                                                              ///<
+    UINT32                                                IndClkDiv:7 ; ///<
+    UINT32                                             Reserved_7_7:1 ; ///<
+    UINT32                                             ClkDirCntlEn:1 ; ///<
+    UINT32                                            ClkDirCntlTog:1 ; ///<
+    UINT32                                            ClkDirCntlDiv:7 ; ///<
+    UINT32                                           Reserved_31_17:15; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx600_STRUCT;
+
+// **** GMMx604 Register Definition ****
+// Address
+#define GMMx604_ADDRESS                                         0x604
+
+// Type
+#define GMMx604_TYPE                                            TYPE_GMM
+// Field Data
+#define GMMx604_SclkStatus_OFFSET                               0
+#define GMMx604_SclkStatus_WIDTH                                1
+#define GMMx604_SclkStatus_MASK                                 0x1
+#define GMMx604_SclkForceStatus_OFFSET                          1
+#define GMMx604_SclkForceStatus_WIDTH                           1
+#define GMMx604_SclkForceStatus_MASK                            0x2
+#define GMMx604_SclkOverclkDetect_OFFSET                        2
+#define GMMx604_SclkOverclkDetect_WIDTH                         1
+#define GMMx604_SclkOverclkDetect_MASK                          0x4
+#define GMMx604_SclkDirCntlTogDone_OFFSET                       3
+#define GMMx604_SclkDirCntlTogDone_WIDTH                        1
+#define GMMx604_SclkDirCntlTogDone_MASK                         0x8
+#define GMMx604_Reserved_31_4_OFFSET                            4
+#define GMMx604_Reserved_31_4_WIDTH                             28
+#define GMMx604_Reserved_31_4_MASK                              0xfffffff0
+
+/// GMMx604
+typedef union {
+  struct {                                                              ///<
+    UINT64                                               SclkStatus:1 ; ///<
+    UINT64                                          SclkForceStatus:1 ; ///<
+    UINT64                                        SclkOverclkDetect:1 ; ///<
+    UINT64                                       SclkDirCntlTogDone:1 ; ///<
+    UINT64                                            Reserved_31_4:28; ///<
+  } Field;                                                              ///<
+  UINT64 Value;                                                         ///<
+} GMMx604_STRUCT;
+
+// **** GMMx5F50 Register Definition ****
+// Address
+#define GMMx5F50_ADDRESS                                        0x5F50
+
+// Type
+#define GMMx5F50_TYPE                                           TYPE_GMM
+// Field Data
+#define GMMx5F50_PortConnectivity_OFFSET                        0
+#define GMMx5F50_PortConnectivity_WIDTH                         3
+#define GMMx5F50_PortConnectivity_MASK                          0x7
+#define GMMx5F50_Reserved_3_3_OFFSET                            3
+#define GMMx5F50_Reserved_3_3_WIDTH                             1
+#define GMMx5F50_Reserved_3_3_MASK                              0x8
+#define GMMx5F50_PortConnectivityOverrideEnable_OFFSET          4
+#define GMMx5F50_PortConnectivityOverrideEnable_WIDTH           1
+#define GMMx5F50_PortConnectivityOverrideEnable_MASK            0x10
+#define GMMx5F50_Reserved_31_5_OFFSET                           5
+#define GMMx5F50_Reserved_31_5_WIDTH                            27
+#define GMMx5F50_Reserved_31_5_MASK                             0xffffffe0
+
+/// GMMx5F50
+typedef union {
+  struct {                                                              ///<
+    UINT32                                         PortConnectivity:3 ; ///<
+    UINT32                                             Reserved_3_3:1 ; ///<
+    UINT32                           PortConnectivityOverrideEnable:1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} GMMx5F50_STRUCT;
+
+// **** D0F0xE4_WRAP_8020 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8020_ADDRESS                               0x8020
+
+// Type
+#define D0F0xE4_WRAP_8020_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8020_Reserved_0_0_OFFSET                   0
+#define D0F0xE4_WRAP_8020_Reserved_0_0_WIDTH                    1
+#define D0F0xE4_WRAP_8020_Reserved_0_0_MASK                     0x1
+#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET               3
+#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_WIDTH                1
+#define D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK                 0x8
+#define D0F0xE4_WRAP_8020_Reserved_31_5_OFFSET                  5
+#define D0F0xE4_WRAP_8020_Reserved_31_5_WIDTH                   27
+#define D0F0xE4_WRAP_8020_Reserved_31_5_MASK                    0xffffffe0
+
+/// D0F0xE4_WRAP_8020
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_0_0:1 ; ///<
+    UINT32                                           :2 ; ///<
+    UINT32                                         PrbsPcieLbSelect:1 ; ///<
+    UINT32                                         :1 ; ///<
+    UINT32                                            Reserved_31_5:27; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8020_STRUCT;
+
+// **** D0F0xE4_WRAP_8025 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8025_ADDRESS                               0x8025
+
+// Type
+#define D0F0xE4_WRAP_8025_TYPE                                  TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET                    0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK                      0x7
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET                    3
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK                      0x18
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET                   5
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK                     0x20
+#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET                   6
+#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH                    2
+#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK                     0xc0
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET                    8
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK                      0x700
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET                    11
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK                      0x1800
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET                   13
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK                     0x2000
+#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET                 14
+#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK                   0xc000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET                    16
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK                      0x70000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET                    19
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK                      0x180000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET                   21
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK                     0x200000
+#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET                 22
+#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK                   0xc00000
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET                    24
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH                     3
+#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK                      0x7000000
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET                    27
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH                     2
+#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK                      0x18000000
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET                   29
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH                    1
+#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK                     0x20000000
+#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET                 30
+#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH                  2
+#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK                   0xc0000000
+
+/// D0F0xE4_WRAP_8025
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              LMTxPhyCmd0:3 ; ///<
+    UINT32                                              LMRxPhyCmd0:2 ; ///<
+    UINT32                                             LMLinkSpeed0:1 ; ///<
+    UINT32                                             Reserved_7_6:2 ; ///<
+    UINT32                                              LMTxPhyCmd1:3 ; ///<
+    UINT32                                              LMRxPhyCmd1:2 ; ///<
+    UINT32                                             LMLinkSpeed1:1 ; ///<
+    UINT32                                           Reserved_15_14:2 ; ///<
+    UINT32                                              LMTxPhyCmd2:3 ; ///<
+    UINT32                                              LMRxPhyCmd2:2 ; ///<
+    UINT32                                             LMLinkSpeed2:1 ; ///<
+    UINT32                                           Reserved_23_22:2 ; ///<
+    UINT32                                              LMTxPhyCmd3:3 ; ///<
+    UINT32                                              LMRxPhyCmd3:2 ; ///<
+    UINT32                                             LMLinkSpeed3:1 ; ///<
+    UINT32                                           Reserved_31_30:2 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xE4_WRAP_8025_STRUCT;
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1072_0:8;
+    UINT32                                               NumDropLsb:8 ; ///<
+    UINT32            ex1072_2:16;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1072_STRUCT;
+
+// **** D0F0xBC_x1F840 Register Definition ****
+// Address
+#define D0F0xBC_x1F840_ADDRESS                                  0x1f840
+
+// Type
+#define D0F0xBC_x1F840_TYPE                                     TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_x1F840_IddspikeOCP_OFFSET                               0
+#define D0F0xBC_x1F840_IddspikeOCP_WIDTH                                16
+#define D0F0xBC_x1F840_IddspikeOCP_MASK                                 0xffff
+#define D0F0xBC_x1F840_IddNbspikeOCP_OFFSET                             16
+#define D0F0xBC_x1F840_IddNbspikeOCP_WIDTH                              16
+#define D0F0xBC_x1F840_IddNbspikeOCP_MASK                               0xffff0000
+
+/// D0F0xBC_x1F840
+typedef union {
+  struct {                                                              ///<
+    UINT32                                              IddspikeOCP:16; ///<
+    UINT32                                            IddNbspikeOCP:16; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_x1F840_STRUCT;
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1073_0:32;
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1073_STRUCT;
+
+// **** D0F0xBC_xE010703C Register Definition ****
+// Address
+#define D0F0xBC_xE010703C_ADDRESS                               0xe010703c
+
+// Type
+#define D0F0xBC_xE010703C_TYPE                                  TYPE_D0F0xBC
+// Field Data
+#define D0F0xBC_xE010703C_Reserved_2_0_OFFSET                   0
+#define D0F0xBC_xE010703C_Reserved_2_0_WIDTH                    3
+#define D0F0xBC_xE010703C_Reserved_2_0_MASK                     0x7
+#define D0F0xBC_xE010703C_NbPstateHi_OFFSET                     3
+#define D0F0xBC_xE010703C_NbPstateHi_WIDTH                      2
+#define D0F0xBC_xE010703C_NbPstateHi_MASK                       0x18
+#define D0F0xBC_xE010703C_NbPstateLo_OFFSET                     5
+#define D0F0xBC_xE010703C_NbPstateLo_WIDTH                      2
+#define D0F0xBC_xE010703C_NbPstateLo_MASK                       0x60
+#define D0F0xBC_xE010703C_Reserved_31_7_OFFSET                  7
+#define D0F0xBC_xE010703C_Reserved_31_7_WIDTH                   25
+#define D0F0xBC_xE010703C_Reserved_31_7_MASK                    0xffffff80
+
+/// D0F0xBC_xE010703C
+typedef union {
+  struct {                                                              ///<
+    UINT32                                             Reserved_2_0:3 ; ///<
+    UINT32                                               NbPstateHi:2 ; ///<
+    UINT32                                               NbPstateLo:2 ; ///<
+    UINT32                                            Reserved_31_7:25; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} D0F0xBC_xE010703C_STRUCT;
+
+
+
+typedef union {
+  struct {                                                              ///<
+    UINT32            ex1075_0:11;
+    UINT32                                           Reserved_31_11:21 ; ///<
+  } Field;                                                              ///<
+  UINT32 Value;                                                         ///<
+} ex1075_STRUCT;
+
+
+
+// Address
+#define D0F0xBC_x1F480_ADDRESS                                  0x1f480
+
+// Type
+#define D0F0xBC_x1F480_TYPE                                     TYPE_D0F0xBC
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
new file mode 100644
index 0000000000..2fb8100c6d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEarly.c
@@ -0,0 +1,153 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB early init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "GeneralServices.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[];
+extern  OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval                          Initialization status.
+ */
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early before CPU
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval                          Initialization status.
+ */
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  AGESA_STATUS            Status;
+
+  // Only run code on BSP
+  if (IsBsp (&EarlyParamsPtr->StdHeader, &Status)) {
+    Status = GnbLibDispatchFeatures (&GnbEarlierFeatureTable[0], &EarlyParamsPtr->StdHeader);
+  }
+
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
new file mode 100644
index 0000000000..3b0366a39a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtEnv.c
@@ -0,0 +1,164 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB env init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATENV_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[];
+extern  BUILD_OPT_CFG UserOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT   GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbEnvConfigPtr     Pointer to gnb env configuration params.
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ */
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT   GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+  GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex;
+  GnbEnvConfigPtr->IommuSupport = UserOptions.CfgIommuSupport;
+  GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum;
+  GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate;
+  GnbEnvConfigPtr->LvdsPowerOnSeqDigonToDe = UserOptions.CfgLvdsPowerOnSeqDigonToDe;
+  GnbEnvConfigPtr->LvdsPowerOnSeqDeToVaryBl = UserOptions.CfgLvdsPowerOnSeqDeToVaryBl;
+  GnbEnvConfigPtr->LvdsPowerOnSeqDeToDigon = UserOptions.CfgLvdsPowerOnSeqDeToDigon;
+  GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToDe = UserOptions.CfgLvdsPowerOnSeqVaryBlToDe;
+  GnbEnvConfigPtr->LvdsPowerOnSeqOnToOffDelay = UserOptions.CfgLvdsPowerOnSeqOnToOffDelay;
+  GnbEnvConfigPtr->LvdsPowerOnSeqVaryBlToBlon = UserOptions.CfgLvdsPowerOnSeqVaryBlToBlon;
+  GnbEnvConfigPtr->LvdsPowerOnSeqBlonToVaryBl = UserOptions.CfgLvdsPowerOnSeqBlonToVaryBl;
+  GnbEnvConfigPtr->LvdsMaxPixelClockFreq = UserOptions.CfgLvdsMaxPixelClockFreq;
+  GnbEnvConfigPtr->LcdBitDepthControlValue = UserOptions.CfgLcdBitDepthControlValue;
+  GnbEnvConfigPtr->Lvds24bbpPanelMode = UserOptions.CfgLvds24bbpPanelMode;
+  GnbEnvConfigPtr->LvdsMiscControl.Value = 0;
+  GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value;
+  GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum;
+  GnbEnvConfigPtr->GnbRemoteDisplaySupport = UserOptions.CfgGnbRemoteDisplaySupport;
+  GnbEnvConfigPtr->LvdsMiscVoltAdjustment = UserOptions.CfgLvdsMiscVoltAdjustment;
+  GnbEnvConfigPtr->DisplayMiscControl.Value = UserOptions.CfgDisplayMiscControl.Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ * @retval                        Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
new file mode 100644
index 0000000000..0e1a7c3dc5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtLate.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB late init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern  OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in,out] LateParamsPtr    Pointer to late configuration params.
+ * @retval                         Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
new file mode 100644
index 0000000000..cae5ff726f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtMid.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB mid init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATMID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in,out] MidParamsPtr    Pointer to mid configuration params.
+ * @retval                        Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
new file mode 100644
index 0000000000..a0cf40b3b4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtPost.c
@@ -0,0 +1,176 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB POST init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "Ids.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern  OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[];
+extern  OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[];
+extern  BUILD_OPT_CFG             UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtPostDef (
+  IN OUT   GNB_POST_CONFIGURATION  *GnbPostConfigPtr,
+  IN       AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbPostConfigPtr     Pointer to GNB POST configuration params.
+ * @param[in] PostParamsPtr        Pointer to POST configuration params.
+ */
+VOID
+GnbInitDataStructAtPostDef (
+  IN OUT   GNB_POST_CONFIGURATION  *GnbPostConfigPtr,
+  IN       AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  GnbPostConfigPtr->IgpuEnableDisablePolicy = UserOptions.CfgIgpuEnableDisablePolicy;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr Pointer to post configuration parameters
+ * @retval                      Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  AGESA_STATUS          Status;
+  Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post after DRAM init
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr Pointer to post configuration parameters
+ * @retval                      Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  AGESA_STATUS          Status;
+  Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
new file mode 100644
index 0000000000..6949cb4162
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtReset.c
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB reset init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
new file mode 100644
index 0000000000..01bb2cef6a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/GnbInitAtS3Save.c
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB late init interface
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "OptionGnb.h"
+#include  "GnbLibFeatures.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_GNBINITATS3SAVE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern  OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[];
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS  *AmdS3SaveParams
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at S3 save
+ *
+ *
+ *
+ * @param[in,out] AmdS3SaveParams    Pointer to AMD_S3SAVE_PARAMS.
+ * @retval                         Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS  *AmdS3SaveParams
+  )
+{
+  AGESA_STATUS  Status;
+  Status = GnbLibDispatchFeatures (&GnbS3SaveFeatureTable[0], &AmdS3SaveParams->StdHeader);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h
new file mode 100644
index 0000000000..a212096f40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Include/Library/GnbTimerLib.h
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBTIMERLIB_H_
+#define _GNBTIMERLIB_H_
+
+VOID
+GnbLibStallS3Save (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+VOID
+GnbLibStall (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+UINT32
+GnbLibTimeStamp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
new file mode 100644
index 0000000000..c1f302376f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Library/GnbTimerLibWrap0/GnbTimerLibWrap0.c
@@ -0,0 +1,184 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various Timer services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbLib.h"
+#include  "GnbTimerLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_LIBRARY_GNBTIMERLIBWRAP0_GNBTIMERLIBWRAP0_FILECODE
+
+
+VOID
+GnbLibStallS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Stall and save to script table
+ *
+ *
+ *
+ * @param[in] Microsecond     Stall time
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibStallS3Save (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, GnbLibStallS3Script_ID, sizeof (Microsecond), &Microsecond);
+  GnbLibStall (Microsecond, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Stall
+ *
+ *
+ *
+ * @param[in] Microsecond     Stall time
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibStall (
+  IN      UINT32              Microsecond,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 TimeStampStart;
+  UINT32 TimeStampDelta;
+  UINT32 TimeStampCurrent;
+
+  TimeStampStart = GnbLibTimeStamp (StdHeader);
+  do {
+    TimeStampCurrent = GnbLibTimeStamp (StdHeader);
+    TimeStampDelta = ((TimeStampCurrent > TimeStampStart) ? (TimeStampCurrent - TimeStampStart) : (0xffffffffull - TimeStampStart + TimeStampCurrent));
+  } while (TimeStampDelta < Microsecond);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Stall S3 script
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        pointer to UINT32 number of us
+ */
+VOID
+GnbLibStallS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  )
+{
+  GnbLibStall (* ((UINT32*) Context), StdHeader);
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Time stamp in us
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a bridge
+ * @retval    FALSE           Device is not a bridge
+ */
+
+UINT32
+GnbLibTimeStamp (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32  TimeStamp;
+  GnbLibPciIndirectRead (
+    MAKE_SBDFO (0, 0, 0, 0, 0xE0),
+    0x13080F0,
+    AccessWidth32,
+    &TimeStamp,
+    StdHeader
+    );
+  return TimeStamp;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h
new file mode 100644
index 0000000000..82842b5d48
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBCOMMONLIB_H_
+#define _GNBCOMMONLIB_H_
+
+#include "GnbLib.h"
+#include "GnbLibCpuAcc.h"
+#include "GnbLibHeap.h"
+#include "GnbLibIoAcc.h"
+#include "GnbLibMemAcc.h"
+#include "GnbLibPci.h"
+#include "GnbLibPciAcc.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
new file mode 100644
index 0000000000..e79dfb7a60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -0,0 +1,548 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuServices.h"
+#include  "Gnb.h"
+#include  "GnbLib.h"
+#include  "GnbLibIoAcc.h"
+#include  "GnbLibPciAcc.h"
+#include  "GnbLibMemAcc.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_SERVICE  *ServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read GNB indirect registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width           Width
+ * @param[out] Value           Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectRead (
+  IN       UINT32       Address,
+  IN       UINT32       IndirectAddress,
+  IN       ACCESS_WIDTH Width,
+     OUT   VOID         *Value,
+  IN       VOID         *Config
+  )
+{
+  UINT32  IndexOffset;
+  IndexOffset = LibAmdAccessWidth (Width);
+  GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
+  GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read GNB indirect registers field
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] FieldOffset     Field offset
+ * @param[in] FieldWidth      Field width
+ * @param[out] Value          Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectReadField (
+  IN       UINT32       Address,
+  IN       UINT32       IndirectAddress,
+  IN       UINT8        FieldOffset,
+  IN       UINT8        FieldWidth,
+     OUT   UINT32       *Value,
+  IN       VOID         *Config
+  )
+{
+  UINT32  Mask;
+  GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config);
+  Mask = (1 << FieldWidth) - 1;
+  *Value = (*Value >> FieldOffset) & Mask;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GNB indirect registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width           Width
+ * @param[in] Value           Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+
+VOID
+GnbLibPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  IndexOffset;
+  IndexOffset = LibAmdAccessWidth (Width);
+  GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
+  GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GNB indirect registers field
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] FieldOffset     Field offset
+ * @param[in] FieldWidth      Field width
+ * @param[in] Value           Pointer to value
+ * @param[in] S3Save          Save for S3 (TRUE/FALSE)
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectWriteField (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT8         FieldOffset,
+  IN      UINT8         FieldWidth,
+  IN      UINT32        Value,
+  IN      BOOLEAN       S3Save,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  UINT32  Mask;
+  GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config);
+  Mask = (1 << FieldWidth) - 1;
+  Data &= (~(Mask << FieldOffset));
+  Data |= ((Value & Mask) << FieldOffset);
+  GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write GNB indirect registers field
+ *
+ *
+ *
+ * @param[in] Address         PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width           Width
+ * @param[in] Mask            And Mask
+ * @param[in] Value           Or Value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciIndirectRMW (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibPciIndirectRead (
+    Address,
+    IndirectAddress,
+    (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width,
+    &Data,
+    Config
+    );
+  Data = (Data & Mask) | Value;
+  GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCI registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address
+ * @param[in] Width           Access width
+ * @param[in] Mask            AND Mask
+ * @param[in] Value           OR Value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibPciRMW (
+  IN      UINT32        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibPciRead (Address, Width, &Data, Config);
+  Data = (Data & Mask) | Value;
+  GnbLibPciWrite (Address, Width, &Data, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write I/O registers
+ *
+ *
+ *
+ * @param[in] Address         I/O Port
+ * @param[in] Width           Access width
+ * @param[in] Mask            AND Mask
+ * @param[in] Value           OR Mask
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibIoRMW (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibIoRead (Address, Width, &Data, Config);
+  Data = (Data & Mask) | Value;
+  GnbLibIoWrite (Address, Width, &Data, Config);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Indirect IO block read
+ *
+ *
+ *
+ * @param[in] IndexPort       Index Port
+ * @param[in] DataPort        Data Port
+ * @param[in] Width           Access width
+ * @param[in] IndexAddress    Index Address
+ * @param[in] Count           Count
+ * @param[in] Buffer          Buffer
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibIndirectIoBlockRead (
+  IN      UINT16        IndexPort,
+  IN      UINT16        DataPort,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        IndexAddress,
+  IN      UINT32        Count,
+  IN      VOID          *Buffer,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Index;
+
+  for (Index = IndexAddress; Index < (IndexAddress + Count); Index++) {
+    GnbLibIoWrite (IndexPort, Width, &Index, Config);
+    GnbLibIoRead (DataPort, Width,  Buffer, Config);
+    Buffer = (VOID *) ((UINT8 *) Buffer + LibAmdAccessWidth (Width));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get IOAPIC ID
+ *
+ *
+ *
+ * @param[in] IoApicBaseAddress   IO APIC base address
+ * @param[in] Config              Pointer to standard header
+ */
+UINT8
+GnbLiGetIoapicId (
+  IN      UINT64        IoApicBaseAddress,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Value;
+  Value = 0x0;
+  GnbLibMemWrite (IoApicBaseAddress, AccessWidth32, &Value, Config);
+  GnbLibMemRead (IoApicBaseAddress + 0x10, AccessWidth32, &Value, Config);
+  return (UINT8) (Value >> 24);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write MMIO registers
+ *
+ *
+ *
+ * @param[in] Address         Physical address
+ * @param[in] Width           Access width
+ * @param[in] Mask            AND Mask
+ * @param[in] Value           OR Value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibMemRMW (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  Data;
+  GnbLibMemRead (Address, Width, &Data, Config);
+  Data = (Data & Mask) | Value;
+  GnbLibMemWrite (Address, Width, &Data, Config);
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Claculate power of number
+ *
+ *
+ *
+ * @param[in]   Value         Number
+ * @param[in]   Power         Power
+ */
+
+UINT32
+GnbLibPowerOf (
+  IN      UINT32  Value,
+  IN      UINT32  Power
+  )
+{
+  UINT32  Result;
+  if (Power == 0) {
+    return 1;
+  }
+  Result = Value;
+  while ((--Power) > 0) {
+    Result *= Value;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Search buffer for pattern
+ *
+ *
+ * @param[in]  Buf1           Pointer to source buffer which will be subject of search
+ * @param[in]  Buf1Length     Length of the source buffer
+ * @param[in]  Buf2           Pointer to pattern buffer
+ * @param[in]  Buf2Length     Length of the pattern buffer
+ * @retval     Pointer on first accurance of Buf2 in Buf1 or NULL
+ */
+
+VOID*
+GnbLibFind (
+  IN      UINT8               *Buf1,
+  IN      UINTN               Buf1Length,
+  IN      UINT8               *Buf2,
+  IN      UINTN               Buf2Length
+  )
+{
+  UINT8 *CurrentBuf1Ptr;
+  CurrentBuf1Ptr = Buf1;
+  while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
+    UINT8 *SourceBufPtr;
+    UINT8 *PatternBufPtr;
+    UINTN PatternBufLength;
+    SourceBufPtr = CurrentBuf1Ptr;
+    PatternBufPtr = Buf2;
+    PatternBufLength = Buf2Length;
+    while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
+    if (PatternBufLength == 0) {
+      return CurrentBuf1Ptr;
+    }
+    CurrentBuf1Ptr++;
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump buffer to HDTOUT
+ *
+ *
+ * @param[in]     Buffer          Buffer pointer
+ * @param[in]     Count           Count of data elements
+ * @param[in]     DataWidth       DataWidth 1 - Byte; 2 - Word; 3 - DWORD; 4 - QWORD
+ * @param[in]     LineWidth       Number of data item per line
+ */
+VOID
+GnbLibDebugDumpBuffer (
+  IN       VOID             *Buffer,
+  IN       UINT32           Count,
+  IN       UINT8            DataWidth,
+  IN       UINT8            LineWidth
+  )
+{
+  UINT32  Index;
+  UINT32  DataItemCount;
+  ASSERT (LineWidth != 0);
+  ASSERT (DataWidth >= 1 && DataWidth <= 4);
+  DataItemCount = 0;
+  for (Index = 0; Index < Count; ) {
+    switch (DataWidth) {
+    case 1:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%02x ", *((UINT8 *) Buffer + Index));
+      Index += 1;
+      break;
+    case 2:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%04x ", *(UINT16 *) ((UINT8 *) Buffer + Index));
+      Index += 2;
+      break;
+    case 3:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%08x ", *(UINT32 *) ((UINT8 *) Buffer + Index));
+      Index += 4;
+      break;
+    case 4:
+      IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4));
+      Index += 8;
+      break;
+    default:
+      IDS_HDT_CONSOLE (GNB_TRACE, "ERROR! Incorrect Data Width\n");
+      return;
+    }
+    if (++DataItemCount >= LineWidth) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "\n");
+      DataItemCount = 0;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump buffer to HDTOUT
+ *
+ *
+ * @param[in]     ServiceId       Service ID
+ * @param[in]     SocketId        Socket ID
+ * @param[in]     ServiceProtocol Service protocol
+ * @param[in]     StdHeader       Standard Configuration Header
+ */
+AGESA_STATUS
+GnbLibLocateService (
+  IN       GNB_SERVICE_ID       ServiceId,
+  IN       UINT8                SocketId,
+  IN       VOID                 **ServiceProtocol,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  GNB_SERVICE     *SeviceEntry;
+  CPU_LOGICAL_ID  LogicalId;
+  SeviceEntry = ServiceTable;
+  GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader);
+  while (SeviceEntry != NULL) {
+    if (SeviceEntry->ServiceId == ServiceId && (LogicalId.Family & SeviceEntry->Family) != 0) {
+      *ServiceProtocol = SeviceEntry->ServiceProtocol;
+      return AGESA_SUCCESS;
+    }
+    SeviceEntry = SeviceEntry->NextService;
+  }
+  return AGESA_UNSUPPORTED;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h
new file mode 100644
index 0000000000..ffbeba60af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h
@@ -0,0 +1,193 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB register access services.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBLIB_H_
+#define _GNBLIB_H_
+
+#define IOC_WRITE_ENABLE 0x80
+
+VOID
+GnbLibPciIndirectReadField (
+  IN       UINT32       Address,
+  IN       UINT32       IndirectAddress,
+  IN       UINT8        FieldOffset,
+  IN       UINT8        FieldWidth,
+     OUT   UINT32       *Value,
+  IN       VOID         *Config
+  );
+
+VOID
+GnbLibPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibPciIndirectRead (
+  IN       UINT32        Address,
+  IN       UINT32        IndirectAddress,
+  IN       ACCESS_WIDTH  Width,
+     OUT   VOID          *Value,
+  IN       VOID          *Config
+  );
+
+VOID
+GnbLibPciIndirectRMW (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibPciIndirectWriteField (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT8         FieldOffset,
+  IN      UINT8         FieldWidth,
+  IN      UINT32        Value,
+  IN      BOOLEAN       S3Save,
+  IN      VOID          *Config
+  );
+
+
+VOID
+GnbLibPciRMW (
+  IN      UINT32        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibIoRMW (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+
+UINT32
+GnbLibPowerOf (
+  IN      UINT32            Value,
+  IN      UINT32            Power
+  );
+
+VOID*
+GnbLibFind (
+  IN      UINT8             *Buf1,
+  IN      UINTN             Buf1Length,
+  IN      UINT8             *Buf2,
+  IN      UINTN             Buf2Length
+  );
+
+VOID
+GnbLibIndirectIoBlockRead (
+  IN      UINT16            IndexPort,
+  IN      UINT16            DataPort,
+  IN      ACCESS_WIDTH      Width,
+  IN      UINT32            IndexAddress,
+  IN      UINT32            Count,
+  IN      VOID              *Buffer,
+  IN      VOID              *Config
+  );
+
+UINT8
+GnbLiGetIoapicId (
+  IN      UINT64            IoApicBaseAddress,
+  IN      VOID              *Config
+  );
+
+VOID
+GnbLibDebugDumpBuffer (
+  IN       VOID             *Buffer,
+  IN       UINT32           Count,
+  IN       UINT8            DataWidth,
+  IN       UINT8            LineWidth
+  );
+
+AGESA_STATUS
+GnbLibLocateService (
+  IN       GNB_SERVICE_ID       ServiceId,
+  IN       UINT8                SocketId,
+  IN       VOID                 **ServiceProtocol,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
new file mode 100644
index 0000000000..39259f7e4d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
@@ -0,0 +1,157 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access various CPU registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "GnbLibCpuAcc.h"
+#include  "GnbLibPciAcc.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read CPU (DCT) indirect registers
+ *
+ *
+ *
+ * @param[in]  Address         PCI address of DCT register
+ * @param[in]  IndirectAddress Offset of DCT register
+ * @param[out] Value           Pointer to value
+ * @param[in]  Config          Pointer to standard header
+ */
+VOID
+GnbLibCpuPciIndirectRead (
+  IN       UINT32        Address,
+  IN       UINT32        IndirectAddress,
+     OUT   UINT32        *Value,
+  IN       VOID          *Config
+  )
+{
+  UINT32  OffsetRegisterValue;
+  GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config);
+  do {
+    GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
+  } while ((OffsetRegisterValue & BIT31) == 0);
+  GnbLibPciRead (Address + 4, AccessWidth32, Value, Config);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write CPU (DCT) indirect registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address of DCT register
+ * @param[in] IndirectAddress Offset of DCT register
+ * @param[in] Value           Pointer to value
+ * @param[in] Config          Pointer to standard header
+ */
+VOID
+GnbLibCpuPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT32        *Value,
+  IN      VOID          *Config
+  )
+{
+  UINT32  OffsetRegisterValue;
+  OffsetRegisterValue = IndirectAddress | BIT30;
+  GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config);
+  GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config);
+  do {
+    GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
+  } while ((OffsetRegisterValue & BIT31) == 0);
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h
new file mode 100644
index 0000000000..4eea7b8be1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access various CPU registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _CPUACCLIB_H_
+#define _CPUACCLIB_H_
+
+VOID
+GnbLibCpuPciIndirectWrite (
+  IN      UINT32        Address,
+  IN      UINT32        IndirectAddress,
+  IN      UINT32        *Value,
+  IN      VOID          *Config
+  );
+
+VOID
+GnbLibCpuPciIndirectRead (
+  IN       UINT32        Address,
+  IN       UINT32        IndirectAddress,
+     OUT   UINT32        *Value,
+  IN       VOID          *Config
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
new file mode 100644
index 0000000000..aa243de9ef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access heap.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "GnbLibPciAcc.h"
+#include  "GnbLibHeap.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      Length            Buffer length
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer allocation fail
+ *
+ */
+
+VOID *
+GnbAllocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = (UINT32) Length;
+  AllocHeapParams.BufferHandle = Handle;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return NULL;
+  }
+  return AllocHeapParams.BufferPtr;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Allocates space for a new buffer in the heap and clear it
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      Length            Buffer length
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer allocation fail
+ *
+ */
+
+VOID *
+GnbAllocateHeapBufferAndClear (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  VOID  *Buffer;
+  Buffer = GnbAllocateHeapBuffer (Handle, Length, StdHeader);
+  if (Buffer != NULL) {
+    LibAmdMemFill (Buffer, 0x00, Length, StdHeader);
+  }
+  return Buffer;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locates a previously allocated buffer on the heap.
+ *
+ *
+ * @param[in]      Handle            Buffer handle
+ * @param[in]      StdHeader         Standard configuration header
+ *
+ * @retval         NULL              Buffer handle not found
+ *
+ */
+
+VOID *
+GnbLocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  LOCATE_HEAP_PTR       LocHeapParams;
+  LocHeapParams.BufferHandle = Handle;
+  Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    return NULL;
+  }
+  return LocHeapParams.BufferPtr;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h
new file mode 100644
index 0000000000..61a618a900
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h
@@ -0,0 +1,96 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access heap.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBHEAPLIB_H_
+#define _GNBHEAPLIB_H_
+
+VOID *
+GnbAllocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+VOID *
+GnbLocateHeapBuffer (
+  IN      UINT32              Handle,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+VOID *
+GnbAllocateHeapBufferAndClear (
+  IN      UINT32              Handle,
+  IN      UINTN               Length,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
new file mode 100644
index 0000000000..b5341f87bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
@@ -0,0 +1,149 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+* Service procedure to access I/O registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "Porting.h"
+#include "AMD.h"
+#include "amdlib.h"
+#include "GnbLibIoAcc.h"
+#include "S3SaveState.h"
+#include "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+
+/*---------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write I/O Port
+ *
+ *
+ *
+ * @param[in] Address         Physical Address
+ * @param[in] Width           Access width
+ * @param[in] Value           Pointer to value
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibIoWrite (
+  IN       UINT16      Address,
+  IN       ACCESS_WIDTH Width,
+  IN       VOID         *Value,
+  IN       VOID         *StdHeader
+  )
+{
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value);
+  }
+  LibAmdIoWrite (Width, Address, Value, StdHeader);
+}
+/**
+ * Read IO port
+ *
+ *
+ *
+ * @param[in]   Address         Physical Address
+ * @param[in]   Width           Access width
+ * @param[out]  Value           Pointer to value
+ * @param[in]   StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibIoRead (
+  IN       UINT16       Address,
+  IN       ACCESS_WIDTH Width,
+     OUT   VOID         *Value,
+  IN       VOID         *StdHeader
+  )
+{
+  LibAmdIoRead (Width, Address, Value, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h
new file mode 100644
index 0000000000..0066fad004
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h
@@ -0,0 +1,93 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access I/O registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _IOACCLIB_H_
+#define _IOACCLIB_H_
+
+
+VOID
+GnbLibIoWrite (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+VOID
+GnbLibIoRead (
+  IN      UINT16        Address,
+  IN      ACCESS_WIDTH  Width,
+  OUT     VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
new file mode 100644
index 0000000000..affdb10218
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
@@ -0,0 +1,152 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access MMIO registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "amdlib.h"
+#include  "GnbLibMemAcc.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write Memory/MMIO registers
+ *
+ *
+ *
+ * @param[in] Address         Physical Address
+ * @param[in] Width           Access width
+ * @param[in] Value           Pointer to value
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibMemWrite (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *StdHeader
+  )
+{
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value);
+  }
+  LibAmdMemWrite (Width, Address, Value, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read Memory/MMIO registers
+ *
+ *
+ *
+ * @param[in]   Address         Physical Address
+ * @param[in]   Width           Access width
+ * @param[out]  Value           Pointer to value
+ * @param[in]   StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLibMemRead (
+  IN       UINT64       Address,
+  IN       ACCESS_WIDTH Width,
+     OUT   VOID         *Value,
+  IN       VOID         *StdHeader
+  )
+{
+  LibAmdMemRead (Width, Address, Value, StdHeader);
+}
+
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h
new file mode 100644
index 0000000000..e0179d2669
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access MMIO registers.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _MEMACCLIB_H_
+#define _MEMACCLIB_H_
+
+VOID
+GnbLibMemWrite (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+VOID
+GnbLibMemRead (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  OUT     VOID          *Value,
+  IN      VOID          *StdHeader
+  );
+
+VOID
+GnbLibMemRMW (
+  IN      UINT64        Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Value,
+  IN      VOID          *Config
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
new file mode 100644
index 0000000000..1353342a54
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
@@ -0,0 +1,430 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbLibPciAcc.h"
+#include  "GnbLibPci.h"
+#include  "GnbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device present
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is present
+ * @retval    FALSE           Device is not present
+ */
+
+BOOLEAN
+GnbLibPciIsDevicePresent (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32  DeviceId;
+  GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader);
+  if (DeviceId == 0xffffffff) {
+    return FALSE;
+  } else {
+    return TRUE;
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device is bridge
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a bridge
+ * @retval    FALSE           Device is not a bridge
+ */
+
+BOOLEAN
+GnbLibPciIsBridgeDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   Header;
+  GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader);
+  if ((Header & 0x7f) == 1) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device is multifunction
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a multifunction device.
+ * @retval    FALSE           Device is a single function device.
+ *
+ */
+BOOLEAN
+GnbLibPciIsMultiFunctionDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8   Header;
+  GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader);
+  if ((Header & 0x80) != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if device is PCIe device
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Device is a PCIe device
+ * @retval    FALSE           Device is not a PCIe device
+ *
+ */
+
+BOOLEAN
+GnbLibPciIsPcieDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  if (GnbLibFindPciCapability (Address, PCIE_CAP_ID, StdHeader) != 0 ) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Find PCI capability pointer
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as described in PCI_ADDR)
+ * @param[in] CapabilityId    PCI capability ID
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Register address of capability pointer
+ *
+ */
+
+UINT8
+GnbLibFindPciCapability (
+  IN      UINT32              Address,
+  IN      UINT8               CapabilityId,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8     CapabilityPtr;
+  UINT8     CurrentCapabilityId;
+  CapabilityPtr = 0x34;
+  if (!GnbLibPciIsDevicePresent (Address, StdHeader)) {
+    return  0;
+  }
+  while (CapabilityPtr != 0) {
+    GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader);
+    if (CapabilityPtr != 0) {
+      GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader);
+      if (CurrentCapabilityId == CapabilityId) {
+        break;
+      }
+      CapabilityPtr++;
+    }
+  }
+  return  CapabilityPtr;
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Find PCIe extended capability pointer
+ *
+ *
+ *
+ * @param[in] Address               PCI address (as described in PCI_ADDR)
+ * @param[in] ExtendedCapabilityId  Extended PCIe capability ID
+ * @param[in] StdHeader             Standard configuration header
+ * @retval                          Register address of extended capability pointer
+ *
+ */
+
+#if 0 /* Not used */
+UINT16
+GnbLibFindPcieExtendedCapability (
+  IN      UINT32              Address,
+  IN      UINT16              ExtendedCapabilityId,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16  CapabilityPtr;
+  UINT32  ExtendedCapabilityIdBlock;
+  if (GnbLibPciIsPcieDevice (Address, StdHeader)) {
+    GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
+    if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) {
+      do {
+        CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff);
+        if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) {
+          return  CapabilityPtr;
+        }
+        GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
+      } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) !=  0);
+    }
+  }
+  return  0;
+}
+#endif
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Scan range of device on PCI bus.
+ *
+ *
+ *
+ * @param[in] Start           Start address to start scan from
+ * @param[in] End             End address of scan
+ * @param[in] ScanData        Supporting data
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+GnbLibPciScan (
+  IN      PCI_ADDR            Start,
+  IN      PCI_ADDR            End,
+  IN      GNB_PCI_SCAN_DATA   *ScanData
+  )
+{
+  UINTN       Bus;
+  UINTN       Device;
+  UINTN       LastDevice;
+  UINTN       Function;
+  UINTN       LastFunction;
+  PCI_ADDR    PciDevice;
+  SCAN_STATUS Status;
+
+  for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) {
+    Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00;
+    LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F;
+    for ( ; Device <= LastDevice; Device++) {
+      if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) {
+        Function = Start.Address.Function;
+      } else {
+        Function = 0x0;
+      }
+      PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0);
+      if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) {
+        continue;
+      }
+      if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) {
+        if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) {
+          LastFunction = Start.Address.Function;
+        } else {
+          LastFunction = 0x7;
+        }
+      } else {
+        LastFunction = 0x0;
+      }
+      for ( ; Function <= LastFunction; Function++) {
+        PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0);
+        if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) {
+          Status = ScanData->GnbScanCallback (PciDevice, ScanData);
+          if ((Status & SCAN_SKIP_FUNCTIONS) != 0) {
+            Function = LastFunction + 1;
+          }
+          if ((Status & SCAN_SKIP_DEVICES) != 0) {
+            Device = LastDevice + 1;
+          }
+          if ((Status & SCAN_SKIP_BUSES) != 0) {
+            Bus = End.Address.Bus + 1;
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Scan all subordinate buses
+ *
+ *
+ * @param[in]   Bridge            PCI bridge address
+ * @param[in,out] ScanData        Scan configuration data
+ *
+ */
+VOID
+GnbLibPciScanSecondaryBus (
+  IN       PCI_ADDR             Bridge,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  PCI_ADDR  StartRange;
+  PCI_ADDR  EndRange;
+  UINT8     SecondaryBus;
+  GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader);
+  if (SecondaryBus != 0) {
+    StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
+    EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0);
+    GnbLibPciScan (StartRange, EndRange, ScanData);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCIe device type
+ *
+ *
+ *
+ * @param[in] Device      PCI address of device.
+ * @param[in] StdHeader  Northbridge configuration structure pointer.
+ *
+ * @retval    PCIE_DEVICE_TYPE
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+PCIE_DEVICE_TYPE
+GnbLibGetPcieDeviceType (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8       PcieCapPtr;
+  UINT8       Value;
+
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader);
+    return Value >> 4;
+  }
+  return PcieNotPcieDevice;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Save config space area
+ *
+ *
+ *
+ * @param[in] Address                 PCI address of device.
+ * @param[in] StartRegisterAddress    Start register address.
+ * @param[in] EndRegisterAddress      End register address.
+ * @param[in] Width                   Acess width.
+ * @param[in] StdHeader               Standard header.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+VOID
+GnbLibS3SaveConfigSpace (
+  IN      UINT32              Address,
+  IN      UINT16              StartRegisterAddress,
+  IN      UINT16              EndRegisterAddress,
+  IN      ACCESS_WIDTH        Width,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16    Index;
+  UINT16    Delta;
+  UINT16    Length;
+  Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress);
+  Delta = LibAmdAccessWidth (Width);
+  for (Index = 0; Index <= Length; Index = Index + Delta) {
+    GnbLibPciRMW (
+      Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)),
+      Width,
+      0xffffffff,
+      0x0,
+      StdHeader
+      );
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h
new file mode 100644
index 0000000000..a0825cfa12
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h
@@ -0,0 +1,186 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various PCI service routines.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBLIBPCI_H_
+#define _GNBLIBPCI_H_
+
+#define PCIE_CAP_ID                 0x10
+#define IOMMU_CAP_ID                0x0F
+
+/// PCIe device type
+typedef enum {
+  PcieDeviceEndPoint,                       ///< Endpoint
+  PcieDeviceLegacyEndPoint,                 ///< Legacy endpoint
+  PcieDeviceRootComplex = 4,                ///< Root complex
+  PcieDeviceUpstreamPort,                   ///< Upstream port
+  PcieDeviceDownstreamPort,                 ///< Downstream Port
+  PcieDevicePcieToPcix,                     ///< PCIe to PCI/PCIx bridge
+  PcieDevicePcixToPcie,                     ///< PCI/PCIx to PCIe bridge
+  PcieNotPcieDevice = 0xff                  ///< unknown device
+} PCIE_DEVICE_TYPE;
+
+typedef  UINT32 SCAN_STATUS;
+
+#define SCAN_SKIP_FUNCTIONS         0x1
+#define SCAN_SKIP_DEVICES           0x2
+#define SCAN_SKIP_BUSES             0x4
+#define SCAN_SUCCESS                0x0
+
+//  Forward declaration needed for multi-structure mutual references
+AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA);
+
+typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+///Scan supporting data
+struct _GNB_PCI_SCAN_DATA {
+  GNB_SCAN_CALLBACK     GnbScanCallback;  ///< Callback for each found device
+  AMD_CONFIG_PARAMS     *StdHeader;       ///< Standard configuration header
+};
+
+#define   PCIE_CAP_ID               0x10
+#define   PCIE_LINK_CAP_REGISTER    0x0C
+#define   PCIE_LINK_CTRL_REGISTER   0x10
+#define   PCIE_DEVICE_CAP_REGISTER  0x04
+#define   PCIE_DEVICE_CTRL_REGISTER 0x08
+#define   PCIE_ASPM_L1_SUPPORT_CAP  BIT11
+
+#define MAX_PAYLOAD_128             0x0     ///< Max allowed payload size 128 bytes
+#define MAX_PAYLOAD_256             0x1     ///< Max allowed payload size 256 bytes
+#define MAX_PAYLOAD_512             0x2     ///< Max allowed payload size 512 bytes
+#define MAX_PAYLOAD_1024            0x3     ///< Max allowed payload size 1024 bytes
+#define MAX_PAYLOAD_2048            0x4     ///< Max allowed payload size 2048 bytes
+#define MAX_PAYLOAD_4096            0x5     ///< Max allowed payload size 4096 bytes
+#define MAX_PAYLOAD                 0x5     ///< Max allowed payload size according to spec is 101b (4096 bytes)
+
+BOOLEAN
+GnbLibPciIsDevicePresent (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+BOOLEAN
+GnbLibPciIsBridgeDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+BOOLEAN
+GnbLibPciIsMultiFunctionDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+BOOLEAN
+GnbLibPciIsPcieDevice (
+  IN      UINT32              Address,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+ );
+
+UINT8
+GnbLibFindPciCapability (
+  IN      UINT32              Address,
+  IN      UINT8               CapabilityId,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLibPciScan (
+  IN      PCI_ADDR            Start,
+  IN      PCI_ADDR            End,
+  IN      GNB_PCI_SCAN_DATA   *ScanData
+ );
+
+VOID
+GnbLibPciScanSecondaryBus (
+  IN       PCI_ADDR             Bridge,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+PCIE_DEVICE_TYPE
+GnbLibGetPcieDeviceType (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLibS3SaveConfigSpace (
+  IN      UINT32              Address,
+  IN      UINT16              StartRegisterAddress,
+  IN      UINT16              EndRegisterAddress,
+  IN      ACCESS_WIDTH        Width,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
new file mode 100644
index 0000000000..ccb2078120
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
@@ -0,0 +1,183 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "Porting.h"
+#include  "AMD.h"
+#include  "amdlib.h"
+#include  "GnbLibPciAcc.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCI registers
+ *
+ *
+ *
+ * @param[in] Address         PCI address (as presented in PCI_ADDR.AddressValue)
+ * @param[in] Width           Access width
+ * @param[in] Value           Pointer to value
+ * @param[in] StdHeader       Pointer to standard header
+ */
+VOID
+GnbLibPciWrite (
+  IN      UINT32              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      VOID                *Value,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  PciAddress.AddressValue = Address;
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value);
+  }
+  LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCI registers
+ *
+ *
+ *
+ * @param[in]   Address         PCI address (as presented in PCI_ADDR.AddressValue)
+ * @param[in]   Width           Access width
+ * @param[out]  Value           Pointer to value
+ * @param[in]   StdHeader       Pointer to standard header
+ */
+
+VOID
+GnbLibPciRead (
+  IN       UINT32             Address,
+  IN       ACCESS_WIDTH       Width,
+     OUT   VOID               *Value,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  PciAddress.AddressValue = Address;
+  LibAmdPciRead (Width, PciAddress, Value, StdHeader);
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll PCI reg
+ *
+ *
+ *
+ * @param[in] Address       PCI address (as presented in PCI_ADDR.AddressValue)
+ * @param[in] Width         Access width
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      AND mask
+ * @param[in] StdHeader     Standard configuration header
+ */
+
+VOID
+GnbLibPciPoll (
+  IN      UINT32             Address,
+  IN      ACCESS_WIDTH       Width,
+  IN      VOID               *Data,
+  IN      VOID               *DataMask,
+  IN      AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  PciAddress.AddressValue = Address;
+  if (Width >= AccessS3SaveWidth8) {
+    S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff);
+  }
+  LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h
new file mode 100644
index 0000000000..a921bf13bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBLIBPCIACC_H_
+#define _GNBLIBPCIACC_H_
+
+VOID
+GnbLibPciWrite (
+  IN      UINT32              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      VOID                *Value,
+  IN      AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+GnbLibPciRead (
+  IN       UINT32             Address,
+  IN       ACCESS_WIDTH       Width,
+     OUT   VOID               *Value,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+VOID
+GnbLibPciPoll (
+  IN      UINT32             Address,
+  IN      ACCESS_WIDTH       Width,
+  IN      VOID               *Data,
+  IN      VOID               *DataMask,
+  IN      AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
new file mode 100644
index 0000000000..d6936d4f24
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c
@@ -0,0 +1,542 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific function translation
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   No more configuration available for given engine type
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+AGESA_STATUS
+PcieFmConfigureEnginesLaneAllocation (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId);
+  }
+  return  AGESA_ERROR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration value
+ *
+ *
+ *
+ * @param[in]  Wrapper                Pointer to internal configuration data area
+ * @param[in]  CoreId                 Core ID
+ * @param[in]  ConfigurationSignature Configuration signature
+ * @param[out] ConfigurationValue     Configuration value (for core configuration)
+ * @retval     AGESA_SUCCESS          Configuration successfully applied
+ * @retval     AGESA_ERROR            Core configuration value can not be determined
+ */
+AGESA_STATUS
+PcieFmGetCoreConfigurationValue (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_INIT_SERVICES    *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature,  ConfigurationValue);
+  }
+  return  AGESA_ERROR;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if engine can be remapped to Device/function number requested by user
+ * defined engine descriptor
+ *
+ *   Function only called if requested device/function does not much native device/function
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieFmCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
+  }
+  return FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration string
+ *
+ *   Debug function for logging configuration
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @param[in] ConfigurationValue   Configuration value
+ * @retval                         Configuration string
+ */
+
+CONST CHAR8*
+PcieFmDebugGetCoreConfigurationString (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_DEBUG_SERVICES   *PcieDebugService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId,  (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue);
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get wrapper name
+ *
+ *  Debug function for logging wrapper name
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @retval                         Wrapper Name string
+ */
+
+CONST CHAR8*
+PcieFmDebugGetWrapperNameString (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_DEBUG_SERVICES   *PcieDebugService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId,  (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper);
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get register address name
+ *
+ *  Debug function for logging register trace
+ *
+ * @param[in] Silicon              Silicon config descriptor
+ * @param[in] AddressFrame         Address Frame
+ * @retval                         Register address name
+ */
+CONST CHAR8*
+PcieFmDebugGetHostRegAddressSpaceString (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_DEBUG_SERVICES   *PcieDebugService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId,  (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame);
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if the lane can be muxed by link width requested by user
+ * defined engine descriptor
+ *
+ *    Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
+ *    Check Engine StartCoreLane could be aligned by user requested link width x2.
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Lane can be muxed
+ * @retval     FALSE               Lane can NOT be muxed
+ */
+
+BOOLEAN
+PcieFmCheckPortPcieLaneCanBeMuxed (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId,  (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine);
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Map engine to specific PCI device address
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @retval     AGESA_ERROR         Fail to map PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address
+ */
+
+AGESA_STATUS
+PcieFmMapPortPciAddress (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_COMPLEX_CONFIG       *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmMapPortPciAddress (Engine);
+  }
+  return  AGESA_ERROR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get total number of silicons/wrappers/engines for this complex
+ *
+ *
+ *
+ * @param[in]  SocketId              Socket ID.
+ * @param[out] Length                Length of configuration info block
+ * @param[out] StdHeader             Standard Configuration Header
+ * @retval     AGESA_SUCCESS         Configuration data length is correct
+ */
+AGESA_STATUS
+PcieFmGetComplexDataLength (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId,  (VOID **)&PcieConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader);
+  }
+  return Status;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build configuration
+ *
+ *
+ * @param[in]  SocketId         Socket ID.
+ * @param[out] Buffer           Pointer to buffer to build internal complex data structure
+ * @param[out] StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieFmBuildComplexConfiguration (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId,  (VOID **)&PcieConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max link speed capability supported by this port
+ *
+ *
+ *
+ * @param[in]  Flags              See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
+ * @param[in]  Engine             Pointer to engine config descriptor
+ * @retval     PcieGen1/PcieGen2  Max supported link gen capability
+ */
+PCIE_LINK_SPEED_CAP
+PcieFmGetLinkSpeedCap (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  PCIe_COMPLEX_CONFIG     *Complex;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PCIe_FAM_INIT_SERVICES  *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine);
+  }
+  return PcieGen1;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Get native PHY lane bitmap
+ *
+ *
+ * @param[in]  PhyLaneBitmap  Package PHY lane bitmap
+ * @param[in]  Engine         Standard configuration header.
+ * @retval     Native PHY lane bitmap
+ */
+UINT32
+PcieFmGetNativePhyLaneBitmap (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  PCIe_COMPLEX_CONFIG     *Complex;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  PCIe_FAM_INIT_SERVICES  *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine);
+  }
+  return 0x0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieFmSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP            LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  )
+{
+  AGESA_STATUS            Status;
+  PCIe_COMPLEX_CONFIG     *Complex;
+  PCIe_FAM_INIT_SERVICES  *PcieInitService;
+
+  Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header);
+  Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie));
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SB port info
+ *
+ *
+ * @param[out] SocketId         Socket ID
+ * @param[out] SbPort           Pointer to SB configuration descriptor
+ * @param[in]  StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    SB configuration determined successfully
+ */
+AGESA_STATUS
+PcieFmGetSbConfigInfo (
+  IN       UINT8                        SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR         *SbPort,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_FAM_CONFIG_SERVICES  *PcieConfigService;
+  Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader);
+  }
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
new file mode 100644
index 0000000000..2ac05a2c60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c
@@ -0,0 +1,157 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific function translation
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU unit present and enabled
+ *
+ *
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+BOOLEAN
+GnbFmCheckIommuPresent (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_FAM_IOMMU_SERVICES    *GnbIommuConfigService;
+  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader);
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbFmCreateIvrsEntry (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_FAM_IOMMU_SERVICES    *GnbIommuConfigService;
+  Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader);
+  }
+  return Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
new file mode 100644
index 0000000000..e142ac7d0d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxConfigLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxConfigEnvInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update GFX config info at ENV
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxConfigEnvInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  AMD_ENV_PARAMS        *EnvParamsPtr;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
+    Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex;
+    Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum;
+    Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate;
+    Gfx->LvdsPowerOnSeqDigonToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDigonToDe;
+    Gfx->LvdsPowerOnSeqDeToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToVaryBl;
+    Gfx->LvdsPowerOnSeqDeToDigon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqDeToDigon;
+    Gfx->LvdsPowerOnSeqVaryBlToDe = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToDe;
+    Gfx->LvdsPowerOnSeqOnToOffDelay = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqOnToOffDelay;
+    Gfx->LvdsPowerOnSeqVaryBlToBlon = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqVaryBlToBlon;
+    Gfx->LvdsPowerOnSeqBlonToVaryBl = EnvParamsPtr->GnbEnvConfiguration.LvdsPowerOnSeqBlonToVaryBl;
+    Gfx->LvdsMaxPixelClockFreq = EnvParamsPtr->GnbEnvConfiguration.LvdsMaxPixelClockFreq;
+    Gfx->LcdBitDepthControlValue = EnvParamsPtr->GnbEnvConfiguration.LcdBitDepthControlValue;
+    Gfx->Lvds24bbpPanelMode = EnvParamsPtr->GnbEnvConfiguration.Lvds24bbpPanelMode;
+    Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value;
+    Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum;
+    Gfx->GnbRemoteDisplaySupport = EnvParamsPtr->GnbEnvConfiguration.GnbRemoteDisplaySupport;
+    Gfx->gfxplmcfg0  = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscVoltAdjustment;
+    Gfx->DisplayMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.DisplayMiscControl.Value;
+    GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader);
+  }
+  GNB_DEBUG_CODE (
+    GfxConfigDebugDump (Gfx);
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
new file mode 100644
index 0000000000..cdf477166c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -0,0 +1,259 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GfxConfigLib.h"
+#include  "GnbCommonLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable GMM Access
+ *
+ *
+ *
+ * @param[in,out]   Gfx            Pointer to GFX configuration
+ * @retval          AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxEnableGmmAccess (
+  IN OUT   GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32      Value;
+
+  if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+
+  // Check if base address for GMM allocated
+  GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx));
+  if (Gfx->GmmBase == 0) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+  // Check if base address for FB allocated
+  GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
+  if ((Value & 0xfffffff0) == 0) {
+    IDS_ERROR_TRAP;
+    return AGESA_ERROR;
+  }
+  //Push CPU MMIO pci config to S3 script
+  GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+  // Turn on memory decoding on APC to enable access to GMM register space
+  if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
+    GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
+    //Push APC pci config to S3 script
+    GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+    GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
+  }
+  // Turn on memory decoding on GFX to enable access to GMM register space
+  GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
+  //Push iGPU pci config to S3 script
+  GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
+  GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get UMA info
+ *
+ * UMA info stored on heap by memory module
+ *
+ * @param[out] UmaInfo      Pointer to UMA info structure
+ * @param[in]  StdHeader    Standard configuration header
+ */
+
+VOID
+GfxGetUmaInfo (
+     OUT   UMA_INFO          *UmaInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UMA_INFO *MemUmaInfo;
+
+  MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader);
+  if (MemUmaInfo == NULL) {
+    LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader);
+    UmaInfo->UmaMode = UMA_NONE;
+  } else {
+    LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader);
+    if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) {
+      UmaInfo->UmaMode = UMA_NONE;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate UMA configuration data
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @param[in,out] Gfx           Pointer to GFX configuration
+ * @retval        AGESA_STATUS  Data located
+ * @retval        AGESA_FATA    Data not found
+ */
+
+AGESA_STATUS
+GfxLocateConfigData (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   GFX_PLATFORM_CONFIG   **Gfx
+  )
+{
+  *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader);
+  if (*Gfx == NULL) {
+    IDS_ERROR_TRAP;
+    return  AGESA_FATAL;
+  }
+  (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Debug dump
+ *
+ *
+ *
+ * @param[in]     Gfx           Pointer to GFX configuration
+ */
+
+VOID
+GfxConfigDebugDump (
+  IN       GFX_PLATFORM_CONFIG      *Gfx
+  )
+{
+  IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n");
+  IDS_HDT_CONSOLE (GFX_MISC, "  HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled");
+  IDS_HDT_CONSOLE (GFX_MISC, "  DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate);
+  IDS_HDT_CONSOLE (GFX_MISC, "  LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl);
+  IDS_HDT_CONSOLE (GFX_MISC, "  AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled");
+  IDS_HDT_CONSOLE (GFX_MISC, "  GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled");
+  IDS_HDT_CONSOLE (GFX_MISC, "  GmcPowerGating - %s\n",
+    (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : (
+    (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : (
+    (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown"))
+  );
+  IDS_HDT_CONSOLE (GFX_MISC, "  UmaSteering - %s\n",
+    (Gfx->UmaSteering == excel993 ) ? "excel993" : (
+    (Gfx->UmaSteering == excel992 ) ? "excel992" : "Unknown")
+    );
+  IDS_HDT_CONSOLE (GFX_MISC, "  iGpuVgaMode - %s\n",
+    (Gfx->iGpuVgaMode == iGpuVgaAdapter) ? "VGA" : (
+    (Gfx->iGpuVgaMode == iGpuVgaNonAdapter) ? "Non VGA" : "Unknown")
+    );
+  IDS_HDT_CONSOLE (GFX_MISC, "  UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA");
+  if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase);
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize);
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes);
+  }
+  IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n");
+
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h
new file mode 100644
index 0000000000..0c0aef794c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.h
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GFXCONFIGLIB_H_
+#define _GFXCONFIGLIB_H_
+
+VOID
+GfxConfigDebugDump (
+  IN       GFX_PLATFORM_CONFIG      *Gfx
+  );
+
+VOID
+GfxGetUmaInfo (
+     OUT   UMA_INFO          *UmaInfo,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GfxLocateConfigData (
+  IN       AMD_CONFIG_PARAMS     *StdHeader,
+     OUT   GFX_PLATFORM_CONFIG   **Gfx
+  );
+
+AGESA_STATUS
+GfxEnableGmmAccess (
+  IN OUT  GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
new file mode 100644
index 0000000000..f2323aa754
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c
@@ -0,0 +1,140 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GfxConfigLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxConfigMidInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update GFX config info at ENV
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxConfigMidInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  AMD_MID_PARAMS        *MidParamsPtr;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
+    Gfx->iGpuVgaMode = MidParamsPtr->GnbMidConfiguration.iGpuVgaMode;
+  }
+  GNB_DEBUG_CODE (
+    GfxConfigDebugDump (Gfx);
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigMidInterface Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
new file mode 100644
index 0000000000..04efa71a53
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
@@ -0,0 +1,163 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GfxConfigLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG      UserOptions;
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxConfigPostInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate UMA configuration data
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxConfigPostInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  GFX_PLATFORM_CONFIG       *Gfx;
+  AMD_POST_PARAMS           *PostParamsPtr;
+  AGESA_STATUS              Status;
+  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
+  Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
+  ASSERT (Gfx != NULL);
+  if (Gfx != NULL) {
+    LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
+    if (GnbBuildOptions.IgfxModeAsPcieEp) {
+      Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
+      Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
+    } else {
+      Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
+      Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
+    }
+    Gfx->StdHeader = /* (PVOID) */(UINT32) StdHeader;
+    Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
+    Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
+    Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
+    Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
+    Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
+    Gfx->GmcClockGating = GnbBuildOptions.CfgGmcClockGating;
+    Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGating;
+    Gfx->UmaSteering = excel992 ;
+    GNB_DEBUG_CODE (
+      GfxConfigDebugDump (Gfx);
+      );
+  } else {
+    Status = AGESA_ERROR;
+  }
+  IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h
new file mode 100644
index 0000000000..b94ae4a9f4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize GFX configuration data structure.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBGFXCONFIG_H_
+#define _GNBGFXCONFIG_H_
+
+#include "GfxConfigLib.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
new file mode 100644
index 0000000000..cc16c333a1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
@@ -0,0 +1,211 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Supporting services to collect discrete GFX card info
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include "GnbCommonLib.h"
+#include  "GfxCardInfo.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA     ScanData;
+  GFX_CARD_CARD_INFO    *GfxCardInfo;
+  PCI_ADDR              BaseBridge;
+  UINT8                 BusNumber;
+} GFX_SCAN_DATA;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+SCAN_STATUS
+GfxScanPcieDevice (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get information about all discrete GFX card in system
+ *
+ *
+ *
+ * @param[out] GfxCardInfo     Pointer to GFX card info structure
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+VOID
+GfxGetDiscreteCardInfo (
+     OUT   GFX_CARD_CARD_INFO  *GfxCardInfo,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  GFX_SCAN_DATA GfxScanData;
+  PCI_ADDR      Start;
+  PCI_ADDR      End;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n");
+  Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0);
+  GfxScanData.BusNumber = 5;
+  GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice;
+  GfxScanData.ScanData.StdHeader = StdHeader;
+  GfxScanData.GfxCardInfo = GfxCardInfo;
+  GnbLibPciScan (Start, End, &GfxScanData.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+GfxScanPcieDevice (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  UINT8   ClassCode;
+  UINT32  VendorId;
+
+  IDS_HDT_CONSOLE (GFX_MISC, "  Evaluate device [%d:%d:%d]\n",
+    Device.Address.Bus, Device.Address.Device, Device.Address.Function
+    );
+
+  if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) {
+    UINT32    SaveBusConfiguration;
+    UINT32    Value;
+
+    if (Device.Address.Bus == 0) {
+      ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device;
+    }
+    GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader);
+    Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus;
+    GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader);
+    ((GFX_SCAN_DATA *) ScanData)->BusNumber++;
+
+    GnbLibPciScanSecondaryBus (Device, ScanData);
+
+    ((GFX_SCAN_DATA *) ScanData)->BusNumber--;
+    GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader);
+    return 0;
+  }
+  GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader);
+  if (ClassCode == 3) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Found GFX Card\n"
+      );
+
+    GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader);
+    if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) {
+      IDS_HDT_CONSOLE (GFX_MISC, "  GFX Card is PCI device\n"
+        );
+      ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
+      return 0;
+    }
+    if ((UINT16) VendorId == 0x1002) {
+      IDS_HDT_CONSOLE (GFX_MISC, "  GFX Card is AMD PCIe device\n"
+        );
+      ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
+    }
+    ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
+  }
+  return 0;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h
new file mode 100644
index 0000000000..e90ea23694
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Supporting services to collect discrete GFX card info
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GFXCARDINFO_H_
+#define _GFXCARDINFO_H_
+
+VOID
+GfxGetDiscreteCardInfo (
+  OUT     GFX_CARD_CARD_INFO  *GfxCardInfo,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
new file mode 100644
index 0000000000..1e89d03f19
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -0,0 +1,636 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+typedef struct {
+  PCIE_CONNECTOR_TYPE ConnectorType;
+  UINT8               DisplayDeviceEnum;
+  UINT16              ConnectorEnum;
+  UINT16              EncoderEnum;
+  UINT8               ConnectorIndex;
+} EXT_CONNECTOR_INFO;
+
+typedef struct {
+  UINT8               DisplayDeviceEnum;
+  UINT8               DeviceIndex;
+  UINT16              DeviceTag;
+  UINT16              DeviceAcpiEnum;
+} EXT_DISPLAY_DEVICE_INFO;
+
+typedef struct {
+  AGESA_STATUS        Status;
+  UINT8               DisplayDeviceEnum;
+  UINT8               RequestedPriorityIndex;
+  UINT8               CurrentPriorityIndex;
+  PCIe_ENGINE_CONFIG  *Engine;
+} CONNECTOR_ENUM_INFO;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+GfxIntegratedEnumConnectorsForDevice (
+  IN       UINT8                            DisplayDeviceEnum,
+     OUT   EXT_DISPLAY_PATH                 *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG             *Pcie,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+VOID
+GfxIntegratedDebugDumpDisplayPath (
+  IN       EXT_DISPLAY_PATH                 *DisplayPath,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+AGESA_STATUS
+GfxIntegratedEnumerateAllConnectors (
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG        *Pcie,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+VOID
+GfxIntegratedCopyDisplayInfo (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPath,
+     OUT   EXT_DISPLAY_PATH            *SecondaryDisplayPath,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+EXT_CONNECTOR_INFO ConnectorInfoTable[] = {
+  {
+    ConnectorTypeDP,
+    DEVICE_DFP,
+    CONNECTOR_DISPLAYPORT_ENUM,
+    ENCODER_NOT_PRESENT,
+    0,
+  },
+  {
+    ConnectorTypeEDP,
+    DEVICE_LCD,
+    CONNECTOR_eDP_ENUM,
+    ENCODER_NOT_PRESENT,
+    1
+  },
+  {
+    ConnectorTypeSingleLinkDVI,
+    DEVICE_DFP,
+    CONNECTOR_SINGLE_LINK_DVI_D_ENUM,
+    ENCODER_NOT_PRESENT,
+    2
+  },
+  {
+    ConnectorTypeDualLinkDVI,
+    DEVICE_DFP,
+    CONNECTOR_DUAL_LINK_DVI_D_ENUM,
+    ENCODER_NOT_PRESENT,
+    3
+  },
+  {
+    ConnectorTypeHDMI,
+    DEVICE_DFP,
+    CONNECTOR_HDMI_TYPE_A_ENUM,
+    ENCODER_NOT_PRESENT,
+    4
+  },
+  {
+    ConnectorTypeTravisDpToVga,
+    DEVICE_CRT,
+    CONNECTOR_VGA_ENUM,
+    ENCODER_TRAVIS_ENUM_ID1,
+    5
+  },
+  {
+    ConnectorTypeTravisDpToLvds,
+    DEVICE_LCD,
+    CONNECTOR_LVDS_ENUM,
+    ENCODER_TRAVIS_ENUM_ID2,
+    6
+  },
+  {
+    ConnectorTypeNutmegDpToVga,
+    DEVICE_CRT,
+    CONNECTOR_VGA_ENUM,
+    ENCODER_ALMOND_ENUM_ID1,
+    5
+  },
+  {
+    ConnectorTypeSingleLinkDviI,
+    DEVICE_DFP,
+    CONNECTOR_SINGLE_LINK_DVI_I_ENUM,
+    ENCODER_NOT_PRESENT,
+    5
+  },
+  {
+    ConnectorTypeCrt,
+    DEVICE_CRT,
+    CONNECTOR_VGA_ENUM,
+    ENCODER_NOT_PRESENT,
+    5
+  },
+  {
+    ConnectorTypeLvds,
+    DEVICE_LCD,
+    CONNECTOR_LVDS_ENUM,
+    ENCODER_NOT_PRESENT,
+    6
+  },
+  {
+    ConnectorTypeEDPToLvds,
+    DEVICE_LCD,
+    CONNECTOR_eDP_ENUM,
+    ENCODER_NOT_PRESENT,
+    1
+  },
+  {
+    ConnectorTypeEDPToRealtecLvds,
+    DEVICE_LCD,
+    CONNECTOR_eDP_ENUM,
+    ENCODER_NOT_PRESENT,
+    1
+  },
+  {
+    ConnectorTypeAutoDetect,
+    DEVICE_LCD,
+    CONNECTOR_LVDS_eDP_ENUM,
+    ENCODER_TRAVIS_ENUM_ID2,
+    7
+  },
+};
+
+UINT8 ConnectorNumerArray[] = {
+//  DP    eDP   SDVI-D  DDVI-D  HDMI   VGA   LVDS   Auto (eDP, LVDS, Travis LVDS)
+    6,    1,    6,      6,      6,     1,    1,     2
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in] ConnectorType   Connector type (see PCIe_DDI_DATA::ConnectorType).
+ * @retval    Pointer to EXT_CONNECTOR_INFO
+ * @retval    NULL if connector type unknown.
+ */
+STATIC EXT_CONNECTOR_INFO*
+GfxIntegratedExtConnectorInfo (
+  IN       UINT8                         ConnectorType
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) {
+    if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) {
+      return &ConnectorInfoTable[Index];
+    }
+  }
+  return NULL;
+}
+
+EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
+  {
+    DEVICE_CRT,
+    1,
+    ATOM_DEVICE_CRT1_SUPPORT,
+    0x100,
+  },
+  {
+    DEVICE_LCD,
+    1,
+    ATOM_DEVICE_LCD1_SUPPORT,
+    0x110,
+  },
+  {
+    DEVICE_DFP,
+    1,
+    ATOM_DEVICE_DFP1_SUPPORT,
+    0x210,
+  },
+  {
+    DEVICE_DFP,
+    2,
+    ATOM_DEVICE_DFP2_SUPPORT,
+    0x220,
+  },
+  {
+    DEVICE_DFP,
+    3,
+    ATOM_DEVICE_DFP3_SUPPORT,
+    0x230,
+  },
+  {
+    DEVICE_DFP,
+    4,
+    ATOM_DEVICE_DFP4_SUPPORT,
+    0x240,
+  },
+  {
+    DEVICE_DFP,
+    5,
+    ATOM_DEVICE_DFP5_SUPPORT,
+    0x250,
+  },
+  {
+    DEVICE_DFP,
+    6,
+    ATOM_DEVICE_DFP6_SUPPORT,
+    0x260,
+  }
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in] DisplayDeviceEnum   Display device enum
+ * @param[in] DisplayDeviceIndex  Display device index
+ * @retval    Pointer to EXT_DISPLAY_DEVICE_INFO
+ * @retval    NULL if can not get display device info
+ */
+STATIC EXT_DISPLAY_DEVICE_INFO*
+GfxIntegratedExtDisplayDeviceInfo (
+  IN       UINT8                         DisplayDeviceEnum,
+  IN       UINT8                         DisplayDeviceIndex
+  )
+{
+  UINT8 Index;
+  UINT8 LastIndex;
+  LastIndex = 0xff;
+  for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) {
+    if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) {
+      LastIndex = Index;
+      if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) {
+        return &DisplayDeviceInfoTable[Index];
+      }
+    }
+  }
+  if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) {
+    return &DisplayDeviceInfoTable[LastIndex];
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors
+ *
+ *
+ *
+ * @param[out]    DisplayPathList   Display path list
+ * @param[in,out] Pcie              PCIe platform configuration info
+ * @param[in]     Gfx               Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAllConnectors (
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG        *Pcie,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  AGESA_STATUS  AgesaStatus;
+  AGESA_STATUS  Status;
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n");
+  Status = GfxIntegratedEnumConnectorsForDevice (
+             DEVICE_DFP,
+             DisplayPathList,
+             Pcie,
+             Gfx
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = GfxIntegratedEnumConnectorsForDevice (
+             DEVICE_CRT,
+             DisplayPathList,
+             Pcie,
+             Gfx
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = GfxIntegratedEnumConnectorsForDevice (
+             DEVICE_LCD,
+             DisplayPathList,
+             Pcie,
+             Gfx
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegratedDdiInterfaceCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  CONNECTOR_ENUM_INFO     *ConnectorEnumInfo;
+  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer;
+  ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
+  if (ExtConnectorInfo == NULL) {
+    AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status);
+    PcieConfigDisableEngine (Engine);
+    return;
+  }
+  if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) {
+    //Not device type we are looking for
+    return;
+  }
+  if (Engine->Type.Ddi.DisplayPriorityIndex >=  ConnectorEnumInfo->RequestedPriorityIndex &&
+      Engine->Type.Ddi.DisplayPriorityIndex <  ConnectorEnumInfo->CurrentPriorityIndex) {
+    ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex;
+    ConnectorEnumInfo->Engine = Engine;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors for specific display device type.
+ *
+ *
+ *
+ * @param[in]     DisplayDeviceEnum Display device list
+ * @param[out]    DisplayPathList   Display path list
+ * @param[in,out] Pcie              PCIe configuration info
+ * @param[in]     Gfx               Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumConnectorsForDevice (
+  IN       UINT8                       DisplayDeviceEnum,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG        *Pcie,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  UINT8                   DisplayDeviceIndex;
+  CONNECTOR_ENUM_INFO     ConnectorEnumInfo;
+  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
+  AGESA_STATUS            Status;
+  UINT8                   ConnectorIdArray[sizeof (ConnectorNumerArray)];
+  ConnectorEnumInfo.Status = AGESA_SUCCESS;
+  DisplayDeviceIndex = 1;
+  ConnectorEnumInfo.RequestedPriorityIndex = 0;
+  ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum;
+  LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx));
+  do {
+    ConnectorEnumInfo.Engine = NULL;
+    ConnectorEnumInfo.CurrentPriorityIndex = 0xff;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+      GfxIntegratedDdiInterfaceCallback,
+      &ConnectorEnumInfo,
+      Pcie
+      );
+    if (ConnectorEnumInfo.Engine == NULL) {
+      break;                                  // No more connector support this
+    }
+    ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1;
+    ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType);
+    ASSERT (ExtConnectorInfo != NULL);
+    ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray));
+    if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >=  ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) {
+      //Run out of supported connectors
+      AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
+      PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
+      continue;
+    }
+    ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1;
+    ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex);
+    if (ExtDisplayDeviceInfo == NULL) {
+      //Run out of supported display device types
+      AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
+      Status = AGESA_ERROR;
+      PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
+    }
+
+    if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) {
+      AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
+      Status = AGESA_ERROR;
+      PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
+    }
+
+    ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex;
+
+    Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx);
+    AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status);
+    if (Status != AGESA_SUCCESS) {
+      continue;
+    }
+    ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++;
+    DisplayDeviceIndex++;
+  } while (ConnectorEnumInfo.Engine != NULL);
+  return ConnectorEnumInfo.Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize display path for given engine
+ *
+ *
+ *
+ * @param[in]  Engine            Engine configuration info
+ * @param[out] DisplayPath       Display path list
+ * @param[out] SecondaryDisplayPath Secondary display path list
+ * @param[in] Gfx                Gfx configuration info
+ */
+
+VOID
+GfxIntegratedCopyDisplayInfo (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPath,
+     OUT   EXT_DISPLAY_PATH            *SecondaryDisplayPath,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  EXT_CONNECTOR_INFO      *ExtConnectorInfo;
+  EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
+  ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
+  ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId);
+  DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8);
+  DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag;
+  DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum;
+  DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex;
+  DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex;
+  DisplayPath->ucChPNInvert = Engine->Type.Ddi.DdiData.LanePnInversionMask;
+  DisplayPath->usCaps = Engine->Type.Ddi.DdiData.Flags;
+  DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum;
+  if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) {
+    DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B;
+  } else {
+    DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue;
+  }
+  GNB_DEBUG_CODE (
+    GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx);
+    );
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) {
+    if (SecondaryDisplayPath != NULL) {
+      SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector;
+    }
+    GNB_DEBUG_CODE (
+      GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx);
+    );
+
+    if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) {
+      DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B;
+    } else {
+      DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue;
+    }
+  }
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump  display path settings
+ *
+ *
+ *
+ * @param[in] DisplayPath            Display path
+ * @param[in] Gfx                    Gfx configuration
+ */
+
+VOID
+GfxIntegratedDebugDumpDisplayPath (
+  IN       EXT_DISPLAY_PATH            *DisplayPath,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+ IDS_HDT_CONSOLE (GFX_MISC, "     usDeviceConnector = 0x%x\n",
+   DisplayPath->usDeviceConnector
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usDeviceTag = 0x%x\n",
+   DisplayPath->usDeviceTag
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usDeviceACPIEnum = 0x%x\n",
+   DisplayPath->usDeviceACPIEnum
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usExtEncoderObjId = 0x%x\n",
+   DisplayPath->usExtEncoderObjId
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     ucChannelMapping = 0x%x\n",
+   DisplayPath->ChannelMapping.ucChannelMapping
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     ucChPNInvert = 0x%x\n",
+   DisplayPath->ucChPNInvert
+   );
+ IDS_HDT_CONSOLE (GFX_MISC, "     usCaps = 0x%x\n",
+   DisplayPath->usCaps
+   );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h
new file mode 100644
index 0000000000..0527f33bb8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXENUMCONNECTORS_H_
+#define _GFXENUMCONNECTORS_H_
+
+
+VOID
+GfxIntegratedCopyDisplayInfo (
+  IN       PCIe_ENGINE_CONFIG             *Engine,
+     OUT   EXT_DISPLAY_PATH               *DisplayPath,
+     OUT   EXT_DISPLAY_PATH               *SecondaryDisplayPath,
+  IN       GFX_PLATFORM_CONFIG            *Gfx
+  );
+
+AGESA_STATUS
+GfxIntegratedEnumerateAllConnectors (
+     OUT   EXT_DISPLAY_PATH                 *DisplayPathList,
+  IN OUT   PCIe_PLATFORM_CONFIG             *Pcie,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
new file mode 100644
index 0000000000..462fa72c01
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -0,0 +1,1013 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Integrated Info Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbFuseTable.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GfxPowerPlayTable.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Software state
+typedef struct {
+  BOOLEAN     Valid;                                  ///< State valid
+  UINT16      Classification;                         ///< State classification
+  UINT32      CapsAndSettings;                        ///< State capability and settings
+  UINT16      Classification2;                        ///< State classification2
+  UINT32      Vclk;                                   ///< UVD VCLK
+  UINT32      Dclk;                                   ///< UVD DCLK
+  UINT8       NumberOfDpmStates;                      ///< Number of DPM states
+  UINT8       DpmSatesArray[MAX_NUM_OF_DPM_STATES];   ///< DPM state index array
+} SW_STATE;
+
+/// DPM state
+typedef struct {
+  BOOLEAN     Valid;                                  ///< State valid
+  UINT32      Sclk;                                   ///< Sclk in kHz
+  UINT8       Vid;                                    ///< VID index
+  UINT16      Tdp;                                    ///< Tdp limit
+} DPM_STATE;
+
+typedef struct {
+  GFX_PLATFORM_CONFIG                       *Gfx;
+  ATOM_PPLIB_POWERPLAYTABLE3                *PpTable;
+  PP_FUSE_ARRAY                             *PpFuses;
+  SW_STATE                                  SwStateArray [MAX_NUM_OF_SW_STATES];          ///< SW state array
+  DPM_STATE                                 DpmStateArray[MAX_NUM_OF_DPM_STATES];         ///< Sclk DPM state array
+  UINT8                                     NumOfClockVoltageLimitEnties;                 ///
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD VceClockVoltageLimitArray[MAX_NUM_OF_VCE_CLK_STATES];
+  UINT8                                     NumOfVceClockEnties;
+  VCECLOCKINFO                              VceClockInfoArray[MAX_NUM_OF_VCE_CLK_STATES];
+  UINT8                                     NumOfVceStateEntries;
+  ATOM_PPLIB_VCE_STATE_RECORD               VceStateArray[MAX_NUM_OF_VCE_STATES];         ///< VCE state array
+} PP_WORKSPACE;
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GfxIntegratedDebugDumpPpTable (
+  IN       ATOM_PPLIB_POWERPLAYTABLE3   *PpTable,
+  IN       GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate existing tdp
+ *
+ *
+ * @param[in     ]  PpFuses          Pointer to  PP_FUSE_ARRAY
+ * @param[in]       Sclk             Sclk in 10kHz
+ * @param[in]       StdHeader        Standard configuration header
+ * @retval                           Tdp limit in DPM state array
+ */
+
+STATIC UINT16
+GfxPowerPlayLocateTdp (
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      UINT32                        Sclk,
+  IN      AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  UINT8   Index;
+  UINT32  DpmIndex;
+  UINT32  DpmSclk;
+  UINT32  DeltaSclk;
+  UINT32  MinDeltaSclk;
+
+  DpmIndex = 0;
+  MinDeltaSclk = 0xFFFFFFFF;
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+    if (PpFuses->SclkDpmDid[Index] != 0) {
+      DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader);
+      DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk);
+      if (DeltaSclk < MinDeltaSclk) {
+        MinDeltaSclk = MinDeltaSclk;
+        DpmIndex = Index;
+      }
+    }
+  }
+  return PpFuses->SclkDpmTdpLimit[DpmIndex];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create new software state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @retval                           Pointer to state entry in SW state array
+ */
+
+STATIC SW_STATE*
+GfxPowerPlayCreateSwState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
+    if (PpWorkspace->SwStateArray[Index].Valid == FALSE) {
+      PpWorkspace->SwStateArray[Index].Valid = TRUE;
+      return  &(PpWorkspace->SwStateArray[Index]);
+    }
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create new DPM state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       Sclk             SCLK in kHz
+ * @param[in]       Vid              Vid index
+ * @param[in]       Tdp              Tdp limit
+ * @retval                           Index of state entry in DPM state array
+ */
+
+STATIC UINT8
+GfxPowerPlayCreateDpmState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT32                        Sclk,
+  IN       UINT8                         Vid,
+  IN       UINT16                        Tdp
+  )
+{
+  UINT8 Index;
+  for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
+    if (PpWorkspace->DpmStateArray[Index].Valid == FALSE) {
+      PpWorkspace->DpmStateArray[Index].Sclk = Sclk;
+      PpWorkspace->DpmStateArray[Index].Vid = Vid;
+      PpWorkspace->DpmStateArray[Index].Valid = TRUE;
+      PpWorkspace->DpmStateArray[Index].Tdp = Tdp;
+      return Index;
+    }
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate existing or Create new DPM state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       Sclk             SCLK in kHz
+ * @param[in]       Vid              Vid index
+ * @param[in]       Tdp              Tdp limit
+ * @retval                           Index of state entry in DPM state array
+ */
+
+STATIC UINT8
+GfxPowerPlayAddDpmState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT32                        Sclk,
+  IN       UINT8                         Vid,
+  IN       UINT16                        Tdp
+  )
+{
+  UINT8 Index;
+  for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
+    if (PpWorkspace->DpmStateArray[Index].Valid && Sclk == PpWorkspace->DpmStateArray[Index].Sclk && Vid == PpWorkspace->DpmStateArray[Index].Vid) {
+      return Index;
+    }
+  }
+  return GfxPowerPlayCreateDpmState (PpWorkspace, Sclk, Vid, Tdp);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Add reference to DPM state for SW state
+ *
+ *
+ * @param[in, out]  SwStateArray     Pointer to SW state array
+ * @param[in]       DpmStateIndex    DPM state index
+ */
+
+STATIC VOID
+GfxPowerPlayAddDpmStateToSwState (
+  IN OUT   SW_STATE                      *SwStateArray,
+  IN       UINT8                         DpmStateIndex
+  )
+{
+  SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy SW state info to PPTable
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+STATIC VOID *
+GfxPowerPlayAttachStateInfoBlock (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINT8                 Index;
+  UINT8                 SwStateIndex;
+  STATE_ARRAY           *StateArray;
+  ATOM_PPLIB_STATE_V2   *States;
+  StateArray = (STATE_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  States = &StateArray->States[0];
+  SwStateIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
+    if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) {
+      States->nonClockInfoIndex  = SwStateIndex;
+      States->ucNumDPMLevels = PpWorkspace->SwStateArray[Index].NumberOfDpmStates;
+      LibAmdMemCopy (
+        &States->ClockInfoIndex[0],
+        PpWorkspace->SwStateArray[Index].DpmSatesArray,
+        PpWorkspace->SwStateArray[Index].NumberOfDpmStates,
+        GnbLibGetHeader (PpWorkspace->Gfx)
+        );
+      States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1));
+      SwStateIndex++;
+    }
+  }
+  StateArray->ucNumEntries = SwStateIndex;
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize + (USHORT) ((UINT8 *) States - (UINT8 *) StateArray);
+  return StateArray;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy clock info to PPTable
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachClockInfoBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  CLOCK_INFO_ARRAY            *ClockInfoArray;
+  UINT8                       Index;
+  UINT8                       ClkStateIndex;
+  ClkStateIndex = 0;
+  ClockInfoArray = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
+    if (PpWorkspace->DpmStateArray[Index].Valid == TRUE) {
+      ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (PpWorkspace->DpmStateArray[Index].Sclk  >> 16);
+      ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (PpWorkspace->DpmStateArray[Index].Sclk);
+      ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = PpWorkspace->DpmStateArray[Index].Vid;
+      ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = PpWorkspace->DpmStateArray[Index].Tdp;
+      ClkStateIndex++;
+    }
+  }
+  ClockInfoArray->ucNumEntries = ClkStateIndex;
+  ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * ClkStateIndex - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
+  return ClockInfoArray;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy non clock info to PPTable
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachNonClockInfoBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  NON_CLOCK_INFO_ARRAY  *NonClockInfoArray;
+  UINT8                 Index;
+  UINT8                 NonClkStateIndex;
+
+  NonClockInfoArray = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  NonClkStateIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
+    if (PpWorkspace->SwStateArray[Index].Valid && PpWorkspace->SwStateArray[Index].NumberOfDpmStates != 0) {
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = PpWorkspace->SwStateArray[Index].Classification;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = PpWorkspace->SwStateArray[Index].CapsAndSettings;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification2 = PpWorkspace->SwStateArray[Index].Classification2;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = PpWorkspace->SwStateArray[Index].Dclk;
+      NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = PpWorkspace->SwStateArray[Index].Vclk;
+      NonClkStateIndex++;
+    }
+  }
+  NonClockInfoArray->ucNumEntries = NonClkStateIndex;
+  NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO);
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO);
+  return NonClockInfoArray;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if fused state valid
+ *
+ *
+ * @param[out]      Index             State index
+ * @param[in]       PpFuses           Pointer to fuse table
+ * @param[in]       Gfx               Gfx configuration info
+ * @retval          TRUE              State is valid
+ */
+STATIC BOOLEAN
+GfxPowerPlayIsFusedStateValid (
+  IN      UINT8                         Index,
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  BOOLEAN Result;
+  Result = FALSE;
+  if (PpFuses->SclkDpmValid[Index] != 0) {
+    Result = TRUE;
+    if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) {
+      Result = FALSE;
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SW state calssification from fuses
+ *
+ *
+ * @param[out]      Index             State index
+ * @param[in]       PpFuses           Pointer to fuse table
+ * @param[in]       Gfx               Gfx configuration info
+ * @retval                            State classification
+ */
+
+STATIC UINT16
+GfxPowerPlayGetClassificationFromFuses (
+  IN      UINT8                         Index,
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  UINT16  Classification;
+  Classification = 0;
+  switch (PpFuses->PolicyFlags[Index]) {
+  case 0x1:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE;
+    break;
+  case 0x2:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE;
+    break;
+  case 0x4:
+    //Possible SD + HD state
+    break;
+  case 0x8:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE;
+    break;
+  case 0x10:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE;
+    break;
+  default:
+    break;
+  }
+  switch (PpFuses->PolicyLabel[Index]) {
+  case POLICY_LABEL_BATTERY:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY;
+    break;
+  case POLICY_LABEL_PERFORMANCE:
+    Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE;
+    break;
+  default:
+    break;
+  }
+  return Classification;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SW state calssification2 from fuses
+ *
+ *
+ * @param[out]      Index             State index
+ * @param[in]       PpFuses           Pointer to fuse table
+ * @param[in]       Gfx               Gfx configuration info
+ * @retval                            State classification2
+ */
+
+STATIC UINT16
+GfxPowerPlayGetClassification2FromFuses (
+  IN      UINT8                         Index,
+  IN      PP_FUSE_ARRAY                 *PpFuses,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  UINT16  Classification2;
+  Classification2 = 0;
+
+  switch (PpFuses->PolicyFlags[Index]) {
+
+  case 0x4:
+    Classification2 |= ATOM_PPLIB_CLASSIFICATION2_MVC;
+    break;
+
+  default:
+    break;
+  }
+
+  return Classification2;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build SCLK state info
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID
+GfxPowerPlayBuildSclkStateTable (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINT8                       ClkStateIndex;
+  UINT8                       DpmFuseIndex;
+  UINT8                       Index;
+  UINT32                      Sclk;
+  SW_STATE                    *State;
+  PP_FUSE_ARRAY               *PpFuses;
+
+  PpFuses = PpWorkspace->PpFuses;
+  // Create States from Fuses
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) {
+    if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, PpWorkspace->Gfx)) {
+      //Create new SW State;
+      State = GfxPowerPlayCreateSwState (PpWorkspace);
+      State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, PpWorkspace->Gfx);
+      State->Classification2 = GfxPowerPlayGetClassification2FromFuses (Index, PpFuses, PpWorkspace->Gfx);
+      if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0 ||
+          (State->Classification2 & ATOM_PPLIB_CLASSIFICATION2_MVC) != 0) {
+        State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]],  GnbLibGetHeader (PpWorkspace->Gfx)) : 0;
+        State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]],  GnbLibGetHeader (PpWorkspace->Gfx)) : 0;
+      }
+      if (((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
+          ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) != 0)) {
+        if (PpWorkspace->Gfx->AbmSupport != 0) {
+          State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT;
+        }
+        if (PpWorkspace->Gfx->DynamicRefreshRate != 0) {
+          State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR;
+        }
+      }
+      for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) {
+        if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) {
+          Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (PpWorkspace->Gfx)) : 0;
+          if (Sclk != 0) {
+            ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]);
+            GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
+          }
+        }
+      }
+    }
+  }
+  // Create Boot State
+  State = GfxPowerPlayCreateSwState (PpWorkspace);
+  State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT;
+  Sclk = 200 * 100;
+  ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx)));
+  GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
+
+  // Create Thermal State
+  State = GfxPowerPlayCreateSwState (PpWorkspace);
+  State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL;
+  Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (PpWorkspace->Gfx));
+  ClkStateIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx)));
+  GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Add ECLK state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       Eclk             SCLK in kHz
+ * @retval                           Index of state entry in ECLK clock array
+ */
+
+STATIC UINT8
+GfxPowerPlayAddEclkState (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT32                        Eclk
+  )
+{
+  UINT8   Index;
+  USHORT  EclkLow;
+  UCHAR   EclkHigh;
+  EclkLow = (USHORT) (Eclk & 0xffff);
+  EclkHigh = (UCHAR) (Eclk >> 16);
+  for (Index = 0; Index < PpWorkspace->NumOfVceClockEnties; Index++) {
+    if (PpWorkspace->VceClockInfoArray[Index].ucECClkHigh == EclkHigh && PpWorkspace->VceClockInfoArray[Index].usECClkLow == EclkLow) {
+      return Index;
+    }
+  }
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucECClkHigh = EclkHigh;
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usECClkLow = EclkLow;
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].ucEVClkHigh = EclkHigh;
+  PpWorkspace->VceClockInfoArray[PpWorkspace->NumOfVceClockEnties].usEVClkLow = EclkLow;
+  return PpWorkspace->NumOfVceClockEnties++;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Add ECLK state
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ * @param[in]       EclkIndex        ECLK index
+  * @param[in]      Vid              Vid index
+ * @retval                           Index of state entry in Eclk Voltage record array
+ */
+
+STATIC UINT8
+GfxPowerPlayAddEclkVoltageRecord (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace,
+  IN       UINT8                         EclkIndex,
+  IN       UINT8                         Vid
+  )
+{
+  UINT8   Index;
+  for (Index = 0; Index < PpWorkspace->NumOfClockVoltageLimitEnties; Index++) {
+    if (PpWorkspace->VceClockVoltageLimitArray[Index].ucVCEClockInfoIndex == EclkIndex) {
+      return Index;
+    }
+  }
+  PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].ucVCEClockInfoIndex = EclkIndex;
+  PpWorkspace->VceClockVoltageLimitArray[PpWorkspace->NumOfClockVoltageLimitEnties].usVoltage = Vid;
+  return PpWorkspace->NumOfClockVoltageLimitEnties++;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach extended header
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceTableRevBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_VCE_TABLE  *VceTable;
+  VceTable = (ATOM_PPLIB_VCE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceTable->revid = 0;
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_VCE_TABLE);
+  return VceTable;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach extended header
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachExtendedHeaderBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_EXTENDEDHEADER *ExtendedHeader;
+  ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  ExtendedHeader->usSize = sizeof (ATOM_PPLIB_EXTENDEDHEADER);
+  PpWorkspace->PpTable->sHeader.usStructureSize += sizeof (ATOM_PPLIB_EXTENDEDHEADER);
+  return ExtendedHeader;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach VCE clock info block
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceClockInfoBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  VCECLOCKINFOARRAY   *VceClockInfoArray;
+  VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceClockInfoArray->ucNumEntries = PpWorkspace->NumOfVceClockEnties;
+  LibAmdMemCopy (
+    &VceClockInfoArray->entries[0],
+    &PpWorkspace->VceClockInfoArray[0],
+    VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO),
+    GnbLibGetHeader (PpWorkspace->Gfx)
+    );
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize +
+                                                  sizeof (VCECLOCKINFOARRAY) +
+                                                  VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) -
+                                                  sizeof (VCECLOCKINFO);
+  return VceClockInfoArray;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach VCE voltage limit block
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceVoltageLimitBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE  *VceClockVoltageLimitTable;
+  VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceClockVoltageLimitTable->numEntries = PpWorkspace->NumOfClockVoltageLimitEnties;
+  LibAmdMemCopy (
+    &VceClockVoltageLimitTable->entries[0],
+    &PpWorkspace->VceClockVoltageLimitArray[0],
+    VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD),
+    GnbLibGetHeader (PpWorkspace->Gfx)
+    );
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize +
+                                                  sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) +
+                                                  VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) -
+                                                  sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD);
+  return VceClockVoltageLimitTable;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach VCE state block
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID *
+GfxPowerPlayAttachVceStateTaleBlock (
+  IN OUT   PP_WORKSPACE                 *PpWorkspace
+  )
+{
+  ATOM_PPLIB_VCE_STATE_TABLE  *VceStateTable;
+  VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) PpWorkspace->PpTable + PpWorkspace->PpTable->sHeader.usStructureSize);
+  VceStateTable->numEntries = PpWorkspace->NumOfVceStateEntries;
+  LibAmdMemCopy (
+    &VceStateTable->entries[0],
+    &PpWorkspace->VceStateArray[0],
+    VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD),
+    GnbLibGetHeader (PpWorkspace->Gfx)
+    );
+  PpWorkspace->PpTable->sHeader.usStructureSize = PpWorkspace->PpTable->sHeader.usStructureSize +
+                                                  sizeof (ATOM_PPLIB_VCE_STATE_TABLE) +
+                                                  VceStateTable->numEntries * sizeof (ATOM_PPLIB_VCE_STATE_RECORD) -
+                                                  sizeof (ATOM_PPLIB_VCE_STATE_RECORD);
+  return VceStateTable;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build VCE state info
+ *
+ *
+ * @param[in, out]  PpWorkspace      PP workspace
+ */
+
+STATIC VOID
+GfxPowerPlayBuildVceStateTable (
+  IN OUT   PP_WORKSPACE                  *PpWorkspace
+  )
+{
+  UINT8                       Index;
+  UINT8                       VceStateIndex;
+  UINT8                       Vid;
+  UINT32                      Eclk;
+  UINT32                      Sclk;
+  UINT8                       UsedStateBitmap;
+  UsedStateBitmap = 0;
+  // build used state
+  for (Index = 0; Index < (sizeof (PpWorkspace->PpFuses->VceFlags) / sizeof (PpWorkspace->PpFuses->VceFlags[0])) ; Index++) {
+    UsedStateBitmap |= PpWorkspace->PpFuses->VceFlags[Index];
+    for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) {
+      if ((PpWorkspace->PpFuses->VceFlags[Index] & (1 << VceStateIndex)) != 0) {
+        Sclk = GfxFmCalculateClock (PpWorkspace->PpFuses->SclkDpmDid[PpWorkspace->PpFuses->VceReqSclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx));
+        Vid = PpWorkspace->PpFuses->SclkDpmVid[PpWorkspace->PpFuses->VceReqSclkSel[Index]];
+        PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = GfxPowerPlayAddDpmState (PpWorkspace, Sclk, Vid, GfxPowerPlayLocateTdp (PpWorkspace->PpFuses, Sclk, GnbLibGetHeader (PpWorkspace->Gfx)));
+        if (PpWorkspace->PpFuses->VceMclk[Index] == 1) {
+          PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex |= (PpWorkspace->PpFuses->VceMclk[Index] << 6);
+        }
+        Eclk = GfxFmCalculateClock (PpWorkspace->PpFuses->EclkDid[Index], GnbLibGetHeader (PpWorkspace->Gfx));
+        PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, Eclk);
+        GfxPowerPlayAddEclkVoltageRecord (PpWorkspace, PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex, Vid);
+        PpWorkspace->NumOfVceStateEntries++;
+      }
+    }
+  }
+  //build unused states
+  for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) {
+    if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) {
+      PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0;
+      PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, 0);
+      PpWorkspace->NumOfVceStateEntries++;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build PP table
+ *
+ *
+ * @param[out] Buffer           Buffer to create PP table
+ * @param[in]  Gfx              Gfx configuration info
+ * @retval     AGESA_SUCCESS
+ * @retval     AGESA_ERROR
+ */
+
+AGESA_STATUS
+GfxPowerPlayBuildTable (
+     OUT   VOID                          *Buffer,
+  IN       GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+  PP_WORKSPACE                PpWorkspace;
+  VOID                        *BlockPtr;
+
+  LibAmdMemFill (&PpWorkspace, 0x00, sizeof (PP_WORKSPACE), GnbLibGetHeader (Gfx));
+  PpWorkspace.PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+  ASSERT (PpWorkspace.PpFuses != NULL);
+  if (PpWorkspace.PpFuses == NULL) {
+    return AGESA_ERROR;
+  }
+  PpWorkspace.PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer;
+  PpWorkspace.Gfx = Gfx;
+  //Fill static info
+  PpWorkspace.PpTable->sHeader.ucTableFormatRevision = 6;
+  PpWorkspace.PpTable->sHeader.ucTableContentRevision = 1;
+  PpWorkspace.PpTable->ucDataRevision = PpWorkspace.PpFuses->PPlayTableRev;
+  PpWorkspace.PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO;
+  PpWorkspace.PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN;
+  PpWorkspace.PpTable->sHeader.usStructureSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3);
+  PpWorkspace.PpTable->usTableSize = sizeof (ATOM_PPLIB_POWERPLAYTABLE3);
+  PpWorkspace.PpTable->usFormatID = 7;
+  if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) {
+    PpWorkspace.PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY;
+  }
+
+  // Fill Slck SW/DPM state info
+  GfxPowerPlayBuildSclkStateTable (&PpWorkspace);
+  // Fill Eclk state info
+  if (PpWorkspace.PpFuses->VceSateTableSupport) {
+    GfxPowerPlayBuildVceStateTable (&PpWorkspace);
+  }
+
+  //Copy state info to actual PP table
+  BlockPtr = GfxPowerPlayAttachStateInfoBlock (&PpWorkspace);
+  PpWorkspace.PpTable->usStateArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+  BlockPtr = GfxPowerPlayAttachClockInfoBlock (&PpWorkspace);
+  PpWorkspace.PpTable->usClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+  BlockPtr = GfxPowerPlayAttachNonClockInfoBlock (&PpWorkspace);
+  PpWorkspace.PpTable->usNonClockInfoArrayOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+  if (PpWorkspace.PpFuses->VceSateTableSupport) {
+    ATOM_PPLIB_EXTENDEDHEADER   *ExtendedHeader;
+    ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) GfxPowerPlayAttachExtendedHeaderBlock (&PpWorkspace);
+    PpWorkspace.PpTable->usExtendendedHeaderOffset = (USHORT) ((UINT8 *) ExtendedHeader - (UINT8 *) (PpWorkspace.PpTable));
+    BlockPtr = GfxPowerPlayAttachVceTableRevBlock (&PpWorkspace);
+    ExtendedHeader->usVCETableOffset = (USHORT) ((UINT8 *) BlockPtr - (UINT8 *) (PpWorkspace.PpTable));
+    GfxPowerPlayAttachVceClockInfoBlock (&PpWorkspace);
+    GfxPowerPlayAttachVceVoltageLimitBlock (&PpWorkspace);
+    GfxPowerPlayAttachVceStateTaleBlock (&PpWorkspace);
+
+  }
+  GNB_DEBUG_CODE (
+    GfxIntegratedDebugDumpPpTable (PpWorkspace.PpTable, Gfx);
+  );
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump PP table
+ *
+ *
+ *
+ * @param[in] PpTable           Power Play table
+ * @param[in] Gfx               Gfx configuration info
+ */
+
+VOID
+GfxIntegratedDebugDumpPpTable (
+  IN       ATOM_PPLIB_POWERPLAYTABLE3   *PpTable,
+  IN       GFX_PLATFORM_CONFIG          *Gfx
+  )
+{
+  UINTN                                     Index;
+  UINTN                                     DpmIndex;
+  STATE_ARRAY                               *StateArray;
+  ATOM_PPLIB_STATE_V2                       *StatesPtr;
+  NON_CLOCK_INFO_ARRAY                      *NonClockInfoArrayPtr;
+  CLOCK_INFO_ARRAY                          *ClockInfoArrayPtr;
+  ATOM_PPLIB_EXTENDEDHEADER                 *ExtendedHeader;
+  ATOM_PPLIB_VCE_STATE_TABLE                *VceStateTable;
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE  *VceClockVoltageLimitTable;
+  VCECLOCKINFOARRAY                         *VceClockInfoArray;
+  UINT8                                     SclkIndex;
+  UINT8                                     EclkIndex;
+
+  IDS_HDT_CONSOLE (GFX_MISC, "  < --- Power Play Table ------ > \n");
+  IDS_HDT_CONSOLE (GFX_MISC, "  Table Revision = %d\n", PpTable->ucDataRevision);
+  StateArray = (STATE_ARRAY *) ((UINT8 *) PpTable + PpTable->usStateArrayOffset);
+  StatesPtr = StateArray->States;
+  NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset);
+  ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
+  IDS_HDT_CONSOLE (GFX_MISC, "  < --- SW State Table ---------> \n");
+  for (Index = 0; Index < StateArray->ucNumEntries; Index++) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  State #%d\n", Index + 1
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    Classification 0x%x\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    Classification2 0x%x\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification2
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    VCLK = %dkHz\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    DCLK = %dkHz\n",
+       NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    DPM State Index: ");
+    for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) {
+      IDS_HDT_CONSOLE (GFX_MISC, "%d ",
+        StatesPtr->ClockInfoIndex [DpmIndex]
+        );
+    }
+    IDS_HDT_CONSOLE (GFX_MISC, "\n");
+    StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1);
+  }
+  IDS_HDT_CONSOLE (GFX_MISC, "  < --- SCLK DPM State Table ---> \n");
+  for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) {
+    UINT32  Sclk;
+    Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16);
+    IDS_HDT_CONSOLE (GFX_MISC, "  DPM State #%d\n",
+      Index
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    SCLK = %d\n",
+      ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16)
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    VID index = %d\n",
+      ClockInfoArrayPtr->ClockInfo[Index].vddcIndex
+      );
+    IDS_HDT_CONSOLE (GFX_MISC, "    tdpLimit  = %d\n",
+      ClockInfoArrayPtr->ClockInfo[Index].tdpLimit
+      );
+  }
+  if (PpTable->usExtendendedHeaderOffset != 0) {
+    ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable + PpTable->usExtendendedHeaderOffset);
+    VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) ExtendedHeader + sizeof (ATOM_PPLIB_EXTENDEDHEADER) + sizeof (ATOM_PPLIB_VCE_TABLE));
+    VceClockVoltageLimitTable = (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE *) ((UINT8 *) VceClockInfoArray +
+                                sizeof (VCECLOCKINFOARRAY) +
+                                VceClockInfoArray->ucNumEntries * sizeof (VCECLOCKINFO) -
+                                sizeof (VCECLOCKINFO));
+    VceStateTable = (ATOM_PPLIB_VCE_STATE_TABLE *) ((UINT8 *) VceClockVoltageLimitTable +
+                    sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE) +
+                    VceClockVoltageLimitTable->numEntries * sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD) -
+                    sizeof (ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD));
+
+    IDS_HDT_CONSOLE (GFX_MISC, "  < --- VCE State Table [%d]--> \n", VceStateTable->numEntries);
+    for (Index = 0; Index < VceStateTable->numEntries; Index++) {
+      SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F;
+      EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex;
+      IDS_HDT_CONSOLE (GFX_MISC, "  VCE State #%d\n", Index
+        );
+      if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) {
+        IDS_HDT_CONSOLE (GFX_MISC, "    Disable\n");
+      } else {
+        IDS_HDT_CONSOLE (GFX_MISC, "    SCLK = %d\n",
+          ClockInfoArrayPtr->ClockInfo[SclkIndex].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[SclkIndex].ucEngineClockHigh << 16)
+          );
+        IDS_HDT_CONSOLE (GFX_MISC, "    ECCLK = %d\n",
+          VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)
+          );
+        IDS_HDT_CONSOLE (GFX_MISC, "    EVCLK = %d\n",
+          VceClockInfoArray->entries[EclkIndex].usEVClkLow | (VceClockInfoArray->entries[EclkIndex].ucEVClkHigh << 16)
+          );
+        IDS_HDT_CONSOLE (GFX_MISC, "    MCLK = %d\n",
+          (VceStateTable->entries[Index].ucClockInfoIndex >> 6 ) & 0x3
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GFX_MISC, "  < --- VCE Voltage Record Table ---> \n");
+    for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) {
+      EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex;
+      IDS_HDT_CONSOLE (GFX_MISC, "  VCE Voltage Record #%d\n", Index
+        );
+      IDS_HDT_CONSOLE (GFX_MISC, "    ECLK = %d\n",
+        VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)
+        );
+      IDS_HDT_CONSOLE (GFX_MISC, "    VID index = %d\n",
+        VceClockVoltageLimitTable->entries[Index].usVoltage
+        );
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h
new file mode 100644
index 0000000000..fd19f605d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h
@@ -0,0 +1,278 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to initialize Power Play Table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXPOWERPLAYTABLE_H_
+#define _GFXPOWERPLAYTABLE_H_
+
+#pragma pack (push, 1)
+
+#define POLICY_LABEL_BATTERY                                0x1
+#define POLICY_LABEL_PERFORMANCE                            0x2
+
+#define MAX_NUM_OF_SW_STATES                                10
+#define MAX_NUM_OF_DPM_STATES                               10
+#define MAX_NUM_OF_VCE_CLK_STATES                           5
+#define MAX_NUM_OF_VCE_STATES                               6
+#define MAX_NUM_OF_FUSED_DPM_STATES                         5
+#define MAX_NUM_OF_FUSED_SW_STATES                          6
+/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
+#define ATOM_PP_PLATFORM_CAP_BACKBIAS                       1
+#define ATOM_PP_PLATFORM_CAP_POWERPLAY                      2
+#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE               4
+#define ATOM_PP_PLATFORM_CAP_ASPM_L0s                       8
+#define ATOM_PP_PLATFORM_CAP_ASPM_L1                        16
+#define ATOM_PP_PLATFORM_CAP_HARDWAREDC                     32
+#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY                  64
+#define ATOM_PP_PLATFORM_CAP_STEPVDDC                       128
+#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL                 256
+#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL                512
+#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1              1024
+#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL                  2048
+#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL                    4096
+#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT             0x2000        // Go to boot state on alerts, e.g. on an AC->DC transition.
+#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT  0x4000        // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
+#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL                  0x8000        // Does
+#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT                  0x00010000ul  // Enable the 'regulator hot' feature.
+#define ATOM_PP_PLATFORM_CAP_BACO                           0x00020000ul  // Does the driver supports BACO state.
+
+
+#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY                1
+#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED               3
+#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE            5
+
+#define ATOM_PPLIB_CLASSIFICATION_BOOT                      0x0008
+#define ATOM_PPLIB_CLASSIFICATION_THERMAL                   0x0010
+#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE        0x0020
+#define ATOM_PPLIB_CLASSIFICATION_REST                      0x0040
+#define ATOM_PPLIB_CLASSIFICATION_FORCED                    0x0080
+#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE             0x0100
+#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE         0x0200
+#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE                  0x0400
+#define ATOM_PPLIB_CLASSIFICATION_3DLOW                     0x0800
+#define ATOM_PPLIB_CLASSIFICATION_ACPI                      0x1000
+#define ATOM_PPLIB_CLASSIFICATION_HD2STATE                  0x2000
+#define ATOM_PPLIB_CLASSIFICATION_HDSTATE                   0x4000
+#define ATOM_PPLIB_CLASSIFICATION_SDSTATE                   0x8000
+#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE               0x0000
+
+#define ATOM_PPLIB_CLASSIFICATION2_MVC                      0x0004       //Multi-View
+
+#define ATOM_PPLIB_ENABLE_VARIBRIGHT                        0x00008000ul
+#define ATOM_PPLIB_ENABLE_DRR                               0x00080000ul
+
+#define ATOM_PP_FANPARAMETERS_NOFAN                         0x80
+#define ATOM_PP_THERMALCONTROLLER_SUMO                      0x0E
+
+/// DPM state info
+typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO {
+  USHORT                      usEngineClockLow;             ///< Sclk [15:0] (Sclk in 10khz)
+  UCHAR                       ucEngineClockHigh;            ///< Sclk [23:16](Sclk in 10khz)
+  UCHAR                       vddcIndex;                    ///< 2-bit VDDC index;
+  USHORT                      tdpLimit;                     ///< TDP Limit
+  USHORT                      rsv1;                         ///< Reserved
+  ULONG                       rsv2[2];                      ///< Reserved
+} ATOM_PPLIB_SUMO_CLOCK_INFO;
+
+/// Non clock info
+typedef struct _ATOM_PPLIB_NONCLOCK_INFO {
+  USHORT                      usClassification;             ///< State classification see ATOM_PPLIB_CLASSIFICATION_*
+  UCHAR                       ucMinTemperature;             ///< Reserved
+  UCHAR                       ucMaxTemperature;             ///< Reserved
+  ULONG                       ulCapsAndSettings;            ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0)
+  UCHAR                       ucRequiredPower;              ///< Reserved
+  USHORT                      usClassification2;            ///< Reserved
+  ULONG                       ulVCLK;                       ///< UVD clocks VCLK unit is in 10KHz
+  ULONG                       ulDCLK;                       ///< UVD clocks DCLK unit is in 10KHz
+  UCHAR                       ucUnused[5];                  ///< Reserved
+} ATOM_PPLIB_NONCLOCK_INFO;
+
+/// Thermal controller info stub
+typedef struct _ATOM_PPLIB_THERMALCONTROLLER {
+  UCHAR                       ucType;                       ///< Reserved. Should be set 0xE
+  UCHAR                       ucI2cLine;                    ///< Reserved. Should be set 0
+  UCHAR                       ucI2cAddress;                 ///< Reserved. Should be set 0
+  UCHAR                       ucFanParameters;              ///< Reserved. Should be set 0x80
+  UCHAR                       ucFanMinRPM;                  ///< Reserved. Should be set 0
+  UCHAR                       ucFanMaxRPM;                  ///< Reserved. Should be set 0
+  UCHAR                       ucReserved;                   ///< Reserved. Should be set 0
+  UCHAR                       ucFlags;                      ///< Reserved. Should be set 0
+} ATOM_PPLIB_THERMALCONTROLLER;
+
+/// SW state info
+typedef struct _ATOM_PPLIB_STATE_V2 {
+  UCHAR                       ucNumDPMLevels;               ///< Number of valid DPM levels in this state
+  UCHAR                       nonClockInfoIndex;            ///< Index to the array of NonClockInfos
+  UCHAR                       ClockInfoIndex[1];            ///< Array of DPM states. Actual number calculated during state enumeration
+} ATOM_PPLIB_STATE_V2;
+
+/// SW state Array
+typedef struct {
+  UCHAR                       ucNumEntries;                 ///< Number of SW states
+  ATOM_PPLIB_STATE_V2         States[1];                    ///< SW state info. Actual number calculated during state enumeration
+} STATE_ARRAY;
+
+/// Clock info Array
+typedef struct {
+  UCHAR                       ucNumEntries;                 ///< Number of ClockInfo entries
+  UCHAR                       ucEntrySize;                  ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO
+  ATOM_PPLIB_SUMO_CLOCK_INFO  ClockInfo[1];                 ///< Clock info array. Size will be determined dynamically base on fuses
+} CLOCK_INFO_ARRAY;
+
+/// Non clock info Array
+typedef struct {
+
+  UCHAR                       ucNumEntries;                 ///< Number of Entries;
+  UCHAR                       ucEntrySize;                  ///< Size of NonClockInfo
+  ATOM_PPLIB_NONCLOCK_INFO    NonClockInfo[1];              ///< Non clock info array
+} NON_CLOCK_INFO_ARRAY;
+
+/// VCE clock info
+typedef struct {
+  USHORT                    usEVClkLow;                   ///< EVCLK low
+  UCHAR                     ucEVClkHigh;                  ///< EVCLK high
+  USHORT                    usECClkLow;                   ///< ECCLK low
+  UCHAR                     ucECClkHigh;                  ///< ECCLK high
+} VCECLOCKINFO;
+
+/// VCE clock info array
+typedef struct {
+  UCHAR                     ucNumEntries;                ///< Number of entries
+  VCECLOCKINFO              entries[1];                  ///< VCE clock arrau
+} VCECLOCKINFOARRAY;
+
+/// VCE voltage limit record
+typedef struct {
+  USHORT                    usVoltage;                    ///< Voltage index
+  UCHAR                     ucVCEClockInfoIndex;          ///< Index of VCE clock state
+} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD;
+
+/// VCE voltage limit table
+typedef struct {
+  UCHAR                                     numEntries;   ///< Number of entries
+  ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD entries[1];   ///< Coltage limit state array
+} ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE;
+
+/// VCE state record
+typedef struct {
+  UCHAR                     ucVCEClockInfoIndex;          ///< Index of VCE clock state
+  UCHAR                     ucClockInfoIndex;             ///< Index of SCLK clock state
+} ATOM_PPLIB_VCE_STATE_RECORD;
+
+/// VCE state table
+typedef struct {
+  UCHAR                       numEntries;                 ///< Number of state entries
+  ATOM_PPLIB_VCE_STATE_RECORD entries[1];                 ///< State entries
+} ATOM_PPLIB_VCE_STATE_TABLE;
+
+/// Extended header
+typedef struct {
+  USHORT                      usSize;                     ///< size of header
+  ULONG                       rsv15;                      ///< reserved
+  ULONG                       rsv16;                      ///< reserved
+  USHORT                      usVCETableOffset;           ///< offset of ATOM_PPLIB_VCE_TABLE
+} ATOM_PPLIB_EXTENDEDHEADER;
+
+/// VCE table
+typedef struct {
+  UCHAR                       revid;                      ///< revision ID
+} ATOM_PPLIB_VCE_TABLE;
+
+/// Power Play table
+typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 {
+  ATOM_COMMON_TABLE_HEADER      sHeader;                    ///< Common header
+  UCHAR                         ucDataRevision;             ///< Revision of PP table
+  UCHAR                         Reserved1[4];               ///< Reserved
+  USHORT                        usStateArrayOffset;         ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
+  USHORT                        usClockInfoArrayOffset;     ///< Offset from start of the table to ClockInfoArray
+  USHORT                        usNonClockInfoArrayOffset;  ///< Offset from Start of the table to NonClockInfoArray
+  USHORT                        Reserved2[2];               ///< Reserved
+  USHORT                        usTableSize;                ///< the size of this structure, or the extended structure
+  ULONG                         ulPlatformCaps;             ///< See ATOM_PPLIB_CAPS_*
+  ATOM_PPLIB_THERMALCONTROLLER  sThermalController;         ///< Thermal controller stub.
+  USHORT                        Reserved4[2];               ///< Reserved
+  UCHAR                         Reserved5;                  ///< Reserved
+  USHORT                        Reserved6;                  ///< Reserved
+  USHORT                        usFormatID;                 ///< Format ID
+  USHORT                        Reserved7[1];               ///< Reserved
+  USHORT                        usExtendendedHeaderOffset;  ///< Extended header offset
+} ATOM_PPLIB_POWERPLAYTABLE3;
+
+#pragma pack (pop)
+
+
+AGESA_STATUS
+GfxPowerPlayBuildTable (
+     OUT  VOID                          *Buffer,
+  IN      GFX_PLATFORM_CONFIG           *Gfx
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
new file mode 100644
index 0000000000..a01e6e7790
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c
@@ -0,0 +1,225 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Supporting services to collect discrete GFX card info
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GfxCardInfo.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if GFX controller fused off
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    TRUE            Gfx controller present and available
+ */
+BOOLEAN
+GfxLibIsControllerPresent (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Gfx SSID Registers
+ *
+ *
+ *
+ * @param[in] Gfx           Pointer to global GFX configuration
+ * @retval    AGESA_STATUS  Always succeeds
+ */
+
+AGESA_STATUS
+GfxInitSsid (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  AGESA_STATUS    Status;
+  UINT32          TempData;
+  PCI_ADDR        IgpuAddress;
+  PCI_ADDR        HdaudioAddress;
+
+  Status = AGESA_SUCCESS;
+  TempData = 0;
+
+  IgpuAddress = Gfx->GfxPciAddress;
+  HdaudioAddress = Gfx->GfxPciAddress;
+  HdaudioAddress.Address.Function = 1;
+
+  // Set SSID for internal GPU
+  if (UserOptions.CfgGnbIGPUSSID != 0) {
+    GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx));
+  } else {
+    GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx));
+    GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx));
+  }
+
+  // Set SSID for internal HD Audio
+  if (UserOptions.CfgGnbHDAudioSSID != 0) {
+    GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx));
+  } else {
+    GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx));
+    GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx));
+  }
+
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy memory content to FB
+ *
+ *
+ * @param[in] Source       Pointer to source
+ * @param[in] FbOffset     FB offset
+ * @param[in] Length       The length to copy
+ * @param[in] Gfx          Pointer to global GFX configuration
+ *
+ */
+VOID
+GfxLibCopyMemToFb (
+  IN     VOID                   *Source,
+  IN     UINT32                  FbOffset,
+  IN     UINT32                  Length,
+  IN     GFX_PLATFORM_CONFIG    *Gfx
+  )
+{
+  GMMx00_STRUCT GMMx00;
+  GMMx04_STRUCT GMMx04;
+  UINT32        Index;
+  for (Index = 0; Index < Length; Index = Index + 4 ) {
+    GMMx00.Value = 0x80000000 | (FbOffset + Index);
+    GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index);
+    GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &GMMx00.Value, GnbLibGetHeader (Gfx));
+    GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, &GMMx04.Value, GnbLibGetHeader (Gfx));
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set iGpu VGA mode
+ *
+ *
+ * @param[in] Gfx          Pointer to global GFX configuration
+ *
+ */
+VOID
+GfxLibSetiGpuVgaMode (
+  IN     GFX_PLATFORM_CONFIG    *Gfx
+  )
+{
+  GnbLibPciIndirectRMW (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32) ~D0F0x64_x1D_VgaEn_MASK,
+    ((Gfx->iGpuVgaMode == iGpuVgaAdapter) ? 1 : 0) << D0F0x64_x1D_VgaEn_OFFSET,
+    GnbLibGetHeader (Gfx)
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h
new file mode 100644
index 0000000000..eb68a44d85
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Gfx Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+#ifndef _GNBGFXINITLIBV1_H_
+#define _GNBGFXINITLIBV1_H_
+
+#include "GnbPcie.h"
+#include "GnbGfx.h"
+#include "GfxEnumConnectors.h"
+#include "GfxPowerPlayTable.h"
+#include "GfxCardInfo.h"
+
+BOOLEAN
+GfxLibIsControllerPresent (
+  IN      AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+AGESA_STATUS
+GfxInitSsid (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+
+VOID
+GfxLibCopyMemToFb (
+  IN     VOID                         *Source,
+  IN     UINT32                       FbOffset,
+  IN     UINT32                       Length,
+  IN     GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+VOID
+GfxLibSetiGpuVgaMode (
+  IN     GFX_PLATFORM_CONFIG          *Gfx
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
new file mode 100644
index 0000000000..037eadd02a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
@@ -0,0 +1,493 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbHandleLib.h"
+#include  "GnbTimerLib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA      GfxEnvInitTableTN[];
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Shut Down Disabled SIMDs
+ *
+ * @param[in] Property        GNB property
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxShutDownDisabledSimdsTN (
+  IN      UINT32                Property,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1006_STRUCT  ex1006 ;
+  ex1009_STRUCT   ex1009;
+  D0F0xBC_xE03002F8_STRUCT  D0F0xBC_xE03002F8;
+  D0F0xBC_xE03002FC_STRUCT  D0F0xBC_xE03002FC;
+  D0F0xBC_xE0300054_STRUCT  GfxChainPgfsmConfig;
+  UINT8                     n;
+  UINT32                    Mask;
+  CPU_LOGICAL_ID            LogicalId;
+  GNB_HANDLE                *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Enter\n");
+
+  GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Gfx));
+
+  GfxChainPgfsmConfig.Value = 0;
+  GfxChainPgfsmConfig.Field.PowerDown = 1;
+  GfxChainPgfsmConfig.Field.P2Select = 1;
+  GfxChainPgfsmConfig.Field.FsmAddr = 0xFF;
+
+  //Step 1: Read fuse to see which SIMD(s) have been disabled
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx));
+
+  //Step 2: Check which SIMD has been disabled
+  for (n = 0; n < 6; n++) {
+    if (((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) || ((ex1006.Field.ex1006_0  >> n) & 0x1)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Disable SIMD %d\n", n);
+      //Step 3: Make sure PGFSM has been programmed in GFX Power Island.
+      //Step 4: Make sure SCLK frequency is below 400Mhz
+      //Step 5: Enable PGFSM clock
+      GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+      ex1009.Value |= (0x1 << (0  + n));
+      GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+      //Step 6
+      GnbRegisterWriteTN (TYPE_D0F0xBC, (D0F0xBC_xE0300054_ADDRESS + (n * 0x1C)), &GfxChainPgfsmConfig.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+      //Step 7
+      Mask = (UINT32) (0x1F << (n * 5));
+      do {
+        GnbRegisterReadTN (D0F0xBC_xE03002F8_TYPE, D0F0xBC_xE03002F8_ADDRESS, &D0F0xBC_xE03002F8.Value, 0, GnbLibGetHeader (Gfx));
+      } while ((D0F0xBC_xE03002F8.Value & Mask )!= 0);
+      //Step 8: Restore previous SCLK divider
+      if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
+        do {
+          GnbRegisterReadTN (D0F0xBC_xE03002FC_TYPE, D0F0xBC_xE03002FC_ADDRESS, &D0F0xBC_xE03002FC.Value, 0, GnbLibGetHeader (Gfx));
+        } while ((D0F0xBC_xE03002FC.Value & Mask )!= Mask);
+      } else {
+      }
+      //Step 10: Turn off PGFSM clock
+      GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+      ex1009.Value &= (~ (UINT64) (0x1 << (0  + n)));
+      GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Shut Down Disabled SIMDs
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxShutDownDisabledRbsTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1006_STRUCT  ex1006 ;
+  D0F0xBC_xE0003024_STRUCT  D0F0xBC_xE0003024;
+  D0F0xBC_xE03000FC_STRUCT  D0F0xBC_xE03000FC;
+  D0F0xBC_xE0300100_STRUCT  D0F0xBC_xE0300100;
+  ex1009_STRUCT   ex1009 ;
+  D0F0xBC_xE03002F4_STRUCT  D0F0xBC_xE03002F4;
+  D0F0xBC_xE03002E4_STRUCT  D0F0xBC_xE03002E4;
+  UINT8                     i;
+  UINT8                     RbNumber;
+  UINT32                    Mask1;
+  UINT32                    Mask2;
+
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.WriteOp = 1;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Enter\n");
+
+  //Step 1: Read fuse to see which SIMD(s) have been disabled
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx));
+
+  //Step 2: Power down disabled RB
+  if (ex1006.Field.ex1006_1  == 0x1) {
+    RbNumber = 0;
+    Mask1 = 0x3FFFA;
+    Mask2 = 0x5;
+  } else if (ex1006.Field.ex1006_1  == 0x2) {
+    RbNumber = 1;
+    Mask1 = 0x3FFF5;
+    Mask2 = 0xA;
+  } else {
+    return AGESA_SUCCESS;
+  }
+  //Step 3: Enable PGFSM commands during reset
+  GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE0003024.Value |= 0x1;
+  GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 4: Make sure PGFSM has been programmed before sending power down command.
+  //CB0 = 0, DB0 = 2, CB1 = 1, DB1 = 3
+  for (i = RbNumber; i < 4; i += 2) {
+    D0F0xBC_xE0300100.Value = (5 << 16 ) | (4 << 8 ) | (10 << 0 ); //reg0
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.FsmAddr = i;
+    D0F0xBC_xE03000FC.Field.RegAddr = 2 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+    D0F0xBC_xE0300100.Value = (50 << 0 ) | (50 << 12 ); //reg1
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.RegAddr = 3 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+    D0F0xBC_xE0300100.Value = 0; //control
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.RegAddr = 1 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+  }
+  //Step 5: Make sure SCLK frequency is below 400Mhz
+  //Step 6: Enable PGFSM clock
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+  ex1009.Field.ex1009_1  = 1;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 7
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.PowerDown = 1;
+  D0F0xBC_xE03000FC.Field.P1Select = 1;
+  D0F0xBC_xE03000FC.Field.P2Select = 1;
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 8
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 9: Wait for isolation to be asserted for RB0/RB1
+  do {
+    GnbRegisterReadTN (D0F0xBC_xE03002F4_TYPE, D0F0xBC_xE03002F4_ADDRESS, &D0F0xBC_xE03002F4.Value, 0, GnbLibGetHeader (Gfx));
+  } while ((D0F0xBC_xE03002F4.Value & Mask1 )!= 0);
+  //Step 10: Restore previous SCLK divider
+  //Step 11: Wait for PSO daughter to be asserted for RB0/RB1
+  do {
+    GnbRegisterReadTN (D0F0xBC_xE03002E4_TYPE, D0F0xBC_xE03002E4_ADDRESS, &D0F0xBC_xE03002E4.Value, 0, GnbLibGetHeader (Gfx));
+  } while ((D0F0xBC_xE03002E4.Value & Mask2 )!= Mask2);
+
+  //Step 12: Set PGFSM power up override bits so SMU will not power up disabled RB
+  D0F0xBC_xE0300100.Value = 0x3 << 11;
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.RegAddr = 1 ;
+  GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 13: Turn off PGFSM clock
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+  ex1009.Field.ex1009_1  = 1;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 14: Disable PGFSM commands during reset
+  GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE0003024.Value &= 0xFFFFFFFE;
+  GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Exit\n");
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GFX straps.
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxEnvInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D0F0x64_x1C_STRUCT  D0F0x64_x1C;
+  D0F0x64_x1D_STRUCT  D0F0x64_x1D;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Enter\n");
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0;
+  D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0;
+
+  D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1;
+  D0F0x64_x1C.Field.RcieEn = 0x1;
+
+  D0F0x64_x1D.Field.VgaEn = 0x1;
+
+  D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio;
+  D0F0x64_x1C.Field.F0En = 0x1;
+  D0F0x64_x1C.Field.RegApSize = 0x1;
+
+  if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x1;
+  } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x0;
+  } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x2;
+  } else {
+    D0F0x64_x1C.Field.MemApSize = 0x3;
+  }
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.WriteDis = 0x1;
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Exit\n");
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Env Post.
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS
+  */
+
+
+AGESA_STATUS
+GfxEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  GNB_HANDLE            *GnbHandle;
+  UINT32                Property;
+  BOOLEAN               ShutDownDisabledSimd;
+  BOOLEAN               ShutDownDisabledRb;
+  UINT8                 SclkDid;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Property = TABLE_PROPERTY_DEAFULT;
+  ShutDownDisabledSimd = GnbBuildOptions.CfgUnusedSimdPowerGatingEnable;
+  ShutDownDisabledRb = GnbBuildOptions.CfgUnusedRbPowerGatingEnable;
+
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnvInitTN (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      ASSERT (Status == AGESA_SUCCESS);
+    } else {
+      GfxFmDisableController (StdHeader);
+      Property |= TABLE_PROPERTY_IGFX_DISABLED;
+    }
+  } else {
+    GfxFmDisableController (StdHeader);
+    Property |= TABLE_PROPERTY_IGFX_DISABLED;
+  }
+  //
+  // Set sclk to 100Mhz
+  //
+  SclkDid = GfxRequestSclkTNS3Save (
+              GfxLibCalculateDidTN (98 * 100, StdHeader),
+              StdHeader
+              );
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GfxEnvInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  if (ShutDownDisabledSimd == TRUE) {
+    GfxShutDownDisabledSimdsTN (Property, Gfx);
+  }
+
+  if ((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) {
+    if (ShutDownDisabledRb == TRUE) {
+      GfxShutDownDisabledRbsTN (Gfx);
+    }
+  }
+  //
+  // Restore Sclk
+  //
+  GfxRequestSclkTNS3Save (
+    SclkDid,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
new file mode 100644
index 0000000000..1cd96d3d83
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
@@ -0,0 +1,595 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64152 $   @e \$Date: 2012-01-16 21:38:07 -0600 (Mon, 16 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbRegisterAccTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbRegistersTN.h"
+#include  "GfxLibTN.h"
+#include  "GfxGmcInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [];
+extern GNB_TABLE ROMDATA GfxGmcInitTableTN [];
+extern GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [];
+
+
+#define GNB_GFX_DRAM_CH_0_PRESENT 1
+#define GNB_GFX_DRAM_CH_1_PRESENT 2
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+DCT_REGISTER_ENTRY DctRegisterTable [] = {
+  {
+    TYPE_D18F2_dct0,
+    D18F2x94_dct0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct0)
+  },
+  {
+    TYPE_D18F2_dct1,
+    D18F2x94_dct1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct1)
+  },
+  {
+    TYPE_D18F2_dct0,
+    D18F2x2E0_dct0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct0)
+  },
+  {
+    TYPE_D18F2_dct1,
+    D18F2x2E0_dct1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x200_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x200_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x200_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x200_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x204_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x204_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x204_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x204_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x22C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x22C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x22C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x22C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x21C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x21C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x21C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x21C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x20C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x20C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x20C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x20C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp1)
+  }
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Fb location
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeFbLocationTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx2024_STRUCT   GMMx2024;
+  GMMx2068_STRUCT   GMMx2068;
+  GMMx2C04_STRUCT   GMMx2C04;
+  GMMx5428_STRUCT   GMMx5428;
+  UINT64            FBBase;
+  UINT64            FBTop;
+  FBBase = 0x0F00000000;
+  FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1;
+  GMMx2024.Value = 0;
+  GMMx2C04.Value = 0;
+  GMMx2024.Field.FB_BASE = (UINT16) (FBBase >> 24);
+  GMMx2024.Field.FB_TOP = (UINT16) (FBTop >> 24);
+  GMMx2068.Field.FB_OFFSET = (UINT32) (Gfx->UmaInfo.UmaBase >> 22);
+  GMMx2C04.Field.NONSURF_BASE = (UINT32) (FBBase >> 8);
+  GMMx5428.Field.CONFIG_MEMSIZE = Gfx->UmaInfo.UmaSize >> 20;
+  GnbRegisterWriteTN (GMMx2024_TYPE, GMMx2024_ADDRESS, &GMMx2024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx2068_TYPE, GMMx2068_ADDRESS, &GMMx2068.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx2C04_TYPE, GMMx2C04_ADDRESS, &GMMx2C04.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Sequencer model info
+ *
+ *
+ * @param[out] DctChannelInfo  Various DCT/GMM info
+ * @param[in]  Gfx             Pointer to global GFX configuration
+ */
+
+STATIC VOID
+GfxGmcDctMemoryChannelInfoTN (
+     OUT   DCT_CHANNEL_INFO              *DctChannelInfo,
+  IN       GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+
+  UINT32       Index;
+  UINT32       Value;
+
+  for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) {
+    GnbRegisterReadTN (
+      DctRegisterTable[Index].RegisterSpaceType,
+      DctRegisterTable[Index].Address,
+      &Value,
+      0,
+      GnbLibGetHeader (Gfx)
+    );
+    *(UINT32 *)((UINT8 *) DctChannelInfo + DctRegisterTable[Index].DctChannelInfoTableOffset) = Value;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize sequencer model
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeSequencerTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+
+  UINT32                    memps0_freq;
+  UINT32                    memps1_freq;
+  UINT32                    scale_mp0;
+  UINT32                    scale_mp1;
+  UINT8                     DramChannelPresent;
+  ex1047_STRUCT      ex1047      ;
+  ex1048_STRUCT          ex1048 ;
+  ex1060_STRUCT        ex1060    ;
+  ex1061_STRUCT        ex1061    ;
+  ex1062_STRUCT        ex1062    ;
+  DCT_CHANNEL_INFO          DctChannel;
+  D18F5x170_STRUCT          D18F5x170;
+  ex1012_STRUCT         ex1012  ;
+  ex1034_STRUCT        ex1034    ;
+
+  GfxGmcDctMemoryChannelInfoTN (&DctChannel, Gfx);
+
+  DramChannelPresent = 0;
+  if (!DctChannel.D18F2x94_dct1.Field.DisDramInterface) {
+    DramChannelPresent |= GNB_GFX_DRAM_CH_1_PRESENT;
+  }
+
+  if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface) {
+    //if (channel 0 present)
+    //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[0]>[4:0] encoding
+    //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[0]>[28:24] encoding
+    DramChannelPresent |= GNB_GFX_DRAM_CH_0_PRESENT;
+    memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct0.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+    memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+  } else {
+    //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[1]>[4:0] encoding
+    //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[1]>[28:24] encoding
+    memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct1.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+    memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct1.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+  }
+
+  GnbRegisterReadTN (D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx));
+  if (D18F5x170.Field.MemPstateDis == 1) {
+    memps1_freq = memps0_freq;
+  }
+
+  //scale_mp0 = sclk_max_freq / memps0_freq
+  //scale_mp1 = sclk_max_freq / memps1_freq
+  //Multiply it by 100 to avoid dealing with floating point values
+  scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq;
+  scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq;
+
+  GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x27f0 , &ex1060.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx));
+
+  if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
+    ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd),
+                                     (DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp),
+                                    (DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO),
+                                     (DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd),
+                                     (DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp),
+                                    (DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO),
+                                     (DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100;
+
+  } else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) {
+    ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct0_mp0.Field.Trcd * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct0_mp0.Field.Trc * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct0_mp0.Field.Trp * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct0_mp1.Field.Trcd * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct0_mp1.Field.Trc * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct0_mp1.Field.Trp * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100;
+
+  } else {
+    ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct1_mp0.Field.Trcd * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct1_mp0.Field.Trc * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct1_mp0.Field.Trp * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct1_mp1.Field.Trcd * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct1_mp1.Field.Trc * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct1_mp1.Field.Trp * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100;
+  }
+
+  GnbRegisterWriteTN (TYPE_GMM , 0x2774 , &ex1047.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2778 , &ex1048.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x27f0 , &ex1060.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x27fc , &ex1061.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  ex1062.Field.ex1062_0  = GfxLibGetNumberOfSclkPerDramBurst (scale_mp0, GnbLibGetHeader (Gfx));
+  ex1062.Field.ex1062_1  = GfxLibGetNumberOfSclkPerDramBurst (scale_mp1, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2808 , &ex1062.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+
+  //MC Performance settings base on memory channel configuration
+  //If 1 channel
+  ex1012.Value = 0x210;
+  ex1034.Value = 0x3;
+  if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
+    //If 2 channels
+    ex1012.Value = 0x1210;
+    ex1034.Value = 0xC3;
+  }
+  GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+STATIC VOID
+GfxGmcSecureGarlicAccessTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1064_STRUCT    ex1064 ;
+  ex1065_STRUCT    ex1065 ;
+  GMMx287C_STRUCT   GMMx287C;
+
+  ex1064.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
+  GnbRegisterWriteTN (TYPE_GMM , 0x2868 , &ex1064.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  ex1065.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1);
+  GnbRegisterWriteTN (TYPE_GMM , 0x286c , &ex1065.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  // Areag FB - 32K reserved by VBIOS for SBIOS to use
+  GMMx287C.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12);
+  GnbRegisterWriteTN (GMMx287C_TYPE, GMMx287C_ADDRESS, &GMMx287C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize C6 aperture location
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeC6LocationTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D18F2x118_STRUCT    D18F2x118;
+  D18F1x44_STRUCT     D18F1x44;
+  GMMx2870_STRUCT     GMMx2870;
+  GMMx2874_STRUCT     GMMx2874;
+
+  // From D18F1x[144:140,44:40] DRAM Base/Limit,
+  // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}.
+  GnbRegisterReadTN (D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx));
+  //
+  // base 39:20, base = Dram Limit + 1
+  // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1)
+  // Node DRAM     D18F1x[144:140,44:40]    CC6DRAMRange         D18F4x128   D18F1x120 D18F1x124
+  //    0 256MB    0MB ~ 240 MB - 1        240 MB ~ 256 MB - 1     0           0 MB,    256 MB - 1
+  //
+
+  // base 39:20
+  GMMx2870.Value = ((D18F1x44.Field.DramLimit_39_24_ + 1) << 4);
+  // top 39:20
+  GMMx2874.Value = (((D18F1x44.Field.DramLimit_39_24_ + 1) << 24) + (16 * 0x100000) - 1) >> 20;
+
+  // Check C6 enable,  D18F2x118[CC6SaveEn]
+  GnbRegisterReadTN (TYPE_D18F2 , 0x118 , &D18F2x118.Value, 0, GnbLibGetHeader (Gfx));
+
+  if (D18F2x118.Field.CC6SaveEn) {
+
+    GnbRegisterWriteTN (GMMx2874_TYPE, GMMx2874_ADDRESS, &GMMx2874.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbRegisterWriteTN (GMMx2870_TYPE, GMMx2870_ADDRESS, &GMMx2870.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GMC
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+
+AGESA_STATUS
+GfxGmcInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx28D8_STRUCT   GMMx28D8;
+  ex1017_STRUCT    ex1017 ;
+  GNB_HANDLE        *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Enter\n");
+   GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
+   ASSERT (GnbHandle != NULL);
+   GnbProcessTable (
+     GnbHandle,
+     GfxGmcColockGatingDisableTN,
+     0,
+     GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+     GnbLibGetHeader (Gfx)
+     );
+   GfxGmcInitializeSequencerTN (Gfx);
+   GfxGmcInitializeFbLocationTN (Gfx);
+   GfxGmcSecureGarlicAccessTN (Gfx);
+   GfxGmcInitializeC6LocationTN (Gfx);
+   GnbProcessTable (
+     GnbHandle,
+     GfxGmcInitTableTN,
+     0,
+     GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+     GnbLibGetHeader (Gfx)
+     );
+   if (Gfx->GmcClockGating) {
+     GnbProcessTable (
+       GnbHandle,
+       GfxGmcColockGatingEnableTN,
+       0,
+       GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+       GnbLibGetHeader (Gfx)
+       );
+   }
+   if (Gfx->UmaSteering == excel993 ) {
+     ex1017.Value = 0x2;
+     GnbRegisterWriteTN (TYPE_GMM , 0x206c , &ex1017.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+   }
+   IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx));
+   if (Gfx->GmcLockRegisters) {
+     GnbRegisterReadTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, 0, GnbLibGetHeader (Gfx));
+     GMMx28D8.Field.CRITICAL_REGS_LOCK = 1;
+     GnbRegisterWriteTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+   }
+   if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) {
+   }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Exit\n");
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h
new file mode 100644
index 0000000000..91de2f7475
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXGMCINITTN_H_
+#define _GFXGMCINITTN_H_
+
+#include  "GnbRegistersTN.h"
+
+AGESA_STATUS
+GfxGmcInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+#pragma pack (push, 1)
+
+/// DCT channel information
+typedef struct {
+  D18F2x94_dct0_STRUCT      D18F2x94_dct0;       ///< Register 0x94
+  D18F2x94_dct1_STRUCT      D18F2x94_dct1;       ///< Register 0x94
+  D18F2x2E0_dct0_STRUCT     D18F2x2E0_dct0;      ///< Register 0x2E0
+  D18F2x2E0_dct1_STRUCT     D18F2x2E0_dct1;      ///< Register 0x2E0
+  D18F2x200_dct0_mp0_STRUCT D18F2x200_dct0_mp0;  ///< Register 0x200
+  D18F2x200_dct0_mp1_STRUCT D18F2x200_dct0_mp1;  ///< Register 0x200
+  D18F2x200_dct1_mp0_STRUCT D18F2x200_dct1_mp0;  ///< Register 0x200
+  D18F2x200_dct1_mp1_STRUCT D18F2x200_dct1_mp1;  ///< Register 0x200
+  D18F2x204_dct0_mp0_STRUCT D18F2x204_dct0_mp0;  ///< Register 0x204
+  D18F2x204_dct0_mp1_STRUCT D18F2x204_dct0_mp1;  ///< Register 0x204
+  D18F2x204_dct1_mp0_STRUCT D18F2x204_dct1_mp0;  ///< Register 0x204
+  D18F2x204_dct1_mp1_STRUCT D18F2x204_dct1_mp1;  ///< Register 0x204
+  D18F2x22C_dct0_mp0_STRUCT D18F2x22C_dct0_mp0;  ///< Register 0x22C
+  D18F2x22C_dct0_mp1_STRUCT D18F2x22C_dct0_mp1;  ///< Register 0x22C
+  D18F2x22C_dct1_mp0_STRUCT D18F2x22C_dct1_mp0;  ///< Register 0x22C
+  D18F2x22C_dct1_mp1_STRUCT D18F2x22C_dct1_mp1;  ///< Register 0x22C
+  D18F2x21C_dct0_mp0_STRUCT D18F2x21C_dct0_mp0;  ///< Register 0x21C
+  D18F2x21C_dct0_mp1_STRUCT D18F2x21C_dct0_mp1;  ///< Register 0x21C
+  D18F2x21C_dct1_mp0_STRUCT D18F2x21C_dct1_mp0;  ///< Register 0x21C
+  D18F2x21C_dct1_mp1_STRUCT D18F2x21C_dct1_mp1;  ///< Register 0x21C
+  D18F2x20C_dct0_mp0_STRUCT D18F2x20C_dct0_mp0;  ///< Register 0x20C
+  D18F2x20C_dct0_mp1_STRUCT D18F2x20C_dct0_mp1;  ///< Register 0x20C
+  D18F2x20C_dct1_mp0_STRUCT D18F2x20C_dct1_mp0;  ///< Register 0x20C
+  D18F2x20C_dct1_mp1_STRUCT D18F2x20C_dct1_mp1;  ///< Register 0x20C
+} DCT_CHANNEL_INFO;
+
+/// DCT_CHANNEL_INFO field entry
+typedef struct {
+  UINT8                 RegisterSpaceType;              ///< Register type
+  UINT32                Address;                        ///< Register address
+  UINT16                DctChannelInfoTableOffset;      ///< destination offset in DCT_CHANNEL_INFO table
+} DCT_REGISTER_ENTRY;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
new file mode 100644
index 0000000000..15c0109566
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
@@ -0,0 +1,922 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64730 $   @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "GeneralServices.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GfxConfigLib.h"
+#include  "GfxLibTN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#define GFX_REFCLK                        100     // (in MHz) Reference clock is 100 MHz
+#define GFX_NCLK_MIN                      700     // (in MHz) Minimum value for NCLK is 700 MHz
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxIntInfoTableInterfaceTN (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+CONST UINT8  DdiLaneConfigArrayTN [][4] = {
+  {31, 24, 1, 0},
+  {24, 31, 0, 1},
+  {24, 27, 0, 0},
+  {27, 24, 0, 0},
+  {28, 31, 1, 1},
+  {31, 28, 1, 1},
+  {32, 38, 2, 2},
+  {32, 35, 2, 2},
+  {35, 32, 2, 2},
+  {8 , 15, 3, 3},
+  {15, 8 , 3, 3},
+  {12, 15, 3, 3},
+  {15, 12, 3, 3},
+  {16, 19, 4, 4},
+  {19, 16, 4, 4},
+  {16, 23, 4, 5},
+  {23, 16, 5, 4},
+  {20, 23, 5, 5},
+  {23, 20, 5, 5},
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init TN Support for eDP to Lvds translators
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegrateducEDPToLVDSRxIdCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8    *uceDPToLVDSRxId;
+  uceDPToLVDSRxId = (UINT8*) Buffer;
+  // APU output DP signal to a 3rd party DP translator chip (Analogix, Parade etc),
+  // the chip is handled by the 3rd party DP Rx firmware and it does not require the AMD SW to have a special
+  // initialize/enable/disable sequence to control this chip, the AMD SW just follows the eDP spec
+  // to enable the LVDS panel through this chip.
+
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) {
+    *uceDPToLVDSRxId = eDP_TO_LVDS_COMMON_ID;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found 3rd party common EDPToLvds Connector\n");
+  }
+  // APU output DP signal to a 3rd party DP translator chip which requires a AMD SW one time initialization
+  // to the chip based on the LVDS panel parameters ( such as power sequence time and panel SS parameter etc ).
+  // After that, the AMD SW does not need any specific enable/disable sequences to control this chip and just
+  // follows the eDP spec. to control the panel.
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) {
+    *uceDPToLVDSRxId = eDP_TO_LVDS_REALTEK_ID;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found Realtec EDPToLvds Connector\n");
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN Nb p-State MemclkFreq
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillNbPstateMemclkFreqTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F2x94_dct0_STRUCT            D18F2x94;
+  D18F2x2E0_dct0_STRUCT           D18F2x2E0;
+  D18F5x160_STRUCT                NbPstate;
+  UINT8                           i;
+  UINT8                           Channel;
+  ULONG                           memps0_freq;
+  ULONG                           memps1_freq;
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x94_dct0_TYPE : D18F2x94_dct1_TYPE),
+    ((Channel == 0) ? D18F2x94_dct0_ADDRESS : D18F2x94_dct1_ADDRESS),
+    &D18F2x94.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x2E0_dct0_TYPE : D18F2x2E0_dct1_TYPE),
+    ((Channel == 0) ? D18F2x2E0_dct0_ADDRESS : D18F2x2E0_dct1_ADDRESS),
+    &D18F2x2E0.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  memps0_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+  memps1_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+
+  for (i = 0; i < 4; i++) {
+    NbPstate.Value = 0;
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      (D18F5x160_ADDRESS + (i * 4)),
+      &NbPstate.Value,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    if (NbPstate.Field.NbPstateEn == 1) {
+      IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq;
+    }
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN HTC Data
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillHtcDataTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F3x64_STRUCT  D18F3x64;
+
+  GnbRegisterReadTN (
+    D18F3x64_TYPE,
+    D18F3x64_ADDRESS,
+    &D18F3x64.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  if (D18F3x64.Field.HtcEn == 1) {
+    IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
+    IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
+  } else {
+    IntegratedInfoTable->ucHtcTmpLmt = 0;
+    IntegratedInfoTable->ucHtcHystLmt = 0;
+  }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get TN CSR phy self refresh power down mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    CsrPhySrPllPdMode
+ */
+STATIC UINT32
+GfxLibGetMemPhyPllPdModeTN (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2xA8_dct0_STRUCT     D18F2xA8;
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2xA8_dct0_TYPE : D18F2xA8_dct1_TYPE),
+    ((Channel == 0) ? D18F2xA8_dct0_ADDRESS : D18F2xA8_dct1_ADDRESS),
+    &D18F2xA8.Value,
+    0,
+    StdHeader
+  );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "MemPhyPllPdMode : %x\n", D18F2xA8.Field.MemPhyPllPdMode);
+  return  D18F2xA8.Field.MemPhyPllPdMode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get TN disable DLL shutdown in self-refresh mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    DisDllShutdownSR
+ */
+STATIC UINT32
+GfxLibGetDisDllShutdownSRTN (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2x90_dct0_STRUCT D18F2x90;
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x90_dct0_TYPE : D18F2x90_dct1_TYPE),
+    ((Channel == 0) ? D18F2x90_dct0_ADDRESS : D18F2x90_dct1_ADDRESS),
+    &D18F2x90.Value,
+    0,
+    StdHeader
+  );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "DisDllShutdownSR : %x\n", D18F2x90.Field.DisDllShutdownSR);
+  return  D18F2x90.Field.DisDllShutdownSR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN NbPstateVid
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillNbPStateVidTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  //TN Register Mapping for D18F5x1[6C:60]
+  D18F5x160_STRUCT  NbPstate[4];
+  D0F0xBC_x1F428_STRUCT  D0F0xBC_x1F428;
+  UINT8             MinNclkIndex;
+  UINT8             i;
+
+  MinNclkIndex = 0;
+  IntegratedInfoTable->ucNBDPMEnable = 0;
+
+
+  GnbRegisterReadTN (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    &D0F0xBC_x1F428.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+  );
+  // Check if NbPstate enbale
+  if (D0F0xBC_x1F428.Field.EnableNbDpm == 1) {
+    //1: enable 0: not enable
+    IntegratedInfoTable->ucNBDPMEnable = 1;
+  }
+
+  for (i = 0; i < 4; i++) {
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      (D18F5x160_ADDRESS + (i * 4)),
+      &NbPstate[i].Value,
+      0,
+      GnbLibGetHeader (Gfx)
+    );
+    if (NbPstate[i].Field.NbPstateEn == 1) {
+      MinNclkIndex = i;
+    }
+    IntegratedInfoTable->ulNbpStateNClkFreq[i] = GfxLibGetNclkTN ((UINT8) NbPstate[i].Field.NbFid, (UINT8) NbPstate[i].Field.NbDid);
+  }
+  IntegratedInfoTable->usNBP0Voltage = (USHORT) ((NbPstate[0].Field.NbVid_7_ << 7) | NbPstate[0].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP1Voltage = (USHORT) ((NbPstate[1].Field.NbVid_7_ << 7) | NbPstate[1].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP2Voltage = (USHORT) ((NbPstate[2].Field.NbVid_7_ << 7) | NbPstate[2].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP3Voltage = (USHORT) ((NbPstate[3].Field.NbVid_7_ << 7) | NbPstate[3].Field.NbVid_6_0_);
+
+  IntegratedInfoTable->ulMinimumNClk = GfxLibGetNclkTN ((UINT8) NbPstate[MinNclkIndex].Field.NbFid, (UINT8) NbPstate[MinNclkIndex].Field.NbDid);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize display path for given engine
+ *
+ *
+ *
+ * @param[in]   Engine            Engine configuration info
+ * @param[out]  DisplayPathList   Display path list
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ */
+
+AGESA_STATUS
+GfxFmMapEngineToDisplayPath (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  AGESA_STATUS      Status;
+  UINT8             PrimaryDisplayPathId;
+  UINT8             SecondaryDisplayPathId;
+  UINTN             DisplayPathIndex;
+  PrimaryDisplayPathId = 0xff;
+  SecondaryDisplayPathId = 0xff;
+  for (DisplayPathIndex = 0; DisplayPathIndex <  (sizeof (DdiLaneConfigArrayTN) / 4); DisplayPathIndex++) {
+    if (DdiLaneConfigArrayTN[DisplayPathIndex][0] == Engine->EngineData.StartLane &&
+        DdiLaneConfigArrayTN[DisplayPathIndex][1] == Engine->EngineData.EndLane) {
+      PrimaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][2];
+      SecondaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][3];
+      break;
+    }
+  }
+  if (PrimaryDisplayPathId != 0xff) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
+    Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE;
+    GfxIntegratedCopyDisplayInfo (
+      Engine,
+      &DisplayPathList[PrimaryDisplayPathId],
+      (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL,
+      Gfx
+      );
+    Status = AGESA_SUCCESS;
+  } else {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Error!!! Map DDI lanes %d - %d to display path failed\n",
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane
+      );
+    PutEventLog (
+      AGESA_ERROR,
+      GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION,
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane,
+      0,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    Status = AGESA_ERROR;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy memory content to FB
+ *
+ *
+ * @param[in] SystemInfoTableV2Ptr    Pointer to integrated info table
+ * @param[in] Gfx                     Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxIntInfoTabablePostToFb (
+  IN       ATOM_FUSION_SYSTEM_INFO_V2     *SystemInfoTableV2Ptr,
+  IN       GFX_PLATFORM_CONFIG            *Gfx
+  )
+{
+  UINT32      Index;
+  UINT32      TableOffset;
+  UINT32      FbAddress;
+
+  TableOffset = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V2)) | 0x80000000;
+  for (Index = 0; Index < sizeof (ATOM_FUSION_SYSTEM_INFO_V2); Index = Index + 4 ) {
+    FbAddress = TableOffset + Index;
+    GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &FbAddress, GnbLibGetHeader (Gfx));
+    GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, (UINT8*) SystemInfoTableV2Ptr + Index, GnbLibGetHeader (Gfx));
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Dispclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxIntInfoTableInitDispclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN   Index;
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->DisplclkDid[Index] != 0) {
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxFmCalculateClock (
+                                                                             PpFuseArray->DisplclkDid[Index],
+                                                                             GnbLibGetHeader (Gfx)
+                                                                             );
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index;
+    }
+  }
+  IntegratedInfoTable->ucDPMState0VclkFid = PpFuseArray->VclkDid[0];
+  IntegratedInfoTable->ucDPMState1VclkFid = PpFuseArray->VclkDid[1];
+  IntegratedInfoTable->ucDPMState2VclkFid = PpFuseArray->VclkDid[2];
+  IntegratedInfoTable->ucDPMState3VclkFid = PpFuseArray->VclkDid[3];
+  IntegratedInfoTable->ucDPMState0DclkFid = PpFuseArray->DclkDid[0];
+  IntegratedInfoTable->ucDPMState1DclkFid = PpFuseArray->DclkDid[1];
+  IntegratedInfoTable->ucDPMState2DclkFid = PpFuseArray->DclkDid[2];
+  IntegratedInfoTable->ucDPMState3DclkFid = PpFuseArray->DclkDid[3];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Sclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxIntInfoTableInitSclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN                       Index;
+  UINTN                       AvailSclkIndex;
+  ATOM_AVAILABLE_SCLK_LIST    *AvailSclkList;
+  BOOLEAN                     Sorting;
+  AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0];
+
+  AvailSclkIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+    if (PpFuseArray->SclkDpmDid[Index] != 0) {
+      AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], GnbLibGetHeader (Gfx));
+      AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index];
+      AvailSclkList[AvailSclkIndex].usVoltageID = PpFuseArray->SclkVid[PpFuseArray->SclkDpmVid[Index]];
+      AvailSclkIndex++;
+    }
+  }
+  //Sort by VoltageIndex & ulSupportedSCLK
+  if (AvailSclkIndex > 1) {
+    do {
+      Sorting = FALSE;
+      for (Index = 0; Index < (AvailSclkIndex - 1); Index++) {
+        ATOM_AVAILABLE_SCLK_LIST  Temp;
+        BOOLEAN                   Exchange;
+        Exchange = FALSE;
+        if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) {
+          Exchange = TRUE;
+        }
+        if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) &&
+            (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) {
+          Exchange = TRUE;
+        }
+        if (Exchange) {
+          Sorting = TRUE;
+          LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+        }
+      }
+    } while (Sorting);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Read GFX PGFSM register
+ *
+ *
+ * @param[in]  RegisterAddress     Index of PGFSM register
+ * @param[out] Value               Pointer to value
+ * @param[in]  StdHeader           Standard configuration header
+ */
+
+STATIC VOID
+GfxPgfsmRegisterReadTN (
+  IN       UINT32                 RegisterAddress,
+     OUT   UINT32                 *Value,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32      RegisterWriteValue;
+  UINT32      RegisterReadValue;
+  RegisterWriteValue = (RegisterAddress << D0F0xBC_xE0300000_RegAddr_OFFSET) +
+                       (1 << D0F0xBC_xE0300000_ReadOp_OFFSET) +
+                       (0 << D0F0xBC_xE0300000_FsmAddr_OFFSET);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Read PGFSM Register %d\n", RegisterAddress);
+  GnbRegisterWriteTN (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    &RegisterWriteValue,
+    0,
+    StdHeader);
+  do {
+    GnbRegisterReadTN (
+      D0F0xBC_xE0300008_TYPE,
+      D0F0xBC_xE0300008_ADDRESS,
+      &RegisterReadValue,
+      0,
+      StdHeader);
+  } while ((RegisterReadValue & D0F0xBC_xE0300008_ReadValid_MASK) == 0);
+  *Value = RegisterReadValue & D0F0xBC_xE0300008_ReadValue_MASK;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Calculate ulGMCRestoreResetTime
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxCalculateRestoreResetTimeTN (
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx,
+  IN       PP_FUSE_ARRAY                    *PpFuseArray
+  )
+{
+  UINT8      MaxDid;
+  ULONG      FreqSclk;
+  UINTN      Index;
+  UINT32     TSclk;
+  UINT32     TRefClk;
+  UINT32     TNclkHalf;
+  UINT32     PgfsmDelayReg0;
+  UINT32     PgfsmDelayReg1;
+  UINT32     ResetTime;
+  UINT32     IsoTime;
+  UINT32     MemSd;
+  UINT32     MotherPso;
+  UINT32     DaughterPso;
+  UINT32     THandshake;
+  UINT32     TGmcSync;
+  UINT32     TPuCmd;
+  UINT32     TPgfsmCmdSerialization;
+  UINT32     TReset;
+  UINT32     TMoPso;
+  UINT32     TDaPso;
+  UINT32     TMemSd;
+  UINT32     TIso;
+  UINT32     TRegRestore;
+  UINT32     TPgfsmCleanUp;
+  UINT32     TGmcPu;
+  UINT32     TGmcPd;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Enter\n");
+  // Find FreqSclk = MIN of frequencies SclkDpmDid (0 to 4) and SclkThermDid
+  // First find the highest Did
+  MaxDid = PpFuseArray->SclkThermDid;
+  for (Index = 0; Index < 4; Index++) {
+    // Compare with SclkDpmDid[x] - These are stored in:
+    // IntegratedInfoTable-> sDISPCLK_Voltage[Index].ulMaximumSupportedCLK
+    MaxDid = MAX (MaxDid, PpFuseArray->SclkDpmDid[Index]);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid);
+  FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx));
+  // FreqSclk is in 10KHz units - need calculations in nS
+  // For accuracy, do calculations in .01nS, then convert at the end
+  TSclk = (100 * (1000000000 / 10000)) / FreqSclk;
+  // FreqRefClk frequency of reference clock
+  // Caclculate period in .01 nS
+  TRefClk = (100 * 1000) / GFX_REFCLK;
+  // FreqNclkHalf = half of Minimum NCLK value
+  // Calculate period in .01 nS
+  TNclkHalf = (100 * 1000) / (GFX_NCLK_MIN / 2);
+
+  // Read delay time values from PGFSM registers
+  GfxPgfsmRegisterReadTN (2 , &PgfsmDelayReg0, GnbLibGetHeader (Gfx));
+  GfxPgfsmRegisterReadTN (3 , &PgfsmDelayReg1, GnbLibGetHeader (Gfx));
+  ResetTime = (PgfsmDelayReg0 & 0x000000FF ) >> 0 ;
+  IsoTime = (PgfsmDelayReg0 & 0x0000FF00 ) >> 8 ;
+  MemSd = (PgfsmDelayReg0 & 0x00FF0000 ) >> 16 ;
+  MotherPso = (PgfsmDelayReg1 & 0x00000FFF ) >> 0 ;
+  DaughterPso = (PgfsmDelayReg1 & 0x00FFF000 ) >> 12 ;
+  IDS_HDT_CONSOLE (GNB_TRACE, "ResetTime = %d\n", ResetTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "IsoTime = %d\n", IsoTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "MemSd = %d\n", MemSd);
+  IDS_HDT_CONSOLE (GNB_TRACE, "MotherPso = %d\n", MotherPso);
+  IDS_HDT_CONSOLE (GNB_TRACE, "DaughterPso = %d\n", DaughterPso);
+
+  // Calculate various timing values required for the final calculation
+  // THandshake = 10*1/FreqNclkHalf
+  THandshake = 10 * TNclkHalf;
+  // TGmcSync = 2.5*(1/FreqRefclk+1/FreqSclk)
+  TGmcSync = (25 * (TRefClk + TSclk)) / 10;
+  // TPuCmd =9*1/FreqSclk
+  TPuCmd = 9 * TSclk;
+  // TPgfsmCmdSerialization = 82*1/FreqSclk
+  TPgfsmCmdSerialization = 82 * TSclk;
+  // TReset = (RESET_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TGmcSync
+  TReset = ((ResetTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TMoPso = (MOTHER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TMoPso = ((MotherPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TDaPso = (DAUGHTER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TDaPso = ((DaughterPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TMemSD = (MEM_SD+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TMemSd = ((MemSd + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TIso = (ISO_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TIso = ((IsoTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TRegRestore = 508*1/FreqSclk
+  TRegRestore = 508 * TSclk;
+  // TPgfsmCleanUp = 3*1/FreqSclk
+  TPgfsmCleanUp = 3 * TSclk;
+  // TGmcPu = TPUCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSD + TIso + TRegRestore
+  TGmcPu = TPuCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSd + TIso + TRegRestore;
+  // TGmcPd = THandshake + TPgfsmCmdSerialization + Tiso + TmemSD + TMoPso + TDaPso + TpgfsmCleanUp + 3*TReset
+  TGmcPd = THandshake + TPgfsmCmdSerialization + TIso + TMemSd + TMoPso + TDaPso + TPgfsmCleanUp + (3 * TReset);
+  // ulGMCRestoreResetTime = TGmcPu + TGmcPd
+  // All calculated times are in .01nS for accuracy.  We can now correct that.
+  // By adding 99 and dividing by 100, value is rounded up to next 1 nS
+  IntegratedInfoTable->ulGMCRestoreResetTime = (TGmcPd + TGmcPu + 99) / 100;
+  IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *
+ *
+ *
+ * @param[in] Gfx             Gfx configuration info
+ * @retval    AGESA_STATUS
+ */
+AGESA_STATUS
+STATIC
+GfxIntInfoTableInitTN (
+  IN      GFX_PLATFORM_CONFIG     *Gfx
+  )
+{
+  AGESA_STATUS                    Status;
+  AGESA_STATUS                    AgesaStatus;
+  ATOM_FUSION_SYSTEM_INFO_V2      SystemInfoTableV2;
+  PP_FUSE_ARRAY                   *PpFuseArray;
+  PCIe_PLATFORM_CONFIG            *Pcie;
+  ATOM_PPLIB_POWERPLAYTABLE3      *PpTable;
+  UINT8                           Channel;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n");
+  LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx));
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7);
+  ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512);
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7;
+  SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
+  SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
+  SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3;     //DDR3
+  SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100;    //Set default engine clock to 200MhZ
+  SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
+  SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
+  SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
+  //Locate PCIe configuration data to get definitions of display connectors
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
+  SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo);
+  SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx));
+
+  SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
+
+  SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
+  if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) {
+    SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429  = Gfx->gfxplmcfg0 ;
+    IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 );
+  }
+
+  SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
+
+  // LVDS
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
+  SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
+  SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    Status = GfxIntegratedEnumerateAllConnectors (
+               &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
+               Pcie,
+               Gfx
+               );
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+    GfxIntegrateducEDPToLVDSRxIdCallback,
+    &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
+    Pcie
+    );
+
+  // Build PP table
+  PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable;
+  // Build PP table
+  Status = GfxPowerPlayBuildTable (PpTable,  Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  // Assign usFormatID to 0x000B to represent Trinity
+  PpTable->usFormatID = 0xB;
+  // Build info from fuses
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    // Build Display clock info
+    GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+    // Build Sclk info table
+    GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  } else {
+    Status = AGESA_ERROR;
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  //@todo review if thouse parameters needed
+  // Fill in Nb P-state MemclkFreq Data
+  GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in HTC Data
+  GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in NB P states VID
+  GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in NCLK info
+  //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill in the M3 arbitration control tables
+  //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Family specific data update
+
+  // Determine ulGMCRestoreResetTime
+  Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
+  SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+  if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2;
+  }
+  if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1;
+  }
+  if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0;
+  }
+  SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig);
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
+  //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
+  GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *  GMC FB access requred
+ *
+ *
+ * @param[in]   StdHeader     Standard configuration header
+ * @retval      AGESA_STATUS
+ */
+AGESA_STATUS
+GfxIntInfoTableInterfaceTN (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  AGESA_STATUS                    AgesaStatus;
+  AGESA_STATUS                    Status;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  if (GfxLibIsControllerPresent (StdHeader)) {
+    Status = GfxLocateConfigData (StdHeader, &Gfx);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status != AGESA_FATAL) {
+      Status = GfxIntInfoTableInitTN (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
new file mode 100644
index 0000000000..8aace220c3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
@@ -0,0 +1,478 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GfxLibTN.h"
+#include  "GnbCommonLib.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = {
+{0 ,  0 ,  0 ,  0 ,  333,  0,  400,  0 },
+{0 ,  0 ,  533,  0 ,  0 ,  0 ,  667,  0 },
+{0 ,  0 ,   800,  0 ,  0 ,  0 ,  0 ,  0 },
+{0 , 1050, 1066, 0 , 0,    0 , 0,    1200}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GfxFmDisableController (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable GFX controller
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ */
+
+VOID
+GfxFmDisableController (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GnbLibPciRMW (
+    MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS),
+    AccessS3SaveWidth32,
+    0xffffffff,
+    1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get system PLL COF
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    System PLL COF
+ */
+UINT32
+GfxLibGetSytemPllCofTN (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D0F0xBC_xFF000000_STRUCT  D0F0xBC_xFF000000;
+  GnbRegisterReadTN (D0F0xBC_xFF000000_TYPE,  D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader);
+  return 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 0x10);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate COF for DFS out of Main PLL
+ *
+ *
+ *
+ * @param[in] Did         Did
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                COF in 10khz
+ */
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32  Divider;
+  UINT32  SystemPllCof;
+  SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100;
+  if (Did >= 8 && Did <= 0x3F) {
+    Divider = Did * 25;
+  } else if (Did > 0x3F && Did <= 0x5F) {
+    Divider = (Did - 64) * 50 + 1600;
+  } else if (Did > 0x5F && Did <= 0x7E) {
+    Divider = (Did - 96) * 100 + 3200;
+  } else if (Did == 0x7f) {
+    Divider = 128 * 100;
+  } else {
+    ASSERT (FALSE);
+    return 200 * 100;
+  }
+  ASSERT (Divider != 0);
+  return (((SystemPllCof * 100) + (Divider - 1)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set idle voltage mode for GFX
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32  Value;
+
+  GnbRegisterReadTN (GMMx670_TYPE, GMMx670_ADDRESS, &Value, 0, GnbLibGetHeader (Gfx));
+  return ((Value & BIT16) == 0) ? TRUE : FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Extract DRAM frequency
+ *
+ *
+ *
+ * @param[in] Encoding   Memory Clock Frequency Value Definition
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    Dram fraquency Mhz
+ */
+UINT32
+GfxLibExtractDramFrequency (
+  IN       UINT8                  Encoding,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  if (Encoding >= (sizeof (GfxMemClockFrequencyDefinitionTable) / sizeof (UINT16))) {
+    ASSERT (FALSE);
+    return 0;
+  }
+  return GfxMemClockFrequencyDefinitionTable[Encoding / 8][Encoding % 8];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max SCLK
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Max SCLK in Mhz
+ */
+UINT32
+GfxLibGetMaxSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32                    MaxSclkClk;
+  D0F0xBC_xFF000000_STRUCT  D0F0xBC_xFF000000;
+  D0F0xBC_xE0003048_STRUCT  D0F0xBC_xE0003048;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0003048_ADDRESS, &D0F0xBC_xE0003048.Value, 0, StdHeader);
+  //sclk_max_freq = 100 * (GCLK_PLL_FUSES.MainPllOptFreqIdStartup + 16) /
+  //                (((SCLK_MIN_DIV.INT<<12 + SCLK_MIN_DIV.FRAC)>>12)
+  MaxSclkClk = 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 16);
+  MaxSclkClk /= ((D0F0xBC_xE0003048.Field.Intv << 12) + D0F0xBC_xE0003048.Field.Fracv) >> 12;
+  return MaxSclkClk;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of SCLK Dram burst
+ *
+ *
+ * @param[in] ScaleMp         Scaled number of sclk_max_freq / memps_freq
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    number of sclks (*2) per dram burst, except (0,1,2,3)=(1,1.25,1.5,1.75)
+ */
+UINT32
+GfxLibGetNumberOfSclkPerDramBurst (
+  IN       UINT32                ScaleMp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+
+  if ((2 * ScaleMp)  < 125) {
+    return 0; //STATE0 = 0
+  } else if ((2 * ScaleMp)  < 150) {
+    return 1; //STATE0 = 1
+  } else if ((2 * ScaleMp)  < 175) {
+    return 2; //STATE0 = 2
+  } else if ((2 * ScaleMp)  < 200) {
+    return 3; //STATE0 = 3
+  } else {
+    //STATE0 = floor(4*scale_mp[0] )
+    return ((4 * ScaleMp) / 100);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate TN NCLK clock
+ *
+ *
+ *
+ * @param[in] NbFid         NbFid
+ * @param[in] NbDid         NbDid
+ * @retval                  Clock in 10KHz
+ */
+
+UINT32
+GfxLibGetNclkTN (
+  IN      UINT8                   NbFid,
+  IN      UINT8                   NbDid
+  )
+{
+  UINT32  Divider;
+  //i.e. NBCOF[0] = (100 * (D18F5x160[NbFid] + 4h) / (2^D18F5x160[NbDid])) Mhz
+  if (NbDid == 1) {
+    Divider = 2;
+  } else if (NbDid == 0) {
+    Divider = 1;
+  } else {
+    Divider = 1;
+  }
+  ASSERT (NbDid == 0 || NbDid == 1);
+  return ((10000 * (NbFid + 4)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set VID through CG client
+ *
+ *
+ * @param[in] Vid             VID code
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxRequestVoltageTN (
+  IN       UINT8                 Vid,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  GMMx770_STRUCT  GMMx770;
+  GMMx774_STRUCT  GMMx774;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Enter\n");
+
+  GnbRegisterReadTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, 0, StdHeader);
+  GMMx770.Field.VoltageChangeEn = 1;
+  GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  GMMx770.Field.VoltageLevel = Vid;
+  GMMx770.Field.VoltageChangeReq = ~GMMx770.Field.VoltageChangeReq;
+  GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  do {
+    GnbRegisterReadTN (GMMx774_TYPE, GMMx774_ADDRESS, &GMMx774, 0, StdHeader);
+  } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SCLK
+ *
+ *
+ * @param[in] Did             Devider
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    previous DID
+ */
+
+UINT8
+GfxRequestSclkTNS3Save (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, GfxRequestSclkTNS3Script_ID, sizeof (Did), &Did);
+  return GfxRequestSclkTN (Did, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SCLK
+ *
+ *
+ * @param[in] Did             Devider
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+UINT8
+GfxRequestSclkTN (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  GMMx600_STRUCT  GMMx600;
+  GMMx604_STRUCT  GMMx604;
+  UINT8           OriginalDid;
+  do {
+    GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader);
+  } while (GMMx604.Field.SclkStatus == 0);
+  GnbRegisterReadTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader);
+  OriginalDid = (UINT8) GMMx600.Field.IndClkDiv;
+  GMMx600.Field.IndClkDiv = Did;
+  GnbRegisterWriteTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader);
+  do {
+    GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader);
+  } while (GMMx604.Field.SclkStatus == 0);
+  return OriginalDid;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Sclk in S3 script
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        pointer to UINT32 number of us
+ */
+VOID
+GfxRequestSclkTNS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  )
+{
+  GfxRequestSclkTN (* ((UINT8*) Context), StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate did from main VCO
+ *
+ *
+ *
+ * @param[in] Vco           Vco in 10Khz
+ * @param[in] StdHeader     Standard configuration header
+ * @retval                  DID
+ */
+
+UINT8
+GfxLibCalculateDidTN (
+  IN       UINT32                Vco,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32  Divider;
+  UINT32  SystemPllCof;
+  UINT8   Did;
+  ASSERT (Vco != 0);
+  SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100;
+  Divider = ((SystemPllCof * 100) + (Vco - 1)) / Vco;
+  Did = 0;
+  if (Divider < 200) {
+  } else if (Divider <= 1575) {
+    Did = (UINT8) (Divider / 25);
+  } else if (Divider <= 3150) {
+    Did = (UINT8) ((Divider - 1600) / 50) + 64;
+  } else if (Divider <= 6200) {
+    Did = (UINT8) ((Divider - 3200) / 100) + 96;
+  } else {
+    Did = 0x7f;
+  }
+  return Did;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h
new file mode 100644
index 0000000000..69dd6477eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXLIBTN_H_
+#define _GFXLIBTN_H_
+
+UINT32
+GfxLibGetSytemPllCofTN (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibExtractDramFrequency (
+  IN       UINT8                  Encoding,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibGetMaxSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT32
+GfxLibGetNumberOfSclkPerDramBurst (
+  IN       UINT32                ScaleMp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT32
+GfxLibGetNclkTN (
+  IN      UINT8                  NbFid,
+  IN      UINT8                  NbDid
+  );
+
+AGESA_STATUS
+GfxRequestVoltageTN (
+  IN       UINT8                 Vid,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT8
+GfxRequestSclkTN (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT8
+GfxRequestSclkTNS3Save (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+GfxRequestSclkTNS3Script (
+  IN      AMD_CONFIG_PARAMS      *StdHeader,
+  IN      UINT16                 ContextLength,
+  IN      VOID*                  Context
+  );
+
+UINT8
+GfxLibCalculateDidTN (
+  IN       UINT32                Vco,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
new file mode 100644
index 0000000000..4e3efa5466
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
@@ -0,0 +1,304 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65199 $   @e \$Date: 2012-02-09 21:36:06 -0600 (Thu, 09 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxLibTN.h"
+#include  "GfxGmcInitTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "PcieConfigData.h"
+#include  "PcieConfigLib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbHandleLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAudioConnectors (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+AGESA_STATUS
+GfxMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+VOID
+exec803 /* GfxAzWorkaroundTN */ (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxSetBootUpVoltageTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltageTN Enter\n");
+  GfxRequestVoltageTN (GnbLocateHighestVidCode (GnbLibGetHeader (Gfx)), GnbLibGetHeader (Gfx));
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+exec803 /* GfxAzWorkaroundTN */ (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32                  i;
+  UINT32                  Address;
+  UINT32                  Data;
+
+
+  Data = 0x156;
+  for (i = 0; i < 6; i++) {
+    Address = 0x5E00 + (i * 0x18);
+    GnbLibMemWrite (Gfx->GmmBase + Address, AccessS3SaveWidth32, &Data, GnbLibGetHeader (Gfx));
+    GnbLibMemRMW (Gfx->GmmBase + Address + 4, AccessS3SaveWidth32, 0xFFFFFF00, 0xF0, GnbLibGetHeader (Gfx));
+  }
+
+  return;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Mid Post.
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status =  GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_FATAL) {
+    GfxFmDisableController (StdHeader);
+  } else {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnableGmmAccess (Gfx);
+      ASSERT (Status == AGESA_SUCCESS);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      if (Status != AGESA_SUCCESS) {
+        // Can not initialize GMM registers going to disable GFX controller
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Fail to establish GMM access\n");
+        Gfx->UmaInfo.UmaMode = UMA_NONE;
+        GfxFmDisableController (StdHeader);
+      } else {
+        Status = GfxGmcInitTN (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxSetBootUpVoltageTN (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxInitSsid (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxIntegratedEnumerateAudioConnectors (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        exec803 /* GfxAzWorkaroundTN */ (Gfx);
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine number of audio ports for each connector
+ *
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegratedAudioEnumCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8    *AudioCount;
+  AudioCount = (UINT8*) Buffer;
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found HDMI Connector\n");
+    (*AudioCount)++;
+  } else if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) {
+    if ((Engine->Type.Ddi.DdiData.Flags & DDI_DATA_FLAGS_DP1_1_ONLY) == 0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.2 Connector\n");
+      *AudioCount += 4;
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.1 Connector\n");
+      (*AudioCount)++;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors with audio capability and configure number of ports
+ *
+ *
+ *
+ * @param[in]     Gfx             Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAudioConnectors (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  UINT8                   AudioCount;
+  AGESA_STATUS            Status;
+  GMMx5F50_STRUCT         GMMx5F50;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Enter\n");
+
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) {
+    AudioCount = 0;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+      GfxIntegratedAudioEnumCallback,
+      &AudioCount,
+      Pcie
+      );
+    if (AudioCount > 4) {
+      AudioCount = 4;
+    }
+    GMMx5F50.Value = 0x00;
+    GMMx5F50.Field.PortConnectivity = (7 - AudioCount);
+    GMMx5F50.Field.PortConnectivityOverrideEnable = 1;
+    GnbRegisterWriteTN (GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n");
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
new file mode 100644
index 0000000000..36e013ef3c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
@@ -0,0 +1,155 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbFuseTable.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxPostInterfaceTN (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Post.
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS
+ */
+
+
+AGESA_STATUS
+GfxPostInterfaceTN (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_POST_PARAMS       *PostParamsPtr;
+  GFX_CARD_CARD_INFO    GfxDiscreteCardInfo;
+  AGESA_STATUS          Status;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    if (GfxLibIsControllerPresent (StdHeader)) {
+      if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
+        LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader);
+        GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader);
+        if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) ||
+          (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) ||
+          ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE)  &&
+          ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) {
+          PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+          IDS_HDT_CONSOLE (GFX_MISC, "  GfxDisabled due dGPU policy\n");
+        }
+      }
+    } else {
+      PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+      Gfx->GfxFusedOff = TRUE;
+    }
+  } else {
+    PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
new file mode 100644
index 0000000000..876614e510
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
@@ -0,0 +1,1096 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GFx tables
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64726 $   @e \$Date: 2012-01-30 01:00:01 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbRegistersTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbInitTN.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [] = {
+  //2.1 Disable clock-gating
+  GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00000C80),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00001401),
+  GNB_ENTRY_TERMINATE
+};
+
+
+GNB_TABLE ROMDATA GfxGmcInitTableTN [] = {
+  GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET),
+  //2.2 System memory address translation
+  GNB_ENTRY_COPY (GMMx2814_TYPE, GMMx2814_ADDRESS,  0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2818_TYPE, GMMx2818_ADDRESS,  0, 32, D18F2x40_dct1_TYPE, D18F2x40_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx281C_TYPE, GMMx281C_ADDRESS,  0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2820_TYPE, GMMx2820_ADDRESS,  0, 32, D18F2x44_dct1_TYPE, D18F2x44_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2824_TYPE, GMMx2824_ADDRESS,  0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2828_TYPE, GMMx2828_ADDRESS,  0, 32, D18F2x48_dct1_TYPE, D18F2x48_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx282C_TYPE, GMMx282C_ADDRESS,  0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2830_TYPE, GMMx2830_ADDRESS,  0, 32, D18F2x4C_dct1_TYPE, D18F2x4C_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2834_TYPE, GMMx2834_ADDRESS,  0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2838_TYPE, GMMx2838_ADDRESS,  0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx283C_TYPE, GMMx283C_ADDRESS,  0, 32, D18F2x60_dct1_TYPE, D18F2x60_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2840_TYPE, GMMx2840_ADDRESS,  0, 32, D18F2x64_dct1_TYPE, D18F2x64_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS,  0,  8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS,  0,  8),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 16,  1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22,  1),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 19,  1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20,  1),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS,  0,  8, D18F2x80_dct1_TYPE, D18F2x80_dct1_ADDRESS,  0,  8),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 16,  1, D18F2x94_dct1_TYPE, D18F2x94_dct1_ADDRESS, 22,  1),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 19,  1, D18F2xA8_dct1_TYPE, D18F2xA8_dct1_ADDRESS, 20,  1),
+  GNB_ENTRY_COPY (GMMx284C_TYPE, GMMx284C_ADDRESS,  0, 32, TYPE_D18F2 , 0x110 ,  0, 32),
+  GNB_ENTRY_COPY (GMMx2850_TYPE, GMMx2850_ADDRESS,  0, 32, D18F2x114_TYPE, D18F2x114_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2854_TYPE, GMMx2854_ADDRESS,  0, 32, D18F1xF0_TYPE,  D18F1xF0_ADDRESS,   0, 32),
+  //GNB_ENTRY_COPY (GMMx2858_TYPE, GMMx2858_ADDRESS,  0, 32, ????, ????,  0, 32),
+  GNB_ENTRY_COPY (GMMx285C_TYPE, GMMx285C_ADDRESS,  0, 32, TYPE_D18F2 , 0x10c ,  0, 32),
+  // 2.4 RENG init
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001b0a05),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000001D),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00080500),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000027),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001050c),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x1000051e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010536),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000031),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001053e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000034),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010546),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000037),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a054e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000053),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001056f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000056),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010572),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000059),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020575),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000800),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a0801),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007b),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001082a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0014082d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000094),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00040843),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000009a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00170851),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000b3),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001d086a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d2),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000891),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d4),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000893),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d6),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020895),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000da),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020899),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000de),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0002089d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e2),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000208a1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e6),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x006808cd),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000150),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0016094d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000168),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d096d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000177),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0009097f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000182),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000a098a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000018e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d0998),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000019d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000409a7),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001a3),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x003709cd),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001dc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000f0a21),
+  GNB_ENTRY_WR (GMMx28D4_TYPE, GMMx28D4_ADDRESS, 0x7b1ec000),
+  GNB_ENTRY_WR (GMMx28D8_TYPE, GMMx28D8_ADDRESS, 0x200cf01d),
+  // 2.5
+  GNB_ENTRY_RMW (GMMx5490_TYPE, GMMx5490_ADDRESS, GMMx5490_FB_WRITE_EN_MASK | GMMx5490_FB_READ_EN_MASK, (1 << GMMx5490_FB_READ_EN_OFFSET) | (1 << GMMx5490_FB_WRITE_EN_OFFSET)),
+  // 2.6 Perfromance tuning
+  GNB_ENTRY_WR (TYPE_GMM , 0x27d0 , 0x10734847),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27c0 , 0x00032005),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27c4 , 0x00C12008),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27d4 , 0x00003d3c),
+  GNB_ENTRY_WR (TYPE_GMM , 0x277c , 0x00000007),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2198 , 0x000221b1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080A20),
+  GNB_ENTRY_WR (TYPE_GMM , 0x201c , 0x66660006),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2020 , 0x70770007),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2018 , 0x66070050),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2014 , 0x77550000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2794 , 0xfcfcfdfc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2798 , 0xfcfcfdfc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27a4 , 0x00ffffff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27a8 , 0x00ffffff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x278c , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2790 , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2628 , 0x44111222),
+  GNB_ENTRY_WR (TYPE_GMM , 0x25e0 , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x262c , 0x11222111),
+  GNB_ENTRY_WR (TYPE_GMM , 0x25e4 , 0x00000002),
+  //2.7 Miscellaneous programming
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b4 , 0x00000000),
+  //2.8 Enabling garlic interface
+  GNB_ENTRY_RMW (TYPE_GMM , 0x2878 , 0x1 , 1 << 0 ),
+  // Limit number of garlic credits to 12
+  GNB_ENTRY_WR (TYPE_GMM , 0x276c , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2898 , 0x01800360),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x289c , 0x8000 , 1 << 15 ),
+  GNB_ENTRY_REV_RMW (0x0000000000000100ull , TYPE_GMM , 0x289c , 0x8000 , 0 << 15 ),
+  GNB_ENTRY_RMW (GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 0 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET),
+  GNB_ENTRY_REV_RMW (0x0000000000000100ull , GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 1 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET),
+  //2.10 UVD and VCE latency
+  //These settings are to improve UVD and VCE latency.
+  //They need these settings to get good memory performance.
+  GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080200),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2190 , 0x001EA1A1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2180 , 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x218c , 0x000FA1E1),
+  GNB_ENTRY_WR (GMMx2188_TYPE, GMMx2188_ADDRESS, 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f0 , 0x0000A1F1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21ec , 0x0000A1F1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f8 , 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f4 , 0x0000A1E1),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x690 , 0x20000000 , 1 << 29 ),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x21a8 , 0x4 , 0),
+//MC Performance settings base on memory channel configuration, so, move settings to GfxGmcInitializeSequencerTN()
+//  GNB_ENTRY_WR (TYPE_GMM , 0x2214 , 0x00000003),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2218 , 0x0000000C),
+  GNB_ENTRY_WR (GMMx2888_TYPE, GMMx2888_ADDRESS, 0x000007DE),
+  GNB_ENTRY_WR (GMMx25C8_TYPE, GMMx25C8_ADDRESS, 0x00403932),
+  GNB_ENTRY_WR (GMMx2114_TYPE, GMMx2114_ADDRESS, 0x00000015),
+  //2.11 Remove blackout
+  GNB_ENTRY_WR (GMMx25C0_TYPE, GMMx25C0_ADDRESS, 0x00000000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20ec , 0x000001DC),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20d4 , 0x00000016),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20ac , 0x00000000),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x2760 , 0x3 , 1 << 0 ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [] = {
+  GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00040c80),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00041401),
+  //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
+  //Implement in GnbCgttOverrideTN
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GfxEnvInitTableTN [] = {
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_GMM ,
+    0xe60 ,
+    0x0,
+    (0x1 << 1 ) | (0x1 << 0 ) |
+    (0x1 << 5 )  | (0x1 << 2 ) |
+    (0x1 << 7 ) | (0x1 << 6 ) |
+    (0x1 << 9 ) | (0x1 << 8 ) |
+    (0x1 << 11 )  | (0x1 << 10 ) |
+    (0x1 << 14 ) | (0x1 << 13 ) |
+    (0x1 << 17 ) | (0x1 << 15 ) |
+    (0x1 << 19 ) | (0x1 << 18 ) |
+    (0x1 << 24 ) | (0x1 << 20 )
+    ),
+//---------------------------------------------------------------------------
+// Configure GMC Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    (10 << 0 ) | (4 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    (90 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown GMC if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300000_P1Select_OFFSET) | (1 << D0F0xBC_xE0300000_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300200_TYPE,
+    D0F0xBC_xE0300200_ADDRESS,
+    D0F0xBC_xE0300200_P1IsoN_MASK,
+    0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Configure UVD Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown UVD if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE030003C_P1Select_OFFSET) | (1 << D0F0xBC_xE030003C_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300218_TYPE,
+    D0F0xBC_xE0300218_ADDRESS,
+    D0F0xBC_xE0300218_P1IsoN_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Configure VCE Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown VCE if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300024_P1Select_OFFSET) | (1 << D0F0xBC_xE0300024_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030020C_TYPE,
+    D0F0xBC_xE030020C_ADDRESS,
+    D0F0xBC_xE030020C_P1IsoN_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_VcePgfsmClockEn_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+
+//---------------------------------------------------------------------------
+// Configure DCE Power Island
+  // Step 1: Take control over DC2 PGFSM. By default display sends power up/down commands.
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03002DC_TYPE,
+    D0F0xBC_xE03002DC_ADDRESS,
+    (1 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET)
+    ),
+  //Step 2: Read CC_RCU_FUSES register
+  //If Internal GPU is fused off go to Step 3, ELSE Go to Step 4.
+
+  //Step 3: Enable PGFSM commands during reset
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  //Step 4:
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300030_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300030_WriteOp_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  //Step 5: IF (cc_rcu_fuses.f.gpu_dis == 0x1) Skip Step6 ELSE Go to Step 6
+  //Step 6: Disable PGFSM commands during reset. Move to after shutdown DCE.
+  //Step 7: Release control over DC2 PGFSM. Move to after shutdown DCE.
+
+// Shutdown DCE if integrated GFX disabled
+  //Step 1: Take control over DC2 PGFSM. By default display sends power up down commands.
+  //Step 2: Read CC_RCU_FUSES register
+  //Step 3: Enable PGFSM commands during reset
+  //Step 4: Make sure SCLK frequency is below 400Mhz
+  //Step 5: Enable PGFSM clock
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK,
+    (1 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET)
+    ),
+  //Step 6
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300030_P1Select_OFFSET) | (1 << D0F0xBC_xE0300030_P2Select_OFFSET)
+    ),
+  //Step 7
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300210_TYPE,
+    D0F0xBC_xE0300210_ADDRESS,
+    D0F0xBC_xE0300210_P1IsoN_MASK,
+    (0 << D0F0xBC_xE0300210_P1IsoN_OFFSET)
+    ),
+  //Step 8: Restore previous SCLK divider
+  //Step 9: Wait PSO daughter to be asserted
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300210 ,
+    0x2000 ,
+    (1 << 13 )
+    ),
+  //Step 10: Turn off PGFSM clock
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK,
+    (0 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET)
+    ),
+  //Step 11: Disable PGFSM commands during reset. Same final 2 step as DCE power island
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03002DC_TYPE,
+    D0F0xBC_xE03002DC_ADDRESS,
+    (0 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET)
+    ),
+
+//---------------------------------------------------------------------------
+// Configure GFX Power Island
+
+  //Step 3
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 4
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 5
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 6
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 7
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 8
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 9
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 10
+    GNB_ENTRY_RMW (
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    0x0
+    ),
+  // Step 12
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+// Shutdown Gfx if integrated GFX disabled
+  // Step 2
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  // Step 3: Save current SCLK. Make sure SCLK frequency is below 400Mhz
+  // Step 5
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    (1 << 0 ) | (1 << 1 ) |
+    (1 << 2 ) | (1 << 3 ) |
+    (1 << 4 ) | (1 << 5 ) |
+    (1 << 6 )
+    ),
+  // Step 6
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300054_P1Select_OFFSET) | (1 << D0F0xBC_xE0300054_P2Select_OFFSET)
+    ),
+  // Step 7
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300070_P1Select_OFFSET) | (1 << D0F0xBC_xE0300070_P2Select_OFFSET)
+    ),
+  // Step 8
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE030008C_P1Select_OFFSET) | (1 << D0F0xBC_xE030008C_P2Select_OFFSET)
+    ),
+  // Step 9
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000A8_P1Select_OFFSET) | (1 << D0F0xBC_xE03000A8_P2Select_OFFSET)
+    ),
+  // Step 10
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000C4_P1Select_OFFSET) | (1 << D0F0xBC_xE03000C4_P2Select_OFFSET)
+    ),
+  // Step 11
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000E0_P1Select_OFFSET) | (1 << D0F0xBC_xE03000E0_P2Select_OFFSET)
+    ),
+  // Step 12
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000FC_P1Select_OFFSET) | (1 << D0F0xBC_xE03000FC_P2Select_OFFSET)
+    ),
+  // Step 13
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03002F4_TYPE,
+    D0F0xBC_xE03002F4_ADDRESS,
+    0xFFFFFFFF,
+    0
+    ),
+  // Step 14
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03002F0_TYPE,
+    D0F0xBC_xE03002F0_ADDRESS,
+    0xFFFFFFFF,
+    0
+    ),
+  // Step 15: Restore SCLK that is saved in step 4
+  // Step 16
+  GNB_ENTRY_FULL_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */,
+    D0F0xBC_xE03002FC_TYPE,
+    D0F0xBC_xE03002FC_ADDRESS,
+    0xFFFFFFFF,
+    0x3FFFFFFF
+    ),
+  // Step 17
+  GNB_ENTRY_FULL_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */,
+    D0F0xBC_xE03002E4_TYPE,
+    D0F0xBC_xE03002E4_ADDRESS,
+    0xFFFFFFFF,
+    0x3FFFF
+    ),
+  // Step 18
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    0
+    ),
+  // Step 19
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Isolate DC, SYS and CP tile when Internal Graphics is disabled
+  // Step 2: Reduce SCLK frequency to 100Mhz. Save current SCLK divider.
+  // Step 3
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003034_TYPE,
+    D0F0xBC_xE0003034_ADDRESS,
+    D0F0xBC_xE0003034_SysIso_MASK | D0F0xBC_xE0003034_CpIso_MASK |
+    D0F0xBC_xE0003034_Dc0Iso_MASK | D0F0xBC_xE0003034_Dc1Iso_MASK |
+    D0F0xBC_xE0003034_DciIso_MASK | D0F0xBC_xE0003034_DcipgIso_MASK,
+    (1 << D0F0xBC_xE0003034_SysIso_OFFSET) | (1 << D0F0xBC_xE0003034_CpIso_OFFSET) |
+    (1 << D0F0xBC_xE0003034_Dc0Iso_OFFSET) | (1 << D0F0xBC_xE0003034_Dc1Iso_OFFSET) |
+    (1 << D0F0xBC_xE0003034_DciIso_OFFSET) | (1 << D0F0xBC_xE0003034_DcipgIso_OFFSET)
+    ),
+  //Step 4: Restore pervious SCLK frequency
+
+//---------------------------------------------------------------------------
+// For IOMMU add logic of GfxDis
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F2xF4_x57_TYPE,
+    D0F2xF4_x57_ADDRESS,
+    D0F2xF4_x57_L1ImuIntGfxDis_MASK,
+    (0x1 << D0F2xF4_x57_L1ImuIntGfxDis_OFFSET)
+    ),
+
+  GNB_ENTRY_TERMINATE
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
new file mode 100644
index 0000000000..b8dc935f43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
@@ -0,0 +1,353 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe early post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#define GnbFpLibGetExp(V)  ((INT32) ((*((UINT64*) &Value) >> 52) & 0x7FF) - (1023 + 52))
+#define GnbFpLibGetMnts(V) (INT64) ((*((UINT64*) &Value) & ((1ull << 52) - 1)) | (1ull << 52))
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+INT32 _fltused = 0;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate power of
+ *
+ *
+ * @param[in]  Value    value
+ * @param[in]  Pow      power
+ * @retval  Value^Pow
+ */
+
+STATIC DOUBLE
+GnbBapmPowerOf (
+  IN      DOUBLE    Value,
+  IN      UINTN     Pow
+  )
+{
+  DOUBLE Result;
+  Result = Value;
+  while ( --Pow > 0) {
+    Result *= Value;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode R from fuse
+ *
+ *
+ * @param[in]  FuseR    R fused value
+ * @retval  R
+ */
+STATIC DOUBLE
+GnbBapmDecodeR (
+  IN      UINT32  FuseR
+  )
+{
+  DOUBLE Value;
+  Value = ((DOUBLE) (FuseR & 0x1ff)) / (2 << (8 - 1));
+  Value = GnbBapmPowerOf (Value, 4);
+  return ((FuseR & 0x200) != 0) ? (-1) * Value : Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode Tau from fuse
+ *
+ *
+ * @param[in]  FuseTau    Tau fused value
+ * @retval  Tau
+ */
+STATIC DOUBLE
+GnbBapmDecodeTau (
+  IN      UINT32  FuseTau
+  )
+{
+  DOUBLE  Value;
+  Value = FuseTau;
+  Value = GnbBapmPowerOf (Value / (2 << (9 - 1)), 16);
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calaculate X
+ *
+ *
+ * @param[in]  Ts         Samplig rate
+ * @param[in]  Tau        Tau value
+ * @param[in]  R          R value
+ * @retval  X
+ */
+STATIC DOUBLE
+GnbBapmCalculateX (
+  IN      DOUBLE  Ts,
+  IN      DOUBLE  Tau,
+  IN      DOUBLE  R
+  )
+{
+  //X=(R*Ts)/(2*Tau+Ts);
+  DOUBLE Result;
+  Result = (R * Ts) / (2 * Tau + Ts);
+  return (Result * GnbBapmPowerOf (2, 36)) + 0.5;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calaculate Y
+ *
+ *
+ * @param[in]  Ts         Samplig rate
+ * @param[in]  Tau        Tau value
+ * @retval  Y
+ */
+STATIC DOUBLE
+GnbBapmCalculateY (
+  IN      DOUBLE  Ts,
+  IN      DOUBLE  Tau
+  )
+{
+  //Y=(2*Tau-Ts)/(2*Tau+Ts);
+  DOUBLE Result;
+  Result = (2 * Tau - Ts) / (2 * Tau + Ts);
+  return (Result *  GnbBapmPowerOf (2, 32)) + 0.5;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set X & Y value
+ *
+ *
+ * @param[in]  X          X value
+ * @param[in]  Y          Y value
+ * @param[in]  AddrOffset Offset of address
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmSetYAndX (
+  IN       INT32              X,
+  IN       INT32              Y,
+  IN       UINT32             AddrOffset,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  GnbRegisterWriteTN (
+    D0F0xBC_x1F480_TYPE,
+    D0F0xBC_x1F480_ADDRESS + AddrOffset,
+    &X,
+    0,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "X: 0x%08x\n", X);
+  GnbRegisterWriteTN (
+    D0F0xBC_x1F480_TYPE,
+    D0F0xBC_x1F480_ADDRESS + AddrOffset + 4,
+    &Y,
+    0,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "Y: 0x%08x\n", Y);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Extract INt32 from DOUBLE
+ *
+ *
+ *
+ * @param[in]  Value  Double value
+ * @retval     int32
+ */
+INT32
+GnbFpLibDoubleToInt32 (
+  IN      DOUBLE  Value
+  )
+{
+  INT64   Mantissa;
+  INT32   Exponent;
+  Mantissa = GnbFpLibGetMnts (Value);
+  Exponent = GnbFpLibGetExp (Value);
+  if (Exponent < -64) {
+    Mantissa = 0;
+  } else if (Exponent < 0) {
+    Mantissa >>=  - Exponent;
+  } else {
+    Mantissa <<= Exponent;
+  }
+  return (INT32) ((Value < 0) ? - Mantissa :  Mantissa);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calcuate BAPM coefficient
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+VOID
+GnbBapmCalculateCoeffsTN (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32  RFuse1;
+  UINT32  TauFuse1;
+  UINT32  Index;
+  DOUBLE  R;
+  DOUBLE  Tau;
+  DOUBLE  Ts;
+  INT32   X;
+  INT32   Y;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Enter\n");
+
+  LibAmdFinit ();
+
+  Ts = ((DOUBLE) (D0F0xBC_x1F468_TimerPeriod_Value * D0F0xBC_x1F46C_BapmPeriod_Value) / 100) / 1000000;
+
+  for (Index = 0; Index < 15; Index++) {
+    GnbRegisterReadTN (
+      TYPE_D0F0xBC ,
+      0xe01040c4  + Index * 4,
+      &RFuse1,
+      0,
+      StdHeader
+      );
+    GnbRegisterReadTN (
+      TYPE_D0F0xBC ,
+      0xe01040c4  + (Index + 15) * 4,
+      &TauFuse1,
+      0,
+      StdHeader
+      );
+
+    R = GnbBapmDecodeR (RFuse1 & 0x3FF);
+    Tau = GnbBapmDecodeTau (TauFuse1 & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+    GnbBapmSetYAndX (X, Y, Index * 2 * 4, StdHeader);
+
+    R = GnbBapmDecodeR ((RFuse1 >> 10) & 0x3FF);
+    Tau = GnbBapmDecodeTau ((TauFuse1 >> 10) & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+
+    GnbBapmSetYAndX (X, Y, (Index * 2 + 30) * 4 , StdHeader);
+
+    R = GnbBapmDecodeR ((RFuse1 >> 20) & 0x3FF);
+    Tau = GnbBapmDecodeTau ((TauFuse1 >> 20) & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+
+    GnbBapmSetYAndX (X, Y, (Index * 2 + 60) * 4 , StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Exit\n");
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h
new file mode 100644
index 0000000000..3ed7b4807f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CAC weights table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBBAPMCOEFFCALCTN_H_
+#define _GNBBAPMCOEFFCALCTN_H_
+
+typedef double DOUBLE;
+
+VOID
+GnbBapmCalculateCoeffsTN (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+INT32
+GnbFpLibDoubleToInt32 (
+  IN      DOUBLE  Value
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
new file mode 100644
index 0000000000..bf17ad1601
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
@@ -0,0 +1,175 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CAC weights table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBCACWEIGHTSTABLETN_H_
+#define _GNBCACWEIGHTSTABLETN_H_
+
+UINT32 CacWeightsTN[] = {
+  0xD65,
+  0x289A,
+  0x289A,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x16F,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x16A5,
+  0x592,
+  0x0,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0xEC9,
+  0xEC9,
+  0x41A,
+  0x41A,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0x79,
+  0x79,
+  0x79,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x3F2,
+  0x3F2,
+  0x0,
+  0x0,
+  0x123,
+  0x0,
+  0x0,
+  0x0,
+  0x123,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x195B,
+  0x629,
+  0x0,
+  0x0,
+  0x195B,
+  0x629,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x88B,
+  0x1206,
+  0x0,
+  0x88B,
+  0x1206,
+  0x0,
+  0x0
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
new file mode 100644
index 0000000000..b3b3101072
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
@@ -0,0 +1,888 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe early post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64732 $   @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbTable.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbSmuFirmwareTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GfxLibTN.h"
+#include  "GnbCacWeightsTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbHandleLib.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "GnbInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA      GnbEarlyInitTableTN [];
+extern GNB_TABLE ROMDATA      GnbEarlierInitTableBeforeSmuTN [];
+extern GNB_TABLE ROMDATA      GnbEarlierInitTableAfterSmuTN [];
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern BUILD_OPT_CFG          UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+GnbEarlierInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+);
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
+
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbAdjustSmuVidBeforeSmuTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_xE0001008_STRUCT  D0F0xBC_xE0001008;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+  D0F0xBC_xE0001008.Field.SClkVid3 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid2 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid1 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid0 -= 4;
+  GnbRegisterWriteTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
+
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbAdjustSmuVidAfterSmuTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F88C_STRUCT                   D0F0xBC_x1F88C;
+  D0F0xBC_x1F8DC_STRUCT                   D0F0xBC_x1F8DC;
+  D0F0xBC_x1F8E0_STRUCT                   D0F0xBC_x1F8E0;
+  D0F0xBC_x1F8E4_STRUCT                   D0F0xBC_x1F8E4;
+  D0F0xBC_x1F8E8_STRUCT                   D0F0xBC_x1F8E8;
+  D0F0xBC_x1F400_STRUCT                   D0F0xBC_x1F400;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Enter\n");
+
+  //Adjust SMU VIDs
+  GnbRegisterReadTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader);
+
+  D0F0xBC_x1F88C.Field.NbVid_3 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_2 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_1 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_0 -= 4;
+
+  D0F0xBC_x1F8DC.Field.SClkVid3 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid2 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid1 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid0 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_2 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_1 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_0 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmNbVid_1 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmNbVid_0 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmSclkVid_3 -= 4;
+  D0F0xBC_x1F8E8.Field.BapmNbVid_3 -= 4;
+  D0F0xBC_x1F8E8.Field.BapmNbVid_2 -= 4;
+
+  GnbRegisterWriteTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader);
+
+  //D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV)
+  GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+  D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb SMU LHTC support
+ *
+ * Part of BAPM enablement.
+ * When BAPM is disabled in battery mode firmware will enable LHTC.
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmLhtcInitTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F638_STRUCT            D0F0xBC_x1F638;
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+  D0F0xBC_x1F86C_STRUCT            D0F0xBC_x1F86C;
+  D0F0xBC_x1F628_STRUCT            D0F0xBC_x1F628;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+
+  //1. Set HTC period to 10 in PM_TIMERS_2 register
+  //Still need to keep PM_CONFIG.Enable_HTC_Limit to 0
+  D0F0xBC_x1F428.Field.field_4  = 0;
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F638.Field.HtcPeriod = 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader);
+
+  //2. Read BapmLhtcCap fuse
+  GnbRegisterReadTN (D0F0xBC_x1F86C_TYPE, D0F0xBC_x1F86C_ADDRESS, &D0F0xBC_x1F86C, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader);
+  if (D0F0xBC_x1F86C.Field.BapmLhtcCap == 0) {
+    D0F0xBC_x1F628.Field.HtcActivePstateLimit = 0;
+  } else {
+    D0F0xBC_x1F628.Field.HtcActivePstateLimit = D0F0xBC_xE0104188.Field.LhtcPstateLimit;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Measured temperature with BAPM
+ *
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmMeasuredTempTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+  D0F0xBC_x1F844_STRUCT            D0F0xBC_x1F844;
+  D0F0xBC_x1F848_STRUCT            D0F0xBC_x1F848;
+  D0F0xBC_x1F84C_STRUCT            D0F0xBC_x1F84C;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+
+  //Measured temperature with BAPM
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F428.Field.line180  = 0;
+  if (D0F0xBC_xE0104188.Field.BapmMeasuredTemp == 1) {
+    D0F0xBC_x1F844.Value = 0x38B;
+    GnbRegisterWriteTN (D0F0xBC_x1F844_TYPE, D0F0xBC_x1F844_ADDRESS, &D0F0xBC_x1F844, 0, StdHeader);
+    D0F0xBC_x1F848.Value = 0x38D;
+    GnbRegisterWriteTN (D0F0xBC_x1F848_TYPE, D0F0xBC_x1F848_ADDRESS, &D0F0xBC_x1F848, 0, StdHeader);
+    D0F0xBC_x1F84C.Value = 0x389;
+    GnbRegisterWriteTN (D0F0xBC_x1F84C_TYPE, D0F0xBC_x1F84C_ADDRESS, &D0F0xBC_x1F84C, 0, StdHeader);
+
+    D0F0xBC_x1F428.Field.line180  = 1;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb SMU LHTC Enable
+ *
+ * Part of BAPM enablement.
+ * When BAPM is disabled in battery mode firmware will enable LHTC.
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbLhtcEnableTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F428.Field.field_4  = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Exit\n");
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Update BAPMTI_TjOffset
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbTjOffsetUpdateTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F870_STRUCT             D0F0xBC_x1F870;
+
+  CPU_LOGICAL_ID                    LogicalId;
+  GNB_HANDLE                        *GnbHandle;
+  D0F0xBC_xE0104040_STRUCT          D0F0xBC_xE0104040;
+  D0F0xBC_x1F85C_STRUCT             D0F0xBC_x1F85C;
+  ex1075_STRUCT           ex1075 ;
+  UINT32                            TimerPeriod;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Enter\n");
+
+
+  TimerPeriod = D0F0xBC_x1F468_TimerPeriod_Value;
+  GnbRegisterReadTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe010413c , &ex1075, 0, StdHeader);
+  // Determine desired AgingRate:
+  // PM_FUSES4.TdpAgeRate * Fuse[BAPMTI_Ts] (encoded in us)
+  // Re-encode TdpAgeRate with 1ms BAPM interval
+  D0F0xBC_x1F85C.Field.TdpAgeRate = (D0F0xBC_x1F85C.Field.TdpAgeRate * ex1075.Field.ex1075_0 ) / (TimerPeriod / 100);
+  GnbRegisterWriteTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader);
+  if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision);
+    return;
+  }
+  GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+  //9900h=FS1r2/FP2 Devastator
+  //9903h=FS1r2/FP2 Devastator Lite
+  //9990h=FS1r2/FP2 Scrapper
+  //9901h=FM2 Devastator
+  //9904h=FM2 Devastator Lite
+  //9991h=FM2 Scrapper
+  if ((D0F0xBC_xE0104040.Field.DeviceID == 0x9900) || (D0F0xBC_xE0104040.Field.DeviceID == 0x9903)) {
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x26;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x26;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x26;
+  } else if (D0F0xBC_xE0104040.Field.DeviceID == 0x9990) {
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x2E;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x2E;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x2E;
+  } else {
+    IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Skip DID- %x\n", D0F0xBC_xE0104040.Field.DeviceID);
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * GPU CAC enablement and weights programming
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+STATIC VOID
+GnbCacEnablement (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F464_STRUCT   D0F0xBC_x1F464;
+  ex1071_STRUCT    ex1071 ;
+  ex1072_STRUCT    ex1072 ;
+  PCI_ADDR                PciAddress;
+  UINT8                   Index;
+  ex1073_STRUCT    ex1073 ;
+  D18F5x160_STRUCT        D18F5x160;
+  DOUBLE                  UnbCac;
+  GMMx898_STRUCT          GMMx898;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader);
+  ex1072.Field.ex1072_2  = 0x29;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader);
+
+  //UNB_CAC_VALUE.UNB_CAC = 2.3734E-04 * FNBPS0 (in MHz) * 2^GPU_CAC_AVRG_CNTL.WEIGHT_PREC
+  GnbRegisterReadTN (D18F5x160_TYPE, D18F5x160_ADDRESS, &D18F5x160.Value, 0, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "NBP0 10khz %x (%d)\n", GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid), GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid));
+  UnbCac = 0.00000204831536 * (1 << ex1072.Field.ex1072_0 ) * GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid);
+  ex1073.Field.ex1073_0  = (UINT32) GnbFpLibDoubleToInt32 (UnbCac);
+  IDS_HDT_CONSOLE (GNB_TRACE, "UnbCac %x (%d)\n", ex1073.Field.ex1073_0 , ex1073.Field.ex1073_0 );
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f91c , &ex1073.Value, 0, StdHeader);
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader);
+  ex1071.Field.ex1071_0  = 0x1;
+  ex1071.Field.ex1071_3  = 0x4;
+  ex1071.Field.ex1071_4  = 0x25;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader);
+
+  GnbRegisterReadTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader);
+  GMMx898.Field.Threshold = 0x31;
+  GnbRegisterWriteTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader);
+
+  // Set CAC/TDP interval
+  GnbRegisterReadTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader);
+  D0F0xBC_x1F464.Field.TdpCntl = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader);
+
+  // Program GPU CAC weights
+
+  for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) {
+    GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0  + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader);
+  }
+
+  // Call BIOS service SMC_MSG_CONFIG_TDP_CNTL
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  GnbSmuServiceRequestV4 (
+    PciAddress,
+    SMC_MSG_CONFIG_TDP_CNTL,
+    0,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode power of CPU out of Watt
+ *
+ *
+ *
+ * @param[in] Encode      PwrCpu encode
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                mWatt
+ */
+STATIC INT32
+CpuPowerDecode (
+  IN      UINT8                           Encode,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT32                   Power;
+  ex1002_STRUCT    ex1002 ;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader);
+
+  //TdpWatt = TdpWattEncode / 1024
+  //PwrCpu / TdpWatt = Encode
+  //PwrCpu = Encode * TdpWattEncode / 1024
+
+  Power = (INT32) ((Encode * ex1002.Field.ex1002_0  *1000) / 1024);
+
+  return Power;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Encode the offset of power of CPU
+ *
+ *
+ *
+ * @param[in] NewPower    New power of mWatt
+ * @param[in] OrgPower    Original power of mWatt
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                Encode
+ */
+STATIC UINT8
+CpuPowerOffsetEncode (
+  IN      INT32                           NewPower,
+  IN      INT32                           OrgPower,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT8                    PowerOffsetEncode;
+  INT32                   PowerOffset;
+  ex1002_STRUCT    ex1002 ;
+  BOOLEAN                 Postive;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader);
+  if (NewPower > OrgPower) {
+    PowerOffset = NewPower - OrgPower;
+    Postive = TRUE;
+  } else {
+    PowerOffset = OrgPower - NewPower;
+    Postive = FALSE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu New Pwr %x (%d)\n", NewPower, NewPower);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu org Pwr %x (%d)\n", OrgPower, OrgPower);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Tdp2Watt %x, (%d)\n", ex1002.Field.ex1002_0 , ex1002.Field.ex1002_0 );
+  //Ceil of (mWatt *1024 / TdpWattEncode) / 1000 = Encode in watt
+  PowerOffset = (((PowerOffset * 1024) / ex1002.Field.ex1002_0 ) + 500) / 1000;
+
+  if (Postive) {
+    PowerOffsetEncode = (INT8) PowerOffset;
+  } else {
+    PowerOffsetEncode = 0 - (INT8) PowerOffset;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PowerOffsetEncode %x\n", PowerOffsetEncode);
+  return (UINT8) PowerOffsetEncode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode power of GPU out of Watt
+ *
+ *
+ *
+ * @param[in] Encode      PwrGpu encode
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                mWatt
+ */
+STATIC INT16
+GpuPowerDecode (
+  IN      UINT16                          Encode,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT16                   Power;
+
+  Power = (INT16) Encode;
+
+
+  return Power;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode Max Tj
+ *
+ *
+ *
+ * @param[in] Encode      Tj encode
+ * @retval                100 x Tj
+ */
+STATIC INT16
+TjMaxDecode (
+  IN      UINT8               Encode
+  )
+{
+  INT16    TjMax;
+
+  TjMax = (INT16) Encode;
+
+  return (TjMax * 100);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * for BAPMTI_TjOffset decoding
+ *
+ *
+ *
+ * @param[in] Encode      Tj encode
+ * @retval                100 x Tjoffset
+ */
+STATIC INT16
+TjOffsetDecode (
+  IN      UINT8               Encode
+  )
+{
+  UINT16      Number;
+  UINT8       Floating;
+  BOOLEAN     Postive;
+  UINT8       TjOffsetEncode;
+
+  TjOffsetEncode = Encode;
+  Postive = TRUE;
+
+  if (Encode == 0) {
+    return 0;
+  }
+
+  if ((TjOffsetEncode & 0x80) != 0) {
+    Postive = FALSE;
+    TjOffsetEncode = (UINT8) (~(Encode - 1));
+  }
+
+  Number = ((TjOffsetEncode >> 2) & 0x1F) * 100;
+
+  Floating = (TjOffsetEncode & 0x3);
+  if (Floating == 1) {
+    Number += 25;
+  } else if (Floating == 2) {
+    Number += 50;
+  } else if (Floating == 3) {
+    Number += 75;
+  } else {
+  }
+
+  if (Postive) {
+    return  (INT16) Number;
+  } else {
+    return (INT16) (0 - Number);
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Trinity SMU supports a software-writeable TjOffset (called swTjOffset) that can be programmed to
+ * account for underspec thermal solutions.
+ * There is a mechanism for customers to adjust TjOffset (via BAPM_PARAMETERS3.TjOffset)
+ * for under-performing thermal solutions.
+ * BIOS will adjust NomPow/MidPow/MaxPow based on this software-programmable TjOffset (called swTjOffset).
+ * SMU firmware will add this value to Fuse[TjOffset] for all TE's during BAPM calculations.
+ *
+ * Tj stands for junction temperature of the processor. However, here is a general description of
+ * our software-programmable TjOffset for BAPM (Birdirectional Application Power Management):
+ * "swTjOffset is an adjustable offset for BAPM thermal calculations to account for changes in
+ * junction temperature, TjOffset. For further details, see Thermal Guide."
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbSoftwareTjOffsetTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F860_STRUCT   D0F0xBC_x1F860;
+  D0F0xBC_x1F864_STRUCT   D0F0xBC_x1F864;
+  ex999_STRUCT    ex999 ;
+  D0F0xBC_x1F870_STRUCT   D0F0xBC_x1F870;
+  ex1000_STRUCT    ex1000 ;
+  ex1001_STRUCT    ex1001 ;
+
+  ex996_STRUCT   ex996;
+  ex997_STRUCT    ex997 ;
+  D0F0xBC_x1F6B4_STRUCT   D0F0xBC_x1F6B4;
+  ex998_STRUCT    ex998 ;
+  INT8                    SwTjOffset;
+  INT16                   Delta_T_org;
+  INT16                   Delta_T_new;
+  INT32                   Cpu_New_Pwr;
+  INT32                   Gpu_New_Pwr;
+
+  SwTjOffset = (INT8) UserOptions.CfgGnbSwTjOffset;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Enter\n");
+
+  IDS_OPTION_HOOK (IDS_GNB_PMM_SWTJOFFSET, &SwTjOffset, StdHeader);
+  if (SwTjOffset == 0) {
+    return;
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "User Input Tj Offset %x\n", SwTjOffset);
+  GnbRegisterReadTN (D0F0xBC_x1F860_TYPE, D0F0xBC_x1F860_ADDRESS, &D0F0xBC_x1F860, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F864_TYPE, D0F0xBC_x1F864_ADDRESS, &D0F0xBC_x1F864, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f868 , &ex999, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f898 , &ex1000, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f8c0 , &ex1001, 0, StdHeader);
+
+  //Tjoffset_new = Tjoffset_org + SwTjOffset
+  //Delta_T_org = T_die - Tjoffset_org - 45
+
+  //Delta_T_new = T_die - Tjoffset_new - 45
+  //            = T_die - (Tjoffset_org + SwTjOffset) - 45
+  //            = T_die - Tjoffset_org - SwTjOffset - 45
+
+  //Pwr_new = Pwr_org * (Delta_T_new/Delta_T_org)
+  //        = Pwr_org * (T_org - TjOffset) / T_org
+
+  //Cpu0
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_3 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_2  = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader), StdHeader);
+
+  //Cpu1
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_0 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_1, StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_1  = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader), StdHeader);
+
+  //GPU
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex997.Field.ex997_0  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader));
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex997.Field.ex997_1  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader));
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_0  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader));
+
+  //SwTjOffset
+  D0F0xBC_x1F6B4.Field.TjOffset = SwTjOffset;
+
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6ac , &ex996, 0, StdHeader);
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6b0 , &ex997, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F6B4_TYPE, D0F0xBC_x1F6B4_ADDRESS, &D0F0xBC_x1F6B4, 0, StdHeader);
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1F6B8 , &ex998, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init TDC
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC VOID
+GnbInitTdc (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_EARLY_PARAMS        *EarlyParams;
+  D0F0xBC_x1F62C_STRUCT   D0F0xBC_x1F62C;
+  D0F0xBC_x1F840_STRUCT   D0F0xBC_x1F840;
+
+  EarlyParams = (AMD_EARLY_PARAMS *) StdHeader;
+  D0F0xBC_x1F62C.Field.Idd = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10;
+  D0F0xBC_x1F62C.Field.Iddnb = EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F62C_TYPE, D0F0xBC_x1F62C_ADDRESS, &D0F0xBC_x1F62C, 0, StdHeader);
+
+  D0F0xBC_x1F840.Field.IddspikeOCP = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10;
+  D0F0xBC_x1F840.Field.IddNbspikeOCP = EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F840_TYPE, D0F0xBC_x1F840_ADDRESS, &D0F0xBC_x1F840, 0, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS                     Status;
+  GNB_HANDLE                       *GnbHandle;
+  UINT32                           Property;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Enter\n");
+  Property = TABLE_PROPERTY_DEAFULT;
+
+  //Check fuse to support BAPM disabled.
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+  if (D0F0xBC_xE0104188.Field.BapmDisable == 0) {
+    Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0;
+  }
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  // SMU LHTC support init
+  GnbBapmLhtcInitTN (StdHeader);
+
+  if ((Property & TABLE_PROPERTY_BAPM) == TABLE_PROPERTY_BAPM) {
+    GnbTjOffsetUpdateTN (StdHeader);
+    GnbSoftwareTjOffsetTN (StdHeader);
+    GnbBapmCalculateCoeffsTN (StdHeader);
+    GnbCacEnablement (StdHeader);
+    GnbBapmMeasuredTempTN (StdHeader);
+  } else {
+    //  If BAPM is disabled (either through fusing or CBS option), AGESA should enable LHTC algorithm.
+    //  Right now, LHTC is only enabled in the "DisableBAPM()" firmware routine, so unless Driver specifically calls this message,
+    //  LHTC will never be enabled if BAPM is disabled from the start.
+    GnbLhtcEnableTN (StdHeader);
+  }
+
+  GnbInitTdc (StdHeader);
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlyInitTableTN,
+             Property,
+             0,
+             StdHeader
+             );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEarlierInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_HANDLE                *GnbHandle;
+  D0F0xBC_xE0107060_STRUCT  D0F0xBC_xE0107060;
+  D0F0xBC_xE0001008_STRUCT  D0F0xBC_xE0001008;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Enter\n");
+
+  GnbAdjustSmuVidBeforeSmuTN (StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GnbRegisterReadTN (D0F0xBC_xE0107060_TYPE, D0F0xBC_xE0107060_ADDRESS, &D0F0xBC_xE0107060, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+  GfxRequestVoltageTN ((UINT8) D0F0xBC_xE0001008.Field.SClkVid1, StdHeader);
+  GfxRequestSclkTN ((UINT8) D0F0xBC_xE0107060.Field.SClkDpmDid1, StdHeader);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlierInitTableBeforeSmuTN,
+             0,
+             0,
+             StdHeader
+             );
+  GnbSmuFirmwareLoadV4 (GnbHandle->Address, (FIRMWARE_HEADER_V4*) &FirmwareTN[0], StdHeader);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlierInitTableAfterSmuTN,
+             0,
+             0,
+             StdHeader
+             );
+
+  GnbAdjustSmuVidAfterSmuTN (StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
new file mode 100644
index 0000000000..f98884dcf9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
@@ -0,0 +1,197 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbFuseTableTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "GnbFuseTable.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern GNB_TABLE ROMDATA      GnbEnvInitTableTN [];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS                   Status;
+  AMD_ENV_PARAMS                 *EnvParamsPtr;
+  UINT32                         Property;
+  GNB_HANDLE                     *GnbHandle;
+  D18F5x170_STRUCT               D18F5x170;
+  D0F0xBC_x1F8DC_STRUCT          D0F0xBC_x1F8DC;
+  PP_FUSE_ARRAY                  *PpFuseArray;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n");
+  Property = TABLE_PROPERTY_DEAFULT;
+  EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GnbLoadFuseTableTN (StdHeader);
+  Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader);
+  GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader);
+  GnbClumpUnitIdV4 (GnbHandle, StdHeader);
+  GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader);
+  Property |= GnbBuildOptions.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0;
+  Property |= GnbBuildOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0;
+  if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) {
+    Property |= TABLE_PROPERTY_IOMMU_DISABLED;
+  }
+
+  if (GnbBuildOptions.CfgNbdpmEnable) {
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      D18F5x170_ADDRESS,
+      &D18F5x170.Value,
+      0,
+      StdHeader
+    );
+    // Check if NbPstate enbale
+    if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) {
+      Property |= TABLE_PROPERTY_NBDPM;
+      PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+      if (PpFuseArray != NULL) {
+        // NBDPM is requesting SclkVid0 from the register.
+        // Write them back if SclkVid has been changed in PpFuseArray.
+        GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader);
+        if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) {
+          D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0];
+          D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1];
+          D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2];
+          D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3];
+          GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        }
+      }
+    }
+  }
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEnvInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
new file mode 100644
index 0000000000..c2bb8823ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
@@ -0,0 +1,1000 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Gnb fuse table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFuseTable.h"
+#include  "GnbFuseTableTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbFuseTableDebugDumpTN (
+  IN       PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+
+
+PP_FUSE_ARRAY  ex907  = {
+  0,                              // PP table revision
+  {1,    0,  0,  0,  0, 0},       // Valid DPM states
+  {0x40, 0,  0,  0,  0, 0},       // Sclk DPM DID
+  {0,    0,  0,  0,  0, 0},       // Sclk DPM VID
+  {0,    0,  0,  0,  0},          // Sclk DPM Cac
+  {1,    0,  0,  0,  0,  0},      // State policy flags
+  {2,    0,  0,  0,  0,  0},      // State policy label
+  {0x40, 0,  0,  0},              // VCLK DID
+  {0x40, 0,  0,  0},              // DCLK DID
+  8,                              // Thermal SCLK
+  {0,    0,  0,  0,  0,  0},      // Vclk/Dclk selector
+  {0,    0,  0,  0},              // Valid Lclk DPM states
+  {0x40, 0x40, 0x40, 0},          // Lclk DPM DID
+  {0x40, 0x40, 0x40, 0},          // Lclk DPM VID
+  {0,    0,  0,  0},              // Displclk DID
+  3,                              // Pcie Gen 2 VID
+  0x10,                           // Main PLL id for 3200 VCO
+  0,                              // WRCK SMU clock Divisor
+  {0x24, 0x24, 0x24, 0x24},       // SCLK VID
+  0,                              // GPU boost cap
+  {0, 0, 0, 0, 0, 0},             // Sclk DPM TDP limit
+  0,                              // TDP limit PG
+  0,                              // Boost margin
+  0,                              // Throttle margin
+  TRUE,                           // Support VCE in PP table
+  {0x3, 0xC, 0x30, 0xC0},         // VCE Flags
+  {0, 1, 0, 1},                   // MCLK for VCE
+  {0, 0, 0, 0},                   // SCLK selector for VCE
+  {0x40, 0x40, 0x40, 0x40}        // Eclk DID
+};
+
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104158_TABLE [] = {
+  {
+    D0F0xBC_xE0104158_EClkDid0_OFFSET,
+    D0F0xBC_xE0104158_EClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[0])
+  },
+  {
+    D0F0xBC_xE0104158_EClkDid1_OFFSET,
+    D0F0xBC_xE0104158_EClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[1])
+  },
+  {
+    D0F0xBC_xE0104158_EClkDid2_OFFSET,
+    D0F0xBC_xE0104158_EClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010415B_TABLE [] = {
+  {
+    D0F0xBC_xE010415B_EClkDid3_OFFSET,
+    D0F0xBC_xE010415B_EClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104184_TABLE [] = {
+  {
+    D0F0xBC_xE0104184_VCEFlag0_OFFSET,
+    D0F0xBC_xE0104184_VCEFlag0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[0])
+  },
+  {
+    D0F0xBC_xE0104184_VCEFlag1_OFFSET,
+    D0F0xBC_xE0104184_VCEFlag1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104187_TABLE [] = {
+  {
+    D0F0xBC_xE0104187_VCEFlag2_OFFSET,
+    D0F0xBC_xE0104187_VCEFlag2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104188_TABLE [] = {
+  {
+    D0F0xBC_xE0104188_VCEFlag3_OFFSET,
+    D0F0xBC_xE0104188_VCEFlag3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[3])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel0_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[0])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel1_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[1])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel2_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[2])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel3_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[3])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 0,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[0])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 1,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[1])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 2,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[2])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 3,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[3])
+  },
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106020_TABLE [] = {
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0])
+  },
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1])
+  },
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106023_TABLE [] = {
+  {
+    D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET,
+    D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106024_TABLE [] = {
+  {
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET,
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4])
+  },
+  {
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET,
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705C_TABLE [] = {
+  {
+    D0F0xBC_xE010705C_PowerplayTableRev_OFFSET,
+    D0F0xBC_xE010705C_PowerplayTableRev_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PPlayTableRev)
+  },
+  {
+    D0F0xBC_xE010705C_SClkThermDid_OFFSET,
+    D0F0xBC_xE010705C_SClkThermDid_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkThermDid)
+  },
+  {
+    D0F0xBC_xE010705C_PcieGen2Vid_OFFSET,
+    D0F0xBC_xE010705C_PcieGen2Vid_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PcieGen2Vid)
+  }
+};
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705F_TABLE [] = {
+  {
+    D0F0xBC_xE010705F_SClkDpmVid0_OFFSET,
+    D0F0xBC_xE010705F_SClkDpmVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0])
+  },
+  {
+    D0F0xBC_xE010705F_SClkDpmVid0_OFFSET,
+    D0F0xBC_xE010705F_SClkDpmVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107060_TABLE [] = {
+  {
+    D0F0xBC_xE0107060_SClkDpmVid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[2])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid3_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid4_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid0_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107063_TABLE [] = {
+  {
+    D0F0xBC_xE0107063_SClkDpmDid3_OFFSET,
+    D0F0xBC_xE0107063_SClkDpmDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107064_TABLE [] = {
+  {
+    D0F0xBC_xE0107064_SClkDpmDid4_OFFSET,
+    D0F0xBC_xE0107064_SClkDpmDid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107067_TABLE [] = {
+  {
+    D0F0xBC_xE0107067_DispClkDid0_OFFSET,
+    D0F0xBC_xE0107067_DispClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107068_TABLE [] = {
+  {
+    D0F0xBC_xE0107068_DispClkDid1_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[1])
+  },
+  {
+    D0F0xBC_xE0107068_DispClkDid2_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107068_DispClkDid3_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107068_LClkDpmDid0_OFFSET,
+    D0F0xBC_xE0107068_LClkDpmDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706B_TABLE [] = {
+  {
+    D0F0xBC_xE010706B_LClkDpmDid1_OFFSET,
+    D0F0xBC_xE010706B_LClkDpmDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706C_TABLE [] = {
+  {
+    D0F0xBC_xE010706C_LClkDpmDid2_OFFSET,
+    D0F0xBC_xE010706C_LClkDpmDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmDid3_OFFSET,
+    D0F0xBC_xE010706C_LClkDpmDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 0,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 1,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 2,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 3,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3])
+  },
+  {
+    D0F0xBC_xE010706C_DClkDid0_OFFSET,
+    D0F0xBC_xE010706C_DClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706F_TABLE [] = {
+  {
+    D0F0xBC_xE010706F_DClkDid1_OFFSET,
+    D0F0xBC_xE010706F_DClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107070_TABLE [] = {
+  {
+    D0F0xBC_xE0107070_DClkDid2_OFFSET,
+    D0F0xBC_xE0107070_DClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107070_DClkDid3_OFFSET,
+    D0F0xBC_xE0107070_DClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107070_VClkDid0_OFFSET,
+    D0F0xBC_xE0107070_VClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107073_TABLE [] = {
+  {
+    D0F0xBC_xE0107073_VClkDid1_OFFSET,
+    D0F0xBC_xE0107073_VClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[1])
+  },
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107074_TABLE [] = {
+  {
+    D0F0xBC_xE0107074_VClkDid2_OFFSET,
+    D0F0xBC_xE0107074_VClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107074_VClkDid3_OFFSET,
+    D0F0xBC_xE0107074_VClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107077_TABLE [] = {
+  {
+    D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET,
+    D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107078_TABLE [] = {
+  {
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET,
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET,
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[0])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[1])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[2])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[3])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[4])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707B_TABLE [] = {
+  {
+    D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET,
+    D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707C_TABLE [] = {
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[1])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[2])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[3])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[4])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707F_TABLE [] = {
+  {
+    D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET,
+    D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xFF000000_TABLE [] = {
+  {
+    D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET,
+    D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, MainPllId)
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0001008_TABLE [] = {
+  {
+    D0F0xBC_xE0001008_SClkVid0_OFFSET,
+    D0F0xBC_xE0001008_SClkVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[0])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid1_OFFSET,
+    D0F0xBC_xE0001008_SClkVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[1])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid2_OFFSET,
+    D0F0xBC_xE0001008_SClkVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[2])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid3_OFFSET,
+    D0F0xBC_xE0001008_SClkVid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[3])
+  }
+};
+
+
+FUSE_TABLE_ENTRY_TN  FuseRegisterTableTN [] = {
+  {
+    D0F0xBC_xE0104158_TYPE,
+    D0F0xBC_xE0104158_ADDRESS,
+    sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104158_TABLE
+  },
+  {
+    D0F0xBC_xE010415B_TYPE,
+    D0F0xBC_xE010415B_ADDRESS,
+    sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010415B_TABLE
+  },
+  {
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104184_TABLE
+  },
+  {
+    D0F0xBC_xE0104187_TYPE,
+    D0F0xBC_xE0104187_ADDRESS,
+    sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104187_TABLE
+  },
+  {
+    D0F0xBC_xE0104188_TYPE,
+    D0F0xBC_xE0104188_ADDRESS,
+    sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104188_TABLE
+  },
+  {
+    D0F0xBC_xE0106020_TYPE,
+    D0F0xBC_xE0106020_ADDRESS,
+    sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106020_TABLE
+  },
+  {
+    D0F0xBC_xE0106023_TYPE,
+    D0F0xBC_xE0106023_ADDRESS,
+    sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106023_TABLE
+  },
+  {
+    D0F0xBC_xE0106024_TYPE,
+    D0F0xBC_xE0106024_ADDRESS,
+    sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106024_TABLE
+  },
+  {
+    D0F0xBC_xE010705C_TYPE,
+    D0F0xBC_xE010705C_ADDRESS,
+    sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010705C_TABLE
+  },
+  {
+    D0F0xBC_xE010705F_TYPE,
+    D0F0xBC_xE010705F_ADDRESS,
+    sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010705F_TABLE
+  },
+  {
+    D0F0xBC_xE0107060_TYPE,
+    D0F0xBC_xE0107060_ADDRESS,
+    sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107060_TABLE
+  },
+  {
+    D0F0xBC_xE0107063_TYPE,
+    D0F0xBC_xE0107063_ADDRESS,
+    sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107063_TABLE
+  },
+  {
+    D0F0xBC_xE0107064_TYPE,
+    D0F0xBC_xE0107064_ADDRESS,
+    sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107064_TABLE
+  },
+  {
+    D0F0xBC_xE0107067_TYPE,
+    D0F0xBC_xE0107067_ADDRESS,
+    sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107067_TABLE
+  },
+  {
+    D0F0xBC_xE0107068_TYPE,
+    D0F0xBC_xE0107068_ADDRESS,
+    sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107068_TABLE
+  },
+  {
+    D0F0xBC_xE010706B_TYPE,
+    D0F0xBC_xE010706B_ADDRESS,
+    sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706B_TABLE
+  },
+  {
+    D0F0xBC_xE010706C_TYPE,
+    D0F0xBC_xE010706C_ADDRESS,
+    sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706C_TABLE
+  },
+  {
+    D0F0xBC_xE010706F_TYPE,
+    D0F0xBC_xE010706F_ADDRESS,
+    sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706F_TABLE
+  },
+  {
+    D0F0xBC_xE0107070_TYPE,
+    D0F0xBC_xE0107070_ADDRESS,
+    sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107070_TABLE
+  },
+  {
+    D0F0xBC_xE0107073_TYPE,
+    D0F0xBC_xE0107073_ADDRESS,
+    sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107073_TABLE
+  },
+  {
+    D0F0xBC_xE0107074_TYPE,
+    D0F0xBC_xE0107074_ADDRESS,
+    sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107074_TABLE
+  },
+  {
+    D0F0xBC_xE0107077_TYPE,
+    D0F0xBC_xE0107077_ADDRESS,
+    sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107077_TABLE
+  },
+  {
+    D0F0xBC_xE0107078_TYPE,
+    D0F0xBC_xE0107078_ADDRESS,
+    sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107078_TABLE
+  },
+  {
+    D0F0xBC_xE010707B_TYPE,
+    D0F0xBC_xE010707B_ADDRESS,
+    sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707B_TABLE
+  },
+  {
+    D0F0xBC_xE010707C_TYPE,
+    D0F0xBC_xE010707C_ADDRESS,
+    sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707C_TABLE
+  },
+  {
+    D0F0xBC_xE010707F_TYPE,
+    D0F0xBC_xE010707F_ADDRESS,
+    sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707F_TABLE
+  },
+  {
+    D0F0xBC_xFF000000_TYPE,
+    D0F0xBC_xFF000000_ADDRESS,
+    sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xFF000000_TABLE
+  },
+  {
+    D0F0xBC_xE0001008_TYPE,
+    D0F0xBC_xE0001008_ADDRESS,
+    sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0001008_TABLE
+  }
+};
+
+FUSE_TABLE_TN  FuseTableTN = {
+  sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN),
+  FuseRegisterTableTN
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Load Fuse Table TN
+ *
+ *
+ * @param[out] PpFuseArray      Pointer to save fuse table
+ * @param[in]  StdHeader        Pointer to Standard configuration
+ * @retval     AGESA_STATUS
+ */
+
+STATIC VOID
+NbFuseLoadFuseTableTN (
+     OUT   PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  FUSE_TABLE_TN             *FuseTable;
+  UINTN                     RegisterIndex;
+  FuseTable = &FuseTableTN;
+  for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) {
+    UINTN   FieldIndex;
+    UINTN   FuseRegisterTableLength;
+    UINT32  FuseValue;
+    FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength;
+
+    GnbRegisterReadTN (
+      FuseTable->FuseTable[RegisterIndex].RegisterSpaceType,
+      FuseTable->FuseTable[RegisterIndex].Register,
+      &FuseValue,
+      0,
+      StdHeader
+    );
+    for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength;  FieldIndex++) {
+      FUSE_REGISTER_ENTRY_TN   RegisterEntry;
+      RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex];
+      *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) &
+                                                            ((1 << RegisterEntry.FieldWidth) - 1));
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb load fuse table
+ *
+ *
+ *
+ * @param[in] StdHeader        Pointer to Standard configuration
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbLoadFuseTableTN (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PP_FUSE_ARRAY          *PpFuseArray;
+  AGESA_STATUS           Status;
+  D18F3xA0_STRUCT        D18F3xA0;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Enter\n");
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    //Support for real fuste table
+    GnbRegisterReadTN (D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader);
+    if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealFuseTable)) {
+      NbFuseLoadFuseTableTN (PpFuseArray, StdHeader);
+      PpFuseArray->VceSateTableSupport = TRUE;
+      IDS_HDT_CONSOLE (NB_MISC, "  Processor Fused\n");
+    } else {
+      LibAmdMemCopy (PpFuseArray, &ex907 , sizeof (PP_FUSE_ARRAY), StdHeader);
+      IDS_HDT_CONSOLE (NB_MISC, "  Processor Unfuse\n");
+    }
+  } else {
+    Status = AGESA_ERROR;
+  }
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader);
+  GnbFuseTableDebugDumpTN (PpFuseArray, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Exit [0x%x]\n", Status);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Debug dump fuse table
+ *
+ *
+ * @param[out] PpFuseArray      Pointer to save fuse table
+ * @param[in]  StdHeader        Pointer to Standard configuration
+ */
+
+VOID
+GnbFuseTableDebugDumpTN (
+  IN       PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINTN   Index;
+
+  IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n");
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->LclkDpmValid[Index]  != 0) {
+      IDS_HDT_CONSOLE (
+        NB_MISC,
+        "  LCLK DID[%d] - 0x%02x (%dMHz)\n",
+        Index,
+        PpFuseArray->LclkDpmDid[Index],
+        (PpFuseArray->LclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->LclkDpmDid[Index], StdHeader) / 100) : 0
+        );
+      IDS_HDT_CONSOLE (NB_MISC, "  LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]);
+    }
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->VclkDid[Index],
+      (PpFuseArray->VclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->VclkDid[Index], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  DCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->DclkDid[Index],
+      (PpFuseArray->DclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DclkDid[Index], StdHeader) / 100) : 0
+    );
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  DISPCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->DisplclkDid[Index],
+      (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DisplclkDid[Index], StdHeader) / 100) : 0
+      );
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  ECLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->EclkDid[Index],
+      (PpFuseArray->EclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->EclkDid[Index], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCE SCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]],
+      (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCE Flags[ % d] - 0x % 02x\n",
+      Index,
+      PpFuseArray->VceFlags[Index]
+      );
+  }
+  for (Index = 0; Index < 6; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  SCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->SclkDpmDid[Index],
+      (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], StdHeader) / 100) : 0
+    );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  SCLK TDP[%d] - 0x%x \n",
+      Index,
+      PpFuseArray->SclkDpmTdpLimit[Index]
+    );
+    IDS_HDT_CONSOLE (NB_MISC, "  SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]);
+  }
+  for (Index = 0; Index < 6; Index++) {
+    IDS_HDT_CONSOLE (NB_MISC, "  State #%d\n", Index);
+  }
+  IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h
new file mode 100644
index 0000000000..5d6177f1e0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fuse table initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBFUSETABLETN_H_
+#define _GNBFUSETABLETN_H_
+
+#pragma pack (push, 1)
+
+/// Fuse field entry
+typedef struct {
+  UINT8                    FieldOffset;              ///< Field offset in fuse register
+  UINT8                    FieldWidth;               ///< Width of field
+  UINT16                   FuseOffset;               ///< destination offset in translation table
+} FUSE_REGISTER_ENTRY_TN;
+
+/// Fuse register entry
+typedef struct {
+  UINT8                    RegisterSpaceType;        ///< Register type
+  UINT32                   Register;                 ///< FCR register address
+  UINT8                    FuseRegisterTableLength;  ///< Length of field table for this register
+  FUSE_REGISTER_ENTRY_TN   *FuseRegisterTable;       ///< Pointer to field table
+} FUSE_TABLE_ENTRY_TN;
+
+/// Fuse translation table
+typedef struct {
+  UINT8                    FuseTableLength;          ///< Length of translation table
+  FUSE_TABLE_ENTRY_TN      *FuseTable;               ///< Pointer to register table
+} FUSE_TABLE_TN;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+GnbLoadFuseTableTN (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h
new file mode 100644
index 0000000000..76196f1c08
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various TN definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBINITTN_H_
+#define _GNBINITTN_H_
+
+#define D0F0xBC_x1F468_TimerPeriod_Value  100000
+#define D0F0xBC_x1F46C_BapmPeriod_Value   1
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h
new file mode 100644
index 0000000000..e6ac431378
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h
@@ -0,0 +1,200 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Tn service installation file
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNB_INIT_TN_INSTALL_H_
+#define _GNB_INIT_TN_INSTALL_H_
+
+//-----------------------------------------------------------------------
+// Specify definition used by module services
+//-----------------------------------------------------------------------
+
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbFamServices.h"
+
+//-----------------------------------------------------------------------
+// Export services
+//-----------------------------------------------------------------------
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE)
+  extern F_PCIEFMGETCOMPLEXDATALENGTH             PcieGetComplexDataLengthTN;
+  extern F_PCIEFMBUILDCOMPLEXCONFIGURATION        PcieBuildComplexConfigurationTN;
+  extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION   PcieConfigureEnginesLaneAllocationTN;
+  extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING        PcieCheckPortPciDeviceMappingTN;
+  extern F_PCIEFMMAPPORTPCIADDRESS                PcieMapPortPciAddressTN;
+  extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED      PcieCheckPortPcieLaneCanBeMuxedTN;
+  extern F_PCIEFMGETSBCONFIGINFO                  PcieGetSbConfigInfoTN;
+  PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = {
+    PcieGetComplexDataLengthTN,
+    PcieBuildComplexConfigurationTN,
+    PcieConfigureEnginesLaneAllocationTN,
+    PcieCheckPortPciDeviceMappingTN,
+    PcieMapPortPciAddressTN,
+    PcieCheckPortPcieLaneCanBeMuxedTN,
+    PcieGetSbConfigInfoTN
+  };
+
+  GNB_SERVICE GnbPcieCongigServicesTN = {
+    GnbPcieFamConfigService,
+    AMD_FAMILY_TN,
+    &GnbPcieConfigProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbPcieCongigServicesTN
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  extern F_PCIEFMGETCORECONFIGURATIONVALUE        PcieGetCoreConfigurationValueTN;
+  extern F_PCIEFMGETLINKSPEEDCAP                  PcieGetLinkSpeedCapTN;
+  extern F_PCIEFMGETNATIVEPHYLANEBITMAP           PcieGetNativePhyLaneBitmapTN;
+  extern F_PCIEFMSETLINKSPEEDCAP                  PcieSetLinkSpeedCapV4;
+
+  PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = {
+    PcieGetCoreConfigurationValueTN,
+    PcieGetLinkSpeedCapTN,
+    PcieGetNativePhyLaneBitmapTN,
+    PcieSetLinkSpeedCapV4
+  };
+
+  GNB_SERVICE GnbPcieInitServicesTN = {
+    GnbPcieFamInitService,
+    AMD_FAMILY_TN,
+    &GnbPcieInitProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbPcieInitServicesTN
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  #if IDSOPT_IDS_ENABLED == TRUE
+    #if IDSOPT_TRACING_ENABLED == TRUE
+      extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING  PcieDebugGetHostRegAddressSpaceStringTN;
+      extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING          PcieDebugGetWrapperNameStringTN;
+      extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING    PcieDebugGetCoreConfigurationStringTN;
+
+      PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = {
+        PcieDebugGetHostRegAddressSpaceStringTN,
+        PcieDebugGetWrapperNameStringTN,
+        PcieDebugGetCoreConfigurationStringTN
+      };
+
+      GNB_SERVICE GnbPcieDebugServicesTN = {
+        GnbPcieFamDebugService,
+        AMD_FAMILY_TN,
+        &GnbPcieDebugProtocolTN,
+        SERVICES_POINTER
+      };
+      #undef  SERVICES_POINTER
+      #define SERVICES_POINTER  &GnbPcieDebugServicesTN
+    #endif
+  #endif
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  extern F_GNB_REGISTER_ACCESS  GnbRegisterReadServiceTN;
+  extern F_GNB_REGISTER_ACCESS  GnbRegisterWriteServiceTN;
+
+  GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = {
+    GnbRegisterReadServiceTN,
+    GnbRegisterWriteServiceTN
+  };
+
+  GNB_SERVICE GnbRegisterAccessServicesTN = {
+    GnbRegisterAccessService,
+    AMD_FAMILY_TN,
+    &GnbRegiterAccessProtocol,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbRegisterAccessServicesTN
+
+  extern F_GNBFMCREATEIVRSENTRY    GnbCreateIvrsEntryTN;
+  extern F_GNBFMCHECKIOMMUPRESENT  GnbCheckIommuPresentTN;
+
+  GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = {
+    GnbCheckIommuPresentTN,
+    GnbCreateIvrsEntryTN
+  };
+
+  GNB_SERVICE GnbIommuConfigServicesTN = {
+    GnbIommuService,
+    AMD_FAMILY_TN,
+    &GnbIommuConfigProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbIommuConfigServicesTN
+
+#endif
+#endif  // _GNB_INIT_TN_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
new file mode 100644
index 0000000000..8f176d77b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbIommu.h"
+#include  "GnbIvrsLib.h"
+#include  "GnbSbIommuLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbIommuIvrs.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbCreateIvhdHeaderTN (
+  IN       IVRS_BLOCK_TYPE            Type,
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbCreateIvhdTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbCreateIvhdrTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbCreateIvrsEntryTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GnbCheckIommuPresentTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU unit present and enabled
+ *
+ *
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+BOOLEAN
+GnbCheckIommuPresentTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  if (GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 0, 2, 0), StdHeader)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbCreateIvrsEntryTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  IVRS_IVHD_ENTRY                   *Ivhd;
+  UINT8                             IommuCapabilityOffset;
+  UINT32                            Value;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Entry\n");
+  if (Type == IvrsIvhdBlock || Type == IvrsIvhdrBlock) {
+    // Update IVINFO
+    IommuCapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, IommuCapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
+    ((IOMMU_IVRS_HEADER *) Ivrs)->IvInfo = Value & (IVINFO_HTATSRESV_MASK | IVINFO_VASIZE_MASK | IVINFO_GASIZE_MASK | IVINFO_PASIZE_MASK);
+
+    // Address of IVHD entry
+    Ivhd = (IVRS_IVHD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength);
+    GnbCreateIvhdHeaderTN (Type, Ivhd, StdHeader);
+    if (Type == IvrsIvhdBlock) {
+      GnbCreateIvhdTN (Ivhd, StdHeader);
+    } else {
+      GnbCreateIvhdrTN (Ivhd, StdHeader);
+    }
+    ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength = ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength + Ivhd->Length;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  Type            Block type
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdHeaderTN (
+  IN       IVRS_BLOCK_TYPE            Type,
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32    Value;
+  Ivhd->Type = (UINT8) Type;
+  Ivhd->Flags = IVHD_FLAG_COHERENT | IVHD_FLAG_IOTLBSUP | IVHD_FLAG_ISOC | IVHD_FLAG_RESPASSPW | IVHD_FLAG_PASSPW | IVHD_FLAG_PPRSUB | IVHD_FLAG_PREFSUP;
+  Ivhd->Length = sizeof (IVRS_IVHD_ENTRY);
+  Ivhd->DeviceId = 0x2;
+  Ivhd->CapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
+  Ivhd->PciSegment = 0;
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x4), AccessWidth32, &Ivhd->BaseAddress, StdHeader);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x8), AccessWidth32, (UINT8 *) &Ivhd->BaseAddress + 4, StdHeader);
+  Ivhd->BaseAddress = Ivhd->BaseAddress & 0xfffffffffffffffe;
+  ASSERT (Ivhd->BaseAddress != 0x0);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
+  Ivhd->IommuInfo = (UINT16) (Value & 0x1f) | (0x13 << IVHD_INFO_UNITID_OFFSET);
+  Ivhd->IommuEfr = (0 << IVHD_EFR_XTSUP_OFFSET) | (0 << IVHD_EFR_NXSUP_OFFSET) | (1 << IVHD_EFR_GTSUP_OFFSET) |
+                   (0 << IVHD_EFR_GLXSUP_OFFSET) | (1 << IVHD_EFR_IASUP_OFFSET) | (0 << IVHD_EFR_GASUP_OFFSET) |
+                   (0 << IVHD_EFR_HESUP_OFFSET) | (0x8 << IVHD_EFR_PASMAX_OFFSET) | (0 << IVHD_EFR_MSINUMPPR_OFFSET) |
+                   (4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHD entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Start;
+  PCI_ADDR  End;
+  Start.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, 0xFF, 0x1F, 6, 0);
+  GnbIvhdAddDeviceRangeEntry (Start, End, 0, Ivhd, StdHeader);
+  SbCreateIvhdEntries (Ivhd, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdrTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+
+
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
new file mode 100644
index 0000000000..626f33d3aa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
@@ -0,0 +1,574 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbFuseTable.h"
+#include  "heapManager.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbTable.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "OptionGnb.h"
+#include  "GfxLibTN.h"
+#include  "GnbFamServices.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern GNB_TABLE ROMDATA      GnbMidInitTableTN[];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUM_DPM_STATES 8
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Registers needs to be set if no GFX PCIe ports beeing us
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to PCIe_PLATFORM_CONFIG
+ */
+
+VOID
+STATIC
+GnbIommuMidInitCheckGfxPciePorts (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  BOOLEAN               GfxPciePortUsed;
+  D0F2xF4_x57_STRUCT    D0F2xF4_x57;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n");
+  GfxPciePortUsed = FALSE;
+
+  WrapperList = PcieConfigGetChildWrapper (Pcie);
+  ASSERT (WrapperList != NULL);
+  if (WrapperList->WrapId == GFX_WRAP_ID) {
+    PCIe_ENGINE_CONFIG   *EngineList;
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieConfigIsPcieEngine (EngineList)) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber);
+        if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+           ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) {
+          // GFX PCIe ports beeing used
+          GfxPciePortUsed = TRUE;
+          IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n");
+          break;
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+  }
+
+  if (!GfxPciePortUsed) {
+    //D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set
+    GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie));
+    D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1;
+    GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to for each PCIe port
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+GnbIommuMidInitOnPortCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GNB_TOPOLOGY_INFO           TopologyInfo;
+  D0F2xFC_x07_L1_STRUCT       D0F2xFC_x07_L1;
+  D0F2xFC_x0D_L1_STRUCT       D0F2xFC_x0D_L1;
+  UINT8                       L1cfgSel;
+  TopologyInfo.PhantomFunction = FALSE;
+  TopologyInfo.PcieToPciexBridge = FALSE;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    TopologyInfo.PhantomFunction = TRUE;
+    TopologyInfo.PcieToPciexBridge = TRUE;
+  } else {
+    if (PcieConfigIsSbPcieEngine (Engine)) {
+      PCI_ADDR  StartSbPcieDev;
+      PCI_ADDR  EndSbPcieDev;
+      StartSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 0, 0);
+      EndSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 7, 0);
+      GnbGetTopologyInfoV4 (StartSbPcieDev, EndSbPcieDev, &TopologyInfo, GnbLibGetHeader (Pcie));
+    } else {
+      GnbGetTopologyInfoV4 (Engine->Type.Port.Address, Engine->Type.Port.Address, &TopologyInfo, GnbLibGetHeader (Pcie));
+    }
+  }
+  L1cfgSel = (Engine->Type.Port.CoreId == 1) ? 1 : 0;
+  if (TopologyInfo.PhantomFunction) {
+    GnbRegisterReadTN (
+      D0F2xFC_x07_L1_TYPE,
+      D0F2xFC_x07_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x07_L1.Value,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+    D0F2xFC_x07_L1.Value |= BIT0;
+    GnbRegisterWriteTN (
+      D0F2xFC_x07_L1_TYPE,
+      D0F2xFC_x07_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x07_L1.Value,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  if (TopologyInfo.PcieToPciexBridge) {
+    GnbRegisterReadTN (
+      D0F2xFC_x0D_L1_TYPE,
+      D0F2xFC_x0D_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x0D_L1.Value,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+    D0F2xFC_x0D_L1.Field.VOQPortBits = 0x7;
+    GnbRegisterWriteTN (
+      D0F2xFC_x0D_L1_TYPE,
+      D0F2xFC_x0D_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x0D_L1.Value,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Orb/Ioc Cgtt Override setting
+ *
+ *
+ * @param[in]  Property   Property
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+VOID
+STATIC
+GnbCgttOverrideTN (
+  IN      UINT32                          Property,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  UINT32                          CGINDx0_Value;
+  UINT32                          CGINDx1_Value;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  AGESA_STATUS                    Status;
+  D0F0x64_x23_STRUCT              D0F0x64_x23;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Enter\n");
+
+  CGINDx0_Value = 0xFFFFFFFF;
+  //When orb clock gating is enabled in the BIOS clear CG_ORB_cgtt_lclk_override - bit 13
+  CGINDx1_Value = 0xFFFFFFFF;
+  if ((Property & TABLE_PROPERTY_ORB_CLK_GATING) == TABLE_PROPERTY_ORB_CLK_GATING) {
+    CGINDx1_Value &= 0xFFFFDFFF;
+  }
+  //When ioc clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 15
+  if ((Property & TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) == TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) {
+    CGINDx1_Value &= 0xFFFF7FFF;
+    if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) != TABLE_PROPERTY_IOMMU_DISABLED) {
+      //only IOMMU enabled and IOC clock gating enable
+      GnbRegisterReadTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, 0, StdHeader);
+      D0F0x64_x23.Field.SoftOverrideClk0 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk1 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk3 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk4 = 1;
+      GnbRegisterWriteTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+    }
+  }
+  //When smu sclk clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 18
+  if ((Property & TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) == TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) {
+    CGINDx1_Value &= 0xFFFBFFFF;
+  }
+
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  if (Status != AGESA_FATAL) {
+    if (Gfx->GmcClockGating) {
+      //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
+      // CGINDx0, clear bit 27, bit 28
+      CGINDx0_Value &= 0xE7FFFFFF;
+      GnbRegisterWriteTN (TYPE_CGIND, 0x0, &CGINDx0_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+      // CGINDx1, clear bit 11
+      CGINDx1_Value &= 0xFFFFF7FF;
+    }
+
+  }
+
+  if (CGINDx1_Value != 0xFFFFFFFF) {
+    GnbRegisterWriteTN (TYPE_CGIND, 0x1, &CGINDx1_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Exit\n");
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * IOMMU Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GnbIommuMidInit (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n");
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (Status == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      GnbIommuMidInitOnPortCallback,
+      NULL,
+      Pcie
+      );
+  }
+
+  GnbIommuMidInitCheckGfxPciePorts (Pcie);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * IOMMU Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GnbLclkDpmInitTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PP_FUSE_ARRAY             *PpFuseArray;
+  PCI_ADDR                  GnbPciAddress;
+  UINT32                    Index;
+  UINT8                     LclkDpmMode;
+  D0F0xBC_x1F200_STRUCT     D0F0xBC_x1F200[NUM_DPM_STATES];
+  D0F0xBC_x1F208_STRUCT     D0F0xBC_x1F208[NUM_DPM_STATES];
+  D0F0xBC_x1F210_STRUCT     D0F0xBC_x1F210[NUM_DPM_STATES];
+  D0F0xBC_x1F300_STRUCT     D0F0xBC_x1F300;
+  ex1003_STRUCT      ex1003 [NUM_DPM_STATES];
+  DOUBLE                    PcieCacLut;
+  ex1072_STRUCT      ex1072 ;
+  D0F0xBC_x1FE00_STRUCT     D0F0xBC_x1FE00;
+  D0F0xBC_x1F30C_STRUCT     D0F0xBC_x1F30C;
+  D18F3x64_STRUCT           D18F3x64;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n");
+  Status = AGESA_SUCCESS;
+  LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
+  IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
+  if (LclkDpmMode == LclkDpmRcActivity) {
+    PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+    if (PpFuseArray != NULL) {
+      Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+      if (Status == AGESA_SUCCESS) {
+        GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+        //Clear DPM_EN bit in LCLK_DPM_CNTL register
+        //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM
+        GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
+        D0F0xBC_x1F300.Field.LclkDpmEn = 0x0;
+        GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        GnbSmuServiceRequestV4 (
+          GnbPciAddress,
+          SMC_MSG_CONFIG_LCLK_DPM,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          StdHeader
+          );
+
+        //Initialize LCLK states
+        LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader);
+        LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
+        LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
+
+        D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0];
+        D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]];
+        D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf;
+
+        D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1];
+        D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]];
+        D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32;
+        D0F0xBC_x1F200[5].Field.StateValid = 0x1;
+
+        D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2];
+        D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]];
+        D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32;
+        D0F0xBC_x1F200[6].Field.StateValid = 0x1;
+
+        GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader);
+        PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 );
+        IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
+        D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
+        GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 );
+        ex1003[6].Field.ex1003_0  = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
+        IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
+
+        for (Index = 0; Index < NUM_DPM_STATES; ++Index) {
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F200_TYPE,
+            D0F0xBC_x1F200_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F200[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F208_TYPE,
+            D0F0xBC_x1F208_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F208[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F210_TYPE,
+            D0F0xBC_x1F210_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F210[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            TYPE_D0F0xBC ,
+            0x1f940  + Index * 4,
+            &ex1003[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+        }
+        //Enable LCLK DPM Voltage Scaling
+        GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
+        D0F0xBC_x1F300.Field.VoltageChgEn = 0x1;
+        D0F0xBC_x1F300.Field.LclkDpmEn = 0x1;
+        D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5;
+        GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+
+        //Programming Lclk Thermal Throttling Threshold
+        GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader);
+        GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader);
+        D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8);
+        D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8);
+        GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+
+        GnbSmuServiceRequestV4 (
+          GnbPciAddress,
+          SMC_MSG_CONFIG_LCLK_DPM,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          StdHeader
+          );
+      }
+    } else {
+      Status = AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Mid Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS      Status;
+  UINT32            Property;
+  AGESA_STATUS      AgesaStatus;
+  GNB_HANDLE        *GnbHandle;
+  UINT8             SclkDid;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Enter\n");
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+
+  Property = TABLE_PROPERTY_DEAFULT;
+  Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED;
+  Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0;
+  Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? TABLE_PROPERTY_ORB_CLK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIocLclkClockGatingEnable ? TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING : 0;
+  Property |= GnbFmCheckIommuPresent (GnbHandle, StdHeader) ? 0: TABLE_PROPERTY_IOMMU_DISABLED;
+  Property |= GnbBuildOptions.SmuSclkClockGatingEnable ? TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING : 0;
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) == 0) {
+    Status = GnbEnableIommuMmioV4 (GnbHandle, StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Status = GnbIommuMidInit (StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  //
+  // Set sclk to 100Mhz
+  //
+  SclkDid = GfxRequestSclkTNS3Save (
+              GfxLibCalculateDidTN (98 * 100, StdHeader),
+              StdHeader
+              );
+
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbMidInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  //
+  // Restore Sclk
+  //
+  GfxRequestSclkTNS3Save (
+    SclkDid,
+    StdHeader
+    );
+
+  GnbCgttOverrideTN (Property, StdHeader);
+
+  Status = GnbLclkDpmInitTN (StdHeader);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
new file mode 100644
index 0000000000..efa2af1256
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
@@ -0,0 +1,128 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbNbInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbPostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbPostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS     Status;
+  PCI_ADDR         GnbAddress;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Enter\n");
+  GnbAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  Status = GnbSetTom (GnbAddress, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
new file mode 100644
index 0000000000..8d36a1f620
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
@@ -0,0 +1,1334 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64211 $   @e \$Date: 2012-01-17 23:00:25 -0600 (Tue, 17 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define GNB_IGNORED_PARAM             0xFF
+#define ORB_WRITE_ENABLE              0x100
+#define IOMMU_L1_WRITE_ENABLE         0x80000000ul
+#define IOMMU_L2_WRITE_ENABLE         0x100
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbRegisterWriteTNDump (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value
+  );
+AGESA_STATUS
+GnbRegisterReadServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GnbRegisterWriteServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Config Dct and Mp.
+ *
+ *
+ *
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[in] StdHeader          Standard configuration header
+ *
+ * @return          true - Memory Pstate context has been changed
+ * @return          false - Memory Pstate context has not been changed
+ */
+STATIC BOOLEAN
+GnbDctMpConfigTN (
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // Select DCT and memory P-state, D18F1x10C[DctCfgSel], D18F1x10C[MemPsSel]
+  D18F1x10C_STRUCT      D18F1x10C;
+  BOOLEAN               MemPsChangd;
+  ACCESS_WIDTH          Width;
+
+  MemPsChangd = FALSE;
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS),
+    Width,
+    &D18F1x10C.Value,
+    StdHeader
+  );
+
+  if ((DctCfgSel != 0xFF) && (DctCfgSel < 2)) {
+    D18F1x10C.Field.DctCfgSel = DctCfgSel;
+  }
+
+  if ((MemPsSel != 0xFF) && (MemPsSel < 2) && (D18F1x10C.Field.MemPsSel != MemPsSel)) {
+    //Switches Mem Pstate
+    D18F1x10C.Field.MemPsSel = MemPsSel;
+    MemPsChangd = TRUE;
+  }
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS),
+    Width,
+    &D18F1x10C.Value,
+    StdHeader
+  );
+
+  return MemPsChangd;
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to Read Dct Additional Data.
+ *
+ *
+ *
+ * @param[in] Address            D18F2x9c Register offset
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[out] Value             Read value
+ * @param[in] StdHeader          Standard configuration header
+ */
+STATIC VOID
+GnbDctAdditionalDataReadTN (
+  IN       UINT32              Address,
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+     OUT   VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  D18F2x98_dct0_STRUCT  D18F2x98;
+  BOOLEAN               PstateChanged;
+  ACCESS_WIDTH          Width;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  PstateChanged = GnbDctMpConfigTN (
+                    DctCfgSel,
+                    MemPsSel,
+                    Flags,
+                    StdHeader
+                  );
+
+  // Clear DctAccessWrite
+  D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF;
+  D18F2x98.Field.DctAccessWrite = 0;
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)),
+    Width,
+    &D18F2x98.Value,
+    StdHeader
+  );
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)),
+    Width,
+    Value,
+    StdHeader
+  );
+
+  if (PstateChanged) {
+    GnbDctMpConfigTN (
+      DctCfgSel,
+      ((MemPsSel == 0) ? 1 : 0),
+      Flags,
+      StdHeader
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to Write Dct Additional Data.
+ *
+ *
+ *
+ * @param[in] Address            D18F2x9c Register offset
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[in] Value              Write value
+ * @param[in] StdHeader          Standard configuration header
+ */
+STATIC VOID
+GnbDctAdditionalDataWriteTN (
+  IN       UINT32              Address,
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  D18F2x98_dct0_STRUCT  D18F2x98;
+  BOOLEAN               PstateChanged;
+  ACCESS_WIDTH          Width;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  PstateChanged = GnbDctMpConfigTN (
+                    DctCfgSel,
+                    MemPsSel,
+                    Flags,
+                    StdHeader
+                  );
+
+  // Put write data on
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)),
+    Width,
+    Value,
+    StdHeader
+  );
+
+  // Set DctAccessWrite
+  D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF;
+  D18F2x98.Field.DctAccessWrite = 1;
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)),
+    Width,
+    &D18F2x98.Value,
+    StdHeader
+  );
+
+  if (PstateChanged) {
+    GnbDctMpConfigTN (
+      DctCfgSel,
+      ((MemPsSel == 0) ? 1 : 0),
+      Flags,
+      StdHeader
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to read all register spaces.
+ *
+ *
+ *
+ * @param[in] GnbHandle          GNB handle
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             Return value
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterReadServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return GnbRegisterReadTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to read all register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             Return value
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterReadTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  ACCESS_WIDTH          Width;
+  UINT32                TempValue;
+  UINT32                TempAddress;
+  BOOLEAN               PstateChanged;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+  TempAddress = 0;
+  TempValue = 0;
+
+
+  switch (RegisterSpaceType) {
+  case TYPE_D0F0:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D0F2:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F0:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 1, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F1:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 1, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_DxF0:
+    // Treat it as complete address for ports
+    GnbLibPciRead (
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F1:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F2:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F3:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 3, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F4:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 4, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F5:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 5, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x64:
+    // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00]
+    // Write enable bit7
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x98:
+    // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00]
+    // Write enable bit8
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xBC:
+    {
+    //SMU, access D0F0xBC_x[FFFFFFFF:00000000]
+    // No write enable
+      UINT64  TempData;
+      //ASSERT ((Address < 0xE0100000 || Address > 0xE0108FFFF) && (Address & 0x3) == 0);
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS),
+        (Address & (~0x3ull)),
+        Width,
+        &TempData,
+        StdHeader
+      );
+      if ((Address & 0x3) != 0) {
+        //Non aligned access allowed to fuse block
+        GnbLibPciIndirectRead (
+          MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS),
+          (Address & (~0x3ull)) + 4,
+          Width,
+          ((UINT32 *) &TempData) + 1,
+          StdHeader
+        );
+      }
+      * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8));
+      break;
+    }
+  case TYPE_D0F0xE4:
+    // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000]
+    // No write enable
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xF4:
+    // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00].
+    // Write enable bit8
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xFC:
+    // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0]
+    // Write enable bit31
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_DxF0xE4:
+    // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00]
+    // No write enable
+    TempValue = ((Address >> 16) & 0xFF);
+    TempAddress = Address & 0xFF;
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS
+      TempAddress,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_MSR:
+    LibAmdMsrRead  (Address, Value, StdHeader);
+    break;
+
+  case TYPE_GMM:
+    ASSERT (Address < 0x40000);
+
+    if ((Address >= 0x600) && (Address <= 0x8FF)) {
+      // CG
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0xE0002000 | (Address - 0x600)),
+        Width,
+        Value,
+        StdHeader
+      );
+    } else {
+      // SRBM
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0x80080000 | (Address & 0x3FFFF)),
+        Width,
+        Value,
+        StdHeader
+      );
+    }
+    break;
+
+  case TYPE_D18F2x9C_dct0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0:
+    GnbDctMpConfigTN (
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct0_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1:
+    GnbDctMpConfigTN (
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct1_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_CGIND:
+    // CG index
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8F8 - 0x600)),
+      Width,
+      &Address,
+      StdHeader
+    );
+    // CG data
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8FC - 0x600)),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+
+
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to write all register spaces.
+ *
+ *
+ *
+ * @param[in] GnbHandle          GnbHandle
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             The value to write
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterWriteServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return GnbRegisterWriteTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to write all register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             The value to write
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterWriteTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+
+  ACCESS_WIDTH          Width;
+  UINT32                TempValue;
+  UINT32                TempAddress;
+  PCI_ADDR              PciAddress;
+  BOOLEAN               PstateChanged;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+  TempAddress = 0;
+  TempValue = 0;
+
+  GNB_DEBUG_CODE (
+    GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
+  );
+
+  switch (RegisterSpaceType) {
+  case TYPE_D0F0:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D0F2:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F0:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 1, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F1:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 1, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_DxF0:
+    // Treat it as complete address for ports
+    GnbLibPciWrite (
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F1:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F2:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F3:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 3, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F4:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 4, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F5:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 5, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x64:
+    // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00]
+    // Write enable bit7
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      Address | IOC_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x98:
+    // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00]
+    // Write enable bit8
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS),
+      Address | ORB_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xBC:
+    //SMU, access D0F0xBC_x[FFFFFFFF:00000000]
+    // No write enable
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xE4:
+    // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000]
+    // No write enable
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xF4:
+    // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00].
+    // Write enable bit8
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS
+      Address | IOMMU_L2_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xFC:
+    // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0]
+    // Write enable bit31
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS
+      Address | IOMMU_L1_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_DxF0xE4:
+    // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00]
+    // No write enable
+    TempValue = ((Address >> 16) & 0xFF);
+    TempAddress = Address & 0xFF;
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS
+      TempAddress,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_MSR:
+    LibAmdMsrWrite  (Address, Value, StdHeader);
+    break;
+
+  case TYPE_GMM:
+    ASSERT (Address < 0x40000);
+
+    if ((Address >= 0x600) && (Address <= 0x8FF)) {
+      // CG
+      GnbLibPciIndirectWrite (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0xE0002000 | (Address - 0x600)),
+        Width,
+        Value,
+        StdHeader
+      );
+    } else {
+      // SRBM
+      GnbLibPciIndirectWrite (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0x80080000 | (Address & 0x3FFFF)),
+        Width,
+        Value,
+        StdHeader
+      );
+    }
+    break;
+
+  case TYPE_D18F2x9C_dct0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0:
+    GnbDctMpConfigTN (
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct0_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1:
+    GnbDctMpConfigTN (
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct1_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+      1,
+      1,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_CGIND:
+    // CG index
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8F8 - 0x600)),
+      Width,
+      &Address,
+      StdHeader
+    );
+    // CG data
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8FC - 0x600)),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_SMU_MSG:
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+    GnbSmuServiceRequestV4 (PciAddress, (UINT8) Address, Flags, StdHeader);
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to dump all write register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset
+ * @param[in] Value              The value to write
+ */
+VOID
+GnbRegisterWriteTNDump (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value
+  )
+{
+  IDS_HDT_CONSOLE (NB_MISC, "  R WRITE Space %s  Address 0x%04x, Value 0x%04x\n",
+    (RegisterSpaceType == TYPE_D0F0) ? "TYPE_D0F0" : (
+    (RegisterSpaceType == TYPE_D0F0x64) ? "TYPE_D0F0x64" : (
+    (RegisterSpaceType == TYPE_D0F0x98) ? "TYPE_D0F0x98" : (
+    (RegisterSpaceType == TYPE_D0F0xBC) ? "TYPE_D0F0xBC" : (
+    (RegisterSpaceType == TYPE_D0F0xE4) ? "TYPE_D0F0xE4" : (
+    (RegisterSpaceType == TYPE_DxF0) ? "TYPE_DxF0" : (
+    (RegisterSpaceType == TYPE_DxF0xE4) ? "TYPE_DxF0xE4" : (
+    (RegisterSpaceType == TYPE_D0F2) ? "TYPE_D0F2" : (
+    (RegisterSpaceType == TYPE_D0F2xF4) ? "TYPE_D0F2xF4" : (
+    (RegisterSpaceType == TYPE_D0F2xFC) ? "TYPE_D0F2xFC" : (
+    (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : (
+    (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : (
+    (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : (
+    (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : (
+    (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : (
+    (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : (
+    (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : (
+    (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : (
+    (RegisterSpaceType == TYPE_GMM) ? "TYPE_GMM" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : (
+    (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))))),
+    Address,
+    *((UINT32*)Value)
+  );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h
new file mode 100644
index 0000000000..6de5c469ae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBREGISTERACCTN_H_
+#define _GNBREGISTERACCTN_H_
+
+AGESA_STATUS
+GnbRegisterWriteTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GnbRegisterReadTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+// Marco
+// DxF0 Port space
+#define PORT_SPACE(Dev, Offset) MAKE_SBDFO (0, 0, Dev, 0, Offset)
+
+// DxF0xE4 Port indirect space
+#define PORTINDT_SPACE(Dev , Func, Offset) ((((UINT32) (Dev)) << 16) | (((UINT32) (Func)) << 8) | \
+                                             ((UINT32)(Offset)))
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
new file mode 100644
index 0000000000..8c44a71d89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
@@ -0,0 +1,14126 @@
+/**
+ * @file
+ *
+ * SMU firmware
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65874 $   @e \$Date: 2012-02-26 21:24:59 -0600 (Sun, 26 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBSMUFIRMWARETN_H_
+#define _GNBSMUFIRMWARETN_H_
+
+UINT32  FirmwareTN[] = {
+ 0x000a0004,
+ 0x00000040,
+ 0x000036a1,
+ 0x00010100,
+ 0xeee2b111,
+ 0x724cbe84,
+ 0xf7cde4cd,
+ 0xbf04e85e,
+ 0x9bdebdfc,
+ 0x0001d7f4,
+ 0x0001d904,
+ 0x00000000,
+ 0x0001d925,
+ 0x0001d934,
+ 0x0001d848,
+ 0x0001da6c,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xaa55aa55,
+ 0x98000000,
+ 0x98000000,
+ 0xd0000000,
+ 0x78010001,
+ 0x38210100,
+ 0xd0e10000,
+ 0xd1210000,
+ 0xf8000039,
+ 0x5b9d0000,
+ 0xf8000062,
+ 0xf80033ff,
+ 0xe0000098,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf8000044,
+ 0xf8003456,
+ 0xe000007d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0xf8000052,
+ 0xf800344e,
+ 0xe0000088,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf8000034,
+ 0xf8003458,
+ 0xe000006d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf800002c,
+ 0xf8003462,
+ 0xe0000065,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0xf8000025,
+ 0x34010002,
+ 0xf8003476,
+ 0xe000005d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf800001c,
+ 0xf8003464,
+ 0xe0000055,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x98000000,
+ 0x781c0001,
+ 0x3b9cebfc,
+ 0x781a0002,
+ 0x3b5a5b80,
+ 0x78010001,
+ 0x3821db84,
+ 0x78030001,
+ 0x3863e038,
+ 0x44230004,
+ 0x58200000,
+ 0x34210004,
+ 0xe3fffffd,
+ 0x34010000,
+ 0x34020000,
+ 0x78030001,
+ 0x3863fe80,
+ 0x58610000,
+ 0x58610018,
+ 0x34030000,
+ 0xf80002b5,
+ 0xf800013d,
+ 0x379cff80,
+ 0x5b810004,
+ 0x5b820008,
+ 0x5b83000c,
+ 0x5b840010,
+ 0x5b850014,
+ 0x5b860018,
+ 0x5b87001c,
+ 0x5b880020,
+ 0x5b890024,
+ 0x5b8a0028,
+ 0x5b9e0078,
+ 0x5b9f007c,
+ 0x2b810080,
+ 0x5b810074,
+ 0xbb800800,
+ 0x34210080,
+ 0x5b810070,
+ 0x98210800,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x379cff80,
+ 0x5b810004,
+ 0x5b820008,
+ 0x5b83000c,
+ 0x5b840010,
+ 0x5b850014,
+ 0x5b860018,
+ 0x5b87001c,
+ 0x5b880020,
+ 0x5b890024,
+ 0x5b8a0028,
+ 0x5b8b002c,
+ 0x5b8c0030,
+ 0x5b8d0034,
+ 0x5b8e0038,
+ 0x5b8f003c,
+ 0x5b900040,
+ 0x5b910044,
+ 0x5b920048,
+ 0x5b93004c,
+ 0x5b940050,
+ 0x5b950054,
+ 0x5b960058,
+ 0x5b97005c,
+ 0x5b980060,
+ 0x5b990064,
+ 0x5b9a0068,
+ 0x5b9b006c,
+ 0x5b9e0078,
+ 0x5b9f007c,
+ 0x2b810080,
+ 0x5b810074,
+ 0xbb800800,
+ 0x34210080,
+ 0x5b810070,
+ 0x98210800,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x34010002,
+ 0xd0010000,
+ 0x2b810004,
+ 0x2b820008,
+ 0x2b83000c,
+ 0x2b840010,
+ 0x2b850014,
+ 0x2b860018,
+ 0x2b87001c,
+ 0x2b880020,
+ 0x2b890024,
+ 0x2b8a0028,
+ 0x2b9d0074,
+ 0x2b9e0078,
+ 0x2b9f007c,
+ 0x2b9c0070,
+ 0x34000000,
+ 0xc3c00000,
+ 0x34010002,
+ 0xd0010000,
+ 0x2b810004,
+ 0x2b820008,
+ 0x2b83000c,
+ 0x2b840010,
+ 0x2b850014,
+ 0x2b860018,
+ 0x2b87001c,
+ 0x2b880020,
+ 0x2b890024,
+ 0x2b8a0028,
+ 0x2b8b002c,
+ 0x2b8c0030,
+ 0x2b8d0034,
+ 0x2b8e0038,
+ 0x2b8f003c,
+ 0x2b900040,
+ 0x2b910044,
+ 0x2b920048,
+ 0x2b93004c,
+ 0x2b940050,
+ 0x2b950054,
+ 0x2b960058,
+ 0x2b97005c,
+ 0x2b980060,
+ 0x2b990064,
+ 0x2b9a0068,
+ 0x2b9b006c,
+ 0x2b9d0074,
+ 0x2b9e0078,
+ 0x2b9f007c,
+ 0x2b9c0070,
+ 0x34000000,
+ 0xc3e00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0xf80000cc,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0xf80000cd,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfff4,
+ 0x5b8b000c,
+ 0x5b8c0008,
+ 0x5b9d0004,
+ 0x780c0001,
+ 0xb9801000,
+ 0x3842db84,
+ 0x34010001,
+ 0x58410000,
+ 0x90201000,
+ 0x90401800,
+ 0x340b0001,
+ 0xa0621800,
+ 0x34050000,
+ 0x44650018,
+ 0x78020001,
+ 0x3842db8c,
+ 0xb8402000,
+ 0xa1630800,
+ 0x44200009,
+ 0x28430000,
+ 0x5c60000c,
+ 0x90201000,
+ 0xa5600800,
+ 0xa0411000,
+ 0xd0220000,
+ 0xd04b0000,
+ 0xe3ffffee,
+ 0x3d6b0001,
+ 0x34a50001,
+ 0x34840008,
+ 0x34420008,
+ 0xe3fffff2,
+ 0x28820004,
+ 0xb8a00800,
+ 0xd8600000,
+ 0xd04b0000,
+ 0xe3ffffe4,
+ 0x398cdb84,
+ 0x34010000,
+ 0x59810000,
+ 0x2b8b000c,
+ 0x2b8c0008,
+ 0x2b9d0004,
+ 0x379c000c,
+ 0xc3a00000,
+ 0x78020001,
+ 0x3842db88,
+ 0x28440000,
+ 0x5c80000f,
+ 0x34010001,
+ 0x58410000,
+ 0x78030001,
+ 0xb8801000,
+ 0x3863db8c,
+ 0x3401001f,
+ 0x58620000,
+ 0x58620004,
+ 0x3421ffff,
+ 0x34630008,
+ 0x4c20fffc,
+ 0x90000800,
+ 0x38210001,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0xb8205800,
+ 0xb8406800,
+ 0xb8606000,
+ 0xfbffffe5,
+ 0x34010001,
+ 0xbc2b2000,
+ 0x3402fffe,
+ 0x3401001f,
+ 0x502b0002,
+ 0xe0000019,
+ 0x90001800,
+ 0x3401fffe,
+ 0xa0611800,
+ 0xd0030000,
+ 0x78010001,
+ 0x3d620003,
+ 0x3821db8c,
+ 0xb4411000,
+ 0x584d0004,
+ 0x584c0000,
+ 0x90200800,
+ 0xa4801000,
+ 0x5d800003,
+ 0xa0220800,
+ 0xe0000002,
+ 0xb8240800,
+ 0xd0210000,
+ 0x78010001,
+ 0x3821db84,
+ 0x28210000,
+ 0x38630001,
+ 0x5c200002,
+ 0xd0030000,
+ 0x34020000,
+ 0xb8400800,
+ 0x2b8b0010,
+ 0x2b8c000c,
+ 0x2b8d0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0x34020001,
+ 0xbc411000,
+ 0x3403fffe,
+ 0xa4402000,
+ 0x3402001f,
+ 0x50410002,
+ 0xe000000f,
+ 0x90001000,
+ 0x3401fffe,
+ 0xa0411000,
+ 0xd0020000,
+ 0x90200800,
+ 0xa0240800,
+ 0xd0210000,
+ 0x78010001,
+ 0x3821db84,
+ 0x28210000,
+ 0x38420001,
+ 0x5c200002,
+ 0xd0020000,
+ 0x34030000,
+ 0xb8600800,
+ 0xc3a00000,
+ 0x379cfff8,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0xb8205800,
+ 0xfbffffa4,
+ 0x34010001,
+ 0xbc2b1800,
+ 0x3402fffe,
+ 0x3401001f,
+ 0x502b0002,
+ 0xe000000f,
+ 0x90001000,
+ 0x3401fffe,
+ 0xa0411000,
+ 0xd0020000,
+ 0x90200800,
+ 0xb8230800,
+ 0xd0210000,
+ 0x78010001,
+ 0x3821db84,
+ 0x28210000,
+ 0x38420001,
+ 0x5c200002,
+ 0xd0020000,
+ 0x34020000,
+ 0xb8400800,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0008,
+ 0xc3a00000,
+ 0x379cfff8,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0xb8205800,
+ 0xfbffff86,
+ 0x90001000,
+ 0x3401fffe,
+ 0xa0411000,
+ 0xd0020000,
+ 0xd02b0000,
+ 0x78010001,
+ 0x3821db84,
+ 0x28210000,
+ 0x38420001,
+ 0x5c200002,
+ 0xd0020000,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0008,
+ 0xc3a00000,
+ 0x90000800,
+ 0x3402fffe,
+ 0xa0220800,
+ 0xd0010000,
+ 0x90200800,
+ 0x34020000,
+ 0xd0220000,
+ 0xc3a00000,
+ 0x34080001,
+ 0xac000007,
+ 0x34010001,
+ 0xd0810000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0xc3a00000,
+ 0x34010001,
+ 0xd0610000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x78038000,
+ 0x78018000,
+ 0x38630000,
+ 0x38210040,
+ 0x58610180,
+ 0x34010000,
+ 0x58610100,
+ 0x78014000,
+ 0x34020001,
+ 0x58620104,
+ 0x38210003,
+ 0x5861010c,
+ 0x34010003,
+ 0x5861010c,
+ 0x34010002,
+ 0x58610110,
+ 0x34010004,
+ 0x5861000c,
+ 0x28610004,
+ 0x38210002,
+ 0x58610004,
+ 0xc3a00000,
+ 0x379cffe8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x7805e000,
+ 0xb8a00800,
+ 0x38211000,
+ 0x28210004,
+ 0x780d0001,
+ 0x780c0001,
+ 0x202101fc,
+ 0x00220002,
+ 0x780b0001,
+ 0x780e0001,
+ 0x780f0001,
+ 0x78040001,
+ 0x74410007,
+ 0x39add848,
+ 0x398cd7f4,
+ 0x396bd925,
+ 0x39ced904,
+ 0x39eff160,
+ 0x3884e02c,
+ 0x5c200003,
+ 0x34022000,
+ 0xe0000014,
+ 0x7441003f,
+ 0x5c200003,
+ 0x3c42000a,
+ 0xe0000010,
+ 0x7441005f,
+ 0x5c200006,
+ 0x3c42000b,
+ 0x7801ffff,
+ 0x38210000,
+ 0xb4411000,
+ 0xe0000009,
+ 0x3c41000c,
+ 0x7443007e,
+ 0x7802fffc,
+ 0x38420000,
+ 0xb4221000,
+ 0x44600003,
+ 0x78020008,
+ 0x38420000,
+ 0x7801e000,
+ 0x38213048,
+ 0x58220000,
+ 0x7801e000,
+ 0x58820000,
+ 0x38212000,
+ 0x28210000,
+ 0x2021007f,
+ 0xb8201000,
+ 0x5c200007,
+ 0x38a51000,
+ 0x28a20004,
+ 0x78010003,
+ 0x3821f800,
+ 0xa0411000,
+ 0x0042000b,
+ 0xb8400800,
+ 0xf80029f4,
+ 0x7801e000,
+ 0x38211000,
+ 0x283d001c,
+ 0x7802e000,
+ 0x38422208,
+ 0x28410000,
+ 0x78090001,
+ 0x78030001,
+ 0x38210001,
+ 0x58410000,
+ 0x3929f000,
+ 0x3863ffff,
+ 0x340a0000,
+ 0x592a0000,
+ 0x35290004,
+ 0x55230002,
+ 0xe3fffffd,
+ 0x78020001,
+ 0x78018000,
+ 0x3842f15c,
+ 0x38210000,
+ 0x58410000,
+ 0x78030001,
+ 0x7806030a,
+ 0x38c60000,
+ 0x3863f180,
+ 0x78010001,
+ 0x58660000,
+ 0x34070a00,
+ 0x3821f184,
+ 0x7805e000,
+ 0x58270000,
+ 0x38a52028,
+ 0x28a10000,
+ 0x78040001,
+ 0x78037fff,
+ 0x20217f00,
+ 0x00210008,
+ 0x3884f318,
+ 0x31810004,
+ 0x38630000,
+ 0x78020001,
+ 0x58830000,
+ 0x3842f31c,
+ 0x78010001,
+ 0x58460000,
+ 0x3821f320,
+ 0x58270000,
+ 0x28a10000,
+ 0x7802e000,
+ 0x384221b4,
+ 0x2021007f,
+ 0x31a10004,
+ 0x28410000,
+ 0x7807e000,
+ 0x38e71008,
+ 0x202101fe,
+ 0x00210001,
+ 0x316a000a,
+ 0x31610009,
+ 0x31610008,
+ 0x28e20000,
+ 0x7805ff00,
+ 0x38a50000,
+ 0xa0451000,
+ 0x00420018,
+ 0x780c0001,
+ 0x3162000b,
+ 0x78010001,
+ 0xb9801000,
+ 0x3821f6c4,
+ 0x31ea0002,
+ 0x3406ffff,
+ 0x38420000,
+ 0x58220000,
+ 0x58260004,
+ 0x58250008,
+ 0x5826000c,
+ 0x58250010,
+ 0x582a0014,
+ 0x582a0018,
+ 0x582a001c,
+ 0x582a0020,
+ 0x582a0024,
+ 0x582a0028,
+ 0x582a002c,
+ 0x582a0030,
+ 0x582a0034,
+ 0x582a0038,
+ 0x5826003c,
+ 0x58250040,
+ 0x582a0058,
+ 0x58260044,
+ 0x58250048,
+ 0x582a004c,
+ 0x582a0050,
+ 0x582a0054,
+ 0x78020001,
+ 0x3842f39c,
+ 0x78010001,
+ 0x584a0000,
+ 0x3821f478,
+ 0x582a0000,
+ 0x78020001,
+ 0x3842f47c,
+ 0x78010001,
+ 0x584a0000,
+ 0x3821f438,
+ 0x58260000,
+ 0x78020001,
+ 0x3842f43c,
+ 0x78010001,
+ 0x58450000,
+ 0x3821f6bc,
+ 0x582a0000,
+ 0x78020001,
+ 0x3842f610,
+ 0x78010001,
+ 0x584a0000,
+ 0x3821f614,
+ 0x582a0000,
+ 0x78020001,
+ 0x3842f388,
+ 0x34010389,
+ 0x58410000,
+ 0x78040001,
+ 0x78030001,
+ 0x3884f38c,
+ 0x38630110,
+ 0x78010001,
+ 0x58830000,
+ 0x3821f140,
+ 0x3808ffff,
+ 0x78020001,
+ 0x58280000,
+ 0x34040100,
+ 0x3842f150,
+ 0x58440000,
+ 0x78010001,
+ 0x3821f14c,
+ 0x78020001,
+ 0x58240000,
+ 0x3842f154,
+ 0x7803e000,
+ 0x58440000,
+ 0x38630000,
+ 0x28620000,
+ 0x78010030,
+ 0x38210000,
+ 0xb8411000,
+ 0x78010001,
+ 0x58620000,
+ 0x3821f600,
+ 0x582a0000,
+ 0x78020001,
+ 0x3403007e,
+ 0x3842f604,
+ 0x78010001,
+ 0x58430000,
+ 0x3821f608,
+ 0x58230000,
+ 0x78020001,
+ 0x3842f5fc,
+ 0x34010008,
+ 0x58410000,
+ 0x78030001,
+ 0x3863f5f4,
+ 0x34010fff,
+ 0x58610000,
+ 0x78020001,
+ 0x3842f628,
+ 0x34010383,
+ 0x58410000,
+ 0x78030001,
+ 0x3863f194,
+ 0x34020001,
+ 0x78010001,
+ 0x58620000,
+ 0x3821f190,
+ 0x58280000,
+ 0x28e10000,
+ 0x78020001,
+ 0x29c30018,
+ 0xa0250800,
+ 0x00210018,
+ 0x3842f384,
+ 0x58410000,
+ 0xb9404800,
+ 0xbcc90800,
+ 0x35290001,
+ 0x58610000,
+ 0x75210005,
+ 0x34630004,
+ 0x4420fffb,
+ 0x03a4000a,
+ 0x03a30010,
+ 0x2084003f,
+ 0xa4801000,
+ 0x3401ffc0,
+ 0xb8411000,
+ 0x59c20010,
+ 0x20630003,
+ 0x78010001,
+ 0x31c30006,
+ 0x59c4001c,
+ 0x3821f900,
+ 0x34050003,
+ 0x34080000,
+ 0x34090006,
+ 0x34060015,
+ 0x3407000c,
+ 0x34020001,
+ 0x3026003b,
+ 0x3029003a,
+ 0x30250034,
+ 0x30270033,
+ 0x30280032,
+ 0x30250037,
+ 0x30250036,
+ 0x30280035,
+ 0x30220031,
+ 0x78040001,
+ 0x7803301a,
+ 0x3884f1a0,
+ 0x38632415,
+ 0x78018008,
+ 0x58830000,
+ 0x398c0000,
+ 0x38210000,
+ 0x582c0e60,
+ 0xf8002f1c,
+ 0xf8002e4b,
+ 0xf8001f8b,
+ 0x78010001,
+ 0x78020001,
+ 0x3842edfc,
+ 0x3821ec00,
+ 0xf8002de8,
+ 0xf8002e3b,
+ 0xb8205800,
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+ 0x59610004,
+ 0x2b8b0010,
+ 0x2b8c000c,
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+ 0xc3a00000,
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+ 0x5b8e0038,
+ 0x5b8f0034,
+ 0x5b900030,
+ 0x5b91002c,
+ 0x5b920028,
+ 0x5b930024,
+ 0x5b940020,
+ 0x5b95001c,
+ 0x5b960018,
+ 0x5b970014,
+ 0x5b980010,
+ 0x5b99000c,
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+ 0x5b9d0004,
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+ 0xb8209800,
+ 0xf80020cd,
+ 0xb8209000,
+ 0x7801e000,
+ 0x38213034,
+ 0x28210000,
+ 0x78020001,
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+ 0x66e10000,
+ 0x3ab5f42c,
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+ 0x5c200017,
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+ 0x2a430050,
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+ 0x88222800,
+ 0x78040001,
+ 0xb8803000,
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+ 0x38c6dd2c,
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+ 0x44250212,
+ 0x29820000,
+ 0x2a61001c,
+ 0x78040001,
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+ 0x1421000b,
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+ 0x2ce1003c,
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+ 0x00410018,
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+ 0x2a410014,
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+ 0x3863f428,
+ 0x28620000,
+ 0x78010001,
+ 0x3821dd84,
+ 0x5b820010,
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+ 0x78060001,
+ 0xb42b2000,
+ 0xb42a1800,
+ 0x38c6dea8,
+ 0x0c820000,
+ 0xb4260800,
+ 0x2c210000,
+ 0x34a50001,
+ 0x74a20006,
+ 0x35290002,
+ 0x35080002,
+ 0x0c610000,
+ 0x4440ffd0,
+ 0x2cc4000c,
+ 0x2ce3000c,
+ 0x78020001,
+ 0x0cc4000e,
+ 0x0ce3000e,
+ 0x3842f66a,
+ 0x0c430000,
+ 0x2cc6000c,
+ 0x78010001,
+ 0x3821f67a,
+ 0x0c260000,
+ 0xe0000003,
+ 0x31c60008,
+ 0x31e60008,
+ 0x2b8b0034,
+ 0x2b8c0030,
+ 0x2b8d002c,
+ 0x2b8e0028,
+ 0x2b8f0024,
+ 0x2b900020,
+ 0x2b91001c,
+ 0x2b920018,
+ 0x2b930014,
+ 0x2b940010,
+ 0x2b95000c,
+ 0x2b960008,
+ 0x2b9d0004,
+ 0x379c0034,
+ 0xc3a00000,
+ 0x379cfff8,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0xf800196a,
+ 0xb8202000,
+ 0x78010001,
+ 0x3821f628,
+ 0x28250000,
+ 0x7803e020,
+ 0x38630000,
+ 0x20a103ff,
+ 0x3c210002,
+ 0x78020001,
+ 0xb4230800,
+ 0x3842f850,
+ 0x2843004c,
+ 0x28210000,
+ 0x780b0001,
+ 0x00620010,
+ 0x202107ff,
+ 0x00210003,
+ 0x00630018,
+ 0x396bf430,
+ 0x204200ff,
+ 0x54410014,
+ 0x780100ff,
+ 0x38210000,
+ 0xa0a10800,
+ 0x0021000f,
+ 0x2025000e,
+ 0x29610000,
+ 0x20210001,
+ 0x5c200017,
+ 0x28820044,
+ 0x3403fff1,
+ 0x28810040,
+ 0xa0431000,
+ 0xb8451000,
+ 0x58820044,
+ 0xf8001949,
+ 0x29610000,
+ 0x38210001,
+ 0x59610000,
+ 0xe000000c,
+ 0x5023000b,
+ 0x29610000,
+ 0x3402fffe,
+ 0x3403fff1,
+ 0xa0220800,
+ 0x59610000,
+ 0x28820044,
+ 0x28810040,
+ 0xa0431000,
+ 0x58820044,
+ 0xf800193a,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0008,
+ 0xc3a00000,
+ 0x78060001,
+ 0x38c6dec0,
+ 0x40c40000,
+ 0xb8204000,
+ 0x208300ff,
+ 0x74610002,
+ 0x7c670003,
+ 0x34850001,
+ 0x5c200003,
+ 0x30c50000,
+ 0xc3a00000,
+ 0x78050001,
+ 0x7c610004,
+ 0x38a5d8f8,
+ 0x34840001,
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+ 0x30c40000,
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+ 0x30a80006,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884d8f8,
+ 0x34030000,
+ 0x5c230004,
+ 0x30c30000,
+ 0x30820004,
+ 0x30820006,
+ 0xc3a00000,
+ 0x379cffe0,
+ 0x5b8b0020,
+ 0x5b8c001c,
+ 0x5b8d0018,
+ 0x5b8e0014,
+ 0x5b8f0010,
+ 0x5b90000c,
+ 0x5b910008,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x78020001,
+ 0x3821dec4,
+ 0x3842dec5,
+ 0x40210000,
+ 0x40420000,
+ 0x780f0001,
+ 0x78110001,
+ 0xb8220800,
+ 0x39eff5f8,
+ 0x3a31f5fc,
+ 0x202d00ff,
+ 0x5da00068,
+ 0x78100001,
+ 0xba007000,
+ 0x39cedecc,
+ 0x29cb0000,
+ 0x29610070,
+ 0xf800190c,
+ 0x29cc0000,
+ 0x59610074,
+ 0x29810068,
+ 0xf8001908,
+ 0x29c40000,
+ 0x5981006c,
+ 0x28820074,
+ 0x2881006c,
+ 0x00420013,
+ 0x00210003,
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+ 0x5c410052,
+ 0x78010001,
+ 0x3821dec0,
+ 0x302d0000,
+ 0x29e50000,
+ 0x2883006c,
+ 0x28860068,
+ 0x00a20006,
+ 0x00610003,
+ 0x20420003,
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+ 0x4c220011,
+ 0x00a10001,
+ 0x3402ffe7,
+ 0xa0621000,
+ 0x20210018,
+ 0xb8411000,
+ 0x5882006c,
+ 0xb8c00800,
+ 0xf80018de,
+ 0x29c50000,
+ 0x29e40000,
+ 0x3403ff3f,
+ 0x28a2006c,
+ 0x28a10068,
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+ 0xa0431000,
+ 0xe0000010,
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+ 0x3402ff3f,
+ 0xa0621000,
+ 0xb8411000,
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+ 0x00840001,
+ 0x28a10068,
+ 0xa0431000,
+ 0x20840018,
+ 0xb8441000,
+ 0x58a2006c,
+ 0xf80018c4,
+ 0x78010001,
+ 0xb8205800,
+ 0x396bdec2,
+ 0x41610000,
+ 0x7c210001,
+ 0x5c20000c,
+ 0x3a10decc,
+ 0x2a040000,
+ 0x3403fffc,
+ 0x2882007c,
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+ 0xa0431000,
+ 0x38420001,
+ 0x5882007c,
+ 0xf80018b5,
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+ 0x31610000,
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+ 0x2a210000,
+ 0x3402fffd,
+ 0x78030001,
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+ 0x5a210000,
+ 0x3863ded0,
+ 0x28620000,
+ 0x78010001,
+ 0x38216250,
+ 0x58410028,
+ 0x3401000a,
+ 0x32210000,
+ 0xe0000004,
+ 0xb9a00800,
+ 0x34020001,
+ 0xfbffff68,
+ 0x2b8b0020,
+ 0x2b8c001c,
+ 0x2b8d0018,
+ 0x2b8e0014,
+ 0x2b8f0010,
+ 0x2b90000c,
+ 0x2b910008,
+ 0x2b9d0004,
+ 0x379c0020,
+ 0xc3a00000,
+ 0x379cffe8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x780c0001,
+ 0x398cdecc,
+ 0x298b0000,
+ 0x780d0001,
+ 0x780e0001,
+ 0x29610068,
+ 0x39adf5f8,
+ 0x39cef5fc,
+ 0xf8001891,
+ 0x78020001,
+ 0x5961006c,
+ 0x3842dec4,
+ 0x40410000,
+ 0x78030001,
+ 0x3863dec5,
+ 0x40620000,
+ 0xb8220800,
+ 0x202500ff,
+ 0x5ca0004f,
+ 0x29880000,
+ 0x78060001,
+ 0x38c6dec0,
+ 0x2904006c,
+ 0x29030074,
+ 0xb8a00800,
+ 0x00840003,
+ 0x00630013,
+ 0x34020001,
+ 0x20630003,
+ 0x20840003,
+ 0x780b0001,
+ 0x780f0001,
+ 0x5c640040,
+ 0x30c50000,
+ 0x2904006c,
+ 0x29a30000,
+ 0x3401ffe7,
+ 0xa0813000,
+ 0x20620003,
+ 0x3401ff3f,
+ 0x00630002,
+ 0xa0813800,
+ 0x3c420003,
+ 0x29090068,
+ 0x00840003,
+ 0x20630003,
+ 0xb8c23000,
+ 0x3c650006,
+ 0xb9200800,
+ 0x20840003,
+ 0xb8c01000,
+ 0x4c83000e,
+ 0x5906006c,
+ 0xf8001856,
+ 0x29850000,
+ 0x29a40000,
+ 0x3403ff3f,
+ 0x28a2006c,
+ 0x3c840004,
+ 0x28a10068,
+ 0xa0431000,
+ 0x208400c0,
+ 0xb8441000,
+ 0x58a2006c,
+ 0xe0000010,
+ 0xb8e53800,
+ 0xb9200800,
+ 0xb8e01000,
+ 0x5907006c,
+ 0xf8001846,
+ 0x29840000,
+ 0x29a30000,
+ 0x3401ffe7,
+ 0x2882006c,
+ 0x20630003,
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+ 0xa0411000,
+ 0x28810068,
+ 0xb8431000,
+ 0x5882006c,
+ 0xf800183b,
+ 0x78010001,
+ 0x3821d8f8,
+ 0x34020000,
+ 0x30220004,
+ 0x30220006,
+ 0x29c10000,
+ 0x396bded0,
+ 0x39ef6250,
+ 0x38210002,
+ 0x59c10000,
+ 0x29610000,
+ 0x3403000a,
+ 0x582f0028,
+ 0x31c30000,
+ 0xe0000002,
+ 0xfbfffef6,
+ 0x2b8b0018,
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+ 0x2b8d0010,
+ 0x2b8e000c,
+ 0x2b8f0008,
+ 0x2b9d0004,
+ 0x379c0018,
+ 0xc3a00000,
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+ 0x5b9d0004,
+ 0x78010001,
+ 0x78020001,
+ 0x3821dec4,
+ 0x3842dec5,
+ 0x40210000,
+ 0x40420000,
+ 0x78030001,
+ 0x780a0001,
+ 0xb8220800,
+ 0x3863decc,
+ 0x394af5fc,
+ 0x202500ff,
+ 0x5ca0001f,
+ 0x28630000,
+ 0x78090001,
+ 0x78080001,
+ 0x2864006c,
+ 0x78070001,
+ 0x341d0001,
+ 0x28630074,
+ 0x00840006,
+ 0x78060001,
+ 0x00630013,
+ 0x3929ded0,
+ 0x3908dec0,
+ 0x38e7d8f8,
+ 0x38c66528,
+ 0xb8a01000,
+ 0xbba00800,
+ 0x20840003,
+ 0x20630003,
+ 0x5c64000b,
+ 0x29210000,
+ 0x30fd0004,
+ 0x31050000,
+ 0x58260028,
+ 0x31450000,
+ 0x29410000,
+ 0x3402fffe,
+ 0xa0220800,
+ 0x59410000,
+ 0xe0000002,
+ 0xfbfffec1,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821ded8,
+ 0x28220000,
+ 0x780c0001,
+ 0x78058000,
+ 0x78010001,
+ 0x3821f6c0,
+ 0x40420008,
+ 0x40210003,
+ 0x780d0001,
+ 0x398cdecc,
+ 0x38a50000,
+ 0x39adf5fc,
+ 0x4841002b,
+ 0x29840000,
+ 0x2883006c,
+ 0x28810068,
+ 0xb8651800,
+ 0xb8601000,
+ 0x5883006c,
+ 0xf80017d9,
+ 0x298b0000,
+ 0x29610070,
+ 0xf80017e4,
+ 0x59610074,
+ 0x29810000,
+ 0x34070003,
+ 0x78060001,
+ 0x2822006c,
+ 0x78040001,
+ 0x340a0001,
+ 0x28210074,
+ 0x00420006,
+ 0x38c6671c,
+ 0x00210013,
+ 0x34090000,
+ 0x38846788,
+ 0x34080002,
+ 0xa0270800,
+ 0xa0471000,
+ 0x78050001,
+ 0x78030001,
+ 0x5c220008,
+ 0x3863ded0,
+ 0x28610000,
+ 0x38a5d8f8,
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+ 0x3863decc,
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+ 0x28610068,
+ 0xa0441000,
+ 0x5862006c,
+ 0xf800177b,
+ 0x29610000,
+ 0x3402ffef,
+ 0xa0220800,
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+ 0x29820000,
+ 0x00210018,
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+ 0x20830001,
+ 0x7c610000,
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+ 0x28c20000,
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+ 0x78010001,
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+ 0xe0000002,
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+ 0x44200022,
+ 0x00410008,
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+ 0x3884d8f8,
+ 0x30810000,
+ 0x40c10002,
+ 0x30810001,
+ 0x28a20000,
+ 0x00410001,
+ 0x20210001,
+ 0x5c200003,
+ 0x40810009,
+ 0x5c20000f,
+ 0x34030001,
+ 0x30830009,
+ 0x28a10000,
+ 0x78020001,
+ 0x3842ded0,
+ 0xb8230800,
+ 0x58a10000,
+ 0x28420000,
+ 0x78010001,
+ 0x30830006,
+ 0x38215e74,
+ 0x58410028,
+ 0x30a30000,
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+ 0x00210012,
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+ 0xe0000006,
+ 0x00420012,
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+ 0x20420001,
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+ 0x5c200014,
+ 0x28a10000,
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+ 0x30830006,
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+ 0x78020001,
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+ 0x58a10000,
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+ 0x78020001,
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+ 0xf800169c,
+ 0x3a31decc,
+ 0x5a210000,
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+ 0x3a10f850,
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+ 0x780f0001,
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+ 0x30a70001,
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+ 0xf8001676,
+ 0x5961006c,
+ 0x2a2b0000,
+ 0x29610078,
+ 0xf8001672,
+ 0x5961007c,
+ 0x2a01008c,
+ 0x29c20000,
+ 0x00210018,
+ 0x30410002,
+ 0x29c10000,
+ 0x302c0006,
+ 0x41e10003,
+ 0x32010090,
+ 0x41ef0002,
+ 0x320f0095,
+ 0xe0000005,
+ 0x3164000a,
+ 0x31a4000a,
+ 0x29c10000,
+ 0x30240006,
+ 0x78010001,
+ 0x3821f5fc,
+ 0x34020008,
+ 0x58220000,
+ 0x2b8b0020,
+ 0x2b8c001c,
+ 0x2b8d0018,
+ 0x2b8e0014,
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+ 0x3842f38c,
+ 0x59610324,
+ 0x28410000,
+ 0x780e0001,
+ 0x780d0001,
+ 0x39cef604,
+ 0x39adf198,
+ 0x2021ff00,
+ 0x5c200005,
+ 0x3781001f,
+ 0x3782001e,
+ 0xfbfffe22,
+ 0xb8202800,
+ 0x340105ff,
+ 0x5961003c,
+ 0x41a10001,
+ 0xb9601000,
+ 0x00210002,
+ 0x20210001,
+ 0x5c200007,
+ 0x28410214,
+ 0x20210400,
+ 0x5c20fffe,
+ 0x28410218,
+ 0x20210400,
+ 0x5c20fffb,
+ 0x398cf38c,
+ 0x29810000,
+ 0x2021ff00,
+ 0x5c200005,
+ 0x4381001f,
+ 0x4382001e,
+ 0xb8a01800,
+ 0xf8000ed5,
+ 0x41a10001,
+ 0x7802e030,
+ 0x38420000,
+ 0x00210002,
+ 0x20210001,
+ 0x5c200007,
+ 0x28410214,
+ 0x20212000,
+ 0x4420fffe,
+ 0x28410218,
+ 0x20212000,
+ 0xe3fffffa,
+ 0x7803e030,
+ 0x38630000,
+ 0x28610324,
+ 0x3402fffd,
+ 0x39eff150,
+ 0xa0220800,
+ 0x58610324,
+ 0x34010000,
+ 0x59e10000,
+ 0x41c10003,
+ 0x3402fffb,
+ 0xa0220800,
+ 0x31c10003,
+ 0xfbfffd8e,
+ 0x2b8b0018,
+ 0x2b8c0014,
+ 0x2b8d0010,
+ 0x2b8e000c,
+ 0x2b8f0008,
+ 0x2b9d0004,
+ 0x379c001c,
+ 0xc3a00000,
+ 0x379cfff8,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0x780b0001,
+ 0xb9601800,
+ 0x3863f14c,
+ 0x34010001,
+ 0x78020001,
+ 0x58610000,
+ 0x3842f604,
+ 0x40410003,
+ 0x38210008,
+ 0x30410003,
+ 0xfbfffd78,
+ 0x78010001,
+ 0x3821dee4,
+ 0x28230000,
+ 0x7802e030,
+ 0x38420000,
+ 0x7801e000,
+ 0x38212020,
+ 0x58230000,
+ 0x28410324,
+ 0x78040008,
+ 0xb8401800,
+ 0x38210001,
+ 0x58410324,
+ 0x340106ff,
+ 0x58410024,
+ 0x38840000,
+ 0x2861020c,
+ 0xa0240800,
+ 0x4420fffe,
+ 0x28610324,
+ 0x3402fffe,
+ 0x396bf14c,
+ 0xa0220800,
+ 0x58610324,
+ 0x34010100,
+ 0x7803e000,
+ 0x59610000,
+ 0x38630010,
+ 0x28610000,
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+ 0xa0240800,
+ 0x58610000,
+ 0x28620000,
+ 0x78010040,
+ 0x38210000,
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+ 0x58620000,
+ 0x28610000,
+ 0xa0240800,
+ 0x58610000,
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+ 0x379c0008,
+ 0xc3a00000,
+ 0x379cffe4,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e01000,
+ 0x3842f14c,
+ 0x34010101,
+ 0x780be030,
+ 0x58410000,
+ 0x396b0000,
+ 0x29610324,
+ 0x7802e000,
+ 0x38422208,
+ 0x38210001,
+ 0x59610324,
+ 0x28410000,
+ 0x780c0001,
+ 0xb9801800,
+ 0x38210001,
+ 0x3863f38c,
+ 0x58410000,
+ 0x28610000,
+ 0x780e0001,
+ 0x780d0001,
+ 0x39cef604,
+ 0x39adf198,
+ 0x2021ff00,
+ 0x5c200005,
+ 0x3781001f,
+ 0x3782001e,
+ 0xfbfffd8b,
+ 0xb8202000,
+ 0x340105ff,
+ 0x59610024,
+ 0x41a10001,
+ 0x00210003,
+ 0x20210001,
+ 0x5c200005,
+ 0xb9601000,
+ 0x2841020c,
+ 0x20210400,
+ 0x5c20fffe,
+ 0x398cf38c,
+ 0x29810000,
+ 0x2021ff00,
+ 0x5c200005,
+ 0x4381001f,
+ 0x4382001e,
+ 0xb8801800,
+ 0xf8000e41,
+ 0x41a10001,
+ 0x00210003,
+ 0x20210001,
+ 0x5c200006,
+ 0x7802e030,
+ 0x38420000,
+ 0x2841020c,
+ 0x20212000,
+ 0x4420fffe,
+ 0x7803e030,
+ 0x38630000,
+ 0x28610324,
+ 0x3402fffe,
+ 0x34040000,
+ 0xa0220800,
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+ 0x39eff14c,
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+ 0x28430000,
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+ 0x7803e000,
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+ 0x386322fc,
+ 0x28650000,
+ 0x7802ffc7,
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+ 0x5b8b000c,
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+ 0x5b8d0004,
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+ 0x004b0018,
+ 0xb8404800,
+ 0x780c0001,
+ 0xc80b1000,
+ 0xb8206800,
+ 0x20a500ff,
+ 0x398cf6c8,
+ 0x34420007,
+ 0x34070008,
+ 0x34060000,
+ 0x3cc80003,
+ 0x340a00ff,
+ 0xc8a80800,
+ 0xbd412000,
+ 0xb5a61800,
+ 0x34c60001,
+ 0x74c10004,
+ 0x50a7000a,
+ 0x30640000,
+ 0x30640005,
+ 0x35050008,
+ 0x51670006,
+ 0x95420800,
+ 0xa0810800,
+ 0x30610005,
+ 0x30610000,
+ 0xe0000004,
+ 0x34e70008,
+ 0x34420008,
+ 0x4420ffed,
+ 0x01280001,
+ 0x34060000,
+ 0xb5a61800,
+ 0x21250001,
+ 0x40610000,
+ 0x64a70000,
+ 0x44200014,
+ 0xb5861000,
+ 0xa4202000,
+ 0x5ce00005,
+ 0x40410000,
+ 0xa0810800,
+ 0x30410000,
+ 0xe0000002,
+ 0x30650000,
+ 0x21020001,
+ 0x64410000,
+ 0xb5862000,
+ 0x5c200007,
+ 0x40610005,
+ 0x40820008,
+ 0xa4200800,
+ 0xa0220800,
+ 0x30810008,
+ 0xe0000002,
+ 0x30620005,
+ 0x34c60001,
+ 0x74c10004,
+ 0x4420ffe6,
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+ 0x4041003e,
+ 0x40440046,
+ 0x4043003d,
+ 0x40450045,
+ 0xb8240800,
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+ 0xb8651800,
+ 0xb8230800,
+ 0x0c410002,
+ 0xc3a00000,
+ 0x780600ff,
+ 0x38c6ffff,
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+ 0x5c250002,
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+ 0xb8a20800,
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+ 0x4420000b,
+ 0x50830002,
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+ 0x28e20000,
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+ 0xc3a00000,
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+ 0x780c0001,
+ 0xc80b1000,
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+ 0x20a500ff,
+ 0x398cf6c8,
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+ 0x34060000,
+ 0x3cc80003,
+ 0x340a00ff,
+ 0xc8a80800,
+ 0xbd412000,
+ 0xb5a61800,
+ 0x34c60001,
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+ 0x51670006,
+ 0x95420800,
+ 0xa0810800,
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+ 0x01270001,
+ 0x34060000,
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+ 0x21210001,
+ 0x40650000,
+ 0x64240000,
+ 0x44a00012,
+ 0xb5861000,
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+ 0x30410000,
+ 0xe0000002,
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+ 0xb5862000,
+ 0x5c200006,
+ 0x40620005,
+ 0x40810008,
+ 0xb8220800,
+ 0x30810008,
+ 0xe0000002,
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+ 0x34c60001,
+ 0x74c10004,
+ 0x4420ffe8,
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+ 0xc3a00000,
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+ 0x5b8e0038,
+ 0x5b8f0034,
+ 0x5b900030,
+ 0x5b91002c,
+ 0x5b920028,
+ 0x5b930024,
+ 0x5b940020,
+ 0x5b95001c,
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+ 0x5b970014,
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+ 0x5b99000c,
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+ 0x34160000,
+ 0xb7760800,
+ 0x40210000,
+ 0x4420008b,
+ 0x78170001,
+ 0x3ece0002,
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+ 0x3821d7e0,
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+ 0x356c0011,
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+ 0xfbfffc3b,
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+ 0xfbfffc37,
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+ 0x356b0002,
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+ 0xfbfffc33,
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+ 0x7801e000,
+ 0x38211000,
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+ 0x20214000,
+ 0x4420000b,
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+ 0xfbfffc23,
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+ 0x3a620200,
+ 0xfbfffc20,
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+ 0x340105dc,
+ 0xf80010cb,
+ 0xa1f17800,
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+ 0xbb001000,
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+ 0xfbfffbcb,
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+ 0xfbfffbc4,
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+ 0xfbfffbb8,
+ 0x36100001,
+ 0x76010004,
+ 0x4420ffee,
+ 0x36d60001,
+ 0x76c10004,
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+ 0x2b900030,
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+ 0x2b940020,
+ 0x2b95001c,
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+ 0x379c004c,
+ 0xc3a00000,
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+ 0x5b8d0024,
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+ 0x5b920010,
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+ 0x34030000,
+ 0x78120001,
+ 0x33830034,
+ 0xb8208000,
+ 0x3a52f6c8,
+ 0x5b830040,
+ 0x33830044,
+ 0x5b830038,
+ 0x3383003c,
+ 0x5b830030,
+ 0x20840001,
+ 0xb8606800,
+ 0x20490001,
+ 0xb60d3800,
+ 0x40e10000,
+ 0x34080000,
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+ 0x5c280003,
+ 0x40e10005,
+ 0x44280027,
+ 0xb64d3000,
+ 0x40c10038,
+ 0x40c20040,
+ 0xb8220800,
+ 0x202100ff,
+ 0x5c200007,
+ 0x37810044,
+ 0xb42d1000,
+ 0x34010001,
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+ 0x3041fffc,
+ 0xb8201800,
+ 0xb9230800,
+ 0x64210000,
+ 0x5c20000b,
+ 0x40c10038,
+ 0x40e30000,
+ 0x37820030,
+ 0xa4200800,
+ 0xb44d1000,
+ 0xa0230800,
+ 0x34050001,
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+ 0xb8880800,
+ 0x64210000,
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+ 0xb8207000,
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+ 0x379c0014,
+ 0xc3a00000,
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+ 0x5b8b001c,
+ 0x5b8c0018,
+ 0x5b8d0014,
+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
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+ 0x34030000,
+ 0x78040001,
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+ 0x5b830020,
+ 0x33830024,
+ 0xb8606000,
+ 0x20470001,
+ 0x3884f6c8,
+ 0x37880020,
+ 0xb5ac1000,
+ 0x40430000,
+ 0x44600010,
+ 0xb50c3000,
+ 0x34050001,
+ 0x5ce00003,
+ 0x40810038,
+ 0x5c20000b,
+ 0x40810038,
+ 0xa4200800,
+ 0xa0230800,
+ 0x44230002,
+ 0x40c50000,
+ 0x30c50000,
+ 0x40420000,
+ 0x40810038,
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+ 0x30810038,
+ 0x358c0001,
+ 0x75810004,
+ 0x34840001,
+ 0x4420ffeb,
+ 0x34011b58,
+ 0xf8000f75,
+ 0x340c0000,
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+ 0x78010001,
+ 0x3821df20,
+ 0xb4617000,
+ 0x37900020,
+ 0xb60c0800,
+ 0x78020001,
+ 0x40210000,
+ 0x3842d7e0,
+ 0xb4621800,
+ 0x340fffdf,
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+ 0x29c20000,
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+ 0x20a1000f,
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+ 0x358c0001,
+ 0x34020001,
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+ 0x28840000,
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+ 0x3801c00b,
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+ 0xfbfffefd,
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+ 0x4420fff0,
+ 0x3801c350,
+ 0xf8000eb2,
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+ 0x28840000,
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+ 0x34040000,
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+ 0x2041000f,
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+ 0x34010000,
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+ 0x78140001,
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+ 0x41810040,
+ 0x41630005,
+ 0x3782003c,
+ 0xa4200800,
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+ 0xb42d1800,
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+ 0x44200006,
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+ 0x78010001,
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+ 0x37900034,
+ 0x40610000,
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+ 0xb60d2000,
+ 0xb8402800,
+ 0x35ad0001,
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+ 0x41620002,
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+ 0x75a10004,
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+ 0x944c1000,
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+ 0x3821d7e0,
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+ 0x3c420018,
+ 0x34216005,
+ 0xfbfff7b5,
+ 0x75810007,
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+ 0x4420001b,
+ 0x340c0000,
+ 0x3da30002,
+ 0x78010001,
+ 0x3821d7e0,
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+ 0x78010001,
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+ 0xb4617000,
+ 0xb5ed1000,
+ 0x40410000,
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+ 0x20210001,
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+ 0x358c0001,
+ 0x5c200009,
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+ 0xb5635800,
+ 0x3561400f,
+ 0xfbfff797,
+ 0x29c20014,
+ 0x3561400a,
+ 0xfbfff794,
+ 0x75810007,
+ 0x4420ffe8,
+ 0x35ad0001,
+ 0x75a10002,
+ 0x4420ffe1,
+ 0xfbfffe7c,
+ 0x2b8b0030,
+ 0x2b8c002c,
+ 0x2b8d0028,
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+ 0x2b8f0020,
+ 0x2b90001c,
+ 0x2b910018,
+ 0x2b920014,
+ 0x2b930010,
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+ 0x2b950008,
+ 0x2b9d0004,
+ 0x379c0040,
+ 0xc3a00000,
+ 0x379cffa4,
+ 0x5b8b0044,
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+ 0x5b8d003c,
+ 0x5b8e0038,
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+ 0x5b900030,
+ 0x5b91002c,
+ 0x5b920028,
+ 0x5b930024,
+ 0x5b940020,
+ 0x5b95001c,
+ 0x5b960018,
+ 0x5b970014,
+ 0x5b980010,
+ 0x5b99000c,
+ 0x5b9b0008,
+ 0x5b9d0004,
+ 0xb8209000,
+ 0x78160001,
+ 0x34010000,
+ 0x3ad6f6c8,
+ 0x78170001,
+ 0x781b0001,
+ 0x78150001,
+ 0x78140001,
+ 0x3381004c,
+ 0xb840c000,
+ 0x3af7f3c4,
+ 0x3b7bf438,
+ 0x3ab5f710,
+ 0x3a94f718,
+ 0x5b810058,
+ 0x3381005c,
+ 0x5b810050,
+ 0x33810054,
+ 0x5b810048,
+ 0xb8207000,
+ 0xbac08000,
+ 0xba406800,
+ 0x41a10000,
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+ 0x7c2100ff,
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+ 0x78130001,
+ 0x3dcf0002,
+ 0xba600800,
+ 0x3821d7e0,
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+ 0x282c0000,
+ 0x780b0001,
+ 0x396bdf20,
+ 0x3581000b,
+ 0xfbfff747,
+ 0xb5eb5800,
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+ 0x3821d7e0,
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+ 0xb4230800,
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+ 0x34216005,
+ 0xfbfff728,
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+ 0x00210018,
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+ 0x4440ffef,
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+ 0x44200018,
+ 0x40a20000,
+ 0x34030001,
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+ 0xa4401000,
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+ 0xa4601800,
+ 0xa0230800,
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+ 0xb42e1000,
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+ 0x204200ff,
+ 0x34040001,
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+ 0x40240000,
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+ 0x38218014,
+ 0xfbfff409,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff3fe,
+ 0xb9c00800,
+ 0xb9a01000,
+ 0xfbfffb62,
+ 0xb9c00800,
+ 0xb9a01000,
+ 0xfbfff85a,
+ 0xb9a01000,
+ 0xb9c00800,
+ 0xfbfff93f,
+ 0xb9c00800,
+ 0xfbfff79e,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff3ef,
+ 0x39eff39c,
+ 0x29e10000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e400016,
+ 0x3a31f6c4,
+ 0x2a210000,
+ 0x3a100000,
+ 0xa0300800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba405800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff3da,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff3d1,
+ 0x2b8b0024,
+ 0x2b8c0020,
+ 0x2b8d001c,
+ 0x2b8e0018,
+ 0x2b8f0014,
+ 0x2b900010,
+ 0x2b91000c,
+ 0x2b920008,
+ 0x2b9d0004,
+ 0x379c0034,
+ 0xc3a00000,
+ 0x379cffd4,
+ 0x5b8b001c,
+ 0x5b8c0018,
+ 0x5b8d0014,
+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f6c4,
+ 0x28220000,
+ 0x780e00ff,
+ 0x780d0001,
+ 0x34010000,
+ 0x33810029,
+ 0x33810020,
+ 0x33810021,
+ 0x33810022,
+ 0x33810023,
+ 0x33810024,
+ 0x33810025,
+ 0x33810026,
+ 0x33810027,
+ 0x33810028,
+ 0xb9c00800,
+ 0x38210000,
+ 0x39adf39c,
+ 0xa0411000,
+ 0x29a30000,
+ 0x00420010,
+ 0x20610007,
+ 0x205000ff,
+ 0x44200009,
+ 0x00620010,
+ 0x00610018,
+ 0x204200ff,
+ 0xfbfff6ee,
+ 0x29a10000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffd7a,
+ 0x29a20000,
+ 0x20410003,
+ 0x4420001d,
+ 0x20410008,
+ 0x5c20001b,
+ 0x78010131,
+ 0x38218014,
+ 0xfbfff399,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff38e,
+ 0x29a20000,
+ 0x378c0020,
+ 0xb9800800,
+ 0xfbfff6f2,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfffaee,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfff7e6,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfff8cb,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff37d,
+ 0x29a10000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e000016,
+ 0x39eff6c4,
+ 0x29e10000,
+ 0x39ce0000,
+ 0xa02e0800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba005800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff369,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff360,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b9d0004,
+ 0x379c002c,
+ 0xc3a00000,
+ 0x379cffe8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f6c4,
+ 0x28220000,
+ 0x780d0131,
+ 0x780b0001,
+ 0x780100ff,
+ 0x38210000,
+ 0x39ad8010,
+ 0x396bf688,
+ 0xa0410800,
+ 0x44200084,
+ 0x780eff00,
+ 0xb9c00800,
+ 0x3821ffff,
+ 0xa0410800,
+ 0x5c20007f,
+ 0xb8206000,
+ 0xb5ac0800,
+ 0xfbfff341,
+ 0x59610000,
+ 0x358c0001,
+ 0x75810007,
+ 0x356b0004,
+ 0x4420fffa,
+ 0x78010201,
+ 0x38210011,
+ 0x780b0001,
+ 0xfbfff338,
+ 0x396bf6a8,
+ 0x59610000,
+ 0x78010111,
+ 0x38210012,
+ 0x780b0001,
+ 0xfbfff332,
+ 0x396bdf10,
+ 0x59610000,
+ 0x78010111,
+ 0x38210013,
+ 0xfbfff32d,
+ 0x59610004,
+ 0x78010211,
+ 0x38210012,
+ 0xfbfff329,
+ 0x59610008,
+ 0x78010211,
+ 0x38210013,
+ 0xfbfff325,
+ 0x5961000c,
+ 0x78010321,
+ 0x78028100,
+ 0x38420000,
+ 0x38210009,
+ 0xfbfff324,
+ 0x78010321,
+ 0x78028100,
+ 0x38420000,
+ 0x3821000a,
+ 0xfbfff31f,
+ 0x78010131,
+ 0x34020100,
+ 0x38218011,
+ 0xfbfff31b,
+ 0x78010132,
+ 0x78022000,
+ 0x7803f000,
+ 0x38420000,
+ 0x38630000,
+ 0x38218014,
+ 0xfbfff322,
+ 0x78010130,
+ 0x78021000,
+ 0x7803f000,
+ 0x38420000,
+ 0x38630000,
+ 0x38218014,
+ 0xfbfff31b,
+ 0x78010130,
+ 0x78021000,
+ 0x7803f000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff314,
+ 0x78010111,
+ 0x3402fffe,
+ 0x38210010,
+ 0xfbfff309,
+ 0x78010211,
+ 0x3402fffe,
+ 0x38210010,
+ 0xfbfff305,
+ 0x78010132,
+ 0x78023000,
+ 0x7803f000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff305,
+ 0x78010132,
+ 0x34020001,
+ 0x38218071,
+ 0xfbfff30a,
+ 0x7801e000,
+ 0x38212028,
+ 0x28220000,
+ 0x34010064,
+ 0x204b007f,
+ 0xf80003c1,
+ 0xf80003ac,
+ 0x7804e000,
+ 0xb8801800,
+ 0x3863000c,
+ 0x28610000,
+ 0x7802e030,
+ 0x38420000,
+ 0x38210004,
+ 0x58610000,
+ 0x340105ff,
+ 0x5841000c,
+ 0x28410204,
+ 0x20210400,
+ 0x5c20fffe,
+ 0xb8801800,
+ 0x3863000c,
+ 0x28620000,
+ 0xb9600800,
+ 0x39ceffff,
+ 0x38420003,
+ 0x58620000,
+ 0xf8000397,
+ 0x78020001,
+ 0x3842f604,
+ 0x28410000,
+ 0x3403fffd,
+ 0xa0230800,
+ 0x58410000,
+ 0xfbfff291,
+ 0xb9e01000,
+ 0x3842f6c4,
+ 0x28410000,
+ 0xa02e0800,
+ 0x58410000,
+ 0x2b8b0018,
+ 0x2b8c0014,
+ 0x2b8d0010,
+ 0x2b8e000c,
+ 0x2b8f0008,
+ 0x2b9d0004,
+ 0x379c0018,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c200003,
+ 0xfbffff5b,
+ 0xfbfff99e,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f47c,
+ 0x40210003,
+ 0x78030001,
+ 0x78020001,
+ 0x7c210001,
+ 0x34040000,
+ 0x3863f39c,
+ 0x3842f6c4,
+ 0x5c240006,
+ 0x30440000,
+ 0x28610000,
+ 0x20210010,
+ 0x5c240002,
+ 0xfbffff46,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cffd8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x34010000,
+ 0x780e0001,
+ 0x33810025,
+ 0x3381001c,
+ 0x3381001d,
+ 0x3381001e,
+ 0x3381001f,
+ 0x33810020,
+ 0x33810021,
+ 0x33810022,
+ 0x33810023,
+ 0x33810024,
+ 0x39cef478,
+ 0x29c20000,
+ 0x7803ff00,
+ 0x3863ffff,
+ 0x00410018,
+ 0xb8403800,
+ 0x3c210002,
+ 0x204cffff,
+ 0x34210008,
+ 0x202100ff,
+ 0x3c220010,
+ 0xa1836000,
+ 0x3c210018,
+ 0x00e40010,
+ 0xb9826000,
+ 0x780f0001,
+ 0x780d0001,
+ 0xb9816000,
+ 0x39eff6c4,
+ 0x39adf6c8,
+ 0x208400ff,
+ 0x34050000,
+ 0x01810010,
+ 0x94851000,
+ 0x34210001,
+ 0x202100ff,
+ 0x34a50001,
+ 0x20420001,
+ 0x3c210010,
+ 0x74a60003,
+ 0x64420000,
+ 0x44400004,
+ 0xa1836000,
+ 0xb9816000,
+ 0x44c0fff4,
+ 0x01820010,
+ 0x01810018,
+ 0x204200ff,
+ 0xc8410800,
+ 0x34250001,
+ 0x780100ff,
+ 0xb8201800,
+ 0x3c420018,
+ 0x3863ffff,
+ 0xa1836000,
+ 0x74a10003,
+ 0xb9826000,
+ 0x5c200010,
+ 0x00e10010,
+ 0xb8603000,
+ 0x202400ff,
+ 0x94851000,
+ 0x01810018,
+ 0x34a50001,
+ 0x34210001,
+ 0x20420001,
+ 0x3c210018,
+ 0x74a30003,
+ 0x64420000,
+ 0x5c400004,
+ 0xa1866000,
+ 0xb9816000,
+ 0x4460fff5,
+ 0x21810003,
+ 0x44200032,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210008,
+ 0x5c20002d,
+ 0x378b001c,
+ 0xb9600800,
+ 0xb9801000,
+ 0xfbfff539,
+ 0x34050001,
+ 0x37860022,
+ 0x40c1fffb,
+ 0x40c20000,
+ 0xb5a52000,
+ 0xb8220800,
+ 0x202100ff,
+ 0x202300f0,
+ 0x2021000f,
+ 0x44200005,
+ 0x40810010,
+ 0x202100f0,
+ 0x30810010,
+ 0xe0000006,
+ 0xb5a51000,
+ 0x44600004,
+ 0x40410010,
+ 0x2021000f,
+ 0x30410010,
+ 0x40c1fffb,
+ 0x40c20000,
+ 0x34a50001,
+ 0x74a30004,
+ 0xb8220800,
+ 0x34c60001,
+ 0x202100ff,
+ 0x5c200002,
+ 0x4460ffe7,
+ 0x41c20000,
+ 0x34010003,
+ 0x4c220002,
+ 0xe0000006,
+ 0x29e20000,
+ 0x780100ff,
+ 0x38210000,
+ 0xa0411000,
+ 0x44400004,
+ 0xb9600800,
+ 0xb9801000,
+ 0xfbfffa95,
+ 0x41c10000,
+ 0x68210003,
+ 0x5c20000a,
+ 0x21810004,
+ 0x44200008,
+ 0xfbfff550,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffeb2,
+ 0x2b8b0018,
+ 0x2b8c0014,
+ 0x2b8d0010,
+ 0x2b8e000c,
+ 0x2b8f0008,
+ 0x2b9d0004,
+ 0x379c0028,
+ 0xc3a00000,
+ 0x379cffe0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x780d0001,
+ 0x39adf6c4,
+ 0x29a10000,
+ 0x780b0001,
+ 0x396bf478,
+ 0x34010000,
+ 0x3381001d,
+ 0x33810014,
+ 0x33810015,
+ 0x33810016,
+ 0x33810017,
+ 0x33810018,
+ 0x33810019,
+ 0x3381001a,
+ 0x3381001b,
+ 0x3381001c,
+ 0x41660000,
+ 0x78040001,
+ 0x3884f6c8,
+ 0x20c10001,
+ 0x64210000,
+ 0x5c200003,
+ 0x34c1ffff,
+ 0x202600ff,
+ 0x780c0001,
+ 0x3cc20002,
+ 0xb9800800,
+ 0x3821f39c,
+ 0x28230000,
+ 0x34420008,
+ 0x204200ff,
+ 0x3c490010,
+ 0x34410007,
+ 0x3c210018,
+ 0x00c20001,
+ 0xb9214800,
+ 0x34460001,
+ 0x20630008,
+ 0x5c60003a,
+ 0xb4c42800,
+ 0x40a80010,
+ 0x40a40000,
+ 0x40a10018,
+ 0x40a30008,
+ 0x40a20020,
+ 0xa5003800,
+ 0xa0e42000,
+ 0xa0280800,
+ 0xa0e31800,
+ 0xb8810800,
+ 0xa0481000,
+ 0xb8431000,
+ 0x30a10000,
+ 0x78010001,
+ 0x7cc30001,
+ 0x30a20008,
+ 0x3821f6c7,
+ 0x44600005,
+ 0x7cc10002,
+ 0x5c200009,
+ 0x78010001,
+ 0x3821f6c6,
+ 0x40230000,
+ 0x40a20028,
+ 0xa0e32000,
+ 0xa0481000,
+ 0xb8821000,
+ 0x30220000,
+ 0x40a30000,
+ 0x40a10038,
+ 0x34020000,
+ 0x37870014,
+ 0x30a20010,
+ 0x98230800,
+ 0xb4e62000,
+ 0x30810000,
+ 0x40a30008,
+ 0x40a10040,
+ 0x37850020,
+ 0xb4a61000,
+ 0x98230800,
+ 0x3041fff9,
+ 0x40820000,
+ 0xb8220800,
+ 0x202100ff,
+ 0x4420000b,
+ 0x41620000,
+ 0x39290003,
+ 0x34010003,
+ 0x4c220002,
+ 0xe0000003,
+ 0x41a10001,
+ 0x44200004,
+ 0xb8e00800,
+ 0xb9201000,
+ 0xfbfffa1c,
+ 0x41610000,
+ 0x68210003,
+ 0x5c200008,
+ 0x398cf39c,
+ 0x29810000,
+ 0x34020000,
+ 0x31a20000,
+ 0x20210010,
+ 0x5c220002,
+ 0xfbfffe3b,
+ 0x2b8b0010,
+ 0x2b8c000c,
+ 0x2b8d0008,
+ 0x2b9d0004,
+ 0x379c0020,
+ 0xc3a00000,
+ 0x379cffe4,
+ 0x5b8b000c,
+ 0x5b8c0008,
+ 0x5b9d0004,
+ 0x34010000,
+ 0x780c0001,
+ 0x33810019,
+ 0x33810010,
+ 0x33810011,
+ 0x33810012,
+ 0x33810013,
+ 0x33810014,
+ 0x33810015,
+ 0x33810016,
+ 0x33810017,
+ 0x33810018,
+ 0x398cf39c,
+ 0x29820000,
+ 0x20410003,
+ 0x20430008,
+ 0x44200008,
+ 0x378b0010,
+ 0xb9600800,
+ 0x5c600005,
+ 0xfbfff46f,
+ 0x29820000,
+ 0xb9600800,
+ 0xfbfff9f0,
+ 0x29810000,
+ 0x00210002,
+ 0x20210001,
+ 0x64210000,
+ 0x5c200006,
+ 0xfbfff4ab,
+ 0x29810000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffe0f,
+ 0x2b8b000c,
+ 0x2b8c0008,
+ 0x2b9d0004,
+ 0x379c001c,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f630,
+ 0x28210000,
+ 0x2021ff00,
+ 0x002b0008,
+ 0x34010003,
+ 0x502b0002,
+ 0xe0000025,
+ 0x7801e000,
+ 0x38212028,
+ 0x28220000,
+ 0x34010064,
+ 0x204d007f,
+ 0xf800022b,
+ 0xf8000216,
+ 0x5d600004,
+ 0x780c0130,
+ 0x398c8060,
+ 0xe000000f,
+ 0x7d610001,
+ 0x5c200004,
+ 0x780c0131,
+ 0x398c8060,
+ 0xe000000a,
+ 0x7d610002,
+ 0x5c200004,
+ 0x780c0132,
+ 0x398c8060,
+ 0xe0000005,
+ 0x7d610003,
+ 0x5c200003,
+ 0x780c0133,
+ 0x398c8060,
+ 0x34020001,
+ 0xb9800800,
+ 0xfbfff141,
+ 0x34020001,
+ 0xb9800800,
+ 0xfbfff15c,
+ 0xb9800800,
+ 0x34020004,
+ 0xfbfff152,
+ 0xb9a00800,
+ 0xf80001f9,
+ 0x2b8b0010,
+ 0x2b8c000c,
+ 0x2b8d0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0x379cfff8,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f630,
+ 0x28210000,
+ 0x780be000,
+ 0x396b3014,
+ 0x29620000,
+ 0x202100ff,
+ 0x08210064,
+ 0x38420002,
+ 0x59620000,
+ 0xf8000602,
+ 0x29610000,
+ 0x3402fffd,
+ 0xa0220800,
+ 0x59610000,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0008,
+ 0xc3a00000,
+ 0x379cfff8,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0x780be000,
+ 0x396b3004,
+ 0x34020001,
+ 0x7801e000,
+ 0x59620000,
+ 0x38213000,
+ 0x28220000,
+ 0x78010001,
+ 0x3821fffe,
+ 0xa0411000,
+ 0x00420001,
+ 0x78010001,
+ 0x3c420002,
+ 0x3821d9d8,
+ 0xb4411000,
+ 0x28410000,
+ 0xd8200000,
+ 0x34010003,
+ 0x59610000,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0008,
+ 0xc3a00000,
+ 0x78030001,
+ 0x3863f380,
+ 0x28620000,
+ 0x78010100,
+ 0x38210000,
+ 0xb4411000,
+ 0x58620000,
+ 0xc3a00000,
+ 0x78038001,
+ 0x78040010,
+ 0x38630000,
+ 0x38840000,
+ 0x78028008,
+ 0x202100ff,
+ 0x58640050,
+ 0x384227e8,
+ 0x58410000,
+ 0x28610050,
+ 0xa0240800,
+ 0x4420fffe,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x202b00ff,
+ 0x656c0006,
+ 0x5d80000d,
+ 0x69610006,
+ 0x5c200004,
+ 0x65610004,
+ 0x5c200007,
+ 0xe000007e,
+ 0x65610008,
+ 0x5c200008,
+ 0x6561000a,
+ 0x5c200008,
+ 0xe0000079,
+ 0xb9602000,
+ 0xe0000006,
+ 0x34040005,
+ 0xe0000004,
+ 0x34040006,
+ 0xe0000002,
+ 0x34040007,
+ 0x780d0001,
+ 0xb9a00800,
+ 0x3821d924,
+ 0x40210000,
+ 0x442b006a,
+ 0x5d80002a,
+ 0x69610006,
+ 0x5c200004,
+ 0x65610004,
+ 0x5c200007,
+ 0xe0000064,
+ 0x65610008,
+ 0x5c200023,
+ 0x6561000a,
+ 0x5c200021,
+ 0xe000005f,
+ 0x7803e000,
+ 0x38632078,
+ 0x28610000,
+ 0x3402fdff,
+ 0xa0220800,
+ 0x58610000,
+ 0x28620000,
+ 0xb8800800,
+ 0x3404feff,
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+ 0x01830005,
+ 0xb8265800,
+ 0x204201c0,
+ 0x01840003,
+ 0xb9625800,
+ 0x20633800,
+ 0x01810001,
+ 0xa0892000,
+ 0xb9635800,
+ 0xa0280800,
+ 0x3d820001,
+ 0xb9645800,
+ 0xb9615800,
+ 0xa0471000,
+ 0x78010001,
+ 0xb9625800,
+ 0x3821f3b0,
+ 0x582b0000,
+ 0x29454038,
+ 0x01810016,
+ 0x01820014,
+ 0x01840012,
+ 0x2021000e,
+ 0xb8265800,
+ 0x204201c0,
+ 0x3ca30010,
+ 0xb9625800,
+ 0x20843800,
+ 0x3ca10012,
+ 0xa0691800,
+ 0xb9645800,
+ 0xa0280800,
+ 0x3ca20014,
+ 0xb9635800,
+ 0xb9615800,
+ 0xa0471000,
+ 0x00a30003,
+ 0x78010001,
+ 0xb9625800,
+ 0x3821f3b4,
+ 0x582b0000,
+ 0x00a20001,
+ 0x2063000e,
+ 0xb8665800,
+ 0x3ca40001,
+ 0x204201c0,
+ 0x3ca30003,
+ 0xb9625800,
+ 0x20843800,
+ 0x3ca10005,
+ 0xa0691800,
+ 0xb9645800,
+ 0xa0280800,
+ 0x3ca20007,
+ 0xb9635800,
+ 0xb9615800,
+ 0xa0471000,
+ 0x00a30010,
+ 0x78010001,
+ 0xb9625800,
+ 0x3821f3b8,
+ 0x582b0000,
+ 0x00a2000e,
+ 0x2063000e,
+ 0xb8665800,
+ 0x00a4000c,
+ 0x204201c0,
+ 0x00a3000a,
+ 0xb9625800,
+ 0x20843800,
+ 0x00a10008,
+ 0xa0691800,
+ 0xb9645800,
+ 0xa0280800,
+ 0x00a20006,
+ 0xb9635800,
+ 0xb9615800,
+ 0xa0471000,
+ 0x78010001,
+ 0xb9625800,
+ 0x3821f3bc,
+ 0x582b0000,
+ 0x294c403c,
+ 0x00a1001d,
+ 0x00a2001c,
+ 0x20210002,
+ 0xb8265800,
+ 0x3d830005,
+ 0x20420008,
+ 0x3d810006,
+ 0xb9625800,
+ 0x20630020,
+ 0xb9635800,
+ 0x20210780,
+ 0x3d840008,
+ 0xb9615800,
+ 0x3d850009,
+ 0x3d83000c,
+ 0x78020001,
+ 0x78010030,
+ 0x20842000,
+ 0x38428000,
+ 0x38210000,
+ 0xa0611800,
+ 0xb9645800,
+ 0xa0a22800,
+ 0xb9655800,
+ 0x78010001,
+ 0xb9635800,
+ 0x3821f3c0,
+ 0x582b0000,
+ 0x2b8b0008,
+ 0x2b8c0004,
+ 0x379c0008,
+ 0xc3a00000,
+ 0x379cffe4,
+ 0x5b8b001c,
+ 0x5b8c0018,
+ 0x5b8d0014,
+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
+ 0x5b910004,
+ 0x7804e010,
+ 0x38840000,
+ 0x28904008,
+ 0x288f4004,
+ 0x78020001,
+ 0x3e030003,
+ 0x01e1001d,
+ 0x3842df88,
+ 0xb8237000,
+ 0x304e008c,
+ 0x020e0005,
+ 0x284b0000,
+ 0x304e008d,
+ 0x020e000d,
+ 0x7803c000,
+ 0x304e008e,
+ 0x020e0015,
+ 0x386303ff,
+ 0x304e008f,
+ 0x28904090,
+ 0x288f408c,
+ 0xa1635800,
+ 0x3e050002,
+ 0x01e1001e,
+ 0x0206001e,
+ 0xb8257000,
+ 0x304e0019,
+ 0x020e0006,
+ 0x2845000c,
+ 0x304e001b,
+ 0x020e000e,
+ 0x7801fff0,
+ 0x304e0018,
+ 0x020e0016,
+ 0x38210000,
+ 0x304e001a,
+ 0x28904094,
+ 0xa0a12800,
+ 0x7807000f,
+ 0x3e030002,
+ 0x38e7ffff,
+ 0xb8c37000,
+ 0x304e0070,
+ 0x020e0006,
+ 0x780980ff,
+ 0x304e0071,
+ 0x288f4094,
+ 0x3929ffff,
+ 0x780aff80,
+ 0x01ee000e,
+ 0x01e3001e,
+ 0x0c4e004a,
+ 0x28904098,
+ 0x394affff,
+ 0x7808ff1f,
+ 0x3e010002,
+ 0x3908ffff,
+ 0xb8617000,
+ 0x0c4e0048,
+ 0x020e000e,
+ 0x0203001e,
+ 0x0c4e0072,
+ 0x2890409c,
+ 0x780cff00,
+ 0x398c1fff,
+ 0x3e010002,
+ 0x7806ff7f,
+ 0xb8617000,
+ 0x304e0009,
+ 0x020e0006,
+ 0x38c6ffff,
+ 0x304e000a,
+ 0x020e000e,
+ 0x780d7fff,
+ 0x304e000b,
+ 0x289040a0,
+ 0x288f409c,
+ 0x39adffff,
+ 0x3e03000a,
+ 0x01e10016,
+ 0x78110001,
+ 0xb8237000,
+ 0xa1c70800,
+ 0x020e000a,
+ 0x3c21000a,
+ 0x304e0016,
+ 0x020e0012,
+ 0xb9615800,
+ 0xba007800,
+ 0x304e0017,
+ 0x584b0000,
+ 0x289040a4,
+ 0x01e3001a,
+ 0x3a31f850,
+ 0x3e010006,
+ 0xb8617000,
+ 0x304e001e,
+ 0x020e0002,
+ 0x3401fc00,
+ 0x304e001f,
+ 0x020e000a,
+ 0xa1615800,
+ 0xa1c73800,
+ 0xb8a72800,
+ 0x5845000c,
+ 0x288f40a4,
+ 0x289040a8,
+ 0x2847001c,
+ 0x01e3001e,
+ 0x3e010002,
+ 0xa0e93800,
+ 0xb8617000,
+ 0x0c4e003a,
+ 0x288f40a8,
+ 0xa0a82800,
+ 0x3408ffff,
+ 0x01ee000f,
+ 0x34090000,
+ 0x21c1007f,
+ 0x3c210018,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f40a8,
+ 0xa0ea3800,
+ 0xb8405000,
+ 0x01ee0016,
+ 0x21c1007f,
+ 0x3c210010,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f40a8,
+ 0x289040ac,
+ 0xa0e63800,
+ 0x01e3001d,
+ 0x3e010003,
+ 0xb8617000,
+ 0x0c4e0024,
+ 0x288f40ac,
+ 0x01ee000d,
+ 0x0c4e0026,
+ 0x288f40ac,
+ 0x289040b0,
+ 0x01e3001d,
+ 0x3e010003,
+ 0xb8617000,
+ 0x304e0029,
+ 0x288f40b0,
+ 0x01ee0005,
+ 0x304e002b,
+ 0x288f40b0,
+ 0x01ee000d,
+ 0x304e0008,
+ 0x288f40b0,
+ 0x01ee0015,
+ 0x21c10007,
+ 0x3c210015,
+ 0xb8a12800,
+ 0x5845000c,
+ 0x288f40b0,
+ 0x3401c0ff,
+ 0x01ee0018,
+ 0x304e000c,
+ 0x288f40b4,
+ 0x0c4f002e,
+ 0x288f40b4,
+ 0x01ee0010,
+ 0x0c4e0036,
+ 0x0c4e0034,
+ 0x288f40b8,
+ 0x0c4f0032,
+ 0x288f40b8,
+ 0x01ee0010,
+ 0x0c4e0038,
+ 0x288f40bc,
+ 0x28430028,
+ 0x28450004,
+ 0x0c4f0030,
+ 0x288f40bc,
+ 0xa0611800,
+ 0xa0ac2800,
+ 0x01ee0010,
+ 0x0c4e002c,
+ 0x288f40c0,
+ 0x21e1003f,
+ 0x3c210008,
+ 0xb8611800,
+ 0x58430028,
+ 0x288f40c0,
+ 0x01ee0006,
+ 0x304e0028,
+ 0x288f413c,
+ 0x21e107ff,
+ 0x3c21000d,
+ 0xb8a12800,
+ 0x58450004,
+ 0x288f413c,
+ 0x01ee000b,
+ 0x304e0020,
+ 0x288f413c,
+ 0x01ee0013,
+ 0x304e0021,
+ 0x288f413c,
+ 0x28904140,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0022,
+ 0x288f4140,
+ 0x01ee0003,
+ 0x304e0010,
+ 0x288f4140,
+ 0x01ee000b,
+ 0x304e0012,
+ 0x288f4140,
+ 0x01ee0013,
+ 0x304e0011,
+ 0x288f4140,
+ 0x28904144,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0013,
+ 0x288f4144,
+ 0x01ee0003,
+ 0x304e0014,
+ 0x288f4144,
+ 0x01ee000b,
+ 0x304e0015,
+ 0x288f4148,
+ 0x01ee000b,
+ 0x304e0050,
+ 0x288f4148,
+ 0x01ee0013,
+ 0x304e0051,
+ 0x288f4148,
+ 0x2890414c,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0052,
+ 0x288f414c,
+ 0x01ee0003,
+ 0x21ce0fff,
+ 0x0c4e0054,
+ 0x288f414c,
+ 0x01ee000f,
+ 0x21ce0fff,
+ 0x0c4e0056,
+ 0x288f414c,
+ 0x28904150,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x21ce0fff,
+ 0x0c4e0058,
+ 0x288f4150,
+ 0x01ee0007,
+ 0x21ce0fff,
+ 0x0c4e005a,
+ 0x288f4150,
+ 0x01ee0013,
+ 0x21ce0fff,
+ 0x0c4e005c,
+ 0x288f4150,
+ 0x28904154,
+ 0x01e3001f,
+ 0x3e010001,
+ 0xb8617000,
+ 0x21ce0fff,
+ 0x0c4e005e,
+ 0x288f4154,
+ 0x3401c000,
+ 0x01ee000b,
+ 0x304e004c,
+ 0x288f4154,
+ 0x01ee0013,
+ 0x304e004d,
+ 0x288f4154,
+ 0x28904158,
+ 0x2843004c,
+ 0x01e6001b,
+ 0x3e050005,
+ 0xa0611800,
+ 0xb8c57000,
+ 0x21c13fff,
+ 0xb8611800,
+ 0x5843004c,
+ 0x288f4158,
+ 0x01ee0009,
+ 0x21c10001,
+ 0x3c210017,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f415c,
+ 0xa0ed3800,
+ 0x01ee0006,
+ 0x21ce003f,
+ 0x304e0060,
+ 0x288f415c,
+ 0x01ee000c,
+ 0x21ce003f,
+ 0x304e0061,
+ 0x288f415c,
+ 0x01ee0012,
+ 0x21ce003f,
+ 0x304e0062,
+ 0x288f415c,
+ 0x01ee0018,
+ 0x21ce003f,
+ 0x304e0063,
+ 0x288f415c,
+ 0x28904160,
+ 0x01e3001e,
+ 0x3e010002,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0064,
+ 0x288f4160,
+ 0x01ee0004,
+ 0x21ce003f,
+ 0x304e0065,
+ 0x288f4160,
+ 0x01ee000a,
+ 0x21ce003f,
+ 0x304e0066,
+ 0x288f4160,
+ 0x01ee0010,
+ 0x21ce003f,
+ 0x304e0067,
+ 0x288f4160,
+ 0x01ee0016,
+ 0x21ce003f,
+ 0x304e0068,
+ 0x288f4160,
+ 0x28904164,
+ 0x01e3001c,
+ 0x3e010004,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0069,
+ 0x288f4164,
+ 0x01ee0002,
+ 0x21ce003f,
+ 0x304e006a,
+ 0x288f4164,
+ 0x01ee0008,
+ 0x21ce003f,
+ 0x304e006b,
+ 0x288f4164,
+ 0x01ee000e,
+ 0x21ce003f,
+ 0x304e006c,
+ 0x288f4164,
+ 0x01ee0014,
+ 0x21ce003f,
+ 0x304e006d,
+ 0x288f4164,
+ 0x01ee001a,
+ 0x304e006e,
+ 0x288f4168,
+ 0x21ee003f,
+ 0x304e006f,
+ 0x288f4170,
+ 0x01ee000e,
+ 0x304e0023,
+ 0x288f4174,
+ 0x01ee0008,
+ 0x304f0084,
+ 0x304e0085,
+ 0x01ee0010,
+ 0x304e0086,
+ 0x01ee0018,
+ 0x304e0087,
+ 0x288f4178,
+ 0x01ee0008,
+ 0x304f0088,
+ 0x304e0089,
+ 0x01ee0010,
+ 0x304e008a,
+ 0x01ee0018,
+ 0x304e008b,
+ 0x288f417c,
+ 0x01ee0008,
+ 0x304f0091,
+ 0x304e0092,
+ 0x01ee0010,
+ 0x304e0093,
+ 0x01ee0018,
+ 0x304e0094,
+ 0x288f4180,
+ 0x01ee0008,
+ 0x304f0096,
+ 0x304e0097,
+ 0x01ee0010,
+ 0x304e0098,
+ 0x01ee0018,
+ 0x304e0099,
+ 0x288f6000,
+ 0x01ee0018,
+ 0x304e003c,
+ 0x288f6004,
+ 0x01ee0008,
+ 0x304f003d,
+ 0x304e003e,
+ 0x01ee0010,
+ 0x304e003f,
+ 0x288f6008,
+ 0x01ee0008,
+ 0x304f0040,
+ 0x304e0041,
+ 0x01ee0010,
+ 0x304e0042,
+ 0x01ee0018,
+ 0x304e0043,
+ 0x288f600c,
+ 0x01ee0008,
+ 0x304f0044,
+ 0x304e0045,
+ 0x01ee0010,
+ 0x304e0046,
+ 0x01ee0018,
+ 0x304e0047,
+ 0x288f6014,
+ 0x01ee0008,
+ 0x3dc1001f,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f6020,
+ 0x01ee0003,
+ 0x21c103ff,
+ 0xb9615800,
+ 0x584b0000,
+ 0x288f7048,
+ 0x01ee000b,
+ 0x01e3001d,
+ 0x21ce003f,
+ 0x304e0074,
+ 0x01ee0011,
+ 0x21ce003f,
+ 0x304e0075,
+ 0x01ee0017,
+ 0x21ce003f,
+ 0x304e0076,
+ 0x2890704c,
+ 0x3e010003,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0077,
+ 0x020e0003,
+ 0x0203001b,
+ 0x21ce003f,
+ 0x304e0078,
+ 0x020e0009,
+ 0x21ce003f,
+ 0x304e0079,
+ 0x020e000f,
+ 0x21ce003f,
+ 0x304e007a,
+ 0x020e0015,
+ 0x21ce003f,
+ 0x304e007b,
+ 0x28907050,
+ 0x3e010005,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e007c,
+ 0x020e0001,
+ 0x0203001f,
+ 0x21ce003f,
+ 0x304e007d,
+ 0x020e0007,
+ 0x21ce003f,
+ 0x304e007e,
+ 0x020e000d,
+ 0x21ce003f,
+ 0x304e007f,
+ 0x020e0013,
+ 0x21ce003f,
+ 0x304e0080,
+ 0x020e0019,
+ 0x21ce003f,
+ 0x304e0081,
+ 0x28907054,
+ 0x3e010001,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0082,
+ 0x020e0005,
+ 0x21ce003f,
+ 0x304e0083,
+ 0x288f705c,
+ 0x01ee0003,
+ 0x304e0004,
+ 0x288f70e0,
+ 0x01ee0015,
+ 0x30480095,
+ 0x21c1000f,
+ 0x30410053,
+ 0x30480090,
+ 0x3d210002,
+ 0xb42a1000,
+ 0x28420000,
+ 0xb4310800,
+ 0x35290001,
+ 0x58220000,
+ 0x75210026,
+ 0x4420fff9,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b910004,
+ 0x379c001c,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0x34020000,
+ 0x780b0001,
+ 0x78058000,
+ 0x396bfe80,
+ 0x38a50338,
+ 0x5b82000c,
+ 0xbbe01800,
+ 0x3401fffc,
+ 0xa0611800,
+ 0xb8402000,
+ 0xb8203800,
+ 0x3c820002,
+ 0x34860001,
+ 0xb4451000,
+ 0x28410000,
+ 0xa0270800,
+ 0x58410000,
+ 0x44230014,
+ 0x20c400ff,
+ 0x74810003,
+ 0x4420fff7,
+ 0x4161001b,
+ 0x202200ff,
+ 0x7c410001,
+ 0x5c200012,
+ 0xd1020000,
+ 0x34010001,
+ 0x3161001a,
+ 0x4161001a,
+ 0x7c210001,
+ 0x4420fffe,
+ 0x4161001b,
+ 0x202100ff,
+ 0x5c200037,
+ 0xd1010000,
+ 0xfbffcc9d,
+ 0xe0000034,
+ 0x37810010,
+ 0xb4241000,
+ 0x34010001,
+ 0x3041fffc,
+ 0xe3ffffec,
+ 0x4381000c,
+ 0x44200009,
+ 0x28a10000,
+ 0xd2010000,
+ 0x34010001,
+ 0x31610003,
+ 0x41610003,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe0000025,
+ 0x4381000d,
+ 0x44200009,
+ 0x28a10004,
+ 0xd2210000,
+ 0x34010001,
+ 0x31610002,
+ 0x41610002,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe000001b,
+ 0x4381000e,
+ 0x44200009,
+ 0x28a10008,
+ 0xd2410000,
+ 0x34010001,
+ 0x31610001,
+ 0x41610001,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe0000011,
+ 0x4381000f,
+ 0x44200009,
+ 0x28a1000c,
+ 0xd2610000,
+ 0x34010001,
+ 0x31610000,
+ 0x41610000,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe0000007,
+ 0xfbffcc6e,
+ 0x34010002,
+ 0x31610003,
+ 0x41610003,
+ 0x7c210002,
+ 0x4420fffe,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884fe80,
+ 0xbbe01800,
+ 0x4081000f,
+ 0x3402fffc,
+ 0x3c630002,
+ 0xa0220800,
+ 0x38210001,
+ 0x3081000f,
+ 0x2881000c,
+ 0x20210003,
+ 0xb8230800,
+ 0x5881000c,
+ 0x4081000f,
+ 0x20210003,
+ 0x7c210001,
+ 0x4420fffd,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884fe80,
+ 0xbbe01800,
+ 0x40810013,
+ 0x3402fffc,
+ 0x3c630002,
+ 0xa0220800,
+ 0x38210001,
+ 0x30810013,
+ 0x28810010,
+ 0x20210003,
+ 0xb8230800,
+ 0x58810010,
+ 0x40810013,
+ 0x20210003,
+ 0x7c210001,
+ 0x4420fffd,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884fe80,
+ 0xbbe01800,
+ 0x4081000b,
+ 0x3402fffc,
+ 0x3c630002,
+ 0xa0220800,
+ 0x38210001,
+ 0x3081000b,
+ 0x28810008,
+ 0x20210003,
+ 0xb8230800,
+ 0x58810008,
+ 0x4081000b,
+ 0x20210003,
+ 0x7c210001,
+ 0x4420fffd,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x7801e000,
+ 0x38210124,
+ 0x34020001,
+ 0x58220000,
+ 0x78030001,
+ 0x3863d848,
+ 0x34010000,
+ 0x30610003,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x780d0001,
+ 0xb9a01800,
+ 0x3863e028,
+ 0x40610000,
+ 0x78028001,
+ 0x38420000,
+ 0x34210001,
+ 0x30610000,
+ 0x28410058,
+ 0x5c200068,
+ 0x780b8001,
+ 0xb9601000,
+ 0x38420000,
+ 0x2844005c,
+ 0x34010001,
+ 0xb960e800,
+ 0xbc242800,
+ 0xb9604800,
+ 0x6881001f,
+ 0xb9606000,
+ 0x5c200003,
+ 0x58450050,
+ 0xe0000002,
+ 0x58450054,
+ 0x7c860028,
+ 0x7c81001d,
+ 0x3c8a0002,
+ 0xa0c10800,
+ 0x6488001e,
+ 0x64210000,
+ 0x78070001,
+ 0x5c200027,
+ 0xb9201800,
+ 0x78050001,
+ 0x78020001,
+ 0x38630000,
+ 0x38a5db74,
+ 0x3842db80,
+ 0x34090004,
+ 0x5d00001f,
+ 0x28610000,
+ 0x28420000,
+ 0x58a10000,
+ 0x28610004,
+ 0x58a10004,
+ 0x58620000,
+ 0x28a10004,
+ 0x20210100,
+ 0x58610004,
+ 0x28610004,
+ 0xd0490000,
+ 0x34010001,
+ 0xd0010000,
+ 0x78010001,
+ 0x3c820002,
+ 0x3821da6c,
+ 0xb4411000,
+ 0x28410000,
+ 0xd8200000,
+ 0x34010000,
+ 0xd0010000,
+ 0x78020001,
+ 0x3842db74,
+ 0x28430000,
+ 0xb9800800,
+ 0x38210000,
+ 0x58230000,
+ 0x28420004,
+ 0x58220004,
+ 0xe0000028,
+ 0xbba01800,
+ 0x78040001,
+ 0x78020001,
+ 0x38630000,
+ 0x3884db6c,
+ 0x3842db80,
+ 0x34050004,
+ 0x5cc0001b,
+ 0x28610000,
+ 0x28420000,
+ 0x58810000,
+ 0x28610004,
+ 0x58810004,
+ 0x58620000,
+ 0x58660004,
+ 0x28610004,
+ 0xd0450000,
+ 0x34010001,
+ 0xd0010000,
+ 0x38e7da6c,
+ 0xb5470800,
+ 0x28210000,
+ 0xd8200000,
+ 0x34010000,
+ 0xd0010000,
+ 0x78010001,
+ 0x3821db6c,
+ 0x28220000,
+ 0xb9601800,
+ 0x38630000,
+ 0x58620000,
+ 0x28210004,
+ 0x58610004,
+ 0xe0000006,
+ 0xd0450000,
+ 0x38e7da6c,
+ 0xb5470800,
+ 0x28210000,
+ 0xd8200000,
+ 0x78018001,
+ 0x38210000,
+ 0x28210058,
+ 0xe3ffff99,
+ 0xb9a01800,
+ 0x3863e028,
+ 0x40610000,
+ 0x34040001,
+ 0x3422ffff,
+ 0x202100ff,
+ 0x50810008,
+ 0x30620000,
+ 0x2b8b0010,
+ 0x2b8c000c,
+ 0x2b8d0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0x30620000,
+ 0x204100ff,
+ 0x5c20ff7f,
+ 0x78018000,
+ 0x38210000,
+ 0x58240008,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0xe3ffff76,
+ 0x78060001,
+ 0x38c6f1a0,
+ 0x78050001,
+ 0x38a5d7f4,
+ 0x30c1000b,
+ 0x28a70028,
+ 0xb8202000,
+ 0x34080000,
+ 0x34030003,
+ 0x48e30009,
+ 0x28a10038,
+ 0x34220060,
+ 0x40410003,
+ 0x3442ffe0,
+ 0x5c200010,
+ 0x3463ffff,
+ 0x48e30002,
+ 0xe3fffffb,
+ 0x28a10010,
+ 0x4501000f,
+ 0x7c810010,
+ 0x5c20000b,
+ 0x40c10002,
+ 0x34020000,
+ 0x30c10008,
+ 0x40c10000,
+ 0x30c10009,
+ 0x78010001,
+ 0x3821db7c,
+ 0xe000000c,
+ 0xb8604000,
+ 0xe3fffff3,
+ 0x7c810020,
+ 0x5c20001a,
+ 0x40c10003,
+ 0x34020001,
+ 0x30c10008,
+ 0x40c10001,
+ 0x30c10009,
+ 0x78010001,
+ 0x3821db7c,
+ 0x7804e000,
+ 0x30220000,
+ 0x38842018,
+ 0x28820000,
+ 0x40c10008,
+ 0x3405ff80,
+ 0xa0451000,
+ 0x2021007f,
+ 0xb8411000,
+ 0x7803e000,
+ 0x58820000,
+ 0x38632010,
+ 0x40c20009,
+ 0x28610000,
+ 0x2042007f,
+ 0xa0250800,
+ 0xb8220800,
+ 0x58610000,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f150,
+ 0x40210002,
+ 0x78028000,
+ 0x78038008,
+ 0x78040001,
+ 0x38420010,
+ 0x38630000,
+ 0x3884f1a0,
+ 0x4420000a,
+ 0x28420000,
+ 0x34010000,
+ 0x58610220,
+ 0x4083000a,
+ 0x20420030,
+ 0xb8400800,
+ 0x3082000b,
+ 0x44430002,
+ 0xfbffffb0,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfff4,
+ 0x5b8b000c,
+ 0x5b8c0008,
+ 0x5b9d0004,
+ 0xfbffd231,
+ 0xb8206000,
+ 0x780b0001,
+ 0xfbffd232,
+ 0x396bf1a0,
+ 0x41620007,
+ 0x78030001,
+ 0x3863db7c,
+ 0x3022000f,
+ 0x78010001,
+ 0x3182000f,
+ 0x3821f150,
+ 0x40210002,
+ 0x34020010,
+ 0x44200007,
+ 0x40610000,
+ 0x7c210001,
+ 0x5c200002,
+ 0x34020020,
+ 0xb8400800,
+ 0xfbffff94,
+ 0x2b8b000c,
+ 0x2b8c0008,
+ 0x2b9d0004,
+ 0x379c000c,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x01300000,
+ 0x01310000,
+ 0x01310000,
+ 0x01320000,
+ 0x01330000,
+ 0x01100000,
+ 0x01110000,
+ 0x02110000,
+ 0x01120000,
+ 0x01130000,
+ 0x01200000,
+ 0x01210000,
+ 0x02210000,
+ 0x01220000,
+ 0x01230000,
+ 0x00000100,
+ 0x00000000,
+ 0x000a0003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000007,
+ 0x0001f000,
+ 0x0001f000,
+ 0x0001f000,
+ 0x000113dc,
+ 0x00011318,
+ 0x01010101,
+ 0x01010101,
+ 0x7fff0000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x000a0003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000007,
+ 0x0001f200,
+ 0x0001f200,
+ 0x0001f200,
+ 0x00011bf8,
+ 0x00011b58,
+ 0x0001f8f0,
+ 0x00015000,
+ 0x0001420c,
+ 0x00010e64,
+ 0x00011928,
+ 0x0001b748,
+ 0x0001b8dc,
+ 0x00000000,
+ 0x00017510,
+ 0x000156bc,
+ 0x00015d18,
+ 0x00016528,
+ 0x000169d0,
+ 0x00016e2c,
+ 0x000174d0,
+ 0x00012f3c,
+ 0x0001d6d4,
+ 0x0000ea60,
+ 0x00004e20,
+ 0x64000000,
+ 0x000186a0,
+ 0x0001f480,
+ 0x80402010,
+ 0x08040200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010000,
+ 0x01000100,
+ 0x00000000,
+ 0x00000000,
+ 0x01010101,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0001f120,
+ 0x00000000,
+ 0x04000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00003178,
+ 0x00000000,
+ 0x00003171,
+ 0x00000000,
+ 0x00003172,
+ 0x00000000,
+ 0x00007103,
+ 0x00000000,
+ 0x00007116,
+ 0x00000000,
+ 0x0000317d,
+ 0x00000000,
+ 0x00007103,
+ 0x00000000,
+ 0x0000712e,
+ 0x00000000,
+ 0x0000710f,
+ 0x00000000,
+ 0x00007110,
+ 0x00000000,
+ 0x00007111,
+ 0x00000000,
+ 0x00007112,
+ 0x00000000,
+ 0x00007113,
+ 0x00000000,
+ 0x0000715c,
+ 0x00000000,
+ 0x0000715d,
+ 0x00000000,
+ 0x00007162,
+ 0x00000000,
+ 0x00007117,
+ 0x00000000,
+ 0x00007157,
+ 0x00000000,
+ 0x00007106,
+ 0x00000000,
+ 0x0001ab20,
+ 0x00010788,
+ 0x0001a8d8,
+ 0x00019fec,
+ 0x0001a4a0,
+ 0x00019a00,
+ 0x0001a450,
+ 0x000199b4,
+ 0x0001a420,
+ 0x00011d94,
+ 0x00010418,
+ 0x00010430,
+ 0x00013138,
+ 0x00013d5c,
+ 0x00012398,
+ 0x00015970,
+ 0x0001244c,
+ 0x0001bb5c,
+ 0x0001b864,
+ 0x00012c48,
+ 0x00012300,
+ 0x00012354,
+ 0x00016834,
+ 0x00012530,
+ 0x00016e2c,
+ 0x0001a984,
+ 0x0001396c,
+ 0x0001aa60,
+ 0x00011e80,
+ 0x0001d380,
+ 0x00011bf8,
+ 0x00011b58,
+ 0x00014c0c,
+ 0x00014e28,
+ 0x0001a704,
+ 0x00019d34,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001c1a8,
+ 0x0001c1e0,
+ 0x00012f3c,
+ 0x0001724c,
+ 0x0001aab8,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001af7c,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001adb4,
+ 0x00012f34,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001d7ac,
+ 0x0001d7b0,
+ 0x00010788,
+ 0x000121b8,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00013340,
+ 0x0001420c,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
new file mode 100644
index 0000000000..75f8c9cb56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
@@ -0,0 +1,1121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "cpuFamRegisters.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = {
+  GNB_ENTRY_RMW (
+    D0F0x98_x07_TYPE,
+    D0F0x98_x07_ADDRESS,
+    D0F0x98_x07_SMUCsrIsocEn_MASK,
+    (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x1E_TYPE,
+    D0F0x98_x1E_ADDRESS,
+    D0F0x98_x1E_HiPriEn_MASK,
+    (1 << D0F0x98_x1E_HiPriEn_OFFSET)
+    ),
+
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = {
+ // Config GFX to legacy mode initially
+  GNB_ENTRY_RMW (
+    D0F0x64_x1D_TYPE,
+    D0F0x64_x1D_ADDRESS,
+    D0F0x64_x1D_IntGfxAsPcieEn_MASK,
+    0
+    ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F87C_TYPE,
+    D0F0xBC_x1F87C_ADDRESS,
+    D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK | D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F880_TYPE,
+    D0F0xBC_x1F880_ADDRESS,
+    D0F0xBC_x1F880_LL_VCE_LoadStep_MASK | D0F0xBC_x1F880_LL_UVD_LoadStep_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F884_TYPE,
+    D0F0xBC_x1F884_ADDRESS,
+    D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK | D0F0xBC_x1F884_LL_DCE_LoadStep_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F888_TYPE,
+    D0F0xBC_x1F888_ADDRESS,
+    D0F0xBC_x1F888_LL_GPU_LoadStep_MASK,
+    0
+  ),
+ // Configure load line VID
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F3D8_TYPE,
+    D0F0xBC_x1F3D8_ADDRESS,
+    (0x00 << D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET) |
+    (0xFE << D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET) |
+    (0xFC << D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET) |
+    (0xF6 << D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F3DC_TYPE,
+    D0F0xBC_x1F3DC_ADDRESS,
+    (0x08 << D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET) |
+    (0x06 << D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET) |
+    (0x04 << D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET) |
+    (0x02 << D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F404_TYPE,
+    D0F0xBC_x1F404_ADDRESS,
+    (0x19 << D0F0xBC_x1F404_LoadLineOffset3_OFFSET) |
+    (0x00 << D0F0xBC_x1F404_LoadLineOffset2_OFFSET) |
+    (0xE7 << D0F0xBC_x1F404_LoadLineOffset1_OFFSET) |
+    (0x00 << D0F0xBC_x1F404_LoadLineOffset0_OFFSET)
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH,
+    D0F0xBC_xE01040A8_TYPE,
+    D0F0xBC_xE01040A8_ADDRESS,
+    D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH,
+    D0F0xBC_xE01040A8_TYPE,
+    D0F0xBC_xE01040A8_ADDRESS,
+    D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH
+  ),
+ GNB_ENTRY_COPY (
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D18F5x188_TYPE,
+    D18F5x188_ADDRESS,
+    D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH
+  ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F3FC_TYPE,
+    D0F0xBC_x1F3FC_ADDRESS,
+    D0F0xBC_x1F3FC_SviVidStepBase_MASK | D0F0xBC_x1F3FC_SviVidStep_MASK,
+    (0x1838 << D0F0xBC_x1F3FC_SviVidStepBase_OFFSET) | (0x19 << D0F0xBC_x1F3FC_SviVidStep_OFFSET)
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK | D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK,
+    (2 << D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET) | (2 << D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET)
+  ),
+//  GNB_ENTRY_COPY (
+//    D18F5x188_TYPE,
+//    D18F5x188_ADDRESS,
+//    D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH,
+//    D0F0xBC_xE0104184_TYPE,
+//    D0F0xBC_xE0104184_ADDRESS,
+//    D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH
+//  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D18F5x188_TYPE,
+    D18F5x188_ADDRESS,
+    D18F5x188_NbLoadLineTrim_MASK,// | D18F5x188_NbOffsetTrim_MASK,
+    (3 << D18F5x188_NbLoadLineTrim_OFFSET)// | (2 << D18F5x188_NbOffsetTrim_OFFSET)
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreLoadLineTrim_MASK | D18F5x12C_CoreOffsetTrim_MASK,
+    (3 << D18F5x12C_CoreLoadLineTrim_OFFSET) | (2 << D18F5x12C_CoreOffsetTrim_OFFSET)
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVdd_MASK | D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK,
+    (3 << D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET) | (3 << D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET)
+  ),
+  // Enable SVI2
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_SviMode_MASK,
+    (1 << D0F0xBC_x1F428_SviMode_OFFSET)
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = {
+  GNB_ENTRY_WR (
+    D0F0x04_TYPE,
+    D0F0x04_ADDRESS,
+    (0x1 << D0F0x04_MemAccessEn_OFFSET) | (0x1 << D0F0x04_BusMasterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x4C_TYPE,
+    D0F0x4C_ADDRESS,
+    D0F0x4C_CfgRdTime_MASK,
+    0x2 << D0F0x4C_CfgRdTime_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x84_TYPE,
+    D0F0x84_ADDRESS,
+    D0F0x84_Ev6Mode_MASK,
+    0x1 << D0F0x84_Ev6Mode_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x64_x46_TYPE,
+    D0F0x64_x46_ADDRESS,
+    0x6 ,
+    1 << D0F0x64_x46_Msi64bitEn_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x0C_TYPE,
+    D0F0x98_x0C_ADDRESS,
+    D0F0x98_x0C_StrictSelWinnerEn_MASK,
+    1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET
+    ),
+  // Configure PM timer
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F468_TYPE,
+    D0F0xBC_x1F468_ADDRESS,
+    D0F0xBC_x1F468_TimerPeriod_MASK,
+    D0F0xBC_x1F468_TimerPeriod_Value << D0F0xBC_x1F468_TimerPeriod_OFFSET
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_EN_PM_CNTL,
+    0
+    ),
+  //Enable voltage controller
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_VoltageCntl_MASK,
+    1 << D0F0xBC_x1F460_VoltageCntl_OFFSET
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F384_TYPE,
+    D0F0xBC_x1F384_ADDRESS,
+    D0F0xBC_x1F384_FirmwareVid_OFFSET,
+    D0F0xBC_x1F384_FirmwareVid_WIDTH,
+    D0F0xBC_xE0001008_TYPE ,
+    D0F0xBC_xE0001008_ADDRESS,
+    D0F0xBC_xE0001008_SClkVid0_OFFSET,
+    D0F0xBC_xE0001008_SClkVid0_WIDTH
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_VOLTAGE_CNTL,
+    0
+    ),
+  GNB_ENTRY_POLL (
+    GMMx7B0_TYPE,
+    GMMx7B0_ADDRESS,
+    GMMx7B0_SMU_VOLTAGE_EN_MASK,
+    0x1 << GMMx7B0_SMU_VOLTAGE_EN_OFFSET
+    ),
+  // Enable thermal controller
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_ThermalCntl_MASK,
+    30 << D0F0xBC_x1F460_ThermalCntl_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F388_TYPE,
+    D0F0xBC_x1F388_ADDRESS,
+    D0F0xBC_x1F388_CsrAddr_MASK | D0F0xBC_x1F388_TcenId_MASK,
+    (0x9 << D0F0xBC_x1F388_CsrAddr_OFFSET) | (0xE << D0F0xBC_x1F388_TcenId_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_THERMAL_CNTL,
+    0
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_PstateMax_OFFSET,
+    D0F0xBC_x1F400_PstateMax_WIDTH,
+    TYPE_D18F3 ,
+    0xdc ,
+    8 ,
+    3
+    ),
+  // Configure VPC
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableVpcAccumulators_MASK,
+    (1 << D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_PstateAllCpusIdle_MASK | D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK,
+    (1 << D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_VpcPeriod_MASK,
+    (0x1B58 << D0F0xBC_x1F46C_VpcPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_VPC_ACCUMULATOR,
+    0
+    ),
+ // Enable TDC
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableTdcLimit_MASK,
+    (1 << D0F0xBC_x1F428_EnableTdcLimit_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F638_TYPE,
+    D0F0xBC_x1F638_ADDRESS,
+    D0F0xBC_x1F638_TdcPeriod_MASK,
+    (0x1 << D0F0xBC_x1F638_TdcPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_TDC_LIMIT,
+    0
+    ),
+
+  // Enable LPMx
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableLpmx_MASK,
+    (1 << D0F0xBC_x1F428_EnableLpmx_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_LpmxPeriod_MASK,
+    (1 << D0F0xBC_x1F46C_LpmxPeriod_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_LPMx,
+    0
+    ),
+  // Enable BAPM
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_BapmCoeffOverride_MASK,
+    (0x1 << D0F0xBC_x1F428_BapmCoeffOverride_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableBapm_MASK,
+    (1 << D0F0xBC_x1F428_EnableBapm_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_BapmPeriod_MASK,
+    (D0F0xBC_x1F46C_BapmPeriod_Value << D0F0xBC_x1F46C_BapmPeriod_OFFSET)
+    ),
+ // Config BAPM
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_BAPM,
+    0
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEnvInitTableTN [] = {
+//---------------------------------------------------------------------------
+// ORB Init
+//D0F0x98_x07[IocBwOptEn]
+//D0F0x98_x07[DropZeroMaskWrEn]
+//D0F0x98_x28[ForceCoherentIntr] = 1
+//D0F0x98_x07[UnadjustThrottlingStpclk ] = 1
+//D0F0x98_x07[MSIHTIntConversionEn] = 0
+//D0F0x98_x07[IommuBwOptEn] = 1
+//D0F0x98_x07[IommuIsocPassPWMode] = 1
+//D0F0x98_x08[NpWrrLenC] = 1
+//D0F0x98_x28[ForceCoherentIntr] = 1
+//D0F0x98_x2C[NBOutbWakeMask] = 1
+//D0F0x98_x2C[OrbRxIdlesMask] = 1
+
+  GNB_ENTRY_RMW (
+    D0F0x98_x07_TYPE,
+    D0F0x98_x07_ADDRESS,
+    D0F0x98_x07_UnadjustThrottlingStpclk_MASK | D0F0x98_x07_MSIHTIntConversionEn_MASK |
+    D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK |
+    D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK,
+    (0x1 << D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET) | (0x0 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) |
+    (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) |
+    (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x08_TYPE,
+    D0F0x98_x08_ADDRESS,
+    D0F0x98_x08_NpWrrLenC_MASK,
+    0x1 << D0F0x98_x08_NpWrrLenC_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x28_TYPE,
+    D0F0x98_x28_ADDRESS,
+    D0F0x98_x28_ForceCoherentIntr_MASK,
+    0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x2C_TYPE,
+    D0F0x98_x2C_ADDRESS,
+    D0F0x98_x2C_NBOutbWakeMask_MASK | D0F0x98_x2C_OrbRxIdlesMask_MASK,
+    (0x1 << D0F0x98_x2C_NBOutbWakeMask_OFFSET) | (0x1 << D0F0x98_x2C_OrbRxIdlesMask_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+//IOMMU L2 Initialization
+  GNB_ENTRY_RMW (
+    D0F2xF4_x10_TYPE,
+    D0F2xF4_x10_ADDRESS,
+    D0F2xF4_x10_DTCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x10_DTCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x11_TYPE,
+    D0F2xF4_x11_ADDRESS,
+    D0F2xF4_x11_DtcAddressMask_MASK | D0F2xF4_x11_DtcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x11_DtcAddressMask_OFFSET) | (0x1 << D0F2xF4_x11_DtcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x14_TYPE,
+    D0F2xF4_x14_ADDRESS,
+    D0F2xF4_x14_ITCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x14_ITCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x15_TYPE,
+    D0F2xF4_x15_ADDRESS,
+    D0F2xF4_x15_ITCAddressMask_MASK | D0F2xF4_x15_ItcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x15_ITCAddressMask_OFFSET) | (1 << D0F2xF4_x15_ItcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x18_TYPE,
+    D0F2xF4_x18_ADDRESS,
+    D0F2xF4_x18_PTCAInvalidationSel_MASK,
+    0x2 << D0F2xF4_x18_PTCAInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x19_TYPE,
+    D0F2xF4_x19_ADDRESS,
+    D0F2xF4_x19_PTCAAddressMask_MASK | D0F2xF4_x19_PtcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x19_PTCAAddressMask_OFFSET) | (1 << D0F2xF4_x19_PtcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x30_TYPE,
+    D0F2xF4_x30_ADDRESS,
+    D0F2xF4_x30_ERRRuleLock1_MASK,
+    0x1 << D0F2xF4_x30_ERRRuleLock1_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x34_TYPE,
+    D0F2xF4_x34_ADDRESS,
+    D0F2xF4_x34_L2aregHostPgsize_MASK | D0F2xF4_x34_L2aregGstPgsize_MASK,
+    (0x2 << D0F2xF4_x34_L2aregHostPgsize_OFFSET) | (0x2 <<  D0F2xF4_x34_L2aregGstPgsize_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x47_TYPE,
+    D0F2xF4_x47_ADDRESS,
+    D0F2xF4_x47_TwAtomicFilterEn_MASK | D0F2xF4_x47_TwNwEn_MASK,
+    (0x1 << D0F2xF4_x47_TwAtomicFilterEn_OFFSET) | (1 << D0F2xF4_x47_TwNwEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x4C_TYPE,
+    D0F2xF4_x4C_ADDRESS,
+    D0F2xF4_x4C_GstPartialPtcCntrl_MASK,
+    0x3 << D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x50_TYPE,
+    D0F2xF4_x50_ADDRESS,
+    D0F2xF4_x50_PDCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x50_PDCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x51_TYPE,
+    D0F2xF4_x51_ADDRESS,
+    D0F2xF4_x51_PDCAddressMask_MASK | D0F2xF4_x51_PdcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x51_PDCAddressMask_OFFSET) | (1 << D0F2xF4_x51_PdcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x56_TYPE,
+    D0F2xF4_x56_ADDRESS,
+    D0F2xF4_x56_CPFlushOnInv_MASK | D0F2xF4_x56_CPFlushOnWait_MASK,
+    (0x0 << D0F2xF4_x56_CPFlushOnInv_OFFSET) | (1 << D0F2xF4_x56_CPFlushOnWait_OFFSET)
+    ),
+
+  GNB_ENTRY_RMW (
+    D0F2xF4_x80_TYPE,
+    D0F2xF4_x80_ADDRESS,
+    D0F2xF4_x80_ERRRuleLock0_MASK,
+    0x1 << D0F2xF4_x80_ERRRuleLock0_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x90_TYPE,
+    D0F2xF4_x90_ADDRESS,
+    D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK,
+    (0x1 << D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x92_TYPE,
+    D0F2xF4_x92_ADDRESS,
+    D0F2xF4_x92_PprIntcoallesceEn_MASK | D0F2xF4_x92_PprIntreqdelay_MASK | D0F2xF4_x92_PprInttimedelay_MASK,
+    (0x0 << D0F2xF4_x92_PprIntcoallesceEn_OFFSET) | (0x20 << D0F2xF4_x92_PprIntreqdelay_OFFSET) | (0x15 << D0F2xF4_x92_PprInttimedelay_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x94_TYPE,
+    D0F2xF4_x94_ADDRESS,
+    D0F2xF4_x94_L2bregHostPgsize_MASK | D0F2xF4_x94_L2bregGstPgsize_MASK,
+    (0x2 << D0F2xF4_x94_L2bregHostPgsize_OFFSET) | (0x2ull << D0F2xF4_x94_L2bregGstPgsize_OFFSET)
+    ),
+//IOMMU L1 Initialization
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// IOMMU Initialization
+  GNB_ENTRY_RMW (
+    D0F2x70_TYPE,
+    D0F2x70_ADDRESS,
+    D0F2x70_PcSupW_MASK,
+    (0x0 << D0F2x70_PcSupW_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x64_x0D_TYPE,
+    D0F0x64_x0D_ADDRESS,
+    D0F0x64_x0D_PciDev0Fn2RegEn_MASK,
+    (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET)
+    ),
+// IOMMU L2 clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING,
+    D0F2xF4_x33_TYPE,
+    D0F2xF4_x33_ADDRESS,
+    D0F2xF4_x33_CKGateL2ARegsDisable_MASK | D0F2xF4_x33_CKGateL2ADynamicDisable_MASK | D0F2xF4_x33_CKGateL2ACacheDisable_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING,
+    D0F2xF4_x90_TYPE,
+    D0F2xF4_x90_ADDRESS,
+    D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK,
+    0x0
+    ),
+// IOMMU L1 clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// Configure IOMMU Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    0x0
+    ),
+// Hide IOMMU function if disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0x64_x0D_TYPE,
+    D0F0x64_x0D_ADDRESS,
+    D0F0x64_x0D_PciDev0Fn2RegEn_MASK,
+    0x0
+    ),
+  //NB P-state Configuration for Runtime
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_NBDPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableNbDpm_MASK,
+    (1 << D0F0xBC_x1F428_EnableNbDpm_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F638_TYPE,
+    D0F0xBC_x1F638_ADDRESS,
+    D0F0xBC_x1F638_NbdpmPeriod_MASK | D0F0xBC_x1F638_PginterlockPeriod_MASK,
+    (1 << D0F0xBC_x1F638_NbdpmPeriod_OFFSET) | (1 << D0F0xBC_x1F638_PginterlockPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH
+  ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Hysteresis_MASK | D0F0xBC_x1F5F8_SkipDPM0_MASK |
+    D0F0xBC_x1F5F8_SkipPG_MASK | D0F0xBC_x1F5F8_EnableNbPsi1_MASK | D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK,
+    (10 << D0F0xBC_x1F5F8_Hysteresis_OFFSET) | (1 << D0F0xBC_x1F5F8_SkipDPM0_OFFSET) |
+    (1 << D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET) | (1 << D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F6E4_TYPE,
+    D0F0xBC_x1F6E4_ADDRESS,
+    D0F0xBC_x1F6E4_DdrVoltFloor_MASK | D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK,
+    (0xFF << D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET) | (0xFF << D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_NBDPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_NBDPM,
+    0
+    ),
+
+//---------------------------------------------------------------------------
+// Configure PCIe Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LOADLINE_ENABLE,
+    TYPE_D0F0xBC ,
+    0x1f428 ,
+    0x40 ,
+    (1 << 6 )
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_LOADLINE_ENABLE,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_LOADLINE,
+    0
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbMidInitTableTN [] = {
+//---------------------------------------------------------------------------
+// Enable LCLK Deep Sleep
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LCLK_DEEP_SLEEP,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_DivId_MASK | GMMx7A0_RampDis_MASK | GMMx7A0_Hysteresis_MASK | GMMx7A0_SclkRunningMask_MASK | GMMx7A0_SmuBusyMask_MASK | GMMx7A0_PcieLclkIdle1Mask_MASK | GMMx7A0_PcieLclkIdle2Mask_MASK | GMMx7A0_L1imugfxIdleMask_MASK | GMMx7A0_L1imugppsbIdleMask_MASK | GMMx7A0_L1imubifIdleMask_MASK | GMMx7A0_L1imuintgenIdleMask_MASK | GMMx7A0_L2imuIdleMask_MASK | GMMx7A0_OrbIdleMask_MASK | GMMx7A0_OnInbWakeMask_MASK | GMMx7A0_OnInbWakeAckMask_MASK | GMMx7A0_OnOutbWakeMask_MASK | GMMx7A0_OnOutbWakeAckMask_MASK | GMMx7A0_DmaactiveMask_MASK,
+    (0x5 << GMMx7A0_DivId_OFFSET) | (0x0 << GMMx7A0_RampDis_OFFSET) | (0xF << GMMx7A0_Hysteresis_OFFSET) | (0x1 << GMMx7A0_SclkRunningMask_OFFSET) | (0x1 << GMMx7A0_SmuBusyMask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle1Mask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle2Mask_OFFSET) | (0x1 << GMMx7A0_L1imugfxIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imugppsbIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imubifIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imuintgenIdleMask_OFFSET) | (0x1 << GMMx7A0_L2imuIdleMask_OFFSET) | (0x1 << GMMx7A0_OrbIdleMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_DmaactiveMask_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_SclkRunningMask_MASK,
+    0x0
+    ),
+// Reset : 0, Enable : 1
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LCLK_DEEP_SLEEP,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_EnableDs_MASK,
+    (0x1 << GMMx7A0_EnableDs_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// LCLK DPM init
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0000120_TYPE,
+    D0F0xBC_xE0000120_ADDRESS,
+    D0F0xBC_xE0000120_BusyCntSel_MASK | D0F0xBC_xE0000120_ActivityCntRst_MASK |
+    D0F0xBC_xE0000120_PeriodCntRst_MASK | D0F0xBC_xE0000120_EnOrbUsCnt_MASK |
+    D0F0xBC_xE0000120_EnOrbDsCnt_MASK,
+    (0x3 << D0F0xBC_xE0000120_BusyCntSel_OFFSET) | (0 << D0F0xBC_xE0000120_ActivityCntRst_OFFSET) |
+    (0x0 << D0F0xBC_xE0000120_PeriodCntRst_OFFSET) | (0x1 << D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET) |
+    (0x1 << D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET)
+    ),
+  //Programming Lclk Thermal Throttling Threshold in GnbLclkDpmInitTN()
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F308_TYPE,
+    D0F0xBC_x1F308_ADDRESS,
+    D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK,
+    (0x1 << D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_LclkDpm_MASK,
+    (0x1 << D0F0xBC_x1F460_LclkDpm_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// ORB clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_ORB_CLK_GATING,
+    D0F0x98_x49_TYPE,
+    D0F0x98_x49_ADDRESS,
+    D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_ORB_CLK_GATING,
+    D0F0x98_x4A_TYPE,
+    D0F0x98_x4A_ADDRESS,
+    D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK,
+    (1 << D0F0x98_x4A_SoftOverrideClk0_OFFSET)
+    ),
+
+//---------------------------------------------------------------------------
+// IOC clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING,
+    D0F0x64_x22_TYPE,
+    D0F0x64_x22_ADDRESS,
+    D0F0x64_x22_SoftOverrideClk4_MASK | D0F0x64_x22_SoftOverrideClk3_MASK | D0F0x64_x22_SoftOverrideClk2_MASK | D0F0x64_x22_SoftOverrideClk1_MASK | D0F0x64_x22_SoftOverrideClk0_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING,
+    D0F0x64_x23_TYPE,
+    D0F0x64_x23_ADDRESS,
+    D0F0x64_x23_SoftOverrideClk4_MASK | D0F0x64_x23_SoftOverrideClk3_MASK | D0F0x64_x23_SoftOverrideClk2_MASK | D0F0x64_x23_SoftOverrideClk1_MASK | D0F0x64_x23_SoftOverrideClk0_MASK,
+    0x0
+    ),
+
+//---------------------------------------------------------------------------
+// Shutdown IOMMU if disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    1 << D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300018_P1Select_OFFSET) | (1 << D0F0xBC_xE0300018_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300208_TYPE,
+    0xe0300208 ,
+    D0F0xBC_xE0300208_P1IsoN_MASK,
+    0 << D0F0xBC_xE0300208_P1IsoN_OFFSET
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300208 ,
+    0x2000 ,
+    1 << 13
+    ),
+  GNB_ENTRY_STALL (10),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+  GNB_ENTRY_TERMINATE
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
new file mode 100644
index 0000000000..f3bf14af5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
@@ -0,0 +1,242 @@
+/**
+ * @file
+ *
+ * ALIB SSDT table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63659 $   @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBSSDTTNFM2_H_
+#define _PCIEALIBSSDTTNFM2_H_
+
+UINT8  AlibSsdtTNFM2[] = {
+  0x53, 0x53, 0x44, 0x54, 0x1F, 0x05, 0x00, 0x00,
+  0x02, 0xE2, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+  0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
+  0x00, 0x00, 0x00, 0x04, 0x10, 0x4A, 0x4F, 0x5C,
+  0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30,
+  0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31,
+  0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, 0x44,
+  0x30, 0x31, 0x41, 0x30, 0x31, 0x33, 0x14, 0x31,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x72, 0x41, 0x30,
+  0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60,
+  0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, 0x30,
+  0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, 0x81,
+  0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, 0x41, 0x30,
+  0x31, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x31, 0x35,
+  0x14, 0x32, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x72,
+  0x41, 0x30, 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C,
+  0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80,
+  0x41, 0x30, 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04,
+  0x5B, 0x81, 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03,
+  0x41, 0x30, 0x31, 0x35, 0x20, 0x70, 0x6A, 0x41,
+  0x30, 0x31, 0x35, 0x14, 0x1C, 0x41, 0x30, 0x31,
+  0x36, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x36, 0x68,
+  0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B,
+  0x60, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60,
+  0x5B, 0x01, 0x41, 0x30, 0x31, 0x37, 0x00, 0x14,
+  0x32, 0x41, 0x30, 0x31, 0x38, 0x02, 0x5B, 0x23,
+  0x41, 0x30, 0x31, 0x37, 0xFF, 0xFF, 0x70, 0x79,
+  0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00,
+  0x60, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE0,
+  0x69, 0x70, 0x41, 0x30, 0x30, 0x36, 0x60, 0x0A,
+  0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x31, 0x37,
+  0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x31, 0x39,
+  0x03, 0x5B, 0x23, 0x41, 0x30, 0x31, 0x37, 0xFF,
+  0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00,
+  0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, 0x37,
+  0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, 0x37,
+  0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, 0x30,
+  0x31, 0x37, 0x14, 0x1C, 0x41, 0x30, 0x32, 0x30,
+  0x04, 0x70, 0x41, 0x30, 0x31, 0x38, 0x68, 0x69,
+  0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, 0x60,
+  0x41, 0x30, 0x31, 0x39, 0x68, 0x69, 0x60, 0x5B,
+  0x01, 0x41, 0x30, 0x32, 0x31, 0x00, 0x14, 0x29,
+  0x41, 0x30, 0x30, 0x38, 0x03, 0x5B, 0x23, 0x41,
+  0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, 0x30, 0x30,
+  0x37, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, 0x60,
+  0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0xA4, 0x60,
+  0x14, 0x26, 0x41, 0x30, 0x31, 0x32, 0x04, 0x5B,
+  0x23, 0x41, 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41,
+  0x30, 0x30, 0x37, 0x68, 0x69, 0x6A, 0x41, 0x30,
+  0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00,
+  0x6B, 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0x14,
+  0x1E, 0x41, 0x30, 0x32, 0x32, 0x05, 0x70, 0x41,
+  0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x60, 0x7D,
+  0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, 0x30,
+  0x31, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x42,
+  0x05, 0x41, 0x30, 0x32, 0x33, 0x02, 0x70, 0x0A,
+  0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60,
+  0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, 0x7B,
+  0x41, 0x30, 0x30, 0x36, 0x68, 0x61, 0x0A, 0xFF,
+  0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, 0x00,
+  0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70,
+  0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4,
+  0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x32, 0x34,
+  0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01,
+  0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10,
+  0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52,
+  0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, 0x5B,
+  0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, 0x4D,
+  0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, 0x42,
+  0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, 0x46,
+  0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, 0x08,
+  0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, 0x03,
+  0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, 0x44,
+  0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, 0x17,
+  0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, 0x00,
+  0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, 0x41,
+  0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, 0x22,
+  0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, 0x42,
+  0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, 0x60,
+  0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF,
+  0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44,
+  0x41, 0x08, 0x41, 0x30, 0x32, 0x35, 0x11, 0x04,
+  0x0B, 0x00, 0x01, 0x14, 0x46, 0x08, 0x41, 0x30,
+  0x30, 0x39, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B,
+  0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00,
+  0x0A, 0x02, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x00, 0x30, 0x00, 0xE0,
+  0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0xFE,
+  0xFF, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0A, 0x01,
+  0x00, 0x00, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60,
+  0x79, 0x68, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30,
+  0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00,
+  0x30, 0x00, 0xE0, 0x60, 0xA2, 0x16, 0x92, 0x93,
+  0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x01,
+  0x00, 0x0A, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B,
+  0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00,
+  0x0A, 0x02, 0x08, 0x41, 0x30, 0x30, 0x32, 0x0A,
+  0x00, 0x08, 0x41, 0x30, 0x30, 0x33, 0x0A, 0x00,
+  0x08, 0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x14,
+  0x46, 0x0B, 0x41, 0x30, 0x30, 0x35, 0x01, 0x70,
+  0x7D, 0x79, 0x0A, 0x18, 0x0A, 0x03, 0x00, 0x0A,
+  0x04, 0x00, 0x62, 0xA0, 0x1C, 0x93, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x62, 0x0B, 0x24, 0x01, 0x41, 0x30, 0x30,
+  0x33, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x34,
+  0x70, 0x41, 0x30, 0x30, 0x36, 0x62, 0x0B, 0x24,
+  0x01, 0x63, 0xA0, 0x13, 0x93, 0x68, 0x0A, 0x00,
+  0x7D, 0x63, 0x7B, 0x41, 0x30, 0x30, 0x33, 0x0C,
+  0x00, 0x00, 0x40, 0x00, 0x00, 0x63, 0xA1, 0x09,
+  0x7B, 0x63, 0x0C, 0xFF, 0xFF, 0xBF, 0xFF, 0x63,
+  0x41, 0x30, 0x30, 0x37, 0x62, 0x0B, 0x24, 0x01,
+  0x63, 0xA0, 0x36, 0x93, 0x41, 0x30, 0x30, 0x32,
+  0x0A, 0x00, 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x08, 0x0A, 0x00, 0x0C, 0xFF, 0xFF,
+  0xFF, 0xFF, 0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00,
+  0x0A, 0x02, 0x61, 0xA0, 0x0C, 0x93, 0x61, 0x0A,
+  0x02, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x32,
+  0xA0, 0x1D, 0x93, 0x41, 0x30, 0x30, 0x32, 0x0A,
+  0x01, 0xA0, 0x09, 0x93, 0x68, 0x0A, 0x00, 0x70,
+  0x0A, 0x20, 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x21,
+  0x60, 0x41, 0x30, 0x30, 0x39, 0x60, 0x08, 0x41,
+  0x30, 0x31, 0x30, 0x0A, 0x00, 0x08, 0x41, 0x30,
+  0x31, 0x31, 0x0A, 0x00, 0x14, 0x48, 0x07, 0x41,
+  0x57, 0x41, 0x4B, 0x01, 0xA0, 0x40, 0x07, 0x93,
+  0x68, 0x0A, 0x03, 0xA0, 0x2E, 0x93, 0x41, 0x30,
+  0x31, 0x30, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x60, 0x41,
+  0x30, 0x30, 0x37, 0x0A, 0xC5, 0x0B, 0x70, 0x01,
+  0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01, 0x0A, 0x0E,
+  0x00, 0x00, 0x00, 0x70, 0x0A, 0x00, 0x41, 0x30,
+  0x31, 0x30, 0xA0, 0x3A, 0x93, 0x41, 0x30, 0x31,
+  0x31, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01,
+  0x00, 0x60, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00, 0x7D,
+  0x60, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00,
+  0x41, 0x30, 0x30, 0x39, 0x0A, 0x16, 0x70, 0x0A,
+  0x00, 0x41, 0x30, 0x31, 0x31, 0x14, 0x49, 0x08,
+  0x41, 0x50, 0x54, 0x53, 0x01, 0xA0, 0x41, 0x08,
+  0x93, 0x68, 0x0A, 0x03, 0x41, 0x30, 0x30, 0x35,
+  0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00,
+  0x60, 0xA0, 0x33, 0x92, 0x93, 0x7B, 0x60, 0x79,
+  0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x28, 0xF4, 0x01, 0x00, 0x7B, 0x60, 0x80,
+  0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00, 0x00,
+  0x41, 0x30, 0x30, 0x39, 0x0A, 0x16, 0x70, 0x0A,
+  0x01, 0x41, 0x30, 0x31, 0x31, 0x70, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x60,
+  0xA0, 0x26, 0x93, 0x7B, 0x60, 0x79, 0x0A, 0x01,
+  0x0A, 0x0E, 0x00, 0x00, 0x0A, 0x00, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x7D,
+  0x60, 0x79, 0x0A, 0x01, 0x0A, 0x0E, 0x00, 0x00,
+  0x70, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x30
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
new file mode 100644
index 0000000000..e9776d0be3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
@@ -0,0 +1,1065 @@
+/**
+ * @file
+ *
+ * ALIB SSDT table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBSSDTTNFS1_H_
+#define _PCIEALIBSSDTTNFS1_H_
+
+UINT8  AlibSsdtTNFS1[] = {
+  0x53, 0x53, 0x44, 0x54, 0xD4, 0x1E, 0x00, 0x00,
+  0x02, 0x5C, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+  0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
+  0x00, 0x00, 0x00, 0x04, 0x10, 0x8F, 0xEA, 0x01,
+  0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30,
+  0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30,
+  0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x32,
+  0x41, 0x30, 0x32, 0x39, 0x08, 0x41, 0x44, 0x30,
+  0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x33,
+  0x41, 0x30, 0x33, 0x30, 0x08, 0x41, 0x44, 0x30,
+  0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x34,
+  0x41, 0x30, 0x33, 0x31, 0x08, 0x41, 0x44, 0x30,
+  0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x35,
+  0x41, 0x30, 0x33, 0x32, 0x08, 0x41, 0x44, 0x30,
+  0x36, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
+  0x36, 0x41, 0x30, 0x33, 0x33, 0x08, 0x41, 0x44,
+  0x30, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44,
+  0x30, 0x38, 0x41, 0x30, 0x33, 0x34, 0x08, 0x41,
+  0x30, 0x33, 0x35, 0x0A, 0x00, 0x08, 0x41, 0x30,
+  0x33, 0x36, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33,
+  0x37, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x33, 0x38,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33, 0x39,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x30,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x30, 0x39,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x39,
+  0x41, 0x30, 0x31, 0x39, 0x08, 0x41, 0x30, 0x34,
+  0x31, 0x12, 0x12, 0x08, 0x0A, 0x01, 0x0A, 0x01,
+  0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01,
+  0x0A, 0x01, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x34,
+  0x32, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31,
+  0x37, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x31, 0x30,
+  0x12, 0x0A, 0x04, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x31, 0x30,
+  0x41, 0x30, 0x34, 0x34, 0x14, 0x44, 0x09, 0x41,
+  0x30, 0x34, 0x35, 0x09, 0x70, 0x83, 0x88, 0x68,
+  0x0A, 0x02, 0x00, 0x61, 0x70, 0x41, 0x30, 0x30,
+  0x33, 0x60, 0x70, 0x61, 0x41, 0x30, 0x33, 0x36,
+  0x7D, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x79,
+  0x0A, 0x01, 0x0A, 0x06, 0x00, 0x62, 0x7D, 0x79,
+  0x41, 0x30, 0x33, 0x36, 0x0A, 0x05, 0x00, 0x79,
+  0x41, 0x30, 0x33, 0x37, 0x0A, 0x06, 0x00, 0x63,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0x60,
+  0x0A, 0xF4, 0x80, 0x62, 0x00, 0x7B, 0x62, 0x63,
+  0x00, 0xA0, 0x07, 0x93, 0x61, 0x60, 0xA4, 0x0A,
+  0x00, 0x41, 0x30, 0x31, 0x33, 0x41, 0x30, 0x33,
+  0x36, 0xA0, 0x0E, 0x93, 0x41, 0x30, 0x32, 0x39,
+  0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01,
+  0xA0, 0x15, 0x91, 0x92, 0x94, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x04, 0xA4, 0x0A, 0x00, 0xA0, 0x0B,
+  0x93, 0x41, 0x30, 0x33, 0x35, 0x0A, 0x00, 0xA4,
+  0x0A, 0x00, 0x41, 0x30, 0x34, 0x36, 0xA4, 0x0A,
+  0x00, 0x14, 0x24, 0x41, 0x30, 0x34, 0x37, 0x01,
+  0x70, 0x41, 0x30, 0x34, 0x38, 0x68, 0x67, 0x70,
+  0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x60, 0xA0,
+  0x08, 0x92, 0x93, 0x60, 0x0A, 0x02, 0xA4, 0x67,
+  0x41, 0x30, 0x34, 0x36, 0xA4, 0x67, 0x14, 0x4E,
+  0x1B, 0x41, 0x30, 0x34, 0x38, 0x01, 0x08, 0x41,
+  0x30, 0x34, 0x39, 0x0A, 0x00, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x37, 0x70, 0x11, 0x03, 0x0A,
+  0x0A, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30,
+  0x35, 0x30, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x35,
+  0x30, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x35,
+  0x31, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x35, 0x31,
+  0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, 0x93,
+  0x41, 0x30, 0x33, 0x35, 0x0A, 0x00, 0xA4, 0x67,
+  0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x35, 0x32,
+  0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x35, 0x33,
+  0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, 0x34,
+  0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x35, 0x35,
+  0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x35, 0x36,
+  0x7B, 0x7A, 0x41, 0x30, 0x35, 0x32, 0x0A, 0x08,
+  0x00, 0x0A, 0xFF, 0x41, 0x30, 0x34, 0x39, 0xA2,
+  0x47, 0x05, 0x92, 0x94, 0x41, 0x30, 0x31, 0x37,
+  0x41, 0x30, 0x30, 0x31, 0xA0, 0x45, 0x04, 0x93,
+  0x41, 0x30, 0x31, 0x38, 0x41, 0x30, 0x31, 0x37,
+  0x0A, 0x01, 0x70, 0x41, 0x30, 0x31, 0x34, 0x79,
+  0x72, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x02, 0x00,
+  0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, 0x7A,
+  0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, 0x7B,
+  0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x61,
+  0xA0, 0x11, 0x90, 0x92, 0x95, 0x41, 0x30, 0x34,
+  0x39, 0x61, 0x92, 0x94, 0x41, 0x30, 0x34, 0x39,
+  0x62, 0xA5, 0x75, 0x41, 0x30, 0x31, 0x37, 0xA0,
+  0x0C, 0x94, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30,
+  0x30, 0x31, 0xA4, 0x67, 0xA0, 0x1E, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x38, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x35,
+  0x32, 0x88, 0x41, 0x30, 0x33, 0x38, 0x41, 0x30,
+  0x31, 0x37, 0x00, 0xA1, 0x16, 0xA0, 0x14, 0x92,
+  0x93, 0x83, 0x88, 0x41, 0x30, 0x33, 0x38, 0x41,
+  0x30, 0x31, 0x37, 0x00, 0x41, 0x30, 0x35, 0x32,
+  0xA4, 0x67, 0x70, 0x0A, 0x00, 0x88, 0x41, 0x30,
+  0x34, 0x32, 0x41, 0x30, 0x31, 0x37, 0x00, 0xA0,
+  0x15, 0x93, 0x41, 0x30, 0x35, 0x36, 0x0A, 0x00,
+  0x70, 0x0A, 0x00, 0x88, 0x41, 0x30, 0x33, 0x38,
+  0x41, 0x30, 0x31, 0x37, 0x00, 0xA0, 0x15, 0x93,
+  0x41, 0x30, 0x35, 0x36, 0x0A, 0x01, 0x70, 0x0A,
+  0x01, 0x88, 0x41, 0x30, 0x34, 0x32, 0x41, 0x30,
+  0x31, 0x37, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30,
+  0x35, 0x36, 0x0A, 0x02, 0x70, 0x0A, 0x01, 0x88,
+  0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x31, 0x37,
+  0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x35, 0x36,
+  0x0A, 0x03, 0x70, 0x0A, 0x02, 0x88, 0x41, 0x30,
+  0x34, 0x30, 0x41, 0x30, 0x31, 0x37, 0x00, 0xA0,
+  0x24, 0x93, 0x7B, 0x41, 0x30, 0x35, 0x33, 0x41,
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+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x00, 0x30, 0x00, 0xE0, 0x60, 0x7D, 0x7B,
+  0x60, 0x0C, 0x00, 0x00, 0xFE, 0xFF, 0x00, 0x7B,
+  0x80, 0x7B, 0x60, 0x0A, 0x01, 0x00, 0x00, 0x0A,
+  0x01, 0x00, 0x60, 0x7D, 0x60, 0x79, 0x68, 0x0A,
+  0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x36, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x00, 0x30, 0x00, 0xE0,
+  0x60, 0xA2, 0x16, 0x92, 0x93, 0x7B, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x04,
+  0x30, 0x00, 0xE0, 0x0A, 0x01, 0x00, 0x0A, 0x01,
+  0xA2, 0x16, 0x92, 0x93, 0x7B, 0x41, 0x30, 0x30,
+  0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x04, 0x30,
+  0x00, 0xE0, 0x0A, 0x02, 0x00, 0x0A, 0x02, 0x14,
+  0x1D, 0x41, 0x30, 0x36, 0x39, 0x01, 0x70, 0x41,
+  0x30, 0x36, 0x35, 0x68, 0x0A, 0xA4, 0x61, 0x7A,
+  0x61, 0x0A, 0x0D, 0x62, 0x7B, 0x62, 0x0A, 0x03,
+  0x62, 0x75, 0x62, 0xA4, 0x62, 0x14, 0x4C, 0x0E,
+  0x41, 0x30, 0x36, 0x31, 0x0A, 0xA0, 0x12, 0x93,
+  0x68, 0x0A, 0x01, 0x70, 0x83, 0x88, 0x41, 0x30,
+  0x34, 0x34, 0x41, 0x30, 0x33, 0x31, 0x00, 0x63,
+  0xA1, 0x0E, 0x70, 0x83, 0x88, 0x41, 0x30, 0x34,
+  0x34, 0x41, 0x30, 0x33, 0x30, 0x00, 0x63, 0x7B,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x3C, 0x20, 0x00, 0xE0, 0x0A, 0x04, 0x62,
+  0x7B, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x40, 0x20, 0x00, 0xE0, 0x0A, 0x01,
+  0x61, 0xA2, 0x1A, 0x92, 0x93, 0x79, 0x61, 0x0A,
+  0x02, 0x00, 0x62, 0x7B, 0x41, 0x30, 0x30, 0x37,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x40, 0x20, 0x00,
+  0xE0, 0x0A, 0x01, 0x61, 0x70, 0x41, 0x30, 0x30,
+  0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x3C, 0x20,
+  0x00, 0xE0, 0x61, 0xA0, 0x0D, 0x93, 0x68, 0x0A,
+  0x01, 0x7B, 0x61, 0x0C, 0xFD, 0xFF, 0xFF, 0xFF,
+  0x61, 0xA1, 0x06, 0x7D, 0x61, 0x0A, 0x02, 0x61,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x3C, 0x20, 0x00, 0xE0, 0x61, 0x7B, 0x61,
+  0x80, 0x79, 0x0A, 0xFF, 0x0A, 0x08, 0x00, 0x00,
+  0x61, 0x7D, 0x61, 0x79, 0x63, 0x0A, 0x08, 0x00,
+  0x61, 0x7B, 0x80, 0x61, 0x00, 0x0A, 0x04, 0x62,
+  0x7D, 0x7B, 0x61, 0x80, 0x0A, 0x04, 0x00, 0x00,
+  0x62, 0x61, 0x41, 0x30, 0x30, 0x36, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x3C, 0x20, 0x00, 0xE0, 0x61,
+  0xA0, 0x21, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2,
+  0x1A, 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00,
+  0x62, 0x7B, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x40, 0x20, 0x00, 0xE0, 0x0A,
+  0x01, 0x61, 0x14, 0x42, 0x14, 0x41, 0x30, 0x30,
+  0x32, 0x01, 0x70, 0x41, 0x30, 0x30, 0x33, 0x61,
+  0x70, 0x0A, 0x00, 0x65, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF3, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x00,
+  0x41, 0x30, 0x30, 0x35, 0x0A, 0x09, 0xA0, 0x48,
+  0x05, 0x93, 0x61, 0x0A, 0x00, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x54, 0xF9,
+  0x01, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x00,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF,
+  0xFF, 0xFF, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x70, 0x0C, 0x01, 0x00, 0x05, 0x00, 0x66, 0xA1,
+  0x44, 0x0A, 0xA0, 0x4F, 0x05, 0x93, 0x68, 0x0A,
+  0x01, 0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x00, 0xFE, 0x01, 0x00, 0x65,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x54, 0xF9, 0x01, 0x00, 0x65, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00,
+  0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF,
+  0x0A, 0x01, 0x41, 0x30, 0x30, 0x34, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C,
+  0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0,
+  0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF,
+  0x0A, 0x00, 0xA1, 0x3D, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF,
+  0xFF, 0xFF, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x70, 0x0A, 0x01, 0x66, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF3, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0x00, 0xFF, 0x66, 0x41,
+  0x30, 0x30, 0x35, 0x0A, 0x09, 0x14, 0x47, 0x07,
+  0x41, 0x30, 0x30, 0x38, 0x03, 0xA0, 0x0A, 0x94,
+  0x68, 0x69, 0x70, 0x69, 0x63, 0x70, 0x68, 0x64,
+  0xA1, 0x07, 0x70, 0x68, 0x63, 0x70, 0x69, 0x64,
+  0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x9C, 0xF3, 0x01, 0x00, 0x60, 0x7B,
+  0x60, 0x0A, 0x18, 0x60, 0xA0, 0x18, 0x93, 0x6A,
+  0x0A, 0x00, 0x7D, 0x7D, 0x79, 0x64, 0x0A, 0x18,
+  0x00, 0x79, 0x63, 0x0A, 0x10, 0x00, 0x00, 0x7D,
+  0x60, 0x0A, 0x03, 0x00, 0x60, 0xA0, 0x18, 0x93,
+  0x6A, 0x0A, 0x01, 0x7D, 0x7D, 0x79, 0x64, 0x0A,
+  0x18, 0x00, 0x79, 0x63, 0x0A, 0x10, 0x00, 0x00,
+  0x7D, 0x60, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x9C,
+  0xF3, 0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x35,
+  0x74, 0x0A, 0x03, 0x6A, 0x00, 0x14, 0x06, 0x41,
+  0x30, 0x30, 0x39, 0x01, 0x08, 0x41, 0x30, 0x31,
+  0x30, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x31,
+  0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x32, 0x0A,
+  0x00, 0x14, 0x46, 0x0B, 0x41, 0x30, 0x31, 0x33,
+  0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, 0x0A, 0x03,
+  0x00, 0x0A, 0x04, 0x00, 0x62, 0xA0, 0x1C, 0x93,
+  0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0x70, 0x41,
+  0x30, 0x31, 0x34, 0x62, 0x0B, 0x24, 0x01, 0x41,
+  0x30, 0x31, 0x31, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x31, 0x32, 0x70, 0x41, 0x30, 0x31, 0x34, 0x62,
+  0x0B, 0x24, 0x01, 0x63, 0xA0, 0x13, 0x93, 0x68,
+  0x0A, 0x00, 0x7D, 0x63, 0x7B, 0x41, 0x30, 0x31,
+  0x31, 0x0C, 0x00, 0x00, 0x40, 0x00, 0x00, 0x63,
+  0xA1, 0x09, 0x7B, 0x63, 0x0C, 0xFF, 0xFF, 0xBF,
+  0xFF, 0x63, 0x41, 0x30, 0x31, 0x35, 0x62, 0x0B,
+  0x24, 0x01, 0x63, 0xA0, 0x36, 0x93, 0x41, 0x30,
+  0x31, 0x30, 0x0A, 0x00, 0xA0, 0x2D, 0x93, 0x41,
+  0x30, 0x31, 0x34, 0x0A, 0x08, 0x0A, 0x00, 0x0C,
+  0xFF, 0xFF, 0xFF, 0xFF, 0x7B, 0x41, 0x30, 0x30,
+  0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4,
+  0x01, 0x00, 0x0A, 0x02, 0x61, 0xA0, 0x0C, 0x93,
+  0x61, 0x0A, 0x02, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x31, 0x30, 0xA0, 0x1D, 0x93, 0x41, 0x30, 0x31,
+  0x30, 0x0A, 0x01, 0xA0, 0x09, 0x93, 0x68, 0x0A,
+  0x00, 0x70, 0x0A, 0x20, 0x60, 0xA1, 0x05, 0x70,
+  0x0A, 0x21, 0x60, 0x41, 0x30, 0x30, 0x35, 0x60,
+  0x14, 0x48, 0x08, 0x41, 0x30, 0x31, 0x36, 0x00,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x70,
+  0x0A, 0x00, 0x61, 0xA2, 0x3E, 0x92, 0x94, 0x41,
+  0x30, 0x31, 0x37, 0x41, 0x30, 0x30, 0x31, 0xA0,
+  0x12, 0x93, 0x41, 0x30, 0x31, 0x38, 0x41, 0x30,
+  0x31, 0x37, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x31,
+  0x37, 0x9F, 0xA0, 0x1A, 0x93, 0x83, 0x88, 0x41,
+  0x30, 0x31, 0x39, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x0A, 0x02, 0x7D, 0x41, 0x30, 0x32, 0x30, 0x41,
+  0x30, 0x31, 0x37, 0x61, 0x61, 0x75, 0x41, 0x30,
+  0x31, 0x37, 0x70, 0x79, 0x61, 0x0A, 0x18, 0x00,
+  0x62, 0x7D, 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00,
+  0x0B, 0x00, 0xFF, 0x00, 0x62, 0x62, 0x7D, 0x7B,
+  0x79, 0x61, 0x0A, 0x08, 0x00, 0x0C, 0x00, 0x00,
+  0xFF, 0x00, 0x00, 0x62, 0x62, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x10, 0xF6,
+  0x01, 0x00, 0x62, 0x41, 0x30, 0x30, 0x35, 0x0A,
+  0x08, 0x14, 0x4E, 0x0E, 0x41, 0x30, 0x32, 0x30,
+  0x01, 0x70, 0x41, 0x30, 0x32, 0x31, 0x68, 0x67,
+  0x70, 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41,
+  0x30, 0x32, 0x32, 0x70, 0x83, 0x88, 0x67, 0x0A,
+  0x01, 0x00, 0x41, 0x30, 0x32, 0x33, 0x70, 0x83,
+  0x88, 0x67, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x32,
+  0x34, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x03, 0x00,
+  0x41, 0x30, 0x32, 0x35, 0x70, 0x7D, 0x79, 0x83,
+  0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, 0x00,
+  0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, 0x0A,
+  0x05, 0x00, 0x00, 0x41, 0x30, 0x32, 0x36, 0x70,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xE0,
+  0x7D, 0x79, 0x41, 0x30, 0x32, 0x36, 0x0A, 0x10,
+  0x00, 0x0B, 0x23, 0x80, 0x00, 0x65, 0x7A, 0x65,
+  0x41, 0x30, 0x32, 0x34, 0x65, 0x79, 0x0A, 0x01,
+  0x72, 0x74, 0x41, 0x30, 0x32, 0x35, 0x41, 0x30,
+  0x32, 0x34, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x74,
+  0x62, 0x0A, 0x01, 0x62, 0x7B, 0x65, 0x62, 0x65,
+  0xA0, 0x26, 0x94, 0x41, 0x30, 0x32, 0x32, 0x41,
+  0x30, 0x32, 0x33, 0x70, 0x41, 0x30, 0x32, 0x33,
+  0x63, 0x70, 0x41, 0x30, 0x32, 0x32, 0x64, 0x74,
+  0x74, 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x32,
+  0x34, 0x00, 0x74, 0x64, 0x63, 0x00, 0x61, 0xA1,
+  0x11, 0x70, 0x41, 0x30, 0x32, 0x33, 0x64, 0x70,
+  0x41, 0x30, 0x32, 0x32, 0x63, 0x70, 0x0A, 0x00,
+  0x61, 0x79, 0x0A, 0x01, 0x72, 0x74, 0x64, 0x63,
+  0x00, 0x0A, 0x01, 0x00, 0x62, 0x79, 0x74, 0x62,
+  0x0A, 0x01, 0x00, 0x61, 0x62, 0x7B, 0x62, 0x80,
+  0x65, 0x00, 0x62, 0x79, 0x74, 0x62, 0x0A, 0x01,
+  0x00, 0x74, 0x63, 0x61, 0x00, 0x62, 0xA4, 0x62,
+  0x08, 0x41, 0x30, 0x32, 0x37, 0x0A, 0x00, 0x08,
+  0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x14, 0x43,
+  0x08, 0x41, 0x57, 0x41, 0x4B, 0x01, 0xA0, 0x40,
+  0x07, 0x93, 0x68, 0x0A, 0x03, 0xA0, 0x2E, 0x93,
+  0x41, 0x30, 0x32, 0x37, 0x0A, 0x01, 0x70, 0x41,
+  0x30, 0x31, 0x34, 0x0A, 0xC5, 0x0B, 0x70, 0x01,
+  0x60, 0x41, 0x30, 0x31, 0x35, 0x0A, 0xC5, 0x0B,
+  0x70, 0x01, 0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01,
+  0x0A, 0x0E, 0x00, 0x00, 0x00, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x32, 0x37, 0xA0, 0x3A, 0x93, 0x41,
+  0x30, 0x32, 0x38, 0x0A, 0x01, 0x70, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28,
+  0xF4, 0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x36,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01,
+  0x00, 0x7D, 0x60, 0x79, 0x0A, 0x01, 0x0A, 0x05,
+  0x00, 0x00, 0x41, 0x30, 0x30, 0x35, 0x0A, 0x16,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x38, 0x70,
+  0x41, 0x30, 0x30, 0x33, 0x61, 0x41, 0x30, 0x31,
+  0x33, 0x61, 0x14, 0x49, 0x08, 0x41, 0x50, 0x54,
+  0x53, 0x01, 0xA0, 0x41, 0x08, 0x93, 0x68, 0x0A,
+  0x03, 0x41, 0x30, 0x31, 0x33, 0x0A, 0x01, 0x70,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x28, 0xF4, 0x01, 0x00, 0x60, 0xA0, 0x33,
+  0x92, 0x93, 0x7B, 0x60, 0x79, 0x0A, 0x01, 0x0A,
+  0x05, 0x00, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4,
+  0x01, 0x00, 0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01,
+  0x0A, 0x05, 0x00, 0x00, 0x00, 0x41, 0x30, 0x30,
+  0x35, 0x0A, 0x16, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x32, 0x38, 0x70, 0x41, 0x30, 0x31, 0x34, 0x0A,
+  0xC5, 0x0B, 0x70, 0x01, 0x60, 0xA0, 0x26, 0x93,
+  0x7B, 0x60, 0x79, 0x0A, 0x01, 0x0A, 0x0E, 0x00,
+  0x00, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x35, 0x0A,
+  0xC5, 0x0B, 0x70, 0x01, 0x7D, 0x60, 0x79, 0x0A,
+  0x01, 0x0A, 0x0E, 0x00, 0x00, 0x70, 0x0A, 0x01,
+  0x41, 0x30, 0x32, 0x37
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
new file mode 100644
index 0000000000..862909513e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "PcieAlibSsdtTNFM2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID *
+PcieAlibGetBaseTableTNFM2 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get base SSDT table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        pointer to SSTD table
+ */
+VOID *
+PcieAlibGetBaseTableTNFM2 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  return &AlibSsdtTNFM2[0];
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
new file mode 100644
index 0000000000..49bae5f302
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
@@ -0,0 +1,196 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63659 $   @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+DefinitionBlock (
+  "PcieAlibSsdtTN.aml",
+  "SSDT",
+  2,
+  "AMD",
+  "ALIB",
+  0x1
+  )
+{
+  Scope(\_SB) {
+
+    Name (varMaxPortIndexNumber, 6)
+
+    include ("PcieAlibMmioData.asl")
+    include ("PcieAlibPciLib.asl")
+    include ("PcieAlibDebugLib.asl")
+    include ("PcieSmuServiceV4.asl")
+
+
+    Name (varBapmControl, 0)
+    Name (varCstateIntControlState, 0)
+    Name (varIsStateInitialized, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  APM/PDM stub
+     *
+     *  Arg0 - AC/DC state
+     *
+     */
+    Method (procApmPdmActivate, 1, NotSerialized) {
+      Store (Or(ShiftLeft (0x18, 3), 4), Local2)
+      if (LEqual (varIsStateInitialized, 0)) {
+        Store (procPciDwordRead (Local2, 0x124), varCstateIntControlState)
+        Store (1, varIsStateInitialized)
+      }
+
+      Store (procPciDwordRead (Local2, 0x124), Local3)
+      if (LEqual (Arg0,DEF_PSPP_STATE_AC)) {
+        // Disable PC6 on AC
+        Or (Local3, And (varCstateIntControlState, 0x00400000), Local3)
+      } else {
+        // Enable PC6 on DC
+        And (Local3, 0xFFBFFFFF, Local3)
+      }
+      procPciDwordWrite (Local2, 0x124, Local3)
+
+      if (LEqual (varBapmControl, 0)) {
+        // If GFX present driver manage BAPM if not ALIB manage BAPM
+        if (LEqual (procPciDwordRead (0x08, 0x00), 0xffffffff)) {
+          And (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), 0x2, Local1);
+          // check if BAPM was enable during BIOS post
+          if (LEqual (Local1, 0x2)) {
+            Store (1, varBapmControl)
+          }
+        }
+      }
+      if (LEqual (varBapmControl,1)) {
+        if (LEqual (Arg0,DEF_PSPP_STATE_AC)) {
+          // Enable BAPM on AC
+          Store (32, Local0)
+        } else {
+          // Disable BAPM on DC
+          Store (33, Local0)
+        }
+        procNbSmuServiceRequest (Local0);
+      }
+    }
+
+    Name (varRestoreNbps, 0)
+    Name (varRestoreNbDpmState, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  _WAK
+     *
+     *
+     *
+     */
+    Method (AWAK, 1) {
+      if (LEqual (Arg0, 3)) {
+        // Clear D18F5x170 [SwNbPstateLoDis] only if it was 0 in APTS
+        if (LEqual (varRestoreNbps, 1)) {
+          Store (procPciDwordRead (0xC5, 0x170), Local0)
+          procPciDwordWrite (0xC5, 0x170, And (Local0, Not (ShiftLeft (1, 14))))
+           Store (0, varRestoreNbps);
+        }
+        if (LEqual (varRestoreNbDpmState, 1)) {
+          Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0)
+          procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, Or (Local0, ShiftLeft (1, 5)))
+          procNbSmuServiceRequest (22);
+          Store (0, varRestoreNbDpmState)
+        }
+      }
+    }
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  _PTS
+     *
+     *
+     *
+     */
+    Method (APTS, 1) {
+      if (LEqual (Arg0, 3)) {
+         procApmPdmActivate (DEF_PSPP_STATE_DC);
+         // Disable NBDPM
+         Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0)
+         if (LNotEqual (And (Local0, ShiftLeft (1, 5)), 0)) {
+           // NBDPM enabled lets disable it
+           procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, And (Local0, Not (ShiftLeft (1, 5))))
+           procNbSmuServiceRequest (22);
+           // Indicate needs to restore NBDPM
+           Store (1, varRestoreNbDpmState);
+         }
+         // Save state of D18F5x170 [SwNbPstateLoDis]
+         Store (procPciDwordRead (0xC5, 0x170), Local0)
+         if (LEqual (And (Local0, ShiftLeft (1, 14)), 0)) {
+          // Set D18F5x170 [SwNbPstateLoDis] = 1
+          procPciDwordWrite (0xC5, 0x170, Or (Local0, ShiftLeft (1, 14)))
+           Store (1, varRestoreNbps);
+         }
+      }
+    }
+  } //End of Scope(\_SB)
+}   //End of DefinitionBlock
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
new file mode 100644
index 0000000000..baa0f85ac1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "PcieAlibSsdtTNFS1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID *
+PcieAlibGetBaseTableTNFS1 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get base SSDT table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        pointer to SSTD table
+ */
+VOID *
+PcieAlibGetBaseTableTNFS1 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  return &AlibSsdtTNFS1[0];
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
new file mode 100644
index 0000000000..9c55714b93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
@@ -0,0 +1,491 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe configuration data definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECOMPLEXDATATN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+TN_COMPLEX_CONFIG ComplexDataTN = {
+  //Silicon
+  {
+    {
+      DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      0,
+      0,
+      offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon)
+    },
+    0,
+    0
+  },
+  //Gfx Wrapper
+  {
+    {
+      DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper)
+    },
+
+    GFX_WRAP_ID,
+    GFX_NUMBER_OF_PIFs,
+    GFX_START_PHY_LANE,
+    GFX_END_PHY_LANE,
+    GFX_CORE_ID,
+    GFX_CORE_ID,
+    16,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      1,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //Gpp Wrapper
+  {
+    {
+      DESCRIPTOR_PCIE_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper)
+    },
+    GPP_WRAP_ID,
+    GPP_NUMBER_OF_PIFs,
+    GPP_START_PHY_LANE,
+    GPP_END_PHY_LANE,
+    GPP_CORE_ID,
+    GPP_CORE_ID,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      1,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //DDI Wrapper
+  {
+    {
+      DESCRIPTOR_DDI_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper)
+    },
+    DDI_WRAP_ID,
+    DDI_NUMBER_OF_PIFs,
+    DDI_START_PHY_LANE,
+    DDI_END_PHY_LANE,
+    0xf,
+    0x0,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      0,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //DDI2 Wrapper
+  {
+    {
+      DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      0,
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper)
+    },
+    DDI2_WRAP_ID,
+    DDI2_NUMBER_OF_PIFs,
+    DDI2_START_PHY_LANE,
+    DDI2_END_PHY_LANE,
+    0xf,
+    0x0,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      0,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //Port 2
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, Port2),
+      0
+    },
+    { PciePortEngine, 8, 23},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        0,
+        15,
+        2,
+        0,
+        GFX_CORE_ID,
+        0,
+        {0},
+        LinkStateResetExit,
+        0,
+        2,
+        1
+      },
+    },
+  },
+  //Port 3
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, Port3),
+      0
+    },
+    { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        UNUSED_LANE_ID,
+        UNUSED_LANE_ID,
+        3,
+        0,
+        GFX_CORE_ID,
+        1,
+        {0},
+        LinkStateResetExit,
+        1,
+        3,
+        1
+      },
+    },
+  },
+  //DdiB
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, DpB),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DdiC
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, DpC),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                               //Initialization Status
+    0xFF                                             //Scratch
+  },
+  //DdiD
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, DpD),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                               //Initialization Status
+    0xFF                                             //Scratch
+  },
+
+  //Port 4
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, Port4),
+      0
+    },
+    { PciePortEngine, 4, 4},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        4,
+        4,
+        4,
+        0,
+        GPP_CORE_ID,
+        1,
+        {0},
+        LinkStateResetExit,
+        2,
+        0,
+        0
+      },
+    },
+  },
+  //Port 5
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, Port5),
+      0
+    },
+    { PciePortEngine, 5, 5},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        5,
+        5,
+        5,
+        0,
+        GPP_CORE_ID,
+        2,
+        {0},
+        LinkStateResetExit,
+        3,
+        0,
+        0
+      },
+    },
+  },
+  //Port 6
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, Port6),
+      0
+    },
+    { PciePortEngine, 6, 6 },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        6,
+        6,
+        6,
+        0,
+        GPP_CORE_ID,
+        3,
+        {0},
+        LinkStateResetExit,
+        4,
+        0,
+        0
+      },
+    },
+  },
+  //Port 7
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, Port7),
+      0
+    },
+    { PciePortEngine, 7, 7 },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        7,
+        7,
+        7,
+        0,
+        GPP_CORE_ID,
+        4,
+        {0},
+        LinkStateResetExit,
+        5,
+        0,
+        0
+      },
+    },
+  },
+  //Port 8
+  {
+    {
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, Port8),
+      0
+    },
+    { PciePortEngine, 0, 3 },
+    INIT_STATUS_PCIE_TRAINING_SUCCESS,            //Initialization Status
+    0xFF,                                         //Scratch
+    {
+      {
+        {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}},
+        0,
+        3,
+        8,
+        0,
+        GPP_CORE_ID,
+        0,
+        {MAKE_SBDFO (0, 0, 8, 0, 0)},
+        LinkStateTrainingSuccess,
+        6,
+        0,
+        0
+      },
+    },
+  },
+  //DpE
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DpE),
+      0
+    },
+   {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DpF
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, DpF),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DpA
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper),
+      0,
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //F12 specific Silicon
+  {
+    OscFuses,
+    {0, 0, 0, 0, 0, 0}
+  }
+};
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h
new file mode 100644
index 0000000000..623636cc06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIECOMPLEXDATATN_H_
+#define _PCIECOMPLEXDATATN_H_
+
+#define SOCKET_ID             0
+
+#define MAX_NUM_PHYs          2
+#define MAX_NUM_LANE_PER_PHY  8
+
+#define NUMBER_OF_PORTS     8
+#define NUMBER_OF_GPP_PORTS 5
+#define NUMBER_OF_GFX_PORTS 2
+#define NUMBER_OF_GFX_DDIS  3
+#define NUMBER_OF_DDIS      2
+#define NUMBER_OF_DDIS2     1
+#define NUMBER_OF_WRAPPERS  3
+#define NUMBER_OF_SILICONS  1
+
+#define GFX_WRAP_ID         1
+#define GFX_NUMBER_OF_PIFs  2
+#define GFX_START_PHY_LANE  8
+#define GFX_END_PHY_LANE    23
+#define GFX_CORE_ID         2
+
+#define GFX_CORE_x16        ((16 << 8) | 0)
+#define GFX_CORE_x8x8       ((8 << 8) | 8)
+
+#define GPP_WRAP_ID         0
+#define GPP_NUMBER_OF_PIFs  1
+#define GPP_START_PHY_LANE  0
+#define GPP_END_PHY_LANE    7
+#define GPP_CORE_ID         1
+
+#define GPP_CORE_x4x1x1x1x1   ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x1x1     ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x1x1_ST  ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x2       ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x2_ST    ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x4         ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
+
+#define DDI_WRAP_ID           2
+#define DDI_NUMBER_OF_PIFs    1
+#define DDI_START_PHY_LANE    24
+#define DDI_END_PHY_LANE      31
+
+#define DDI2_WRAP_ID          3
+#define DDI2_NUMBER_OF_PIFs   1
+#define DDI2_START_PHY_LANE   32
+#define DDI2_END_PHY_LANE     38
+
+///Gen2 capability
+typedef enum {
+  OscFuses,                   ///< Not capable
+  OscRO,                      ///< Gen2 with RO
+  OscLC,                      ///< Gen2 with LC
+  OscDefault,                 ///< Skip initialization of OSC
+} OSC_MODE;
+
+///Family specific silicon configuration
+typedef struct {
+  OSC_MODE  OscMode;          ///<OSC mode
+  UINT8     PortDevMap[6];    ///< Device number that has beed allocated already
+} TN_PCIe_SILICON_CONFIG;
+
+
+/// Complex Configuration
+typedef struct {
+  PCIe_SILICON_CONFIG     Silicon;                ///< Silicon
+  PCIe_WRAPPER_CONFIG     GfxWrapper;             ///< Graphics Wrapper
+  PCIe_WRAPPER_CONFIG     GppWrapper;             ///< General Purpose Port
+  PCIe_WRAPPER_CONFIG     DdiWrapper;             ///< DDI
+  PCIe_WRAPPER_CONFIG     Ddi2Wrapper;            ///< DDI
+  PCIe_ENGINE_CONFIG      Port2;                  ///< Port 2
+  PCIe_ENGINE_CONFIG      Port3;                  ///< Port 3
+  PCIe_ENGINE_CONFIG      DpB;                    ///< DPB
+  PCIe_ENGINE_CONFIG      DpC;                    ///< DPC
+  PCIe_ENGINE_CONFIG      DpD;                    ///< DPD
+  PCIe_ENGINE_CONFIG      Port4;                  ///< Port 4
+  PCIe_ENGINE_CONFIG      Port5;                  ///< Port 5
+  PCIe_ENGINE_CONFIG      Port6;                  ///< Port 6
+  PCIe_ENGINE_CONFIG      Port7;                  ///< Port 7
+  PCIe_ENGINE_CONFIG      Port8;                  ///< Port 8
+  PCIe_ENGINE_CONFIG      DpE;                    ///< DPE
+  PCIe_ENGINE_CONFIG      DpF;                    ///< DPF
+  PCIe_ENGINE_CONFIG      DpA;                    ///< DPA
+  TN_PCIe_SILICON_CONFIG  FmSilicon;               ///< Fm Silicon
+} TN_COMPLEX_CONFIG;
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
new file mode 100644
index 0000000000..8d687d910a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
@@ -0,0 +1,1002 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe wrapper configuration services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern TN_COMPLEX_CONFIG      ComplexDataTN;
+extern PCIe_PORT_DESCRIPTOR   DefaultSbPort;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+PcieConfigureEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureGppEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdi2EnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+PcieGetCoreConfigurationValueTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  );
+
+BOOLEAN
+PcieCheckPortPciDeviceMappingTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  );
+
+CONST CHAR8*
+PcieDebugGetCoreConfigurationStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  );
+
+CONST CHAR8*
+PcieDebugGetWrapperNameStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  );
+
+CONST CHAR8*
+PcieDebugGetHostRegAddressSpaceStringTN (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  );
+
+BOOLEAN
+PcieCheckPortPcieLaneCanBeMuxedTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  );
+
+AGESA_STATUS
+PcieMapPortPciAddressTN (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  );
+
+AGESA_STATUS
+PcieGetComplexDataLengthTN (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieBuildComplexConfigurationTN (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+UINT32
+PcieGetNativePhyLaneBitmapTN (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+AGESA_STATUS
+PcieGetSbConfigInfoTN (
+  IN       UINT8                         SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR          *SbPort,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   No more configuration available for given engine type
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+AGESA_STATUS
+PcieConfigureEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_ERROR;
+  switch (Wrapper->WrapId) {
+  case GFX_WRAP_ID:
+    Status = PcieConfigureGfxEnginesLaneAllocationTN (Wrapper, EngineType, ConfigurationId);
+    break;
+  case GPP_WRAP_ID:
+    if (EngineType != PciePortEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureGppEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case DDI_WRAP_ID:
+    if (EngineType != PcieDdiEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case DDI2_WRAP_ID:
+    if (EngineType != PcieDdiEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureDdi2EnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return Status;
+}
+
+CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = {
+{0,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+{0,   7, 8,              15}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxPortEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  UINTN               CoreLaneIndex;
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  CoreLaneIndex = 0;
+  while (EnginesList != NULL) {
+    if (PcieLibIsPcieEngine (EnginesList)) {
+      PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+      EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+      EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    }
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = {
+  {0,   7, 8,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+  {4,   7, 8,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+  {0,   7, 8,  11, 12,             15},
+  {4,   7, 8,  11, 12,             15}
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  UINTN               LaneIndex;
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  while (EnginesList != NULL) {
+    if (PcieLibIsDdiEngine (EnginesList)) {
+      PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+      EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+      EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    }
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   Configuration not applicable
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS  Status;
+
+  switch (EngineType) {
+  case PciePortEngine:
+    Status = PcieConfigureGfxPortEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case PcieDdiEngine:
+    Status = PcieConfigureGfxDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  default:
+    Status = AGESA_UNSUPPORTED;
+  }
+  return Status;
+}
+
+
+
+CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
+//4     5                                6                               7                                8 (SB)
+  {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID,  UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, 6,              7,               UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID,  6,              7,              UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, 6,              6,               7,              7,              UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID,  6,              6,              7,              7,               0, 3},
+  {4, 4, 5,              5,               6,              6,              7,              7,               0, 3}
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureGppEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               CoreLaneIndex;
+  UINTN               PortIdIndex;
+  if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  CoreLaneIndex = 0;
+  PortIdIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
+  {0,  3,   4,              7},
+  {0,  7,   UNUSED_LANE_ID, UNUSED_LANE_ID}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure DDI engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               LaneIndex;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+CONST UINT8 Ddi2LaneConfigurationTable [][NUMBER_OF_DDIS2 * 2] = {
+  {0,  6},
+  {0,  3}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure DDI engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdi2EnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               LaneIndex;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  if (ConfigurationId > ((sizeof (Ddi2LaneConfigurationTable) / (NUMBER_OF_DDIS2 * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->EngineData.StartLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList->EngineData.EndLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get configuration Value for GFX wrapper
+ *
+ *
+ *
+ * @param[in]   ConfigurationSignature  Configuration signature
+ * @param[out]  ConfigurationValue      Configuration value
+ * @retval     AGESA_SUCCESS            Correct core configuration value returned by in *ConfigurationValue
+ * @retval     AGESA_ERROR              ConfigurationSignature is incorrect.
+ */
+STATIC AGESA_STATUS
+PcieGetGfxConfigurationValueTN (
+  IN       UINT64    ConfigurationSignature,
+     OUT   UINT8     *ConfigurationValue
+  )
+{
+  switch (ConfigurationSignature) {
+  case GFX_CORE_x16:
+    *ConfigurationValue = 0;
+    break;
+  case GFX_CORE_x8x8:
+    *ConfigurationValue = 0x5;
+    break;
+  default:
+    ASSERT (FALSE);
+    return  AGESA_ERROR;
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get configuration Value for GPP wrapper
+ *
+ *
+ *
+ * @param[in]   ConfigurationSignature  Configuration signature
+ * @param[out]  ConfigurationValue      Configuration value
+ * @retval      AGESA_SUCCESS           Correct core configuration value returned by in *ConfigurationValue
+ * @retval      AGESA_ERROR             ConfigurationSignature is incorrect
+ */
+STATIC AGESA_STATUS
+PcieGetGppConfigurationValueTN (
+  IN       UINT64    ConfigurationSignature,
+     OUT   UINT8     *ConfigurationValue
+  )
+{
+  switch (ConfigurationSignature) {
+  case GPP_CORE_x4x1x1x1x1:
+    *ConfigurationValue = 0x4;
+    break;
+  case GPP_CORE_x4x2x1x1:
+    *ConfigurationValue = 0x3;
+    break;
+  case GPP_CORE_x4x2x2:
+    *ConfigurationValue = 0x2;
+    break;
+  case GPP_CORE_x4x4:
+    *ConfigurationValue = 0x1;
+    break;
+  default:
+    ASSERT (FALSE);
+    return  AGESA_ERROR;
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration value
+ *
+ *
+ *
+ * @param[in]  Wrapper                Pointer to internal configuration data area
+ * @param[in]  CoreId                 Core ID
+ * @param[in]  ConfigurationSignature Configuration signature
+ * @param[out] ConfigurationValue     Configuration value (for core configuration)
+ * @retval     AGESA_SUCCESS          Configuration successfully applied
+ * @retval     AGESA_ERROR            Core configuration value can not be determined
+ */
+AGESA_STATUS
+PcieGetCoreConfigurationValueTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  )
+{
+  AGESA_STATUS  Status;
+
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+    Status = PcieGetGfxConfigurationValueTN (ConfigurationSignature, ConfigurationValue);
+  } else if (Wrapper->WrapId == GPP_WRAP_ID) {
+    Status = PcieGetGppConfigurationValueTN (ConfigurationSignature, ConfigurationValue);
+  } else {
+    Status = AGESA_ERROR;
+  }
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if engine can be remapped to Device/function number requested by user
+ * defined engine descriptor
+ *
+ *   Function only called if requested device/function does not much native device/function
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckPortPciDeviceMappingTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  BOOLEAN   Result;
+  if (PortDescriptor->Port.DeviceNumber >= 2 && PortDescriptor->Port.DeviceNumber <= 7 && PortDescriptor->Port.FunctionNumber == 0 && !PcieConfigIsSbPcieEngine (Engine)) {
+    Result = TRUE;
+  } else {
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration string
+ *
+ *   Debug function for logging configuration
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @param[in] ConfigurationValue   Configuration value
+ * @retval                         Configuration string
+ */
+
+CONST CHAR8*
+PcieDebugGetCoreConfigurationStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  )
+{
+  switch (ConfigurationValue) {
+  case 0:
+    return "1x16";
+  case 5:
+    return "2x8";
+  case 4:
+    return "1x4, 4x1";
+  case 3:
+    return "1x4, 1x2, 2x1";
+  case 2:
+    return "1x4, 2x2";
+  case 1:
+    return "1x4, 1x4";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get wrapper name
+ *
+ *  Debug function for logging wrapper name
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @retval                         Wrapper Name string
+ */
+
+CONST CHAR8*
+PcieDebugGetWrapperNameStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  )
+{
+  switch (Wrapper->WrapId) {
+  case  GPP_WRAP_ID:
+    return "GPPSB";
+  case  GFX_WRAP_ID:
+    return "GFX";
+  case  DDI_WRAP_ID:
+    return "DDI";
+  case  DDI2_WRAP_ID:
+    return "DDI2";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get register address name
+ *
+ *  Debug function for logging register trace
+ *
+ * @param[in] Silicon              Silicon config descriptor
+ * @param[in] AddressFrame         Address Frame
+ * @retval                         Register address name
+ */
+CONST CHAR8*
+PcieDebugGetHostRegAddressSpaceStringTN (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  )
+{
+  switch (AddressFrame) {
+  case  0x130:
+    return "GPP  WRAP";
+  case  0x131:
+    return "GFX  WRAP";
+  case  0x132:
+    return "DDI  WRAP";
+  case  0x133:
+    return "DDI2 WRAP";
+  case  0x110:
+    return "GPP  PIF0";
+  case  0x111:
+    return "GFX  PIF0";
+  case  0x211:
+    return "GFX  PIF1";
+  case  0x112:
+    return "DDI  PIF0";
+  case  0x113:
+    return "DDI2 PIF0";
+  case  0x120:
+    return "GPP  PHY0";
+  case  0x121:
+    return "GFX  PHY0";
+  case  0x221:
+    return "GFX  PHY1";
+  case  0x122:
+    return "DDI  PHY0";
+  case  0x123:
+    return "DDI2 PHY0";
+  case  0x101:
+    return "GPP  CORE";
+  case  0x201:
+    return "GFX  CORE";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if the lane can be muxed by link width requested by user
+ * defined engine descriptor
+ *
+ *    Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
+ *    Check Engine StartCoreLane could be aligned by user requested link width x2.
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Lane can be muxed
+ * @retval     FALSE               Lane can NOT be muxed
+ */
+
+BOOLEAN
+PcieCheckPortPcieLaneCanBeMuxedTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  UINT16                DescriptorHiLane;
+  UINT16                DescriptorLoLane;
+  UINT16                DescriptorNumberOfLanes;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+  UINT16                NormalizedLoPhyLane;
+  BOOLEAN               Result;
+
+  Result  = FALSE;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+
+  NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane;
+
+  if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) {
+    Result = TRUE;
+  } else {
+    if (((PortDescriptor->Port.MiscControls.SbLink == 0x0) && ((Engine->Type.Port.StartCoreLane % 2) == 0)) || (Engine->Type.Port.StartCoreLane == 0)) {
+      if (NormalizedLoPhyLane == 0) {
+        Result = TRUE;
+      } else {
+        if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) {
+          Result = TRUE;
+        }
+      }
+    }
+  }
+  return Result;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Map engine to specific PCI device address
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @retval     AGESA_ERROR         Fail to map PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address
+ */
+
+AGESA_STATUS
+PcieMapPortPciAddressTN (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  TN_COMPLEX_CONFIG       *ComplexConfig;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  UINT8                   PortDevMap[6];
+  UINT8                   FreeDevMap[6];
+  UINT8                   PortIndex;
+  UINT8                   EnginePortIndex;
+  UINT8                   FreeIndex;
+  D0F0x64_x20_STRUCT      D0F0x64_x20;
+  D0F0x64_x21_STRUCT      D0F0x64_x21;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Enter\n");
+  if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
+    Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
+    Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
+  }
+  if (!PcieConfigIsSbPcieEngine (Engine)) {
+    ComplexConfig = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
+    Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+    LibAmdMemFill (&FreeDevMap[0], 0x0, sizeof (FreeDevMap), GnbLibGetHeader (Pcie));
+    LibAmdMemCopy (&PortDevMap[0], &ComplexConfig->FmSilicon.PortDevMap, sizeof (PortDevMap), GnbLibGetHeader (Pcie));
+    for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
+      if (PortDevMap[PortIndex] != 0) {
+        FreeDevMap[PortDevMap[PortIndex] - 2] = 1;
+      }
+    }
+    EnginePortIndex = Engine->Type.Port.PortData.DeviceNumber - 2;
+    if (FreeDevMap[EnginePortIndex] == 0) {
+      // Dev number not yet allocated
+      ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
+      FreeDevMap[EnginePortIndex] = 1;
+      PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
+      for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
+        if (PortDevMap[PortIndex] == 0) {
+          for (FreeIndex = 0; FreeIndex < sizeof (FreeDevMap); FreeIndex++) {
+            if (FreeDevMap[FreeIndex] == 0) {
+              FreeDevMap[FreeIndex] = 1;
+              break;
+            }
+          }
+          PortDevMap[PortIndex] = FreeIndex + 2;
+        }
+      }
+
+      GnbRegisterReadTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x20.Field.ProgDevMapEn = 0;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      GnbRegisterReadTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x21.Field.GfxPortADevmap = PortDevMap[2 - 2];
+      D0F0x64_x21.Field.GfxPortBDevmap = PortDevMap[3 - 2];
+      D0F0x64_x20.Field.GppPortBDevmap = PortDevMap[4 - 2];
+      D0F0x64_x20.Field.GppPortCDevmap = PortDevMap[5 - 2];
+      D0F0x64_x20.Field.GppPortDDevmap = PortDevMap[6 - 2];
+      D0F0x64_x20.Field.GppPortEDevmap = PortDevMap[7 - 2];
+      D0F0x64_x20.Field.ProgDevMapEn = 0x1;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      GnbRegisterWriteTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x20.Field.ProgDevMapEn = 1;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Fail device %d to port %d\n", Engine->Type.Port.PortData.DeviceNumber, Engine->Type.Port.NativeDevNumber);
+      Status = AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get total number of silicons/wrappers/engines for this complex
+ *
+ *
+ *
+ * @param[in]  SocketId              Socket ID.
+ * @param[out] Length                Length of configuration info block
+ * @param[out] StdHeader             Standard configuration header
+ * @retval     AGESA_SUCCESS         Configuration data length is correct
+ */
+AGESA_STATUS
+PcieGetComplexDataLengthTN (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  *Length = sizeof (TN_COMPLEX_CONFIG);
+  return  AGESA_SUCCESS;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build configuration
+ *
+ *
+ *
+ * @param[in]  SocketId         Socket ID.
+ * @param[out] Buffer           Pointer to buffer to build internal complex data structure
+ * @param[out] StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieBuildComplexConfigurationTN (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  LibAmdMemCopy (Buffer, &ComplexDataTN, sizeof (TN_COMPLEX_CONFIG), StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  get native PHY lane bitmap
+ *
+ *
+ * @param[in]  PhyLaneBitmap  Package PHY lane bitmap
+ * @param[in]  Engine         Standard configuration header.
+ * @retval     Native PHY lane bitmap
+ */
+UINT32
+PcieGetNativePhyLaneBitmapTN (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  )
+{
+  return PhyLaneBitmap;
+}
+
+STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = {
+  0,
+  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0)
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build default SB configuration descriptor
+ *
+ *
+ * @param[in]  SocketId         Socket Id
+ * @param[out] SbPort           Pointer to SB configuration descriptor
+ * @param[in]  StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieGetSbConfigInfoTN (
+  IN       UINT8                         SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR          *SbPort,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader);
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
new file mode 100644
index 0000000000..642f41ff89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
@@ -0,0 +1,810 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64781 $   @e \$Date: 2012-01-30 21:19:50 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbNbInitLibV4.h"
+#include  "PcieLibTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuFamRegisters.h"
+#include  "F15TnPackageType.h"
+#include  "GeneralServices.h"
+#include  "Filecode.h"
+
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN;
+extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN;
+extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY lane parameter Init
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PciePhyLaneInitInitCallbackTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      VOID                  *Buffer,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   Phy;
+  UINT8   PhyLaneIndex;
+  UINT8   Lane;
+  UINT32  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper);
+  for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) {
+    if ((LaneBitmap & (1 << Lane)) != 0) {
+      Phy = Lane / MAX_NUM_LANE_PER_PHY;
+      PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY;
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80),
+        D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK,
+        (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET),
+        FALSE,
+        Pcie
+        );
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80),
+        D0F0xE4_PHY_4002_LfcMax_MASK,
+        (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET),
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Satic init for various registers.
+ *
+ *
+ *
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+STATIC
+PcieEarlyStaticInitTN (
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINTN Index;
+
+  for (Index = 0; Index < PcieInitEarlyTableTN.Length; Index++) {
+    GnbLibPciIndirectRMW (
+      MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS),
+      PcieInitEarlyTableTN.Table[Index].Reg,
+      AccessWidth32,
+      (UINT32)~PcieInitEarlyTableTN.Table[Index].Mask,
+      PcieInitEarlyTableTN.Table[Index].Data,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init core registers.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+STATIC
+PcieEarlyCoreInitTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINT8   CoreId;
+  UINTN   Index;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n");
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      for (Index = 0; Index < CoreInitTableTN.Length; Index++) {
+        UINT32 Value;
+        Value = PcieRegisterRead (
+                  Wrapper,
+                  CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
+                  Pcie
+                  );
+        Value &= (~CoreInitTableTN.Table[Index].Mask);
+        Value |= CoreInitTableTN.Table[Index].Data;
+        PcieRegisterWrite (
+          Wrapper,
+          CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
+          Value,
+          FALSE,
+          Pcie
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Dll Cap based on fuses
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper configuration data area
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+STATIC VOID
+PcieSetDllCapTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D18F3x1FC_STRUCT           D18F3x1FC;
+  D0F0xE4_PHY_500F_STRUCT    D0F0xE4_PHY_500F;
+  D0F0xE4_PHY_4010_STRUCT    D0F0xE4_PHY_4010;
+  D0F0xE4_PHY_4011_STRUCT    D0F0xE4_PHY_4011;
+  UINT32                     Gen1Index;
+  UINT32                     Gen2Index;
+  CPU_LOGICAL_ID             LogicalId;
+  GNB_HANDLE                 *GnbHandle;
+
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n");
+
+  D0F0xE4_PHY_500F.Value = 0;
+  GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie));
+
+  //Read SWDllCapTableEn
+  GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie));
+  IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value);
+
+  if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull  )) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n");
+    // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0])
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS));
+    D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value);
+    // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0])
+    IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS));
+    D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value);
+
+    // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0
+    // Else...
+    // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical
+    // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast
+    // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow
+    IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl);
+    if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp);
+      Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1;
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case...");
+      switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) {
+      case 0:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n");
+        Gen1Index = 0xd;
+        break;
+      case 1:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n");
+        Gen1Index = 0xf;
+        break;
+      case 2:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n");
+        Gen1Index = 0xa;
+        break;
+      default:
+        IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n");
+        Gen1Index = 0xd; //Use typical for default case
+        break;
+      }
+    }
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index);
+    // Bits  3:0 = Gen1Index[3:0]
+    // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0]
+    if (D18F3x1FC.Field.SWDllCapTableEn != 0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50);
+      Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50;
+    } else {
+      Gen2Index = 0x03; // Hard coded default
+    }
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index);
+    PcieRegisterWrite (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
+      D0F0xE4_PHY_500F.Value,
+      FALSE,
+      Pcie
+      );
+    // Set DllProcessFreqCtlOverride on second write
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
+    PcieRegisterWrite (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
+      D0F0xE4_PHY_500F.Value,
+      FALSE,
+      Pcie
+      );
+    if (Wrapper->WrapId == 1) {
+      // For Wrapper 1, configure PHY0 and PHY1
+      D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0;
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
+        D0F0xE4_PHY_500F.Value,
+        FALSE,
+        Pcie
+        );
+      // Set DllProcessFreqCtlOverride on second write
+      D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
+        D0F0xE4_PHY_500F.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * TN FP2 PCIE allocation x8 check
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+
+STATIC AGESA_STATUS
+PcieFP2x8CheckCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINT32                    LaneBitmap;
+  AGESA_STATUS              Status;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n");
+
+  Status = AGESA_SUCCESS;
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap);
+
+    if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n");
+      Status = AGESA_ERROR;
+      PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_LANES_CONFIGURATION,
+        (LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane),
+        (LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane),
+        0,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+
+      ASSERT (FALSE);
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * TN FP2 PCIE critera check
+ *
+ *
+ *
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+STATIC AGESA_STATUS
+PcieFP2CriteriaTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS              Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Enter\n");
+
+  // PACKAGE_TYPE_FP2    1
+  // PACKAGE_TYPE_FS1r2  2
+  // PACKAGE_TYPE_FM2    4
+  if (LibAmdGetPackageType (GnbLibGetHeader (Pcie)) != PACKAGE_TYPE_FP2) {
+    return AGESA_SUCCESS;
+  }
+  // FP2 force gen1
+  Pcie->PsppPolicy = PsppPowerSaving;
+  // FP2 only use x8 on the same PHY
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieFP2x8CheckCallbackTN, NULL, Pcie);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Exit\n");
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RX offset cancellation enablement
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper configuration data area
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+STATIC VOID
+PcieOffsetCancelCalibration (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32                LaneBitmap;
+  D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C;
+
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
+  if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) {
+    return;
+  }
+
+  if (LaneBitmap != 0) {
+    D0F0xBC_x1F39C.Value = 0;
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane;
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Wrapper)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Wrapper)->Address,
+      SMC_MSG_PHY_LN_ON,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PcieInitSrbmCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+  PcieOffsetCancelCalibration (Wrapper, Pcie);
+  PciePifApplyGanging (Wrapper, Pcie);
+  PciePhyApplyGanging (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY Pll Personality Init Callback
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PciePhyLetPllPersonalityInitCallbackTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      VOID                  *Buffer,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n");
+  PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie);
+  PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieSetPhyPersonalityTN (Wrapper, Pcie);
+  PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Init prior training.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+AGESA_STATUS
+STATIC
+PcieEarlyInitCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  BOOLEAN       CoreConfigChanged;
+  BOOLEAN       PllConfigChanged;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n");
+  CoreConfigChanged = FALSE;
+  PllConfigChanged = FALSE;
+  PcieTopologyPrepareForReconfig (Wrapper, Pcie);
+  Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  PcieTopologyApplyLaneMux (Wrapper, Pcie);
+  PciePifSetRxDetectPowerMode (Wrapper, Pcie);
+  PciePifSetLs2ExitTime (Wrapper, Pcie);
+  PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie);
+  if (CoreConfigChanged || PllConfigChanged) {
+    PcieTopologyExecuteReconfigV4 (Wrapper, Pcie);
+  }
+  PcieTopologyCleanUpReconfig (Wrapper, Pcie);
+  PcieTopologySetLinkReversalV4 (Wrapper, Pcie);
+
+  if (Wrapper->Features.PowerOffUnusedPlls != 0) {
+    PciePifPllPowerDown (
+      PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper),
+      Wrapper,
+      Pcie
+      );
+    PciePifPllInitForDdi (Wrapper, Pcie);
+    PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie);
+  }
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieSetDdiOwnPhyV4 (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePhyAvertClockPickers (Wrapper, Pcie);
+  PcieEarlyCoreInitTN (Wrapper, Pcie);
+  PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie);
+  if (PcieConfigIsPcieWrapper (Wrapper)) {
+    PcieSetDllCapTN (Wrapper, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Init
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PcieEarlyInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS        Status;
+  AGESA_STATUS        AgesaStatus;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieFP2CriteriaTN (Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieEarlyStaticInitTN (Pcie);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieOscInitTN (Pcie);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieSetVoltageTN (PcieGen1, Pcie);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieEarlyPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n");
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie);
+  PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
+  PcieSetLinkWidthCap (Engine, Pcie);
+  PcieCompletionTimeout (Engine, Pcie);
+  PcieLinkSetSlotCap (Engine, Pcie);
+  PcieLinkInitHotplug (Engine, Pcie);
+  //PciePhyChannelCharacteristic (Engine, Pcie);
+  if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
+      (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
+       Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
+       Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
+    ASSERT (!PcieConfigIsSbPcieEngine (Engine));
+    //
+    //  Pass endpoint tstaus in scratch
+    //
+    PciePortRegisterRMW (
+      Engine,
+      DxF0xE4_x01_ADDRESS,
+      0x1,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
+  }
+  if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PcieEarlyPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
+  if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+    Pcie->TrainingExitState = LinkStateResetExit;
+  }
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieEarlyPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Enter\n");
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PcieEarlyInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieEarlyPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
new file mode 100644
index 0000000000..f0cf287a7f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Env Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PcieEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreTNS3Script_ID, 0, NULL);
+  return  AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
new file mode 100644
index 0000000000..3d00bdb6e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
@@ -0,0 +1,639 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * TN specific PCIe configuration data services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbSbLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbNbInitLibV1.h"
+#include  "PcieComplexDataTN.h"
+#include  "PcieLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+PCIE_LINK_SPEED_CAP
+PcieGetLinkSpeedCapTN (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Control port visibility in PCI config space
+ *
+ *
+ * @param[in]  Control         Make port Hide/Unhide ports
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PciePortsVisibilityControlTN (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG *Silicon;
+  Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  ASSERT (Silicon != NULL);
+  switch (Control) {
+  case UnhidePorts:
+    PcieSiliconUnHidePorts (Silicon, Pcie);
+    break;
+  case HidePorts:
+    PcieSiliconHidePorts (Silicon, Pcie);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down inactive lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePowerDownPllInL1TN (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+
+  UINT32              LaneBitmapForPllOffInL1;
+  UINT32              ActiveLaneBitmap;
+  UINT8               PllPowerUpLatency;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Enter\n");
+  ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper);
+  if (ActiveLaneBitmap != 0) {
+    PllPowerUpLatency = PciePifGetPllPowerUpLatencyTN (Wrapper, Pcie);
+    LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie);
+    if ((LaneBitmapForPllOffInL1 != 0) && ((ActiveLaneBitmap & LaneBitmapForPllOffInL1) == ActiveLaneBitmap)) {
+      LaneBitmapForPllOffInL1 &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper);
+      LaneBitmapForPllOffInL1 |= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, 0, Wrapper);
+      PciePifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Exit\n");
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request boot up voltage
+ *
+ *
+ *
+ * @param[in]  LinkCap             Global GEN capability
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+VOID
+PcieSetVoltageTN (
+  IN      PCIE_LINK_SPEED_CAP   LinkCap,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                      TargetVid;
+  D0F0xBC_xE010705C_STRUCT   D0F0xBC_xE010705C;
+  GMMx63C_STRUCT             GMMx63C;
+  GMMx640_STRUCT             GMMx640;
+  UINT8                      MinVidIndex;
+  D0F0xBC_xE0001008_STRUCT   D0F0xBC_xE0001008;
+  UINT8                      SclkVid[4];
+  UINT8                      Index;
+  PP_FUSE_ARRAY              *PpFuseArray;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Enter\n");
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie));
+  if (PpFuseArray == NULL) {
+    GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, GnbLibGetHeader (Pcie));
+    SclkVid[0] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid0;
+    SclkVid[1] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid1;
+    SclkVid[2] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid2;
+    SclkVid[3] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid3;
+    GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010705C_ADDRESS, &D0F0xBC_xE010705C, 0, GnbLibGetHeader (Pcie));
+    Index = (UINT8) D0F0xBC_xE010705C.Field.PcieGen2Vid;
+  } else {
+    SclkVid[0] = PpFuseArray->SclkVid[0];
+    SclkVid[1] = PpFuseArray->SclkVid[1];
+    SclkVid[2] = PpFuseArray->SclkVid[2];
+    SclkVid[3] = PpFuseArray->SclkVid[3];
+    Index = PpFuseArray->PcieGen2Vid;
+  }
+  if (LinkCap > PcieGen1) {
+    ASSERT (SclkVid[Index] != 0);
+    TargetVid = SclkVid[Index];
+  } else {
+
+    MinVidIndex = 0;
+    for (Index = 0; Index < 4; Index++) {
+      if (SclkVid[Index] > SclkVid[MinVidIndex]) {
+        MinVidIndex = (UINT8) Index;
+      }
+    }
+    ASSERT (SclkVid[MinVidIndex] != 0);
+    TargetVid = SclkVid[MinVidIndex];
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid);
+
+  GnbRegisterReadTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, 0, GnbLibGetHeader (Pcie));
+  //Wait for voltage change to complete before it can issue next voltage change request
+  do {
+    GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie));
+  } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq);
+  //Enable voltage client
+  if (LinkCap == PcieGen1) {
+    GMMx63C.Field.VoltageChangeEn = 0;
+  } else {
+    GMMx63C.Field.VoltageChangeEn = 1;
+  }
+  GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  //Program level and toggle request
+  GMMx63C.Field.VoltageLevel = TargetVid;
+  GMMx63C.Field.VoltageChangeReq = !GMMx63C.Field.VoltageChangeReq;
+  GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  //Wait for voltage change to complete before it can issue next voltage change request
+  do {
+    GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie));
+  } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL power up latency
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ * @retval                 Pll wake up latency in us
+ */
+UINT8
+PciePifGetPllPowerUpLatencyTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  return 35;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max link speed capability supported by this port
+ *
+ *
+ *
+ * @param[in]  Flags              See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
+ * @param[in]  Engine             Pointer to engine config descriptor
+ * @retval     PcieGen1/PcieGen2  Max supported link gen capability
+ */
+PCIE_LINK_SPEED_CAP
+PcieGetLinkSpeedCapTN (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  PCIE_LINK_SPEED_CAP   LinkSpeedCapability;
+  TN_COMPLEX_CONFIG     *ComplexData;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+
+  ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+  LinkSpeedCapability = PcieGen2;
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
+  if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) {
+    LinkSpeedCapability = PcieGen2;
+  } else {
+    LinkSpeedCapability = PcieGen1;
+  }
+  if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) {
+    Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability;
+  }
+  if (Pcie->PsppPolicy == PsppPowerSaving) {
+    LinkSpeedCapability = PcieGen1;
+  }
+  if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) {
+    LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
+  }
+  if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
+    if ((Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) {
+      LinkSpeedCapability = PcieGen1;
+    }
+  }
+  return LinkSpeedCapability;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PLL personality
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieSetPhyPersonalityTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Phy;
+  UINT8                   Mode;
+  if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID || Wrapper->WrapId == DDI2_WRAP_ID) {
+    for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+      if (Wrapper->WrapId == GFX_WRAP_ID) {
+        Mode = (Phy == 0)? 0x1 : 0;
+      } else {
+        Mode = 0x2;
+      }
+      PcieRegisterWriteField (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS),
+        D0F0xE4_PHY_2005_PllMode_OFFSET,
+        D0F0xE4_PHY_2005_PllMode_WIDTH,
+        Mode,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DCC recalibration
+ *
+ *
+ *
+ * @param[in]     Wrapper           Pointer to internal configuration data area
+ * @param[in,out] Buffer            Pointer to buffer
+ * @param[in]     Pcie              Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieForceDccRecalibrationCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePhyForceDccRecalibration (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare for Osc switch
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscPifInitPrePowerdownCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PciePifSetPllRampTime (LongRampup, Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Do Osc switch
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscInitPllModeCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  TN_COMPLEX_CONFIG         *ComplexData;
+  TN_PCIe_SILICON_CONFIG    *FmSilicon;
+  UINT8                     Phy;
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Wrapper);
+  ASSERT (ComplexData != NULL);
+  FmSilicon = &ComplexData->FmSilicon;
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+    Phy = 1;
+  } else if (Wrapper->WrapId == GPP_WRAP_ID) {
+    Phy = 0;
+  } else {
+    ASSERT (FALSE);
+    return AGESA_ERROR;
+  }
+  switch (FmSilicon->OscMode) {
+  case  OscLC:
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_IsLc_OFFSET,
+      D0F0xE4_PHY_2002_IsLc_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    break;
+  case  OscRO:
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_RoCalEn_OFFSET,
+      D0F0xE4_PHY_2002_RoCalEn_WIDTH,
+      0x0,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_RoCalEn_OFFSET,
+      D0F0xE4_PHY_2002_RoCalEn_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post Osc init
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscPifInitPostPowerdownCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
+  PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare PHY for Gen2
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieOscInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  TN_COMPLEX_CONFIG         *ComplexData;
+  TN_PCIe_SILICON_CONFIG    *FmSilicon;
+  D0F0xE4_WRAP_FFF1_STRUCT  D0F0xE4_WRAP_FFF1;
+  AGESA_STATUS              Status;
+  UINT8                     SaveSbLinkAspm;
+  UINT32                    Value;
+
+  Value = 0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Enter\n");
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  ASSERT (ComplexData != NULL);
+  FmSilicon = &ComplexData->FmSilicon;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "  OSC Mode - %s\n",
+    (FmSilicon->OscMode == OscFuses) ? "Fuses" : (
+    (FmSilicon->OscMode == OscRO) ? "RO" : (
+    (FmSilicon->OscMode == OscLC) ? "LC" : (
+    (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown")))
+    );
+
+  if (FmSilicon->OscMode == OscFuses) {
+    D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead (
+                                &ComplexData->GppWrapper,
+                                WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS),
+                                Pcie
+                                );
+
+    if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) {
+      FmSilicon->OscMode = OscRO;
+    } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) {
+      FmSilicon->OscMode = OscLC;
+    } else {
+      FmSilicon->OscMode = OscDefault;
+    }
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "  OSC Mode From Fuses - %s\n",
+      (FmSilicon->OscMode == OscFuses) ? "Fuses" : (
+      (FmSilicon->OscMode == OscRO) ? "RO" : (
+      (FmSilicon->OscMode == OscLC) ? "LC" : (
+      (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown")))
+      );
+  }
+  if (FmSilicon->OscMode != OscDefault) {
+
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscPifInitPrePowerdownCallback,
+      NULL,
+      Pcie
+      );
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscInitPllModeCallback,
+      NULL,
+      Pcie
+      );
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieForceDccRecalibrationCallbackTN,
+      NULL,
+      Pcie
+      );
+
+    SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm;
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1;
+
+    Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie);
+    ASSERT (Status == AGESA_SUCCESS);
+#ifdef  USE_L1_POLLING
+    //Use L1 Entry pooling
+    PciePollLinkForL1Entry (&ComplexData->Port8, Pcie);
+#else
+    {
+      D0F0xBC_x1F630_STRUCT  D0F0xBC_x1F630;
+
+      GnbRegisterReadTN (D0F0xBC_x1F630_TYPE,  D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie));
+      D0F0xBC_x1F630.Field.RECONF_WAIT = 60;
+      GnbRegisterWriteTN (D0F0xBC_x1F630_TYPE,  D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie));
+
+      GnbSmuServiceRequestV4 (
+        ComplexData->Silicon.Address,
+        SMC_MSG_PCIE_PLLSWITCH,
+        0,
+        GnbLibGetHeader (Pcie)
+      );
+    }
+#endif
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled;
+
+    SbPcieLinkAspmControl (&ComplexData->Port8, Pcie);
+    PciePollLinkForL0Exit (&ComplexData->Port8, Pcie);
+
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm;
+
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscPifInitPostPowerdownCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Exit\n");
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h
new file mode 100644
index 0000000000..1f65ce2ecf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * TN specific PCIe configuration data services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIELIBTN_H_
+#define _PCIELIBTN_H_
+
+VOID
+PciePortsVisibilityControlTN (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PciePowerDownPllInL1TN (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieSetVoltageTN (
+  IN      PCIE_LINK_SPEED_CAP   LinkCap,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT8
+PciePifGetPllPowerUpLatencyTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetPhyPersonalityTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieOscInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
new file mode 100644
index 0000000000..2a751be1b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
@@ -0,0 +1,283 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbFamServices.h"
+#include  "PcieLibTN.h"
+#include  "PciePowerGateTN.h"
+#include  "PciePortServicesV4.h"
+#include  "PcieMaxPayloadV4.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieMidPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie);
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    PcieEnableSlotPowerLimit (Engine, Pcie);
+    if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
+      PcieInitPortForIommuV4 (Engine, Pcie);
+    }
+  }
+  PcieEnableAspm (Engine,  Pcie);
+  if (GnbBuildOptions.CfgMaxPayloadEnable) {
+    PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PcieMidPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS         Status;
+  PCIE_LINK_SPEED_CAP  GlobalSpeedCap;
+
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieMidPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+
+  GlobalSpeedCap = PcieUtilGlobalGenCapability (
+                     PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
+                     Pcie
+                     );
+
+
+  PcieSetVoltageTN (GlobalSpeedCap, Pcie);
+
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Late Init.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+AGESA_STATUS
+STATIC
+PcieMidInitCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  PciePwrPowerDownUnusedLanes (Wrapper, Pcie);
+  PciePowerDownPllInL1TN (Wrapper, Pcie);
+  PciePwrClockGatingV4 (Wrapper, Pcie);
+  PcieLockRegisters (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Late Init
+ *
+ *   Late PCIe initialization
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PcieMidInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = PciePowerGateTN (Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PcieMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PcieMidPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieMidInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
new file mode 100644
index 0000000000..b30e92b437
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
@@ -0,0 +1,498 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63818 $   @e \$Date: 2012-01-09 03:02:03 -0600 (Mon, 09 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "PcieLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PciePostEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PciePostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PciePostS3InterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+VOID
+PcieLateRestoreInitTNS3Script (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  IN      UINT16                          ContextLength,
+  IN      VOID*                           Context
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePostPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP LinkSpeedCapability;
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+    PcieLinkSafeMode (Engine, Pcie);
+  }
+  LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
+  PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) {
+    PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie);
+    PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+  }
+  if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    PcieForceCompliance (Engine, Pcie);
+    PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePostS3PortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP       LinkSpeedCapability;
+  PCIE_LINK_TRAINING_STATE  State;
+
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+
+  LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
+  PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
+
+  if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+    PcieLinkSafeMode (Engine, Pcie);
+  }
+
+  if (!PcieConfigIsSbPcieEngine (Engine)) {
+    //
+    // General Port
+    //
+    State = LinkStateDeviceNotPresent;
+    if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) {
+      //
+      // Non hotplug device: we only check status from previous boot
+      //
+      if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        State = LinkStateResetExit;
+      }
+    } else {
+      UINT32  PcieScratch;
+      //
+      //  Get endpoint staus from scratch
+      //
+      PcieScratch = PciePortRegisterRead (Engine, DxF0xE4_x01_ADDRESS, Pcie);
+      //
+      // Hotplug device: we check ep status if reported
+      //
+      if ((PcieScratch & 0x1) == 0) {
+        State = LinkStateResetExit;
+      }
+    }
+    //
+    // For compialnce we always leave link in enabled state
+    //
+    if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) {
+      State = LinkStateResetExit;
+    }
+    PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+  } else {
+    //
+    // SB port
+    //
+    State = LinkStateTrainingSuccess;
+  }
+  PcieTrainingSetPortState (Engine, State, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostEarlyPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  // Distributed Training started at PciePortInit complete it now to get access to PCIe devices
+  if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+    Pcie->TrainingExitState = LinkStateTrainingCompleted;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PciePostPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostS3PortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PciePostS3PortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Init
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PciePostInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP  GlobalSpeedCap;
+
+  GlobalSpeedCap = PcieUtilGlobalGenCapability (
+                     PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
+                     Pcie
+                     );
+
+
+  PcieSetVoltageTN (GlobalSpeedCap, Pcie);
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostEarlyPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PciePostPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostS3InterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+      Status = PciePostS3PortInitTN (Pcie);
+    } else {
+      Status = PciePostPortInitTN (Pcie);
+    }
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe S3 restore
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        Context pointer (not used)
+ */
+VOID
+PcieLateRestoreInitTNS3Script (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  IN      UINT16                          ContextLength,
+  IN      VOID*                           Context
+  )
+{
+  PciePostS3InterfaceTN (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
new file mode 100644
index 0000000000..4197fd842c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
@@ -0,0 +1,383 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe power gate initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "OptionGnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Report used lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePowerGateReportActiveLanesCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  UINT32                  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Engine);
+  if (LaneBitmap != 0) {
+    D0F0xBC_x1F39C.Value = 0;
+    D0F0xBC_x1F39C.Field.Tx = 0;
+    D0F0xBC_x1F39C.Field.Rx = 0;
+    D0F0xBC_x1F39C.Field.Core = 0;
+    D0F0xBC_x1F39C.Field.SkipPhy = 1;
+    D0F0xBC_x1F39C.Field.SkipCore = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    if (PcieConfigIsPcieEngine (Engine) && PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine) == PcieGen2) {
+      D0F0xBC_x1F610_STRUCT  D0F0xBC_x1F610;
+      UINT32                 Gen2LaneBitmap;
+      Gen2LaneBitmap = ((1 << (D0F0xBC_x1F39C.Field.UpperLaneID - D0F0xBC_x1F39C.Field.LowerLaneID + 1)) - 1) << D0F0xBC_x1F39C.Field.LowerLaneID;
+      GnbRegisterReadTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, 0, GnbLibGetHeader (Pcie));
+      D0F0xBC_x1F610.Field.GFXH |= (Gen2LaneBitmap >> 16) & 0xFF;
+      D0F0xBC_x1F610.Field.GFXL |= (Gen2LaneBitmap >> 8) & 0xFF;
+      D0F0xBC_x1F610.Field.GPPSB |= (Gen2LaneBitmap  & 0xFF );
+      GnbRegisterWriteTN (D0F0xBC_x1F610_TYPE,  D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    }
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_ON,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Wrapper         Pointer to wrapper configuration
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ * @retval          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePowerGatePowerDownUnusedLanesCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Index;
+  UINTN                   State;
+  UINT32                  LaneBitmap;
+  UINT16                  StartLane;
+  UINT16                  EndLane;
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Enter\n");
+
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (
+                 LANE_TYPE_PHY_NATIVE_ALL,
+                 LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG,
+                 Wrapper
+                 );
+  IDS_HDT_CONSOLE (GNB_TRACE, " Lane Bitmap 0x%x\n", LaneBitmap);
+  if (LaneBitmap != 0) {
+    State = 0;
+    StartLane = 0;
+    EndLane = 0;
+    for (Index = 0; Index <= (LibAmdBitScanReverse (LaneBitmap) + 1); Index++) {
+      if ((State == 0) && ((LaneBitmap & (1 << Index)) != 0)) {
+        StartLane = Index;
+        State = 1;
+      } else if ((State == 1) && ((LaneBitmap & (1 << Index)) == 0)) {
+        EndLane = Index - 1;
+        State = 0;
+        GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+        D0F0xBC_x1F39C.Field.Tx = 1;
+        D0F0xBC_x1F39C.Field.Rx = 1;
+        D0F0xBC_x1F39C.Field.Core = 1;
+        D0F0xBC_x1F39C.Field.LowerLaneID = StartLane + Wrapper->StartPhyLane;
+        D0F0xBC_x1F39C.Field.UpperLaneID = EndLane + Wrapper->StartPhyLane;
+        IDS_HDT_CONSOLE (
+          PCIE_MISC,
+          "  LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+          D0F0xBC_x1F39C.Field.LowerLaneID,
+          D0F0xBC_x1F39C.Field.UpperLaneID,
+          D0F0xBC_x1F39C.Field.Tx,
+          D0F0xBC_x1F39C.Field.Rx,
+          D0F0xBC_x1F39C.Field.Core
+          );
+        GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+        GnbSmuServiceRequestV4 (
+          PcieConfigGetParentSilicon (Wrapper)->Address,
+          SMC_MSG_PHY_LN_OFF,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          GnbLibGetHeader (Pcie)
+          );
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePowerGatePowerDownLanesCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  UINT32                  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Engine);
+  if (LaneBitmap != 0) {
+    GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.Core = 0;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  PCIe Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Engine);
+  if (LaneBitmap != 0) {
+    GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.Core = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  DDI Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Power gate init
+ *
+ *   Late PCIe initialization
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ */
+
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   PowerGatingFlags;
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Enter\n");
+  PowerGatingFlags = GnbBuildOptions.CfgPciePowerGatingFlags;
+  // Report used lanes
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE,
+    PciePowerGateReportActiveLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+
+  IDS_OPTION_HOOK (IDS_GNB_PCIE_POWER_GATING, &PowerGatingFlags, GnbLibGetHeader (Pcie));
+
+  // Update flags
+  GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+  if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_CORE) == 0) {
+    D0F0xBC_x1F39C.Field.SkipCore = 0;
+  }
+  if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_PHY) == 0) {
+    D0F0xBC_x1F39C.Field.SkipPhy = 0;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  // Power down unused lanes
+  PcieConfigRunProcForAllWrappers (
+    DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER,
+    PciePowerGatePowerDownUnusedLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+  //Power down hotplug lanes
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE,
+    PciePowerGatePowerDownLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Exit\n");
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
new file mode 100644
index 0000000000..b8d2116a96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe power gate initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERGATETN_H_
+#define _PCIEPOWERGATETN_H_
+
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
new file mode 100644
index 0000000000..faa2fa8f80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
@@ -0,0 +1,258 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65061 $   @e \$Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "PcieComplexDataTN.h"
+#include  "GnbRegistersTN.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
+  {
+    WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS),
+    D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
+    0
+  },
+  {
+    PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  }
+ };
+
+CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN  = {
+  &PcieInitEarlyTable[0],
+  sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
+};
+
+STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
+  {
+    D0F0xE4_CORE_0020_ADDRESS,
+    D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
+    D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK,
+    (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0010_ADDRESS,
+    D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK,
+    (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_001C_ADDRESS,
+    D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
+    D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
+    D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
+    (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
+    (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
+    (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0040_ADDRESS,
+    D0F0xE4_CORE_0040_PElecIdleMode_MASK,
+    (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0002_ADDRESS,
+    D0F0xE4_CORE_0002_HwDebug_0__MASK,
+    (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET)
+  },
+  {
+    D0F0xE4_CORE_00C1_ADDRESS,
+    D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
+    D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
+    (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
+    (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_00B0_ADDRESS,
+    D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK,
+    (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
+  }
+};
+
+CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN  = {
+  &CoreInitTable[0],
+  sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
+};
+
+
+STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
+  {
+    DxF0xE4_x02_ADDRESS,
+    DxF0xE4_x02_RegsLcAllowTxL1Control_MASK,
+    (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET)
+  },
+  {
+    DxF0xE4_x70_ADDRESS,
+    DxF0xE4_x70_RxRcbCplTimeoutMode_MASK,
+    (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET)
+  },
+  {
+    DxF0xE4_xA0_ADDRESS,
+    DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK,
+    (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) |
+    (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) |
+    (0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET)
+  },
+  {
+    DxF0xE4_xA1_ADDRESS,
+    DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK,
+    (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET)
+  },
+  {
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK,
+    (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) |
+    (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET)
+  },
+  {
+    DxF0xE4_xA3_ADDRESS,
+    DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK,
+    (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET)
+  },
+  {
+    DxF0xE4_xB1_ADDRESS,
+    DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK,
+    (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) |
+    (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET)
+  }
+};
+
+CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN  = {
+  &PortInitEarlyTable[0],
+  sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
+};
+
+
+STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
+  {
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcDynLanesPwrState_MASK,
+    (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET)
+  },
+  {
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK,
+    (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET)
+  }
+};
+
+CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN  = {
+  &PortInitMidTable[0],
+  sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
new file mode 100644
index 0000000000..fb44d8328e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
@@ -0,0 +1,361 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbIvrsLib.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define IVRS_TABLE_LENGTH 8 * 1024
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+GnbBuildIvmdList (
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbIommuIvrsTableDump (
+  IN       VOID                 *Ivrs,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+AGESA_STATUS
+GnbIommuIvrsTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+IOMMU_IVRS_HEADER IvrsHeader = {
+  {'I', 'V', 'R', 'S'},
+  sizeof (IOMMU_IVRS_HEADER),
+  2,
+  0,
+  {'A', 'M', 'D', ' ', ' ', 0},
+  {'A', 'M', 'D', 'I', 'O', 'M', 'M', 'U'},
+  1,
+  {'A','M','D',' '},
+  0,
+  0,
+  0
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build IVRS table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        AGESA_SUCCESS
+ * @retval        AGESA_ERROR
+ */
+
+AGESA_STATUS
+GnbIommuIvrsTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AGESA_STATUS            Status;
+  AMD_LATE_PARAMS         *LateParamsPtr;
+  VOID                    *Ivrs;
+  BOOLEAN                 IvrsSupport;
+  GNB_HANDLE              *GnbHandle;
+
+  Status = AGESA_SUCCESS;
+  LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader;
+  IvrsSupport = FALSE;
+  Ivrs = LateParamsPtr->AcpiIvrs;
+  if (Ivrs == NULL) {
+    Ivrs = GnbAllocateHeapBuffer (
+             AMD_ACPI_IVRS_BUFFER_HANDLE,
+             IVRS_TABLE_LENGTH,
+             StdHeader
+             );
+    ASSERT (Ivrs != NULL);
+    if (Ivrs == NULL) {
+      return  AGESA_ERROR;
+    }
+    LateParamsPtr->AcpiIvrs = Ivrs;
+  }
+  LibAmdMemFill (Ivrs, 0x0, IVRS_TABLE_LENGTH, StdHeader);
+  LibAmdMemCopy (Ivrs, &IvrsHeader, sizeof (IvrsHeader), StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  while (GnbHandle != NULL) {
+    if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Build IVRS for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      IvrsSupport = TRUE;
+      GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdBlock, Ivrs, StdHeader);
+      GnbBuildIvmdList (IvrsIvmdBlock, Ivrs, StdHeader);
+      if (GnbBuildOptions.IvrsRelativeAddrNamesSupport) {
+        GnbFmCreateIvrsEntry (GnbHandle, IvrsIvhdrBlock, Ivrs, StdHeader);
+        GnbBuildIvmdList (IvrsIvmdrBlock, Ivrs, StdHeader);
+      }
+    }
+    GnbHandle = GnbGetNextHandle (GnbHandle);
+  }
+  if (IvrsSupport == TRUE) {
+    ChecksumAcpiTable ((ACPI_TABLE_HEADER*) Ivrs, StdHeader);
+    GNB_DEBUG_CODE (GnbIommuIvrsTableDump (Ivrs, StdHeader));
+  } else {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  IVRS table not generated\n");
+    LateParamsPtr->AcpiIvrs = NULL;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build IVMD list
+ *
+ *
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbBuildIvmdList (
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  IOMMU_EXCLUSION_RANGE_DESCRIPTOR  *IvrsExclusionRangeList;
+  IVRS_IVMD_ENTRY                   *Ivmd;
+  UINT16                            StartId;
+  UINT16                            EndId;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Entry\n");
+  IvrsExclusionRangeList = ((AMD_LATE_PARAMS*)StdHeader)->IvrsExclusionRangeList;
+  if (IvrsExclusionRangeList != NULL) {
+    // Process the entire IvrsExclusionRangeList here and create an IVMD for eache entry
+    IDS_HDT_CONSOLE (GNB_TRACE, "Process Exclusion Range List\n");
+    while ((IvrsExclusionRangeList->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) {
+      if ((IvrsExclusionRangeList->Flags & DESCRIPTOR_IGNORE) == 0) {
+        // Address of IVMD entry
+        Ivmd = (IVRS_IVMD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength);
+        StartId =
+          (IvrsExclusionRangeList->RequestorIdStart.Bus << 8) +
+          (IvrsExclusionRangeList->RequestorIdStart.Device << 3) +
+          (IvrsExclusionRangeList->RequestorIdStart.Function);
+        EndId =
+          (IvrsExclusionRangeList->RequestorIdEnd.Bus << 8) +
+          (IvrsExclusionRangeList->RequestorIdEnd.Device << 3) +
+          (IvrsExclusionRangeList->RequestorIdEnd.Function);
+        GnbIvmdAddEntry (
+          Type,
+          StartId,
+          EndId,
+          IvrsExclusionRangeList->RangeBaseAddress,
+          IvrsExclusionRangeList->RangeLength,
+          Ivmd,
+          StdHeader);
+        // Add entry size to existing table length
+        ((IOMMU_IVRS_HEADER *)Ivrs)->TableLength += sizeof (IVRS_IVMD_ENTRY);
+      }
+      // Point to next entry in IvrsExclusionRangeList
+      IvrsExclusionRangeList++;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBuildIvmdList Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dump IVRS table
+ *
+ *
+ * @param[in]     Ivrs            Pointer to IVRS table
+ * @param[in]     StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbIommuIvrsTableDump (
+  IN       VOID                 *Ivrs,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8   *Block;
+  UINT8   *Entry;
+  Block = (UINT8 *) Ivrs + sizeof (IOMMU_IVRS_HEADER);
+  IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table Start -----------> \n");
+  IDS_HDT_CONSOLE (GNB_TRACE, "  IVInfo           = 0x%08x\n", ((IOMMU_IVRS_HEADER *) Ivrs)-> IvInfo);
+  while (Block < ((UINT8 *) Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength)) {
+    if (*Block == IvrsIvhdBlock) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block Start -------->\n");
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Flags            = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->Flags);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  DeviceId         = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->DeviceId);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  CapabilityOffset = 0x%02x\n", ((IVRS_IVHD_ENTRY *) Block)->CapabilityOffset);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  BaseAddress      = 0x%08x%08x\n", (UINT32) (((IVRS_IVHD_ENTRY *) Block)->BaseAddress >> 32), (UINT32) ((IVRS_IVHD_ENTRY *) Block)->BaseAddress);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  PCI Segment      = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->PciSegment);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  IommuInfo        = 0x%04x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuInfo);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  IommuEfr         = 0x%08x\n", ((IVRS_IVHD_ENTRY *) Block)->IommuEfr);
+      Entry = Block + sizeof (IVRS_IVHD_ENTRY);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block Device Entries Start -------->\n");
+      while (Entry < (Block + ((IVRS_IVHD_ENTRY *) Block)->Length)) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "  ");
+        switch (*Entry) {
+        case IvhdEntrySelect:
+        case IvhdEntryEndRange:
+          GnbLibDebugDumpBuffer (Entry, 4, 1, 4);
+          Entry = Entry + 4;
+          break;
+        case IvhdEntryStartRange:
+          GnbLibDebugDumpBuffer (Entry, 8, 1, 8);
+          Entry = Entry + 8;
+          break;
+        case IvhdEntryAliasStartRange:
+          GnbLibDebugDumpBuffer (Entry, 12, 1, 12);
+          Entry = Entry + 12;
+          break;
+        case IvhdEntryAliasSelect:
+        case IvhdEntryExtendedSelect:
+        case IvhdEntrySpecialDevice:
+          GnbLibDebugDumpBuffer (Entry, 8, 1, 8);
+          Entry = Entry + 8;
+          break;
+        case IvhdEntryPadding:
+          Entry = Entry + 4;
+          break;
+        default:
+          IDS_HDT_CONSOLE (GNB_TRACE, "  Unsupported entry type [%d]\n");
+          ASSERT (FALSE);
+        }
+      }
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block Device Entries End -------->\n");
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVHD Block End ---------->\n");
+      Block = Block + ((IVRS_IVHD_ENTRY *) Block)->Length;
+    } else if (
+        (*Block == IvrsIvmdBlock) ||
+        (*Block == IvrsIvmdBlockRange) ||
+        (*Block == IvrsIvmdBlockSingle) ||
+        (*Block == IvrsIvmdrBlock) ||
+        (*Block == IvrsIvmdrBlockSingle)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVMD Block Start -------->\n");
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Flags            = 0x%02x\n", ((IVRS_IVMD_ENTRY *) Block)->Flags);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  DeviceId         = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->DeviceId);
+      switch (*Block) {
+      case IvrsIvmdBlock:
+      case IvrsIvmdrBlock:
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Applies to all devices\n");
+        break;
+      case IvrsIvmdBlockSingle:
+      case IvrsIvmdrBlockSingle:
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Applies to a single device\n");
+        break;
+      default:
+        IDS_HDT_CONSOLE (GNB_TRACE, "  DeviceId End   = 0x%04x\n", ((IVRS_IVMD_ENTRY *) Block)->AuxiliaryData);
+      }
+      IDS_HDT_CONSOLE (GNB_TRACE, "  StartAddress     = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockStart >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockStart);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  BockLength       = 0x%08x%08x\n", (UINT32) (((IVRS_IVMD_ENTRY *) Block)->BlockLength >> 32), (UINT32) ((IVRS_IVMD_ENTRY *) Block)->BlockLength);
+      IDS_HDT_CONSOLE (GNB_TRACE, "  <-------------IVMD Block End ---------->\n");
+      Block = Block + ((IVRS_IVMD_ENTRY *) Block)->Length;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table Raw Data --------> \n");
+  GnbLibDebugDumpBuffer (Ivrs, ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength, 1, 16);
+  IDS_HDT_CONSOLE (GNB_TRACE, "\n");
+  IDS_HDT_CONSOLE (GNB_TRACE, "<----------  IVRS Table End -------------> \n");
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h
new file mode 100644
index 0000000000..c48224f970
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBIOMMUIVRS_H_
+#define _GNBIOMMUIVRS_H_
+
+AGESA_STATUS
+GnbIommuIvrsTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c
new file mode 100644
index 0000000000..b5eb7ed124
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFamServices.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Iommu Scratch Memory Range
+ * 1) code needs to be executed at Late Init
+ * 2) Allocate heap using  heap type HEAP_RUNTIME_SYSTEM_MEM
+ * 3) Allocate enough memory to be able to get address aligned required by register
+ * 4) Assign same address to all Gnb in system
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+AGESA_STATUS
+GnbIommuScratchMemoryRangeInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  ALLOCATE_HEAP_PARAMS  AllocHeapParams;
+  UINT32                AddressLow;
+  UINT32                AddressHigh;
+  GNB_HANDLE            *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Enter\n");
+
+  AllocHeapParams.RequestedBufferSize = 128;
+  AllocHeapParams.BufferHandle = AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE;
+  AllocHeapParams.Persist = HEAP_RUNTIME_SYSTEM_MEM;
+  Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
+  if (Status != AGESA_SUCCESS) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  Iommu Scratch Memory not allocated.\n");
+    ASSERT (FALSE);
+    return AGESA_FATAL;
+  }
+
+  AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK;
+  AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK;
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  while (GnbHandle != NULL) {
+    if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Set Iommu Scratch Memory for Socket %d Silicon %d\n", GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      GnbLibPciIndirectWrite (
+        GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+        D0F0x98_x27_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        &AddressLow,
+        StdHeader);
+
+      GnbLibPciIndirectWrite (
+        GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+        D0F0x98_x26_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        &AddressHigh,
+        StdHeader);
+    }
+    GnbHandle = GnbGetNextHandle (GnbHandle);
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuScratchMemoryRangeInterface Exit\n");
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
new file mode 100644
index 0000000000..d18493eb09
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c
@@ -0,0 +1,267 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64895 $   @e \$Date: 2012-02-02 01:01:48 -0600 (Thu, 02 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbIommu.h"
+#include  "GnbFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbIommuIvrs.h"
+#include  "GnbIvrsLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry for device range
+ *
+ *
+ * @param[in]  StartRange      Address of start range
+ * @param[in]  EndRange        Address of end range
+ * @param[in]  DataSetting     Data setting
+ * @param[in]  Ivhd            Pointer to IVHD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvhdAddDeviceRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  IVHD_GENERIC_ENTRY  *Entry;
+  Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
+  Entry->Type = IvhdEntryStartRange;
+  Entry->DeviceId = DEVICE_ID (StartRange);
+  Entry->DataSetting = DataSetting;
+  Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
+  Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
+  Entry->Type = IvhdEntryEndRange;
+  Entry->DeviceId = DEVICE_ID (EndRange);
+  Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry for aliased range
+ *
+ *
+ * @param[in]  StartRange      Address of start range
+ * @param[in]  EndRange        Address of end range
+ * @param[in]  Alias           Address of alias requestor ID for range
+ * @param[in]  DataSetting     Data setting
+ * @param[in]  Ivhd            Pointer to IVHD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvhdAddDeviceAliasRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       PCI_ADDR             Alias,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  IVHD_ALIAS_ENTRY    *RangeEntry;
+  IVHD_GENERIC_ENTRY  *Entry;
+  UINT16              Offset;
+  Offset = (Ivhd->Length + 0x7) & (~ 0x7);
+  RangeEntry = (IVHD_ALIAS_ENTRY *) ((UINT8 *) Ivhd + Offset);
+  RangeEntry->Type = IvhdEntryAliasStartRange;
+  RangeEntry->DeviceId = DEVICE_ID (StartRange);
+  RangeEntry->AliasDeviceId = DEVICE_ID (Alias);
+  RangeEntry->DataSetting = DataSetting;
+  Ivhd->Length = sizeof (IVHD_ALIAS_ENTRY) + Offset;
+  Entry = (IVHD_GENERIC_ENTRY *) ((UINT8 *) Ivhd + Ivhd->Length);
+  Entry->Type = IvhdEntryEndRange;
+  Entry->DeviceId = DEVICE_ID (EndRange);
+  Ivhd->Length += sizeof (IVHD_GENERIC_ENTRY);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry for special device
+ *
+ *
+ * @param[in]  SpecialDevice   Special device Type
+ * @param[in]  Device          Address of requestor ID for special device
+ * @param[in]  Id              Apic ID/ Hpet ID
+ * @param[in]  DataSetting     Data setting
+ * @param[in]  Ivhd            Pointer to IVHD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvhdAddSpecialDeviceEntry (
+  IN       IVHD_SPECIAL_DEVICE  SpecialDevice,
+  IN       PCI_ADDR             Device,
+  IN       UINT8                Id,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  IVHD_SPECIAL_ENTRY  *SpecialEntry;
+  UINT16               Offset;
+  Offset = (Ivhd->Length + 0x7) & (~ 0x7);
+  SpecialEntry = (IVHD_SPECIAL_ENTRY *) ((UINT8 *) Ivhd + Offset);
+  SpecialEntry->Type = IvhdEntrySpecialDevice;
+  SpecialEntry->AliasDeviceId = DEVICE_ID (Device);
+  SpecialEntry->Variety = (UINT8) SpecialDevice;
+  SpecialEntry->Handle = Id;
+  SpecialEntry->DataSetting = DataSetting;
+  Ivhd->Length = sizeof (IVHD_SPECIAL_ENTRY) + Offset;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVMD entry
+ *
+ *
+ * @param[in]  Type            Root type for IVMD (IvrsIvmdBlock or IvrsIvmdrBlock)
+ * @param[in]  StartDevice     Device ID of start device range
+ *                             Use 0x0000 for ALL
+ * @param[in]  EndDevice       Device ID of end device range
+ *                             Use 0xFFFF for ALL
+ *                             Use == StartDevice for specific device
+ * @param[in]  BlockAddress    Address of memory block to be excluded
+ * @param[in]  BlockLength     Length of memory block go be excluded
+ * @param[in]  Ivmd            Pointer to IVMD entry
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbIvmdAddEntry (
+  IN       IVRS_BLOCK_TYPE      Type,
+  IN       UINT16               StartDevice,
+  IN       UINT16               EndDevice,
+  IN       UINT64               BlockAddress,
+  IN       UINT64               BlockLength,
+  IN       IVRS_IVMD_ENTRY      *Ivmd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  Ivmd->Flags = IVMD_FLAG_EXCLUSION_RANGE;
+  Ivmd->Length = sizeof (IVRS_IVMD_ENTRY);
+  Ivmd->DeviceId = StartDevice;
+  Ivmd->AuxiliaryData = 0x0;
+  Ivmd->Reserved = 0x0000000000000000;
+  Ivmd->BlockStart = BlockAddress;
+  Ivmd->BlockLength = BlockLength;
+  if (Type == IvrsIvmdBlock) {
+    if (StartDevice == EndDevice) {
+      Ivmd->Type = IvrsIvmdBlockSingle;
+    } else if ((StartDevice == 0x0000) && (EndDevice == 0xFFFF)) {
+      Ivmd->Type = IvrsIvmdBlock;
+    } else {
+      Ivmd->Type = IvrsIvmdBlockRange;
+      Ivmd->AuxiliaryData = EndDevice;
+    }
+  } else {
+    if (StartDevice == EndDevice) {
+      Ivmd->Type = IvrsIvmdrBlockSingle;
+    } else {
+      Ivmd->Type = IvrsIvmdrBlock;
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h
new file mode 100644
index 0000000000..5291d34f1b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.h
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBIVRSLIB_H_
+#define _GNBIVRSLIB_H_
+
+
+VOID
+GnbIvhdAddDeviceRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+GnbIvhdAddDeviceAliasRangeEntry (
+  IN       PCI_ADDR             StartRange,
+  IN       PCI_ADDR             EndRange,
+  IN       PCI_ADDR             Alias,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+GnbIvhdAddSpecialDeviceEntry (
+  IN       IVHD_SPECIAL_DEVICE  SpecialDevice,
+  IN       PCI_ADDR             Device,
+  IN       UINT8                Id,
+  IN       UINT8                DataSetting,
+  IN       IVRS_IVHD_ENTRY      *Ivhd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+GnbIvmdAddEntry (
+  IN       IVRS_BLOCK_TYPE      Type,
+  IN       UINT16               StartDevice,
+  IN       UINT16               EndDevice,
+  IN       UINT64               BlockAddress,
+  IN       UINT64               BlockLength,
+  IN       IVRS_IVMD_ENTRY      *Ivmd,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
new file mode 100644
index 0000000000..f160e8bcb1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c
@@ -0,0 +1,203 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB UNB library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuServices.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFamServices.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Host bridge PCI Address
+ *
+ *
+ *
+ * @param[in]   GnbHandle      Socket ID
+ * @param[in]   StdHeader      Standard configuration header
+ * @retval                     PCI address of GNB for a given socket/silicon.
+ */
+
+PCI_ADDR
+GnbFmGetPciAddress (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  GnbPciAddress;
+  UINT8     NodeId;
+  UINT8     Register;
+  UINT32    Value;
+  GnbPciAddress.AddressValue = ILLEGAL_SBDFO;
+  NodeId = GnbGetNodeId (GnbHandle);
+  for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) {
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader);
+    if (((Value >> 4) & 0x7) == NodeId) {
+      GnbPciAddress.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0, 0, 0);
+      break;
+    }
+  }
+  ASSERT (GnbPciAddress.AddressValue != ILLEGAL_SBDFO);
+  return GnbPciAddress;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bus range decoded by GNB
+ *
+ * Final bus allocation can not be assumed until AmdInitMid
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  StartBusNumber  Beggining of the Bus Range
+ * @param[out]  EndBusNumber    End of the Bus Range
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+AGESA_STATUS
+GnbFmGetBusDecodeRange (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *StartBusNumber,
+     OUT   UINT8                      *EndBusNumber,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT8         NodeId;
+  UINT8         Register;
+  UINT32        Value;
+  AGESA_STATUS  Status;
+  Status = AGESA_ERROR;
+  NodeId = GnbGetNodeId (GnbHandle);
+  for (Register = 0xE0; Register <= 0xEC; Register = Register + 4) {
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 24 + NodeId, 1, Register), AccessWidth32, &Value, StdHeader);
+    if (((Value >> 4) & 0x7) == NodeId) {
+      *StartBusNumber = (UINT8) ((Value >> 16) & 0xff);
+      *EndBusNumber = (UINT8) ((Value >> 24) & 0xff);
+      Status = AGESA_SUCCESS;
+      break;
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link to which GNB connected to
+ *
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  LinkId          Link to which GNB connected to
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+
+AGESA_STATUS
+GnbFmGetLinkId (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *LinkId,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32  Value;
+  ASSERT (GnbHandle->NodeId != 0xFF);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18 + GnbHandle->NodeId, 0, 0x1A0), AccessWidth32, &Value, StdHeader);
+  *LinkId = LibAmdBitScanForward (Value & 0xAAAA) / 2;
+  ASSERT (*LinkId < 8);
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
new file mode 100644
index 0000000000..942d34d539
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
@@ -0,0 +1,432 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init NB set top of memory
+ *
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+AGESA_STATUS
+GnbSetTom (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AGESA_STATUS  Status;
+  UINT64        MsrData;
+  UINT32        Value;
+  Status = AGESA_SUCCESS;
+  //Read memory size below 4G from MSR C001_001A
+  LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader);
+  //Write to NB register 0x90
+  Value = (UINT32)MsrData & 0xFF800000;     //Keep bits 31:23
+  GnbLibPciRMW (
+    NbPciAddress.AddressValue | D0F0x90_ADDRESS,
+    AccessS3SaveWidth32,
+    0x007FFFFF,
+    Value,
+    StdHeader
+    );
+  if (Value == 0) {
+    Status = AGESA_WARNING;
+  }
+
+  LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
+  if ((MsrData & BIT21) != 0) {
+    //Read memory size above 4G from MSR C001_001D
+    LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader);
+    // Write memory size[39:32] to indirect register 1A[7:0]
+    Value = (UINT32) ((MsrData >> 32) & 0xFF);
+    GnbLibPciIndirectRMW (
+      NbPciAddress.AddressValue | D0F0x60_ADDRESS,
+      D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      0xFFFFFF00,
+      Value,
+      StdHeader
+    );
+
+    // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0
+    Value = (UINT32)MsrData & 0xFF800000;     //Keep bits 31:23
+    Value |= BIT0;                            // Enable top of memory
+    GnbLibPciIndirectRMW (
+      NbPciAddress.AddressValue | D0F0x60_ADDRESS,
+      D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      0x007FFFFF,
+      Value,
+      StdHeader
+    );
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Avoid LPC DMA transaction deadlock
+ *
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbLpcDmaDeadlockPrevention (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // For GPP Link core, enable special NP memory write protocol on the  processor side PCIE controller
+  GnbLibPciIndirectRMW (
+    NbPciAddress.AddressValue | D0F0xE0_ADDRESS,
+    CORE_SPACE (1, D0F0xE4_CORE_0010_ADDRESS),
+    AccessWidth32,
+    0xFFFFFFFF,
+    1 << 9 ,
+    StdHeader
+  );
+
+  //Enable special NP memory write protocol in ORB
+  GnbLibPciIndirectRMW (
+    NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+    D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessS3SaveWidth32,
+    0xFFFFFFFF,
+    1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET,
+    StdHeader
+  );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Dynamic Wake
+ * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
+ *   that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high).
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbOrbDynamicWake (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+
+  ex495_STRUCT     ex495  ;
+
+  GnbLibPciIndirectRead (
+    NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+    0x2c  | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessWidth32,
+    &ex495.Value,
+    StdHeader
+    );
+
+  // Enable Dynamic wake
+  // Wake Hysteresis timer value.  Specifies the number of SMU pulses to count.
+  if (GnbBuildOptions.CfgOrbDynWakeEnable) {
+    ex495.Field.ex495_1  = 1;
+  } else {
+    ex495.Field.ex495_1  = 0;
+  }
+  ex495.Field.ex495_3  = 0x64;
+
+  IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &ex495, StdHeader);
+
+  GnbLibPciIndirectWrite (
+    NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+    0x2c  | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessS3SaveWidth32,
+    &ex495.Value,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lock NB registers
+ *
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbLock (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  GnbLibPciIndirectWriteField (
+    NbPciAddress.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
+    D0F0x64_x00_HwInitWrLock_OFFSET,
+    D0F0x64_x00_HwInitWrLock_WIDTH,
+    0x1,
+    TRUE,
+    StdHeader
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * UnitID Clumping
+ *
+ *
+ * @param[in] NbPciAddress    Gnb PCI address
+ * @param[in] StdHeader       Standard Configuration Header
+ */
+
+VOID
+GnbClumpUnitID (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32  Value;
+  GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 2, 0, 0), AccessWidth32, &Value, StdHeader);
+  if (Value != 0xFFFFFFFF) {
+    GnbLibPciRead (MAKE_SBDFO (0, NbPciAddress.Address.Bus, 3, 0, 0), AccessWidth32, &Value, StdHeader);
+    if (Value == 0xFFFFFFFF) {
+      GnbLibPciIndirectRMW (
+        NbPciAddress.AddressValue | D0F0x94_ADDRESS,
+        0x3a  | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        0xFFFFFFFF,
+        1 << 3 /* D0F0x98_x3A_ClumpingEn_OFFSET*/,
+        StdHeader
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the index of highest SCLK VID
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID index
+ */
+UINT8
+GnbLocateHighestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8             MaxVid;
+  UINT8             MaxVidIndex;
+  UINTN             Index;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray == NULL) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  ERROR!!! Heap Location\n");
+    return 0;
+  }
+
+  MaxVidIndex = 0;
+  MaxVid = 0xff;
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->SclkVid[Index] != 0 && PpFuseArray->SclkVid[Index] < MaxVid) {
+      MaxVid = PpFuseArray->SclkVid[Index];
+      MaxVidIndex = (UINT8) Index;
+    }
+  }
+  ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0);
+  return MaxVidIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the index of lowest SCLK VID
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID index
+ */
+UINT8
+GnbLocateLowestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8             MinVidIndex;
+  UINTN             Index;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray == NULL) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  ERROR!!! Heap Location\n");
+    return 0;
+  }
+
+  MinVidIndex = 0;
+
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->SclkVid[Index] > PpFuseArray->SclkVid[MinVidIndex]) {
+      MinVidIndex = (UINT8) Index;
+    }
+  }
+  ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0);
+  return MinVidIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the highest SCLK VID (high voltage)
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID
+ */
+UINT8
+GnbLocateHighestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                         MaxVidIndex;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+
+  MaxVidIndex = GnbLocateHighestVidIndex (StdHeader);
+  ASSERT (PpFuseArray->SclkVid[MaxVidIndex] != 0);
+  return PpFuseArray->SclkVid[MaxVidIndex];
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the lowest SCLK VID (low voltage)
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    NBVDD VID
+ */
+UINT8
+GnbLocateLowestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT8                         MinVidIndex;
+  PP_FUSE_ARRAY     *PpFuseArray;
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  MinVidIndex = GnbLocateLowestVidIndex (StdHeader);
+  ASSERT (PpFuseArray->SclkVid[MinVidIndex] != 0);
+  return PpFuseArray->SclkVid[MinVidIndex];
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
new file mode 100644
index 0000000000..948ee4c404
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBNBINITLIBV1_H_
+#define _GNBNBINITLIBV1_H_
+
+
+AGESA_STATUS
+GnbSetTom (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLpcDmaDeadlockPrevention (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbOrbDynamicWake (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbLock (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+GnbClumpUnitID (
+  IN      PCI_ADDR            NbPciAddress,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+UINT8
+GnbLocateHighestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+UINT8
+GnbLocateLowestVidIndex (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+UINT8
+GnbLocateHighestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+UINT8
+GnbLocateLowestVidCode (
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
new file mode 100644
index 0000000000..faf72986d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -0,0 +1,620 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "GnbFamServices.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define SMC_RAM_START_ADDR 0x10000ul
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA     ScanData;
+  GNB_TOPOLOGY_INFO     *TopologyInfo;
+} GNB_TOPOLOGY_INFO_DATA;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GnbSmuServiceRequestV4S3Script (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      UINT16                ContextLength,
+  IN      VOID                  *Context
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check a PCIE device to see if it supports phantom functions
+ *
+ * @param[in] Device      Device pci address
+ * @param[in] StdHeader   Standard configuration header
+ * @return    TRUE        Current device supports phantom functions
+ */
+STATIC BOOLEAN
+GnbCheckPhantomFuncSupport (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  UINT8   PcieCapPtr;
+  UINT32  Value;
+  Value = 0;
+
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 4), AccessWidth32, &Value, StdHeader);
+  }
+  return ((Value & (BIT3 | BIT4)) != 0) ? TRUE : FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status
+ */
+
+SCAN_STATUS
+STATIC
+GnbTopologyInfoScanCallback (
+  IN       PCI_ADDR                 Device,
+  IN OUT   GNB_PCI_SCAN_DATA        *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  GNB_TOPOLOGY_INFO_DATA  *GnbTopologyInfo;
+  PCIE_DEVICE_TYPE        DeviceType;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  GnbIommuInfoScanCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  GnbTopologyInfo = (GNB_TOPOLOGY_INFO_DATA *)ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData);
+    break;
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &GnbTopologyInfo->ScanData);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDevicePcieToPcix:
+    GnbTopologyInfo->TopologyInfo->PcieToPciexBridge = TRUE;
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    if (GnbCheckPhantomFuncSupport (Device, ScanData->StdHeader)) {
+      GnbTopologyInfo->TopologyInfo->PhantomFunction = TRUE;
+    }
+    ScanStatus = SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  default:
+    break;
+  }
+  return ScanStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get IOMMU topology info
+ *
+ *
+ *
+ * @param[in] StartPciAddress   Start PCI address
+ * @param[in] EndPciAddress     End PCI address
+ * @param[in] TopologyInfo      Topology info structure
+ * @param[in] StdHeader         Standard Configuration Header
+ */
+
+AGESA_STATUS
+GnbGetTopologyInfoV4 (
+  IN       PCI_ADDR                  StartPciAddress,
+  IN       PCI_ADDR                  EndPciAddress,
+     OUT   GNB_TOPOLOGY_INFO         *TopologyInfo,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  GNB_TOPOLOGY_INFO_DATA  GnbTopologyInfo;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Enter\n");
+  GnbTopologyInfo.ScanData.GnbScanCallback = GnbTopologyInfoScanCallback;
+  GnbTopologyInfo.ScanData.StdHeader = StdHeader;
+  GnbTopologyInfo.TopologyInfo = TopologyInfo;
+  GnbLibPciScan (StartPciAddress, EndPciAddress, &GnbTopologyInfo.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbGetTopologyInfoV4 Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SMU service request
+ *
+ *
+ * @param[in]  GnbPciAddress   GNB PCI address
+ * @param[in]  RequestId       Request ID
+ * @param[in]  AccessFlags     See GNB_ACCESS_FLAGS_* definitions
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+VOID
+GnbSmuServiceRequestV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       UINT8                    RequestId,
+  IN       UINT32                   AccessFlags,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  D0F0xBC_xE0003004_STRUCT  D0F0xBC_xE0003004;
+  D0F0xBC_xE0003000_STRUCT  D0F0xBC_xE0003000;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Enter\n");
+  IDS_HDT_CONSOLE (NB_MISC, "  Service Request %d\n", RequestId);
+
+  if ((AccessFlags & GNB_REG_ACC_FLAG_S3SAVE) != 0) {
+    SMU_MSG_CONTEXT SmuMsgContext;
+    SmuMsgContext.GnbPciAddress.AddressValue = GnbPciAddress.AddressValue;
+    SmuMsgContext.RequestId = RequestId;
+    S3_SAVE_DISPATCH (StdHeader, GnbSmuServiceRequestV4S3Script_ID, sizeof (SmuMsgContext), &SmuMsgContext);
+  }
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader);
+  } while (D0F0xBC_xE0003004.Field.IntDone == 0x0);
+  GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader);
+  D0F0xBC_xE0003000.Field.IntToggle = ~D0F0xBC_xE0003000.Field.IntToggle;
+  D0F0xBC_xE0003000.Field.ServiceIndex = RequestId;
+  GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003000_ADDRESS, AccessWidth32, &D0F0xBC_xE0003000.Value, StdHeader);
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader);
+  } while (D0F0xBC_xE0003004.Field.IntAck == 0x0);
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003004_ADDRESS, AccessWidth32, &D0F0xBC_xE0003004.Value, StdHeader);
+  } while (D0F0xBC_xE0003004.Field.IntDone == 0x0);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuServiceRequestV4 Exit\n");
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SMU service request for S3 script
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @param[in]  ContextLength   Context length
+ * @param[in]  Context         Pointer to Context
+ */
+
+VOID
+GnbSmuServiceRequestV4S3Script (
+  IN      AMD_CONFIG_PARAMS     *StdHeader,
+  IN      UINT16                ContextLength,
+  IN      VOID                  *Context
+  )
+{
+  SMU_MSG_CONTEXT   *SmuMsgContext;
+  SmuMsgContext =  (SMU_MSG_CONTEXT *) Context;
+  GnbSmuServiceRequestV4 (SmuMsgContext->GnbPciAddress, SmuMsgContext->RequestId, 0, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SMU firmware download
+ *
+ *
+ * @param[in]  GnbPciAddress   GNB Pci Address
+ * @param[in]  Firmware        Pointer tp firmware
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+AGESA_STATUS
+GnbSmuFirmwareLoadV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       FIRMWARE_HEADER_V4       *Firmware,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  UINT32                     Index;
+  D0F0xBC_xE00030A4_STRUCT  D0F0xBC_xE00030A4;
+  D0F0xBC_xE0000004_STRUCT  D0F0xBC_xE0000004;
+  D0F0xBC_xE0003088_STRUCT  D0F0xBC_xE0003088;
+  ex1005_STRUCT   ex1005 ;
+  D0F0xBC_x1F380_STRUCT      D0F0xBC_x1F380;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Enter\n");
+  IDS_HDT_CONSOLE (NB_MISC, "  Firmware version 0x%x\n", Firmware->Version);
+  // Step 2, 10, make sure Rom firmware sequance is done
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0000004_ADDRESS, AccessWidth32, &D0F0xBC_xE0000004.Value, StdHeader);
+  } while (D0F0xBC_xE0000004.Field.boot_seq_done == 0);
+  // Step 1, check if firmware running in protected mode
+  GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE00030A4_ADDRESS, AccessWidth32, &D0F0xBC_xE00030A4.Value, StdHeader);
+  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {
+    // Step3, Clear firmware interrupt flags
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_x1F380_ADDRESS,
+      AccessWidth32,
+      0x0,
+      0x0,
+      StdHeader
+      );
+  }
+  //Step 4, 11, Assert LM32 reset
+  GnbLibPciIndirectRMW (
+    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+    0x80000000 ,
+    AccessWidth32,
+    (UINT32) ~(0x1 ),
+    1 << 0 ,
+    StdHeader
+    );
+  // Step5, 12, Load firmware
+  for (Index = 0; Index < (Firmware->FirmwareLength + Firmware->HeaderLength); Index++) {
+    GnbLibPciIndirectWrite (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, SMC_RAM_START_ADDR + (Index * 4), AccessWidth32, &((UINT32 *) Firmware)[Index], StdHeader);
+  }
+  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 0) {
+    //Step 6, Write jmp to RAM firmware
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      0x0,
+      AccessWidth32,
+      0x0,
+      0xE0000000 + ((SMC_RAM_START_ADDR + Firmware->HeaderLength * 4) >> 2),
+      StdHeader
+      );
+  } else {
+    //Step 13, Clear autentification done
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_xE0003088_ADDRESS,
+      AccessWidth32,
+      0x0,
+      0x0,
+      StdHeader
+      );
+  }
+  // Step 7, 14 Enable LM32 clock
+  GnbLibPciIndirectRMW (
+    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+    0x80000004 ,
+    AccessWidth32,
+    (UINT32) ~(0x1 ),
+    0 << 0 ,
+    StdHeader
+    );
+
+  //Step 8, 15, Deassert LM32 reset
+  GnbLibPciIndirectRMW (
+    GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+    0x80000000 ,
+    AccessWidth32,
+    (UINT32) ~(0x1 ),
+    0 << 0 ,
+    StdHeader
+    );
+
+  if (D0F0xBC_xE00030A4.Field.SmuProtectedMode == 1) {
+    IDS_HDT_CONSOLE (NB_MISC, "  Protected mode: poll init autehtication vector\n");
+    // Step 16, Wait for rom firmware init autehtication vector
+    do {
+      GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, 0x80010000 , AccessWidth32, &ex1005.Value, StdHeader);
+    } while (ex1005.Value != 0x400);
+    // Call Authentication service
+    GnbSmuServiceRequestV4 (GnbPciAddress, SMC_MSG_FIRMWARE_AUTH, 0, StdHeader);
+    IDS_HDT_CONSOLE (NB_MISC, "  Protected mode: poll init autehtication done\n");
+    // Wait for autehtication done
+    do {
+      GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_xE0003088_ADDRESS, AccessWidth32, &D0F0xBC_xE0003088.Value, StdHeader);
+    } while (D0F0xBC_xE0003088.Field.SmuAuthDone == 0x0);
+    //Step 17, Check Authentication results
+    if (D0F0xBC_xE0003088.Field.SmuAuthPass == 0) {
+      IDS_HDT_CONSOLE (NB_MISC, "  ERROR!!!Autehtication fail!!!\n");
+      ASSERT (FALSE);
+      return AGESA_FATAL;
+    }
+    // Step 18, Clear firmware interrupt enable flag
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_x1F380_ADDRESS,
+      AccessWidth32,
+      0x0,
+      0x0,
+      StdHeader
+      );
+    //Step 19, Assert LM32 reset
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      0x80000000 ,
+      AccessWidth32,
+      (UINT32) ~(0x1 ),
+      1 << 0 ,
+      StdHeader
+      );
+    //Step 20, Deassert LM32 reset
+    GnbLibPciIndirectRMW (
+      GnbPciAddress.AddressValue | D0F0xB8_ADDRESS,
+      0x80000000 ,
+      AccessWidth32,
+      (UINT32) ~(0x1 ),
+      0 << 0 ,
+      StdHeader
+      );
+  }
+//Step 9, 21 Wait firmware to initialize
+  do {
+    GnbLibPciIndirectRead (GnbPciAddress.AddressValue | D0F0xB8_ADDRESS, D0F0xBC_x1F380_ADDRESS, AccessWidth32, &D0F0xBC_x1F380.Value, StdHeader);
+  } while (D0F0xBC_x1F380.Field.InterruptsEnabled == 0);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSmuFirmwareLoadV4 Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get IOMMU PCI address
+ *
+ *
+ * @param[in]  GnbHandle       GNB handle
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+PCI_ADDR
+GnbGetIommuPciAddressV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PCI_ADDR  GnbIommuPciAddress;
+  GnbIommuPciAddress = GnbGetHostPciAddress (GnbHandle);
+  GnbIommuPciAddress.Address.Function = 0x2;
+  return  GnbIommuPciAddress;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * UnitID Clumping
+ *
+ *
+ * @param[in]  GnbHandle       GNB handle
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+VOID
+GnbClumpUnitIdV4 (
+  IN      GNB_HANDLE                *GnbHandle,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT32              Value;
+
+  Value = 0;
+  EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_PCIE_ENGINE, &GnbHandle->Header);
+  while (EngineList != NULL) {
+    if (EngineList->Type.Port.NumberOfUnitId != 0) {
+      if (!PcieConfigIsActivePcieEngine (EngineList)) {
+        Value |= (((1 << EngineList->Type.Port.NumberOfUnitId) - 1) << EngineList->Type.Port.UnitId);
+      } else {
+        if (EngineList->Type.Port.NumberOfUnitId > 1) {
+          Value |= (((1 << (EngineList->Type.Port.NumberOfUnitId - 1)) - 1) << (EngineList->Type.Port.UnitId + 1));
+        }
+      }
+    }
+    EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
+  }
+  // Set GNB
+  GnbLibPciIndirectRMW (
+    GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+    D0F0x98_x3A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+    AccessS3SaveWidth32,
+    (UINT32) ~Value,
+    Value,
+    StdHeader
+    );
+  //Set UNB
+  GnbLibPciRMW (
+    MAKE_SBDFO (0, 0, GnbHandle->NodeId + 0x18, 0, D18F0x110_ADDRESS + GnbHandle->LinkId * 4),
+    AccessS3SaveWidth32,
+    (UINT32) ~Value,
+    Value,
+    StdHeader
+    );
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Config GNB to prevent LPC deadlock scenario
+ *
+ *
+ * @param[in]  GnbHandle       GNB handle
+ * @param[in]  StdHeader       Standard configuration header
+ */
+
+VOID
+GnbLpcDmaDeadlockPreventionV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  PCIe_ENGINE_CONFIG    *EngineList;
+
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &GnbHandle->Header);
+  EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &GnbHandle->Header);
+  while (EngineList != NULL) {
+    if (PcieConfigIsPcieEngine (EngineList) && PcieConfigIsSbPcieEngine (EngineList)) {
+      PcieRegisterRMW (
+        PcieConfigGetParentWrapper (EngineList),
+        CORE_SPACE (EngineList->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
+        D0F0xE4_CORE_0010_UmiNpMemWrite_MASK,
+        1 << D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET,
+        TRUE,
+        Pcie
+        );
+      //Enable special NP memory write protocol in ORB
+      GnbLibPciIndirectRMW (
+        GnbHandle->Address.AddressValue | D0F0x94_ADDRESS,
+        D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
+        AccessS3SaveWidth32,
+        0xFFFFFFFF,
+        1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET,
+        StdHeader
+        );
+      break;
+    }
+    EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable IOMMU base address. (MMIO space )
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        AGESA_SUCCESS
+ * @retval        AGESA_ERROR
+ */
+
+AGESA_STATUS
+GnbEnableIommuMmioV4 (
+  IN       GNB_HANDLE           *GnbHandle,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AGESA_STATUS            Status;
+  UINT16                  CapabilityOffset;
+  UINT64                  BaseAddress;
+  UINT32                  Value;
+  PCI_ADDR                GnbIommuPciAddress;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Enter\n");
+
+  if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) {
+    GnbIommuPciAddress = GnbGetIommuPciAddressV4 (GnbHandle, StdHeader);
+    CapabilityOffset = GnbLibFindPciCapability (GnbIommuPciAddress.AddressValue, IOMMU_CAP_ID, StdHeader);
+
+    GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessWidth32, &Value, StdHeader);
+    BaseAddress = (UINT64) Value << 32;
+    GnbLibPciRead (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessWidth32, &Value, StdHeader);
+    BaseAddress |= Value;
+
+    if ((BaseAddress & 0xfffffffffffffffe) != 0x0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader);
+      GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader);
+    } else {
+      ASSERT (FALSE);
+      Status = AGESA_ERROR;
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnableIommuMmio Exit\n");
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h
new file mode 100644
index 0000000000..95d97df935
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.h
@@ -0,0 +1,149 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * NB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBNBINITLIBV4_H_
+#define _GNBNBINITLIBV4_H_
+
+#pragma pack (push, 1)
+
+/// Firmware header
+typedef struct {
+  UINT32  Version;                  ///< Version
+  UINT32  HeaderLength;             ///< Header length
+  UINT32  FirmwareLength;           ///< Firmware length
+  UINT32  EntryPoint;               ///< Entry point
+  UINT32  MessageDigest[5];         ///< Message digest
+  UINT32  Reserved_A[3];            ///< Reserved
+  UINT32  CurrentSystemState;       ///< Current system state
+  UINT32  DpmCacHistory;            ///< DpmCac History
+  UINT32  DpmResidencyCounters;     ///< DPM recidency counters
+  UINT32  Reserved_B[16];           ///< Reserved
+  UINT32  Reserved_C[16];           ///< Reserved
+  UINT32  Reserved_D[16];           ///< Reserved
+  UINT32  HeaderEnd;                ///< Header end signature
+} FIRMWARE_HEADER_V4;
+
+/// SMU service request contect
+typedef struct {
+  PCI_ADDR          GnbPciAddress;   ///< PCIe address of GNB
+  UINT8             RequestId;       ///< Request/Msg ID
+} SMU_MSG_CONTEXT;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+GnbGetTopologyInfoV4 (
+  IN       PCI_ADDR                  StartPciAddress,
+  IN       PCI_ADDR                  EndPciAddress,
+     OUT   GNB_TOPOLOGY_INFO         *TopologyInfo,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+VOID
+GnbSmuServiceRequestV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       UINT8                    RequestId,
+  IN       UINT32                   AccessFlags,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbSmuFirmwareLoadV4 (
+  IN       PCI_ADDR                 GnbPciAddress,
+  IN       FIRMWARE_HEADER_V4       *Firmware,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+PCI_ADDR
+GnbGetIommuPciAddressV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+VOID
+GnbClumpUnitIdV4 (
+  IN      GNB_HANDLE                *GnbHandle,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+VOID
+GnbLpcDmaDeadlockPreventionV4 (
+  IN       GNB_HANDLE               *GnbHandle,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbEnableIommuMmioV4 (
+  IN       GNB_HANDLE           *GnbHandle,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
new file mode 100644
index 0000000000..1b3742da7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -0,0 +1,578 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "cpuLateInit.h"
+#include  "cpuRegisters.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "OptionGnb.h"
+#include  "PcieAlib.h"
+#include  "GnbFuseTable.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern  F_ALIB_GET    *AlibGetBaseTable;
+extern  F_ALIB_UPDATE *AlibDispatchTable[];
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieAlibUpdatePcieMmioInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+PcieAlibUpdateVoltageInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+AGESA_STATUS
+PcieAlibUpdatePcieInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+STATIC
+PcieAlibSetPortMaxSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+STATIC
+PcieAlibSetPortOverrideSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+STATIC
+PcieAlibSetPortInfoCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PcieAlibBuildAcpiTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+     OUT   VOID                 **AlibSsdtPtr
+  );
+
+VOID
+STATIC
+PcieAlibSetSclkVid (
+  IN OUT   VOID                  *Buffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create ACPI ALIB SSDT table
+ *
+ *
+ *
+ * @param[in] StdHeader           Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieAlibFeature (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  AMD_LATE_PARAMS *LateParamsPtr;
+  LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader;
+  return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build ALIB ACPI table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @param[in,out] AlibSsdtPtr     Pointer to pointer to ALIB SSDT table
+ * @retval        AGESA_SUCCESS
+ * @retval        AGESA_ERROR
+ */
+
+AGESA_STATUS
+PcieAlibBuildAcpiTable (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+     OUT   VOID                 **AlibSsdtPtr
+  )
+{
+  AGESA_STATUS            Status;
+  AGESA_STATUS            AgesaStatus;
+  UINTN                   Index;
+  VOID                    *AlibSsdtBuffer;
+  VOID                    *AlibSsdtTable;
+  UINTN                   AlibSsdtlength;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  AlibSsdtTable = AlibGetBaseTable (StdHeader);
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength;
+  if (*AlibSsdtPtr == NULL) {
+    AlibSsdtBuffer = GnbAllocateHeapBuffer (
+                       AMD_ACPI_ALIB_BUFFER_HANDLE,
+                       AlibSsdtlength,
+                       StdHeader
+                       );
+    ASSERT (AlibSsdtBuffer != NULL);
+    if (AlibSsdtBuffer == NULL) {
+      return  AGESA_ERROR;
+    }
+    *AlibSsdtPtr = AlibSsdtBuffer;
+  } else {
+    AlibSsdtBuffer = *AlibSsdtPtr;
+  }
+  // Copy template to buffer
+  LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader);
+  // Disaptch fucntion form table
+  Index = 0;
+  while (AlibDispatchTable[Index] != NULL) {
+    Status = AlibDispatchTable[Index] (AlibSsdtBuffer, StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Index++;
+  }
+  if (AgesaStatus != AGESA_SUCCESS) {
+    //Shrink table length to size of the header
+    ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
+  }
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTable Exit [0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update MMIO info
+ *
+ *
+ *
+ *
+ * @param[in] AlibSsdtBuffer      Ponter to SSDT table
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+AGESA_STATUS
+PcieAlibUpdatePcieMmioInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32        AmlObjName;
+  UINT32        AlibSsdtlength;
+  VOID          *AmlObjPtr;
+  AGESA_STATUS  Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Enter\n");
+  Status = AGESA_SUCCESS;
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength;
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '1');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    UINT64  LocalMsrRegister;
+    LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader);
+    if ((LocalMsrRegister & BIT0) != 0 && (LocalMsrRegister & 0xFFFFFFFF00000000) == 0) {
+      *(UINT32*)((UINT8*) AmlObjPtr + 5) = (UINT32)(LocalMsrRegister & 0xFFFFF00000);
+    } else {
+      Status = AGESA_FATAL;
+    }
+  } else {
+    Status = AGESA_FATAL;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieMmioInfo Exit\n");
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update MMIO info
+ *
+ *
+ *
+ *
+ * @param[in] AlibSsdtBuffer      Ponter to SSDT table
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+AGESA_STATUS
+PcieAlibUpdateVoltageInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32          AmlObjName;
+  UINT32          AlibSsdtlength;
+  VOID            *AmlObjPtr;
+  UINT8           BootUpVidIndex;
+  UINT8           Gen1VidIndex;
+  PP_FUSE_ARRAY   *PpFuseArray;
+  AGESA_STATUS    Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Enter\n");
+  Status = AGESA_SUCCESS;
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength;
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '3');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      *(UINT8*)((UINT8*) AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid;
+    } else {
+      Status = AGESA_FATAL;
+    }
+  } else {
+    Status = AGESA_FATAL;
+  }
+
+  Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader);
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '4');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    *(UINT8*)((UINT8*) AmlObjPtr + 5) = Gen1VidIndex;
+  } else {
+    Status = AGESA_FATAL;
+  }
+
+  BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader);
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '5');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    *(UINT8*)((UINT8*) AmlObjPtr + 5) = BootUpVidIndex;
+  } else {
+    Status = AGESA_FATAL;
+  }
+
+  AmlObjName = STRING_TO_UINT32 ('A', 'D', '1', '0');
+  AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+  ASSERT (AmlObjPtr != NULL);
+  if (AmlObjPtr != NULL) {
+    PcieAlibSetSclkVid ((UINT8*) ((UINT8*)AmlObjPtr + 7), StdHeader);
+  } else {
+    Status = AGESA_FATAL;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageInfo Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update PCIe info
+ *
+ *
+ *
+ *
+ * @param[in] AlibSsdtBuffer      Ponter to SSDT table
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+AGESA_STATUS
+PcieAlibUpdatePcieInfo (
+  IN OUT   VOID                  *AlibSsdtBuffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  UINT32                AmlObjName;
+  UINT32                AlibSsdtlength;
+  VOID                  *AmlObjPtr;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Enter\n");
+  Status = AGESA_SUCCESS;
+  AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength;
+  if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '2');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      *(UINT8*)((UINT8*) AmlObjPtr + 5) = Pcie->PsppPolicy;
+    } else {
+      Status = AGESA_FATAL;
+    }
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '6');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      PcieConfigRunProcForAllEngines (
+        DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+        PcieAlibSetPortMaxSpeedCallback,
+        (UINT8*)((UINT8*) AmlObjPtr + 7),
+        Pcie
+        );
+    } else {
+      Status = AGESA_FATAL;
+    }
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '8');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      PcieConfigRunProcForAllEngines (
+        DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+        PcieAlibSetPortOverrideSpeedCallback,
+        (UINT8*)((UINT8*) AmlObjPtr + 7),
+        Pcie
+        );
+    } else {
+      Status = AGESA_FATAL;
+    }
+    AmlObjName = STRING_TO_UINT32 ('A', 'D', '0', '7');
+    AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+    ASSERT (AmlObjPtr != NULL);
+    if (AmlObjPtr != NULL) {
+      PcieConfigRunProcForAllEngines (
+        DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+        PcieAlibSetPortInfoCallback,
+        (UINT8*)((UINT8*) AmlObjPtr + 4),
+        Pcie
+        );
+    } else {
+      Status = AGESA_FATAL;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieInfo Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init max port speed capability
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortMaxSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   *PsppMaxPortSpeedPackage;
+  PsppMaxPortSpeedPackage = (UINT8*) Buffer;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init max port speed capability
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortOverrideSpeedCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   *PsppOverridePortSpeedPackage;
+  PsppOverridePortSpeedPackage = (UINT8*) Buffer;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode;
+  }
+  if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init port info
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortInfoCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ALIB_PORT_INFO_PACKAGE  *PortInfoPackage;
+  UINT8                   PortIndex;
+  PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer;
+  PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2;
+  PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane;
+  PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane;
+  PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane;
+  PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane;
+  PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId;
+  PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieConfigGetParentWrapper (Engine)->WrapId);
+  PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
+  PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine);
+  PortInfoPackage->PortInfo[PortIndex].ClkPmSupport = Engine->Type.Port.PortData.MiscControls.ClkPmSupport;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init port info
+ *
+ *
+ *
+ *
+ * @param[in, out]  Buffer          Asl buffer
+ * @param[in]       StdHeader       Standard configuration header
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetSclkVid (
+  IN OUT   VOID                  *Buffer,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8             *SclkVid;
+  PP_FUSE_ARRAY     *PpFuseArray;
+  UINT8             Index;
+
+  SclkVid = (UINT8*) Buffer;
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray == NULL) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "  ERROR!!! Heap Location\n");
+    return;
+  }
+
+  for (Index = 0; Index < 4; Index++) {
+    SclkVid[Index * 2 + 1] = PpFuseArray->SclkVid[Index];
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h
new file mode 100644
index 0000000000..63a06e1ab2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIB_H_
+#define _PCIEALIB_H_
+
+#pragma pack (push, 1)
+///Port info asl buffer
+typedef struct {
+  UINT8                   BufferOp;           ///< Opcode
+  UINT8                   PkgLength;          ///< Package length
+  UINT8                   BufferSize;         ///< Buffer size
+  UINT8                   ByteList;           ///< Byte lisy
+  UINT8                   StartPhyLane;       ///< Port Start PHY lane
+  UINT8                   EndPhyLane;         ///< Port End PHY lane
+  UINT8                   StartCoreLane;      ///< Port Start Core lane
+  UINT8                   EndCoreLane;        ///< Port End Core lane
+  UINT8                   PortId;             ///< Port ID
+  UINT16                  WrapperId;          ///< Wrapper ID
+  UINT8                   LinkHotplug;        ///< Link hotplug type
+  UINT8                   MaxSpeedCap;        ///< Max port speed capability
+  UINT8                   ClkPmSupport;       ///< ClkPmSupport
+} ALIB_PORT_INFO_BUFFER;
+///Ports info asl package
+typedef struct {
+  UINT8                   PackageOp;          ///< Opcode
+  UINT8                   PkgLength;          ///< Package length
+  UINT8                   NumElements;        ///< number of elements
+  UINT8                   PackageElementList; ///< package element list
+  ALIB_PORT_INFO_BUFFER   PortInfo[7];        ///< Array of port info buffers
+} ALIB_PORT_INFO_PACKAGE;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+PcieAlibFeature (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
new file mode 100644
index 0000000000..5c53c6b870
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * ALIB PSPP config
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBCONFIG_H_
+#define _PCIEALIBCONFIG_H_
+
+//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT
+// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK
+
+#define DEF_OFFSET_START_CORE_LANE              2
+#define DEF_OFFSET_END_CORE_LANE                3
+#define DEF_OFFSET_START_PHY_LANE               0
+#define DEF_OFFSET_END_PHY_LANE                 1
+#define DEF_OFFSET_PORT_ID                      4
+#define DEF_OFFSET_WRAPPER_ID                   5
+#define DEF_OFFSET_LINK_HOTPLUG                 7
+#define DEF_OFFSET_GEN2_CAP                     8
+#define DEF_OFFSET_CLK_PM_SUPPORT               9
+
+#define DEF_BASIC_HOTPLUG                       1
+
+#define DEF_PSPP_POLICY_START                   1
+#define DEF_PSPP_POLICY_STOP                    0
+#define DEF_PSPP_POLICY_PERFORMANCE             1
+#define DEF_PSPP_POLICY_BALANCEHIGH             2
+#define DEF_PSPP_POLICY_BALANCELOW              3
+#define DEF_PSPP_POLICY_POWERSAVING             4
+#define DEF_PSPP_STATE_AC                       0
+#define DEF_PSPP_STATE_DC                       1
+
+#define DEF_TRAINING_STATE_COMPLETE             0
+#define DEF_TRAINING_STATE_DETECT_PRESENCE      1
+#define DEF_TRAINING_STATE_PRESENCE_DETECTED    2
+#define DEF_TRAINING_GEN2_WORKAROUND            3
+#define DEF_TRAINING_STATE_NOT_PRESENT          4
+#define DEF_TRAINING_DEVICE_PRESENT             5
+#define DEF_TRAINING_STATE_RELEASE_TRAINING     6
+#define DEF_TRAINING_STATE_REQUEST_RESET        7
+#define DEF_TRAINING_STATE_EXIT                 8
+
+#define DEF_LINK_SPEED_GEN1                     1
+#define DEF_LINK_SPEED_GEN2                     2
+
+#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT   0
+#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT       1
+
+#define DEF_PORT_NOT_ALLOCATED                  0
+#define DEF_PORT_ALLOCATED                      1
+
+#define DEF_PCIE_LANE_POWERON                   1
+#define DEF_PCIE_LANE_POWEROFF                  0
+#define DEF_PCIE_LANE_POWEROFFUNUSED            2
+
+#define DEF_SCARTCH_PSPP_START_OFFSET           0
+#define DEF_SCARTCH_PSPP_POLICY_OFFSET          1
+#define DEF_SCARTCH_PSPP_ACDC_OFFSET            5
+#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET        6
+#define DEF_SCARTCH_PSPP_REQ_OFFSET             16
+
+#define DEF_LINKWIDTH_ACTIVE                    0
+#define DEF_LINKWIDTH_MAX_PHY                   1
+
+#define DEF_SB_PORT_INDEX                       6
+
+#define TRUE                                    1
+#define FALSE                                   0
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
new file mode 100644
index 0000000000..bc1f70db88
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
@@ -0,0 +1,111 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Master control method
+   *
+   *  Arg0 - Function ID
+   *  Arg1 - Function specific data buffer
+   */
+  Method (ALIB, 2, NotSerialized) {
+    If (Lequal (Arg0, 0x1)) {
+      return (procPsppReportAcDsState (Arg1))
+    }
+    If (LEqual (Arg0, 0x2)) {
+      return (procPsppPerformanceRequest (Arg1))
+    }
+    If (LEqual (Arg0, 0x3)) {
+      return (procPsppControl (Arg1))
+    }
+    If (LEqual (Arg0, 0x4)) {
+      return (procPcieSetBusWidth (Arg1))
+    }
+    If (LEqual (Arg0, 0x5)) {
+      return (procAlibInit ())
+    }
+    If (LEqual (Arg0, 0x6)) {
+      return (procPciePortHotplug (Arg1))
+    }
+    return (0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Alib Init
+   *
+   *
+   */
+  Method (procAlibInit, 0, Serialized) {
+
+    return (0)
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
new file mode 100644
index 0000000000..e8820cf502
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibDebugLib.esl
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+  Name (varStringBuffer, Buffer (256) {})
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
new file mode 100644
index 0000000000..951193a57b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
@@ -0,0 +1,787 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+   External(\_SB.ALIC,  MethodObj)
+   External(P80H)
+
+  Name (varStartPhyLane, 0)
+  Name (varEndPhyLane, 0)
+  Name (varStartCoreLane, 0)
+  Name (varEndCoreLane, 0)
+  Name (varWrapperId, 0)
+  Name (varPortId, 0)
+  Name (varMaxPhyLinkWidth, 0)
+
+  Name (varNormalizeLinkWidthBuffer, Buffer () {1, 2, 4, 4, 8, 8, 8, 8, 16, 16, 16, 16, 16, 16, 16, 16})
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Set PCIe Bus Width
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPcieSetBusWidth, 1, NotSerialized) {
+    Store ("procPcieSetBusWidth Enter", Debug)
+
+    Name (varClientBus, 0)
+    Name (varArgBusWidth, 0)
+    Store (0, varPortIndex)
+    Store (Buffer (10) {}, Local7)
+
+    //ClientId: WORD
+    //Bits  2-0: Function number.
+    //Bits  7-3: Device number.
+    //Bits 15-8: Bus number.
+    Store (DerefOf (Index (Arg0, 0x3)), varClientBus)
+    Store (DerefOf (Index (Arg0, 0x4)), varArgBusWidth)
+    Store (Concatenate ("  Client Bus   : ", ToHexString (varClientBus), varStringBuffer), Debug)
+    Store (Concatenate ("  Arg Bus Width : ", ToHexString (varArgBusWidth), varStringBuffer), Debug)
+
+    Store (3, Index (Local7, 0x0)) // Return Buffer Length
+    Store (0, Index (Local7, 0x1)) // Return Buffer Length
+    Store (varArgBusWidth, Index (Local7, 0x2)) // Return BusWidth
+    // disable interface
+    return (Local7)
+
+    //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes
+
+    // determine port index base on "Client ID"
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) {
+        Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
+        And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2)             //Local2 Port Subordinate Bus number
+        And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1)                //Local1 Port Secondary Bus number
+        if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) {
+          break
+        }
+      }
+      Increment (varPortIndex)
+    }
+    if (LGreater (varPortIndex, varMaxPortIndexNumber)) {
+      Store ("procPcieSetBusWidth Exit -- over max port index", Debug)
+      return (Local7)
+    }
+
+    Store (Concatenate ("  Pcie Set BusWidth for port index : ", ToHexString (varPortIndex), varStringBuffer), Debug)
+
+    // Normalize link width (Num Lanes) to correct value x1, x2.x4,x8,x16,
+    // make sure that number of lanes requested to be powered on less or equal mx port link width
+    if (LLessEqual (procPcieGetLinkWidth (varPortIndex, DEF_LINKWIDTH_MAX_PHY), varArgBusWidth)) {
+      // Active link equal max link width, nothing needs to be done
+      Store ("procPcieSetBusWidth Exit -- over max lanes supported", Debug)
+      return (Local7)
+    }
+    Store (DeRefOf (Index (varNormalizeLinkWidthBuffer, varArgBusWidth)), Local1)
+
+
+    // call procPcieLaneControl to power on all lanes (Arg0 - port index , Arg1 - 1, Arg2 = 0)
+    procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWERON, 0)
+
+    // call procPcieLaneControl power off unused lanes (Arg0 - port index, Arg1 - 1, Arg2 = Link width)
+    procPcieLaneControl (varPortIndex, DEF_PCIE_LANE_POWEROFFUNUSED, Local1)
+
+#ifdef PHY_SPEED_REPORT_SUPPORT
+    procReportPhySpeedCap ()
+#endif
+    Store (Local1, Index (Local7, 0x2)) // Return BusWidth
+
+    Store ("procPcieSetBusWidth Exit", Debug)
+    return (Local7)
+  }
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe port hotplug
+   *
+   *  Arg0   - Data Buffer
+   *  Retval - Return buffer
+   */
+  Method (procPciePortHotplug, 1, Serialized) {
+    Store ("PciePortHotplug Enter", Debug)
+    Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0)
+    Store (DerefOf (Index (Arg0, 2)), varPortBdfLocal1)
+
+    Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal4)
+    if (LEqual(varHotplugStateLocal0, 1)) {
+      // Enable port
+      Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2)
+    } else {
+      // Disable port
+      Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2)
+    }
+
+    //Disable ASPM
+    Store (procPciDwordRead (varPortBdfLocal1, 0x68), Local3)
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00)
+
+    Store (procPciePortTraining (varPortIndexLocal4, Local2), varHotplugStateLocal0)
+
+    //Restore ASPM
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (Local3, 0x3))
+
+#ifdef PHY_SPEED_REPORT_SUPPORT
+    procReportPhySpeedCap ()
+#endif
+
+    Store (Buffer (10) {}, Local7)
+    CreateWordField (Local7, 0x0, varReturnBufferLength)
+    CreateByteField (Local7, 0x2, varReturnStatus)
+    CreateByteField (Local7, 0x3, varReturnDeviceStatus)
+    Store (0x4, varReturnBufferLength)
+    Store (0x0, varReturnStatus)
+    Store (varHotplugStateLocal0, varReturnDeviceStatus)
+    Store ("PciePortHotplug Exit", Debug)
+    return (Local7)
+  }
+
+  Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0})
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Train PCIe port
+   *
+   *
+   *  Arg0  - Port Index
+   *  Arg1  - Initial state
+   */
+  Method (procPciePortTraining, 2, Serialized) {
+    Store ("PciePortTraining Enter", Debug)
+    Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+    // Check if port supports basic hotplug
+    Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1)
+    if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) {
+      Store ("  No action.[Hotplug type]", Debug)
+      Store ("procPciePortTraining Exit", Debug)
+      return (varResultLocal4)
+    }
+    Store (Arg1, varStateLocal2)
+    while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) {
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) {
+        Store (" State: Release training", Debug)
+        // Remove link speed override
+        Store (0, Index (varOverrideLinkSpeed, Arg0))
+        // Enable link width upconfigure
+        procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000)
+        if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+          // Request Max link speed for hotplug by going to AC state
+          Store (0, varPsppAcDcOverride)
+          procApplyPsppState ()
+        } else {
+          procPcieSetLinkSpeed (Arg0, DeRefOf (Index (varMaxLinkSpeed, Arg0)))
+        }
+        // Power on/enable port lanes
+        procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON, 0)
+        // Release training
+        procPcieTrainingControl (Arg0, 0)
+        // Move to next state to check presence detection
+        Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2)
+        // Initialize retry count
+        Store(0, varCountLocal3)
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) {
+        Store (" State: Detect presence", Debug)
+        And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1)
+        if (LGreater (varTempLocal1, 0x4)) {
+          // device connection detected move to next state
+          Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2)
+          // reset retry counter
+          Store(0, varCountLocal3)
+          continue
+        }
+        if (LLess (varCountLocal3, 80)) {
+          Sleep (1)
+          Increment (varCountLocal3)
+        } else {
+          // detection time expired move to device not present state
+          Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+        }
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) {
+        Store (" State: Device detected", Debug)
+        Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1)
+        And (varTempLocal1, 0x3f, varTempLocal1)
+        if (LAnd (LGreaterEqual (varTempLocal1, 0x10), LLessEqual (varTempLocal1, 0x13))) {
+          Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2)
+          continue
+        }
+        if (LLess (varCountLocal3, 80)) {
+          Sleep (1)
+          Increment (varCountLocal3)
+          continue
+        }
+        Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+        if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) {
+          // GEN2 workaround already applied but device not trained successfully move device not present state
+          continue
+        }
+
+        if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) {
+          Store (" Request Gen2 workaround", Debug)
+          procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000)
+          Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0))
+          procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1)
+          Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2)
+        }
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) {
+        Store (" State: Device not present", Debug)
+        procPcieTrainingControl (Arg0, 1)
+        procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF, 0)
+#ifdef  PCIE_MAX_PAYLOAD_SUPPORT
+        procPcieClearMaxPayload (Arg0)
+#endif
+
+        // Find device on secondary bus
+        Store (ShiftLeft (Add( Arg0, 2), 3), varTempBdfLocal0)
+        Store (procPciDwordRead (varTempBdfLocal0, 0x18), varTempLocal1)
+        And (ShiftRight (varTempLocal1, 8), 0xFF,  varTempLocal1)
+        Store (Concatenate ("  Remove device from Bus   : ", ToHexString (varTempLocal1), varStringBuffer), Debug)
+        ShiftLeft (varTempLocal1, 8, varTempBdfLocal0)
+        Store (procPciDwordRead (varTempBdfLocal0, 0x0), varTempLocal0)
+        if (LEqual (varTempLocal0, 0xFFFFFFFF)) {
+          Store ("  Device has been un-pluged!! ", Debug)
+        }
+        // Exclude device from PSPP managment since it is not present
+        Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0))
+        Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2)
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) {
+        Store (" State: Request Reset", Debug)
+        if (CondRefOf (\_SB.ALIC, Local6)) {
+          Store (" Call ALIC method", Debug)
+          //varTempLocal1  contain port BDF
+          Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1)
+          \_SB.ALIC (varTempLocal1, 0)
+          Sleep (2)
+          \_SB.ALIC (varTempLocal1, 1)
+          Store (0, varCountLocal3)
+          Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2)
+          continue
+        }
+        Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) {
+        Store (" State: Device present", Debug)
+        Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4)
+        Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2)
+#ifdef  PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK
+        procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED, 0)
+#endif
+#ifdef  PCIE_MAX_PAYLOAD_SUPPORT
+        procPcieSetMaxPayload (Arg0)
+#endif
+#ifdef  PCIE_CLKPM_SUPPORT
+        procPcieClkPmConfigure (Arg0)
+#endif
+      }
+      if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) {
+        if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+          Store (1, varPsppAcDcOverride)
+          procApplyPsppState ()
+        }
+        Store (DEF_TRAINING_STATE_EXIT, varStateLocal2)
+      }
+    }
+    Store ("PciePortTraining Exit", Debug)
+    return (varResultLocal4)
+  }
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Lane control
+   *
+   *  Arg0   - Port Index
+   *  Arg1   - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes
+   *  Arg2   - link width
+   */
+
+  Method (procPcieLaneControl, 3, Serialized) {
+    Store ("PcieLaneControl Enter", Debug)
+    Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+    Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+#endif
+    Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane)
+
+    Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varMaxPhyLinkWidth)
+
+    if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) {
+      procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 1)
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+      procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1)
+#endif
+    }
+    if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) {
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+      procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0)
+#endif
+      procPcieLaneEnableControl (Arg0, varStartCoreLane, Add (varStartCoreLane, Subtract(varMaxPhyLinkWidth, 1)), 0)
+    }
+    if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) {
+      return (0)
+    }
+
+    //  Local2 should have link width (active lanes)
+    //  Local3 should have first non active lanes
+    //  Local4 should have last non active lanes
+
+    if (LEqual(Arg2, 0)) {
+      Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2)
+    } else {
+      Store ( Arg2 , varActiveLinkWidthLocal2)
+    }
+    // Let say Link width is x1 than local2 = 1, Local3 = 1 Local4 = 15 for non reversed case
+    // while for reversed case should be Local2 = 1 Local3 = 0 and Local4 = 14
+
+    if (LLessEqual (varMaxPhyLinkWidth, varActiveLinkWidthLocal2)) {
+      // Active link equal max link width, nothing needs to be done
+      return (0)
+    }
+
+    Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1)
+    //There is unused lanes after device plugged
+    if (LEqual(varIsReversedLocal1, FALSE)) {
+      Store (" Port Not Reversed", Debug)
+      // Link not reversed
+      Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3)
+      Store (varEndCoreLane, Local4)
+    } else {
+      // Link reversed
+      Store (" Port Reversed", Debug)
+      Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4)
+      Store (varStartCoreLane, Local3)
+    }
+    procPcieLaneEnableControl (Arg0, Local3, Local4, 1)
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
+    if (LGreater (varStartPhyLane, varEndPhyLane)) {
+      Store (varEndPhyLane, Local3)
+      Store (varStartPhyLane, Local4)
+    } else {
+      Store (varEndPhyLane, Local4)
+      Store (varStartPhyLane, Local3)
+    }
+    if (LEqual(varIsReversedLocal1, FALSE)) {
+      // Not reversed
+      Add (Local3, varActiveLinkWidthLocal2, Local3)
+    } else {
+      // Link reversed
+      Subtract (Local4, varActiveLinkWidthLocal2, Local4)
+    }
+    procPcieLanePowerControl (Local3, Local4, 1)
+#endif
+    return (0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Check if GEN2 workaround applicable
+   *
+   *  Arg0   - Port Index
+   *  Retval - TRUE / FALSE
+   */
+
+  Method (procPcieCheckForGen2Workaround, 1, NotSerialized) {
+    Store (Buffer (16) {}, Local1)
+    Store (0x0, Local0)
+    while (LLessEqual (Local0, 0x3)) {
+      Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2)
+      Store (Local2,  Index (Local1, Multiply (Local0, 4)))
+      Store (ShiftRight (Local2, 8),   Index (Local1, Add (Multiply (Local0, 4), 1)))
+      Store (ShiftRight (Local2, 16),  Index (Local1, Add (Multiply (Local0, 4), 2)))
+      Store (ShiftRight (Local2, 24),  Index (Local1, Add (Multiply (Local0, 4), 3)))
+      Increment (Local0)
+    }
+    Store (0, Local0)
+    while (LLess (Local0, 15)) {
+      if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a),  LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) {
+        return (TRUE)
+      }
+      Increment (Local0)
+    }
+    return (FALSE)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Is port reversed
+   *
+   *  Arg0   - Port Index
+   *  Retval - 0 - Not reversed / !=0 - Reversed
+   */
+  Method (procPcieIsPortReversed , 1, Serialized) {
+    Store (procPcieGetPortInfo (Arg0), Local7)
+
+    Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+    Store (0, Local0)
+    if (LGreater (varStartPhyLane, varEndPhyLane)) {
+      Store (1, Local0)
+    }
+    And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1)
+    return (And (Xor (Local0, Local1), 0x1))
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Training Control
+   *
+   *  Arg0  - Port Index
+   *  Arg1  - Hold Training (1) / Release Training (0)
+   */
+  Method (procPcieTrainingControl , 2, NotSerialized) {
+    Store ("PcieTrainingControl Enter", Debug)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+    Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId)
+    Store (
+      Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))),
+      varWrapperId
+    )
+    procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1);
+    Store ("PcieTrainingControl Exit", Debug)
+  }
+
+
+Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Get actual negotiated/PHY or core link width
+   *
+   *  Arg0   - Port Index
+   *  Arg1   - 0/1 Negotiated/Phy
+   *  Retval - Link Width
+   */
+  Method (procPcieGetLinkWidth, 2, NotSerialized) {
+    Store ("PcieGetLinkWidth Enter", Debug)
+    Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+
+    if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){
+       //Get negotiated length
+      And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0)
+      Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1)
+      Store (Concatenate ("  Active Link Width :", ToHexString (Local1), varStringBuffer), Debug)
+    } else {
+       //Get phy length
+      Store (procPcieGetPortInfo (Arg0), Local7)
+      Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+      Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+      if (LGreater (varStartPhyLane, varEndPhyLane)) {
+        Subtract (varStartPhyLane, varEndPhyLane, Local1)
+      } else {
+        Subtract (varEndPhyLane, varStartPhyLane, Local1)
+      }
+      Increment (Local1)
+      Store (Concatenate ("  PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug)
+    }
+    Store ("PcieGetLinkWidth Exit", Debug)
+    return (Local1)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe lane mux lane enable control (hotplug support)
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Start Lane
+   *  Arg2 - End Lane
+   *  Arg3 - Enable(0) / Disable(1)
+   */
+  Method (procPcieLaneEnableControl, 4, Serialized) {
+    Store ("PcieLaneEnableControl Enter", Debug)
+    Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+    Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug)
+    Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug)
+    Store (procPcieGetPortInfo (Arg0), Local7)
+    Store (Arg1, varStartCoreLane)
+    Store (Arg2, varEndCoreLane)
+    Store (
+      Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))),
+      varWrapperId
+    )
+    if (LGreater (varStartCoreLane, varEndCoreLane)) {
+      Subtract (varStartCoreLane, varEndCoreLane, Local1)
+      Store (varEndCoreLane, Local2)
+    } else {
+      Subtract (varEndCoreLane, varStartCoreLane, Local1)
+      Store (varStartCoreLane, Local2)
+    }
+    ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3)
+    Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4)
+    Store (Concatenate (" Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug)
+    if (Lequal (Arg3, 1)) {
+      Store (0, varLaneBitmapOrMaskLocal3)
+    }
+    procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3);
+    Stall (10)
+    Store ("PcieLaneEnableControl Exit", Debug)
+  }
+
+#ifdef  PCIE_MAX_PAYLOAD_SUPPORT
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Max_Payload_Size Blacklist
+   *
+   *  Entry 1 = Vendor & Device ID
+   *  Entry 2 = Max_Payload_Size for this device
+   */
+  Name (varPayloadBlacklist, Package () {
+    Package() {0x10831969, 0}
+  })
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Set Max_Payload_Size
+   *
+   *  Arg0 - Port Index
+   */
+   Method (procPcieSetMaxPayload, 1, Serialized) {
+
+   // Local variable usage
+   // varTempLocal0 - Temporary storage
+   // varBdfLocal1 - Address of port config space
+   // varCapLocal2 - Offset of port PCIe Capabilities
+   // varMaxPayloadLocal3 - Largest common value of Max_Payload_Size capability
+   // varMaxFunctionLocal4 - Max function number
+   // varFunctionLocal5 - Current function number
+   // varDeviceIDLocal6 - Root port BDF and Vendor and device ID for blacklist workaround
+   // varIndexLocal7 - Package index for blacklist workaround
+
+    Store ("PcieSetMaxPayload Enter", Debug)
+
+    // Get Port BDF from Port Index
+    Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6)
+    Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2)
+    if (LNotEqual (varCapLocal2, 0)) {
+
+      // Find device on secondary bus
+      Store (procPciDwordRead (varDeviceIDLocal6, 0x18), varTempLocal0)
+      And (ShiftRight (varTempLocal0, 8), 0xFF,  varTempLocal0)
+
+      Store (Concatenate ("  EP on SecondaryBus : ", ToHexString (varTempLocal0), varStringBuffer), Debug)
+
+      ShiftLeft (varTempLocal0, 8, varBdfLocal1)
+
+      Store (procPciDwordRead (varBdfLocal1, 0xC), varTempLocal0)
+      Store (And (ShiftRight (varTempLocal0, 16), 0xFF),  varTempLocal0)
+      if (LNotEqual (And (varTempLocal0, 0x80), 0)) {
+        Store (0x7, varMaxFunctionLocal4)
+      } else {
+        Store (0x0, varMaxFunctionLocal4)
+      }
+      // Start with illegal value so we will know if a device is foudn
+      Store (0x08, varMaxPayloadLocal3)
+      // Search all functions and find smallest Max_Payload_Size
+      Store (0x0, varFunctionLocal5)
+      while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) {
+        Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2)
+        if (LNotEqual (varCapLocal2, 0)) {
+          And (procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), Add (varCapLocal2, 0x04)), 0x07, varTempLocal0)
+          // Scan blacklist package for workaround
+          Store(procPciDwordRead (Add (varBdfLocal1, varFunctionLocal5), 0), varDeviceIDLocal6)
+          Store (0, varIndexLocal7)
+          while (LLess (varIndexLocal7, SizeOf (varPayloadBlacklist))) {
+            if (LEqual (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 0)), varDeviceIDLocal6)) {
+              Store (DeRefOf (Index (DeRefOf (Index (varPayloadBlacklist, varIndexLocal7)), 1)), varTempLocal0)
+            }
+            Increment (varIndexLocal7)
+          }
+          if (LLess (varTempLocal0, varMaxPayloadLocal3)) {
+            Store (varTempLocal0, varMaxPayloadLocal3)
+          }
+        }
+        Increment(varFunctionLocal5)
+      }
+
+      // We will only set Max_Payload_Size if PCIe capabilties were found on the downstream side
+      if (LNotEqual (varMaxPayloadLocal3, 0x08)) {
+        // Read root port Max_Payload_Size and compare with device supported value
+        Store (ShiftLeft (Add( Arg0, 2), 3), varDeviceIDLocal6)
+        Store (procFindPciCapability (varDeviceIDLocal6, 0x10), varCapLocal2)
+        And (procPciDwordRead (varDeviceIDLocal6, Add (varCapLocal2, 0x04)), 0x07, varTempLocal0)
+        if (LLess (varTempLocal0, varMaxPayloadLocal3)) {
+          Store (varTempLocal0, varMaxPayloadLocal3)
+        }
+        // Search all functions and set smallest Max_Payload_Size to all functions
+        // Relocate Max_Payload_Size data to bits 7-5
+        Store (Concatenate ("  Setting Max_Payload_Size : ", ToHexString (varMaxPayloadLocal3), varStringBuffer), Debug)
+        ShiftLeft (varMaxPayloadLocal3, 5, varMaxPayloadLocal3)
+        // Set the root port Max_Payload_Size
+        procPciDwordRMW (varDeviceIDLocal6, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3)
+        //Set the Max_Payload_Size in each function that has PCIe Capabilities
+        Store (0x0, varFunctionLocal5)
+        while (LLessEqual (varFunctionLocal5, varMaxFunctionLocal4)) {
+          Store (procFindPciCapability (Add (varBdfLocal1, varFunctionLocal5), 0x10), varCapLocal2)
+          if (LNotEqual (varCapLocal2, 0)) {
+            procPciDwordRMW (varBdfLocal1, Add (varCapLocal2, 0x08), Not (0x000000E0), varMaxPayloadLocal3)
+          }
+          Increment(varFunctionLocal5)
+        }
+      }
+    }
+    Store ("PcieSetMaxPayload Exit", Debug)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Clear Max_Payload_Size
+   *
+   *  Arg0 - Port Index
+   */
+   Method (procPcieClearMaxPayload, 1, Serialized) {
+
+   // Local variable usage
+   // varPortBdfLocal0 - Address of root port config space
+   // varPortCapLocal1 - Offset of root port PCIe Capabilities
+
+    Store ("PcieClearMaxPayload Enter", Debug)
+
+    // Get Port BDF from Port Index
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal0)
+    Store (procFindPciCapability (varPortBdfLocal0, 0x10), varPortCapLocal1)
+    if (LNotEqual (varPortCapLocal1, 0)) {
+      // Set the root port Max_Payload_Size to default = 0x0
+      procPciDwordRMW (varPortBdfLocal0, Add (varPortCapLocal1, 0x08), Not (0x000000E0), 0x0)
+
+    }
+    Store ("PcieClearMaxPayload Exit", Debug)
+  }
+#endif
+
+#ifdef  PCIE_CLKPM_SUPPORT
+    Method  (procPcieClkPmConfigure, 1, Serialized) {
+      Store ("PcieClkPmConfigure Enter", Debug)
+      Store (procPcieGetPortInfo (Arg0), Local7)
+      Store (DerefOf (Index (Local7, DEF_OFFSET_CLK_PM_SUPPORT)), varTempLocal0)
+      if (LEqual (varTempLocal0, 0)) {
+        Store ("PcieClkPmConfigure Exit", Debug)
+        return (0)
+      }
+      // Get Port PCI address
+      Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+      Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal0)
+      // Get device BDf on secondary bus
+      And (varTempLocal0, 0xFF00,  varEndpointBdfLocal2)
+
+      Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal0)
+      Store (And (ShiftRight (varTempLocal0, 16), 0xFF),  varTempLocal0)
+      if (LNotEqual (And (varTempLocal0, 0x80), 0)) {
+        Store (0x7, varMaxFunctionLocal3)
+      } else {
+        Store (0x0, varMaxFunctionLocal3)
+      }
+      Store (0, varFunctionLocal4)
+      Store (0, varIsClkPmSupportedLocal5)
+      while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) {
+        //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+        Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6)
+        if (LEqual (varPcieCapabilityOffsetLocal6, 0)) {
+          Increment (varFunctionLocal4)
+          continue
+        }
+        // Found PCI capability
+        if (LNotEqual (And (procPciDwordRead (Or (varEndpointBdfLocal2, varFunctionLocal4), Add (varPcieCapabilityOffsetLocal6, 0xC)), ShiftLeft (1,18)), 0)) {
+          Store (1, varIsClkPmSupportedLocal5)
+        } else {
+          Store (0, varIsClkPmSupportedLocal5)
+          break
+        }
+        Increment (varFunctionLocal4)
+      }
+      if (LEqual (varIsClkPmSupportedLocal5, 0)) {
+        Store ("PcieClkPmConfigure Exit", Debug)
+        return (0)
+      }
+      Store (0, varFunctionLocal4)
+
+      while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal3)) {
+        //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+        Store (procFindPciCapability (Or (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieCapabilityOffsetLocal6)
+        if (LEqual (varPcieCapabilityOffsetLocal6, 0)) {
+          Increment (varFunctionLocal4)
+          continue
+        }
+        // Enable CLK PM Capability
+        procPciDwordRMW (Or (varEndpointBdfLocal2, varFunctionLocal4),  Add (varPcieCapabilityOffsetLocal6, 0x10), 0xffffffff, ShiftLeft (1, 8))
+        Increment (varFunctionLocal4)
+      }
+      Store ("PcieClkPmConfigure Exit", Debug)
+    }
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
new file mode 100644
index 0000000000..abe0cdd459
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibMmioData.esl
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe MMIO Base address
+   *
+   */
+
+  Name (
+    AD01,
+    0xE0000000
+  )
+
+  Alias (
+    AD01,
+    varPcieBase
+  )
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
new file mode 100644
index 0000000000..378c0392ef
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl
@@ -0,0 +1,289 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCI config register through MMIO
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Register offset
+   */
+  Method (procPciDwordRead, 2, Serialized) {
+    Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
+    Add (Arg1, Local0, Local0)
+    OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
+      Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
+      Offset (0x0),
+      varPciReg32, 32,
+      }
+    return (varPciReg32)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCI config register through MMIO
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Register offset
+   *  Arg2 - Value
+   */
+  Method (procPciDwordWrite, 3, Serialized) {
+    Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
+    Add (Arg1, Local0, Local0)
+    OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
+      Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
+      Offset (0x0),
+      varPciReg32, 32,
+      }
+    Store (Arg2, varPciReg32)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCI config register through MMIO
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Register offset
+   *  Arg2 - AND mask
+   *  Arg3 - OR mask
+   */
+  Method (procPciDwordRMW, 4, Serialized) {
+    Store (procPciDwordRead (Arg0, Arg1), Local0)
+    Or (And (Local0, Arg2), Arg3, Local0)
+    procPciDwordWrite (Arg0, Arg1, Local0)
+  }
+
+  Mutex(varPciePortAccessMutex, 0)
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Register offset
+   *
+   */
+  Method (procPciePortIndirectRegisterRead, 2, NotSerialized) {
+    Acquire(varPciePortAccessMutex, 0xFFFF)
+    Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+    procPciDwordWrite (Local0, 0xe0, Arg1)
+    Store (procPciDwordRead (Local0, 0xe4), Local0)
+    Release (varPciePortAccessMutex)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCIe port indirect register
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Register offset
+   *  Arg2 - Value
+   */
+  Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) {
+    Acquire(varPciePortAccessMutex, 0xFFFF)
+    Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+    procPciDwordWrite (Local0, 0xe0, Arg1)
+    procPciDwordWrite (Local0, 0xe4, Arg2)
+    Release (varPciePortAccessMutex)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Register offset
+   *  Arg2 - AND Mask
+   *  Arg3 - OR Mask
+   *
+   */
+  Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) {
+    Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0)
+    Or (And (Local0, Arg2), Arg3, Local0)
+    procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0)
+  }
+  Mutex(varHostAccessMutex, 0)
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - BDF
+   *  Arg1 - Register offset
+   *  Arg2 - Register address
+   *
+   */
+  Method (procIndirectRegisterRead, 3, NotSerialized) {
+    Acquire(varHostAccessMutex, 0xFFFF)
+    procPciDwordWrite (Arg0, Arg1, Arg2)
+    Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0)
+    Release(varHostAccessMutex)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write PCIe port indirect register
+   *
+   *  Arg0 - BDF
+   *  Arg1 - Register offset
+   *  Arg2 - Register address
+   *  Arg3 - Value
+   */
+  Method (procIndirectRegisterWrite, 4, NotSerialized) {
+    Acquire(varHostAccessMutex, 0xFFFF)
+    procPciDwordWrite (Arg0, Arg1, Arg2)
+    procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3)
+    Release(varHostAccessMutex)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read Modify Write indirect registers
+   *
+   *  Arg0 - BDF
+   *  Arg1 - Register Offset
+   *  Arg2 - Register Address
+   *  Arg3 - AND Mask
+   *  Arg4 - OR Mask
+   *
+   */
+  Method (procIndirectRegisterRMW, 5, NotSerialized) {
+    Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0)
+    Or (And (Local0, Arg3), Arg4, Local0)
+    procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Find Pci Capability
+   *
+   *  Arg0 - PCI address Bus/device/func
+   *  Arg1 - Capability id
+   */
+  Method (procFindPciCapability, 2, NotSerialized) {
+    Store (0x34, Local1)
+    if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) {
+      // Device not present
+      return  (0)
+    }
+    Store (1, Local0)
+    while (LEqual (Local0, 1)) {
+      Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1)
+      if (LEqual (Local1, 0)) {
+        break
+      }
+      if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) {
+        Store (0, Local0)
+      } else {
+        Increment (Local1)
+      }
+    }
+    return (Local1)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *
+   *
+   *  Arg0  - Aspm
+   *  Arg1  - 0: Read, 1: Write
+   */
+  Method (procPcieSbAspmControl, 2, Serialized) {
+      // Create an opregion for PM IO Registers
+      OperationRegion (PMIO, SystemIO, 0xCD6, 0x2)
+      Field (PMIO, ByteAcc, NoLock, Preserve)
+      {
+        PMRI, 8,
+        PMRD, 8
+      }
+      IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve)
+      {
+        Offset(0xE0),               // IO Base address of A-Link Express/ A-Link Bridge register
+        ABAR, 32,
+      }
+    OperationRegion (ACFG, SystemIO, ABAR, 0x8)
+      Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA
+      {
+        ABIX, 32,
+        ABDA, 32
+      }
+
+    Store (0, Local0)
+    if (LEqual (Arg1, 0)) {
+      Store (0x80000068, ABIX)
+      Store (ABDA, Local0)
+      return (Local0)
+    } else {
+      Store (0x80000068, ABIX)
+      Store (ABDA, Local0)
+      Or (And (Local0, 0xfffffffc), Arg0, Local0)
+      Store (Local0, ABDA)
+    }
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
new file mode 100644
index 0000000000..228c839b3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPortData.esl
@@ -0,0 +1,109 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe port info
+   *
+   */
+
+  Name (
+    AD07,
+    Package () {
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev2
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev3
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev4
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev5
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev6
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev7
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev8
+      Buffer () {0,0,0,0,0,0,0,0,0,0},    //dev9
+    }
+  )
+
+  Alias (
+    AD07,
+    varPortInfo
+  )
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *
+   *
+   *  Arg0 	- Port ID
+   *  Retval	- buffer that represent port data set
+   */
+  Method (procPcieGetPortInfo, 1, NotSerialized) {
+    return (DeRefOf (Index (varPortInfo, Arg0)))
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
new file mode 100644
index 0000000000..bedd41cddd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
@@ -0,0 +1,825 @@
+/**
+* @file
+*
+* ALIB PSPP ASL library
+*
+*
+*
+* @xrefitem bom "File Content Label" "Release Content"
+* @e project:     AGESA
+* @e sub-project: GNB
+* @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+*
+*/
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe Performance Policy
+   *
+   *  varPsppPolicy - 0 Disabled
+   *                  1 Performance
+   *                  2 Balance Hight
+   *                  3 Balance Low
+   *                  4 Power Saving
+   */
+  Name (
+    AD02,
+    0x0
+  )
+
+  Alias (
+    AD02,
+    varPsppPolicy
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  GEN2 VID
+   *
+   */
+
+  Name (
+    AD03,
+    0x0
+  )
+
+  Alias (
+    AD03,
+    varGen2Vid
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  GEN1 VID
+   *
+   */
+  Name (
+    AD04,
+    0x0
+  )
+
+  Alias (
+    AD04,
+    varGen1Vid
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Boot VID
+   *
+   */
+
+  Name (
+    AD05,
+    0x0
+  )
+
+  Alias (
+    AD05,
+    varBootVid
+  )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Max Port link speed
+   *
+   */
+  Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  Alias (AD06, varMaxLinkSpeed)
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Max link speed that was changed during runtime (hotplug for instance)
+   *
+   */
+
+  Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  Alias (AD08,  varOverrideLinkSpeed)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Policy service status
+   *
+   *  varPsppPolicyService - 0 (Stopped)
+   *                         1 (Started)
+   */
+
+  Name (varPsppPolicyService, 0x0 )
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  AC DC state
+   *
+   *  varPsppAcDcState - 0 (AC)
+   *                     1 (DC)
+   */
+
+  Name (varPsppAcDcState, 0x0)
+  Name (varPsppAcDcOverride, 0x1)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Client ID array
+   *
+   */
+
+  Name (varPsppClientIdArray,
+    Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+    )
+
+  Name (varDefaultPsppClientIdArray,
+    Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+    )
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  LInk speed requested by device driver
+   *
+   */
+
+  Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Current link speed
+   *
+   */
+  Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+  Alias (AD09,  varCurrentLinkSpeed)
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Template link speed
+   *
+   */
+  Name (
+    varGen1LinkSpeedTemplate,
+    Package () {
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1,
+    DEF_LINK_SPEED_GEN1
+    })
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Template link speed
+   *
+   */
+  Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 })
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Global varuable
+   *
+   */
+  Name (varPortIndex, 0)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Sclk VID that was changed during runtime
+   *
+   */
+
+  Name (AD10, Package () {0x00, 0x00, 0x00, 0x00})
+
+  Alias (AD10,  varSclkVid)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Report AC/DC state
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppReportAcDsState, 1, Serialized) {
+    Store ("PsppReportAcDsState Enter", Debug)
+
+    Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1)
+    Store (Concatenate ("  AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug)
+
+    Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0)
+    Store (varArgAcDcStateLocal1, varPsppAcDcState)
+
+    Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2)
+    Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3)
+    procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3))
+
+
+    if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) {
+      Store ("  No action. [AC/DC state not changed]", Debug)
+      Store ("PsppReportAcDsState Exit", Debug)
+      return (0)
+    }
+
+    // Disable both APM (boost) and PDM flow on DC event enable it on AC.
+    procApmPdmActivate(varPsppAcDcState)
+
+    // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service.
+    if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN1)
+#endif
+    }
+    if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+      Store ("  No action. [Policy type]", Debug)
+      Store ("PsppReportAcDsState Exit", Debug)
+      return (0)
+    }
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+      Store ("  No action. [Policy not started]", Debug)
+      Store ("PsppReportAcDsState Exit", Debug)
+      return (0)
+    }
+    procApplyPsppState ()
+    Store ("PsppReportAcDsState Exit", Debug)
+    return (0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe Performance Request
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppPerformanceRequest, 1, NotSerialized) {
+    Store (procPsppProcessPerformanceRequest (Arg0), Local7)
+    Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0)
+    if (LNotEqual (varReturnStatusLocal0, 2)) {
+      return (Local7)
+    }
+    procApplyPsppState ()
+    return (Local7)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PCIe Performance Request
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppProcessPerformanceRequest, 1, NotSerialized) {
+    Store ("PsppProcessPerformanceRequest Enter", Debug)
+    Name (varClientBus, 0)
+    Store (0, varPortIndex)
+    Store (Buffer (10) {}, Local7)
+    CreateWordField (Local7, 0x0, varReturnBufferLength)
+    Store (3, varReturnBufferLength)
+    CreateByteField (Local7, 0x2, varReturnStatus)
+    Store (1, varReturnStatus)
+
+    if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+      Store ("  No action. [Policy type]", Debug)
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+      Store ("  No action. [Policy not started]", Debug)
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+    CreateWordField (Arg0, 0x2, varClientId)
+    CreateWordField (Arg0, 0x4, varValidFlag)
+    CreateWordField (Arg0, 0x6, varFlag)
+    CreateByteField (Arg0, 0x8, varRequestType)
+    CreateByteField (Arg0, 0x9, varRequestData)
+
+    Store (Concatenate ("  Client ID   : ", ToHexString (varClientId), varStringBuffer), Debug)
+    Store (Concatenate ("  Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug)
+    Store (Concatenate ("  Flags       : ", ToHexString (varFlag), varStringBuffer), Debug)
+    Store (Concatenate ("  Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug)
+    Store (Concatenate ("  Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug)
+
+
+    And (ShiftRight (varClientId, 8), 0xff, varClientBus)
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) {
+        Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
+        And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2)             //Local2 Port Subordinate Bus number
+        And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1)                //Local1 Port Secondary Bus number
+        if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) {
+          break
+        }
+      }
+      Increment (varPortIndex)
+    }
+    if (LGreater (varPortIndex, varMaxPortIndexNumber)) {
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+
+    Store (Concatenate ("  Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug)
+
+    if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) {
+      Store (varClientId, Index (varPsppClientIdArray, varPortIndex))
+    } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) {
+      // We already have registered client
+      Store ("  No action. [Unsupported request]", Debug)
+      Store ("PsppPerformanceRequest Exit", Debug)
+      return (Local7)
+    }
+    Store (0, Index (varLowVoltageRequest, varPortIndex))
+    if (LEqual (varRequestData, 0)) {
+      Store (0x0000, Index (varPsppClientIdArray, varPortIndex))
+    }
+    if (LEqual (varRequestData, 1)) {
+      Store (1, Index (varLowVoltageRequest, varPortIndex))
+    }
+    if (LEqual (varRequestData, 2)) {
+      Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex))
+    }
+    if (LEqual (varRequestData, 3)) {
+      Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex))
+    }
+    if (LEqual (And (varValidFlag, varFlag), 0x1)) {
+      Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex))
+    }
+    Store (2, varReturnStatus)
+    Store ("PsppProcessPerformanceRequest Exit", Debug)
+    return (Local7)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PSPP Start/Stop Management Request
+   *
+   *  Arg0 - Data Buffer
+   */
+
+  Method (procChecPortAllocated, 1, Serialized) {
+    if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) {
+      return (DEF_PORT_NOT_ALLOCATED)
+    }
+    return (DEF_PORT_ALLOCATED)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  PSPP Start/Stop Management Request
+   *
+   *  Arg0 - Data Buffer
+   */
+  Method (procPsppControl, 1, Serialized) {
+    Store ("PsppControl Enter", Debug)
+    Store (Buffer (256) {}, Local7)
+    Store (3, Index (Local7, 0x0)) // Return Buffer Length
+    Store (0, Index (Local7, 0x1)) // Return Buffer Length
+    Store (0, Index (Local7, 0x2)) // Return Status
+
+    Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService)
+
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0)
+
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) {
+      if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) {
+      // Policy already started
+        Store (" No action. [Policy already started]", Debug)
+        Store ("PsppControl Exit", Debug)
+        return (Local7)
+      }
+      Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0)
+    }
+    if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+      if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) {
+        // Policy already stopped
+        Store ("  No action. [Policy already stopped]", Debug)
+        Store ("PsppControl Exit", Debug)
+        return (Local7)
+      }
+      And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0)
+    }
+    Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0)
+    procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0)
+
+    procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray))
+
+    // Reevaluate APM/PDM state here on S3 resume while staying on DC.
+    procApmPdmActivate(varPsppAcDcState)
+
+    // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service.
+    if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN1)
+#endif
+    }
+    //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage
+    if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
+      // Load default speed capability state
+      if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) {
+        procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed))
+        Store (0, varPortIndex)
+        while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+          if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) {
+            Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex))
+          }
+          Increment (varPortIndex)
+        }
+      } else {
+        procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed))
+#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT
+       Store (DeRefOf (Index (varMaxLinkSpeed, DEF_SB_PORT_INDEX)),Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX))
+       //Store (DEF_LINK_SPEED_GEN2, Index (varCurrentLinkSpeed, DEF_SB_PORT_INDEX))
+#endif
+
+      }
+      procApplyPsppState ()
+    }
+    Store ("PsppControl Exit", Debug)
+    return (Local7)
+  }
+
+  Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Evaluate PCIe speed on all links according to PSPP state and client requests
+   *
+   *
+   *
+   */
+  Method (procApplyPsppState, 0, Serialized) {
+    Store ("ApplyPsppState Enter", Debug)
+    Store (0, varPortIndex)
+
+    procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed))
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) {
+        Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex))
+      }
+      Increment (varPortIndex)
+    }
+    if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) {
+      procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed))
+    }
+    if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) {
+      // Set GEN2 voltage
+      Store ("Set GEN2 VID", Debug)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN2)
+#endif
+      procPcieSetVoltage (DEF_LINK_SPEED_GEN2, 1)
+//      procPcieAdjustPll (DEF_LINK_SPEED_GEN2)
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2)
+    }
+    Store (0, varPortIndex)
+    while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+      if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) {
+        Increment (varPortIndex)
+        continue
+      }
+      Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0)
+      Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2)
+      if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) {
+        Increment (varPortIndex)
+        continue
+      }
+      Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex))
+      procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2)
+      Increment (varPortIndex)
+    }
+    if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) {
+      // Set GEN1 voltage
+      Store ("Set GEN1 VID", Debug)
+      procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1)
+//      procPcieAdjustPll (DEF_LINK_SPEED_GEN1)
+      procPcieSetVoltage (DEF_LINK_SPEED_GEN1, 0)
+#ifdef ALTVDDNB_SUPPORT
+      procNbAltVddNb (DEF_LINK_SPEED_GEN1)
+#endif
+    }
+#ifdef PHY_SPEED_REPORT_SUPPORT
+    procReportPhySpeedCap ()
+#endif
+    Store ("ApplyPsppState Exit", Debug)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCI config register
+   *
+   *  Arg0 - Port Index
+   *
+   */
+  Method (procGetPortRequestedCapability, 1) {
+    Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0)
+    Store (procPsppGetAcDcState(), varAcDcStateLocal1)
+    if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
+      if (LOr (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
+        // Default policy cap to GEN1
+        Store (DEF_LINK_SPEED_GEN1, varCurrentSpeedLocal0)
+      }
+#ifdef SBLINK_BALANCE_LOW_GEN2_SUPPORT
+      if (LAnd (LEqual (varAcDcStateLocal1, DEF_PSPP_STATE_AC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
+        if (LEqual (Arg0, DEF_SB_PORT_INDEX)) {
+          Store (DEF_LINK_SPEED_GEN2, varCurrentSpeedLocal0)
+        }
+      }
+#endif
+      if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) {
+        Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), varCurrentSpeedLocal0)
+      }
+    } else {
+      Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), varCurrentSpeedLocal0)
+    }
+    Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)),varMaxLinkSpeedLocal2)
+    if (LLess (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0)) {
+      Store (varMaxLinkSpeedLocal2, varCurrentSpeedLocal0)
+    }
+
+
+    return (varCurrentSpeedLocal0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Set capability and speed
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - Link speed
+   */
+  Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) {
+    Store ("SetPortCapabilityAndSpeed Enter", Debug)
+    Store (Concatenate ("  Port Index : ", ToHexString (Arg0), varStringBuffer), Debug)
+    Store (Concatenate ("  Speed      : ", ToHexString (Arg1), varStringBuffer), Debug)
+
+    //UnHide UMI port
+    if (LEqual (Arg0, 6)) {
+      procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40);
+    }
+
+    procPcieSetLinkSpeed (Arg0, Arg1)
+
+    // Programming for LcInitSpdChgWithCsrEn
+    if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
+      // Registered port, LcInitSpdChgWithCsrEn = 0.
+      procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0)
+    } else {
+      procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000)
+    }
+
+    // Determine port PCI address and check port present
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+    And (procPciePortIndirectRegisterRead (Arg0, 0xA5), 0x3f, varPortPresentLocal3)
+    procPciePortIndirectRegisterWrite (Arg0, 0x1, varPortPresentLocal3)
+    if (LGreaterEqual (varPortPresentLocal3, 0x10)) {
+      procDisableAndSaveAspm (Arg0)
+      Store (1, Local2)
+      while (Local2) {
+        //retrain port
+        procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20)
+        Sleep (30)
+        while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) {
+          Sleep (10)
+        }
+        Store (0, Local2)
+        if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) {
+          //Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentLinkSpeedLocal4)
+          if (LNotEqual (procPciePortGetCurrentLinkSpeed (Arg0), DEF_LINK_SPEED_GEN1)) {
+            Store (1, Local2)
+          }
+        }
+      }
+      procRestoreAspm (Arg0)
+    } else {
+      Store ("  Device not present. Set capability and speed only", Debug)
+    }
+    //Hide UMI port
+    if (LEqual (Arg0, 6)) {
+      procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00);
+    }
+    Store ("SetPortCapabilityAndSpeed Exit", Debug)
+  }
+
+  Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
+  Name (varPcieLinkControlOffset, 0)
+  Name (varPcieLinkControlData, 0)
+  Name (varPcieRcControlData, 0)
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Disable and save ASPM state
+   *
+   *  Arg0 - Port Index
+   */
+  Method (procDisableAndSaveAspm, 1, Serialized) {
+    Store (0, varPcieLinkControlOffset)
+    Store (0, varPcieLinkControlData)
+
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+    if (LEqual (Arg0, 6)) {
+      Store ("  Disable SB ASPM", Debug)
+      Store (procPcieSbAspmControl (0, 0),  Index (varPcieLinkControlArray, 0))
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug)
+      procPcieSbAspmControl (0, 1)
+      return (0)
+    }
+
+    Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 8), 0xFF),  varTempLocal3)
+
+    Store (Concatenate ("  Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2)
+    Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 16), 0xFF),  varTempLocal3)
+
+    Store (Concatenate ("  EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    if (LNotEqual (And (varTempLocal3, 0x80), 0)) {
+      Store (0x7, varMaxFunctionLocal0)
+    } else {
+      Store (0x0, varMaxFunctionLocal0)
+    }
+    Store (0, varFunctionLocal4)
+    while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) {
+      //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+      Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset)
+      if (LEqual (varPcieLinkControlOffset, 0)) {
+        Increment (varFunctionLocal4)
+        continue
+      }
+      Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
+
+      Store (Concatenate ("  Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug)
+      Store (Concatenate ("  PcieLinkControl register offset  : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug)
+      // Save ASPM on EP
+      Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData)
+      Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4))
+
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug)
+
+      procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00)
+      Store ("Disable ASPM on EP Complete!!", Debug)
+      Increment (varFunctionLocal4)
+    }
+    //Disable ASPM on RC
+    Store (procPciDwordRead (varPortBdfLocal1, 0x68), varPcieRcControlData)
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), 0x00)
+  }
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Restore ASPM
+   *
+   *  Arg0 - Port Index
+   */
+   Method (procRestoreAspm, 1, Serialized) {
+
+    Store (0, varPcieLinkControlOffset)
+    Store (0, varPcieLinkControlData)
+
+
+    // Restore SB ASPM
+    if (LEqual (Arg0, 6)) {
+      Store ("  Restore SB ASPM", Debug)
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug)
+      procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1)
+      return (0)
+    }
+    Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+    // Restore EP ASPM
+    Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 8), 0xFF),  varTempLocal3)
+    // Restore ASPM on RC
+    procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000003), And (varPcieRcControlData, 0x3))
+
+    Store (Concatenate ("  Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2)
+    Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3)
+    Store (And (ShiftRight (varTempLocal3, 16), 0xFF),  varTempLocal3)
+
+    Store (Concatenate ("  EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+    if (LNotEqual (And (varTempLocal3, 0x80), 0)) {
+      Store (0x7, varMaxFunctionLocal0)
+    } else {
+      Store (0x0, varMaxFunctionLocal0)
+    }
+    Store (0, varFunctionLocal4)
+    while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) {
+      //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+      Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset)
+      if (LEqual (varPcieLinkControlOffset, 0)) {
+        Increment (varFunctionLocal4)
+        continue
+      }
+      Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
+
+      Store (Concatenate ("  Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug)
+      Store (Concatenate ("  Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug)
+      Store (Concatenate ("  PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug)
+
+      procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4)))
+      Increment (varFunctionLocal4)
+    }
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Request VID
+   *
+   *  Arg0 - Port Index
+   *  Arg1 - PCIe speed
+   */
+
+  Method (procPcieSetLinkSpeed, 2) {
+    Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+    if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) {
+      procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21)
+      procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0)
+    } else {
+      procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001)
+      procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2)
+    }
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Ref Source Pckage
+   *  Arg1 - Ref to Destination Package
+   *
+   */
+  Method (procCopyPackage, 2, NotSerialized) {
+
+    Store (SizeOf (Arg0), Local1)
+    Store (0, Local0)
+    While (LLess (Local0, Local1)) {
+      Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0))
+      Increment (Local0)
+    }
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read PCIe port indirect register
+   *
+   *  Arg0 - Ref Source Pckage
+   *  Arg1 - Ref to Destination Package
+   *
+   */
+  Method (procPsppGetAcDcState, 0 , NotSerialized) {
+    Return (And (varPsppAcDcState, varPsppAcDcOverride))
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
new file mode 100644
index 0000000000..a88b5d9e7a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c
@@ -0,0 +1,445 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe link ASPM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "OptionGnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "PcieAspmBlackList.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS GnbBuildOptions;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  PCIE_ASPM_TYPE          Aspm;
+  PCI_ADDR                DownstreamPort;
+} PCIE_ASPM_DATA;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieAspmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+
+SCAN_STATUS
+PcieAspmCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+VOID
+PcieAspmEnableOnLink (
+  IN       PCI_ADDR                 Downstream,
+  IN       PCI_ADDR                 Upstream,
+  IN       PCIE_ASPM_TYPE           Aspm,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+PCIE_ASPM_TYPE
+PcieAspmGetPmCapability (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable PCIE Advance state power management
+ *
+ *
+ *
+ * @param[in] DownstreamPort      PCI Address of the downstream port
+ * @param[in] Aspm                ASPM type
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+VOID
+PcieLinkAspmEnable (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       PCIE_ASPM_TYPE          Aspm,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_ASPM_DATA PcieAspmData;
+  PcieAspmData.Aspm = Aspm;
+  PcieAspmData.ScanData.StdHeader = StdHeader;
+  PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieAspmCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_ASPM_DATA          *PcieAspmData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieAspmCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  PcieAspmData = (PCIE_ASPM_DATA *) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    PcieAspmData->DownstreamPort = Device;
+    //PcieExitLatencyData->LinkCount++;
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
+    //PcieExitLatencyData->LinkCount--;
+    break;
+  case  PcieDeviceUpstreamPort:
+    PcieAspmEnableOnLink (
+      PcieAspmData->DownstreamPort,
+      Device,
+      PcieAspmData->Aspm,
+      ScanData->StdHeader
+      );
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    PcieAspmEnableOnLink (
+      PcieAspmData->DownstreamPort,
+      Device,
+      PcieAspmData->Aspm,
+      ScanData->StdHeader
+      );
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  default:
+    break;
+  }
+  return ScanStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set  ASMP State on PCIe device function
+ *
+ *
+ *
+ * @param[in] Function    PCI address of function.
+ * @param[in] Aspm                Aspm capability to enable
+ * @param[in] StdHeader           Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmEnableOnFunction (
+  IN       PCI_ADDR             Function,
+  IN       PCIE_ASPM_TYPE       Aspm,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8       PcieCapPtr;
+  PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
+      AccessS3SaveWidth8,
+      (UINT32)~(BIT0 | BIT1),
+      Aspm,
+      StdHeader
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set ASMP State on all function of PCI device
+ *
+ *
+ *
+ * @param[in] Device    PCI address of device.
+ * @param[in] Aspm                Aspm capability to enable
+ * @param[in] StdHeader           Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC VOID
+PcieAspmEnableOnDevice (
+  IN       PCI_ADDR             Device,
+  IN       PCIE_ASPM_TYPE       Aspm,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8 MaxFunc;
+  UINT8 CurrentFunc;
+  MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
+  for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+    Device.Address.Function = CurrentFunc;
+    if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
+      PcieAspmEnableOnFunction (Device, Aspm, StdHeader);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Enable ASPM on link
+ *
+ *
+ *
+ * @param[in] Downstream          PCI Address of downstrteam port
+ * @param[in] Upstream            PCI Address of upstream port
+ * @param[in] Aspm                Aspm capability to enable
+ * @param[in] StdHeader           Standard configuration header
+ */
+
+VOID
+PcieAspmEnableOnLink (
+  IN       PCI_ADDR                 Downstream,
+  IN       PCI_ADDR                 Upstream,
+  IN       PCIE_ASPM_TYPE           Aspm,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  PCIe_LINK_ASPM  LinkAsmp;
+  PCIE_ASPM_TYPE  DownstreamCap;
+  PCIE_ASPM_TYPE  UpstreamCap;
+  LinkAsmp.DownstreamPort = Downstream;
+  DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader);
+  LinkAsmp.UpstreamPort = Upstream;
+  UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader);
+  LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1;
+  LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm;
+  LinkAsmp.RequestedAspm = Aspm;
+  if ((UpstreamCap & Aspm & AspmL0s) != 0) {
+    LinkAsmp.UpstreamAspm |= AspmL0s;
+  }
+  if ((DownstreamCap & Aspm & AspmL0s) != 0) {
+    LinkAsmp.DownstreamAspm |= AspmL0s;
+  }
+  if (GnbBuildOptions.PcieAspmBlackListEnable == 1) {
+    PcieAspmBlackListFeature (&LinkAsmp, StdHeader);
+  }
+  //AgesaPcieLinkAspm (&LinkAsmp, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  Set ASPM [%d]  for Device = %d:%d:%d\n",
+    (LinkAsmp.UpstreamAspm) ,
+    LinkAsmp.UpstreamPort.Address.Bus,
+    LinkAsmp.UpstreamPort.Address.Device,
+    LinkAsmp.UpstreamPort.Address.Function
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "  Set ASPM [%d]  for Device = %d:%d:%d\n",
+    (LinkAsmp.DownstreamAspm) ,
+    LinkAsmp.DownstreamPort.Address.Bus,
+    LinkAsmp.DownstreamPort.Address.Device,
+    LinkAsmp.DownstreamPort.Address.Function
+    );
+  // Disable ASPM  Upstream component
+  PcieAspmEnableOnDevice (Upstream, AspmDisabled, StdHeader);
+  // Enable  ASPM  Donstream component
+  PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader);
+  // Enable  ASPM  Upstream component
+  PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader);
+}
+
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Port/Endpoint ASMP capability
+ *
+ *
+ *
+ * @param[in] Device      PCI address of downstream port
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    PCIE_ASPM_TYPE
+ */
+ /*----------------------------------------------------------------------------------------*/
+PCIE_ASPM_TYPE
+PcieAspmGetPmCapability (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  UINT8   PcieCapPtr;
+  UINT32  Value;
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr == 0) {
+    return 0;
+  }
+  GnbLibPciRead (
+    Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
+    AccessWidth32,
+    &Value,
+    StdHeader
+    );
+  return (Value >> 10) & 3;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAspmPortInitCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled &&
+      !PcieConfigIsSbPcieEngine (Engine) &&
+      PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PcieLinkAspmEnable (
+      Engine->Type.Port.Address,
+      Engine->Type.Port.PortData.LinkAspm,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Interface to enable Clock Power Managment
+ *
+ *
+ *
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    AGESA_STATUS
+ */
+ /*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieAspmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Enter\n");
+  AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieAspmPortInitCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieAspmInterface Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h
new file mode 100644
index 0000000000..16bf03ec4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAspm/PcieAspm.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe link ASPM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPM_H_
+#define _PCIEASPM_H_
+
+VOID
+PcieLinkAspmEnable (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       PCIE_ASPM_TYPE          Aspm,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+VOID
+PcieAspmEnableOnFunction (
+  IN       PCI_ADDR                Function,
+  IN       PCIE_ASPM_TYPE          Aspm,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
new file mode 100644
index 0000000000..d268915b5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c
@@ -0,0 +1,353 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Clock Power Managment
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "PcieClkPm.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable Clock Power Managment on function of the device
+ *
+ *
+ *
+ * @param[in] Function     PCI address of function.
+ * @param[in] StdHeader    Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC VOID
+PcieClkPmEnableOnFunction (
+  IN       PCI_ADDR             Function,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8       PcieCapPtr;
+  PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER),
+      AccessS3SaveWidth32,
+      (UINT32)~(BIT8),
+      BIT8,
+      StdHeader
+      );
+  }
+}
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * check capability of intire device including its functions
+ *
+ *
+ *
+ * @param[in] Device      PCI address of downstream port
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    TRUE - Device support Clock Power Managment
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC BOOLEAN
+PcieClkPmCheckDeviceCapability (
+  IN       PCI_ADDR                 Device,
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+
+  UINT8   MaxFunc;
+  UINT8   CurrentFunc;
+  UINT8   PcieCapPtr;
+  UINT32  Value;
+
+  MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
+
+  for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+    Device.Address.Function = CurrentFunc;
+    if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
+      PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
+      if (PcieCapPtr == 0) {
+        return FALSE;
+      }
+      GnbLibPciRead (
+        Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
+        AccessWidth32,
+        &Value,
+        StdHeader
+        );
+      if ((Value & BIT18) == 0) {
+        return FALSE;
+      }
+    }
+  }
+  return TRUE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Clock power managment on device
+ *
+ *
+ *
+ * @param[in] Device        PCI address of device.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+STATIC VOID
+PcieClkPmEnableOnDevice (
+  IN       PCI_ADDR             Device,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8 MaxFunc;
+  UINT8 CurrentFunc;
+  if (PcieClkPmCheckDeviceCapability (Device, StdHeader)) {
+    MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
+    for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+      Device.Address.Function = CurrentFunc;
+      if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
+       IDS_HDT_CONSOLE (GNB_TRACE, "  Enable Clock Power Managment for Device = %d:%d:%d\n",
+        Device.Address.Bus,
+        Device.Address.Device,
+        Device.Address.Function
+        );
+        PcieClkPmEnableOnFunction (Device, StdHeader);
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+STATIC SCAN_STATUS
+PcieClkPmCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_DEVICE_TYPE        DeviceType;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieClkPmCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, ScanData);
+    break;
+  case  PcieDeviceUpstreamPort:
+    PcieClkPmEnableOnDevice (Device, ScanData->StdHeader);
+    GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
+    GnbLibPciScanSecondaryBus (Device, ScanData);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    PcieClkPmEnableOnDevice (Device, ScanData->StdHeader);
+    ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
+    break;
+  default:
+    break;
+  }
+  return ScanStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Confiugure Clock Power Managment
+ *
+ *
+ *
+ *
+ * @param[in]       DownstreamPort       Downstream port PCI address
+ * @param[in]       StdHeader            Standard configuration header
+ *
+ */
+
+VOID
+STATIC
+PcieClkPmPortInitConfigure (
+  IN       PCI_ADDR               DownstreamPort,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GNB_PCI_SCAN_DATA  ScanData;
+  ScanData.StdHeader = StdHeader;
+  ScanData.GnbScanCallback = PcieClkPmCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &ScanData);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieClkPmPortInitCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.MiscControls.ClkPmSupport == 0x1 &&
+      !PcieConfigIsSbPcieEngine (Engine) &&
+      PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    PcieClkPmPortInitConfigure (
+      Engine->Type.Port.Address,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Interface to enable Clock Power Managment
+ *
+ *
+ *
+ * @param[in] StdHeader   Standard configuration header
+ *
+ * @retval    AGESA_STATUS
+ */
+ /*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieClkPmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Enter\n");
+  AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (AgesaStatus == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieClkPmPortInitCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieClkPmInterface Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h
new file mode 100644
index 0000000000..3d14ac8abc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe link ASPM
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIECLKPM_H_
+#define _PCIECLKPM_H_
+
+AGESA_STATUS
+PcieClkPmInterface (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
new file mode 100644
index 0000000000..4b354caba4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c
@@ -0,0 +1,162 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate/manes GNB/PCIe configuration
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get GNB handle
+ *
+ *
+ * @param[in]       StdHeader       Standard configuration header
+ */
+GNB_HANDLE *
+GnbGetHandle (
+  IN      AMD_CONFIG_PARAMS                 *StdHeader
+  )
+{
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  GNB_HANDLE            *GnbHandle;
+  AGESA_STATUS          Status;
+  GnbHandle = NULL;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    GnbHandle = (GNB_HANDLE *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  }
+  return GnbHandle;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get GNB socket ID
+ *
+ *
+ * @param[in]       GnbHandle       Gnb handle
+ */
+UINT8
+GnbGetSocketId (
+  IN      GNB_HANDLE                        *GnbHandle
+  )
+{
+  return PcieConfigGetParentComplex (GnbHandle)->SocketId;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Get PCI_ADDR of GNB
+ *
+ *
+ * @param[in] Handle          Pointer to GNB_HANDLE
+ * @retval    PCI_ADDR        PCI_ADDR of device
+ */
+
+PCI_ADDR
+GnbGetHostPciAddress (
+  IN      GNB_HANDLE          *Handle
+  )
+{
+  ASSERT (Handle != NULL);
+  return Handle->Address;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
new file mode 100644
index 0000000000..affaa8c0ab
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBHANDLELIB_H_
+#define _GNBHANDLELIB_H_
+
+
+GNB_HANDLE *
+GnbGetHandle (
+  IN      AMD_CONFIG_PARAMS                 *StdHeader
+  );
+
+UINT8
+GnbGetSocketId (
+  IN      GNB_HANDLE                        *GnbHandle
+  );
+
+PCI_ADDR
+GnbGetHostPciAddress (
+  IN      GNB_HANDLE          *Handle
+ );
+
+
+#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY)
+
+#define GnbGetSiliconId(Handle) (Handle != NULL ? (Handle)->SiliconId : 0)
+#define GnbGetNodeId(Handle) (Handle != NULL ? (Handle)->NodeId : 0)
+
+#define GnbIsGnbConnectedToSb(Handle) (Handle != NULL ? ((Handle)->Address.AddressValue == 0x0) : FALSE)
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h
new file mode 100644
index 0000000000..9074aba624
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe configuration
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBPCIECONFIG_H_
+#define _GNBPCIECONFIG_H_
+
+#include "GnbPcie.h"
+#include "PcieConfigData.h"
+#include "PcieConfigLib.h"
+#include "GnbHandleLib.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
new file mode 100644
index 0000000000..febae7f986
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
@@ -0,0 +1,561 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "OptionGnb.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbFamServices.h"
+#include  "cpuServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "PcieMapTopology.h"
+#include  "PcieInputParser.h"
+#include  "PcieConfigLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PcieConfigAttachChild(P, C)  (P)->Child = (UINT16) ((UINT8 *) C - (UINT8 *) P);
+#define PcieConfigAttachParent(P, C) (C)->Parent = (UINT16) ((UINT8 *) C - (UINT8 *) P);
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+PcieConfigAttachComplexes (
+  IN  OUT   PCIe_COMPLEX_CONFIG             *Base,
+  IN  OUT   PCIe_COMPLEX_CONFIG             *New
+  );
+
+AGESA_STATUS
+PcieUpdateConfigurationData (
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+PCIe_COMPLEX_DESCRIPTOR *
+PcieConfigProcessUserConfig (
+  IN       PCIe_COMPLEX_DESCRIPTOR         *PcieComplexList,
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PcieConfigurationInit (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PcieConfigurationMap (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create internal PCIe configuration topology
+ *
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     AGESA_SUCCESS   Configuration data successfully allocated.
+ * @retval     AGESA_FATAL     Configuration data allocation failed.
+ */
+
+AGESA_STATUS
+PcieConfigurationInit (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  PCIe_SILICON_CONFIG   *Silicon;
+  UINT8                 SocketId;
+  UINTN                 CurrentComplexesDataLength;
+  UINTN                 ComplexesDataLength;
+  UINT8                 ComplexIndex;
+  VOID                  *Buffer;
+  ComplexesDataLength = 0;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n");
+  for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
+    if (IsProcessorPresent (SocketId, StdHeader)) {
+      Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
+      ASSERT (Status == AGESA_SUCCESS);
+      ComplexesDataLength += CurrentComplexesDataLength;
+    }
+  }
+  ComplexIndex = 0;
+  Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
+  ASSERT (Pcie != NULL);
+  if (Pcie != NULL) {
+    PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
+    PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY);
+    Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
+    for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
+      if (IsProcessorPresent (SocketId, StdHeader)) {
+        Pcie->ComplexList[ComplexIndex].SocketId = SocketId;
+        //Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration
+        PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header);
+        //Attach Comples to Pcie
+        PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
+        PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY);
+        PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
+        Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]);
+        while (Silicon != NULL) {
+          PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header);
+          GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader);
+          GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader);
+          Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY);
+        }
+
+        if (ComplexIndex > 0) {
+          PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]);
+        }
+        PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
+        Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength);
+        ComplexIndex++;
+      }
+    }
+  } else {
+    Status = AGESA_FATAL;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create internal PCIe configuration topology
+ *
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     AGESA_SUCCESS   Configuration data successfully allocated.
+ * @retval     AGESA_FATAL     Configuration data allocation failed.
+ */
+
+AGESA_STATUS
+PcieConfigurationMap (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_EARLY_PARAMS            *EarlyParamsPtr;
+  PCIe_COMPLEX_DESCRIPTOR     *PcieComplexList;
+  PCIe_PLATFORM_CONFIG        *Pcie;
+  PCIe_COMPLEX_CONFIG         *Complex;
+  PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor;
+  AGESA_STATUS                Status;
+  AGESA_STATUS                AgesaStatus;
+  UINTN                       Index;
+  UINTN                       NumberOfComplexes;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationMap Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader;
+  PcieComplexList = PcieConfigProcessUserConfig (EarlyParamsPtr->GnbConfig.PcieComplexList, StdHeader);
+  GNB_DEBUG_CODE (
+    if (PcieComplexList != NULL) {
+      PcieUserConfigConfigDump (PcieComplexList);
+    }
+  );
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
+    NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList);
+    while (Complex != NULL) {
+      for (Index = 0; Index < NumberOfComplexes; Index++) {
+        ComplexDescriptor = PcieInputParserGetComplexDescriptor (PcieComplexList, Index);
+        if (ComplexDescriptor->SocketId == Complex->SocketId) {
+          Status = PcieMapTopologyOnComplex (ComplexDescriptor, Complex, Pcie);
+          AGESA_STATUS_UPDATE (Status, AgesaStatus);
+        }
+      }
+      Complex = PcieLibGetNextDescriptor (Complex);
+    }
+  }
+  Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.CfgGnbLinkReceiverDetectionPooling;
+  Pcie->LinkL0Pooling = GnbBuildOptions.CfgGnbLinkL0Pooling;
+  Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.CfgGnbLinkGpioResetAssertionTime;
+  Pcie->LinkResetToTrainingTime = GnbBuildOptions.CfgGnbLinkResetToTrainingTime;
+  Pcie->GfxCardWorkaround = GfxWorkaroundEnable;
+  Pcie->TrainingExitState = LinkStateTrainingCompleted;
+  Pcie->TrainingAlgorithm = GnbBuildOptions.CfgGnbTrainingAlgorithm;
+  if ((UserOptions.CfgAmdPlatformType  & AMD_PLATFORM_MOBILE) != 0) {
+    Pcie->GfxCardWorkaround = GfxWorkaroundDisable;
+  }
+  Pcie->PsppPolicy =  EarlyParamsPtr->GnbConfig.PsppPolicy;
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader);
+  GNB_DEBUG_CODE (
+    PcieConfigDebugDump (Pcie);
+    );
+  HeapDeallocateBuffer (AMD_GNB_TEMP_DATA_HANDLE, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate global PCIe configuration data
+ *
+ *
+ *
+ * @param[in]  PcieComplexList User PCIe topology configuration
+ * @param[out] StdHeader       Standard configuration header
+ * @retval     Updated topology configuration
+ */
+PCIe_COMPLEX_DESCRIPTOR *
+PcieConfigProcessUserConfig (
+  IN       PCIe_COMPLEX_DESCRIPTOR         *PcieComplexList,
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  UINT32                    Node0SocketId;
+  UINT32                    Node0SiliconId;
+  UINTN                     NumberOfComplexes;
+  UINTN                     NumberOfPorts;
+  UINTN                     Index;
+  UINT16                    DescriptorLoLane;
+  UINT16                    DescriptorHiLane;
+  PCIe_COMPLEX_DESCRIPTOR   *ResultComplexConfig;
+  PCIe_COMPLEX_DESCRIPTOR   *SbComplexDescriptor;
+  PCIe_PORT_DESCRIPTOR      *SbPortDescriptor;
+  PCIe_PORT_DESCRIPTOR      DefaultSbPortDescriptor;
+  PCIe_ENGINE_DESCRIPTOR    *EngineDescriptor;
+  AGESA_STATUS              Status;
+  SbPortDescriptor = NULL;
+  GetSocketModuleOfNode (0, &Node0SocketId, &Node0SiliconId, StdHeader);
+  Status = PcieFmGetSbConfigInfo ((UINT8) Node0SocketId, &DefaultSbPortDescriptor, StdHeader);
+  if (Status == AGESA_UNSUPPORTED) {
+    return PcieComplexList;
+  }
+  if (PcieComplexList == NULL) {
+    // No complex descriptor for any silicon was provided
+    // 1. Create complex descriptor
+    // 2. Create SB port descriptor
+    // 3. Attach SB descriptor to complex descriptor created in step #1
+    ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear (
+                                                        AMD_GNB_TEMP_DATA_HANDLE,
+                                                        sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR),
+                                                        StdHeader
+                                                        );
+    SbComplexDescriptor = ResultComplexConfig;
+    SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR));
+    LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
+    SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+    // Attach post array to complex descriptor
+    SbComplexDescriptor->PciePortList = SbPortDescriptor;
+    SbComplexDescriptor->SocketId = Node0SocketId;
+    SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+  } else {
+    NumberOfComplexes = PcieInputParserGetNumberOfComplexes (PcieComplexList);
+    SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket (PcieComplexList, Node0SocketId);
+    if (SbComplexDescriptor == NULL) {
+      // No complex descriptor for silicon that have SB attached.
+      // 1. Create complex descriptor. Will be first one in the list
+      // 2. Create SB port descriptor
+      // 3. Attach SB descriptor to complex descriptor created in step #1
+      ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBufferAndClear (
+                                                          AMD_GNB_TEMP_DATA_HANDLE,
+                                                          (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR),
+                                                          StdHeader
+                                                          );
+      SbComplexDescriptor = ResultComplexConfig;
+      SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8 *) ResultComplexConfig + (NumberOfComplexes + 1) * sizeof (PCIe_COMPLEX_DESCRIPTOR));
+      LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
+      SbPortDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+      // Attach post array to complex descriptor
+      SbComplexDescriptor->PciePortList = SbPortDescriptor;
+      SbComplexDescriptor->SocketId = Node0SocketId;
+      SbComplexDescriptor->Flags |= DESCRIPTOR_TERMINATE_LIST;
+      LibAmdMemCopy (
+        (UINT8 *) ResultComplexConfig + sizeof (PCIe_COMPLEX_DESCRIPTOR),
+        PcieComplexList,
+        NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR),
+        StdHeader
+        );
+
+    } else {
+      // Complex descriptor that represent silicon that have SB attached exist
+      // 1. Determine if complex have descriptor for SB
+      // 2. Create new descriptor for SB if needed
+      NumberOfPorts = PcieInputParserGetLengthOfPcieEnginesList (SbComplexDescriptor);
+      ResultComplexConfig = (PCIe_COMPLEX_DESCRIPTOR *) GnbAllocateHeapBuffer (
+                                                          AMD_GNB_TEMP_DATA_HANDLE,
+                                                          NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + (NumberOfPorts + 1) * sizeof (PCIe_PORT_DESCRIPTOR),
+                                                          StdHeader
+                                                          );
+      // Copy complex descriptor array
+      LibAmdMemCopy (
+        ResultComplexConfig,
+        PcieComplexList,
+        NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR),
+        StdHeader
+        );
+      if (NumberOfPorts != 0) {
+        // Copy port descriptor array associated with complex with SB attached
+        LibAmdMemCopy (
+          (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR),
+          SbComplexDescriptor->PciePortList,
+          NumberOfPorts * sizeof (PCIe_PORT_DESCRIPTOR),
+          StdHeader
+          );
+        // Update SB complex pointer on in memory list
+        SbComplexDescriptor = PcieInputParserGetComplexDescriptorOfSocket ((PCIe_COMPLEX_DESCRIPTOR *) ResultComplexConfig, Node0SocketId);
+        // Attach port descriptor array to complex
+        SbComplexDescriptor->PciePortList = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR));
+        for (Index = 0; Index < NumberOfPorts; ++Index) {
+          EngineDescriptor = PcieInputParserGetEngineDescriptor (SbComplexDescriptor, Index);
+          if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+            DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+            DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+            if (DescriptorLoLane >= DefaultSbPortDescriptor.EngineData.StartLane && DescriptorLoLane <= DefaultSbPortDescriptor.EngineData.EndLane) {
+              SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) EngineDescriptor;
+            }
+          }
+        }
+      }
+      if (SbPortDescriptor == NULL) {
+        // No descriptor that represent SB where found, create new one, will be first one in list
+        SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR));
+        // Copy default config info
+        LibAmdMemCopy (SbPortDescriptor, &DefaultSbPortDescriptor, sizeof (PCIe_PORT_DESCRIPTOR), StdHeader);
+        // Reattach descriptor list to complex
+        SbComplexDescriptor->PciePortList = SbPortDescriptor;
+      } else {
+        // Move SB descriptor to be first one in array
+        LibAmdMemCopy (
+          (UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR),
+          SbPortDescriptor,
+          sizeof (PCIe_PORT_DESCRIPTOR),
+          StdHeader
+          );
+        // Disable original SB descriptor
+        SbPortDescriptor->EngineData.EngineType = PcieUnusedEngine;
+        //Update pointer to new SB descriptor
+        SbPortDescriptor = (PCIe_PORT_DESCRIPTOR *) ((UINT8*) ResultComplexConfig + NumberOfComplexes * sizeof (PCIe_COMPLEX_DESCRIPTOR));
+        //It is no longer a descriptor that terminates list
+        SbPortDescriptor->Flags &= (~ DESCRIPTOR_TERMINATE_LIST);
+        // Reattach descriptor list to complex
+        SbComplexDescriptor->PciePortList = SbPortDescriptor;
+      }
+    }
+  }
+  // Mark descriptor as SB link
+  SbPortDescriptor->Port.MiscControls.SbLink = 0x1;
+  return ResultComplexConfig;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate global PCIe configuration data
+ *
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @param[out] Pcie            Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS   Configuration data successfully located
+ * @retval     AGESA_FATAL     Configuration can not be located.
+ */
+AGESA_STATUS
+PcieLocateConfigurationData (
+  IN       AMD_CONFIG_PARAMS               *StdHeader,
+     OUT   PCIe_PLATFORM_CONFIG            **Pcie
+  )
+{
+  *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader);
+  if (*Pcie == NULL) {
+    IDS_ERROR_TRAP;
+    return AGESA_FATAL;
+  }
+  (*Pcie)->StdHeader = /* (PVOID) */ (UINT32)StdHeader;
+  PcieUpdateConfigurationData (*Pcie);
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attache descriptors
+ *
+ *
+ * @param[in]      Type       Descriptor type
+ * @param[in,out]  Base       Base descriptor
+ * @param[in,out]  New      New  descriptor
+ */
+VOID
+STATIC
+PcieConfigAttachDescriptors (
+  IN       UINT32                         Type,
+  IN OUT   PCIe_DESCRIPTOR_HEADER         *Base,
+  IN OUT   PCIe_DESCRIPTOR_HEADER         *New
+  )
+{
+  PCIe_DESCRIPTOR_HEADER  *Left;
+  PCIe_DESCRIPTOR_HEADER  *Right;
+
+  Left = PcieConfigGetPeer (DESCRIPTOR_TERMINATE_GNB, PcieConfigGetChild (Type, Base));
+  ASSERT (Left != NULL);
+  Right = PcieConfigGetChild (Type, New);
+  Left->Peer = (UINT16) ((UINT8 *) Right - (UINT8 *) Left);
+  PcieConfigResetDescriptorFlags (Left, DESCRIPTOR_TERMINATE_TOPOLOGY);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Attach configurations of two GNB to each other.
+ *
+ * Function will link all data structure to linked lists
+ *
+ * @param[in,out]  Base       Base complex descriptor
+ * @param[in,out]  New        New complex descriptor
+ */
+VOID
+STATIC
+PcieConfigAttachComplexes (
+  IN OUT   PCIe_COMPLEX_CONFIG            *Base,
+  IN OUT   PCIe_COMPLEX_CONFIG            *New
+  )
+{
+  // Connect Complex
+  Base->Header.Peer = (UINT16) ((UINT8 *) New - (UINT8 *) Base);
+  PcieConfigResetDescriptorFlags (Base, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  // Connect Silicon
+  PcieConfigAttachDescriptors (DESCRIPTOR_SILICON, &Base->Header, &New->Header);
+  // Connect Wrappers
+  PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, &Base->Header, &New->Header);
+  // Connect Engines
+  PcieConfigAttachDescriptors (DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE, &Base->Header, &New->Header);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update configuration data
+ *
+ * Puprouse of this structure to update config data that base on programming of
+ * other silicon compoments. For instance PCI address of GNB and PCIe ports
+ * can change by AGESA or external agent
+ *
+ *
+ * @param[in,out]   Pcie        Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS    Configuration data successfully update
+ * @retval     AGESA_FATAL      Failt to update configuration
+ */
+AGESA_STATUS
+PcieUpdateConfigurationData (
+  IN       PCIe_PLATFORM_CONFIG            *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG   *Silicon;
+  PCIe_ENGINE_CONFIG    *Engine;
+  PCI_ADDR              NewAddress;
+  // Update silicon configuration
+  Silicon = PcieConfigGetChildSilicon (Pcie);
+  while (Silicon != NULL) {
+    NewAddress = GnbFmGetPciAddress ((GNB_HANDLE *) PcieConfigGetParentComplex (Silicon), GnbLibGetHeader (Pcie));
+    if (Silicon->Address.AddressValue != NewAddress.AddressValue) {
+      Silicon->Address.AddressValue = NewAddress.AddressValue;
+      Engine = PcieConfigGetChildEngine (Silicon);
+      while (Engine != NULL) {
+        if (PcieConfigIsPcieEngine (Engine)) {
+          Engine->Type.Port.Address.Address.Bus = Silicon->Address.Address.Bus;
+        }
+        Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_GNB);
+      }
+    }
+    Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
new file mode 100644
index 0000000000..063d408245
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIECONFIGDATA_H_
+#define _PCIECONFIGDATA_H_
+
+
+AGESA_STATUS
+PcieLocateConfigurationData (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  OUT     PCIe_PLATFORM_CONFIG            **Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
new file mode 100644
index 0000000000..0083e80ad9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -0,0 +1,827 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65589 $   @e \$Date: 2012-02-19 20:32:29 -0600 (Sun, 19 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "PcieMapTopology.h"
+#include  "PcieInputParser.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * get Master Lane of PCIe port engine
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine descriptor
+ * @retval                 Master Engine Lane Number
+ */
+UINT8
+PcieConfigGetPcieEngineMasterLane (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT8                 MasterLane;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+  ASSERT (PcieConfigIsPcieEngine (Engine));
+
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  if (Engine->EngineData.StartLane <= Engine->EngineData.EndLane) {
+    MasterLane = (UINT8) (Engine->EngineData.StartLane - Wrapper->StartPhyLane);
+  } else {
+    MasterLane = (UINT8) (Engine->EngineData.EndLane - Wrapper->StartPhyLane);
+  }
+  return MasterLane;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of core lanes
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine descriptor
+ * @retval                 Number of core lane
+ */
+UINT8
+PcieConfigGetNumberOfCoreLane (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) {
+    return 0;
+  }
+  return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable engine
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ */
+VOID
+PcieConfigDisableEngine (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  if (PcieConfigIsSbPcieEngine (Engine)) {
+    return;
+  }
+  PcieConfigResetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable all engines on wrapper
+ *
+ *
+ *
+ * @param[in]  EngineTypeMask Engine type bitmap.
+ * @param[in]  Wrapper        Pointer to wrapper config descriptor
+ */
+VOID
+PcieConfigDisableAllEngines (
+  IN      UINTN                          EngineTypeMask,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) {
+      PcieConfigDisableEngine (EngineList);
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get engine PHY lanes bitmap
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ */
+UINT32
+PcieConfigGetEnginePhyLaneBitMap (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitMap;
+  LaneBitMap = 0;
+  if (PcieLibIsEngineAllocated (Engine)) {
+    LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) <<  (PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane);
+  }
+  return LaneBitMap;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of phy lanes
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine config descriptor
+ * @retval                 Number of Phy lane
+ */
+UINT8
+PcieConfigGetNumberOfPhyLane (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
+    return 0;
+  }
+  if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
+    return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1);
+  } else {
+    return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get port configuration signature for given wrapper and core
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper config descriptor
+ * @param[in]  CoreId      Core ID
+ * @retval                 Configuration Signature
+ */
+UINT64
+PcieConfigGetConfigurationSignature (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper,
+  IN      UINT8                          CoreId
+  )
+{
+  UINT64              ConfigurationSignature;
+  PCIe_ENGINE_CONFIG  *EngineList;
+  ConfigurationSignature = 0;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsPcieEngine (EngineList) && EngineList->Type.Port.CoreId == CoreId) {
+      ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList);
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  return ConfigurationSignature;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check Port Status
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  PortStatus      Check if status asserted for port
+ * @retval                     TRUE if status asserted
+ */
+BOOLEAN
+PcieConfigCheckPortStatus (
+  IN       PCIe_ENGINE_CONFIG            *Engine,
+  IN       UINT32                        PortStatus
+  )
+{
+  return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set/Reset port status
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  SetStatus       SetStatus
+ * @param[in]  ResetStatus     ResetStatus
+ *
+ */
+UINT16
+PcieConfigUpdatePortStatus (
+  IN       PCIe_ENGINE_CONFIG               *Engine,
+  IN       PCIe_ENGINE_INIT_STATUS          SetStatus,
+  IN       PCIe_ENGINE_INIT_STATUS          ResetStatus
+  )
+{
+  Engine->InitStatus |= SetStatus;
+  Engine->InitStatus &= (~ResetStatus);
+  return Engine->InitStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute callback on all descriptor of specific type
+ *
+ *
+ * @param[in]       InDescriptorFlags    Include descriptor flags
+ * @param[in]       OutDescriptorFlags   Exlude descriptor flags
+ * @param[in]       TerminationFlags     Termination flags
+ * @param[in]       Callback             Pointer to callback function
+ * @param[in, out]  Buffer               Pointer to buffer to pass information to callback
+ * @param[in]       Pcie                 Pointer to global PCIe configuration
+ */
+
+AGESA_STATUS
+PcieConfigRunProcForAllDescriptors (
+  IN       UINT32                           InDescriptorFlags,
+  IN       UINT32                           OutDescriptorFlags,
+  IN       UINT32                           TerminationFlags,
+  IN       PCIe_RUN_ON_DESCRIPTOR_CALLBACK  Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  )
+{
+  AGESA_STATUS            AgesaStatus;
+  AGESA_STATUS            Status;
+  PCIe_DESCRIPTOR_HEADER  *Descriptor;
+
+  AgesaStatus = AGESA_SUCCESS;
+  Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header);
+  while (Descriptor != NULL) {
+    if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) {
+      Status = Callback (Descriptor, Buffer, Pcie);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+    Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags);
+  }
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute callback on all wrappers in topology
+ *
+ *
+ * @param[in]       DescriptorFlags   Wrapper Flags
+ * @param[in]       Callback          Pointer to callback function
+ * @param[in, out]  Buffer            Pointer to buffer to pass information to callback
+ * @param[in]       Pcie              Pointer to global PCIe configuration
+ */
+
+AGESA_STATUS
+PcieConfigRunProcForAllWrappers (
+  IN       UINT32                        DescriptorFlags,
+  IN       PCIe_RUN_ON_WRAPPER_CALLBACK  Callback,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+
+  AgesaStatus = AGESA_SUCCESS;
+  Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header);
+  while (Wrapper != NULL) {
+    if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
+      if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) {
+        Status = Callback (Wrapper, Buffer, Pcie);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      }
+    }
+    Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute callback on all engine in topology
+ *
+ *
+ * @param[in]       DescriptorFlags Engine flags.
+ * @param[in]       Callback        Pointer to callback function
+ * @param[in, out]  Buffer          Pointer to buffer to pass information to callback
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PcieConfigRunProcForAllEngines (
+  IN       UINT32                        DescriptorFlags,
+  IN       PCIe_RUN_ON_ENGINE_CALLBACK   Callback,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+
+  PCIe_ENGINE_CONFIG  *Engine;
+  Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header);
+  while (Engine != NULL) {
+    if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
+      if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) {
+        if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) {
+          Callback (Engine, Buffer, Pcie);
+        }
+      }
+    }
+    Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get parent descriptor of specific type
+ *
+ *
+ * @param[in]       Type            Descriptor type
+ * @param[in]       Descriptor      Pointer to buffer to pass information to callback
+ */
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetParent (
+  IN       UINT32                        Type,
+  IN       PCIe_DESCRIPTOR_HEADER        *Descriptor
+  )
+{
+  while ((Descriptor->DescriptorFlags & Type) == 0) {
+    if (Descriptor->Parent != 0) {
+      Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor - Descriptor->Parent);
+    } else {
+      return NULL;
+    }
+  }
+  return Descriptor;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get child descriptor of specific type
+ *
+ *
+ * @param[in]       Type            Descriptor type
+ * @param[in]       Descriptor      Pointer to buffer to pass information to callback
+ */
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetChild (
+  IN       UINT32                        Type,
+  IN       PCIe_DESCRIPTOR_HEADER        *Descriptor
+  )
+{
+  while ((Descriptor->DescriptorFlags & Type) == 0) {
+    if (Descriptor->Child != 0) {
+      Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Child);
+    } else {
+      return NULL;
+    }
+  }
+  return Descriptor;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get peer descriptor of specific type
+ *
+ *
+ * @param[in]       Type            Descriptor type
+ * @param[in]       Descriptor      Pointer to buffer to pass information to callback
+ */
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetPeer (
+  IN       UINT32                        Type,
+  IN       PCIe_DESCRIPTOR_HEADER        *Descriptor
+  )
+{
+  ASSERT (Descriptor != NULL);
+  while ((Descriptor->DescriptorFlags & Type) == 0) {
+    if (Descriptor->Peer != 0) {
+      Descriptor = (PCIe_DESCRIPTOR_HEADER *) ((UINT8 *) Descriptor + Descriptor->Peer);
+    } else {
+      return NULL;
+    }
+  }
+  return Descriptor;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check is engine is active or potentially active
+ *
+ *
+ *
+ * @param[in]  Engine      Pointer to engine descriptor
+ * @retval                 TRUE  - engine active
+ * @retval                 FALSE - engine not active
+ */
+BOOLEAN
+PcieConfigIsActivePcieEngine (
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  BOOLEAN Result;
+  ASSERT (PcieConfigIsPcieEngine (Engine));
+  Result = FALSE;
+  if (PcieConfigIsEngineAllocated (Engine)) {
+    if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+      (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate SB engine on wrapper
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to wrapper config descriptor
+ * @retval                 SB engine pointer or NULL
+ */
+PCIe_ENGINE_CONFIG *
+PcieConfigLocateSbEngine (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsSbPcieEngine (EngineList)) {
+      return EngineList;
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  return NULL;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump engine configuration
+ *
+ *
+ * @param[in]  EngineList           Engine Configuration
+ */
+VOID
+PcieConfigEngineDebugDump (
+  IN      PCIe_ENGINE_CONFIG        *EngineList
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Descriptor Flags - 0x%08x\n", EngineList->Header.DescriptorFlags);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Engine Type - %s\n        Start Phy Lane - %d\n        End   Phy Lane - %d\n",
+    ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"),
+    EngineList->EngineData.StartLane,
+    EngineList->EngineData.EndLane
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Scrath         - %d\n", EngineList->Scratch);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Init Status    - 0x%08x\n", EngineList->InitStatus);
+  if (PcieLibIsPcieEngine (EngineList)) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "        PCIe port configuration:\n");
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Port Training - %s\n",
+      (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled"
+      );
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          End Core Lane   - %d\n", EngineList->Type.Port.EndCoreLane);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Requested PCI Dev Number   - %d\n",EngineList->Type.Port.PortData.DeviceNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Requested PCI Func Number  - %d\n",EngineList->Type.Port.PortData.FunctionNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          PCI Address - %d:%d:%d\n",
+      EngineList->Type.Port.Address.Address.Bus,
+      EngineList->Type.Port.Address.Address.Device,
+      EngineList->Type.Port.Address.Address.Function
+      );
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Misc Control  - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Native PCI Dev Number  - %d\n", EngineList->Type.Port.NativeDevNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Hotplug - %s\n",
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) ? "Disabled" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugBasic) ? "Basic" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugServer) ? "Server" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugEnhanced) ? "Enhanced" : (
+      (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard) ? "Inboard" : "Unknown"))))
+      );
+    ASSERT (EngineList->Type.Port.PortData.LinkHotplug < MaxHotplug);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          ASPM    - %s\n",
+      (EngineList->Type.Port.PortData.LinkAspm == AspmDisabled) ? "Disabled" : (
+      (EngineList->Type.Port.PortData.LinkAspm == AspmL0s) ? "L0s" : (
+      (EngineList->Type.Port.PortData.LinkAspm == AspmL1) ? "L1" :  (
+      (EngineList->Type.Port.PortData.LinkAspm == AspmL0sL1) ? "L0s & L1" : "Unknown")))
+      );
+    ASSERT (EngineList->Type.Port.PortData.LinkAspm < MaxAspm);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Speed   - %d\n",
+      EngineList->Type.Port.PortData.LinkSpeedCapability
+      );
+  } else {
+    IDS_HDT_CONSOLE (PCIE_MISC, "        DDI configuration:\n");
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Connector - %s\n",
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) ? "Single Link DVI-I" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeCrt) ? "CRT" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) ? "eDP To Lvds" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) ? "Realtec eDP To Lvds" : (
+      (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect) ? "Autodetect" : "Unknown")))))))))))))
+      );
+    ASSERT (EngineList->Type.Ddi.DdiData.ConnectorType < MaxConnectorType);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1);
+    ASSERT (EngineList->Type.Ddi.DdiData.AuxIndex < MaxAux);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1);
+    ASSERT (EngineList->Type.Ddi.DdiData.HdpIndex < MaxHdp);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump wrapper configuration
+ *
+ *
+ * @param[in]  WrapperList           Wrapper Configuration
+ */
+VOID
+PcieConfigWrapperDebugDump (
+  IN      PCIe_WRAPPER_CONFIG        *WrapperList
+  )
+{
+  PCIe_ENGINE_CONFIG    *EngineList;
+  IDS_HDT_CONSOLE (PCIE_MISC, "      <---------Wrapper - %s Config -------->\n",
+    PcieFmDebugGetWrapperNameString (WrapperList)
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Start PHY lane - %02d\n", WrapperList->StartPhyLane);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        End   PHY lane - %02d\n", WrapperList->EndPhyLane);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        Descriptor Flags - 0x%08x\n", WrapperList->Header.DescriptorFlags);
+  IDS_HDT_CONSOLE (PCIE_MISC, "        PowerOffUnusedLanes - %x\n        PowerOffUnusedPlls - %x\n        ClkGating - %x\n"
+                              "        LclkGating - %x\n        TxclkGatingPllPowerDown - %x\n        PllOffInL1 - %x\n",
+    WrapperList->Features.PowerOffUnusedLanes,
+    WrapperList->Features.PowerOffUnusedPlls,
+    WrapperList->Features.ClkGating,
+    WrapperList->Features.LclkGating,
+    WrapperList->Features.TxclkGatingPllPowerDown,
+    WrapperList->Features.PllOffInL1
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "      <---------Wrapper - %s Config End----->\n",
+    PcieFmDebugGetWrapperNameString (WrapperList)
+    );
+  EngineList = PcieConfigGetChildEngine (WrapperList);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      PcieConfigEngineDebugDump (EngineList);
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump configuration to debug out
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieConfigDebugDump (
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG   *SiliconList;
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  PCIe_COMPLEX_CONFIG   *ComplexList;
+  ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
+  IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n");
+  IDS_HDT_CONSOLE (PCIE_MISC, "  PSPP Policy - %s\n",
+   (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" :
+   (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : (
+   (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : (
+   (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : (
+   (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown")))
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  GFX Workaround - %s\n",
+   (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled"
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  LinkL0Pooling - %dus\n",
+   Pcie->LinkL0Pooling
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  LinkGpioResetAssertionTime - %dus\n",
+   Pcie->LinkGpioResetAssertionTime
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  LinkReceiverDetectionPooling - %dus\n",
+   Pcie->LinkReceiverDetectionPooling
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Training Algorythm - %s\n",
+    (Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : (
+    (Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown")
+    );
+  while (ComplexList != NULL) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "  <---------- Complex Config Start ---------->\n");
+    IDS_HDT_CONSOLE (PCIE_MISC, "    Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags);
+    IDS_HDT_CONSOLE (PCIE_MISC, "    Socket ID - %d\n", ComplexList->SocketId);
+    SiliconList = PcieConfigGetChildSilicon (ComplexList);
+    while (SiliconList != NULL) {
+      IDS_HDT_CONSOLE (PCIE_MISC, "    <---------- Silicon Config Start -------->\n");
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags);
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Silicon ID - %d\n", SiliconList->SiliconId);
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Node ID - %d\n", SiliconList->NodeId);
+      IDS_HDT_CONSOLE (PCIE_MISC, "      Host PCI Address - %d:%d:%d\n",
+        SiliconList->Address.Address.Bus,
+        SiliconList->Address.Address.Device,
+        SiliconList->Address.Address.Function
+        );
+      WrapperList = PcieConfigGetChildWrapper (SiliconList);
+      while (WrapperList != NULL) {
+        PcieConfigWrapperDebugDump (WrapperList);
+        WrapperList = PcieLibGetNextDescriptor (WrapperList);
+      }
+      IDS_HDT_CONSOLE (PCIE_MISC, "    <---------- Silicon Config End ---------->\n");
+      SiliconList = PcieLibGetNextDescriptor (SiliconList);
+    }
+    IDS_HDT_CONSOLE (PCIE_MISC, "  <---------- Complex Config End ------------>\n");
+    ComplexList = PcieLibGetNextDescriptor (ComplexList);
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump input configuration to user engine descriptor
+ *
+ *
+ * @param[in]  EngineDescriptor   Pointer to engine descriptor
+ */
+VOID
+PcieUserDescriptorConfigDump (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor
+  )
+{
+
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Engine Type - %s\n",
+    (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : (
+    (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : (
+    (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid"))
+    );
+  IDS_HDT_CONSOLE (PCIE_MISC, "    Start Phy Lane - %d\n    End   Phy Lane - %d\n",
+    EngineDescriptor->EngineData.StartLane,
+    EngineDescriptor->EngineData.EndLane
+  );
+  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "    PortPresent - %d\n    ChannelType  - %d\n    DeviceNumber - %d\n    FunctionNumber - %d\n    LinkSpeedCapability - %d\n    LinkAspm - %d\n    LinkHotplug - %d\n    ResetId - %d\n    SB link - %d\n    MiscControls - 0x%02x\n" ,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls
+    );
+  }
+  if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "    ConnectorType - %d\n    AuxIndex  - %d\n    HdpIndex - %d\n" ,
+      ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType,
+      ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex,
+      ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex
+    );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump input configuration to debug out
+ *
+ *
+ * @param[in]  ComplexDescriptor   Pointer to user defined complex descriptor
+ */
+VOID
+PcieUserConfigConfigDump (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor
+  )
+{
+  PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor;
+  PCIe_COMPLEX_DESCRIPTOR     *CurrentComplexDescriptor;
+  UINTN                       ComplexIndex;
+  UINTN                       Index;
+  UINTN                       NumberOfEngines;
+  UINTN                       NumberOfComplexes;
+
+  IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n");
+
+  NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor);
+  for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) {
+    CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex);
+    NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor);
+    IDS_HDT_CONSOLE (PCIE_MISC, "  ComplexDescriptor SocketId - %d\n  NumberOfEngines - %d\n",
+        ComplexDescriptor->SocketId,
+        NumberOfEngines
+      );
+
+    for (Index = 0; Index < NumberOfEngines; Index++) {
+      EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
+      PcieUserDescriptorConfigDump (EngineDescriptor);
+    }
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
new file mode 100644
index 0000000000..4a732dce78
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
@@ -0,0 +1,248 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB function to create/locate PCIe configuration data area
+ *
+ * Contain code that create/locate and rebase configuration data area.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIECONFIGLIB_H_
+#define _PCIECONFIGLIB_H_
+
+typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) (
+  IN      PCIe_ENGINE_CONFIG                *Engine,
+  IN OUT  VOID                              *Buffer,
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) (
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper,
+  IN OUT  VOID                              *Buffer,
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+typedef AGESA_STATUS (*PCIe_RUN_ON_DESCRIPTOR_CALLBACK) (
+  IN      PCIe_DESCRIPTOR_HEADER            *Descriptor,
+  IN OUT  VOID                              *Buffer,
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+UINT8
+PcieConfigGetPcieEngineMasterLane (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT8
+PcieConfigGetNumberOfCoreLane (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+VOID
+PcieConfigDisableAllEngines (
+  IN      UINTN                             EngineTypeMask,
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper
+  );
+
+VOID
+PcieConfigDisableEngine (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT32
+PcieConfigGetEnginePhyLaneBitMap (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT8
+PcieConfigGetNumberOfPhyLane (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+UINT64
+PcieConfigGetConfigurationSignature (
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper,
+  IN      UINT8                             CoreId
+  );
+
+BOOLEAN
+PcieConfigCheckPortStatus (
+  IN       PCIe_ENGINE_CONFIG               *Engine,
+  IN       UINT32                           PortStatus
+  );
+
+UINT16
+PcieConfigUpdatePortStatus (
+  IN       PCIe_ENGINE_CONFIG               *Engine,
+  IN       PCIe_ENGINE_INIT_STATUS          SetStatus,
+  IN       PCIe_ENGINE_INIT_STATUS          ResetStatus
+  );
+
+VOID
+PcieConfigRunProcForAllEngines (
+  IN       UINT32                           DescriptorFlags,
+  IN       PCIe_RUN_ON_ENGINE_CALLBACK      Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+AGESA_STATUS
+PcieConfigRunProcForAllWrappers (
+  IN       UINT32                           DescriptorFlags,
+  IN       PCIe_RUN_ON_WRAPPER_CALLBACK     Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+AGESA_STATUS
+PcieConfigRunProcForAllDescriptors (
+  IN       UINT32                           InDescriptorFlags,
+  IN       UINT32                           OutDescriptorFlags,
+  IN       UINT32                           TerminationFlags,
+  IN       PCIe_RUN_ON_DESCRIPTOR_CALLBACK  Callback,
+  IN OUT   VOID                             *Buffer,
+  IN       PCIe_PLATFORM_CONFIG             *Pcie
+  );
+
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetParent (
+  IN       UINT32                           Type,
+  IN       PCIe_DESCRIPTOR_HEADER           *Descriptor
+  );
+
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetChild (
+  IN       UINT32                           Type,
+  IN       PCIe_DESCRIPTOR_HEADER           *Descriptor
+  );
+
+PCIe_DESCRIPTOR_HEADER *
+PcieConfigGetPeer (
+  IN       UINT32                           Type,
+  IN       PCIe_DESCRIPTOR_HEADER           *Descriptor
+ );
+
+BOOLEAN
+PcieConfigIsActivePcieEngine (
+  IN      PCIe_ENGINE_CONFIG                *Engine
+  );
+
+PCIe_ENGINE_CONFIG *
+PcieConfigLocateSbEngine (
+  IN      PCIe_WRAPPER_CONFIG               *Wrapper
+  );
+
+VOID
+PcieConfigDebugDump (
+  IN      PCIe_PLATFORM_CONFIG              *Pcie
+  );
+
+VOID
+PcieConfigWrapperDebugDump (
+  IN      PCIe_WRAPPER_CONFIG               *WrapperList
+  );
+
+VOID
+PcieConfigEngineDebugDump (
+  IN      PCIe_ENGINE_CONFIG                *EngineList
+  );
+
+VOID
+PcieUserConfigConfigDump (
+  IN      PCIe_COMPLEX_DESCRIPTOR           *ComplexDescriptor
+  );
+
+VOID
+PcieUserDescriptorConfigDump (
+  IN      PCIe_ENGINE_DESCRIPTOR            *EngineDescriptor
+  );
+
+#define PcieConfigGetParentWrapper(Descriptor)    ((PCIe_WRAPPER_CONFIG *) PcieConfigGetParent (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header)))
+#define PcieConfigGetParentSilicon(Descriptor)    ((PCIe_SILICON_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &((Descriptor)->Header)))
+#define PcieConfigGetParentComplex(Descriptor)    ((PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &((Descriptor)->Header)))
+#define PcieConfigGetPlatform(Descriptor)         ((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))
+#define PcieConfigGetChildWrapper(Descriptor)     ((PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &((Descriptor)->Header)))
+#define PcieConfigGetChildEngine(Descriptor)      ((PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &((Descriptor)->Header)))
+#define PcieConfigGetChildSilicon(Descriptor)     ((PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &((Descriptor)->Header)))
+#define PcieConfigGetNextDescriptor(Descriptor)   ((((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor)))
+#define PcieConfigIsPcieEngine(Descriptor)        (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE)
+#define PcieConfigIsDdiEngine(Descriptor)         (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE)
+#define PcieConfigIsPcieWrapper(Descriptor)       (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE)
+#define PcieConfigIsSbPcieEngine(Engine)          (Engine != NULL ? ((BOOLEAN) (Engine->Type.Port.PortData.MiscControls.SbLink)) : FALSE)
+#define PcieConfigIsDdiWrapper(Descriptor)        (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE)
+#define PcieConfigIsEngineAllocated(Descriptor)   (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE)
+#define PcieConfigIsVirtualDesciptor(Descriptor)  (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE)
+#define PcieConfigSetDescriptorFlags(Descriptor, SetDescriptorFlags)   if (Descriptor != NULL) (Descriptor)->Header.DescriptorFlags |= SetDescriptorFlags
+#define PcieConfigResetDescriptorFlags(Descriptor, ResetDescriptorFlags) if (Descriptor != NULL) ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags &= (~(ResetDescriptorFlags))
+#define PcieInputParsetGetNextDescriptor(Descriptor) (Descriptor != NULL ? ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1))) : NULL)
+#define PcieConfigGetNextTopologyDescriptor(Descriptor, Termination) (Descriptor != NULL ? (((((PCIe_DESCRIPTOR_HEADER *) Descriptor)->DescriptorFlags & Termination) != 0) ? NULL : ((UINT8 *) Descriptor + ((PCIe_DESCRIPTOR_HEADER *) Descriptor)->Peer)) : NULL)
+#define GnbGetNextHandle(Descriptor) (GNB_HANDLE *) PcieConfigGetNextTopologyDescriptor (Descriptor, DESCRIPTOR_TERMINATE_TOPOLOGY)
+#define PcieConfigGetNextDataDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0 ? NULL : ++Descriptor)
+
+#define PcieConfigGetStdHeader(Descriptor)         ((AMD_CONFIG_PARAMS *)((PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &((Descriptor)->Header)))->StdHeader)
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
new file mode 100644
index 0000000000..b4b6106772
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
@@ -0,0 +1,275 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Procedure to parse PCIe input configuration data
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "PcieInputParser.h"
+#include  "PcieConfigLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of complexes in platform topology configuration
+ *
+ *
+ *
+ * @param[in] ComplexList  First complex configuration in complex configuration array
+ * @retval                 Number of Complexes
+ *
+ */
+UINTN
+PcieInputParserGetNumberOfComplexes (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList
+  )
+{
+  UINTN                Result;
+  Result = 0;
+  while (ComplexList != NULL) {
+    Result++;
+    ComplexList = PcieInputParsetGetNextDescriptor (ComplexList);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of PCIe engines in given complex
+ *
+ *
+ *
+ * @param[in] Complex     Complex configuration
+ * @retval                Number of Engines
+ */
+UINTN
+PcieInputParserGetLengthOfPcieEnginesList (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+  )
+{
+  UINTN                 Result;
+  PCIe_PORT_DESCRIPTOR  *PciePortList;
+  Result = 0;
+  PciePortList = Complex->PciePortList;
+  while (PciePortList != NULL) {
+    Result++;
+    PciePortList = PcieInputParsetGetNextDescriptor (PciePortList);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of DDI engines in given complex
+ *
+ *
+ *
+ * @param[in] Complex     Complex configuration
+ * @retval                Number of Engines
+ */
+STATIC UINTN
+PcieInputParserGetLengthOfDdiEnginesList (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+  )
+{
+  UINTN                 Result;
+  PCIe_DDI_DESCRIPTOR  *DdiLinkList;
+  Result = 0;
+  DdiLinkList = Complex->DdiLinkList;
+  while (DdiLinkList != NULL) {
+    Result++;
+    DdiLinkList = PcieInputParsetGetNextDescriptor (DdiLinkList);
+  }
+  return Result;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of engines in given complex
+ *
+ *
+ *
+ * @param[in] Complex     Complex configuration header
+ * @retval                Number of Engines
+ */
+UINTN
+PcieInputParserGetNumberOfEngines (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *Complex
+  )
+{
+  UINTN                     Result;
+
+  Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) +
+           PcieInputParserGetLengthOfPcieEnginesList (Complex);
+  return Result;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Complex descriptor by index from given Platform configuration
+ *
+ *
+ *
+ * @param[in] ComplexList Platform topology configuration
+ * @param[in] Index       Complex descriptor Index
+ * @retval                Pointer to Complex Descriptor
+ */
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *ComplexList,
+  IN      UINTN                           Index
+  )
+{
+  ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList)));
+  return &ComplexList[Index];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Complex descriptor by index from given Platform configuration
+ *
+ *
+ *
+ * @param[in] ComplexList  Platform topology configuration
+ * @param[in] SocketId     Socket Id
+ * @retval                Pointer to Complex Descriptor
+ */
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptorOfSocket (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *ComplexList,
+  IN      UINT32                          SocketId
+  )
+{
+  PCIe_COMPLEX_DESCRIPTOR *Result;
+  Result = NULL;
+  while (ComplexList != NULL) {
+    if (ComplexList->SocketId == SocketId) {
+      Result = ComplexList;
+      break;
+    }
+    ComplexList = PcieInputParsetGetNextDescriptor (ComplexList);
+  }
+  return Result;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Engine descriptor from given complex by index
+ *
+ *
+ *
+ * @param[in] Complex     Complex descriptor
+ * @param[in] Index       Engine descriptor index
+ * @retval                Pointer to Engine Descriptor
+ */
+PCIe_ENGINE_DESCRIPTOR*
+PcieInputParserGetEngineDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR         *Complex,
+  IN      UINTN                           Index
+  )
+{
+  UINTN PcieListlength;
+  ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex)));
+  PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex);
+  if (Index < PcieListlength) {
+    return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]);
+  } else {
+    return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
new file mode 100644
index 0000000000..630f9ae187
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  Procedure to parse PCIe input configuration data
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEINPUTPARSER_H_
+#define _PCIEINPUTPARSER_H_
+
+
+UINTN
+PcieInputParserGetNumberOfComplexes (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList
+ );
+
+UINTN
+PcieInputParserGetNumberOfEngines (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+ );
+
+
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList,
+  IN      UINTN                         Index
+ );
+
+PCIe_ENGINE_DESCRIPTOR*
+PcieInputParserGetEngineDescriptor (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex,
+  IN      UINTN                         Index
+ );
+
+PCIe_COMPLEX_DESCRIPTOR*
+PcieInputParserGetComplexDescriptorOfSocket (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *ComplexList,
+  IN      UINT32                        SocketId
+  );
+
+UINTN
+PcieInputParserGetLengthOfPcieEnginesList (
+  IN      PCIe_COMPLEX_DESCRIPTOR       *Complex
+  );
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
new file mode 100644
index 0000000000..f1fc4b8ac5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
@@ -0,0 +1,672 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Procedure to map user define topology to processor configuration
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GeneralServices.h"
+#include  "PcieInputParser.h"
+#include  "PcieMapTopology.h"
+#include  "GnbPcieConfig.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieMapPortsPciAddresses (
+  IN      PCIe_SILICON_CONFIG         *Silicon,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  );
+
+AGESA_STATUS
+PcieMapTopologyOnWrapper (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT  PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+ );
+
+VOID
+PcieMapInitializeEngineData (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT  PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+ );
+
+BOOLEAN
+PcieCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR        *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  );
+
+BOOLEAN
+PcieIsDescriptorLinkWidthValid (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor
+  );
+
+BOOLEAN
+PcieCheckLanesMatch (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  );
+
+BOOLEAN
+PcieCheckDescriptorMapsToWrapper (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_WRAPPER_CONFIG         *Wrapper
+  );
+
+VOID
+PcieAllocateEngine (
+  IN      UINT8                       DescriptorIndex,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  ComplexDescriptor   Pointer to used define complex descriptor
+ * @param[in]  Complex             Pointer to complex descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+PcieMapTopologyOnComplex (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN      PCIe_COMPLEX_CONFIG         *Complex,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG *Silicon;
+  PCIe_WRAPPER_CONFIG *Wrapper;
+  AGESA_STATUS        AgesaStatus;
+  AGESA_STATUS        Status;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
+  Silicon = PcieConfigGetChildSilicon (Complex);
+  while (Silicon != NULL) {
+    Wrapper = PcieConfigGetChildWrapper (Silicon);
+    while (Wrapper != NULL) {
+      Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      if (Status == AGESA_ERROR) {
+        PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Fail to map topology on %s Wrapper\n",
+          PcieFmDebugGetWrapperNameString (Wrapper)
+          );
+        ASSERT (FALSE);
+      }
+      Wrapper = PcieLibGetNextDescriptor (Wrapper);
+    }
+    Status = PcieMapPortsPciAddresses (Silicon, Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Silicon = PcieLibGetNextDescriptor (Silicon);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  EngineType          Engine type
+ * @param[in]  ComplexDescriptor   Pointer to used define complex descriptor
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+STATIC AGESA_STATUS
+PcieEnginesToWrapper (
+  IN      PCIE_ENGINE_TYPE            EngineType,
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN      PCIe_WRAPPER_CONFIG         *Wrapper
+  )
+{
+  AGESA_STATUS                Status;
+  PCIe_ENGINE_CONFIG          *EngineList;
+  PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor;
+  UINT8                       ConfigurationId;
+  UINT8                       Allocations;
+  UINTN                       Index;
+  UINTN                       NumberOfDescriptors;
+
+  ConfigurationId = 0;
+  Allocations = 0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n");
+  NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor);
+  do {
+    Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++);
+    if (Status == AGESA_SUCCESS) {
+      Allocations = 0;
+      for (Index = 0; Index < NumberOfDescriptors; Index++) {
+        EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
+        if (EngineDescriptor->EngineData.EngineType == EngineType) {
+          // Step 1, belongs to wrapper check.
+          if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) {
+            ++Allocations;
+            EngineList = PcieConfigGetChildEngine (Wrapper);
+            while (EngineList != NULL) {
+              if (!PcieLibIsEngineAllocated (EngineList)) {
+                // Step 2.user descriptor less or equal to link width of engine
+                if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) {
+                  // Step 3, Check if link width is correct.x1, x2, x4, x8, x16.
+                  if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) {
+                    PcieConfigDisableEngine (EngineList);
+                    return AGESA_ERROR;
+                  }
+                  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+                    // Step 4, Family specifc, port device number match engine device
+                    if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
+                      //Step 5, Family specifc, lanes can be muxed.
+                      if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
+                        PcieAllocateEngine ((UINT8) Index, EngineList);
+                        --Allocations;
+                        break;
+                      }
+                    }
+                  } else {
+                    PcieAllocateEngine ((UINT8) Index, EngineList);
+                    --Allocations;
+                    break;
+                  }
+                }
+              } //end if PcieLibIsEngineAllocated
+              EngineList = PcieLibGetNextDescriptor (EngineList);
+            }
+          } //end if PcieCheckDescriptorMapsToWrapper
+        } // end if EngineType
+      } //end for
+    }
+  } while (Status == AGESA_SUCCESS && Allocations != 0);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if lane from  user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
+ *
+ *
+ * @param[in]  EngineDescriptor    Pointer to used define engine descriptor
+ * @param[in]  Wrapper             Pointer to PCIe_WRAPPER_CONFIG
+ * @retval     TRUE                Belongs to wrapper
+ * @retval     FALSE               Not belongs to wrapper
+ */
+BOOLEAN
+PcieCheckDescriptorMapsToWrapper (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_WRAPPER_CONFIG         *Wrapper
+  )
+{
+  BOOLEAN Result;
+  UINT16  DescriptorHiLane;
+  UINT16  DescriptorLoLane;
+  UINT16  DescriptorNumberOfLanes;
+
+  DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+  Result = FALSE;
+
+  if (Wrapper->StartPhyLane <= DescriptorLoLane && DescriptorHiLane <= Wrapper->EndPhyLane) {
+    // Lanes of descriptor belongs to wrapper
+    Result = TRUE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Engine to be allocated.
+ *
+ *
+ * @param[in]  DescriptorIndex    UINT8 index
+ * @param[in]  Engine             Pointer to engine config
+ */
+VOID
+PcieAllocateEngine (
+  IN      UINT8                       DescriptorIndex,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  )
+{
+  PcieConfigSetDescriptorFlags (Engine, DESCRIPTOR_ALLOCATED);
+  Engine->Scratch = DescriptorIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ * PCIE port
+ *
+ *
+ * 1 Check if lane from  user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
+ * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
+ * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
+ * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG)
+ * 5 Check if lane can be muxed
+ *
+ *
+ * DDI Link
+ *
+ * 1 Check if lane from  user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
+ * 2 Check lane from  (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
+ *
+ *
+ *
+ * @param[in]     ComplexDescriptor   Pointer to used define complex descriptor
+ * @param[in,out] Wrapper             Pointer to wrapper config descriptor
+ * @param[in]     Pcie                Pointer to global PCIe configuration
+ * @retval        AGESA_SUCCESS       Topology successfully mapped
+ * @retval        AGESA_ERROR         Topology can not be mapped
+ */
+AGESA_STATUS
+PcieMapTopologyOnWrapper (
+  IN       PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT   PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  AGESA_STATUS                AgesaStatus;
+  AGESA_STATUS                Status;
+  PCIe_ENGINE_CONFIG          *EngineList;
+  UINT32                      WrapperPhyLaneBitMap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status == AGESA_ERROR) {
+      // If we can not map topology on wrapper we can not enable any engines.
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION,
+        Wrapper->WrapId,
+        Wrapper->StartPhyLane,
+        Wrapper->EndPhyLane,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+      PcieConfigDisableAllEngines (PciePortEngine, Wrapper);
+    }
+  }
+  if (PcieLibIsDdiWrapper (Wrapper)) {
+    Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status == AGESA_ERROR) {
+      // If we can not map topology on wrapper we can not enable any engines.
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION,
+        Wrapper->WrapId,
+        Wrapper->StartPhyLane,
+        Wrapper->EndPhyLane,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+      PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper);
+    }
+  }
+  // Copy engine data
+  PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie);
+
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  // Verify if we oversubscribe lanes and PHY link width
+  WrapperPhyLaneBitMap = 0;
+  while (EngineList != NULL) {
+    UINT32  EnginePhyLaneBitMap;
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList);
+      if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n",
+          EngineList->EngineData.StartLane,
+          EngineList->EngineData.EndLane
+          );
+        PutEventLog (
+          AGESA_ERROR,
+          GNB_EVENT_INVALID_LANES_CONFIGURATION,
+          EngineList->EngineData.StartLane,
+          EngineList->EngineData.EndLane,
+          0,
+          0,
+          GnbLibGetHeader (Pcie)
+          );
+        PcieConfigDisableEngine (EngineList);
+        Status = AGESA_ERROR;
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      } else {
+        WrapperPhyLaneBitMap |= EnginePhyLaneBitMap;
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnWrapper Exit [%d]\n", AgesaStatus);
+  return AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize engine data
+ *
+ *
+ *
+ * @param[in]     ComplexDescriptor   Pointer to user defined complex descriptor
+ * @param[in,out] Wrapper             Pointer to wrapper config descriptor
+ * @param[in]     Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieMapInitializeEngineData (
+  IN       PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN OUT   PCIe_WRAPPER_CONFIG         *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  PCIe_ENGINE_DESCRIPTOR    *EngineDescriptor;
+
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (EngineList->Scratch != 0xFF) {
+        EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch);
+        LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie));
+        if (PcieLibIsDdiEngine (EngineList)) {
+          LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie));
+          EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch;
+        } else if (PcieLibIsPcieEngine (EngineList)) {
+          LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie));
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate PCI addresses for all PCIe engines on silicon
+ *
+ *
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckPortPciDeviceMapping (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  BOOLEAN Result;
+
+  if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
+    PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) ||
+    (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) {
+    Result = TRUE;
+  } else {
+    Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
+  }
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate PCI addresses for all PCIe engines on silicon
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configurration
+ * @param[in]  Pcie                Pointer PCIe configuration
+ * @retval     AGESA_ERROR         Fail to allocate PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address for all PCIe ports
+ */
+
+AGESA_STATUS
+STATIC
+PcieMapPortsPciAddresses (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  AGESA_STATUS        Status;
+  AGESA_STATUS        AgesaStatus;
+  PCIe_WRAPPER_CONFIG *WrapperList;
+  PCIe_ENGINE_CONFIG  *EngineList;
+  AgesaStatus = AGESA_SUCCESS;
+  WrapperList = PcieConfigGetChildWrapper (Silicon);
+  while (WrapperList != NULL) {
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
+        Status = PcieFmMapPortPciAddress (EngineList);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+        if (Status == AGESA_SUCCESS) {
+          EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
+                                                         0,
+                                                         Silicon->Address.Address.Bus,
+                                                         EngineList->Type.Port.PortData.DeviceNumber,
+                                                         EngineList->Type.Port.PortData.FunctionNumber,
+                                                         0
+                                                         );
+        } else {
+          EngineList->Type.Port.PortData.PortPresent = OFF;
+          IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Fail to allocate PCI address for PCIe port\n"
+            );
+          //Report error
+          PutEventLog (
+            AGESA_ERROR,
+            GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
+            EngineList->Type.Port.PortData.DeviceNumber,
+            0,
+            0,
+            0,
+            GnbLibGetHeader (Pcie)
+            );
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    WrapperList = PcieLibGetNextDescriptor (WrapperList);
+  }
+  return AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * If link width from user descriptor less or equal to link width of engine
+ *
+ *
+ * @param[in]  EngineDescriptor    Pointer to used define engine descriptor
+ * @param[in]  Engine              Pointer to engine config
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckLanesMatch (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor,
+  IN      PCIe_ENGINE_CONFIG          *Engine
+  )
+{
+  BOOLEAN Result;
+  UINT16  DescriptorHiLane;
+  UINT16  DescriptorLoLane;
+  UINT16  DescriptorNumberOfLanes;
+
+  DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+  Result = FALSE;
+
+  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+    //
+    // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
+    //
+    if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) {
+      Result = TRUE;
+    }
+  } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
+    //
+    //For Ddi, check lane from  (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
+    //
+    if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) {
+      Result = TRUE;
+    }
+  }
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
+ *
+ *
+ * @param[in]  EngineDescriptor    A pointer of PCIe_ENGINE_DESCRIPTOR
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieIsDescriptorLinkWidthValid (
+  IN      PCIe_ENGINE_DESCRIPTOR      *EngineDescriptor
+  )
+{
+  BOOLEAN   Result;
+  UINT16    DescriptorHiLane;
+  UINT16    DescriptorLoLane;
+  UINT16    DescriptorNumberOfLanes;
+
+  Result = FALSE;
+  DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+
+  if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
+    if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 ||
+        DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) {
+      Result = TRUE;
+    }
+  } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
+    if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 7) {
+      Result = TRUE;
+    }
+  }
+
+  GNB_DEBUG_CODE (
+    if (!Result) {
+      IDS_HDT_CONSOLE (PCIE_MISC, "  Invalid Link width [Engine Lanes %d..%d]\n",
+        DescriptorLoLane,
+        DescriptorHiLane
+      );
+    }
+  );
+
+  return Result;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
new file mode 100644
index 0000000000..7f69aeab85
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Procedure to map user define topology to processor configuration
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEMAPTOPOLOGY_H_
+#define _PCIEMAPTOPOLOGY_H_
+
+AGESA_STATUS
+PcieMapTopologyOnComplex (
+  IN      PCIe_COMPLEX_DESCRIPTOR     *ComplexDescriptor,
+  IN      PCIe_COMPLEX_CONFIG         *Complex,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+ );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
new file mode 100644
index 0000000000..d92559cca9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Init Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEINITLIBV1_H_
+#define _PCIEINITLIBV1_H_
+
+#include "PciePifServices.h"
+#include "PciePortRegAcc.h"
+#include "PciePowerMgmt.h"
+#include "PcieTimer.h"
+#include "PcieTopologyServices.h"
+#include "PcieUtilityLib.h"
+#include "PcieWrapperRegAcc.h"
+#include "PcieAspmExitLatency.h"
+#include "PcieSiliconServices.h"
+#include "PciePortServices.h"
+#include "PcieAspm.h"
+#include "PciePhyServices.h"
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
new file mode 100644
index 0000000000..4642b7fa24
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -0,0 +1,179 @@
+/**
+ * @file
+ *
+ * PCIe link ASPM Black List
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "PcieAspmBlackList.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+UINT16  AspmBrDeviceTable[] = {
+ 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s),
+ 0x168C, 0xFFFF, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x9123, (UINT16) ~(AspmL0s),
+ 0x1969, 0x1083, (UINT16) ~(AspmL0s)
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie ASPM Black List
+ *
+ *
+ *
+ * @param[in] LinkAsmp            PCie ASPM black list
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieAspmBlackListFeature (
+  IN       PCIe_LINK_ASPM         *LinkAsmp,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  UpstreamDeviceId;
+  UINT32  DownstreamDeviceId;
+  UINTN   i;
+  UINT32  DeviceId;
+  UINT32  VendorId;
+
+  GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader);
+  GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader);
+  for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    VendorId = AspmBrDeviceTable[i];
+    DeviceId = AspmBrDeviceTable[i + 1];
+    if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) {
+      if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) {
+        LinkAsmp->UpstreamAspm &= AspmBrDeviceTable[i + 2];
+        LinkAsmp->DownstreamAspm &= AspmBrDeviceTable[i + 2];
+      }
+    }
+  }
+  if ((UINT16)UpstreamDeviceId == 0x168c) {
+    LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL1;
+    LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm;
+    GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader);
+
+    DeviceId = UpstreamDeviceId >> 16;
+    if ((DeviceId == 0x002C) || (DeviceId == 0x002B) || (DeviceId == 0x002E)) {
+      LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL0sL1;
+      LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm & AspmL1;
+    }
+  }
+  if (UpstreamDeviceId == 0x10831969) {
+    GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x12F8, AccessS3SaveWidth32, 0xFFF7F7FF, 0, StdHeader);
+  }
+
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
new file mode 100644
index 0000000000..2857a70f29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * PCIe ASPM Black List
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPMBLACKLIST_H_
+#define _PCIEASPMBLACKLIST_H_
+
+///PCIe ASPM Black List
+
+AGESA_STATUS
+PcieAspmBlackListFeature (
+  IN       PCIe_LINK_ASPM         *LinkAsmp,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
new file mode 100644
index 0000000000..744c88b53b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
@@ -0,0 +1,218 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to calculate PCIe topology segment maximum exit latency
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo;
+  PCI_ADDR                DownstreamPort;
+  UINT8                   LinkCount;
+} PCIE_EXIT_LATENCY_DATA;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+SCAN_STATUS
+PcieAspmGetMaxExitLatencyCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine ASPM L-state maximum exit latency for PCIe segment
+ *
+ *  Scan through all link in segment to determine maxim exit latency requirement by EPs.
+ *
+ * @param[in]   DownstreamPort    PCI address of PCIe port
+ * @param[out]  AspmLatencyInfo   Latency info
+ * @param[in]   StdHeader         Standard configuration header
+ *
+ */
+
+VOID
+PcieAspmGetMaxExitLatency (
+  IN       PCI_ADDR                DownstreamPort,
+     OUT   PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_EXIT_LATENCY_DATA  PcieExitLatencyData;
+  PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo;
+  PcieExitLatencyData.ScanData.StdHeader = StdHeader;
+  PcieExitLatencyData.LinkCount = 0;
+  PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieAspmGetMaxExitLatencyCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_EXIT_LATENCY_DATA  *PcieExitLatencyData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT32                  Value;
+  UINT8                   PcieCapPtr;
+  UINT8                   L1AcceptableLatency;
+
+  PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+    PcieExitLatencyData->DownstreamPort = Device;
+    PcieExitLatencyData->LinkCount++;
+    GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData);
+    PcieExitLatencyData->LinkCount--;
+    break;
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+    ASSERT (PcieCapPtr != 0);
+    GnbLibPciRead (
+      Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
+      AccessWidth32,
+      &Value,
+      ScanData->StdHeader
+      );
+    if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) {
+      GnbLibPciRead (
+        Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER),
+        AccessWidth32,
+        &Value,
+        ScanData->StdHeader
+        );
+      L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7));
+      if (PcieExitLatencyData->LinkCount > 1) {
+        L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount;
+      }
+      if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency <  L1AcceptableLatency) {
+        PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency;
+      }
+      IDS_HDT_CONSOLE (PCIE_MISC, "  Device max exit latency  L1 - %d us\n",
+        L1AcceptableLatency
+        );
+    }
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
new file mode 100644
index 0000000000..12c16e5a69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to calculate PCIe topology segment maximum exit latency
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEASPMEXITLATENCY_H_
+#define _PCIEASPMEXITLATENCY_H_
+
+VOID
+PcieAspmGetMaxExitLatency (
+  IN       PCI_ADDR                DownstreamPort,
+     OUT   PCIe_ASPM_LATENCY_INFO  *AspmLatencyInfo,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
new file mode 100644
index 0000000000..77def5281c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
@@ -0,0 +1,334 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MAX_NUM_PHYs          2
+#define MAX_NUM_LANE_PER_PHY  8
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+//Channel Type:              LowLoss / HighLoss / Mob0db / Mob3db / Ext6db / Ext8db
+INT8  chtype_0 /* DeemphasisSel */ [] = {      1,         0,        1,      1,       0,        0};
+INT8  chtype_1 /* DeemphGen1Nom */ [] = {      42,        42,       0,      0,       42,       42};
+INT8  chtype_2 /* DeemPh35Gen2Nom */ [] = {    42,        64,       0,      42,      64,       77};
+INT8  chtype_3 /* Deemph60Gen2NOm */ [] = {    42,        64,       0,      42,      64,       77};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY lane ganging
+ *
+ *
+ *
+ * @param[out] Wrapper             Pointer to internal configuration data area
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT8               GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY];
+  UINT8               MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY];
+  UINT16              LoPhylane;
+  UINT16              HiPhylane;
+  UINT8               Phy;
+  UINT16              Lane;
+  UINT16              PhyLinkWidth;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n");
+  LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie));
+  LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie));
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      HiPhylane = PcieLibGetHiPhyLane (EngineList) - Wrapper->StartPhyLane;
+      LoPhylane = PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
+      PhyLinkWidth = HiPhylane - LoPhylane + 1;
+
+      if (PhyLinkWidth >= 8) {
+        for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) {
+          ((UINT8 *) GangMatrix)[Lane] = 1;
+        }
+      } else {
+        if (PhyLinkWidth > 0 && PhyLinkWidth < 4) {
+          for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) {
+            ((UINT8 *) MasterMatrix)[Lane] = 1;
+          }
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+    for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) {
+      D0F0xE4_PHY_6005_STRUCT  D0F0xE4_PHY_6005;
+      D0F0xE4_PHY_6005.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80),
+                                 Pcie
+                                 );
+      D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane];
+      D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane];
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80),
+        D0F0xE4_PHY_6005.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Point "virtual" PLL clock picker away from PCIe
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to internal configuration data area
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyAvertClockPickers (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  DdiLanes;
+  UINT8   Nibble;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n");
+  DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (DdiLanes & (0xf << (Nibble * 4))) {
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PHY_0009_PCIePllSel_MASK,
+        0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET,
+        FALSE,
+        Pcie
+        );
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK,
+        (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET),
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PHY channel characteristic
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePhyChannelCharacteristic (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG         *Wrapper;
+  UINT16                      StartLane;
+  UINT16                      EndLane;
+  UINT16                      Lane;
+  UINT8                       ChannelType;
+
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  ChannelType = Engine->Type.Port.PortData.ChannelType;
+  StartLane = MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane;
+  EndLane = MAX (Engine->EngineData.StartLane, Engine->EngineData.EndLane) - Wrapper->StartPhyLane;
+
+  PcieRegisterRMW (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0803_ADDRESS + (Engine->Type.Port.PortId) * 0x100),
+    D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK,
+    chtype_0 /* DeemphasisSel */[ChannelType] << D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET,
+    FALSE,
+    Pcie
+    );
+  for (Lane = StartLane; Lane <= EndLane; Lane++) {
+    UINT16 PhyLane;
+    UINT16 Phy;
+    if (Lane < MAX_NUM_LANE_PER_PHY ) {
+      Phy = 0;
+      PhyLane = Lane;
+    } else {
+      Phy = 1;
+      PhyLane = Lane - MAX_NUM_LANE_PER_PHY;
+    }
+    PcieRegisterRMW (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80),
+      D0F0xE4_PHY_6006_DeemphGen1Nom_MASK,
+      chtype_1 /* DeemphGen1Nom */[ChannelType] << D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterRMW (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80),
+      D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK,
+      chtype_2 /* DeemPh35Gen2Nom */[ChannelType] << D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterRMW (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6006_ADDRESS + PhyLane * 0x80),
+      D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK,
+      chtype_3 /* Deemph60Gen2NOm */[ChannelType] << D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DCC recalibration
+ *
+ *
+ *
+ * @param[in]     Wrapper           Pointer to internal configuration data area
+ * @param[in]     Pcie              Pointer to global PCIe configuration
+ */
+
+AGESA_STATUS
+PciePhyForceDccRecalibration (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   Phy;
+  UINT8   PhyLane;
+  for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+    for (PhyLane = 0; PhyLane < MAX_NUM_LANE_PER_PHY; PhyLane++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4001_ADDRESS + PhyLane * 0x80),
+        D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET,
+        D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH,
+        0x1,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
new file mode 100644
index 0000000000..946de59030
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEPHYSERVICES_H_
+#define _PCIEPHYSERVICES_H_
+
+VOID
+PciePhyApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyAvertClockPickers (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePhyChannelCharacteristic (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PciePhyForceDccRecalibration (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
new file mode 100644
index 0000000000..8973820082
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
@@ -0,0 +1,654 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PIF_GANG_0to1  0x1
+#define PIF_GANG_2to3  (0x1 << 1)
+#define PIF_GANG_4to5  (0x1 << 2)
+#define PIF_GANG_6to7  (0x1 << 3)
+#define PIF_GANG_0to3  (0x1 << 4)
+#define PIF_GANG_4to7  (0x1 << 8)
+#define PIF_GANG_0to7  (0x1 << 9)
+#define PIF_GANG_ALL   (0x1 << 25)
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply PIF ganging for all lanes for given wrapper
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG      *EngineList;
+  UINT32                  LaneBitmap;
+  UINT8                   Pif;
+  D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2];
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n");
+  LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie));
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, EngineList);
+      switch (LaneBitmap) {
+      case  0x0003:
+        D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1;
+        break;
+      case  0x000c:
+        D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1;
+        break;
+      case  0x0030:
+        D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1;
+        break;
+      case  0x00c0:
+        D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1;
+        break;
+      case  0x000f:
+        D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1;
+        break;
+      case  0x00f0:
+        D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1;
+        break;
+      case  0x00ff:
+        D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1;
+        break;
+      case  0x0300:
+        D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1;
+        break;
+      case  0x0c00:
+        D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1;
+        break;
+      case  0x3000:
+        D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1;
+        break;
+      case  0xc000:
+        D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1;
+        break;
+      case  0x0f00:
+        D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1;
+        break;
+      case  0xf000:
+        D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1;
+        break;
+      case  0xff00:
+        D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1;
+        break;
+      case  0xffff:
+        D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1;
+        D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1;
+        break;
+      default:
+        break;
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS),
+        D0F0xE4_PIF_0011[Pif].Value,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL powerdown
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllPowerDown (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT16                  NibbleBitmap;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n");
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    NibbleBitmap = (0xF << (Nibble * 4));
+    if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL init for DDI
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifPllInitForDdi (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  UINT32                  LaneBitmap;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n");
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (LaneBitmap & (0xF << (Nibble * 4))) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for on PIF to indicate action completion
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollPifForCompeletion (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  //UINT32                  TimeStamp;
+  UINT8                   Pif;
+  D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015;
+  //TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    do {
+      D0F0xE4_PIF_0015.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS),
+                                 Pcie
+                                 );
+      //if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) {
+      //  break;
+      //}
+    } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable fifo reset
+ *
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+VOID
+PciePifDisableFifoReset (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET,
+      D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program LS2 exit time
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetLs2ExitTime (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET,
+        D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH,
+        0x0,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PLL mode for L1
+ *
+ *
+ * @param[in]  LaneBitmap  Power down PLL for these lanes
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+VOID
+PciePifSetPllModeForL1 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Nibble;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  for (Nibble = 0; Nibble < 4; Nibble++) {
+    if (LaneBitmap & (0xF << (Nibble * 4))) {
+      D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+                                 Pcie
+                                 );
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
+      PcieRegisterWrite (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
+        D0F0xE4_PIF_0012.Value,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program receiver detection power mode
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PciePifSetRxDetectPowerMode (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+        Wrapper,
+        PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+        D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET,
+        D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH,
+        0x1,
+        FALSE,
+        Pcie
+        );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pll ramp up time
+ *
+ *
+ *
+ * @param[in]  Rampup              Ramp up time
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifSetPllRampTime (
+  IN      PCIE_PLL_RAMPUP_TIME  Rampup,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Pif;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
+  D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0013.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0010.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+                               Pcie
+                               );
+    if (Rampup == NormalRampup) {
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
+      D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1;
+      D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0;
+    } else {
+      D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3;
+      D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3;
+      D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010.Value,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down PIFs
+ *
+ *
+ *
+ * @param[in]  Control             Power up or Power down control
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifPllPowerControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8   Pif;
+  UINT8   PllPowerStateInOff;
+  PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET,
+      D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH,
+      PllPowerStateInOff,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET,
+      D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH,
+      PllPowerStateInOff,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down PIFs
+ *
+ *
+ *
+ * @param[in]  Control             Power up/Down control
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePifFullPowerStateControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8                   Pif;
+  D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
+  D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    D0F0xE4_PIF_0012.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+                               Pcie
+                               );
+    D0F0xE4_PIF_0013.Value = PcieRegisterRead (
+                               Wrapper,
+                               PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+                               Pcie
+                               );
+    if (Control == PowerDownPifs) {
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff;
+      D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff;
+    } else {
+      D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2;
+      D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2;
+      D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0;
+      D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
+      D0F0xE4_PIF_0012.Value,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
+      D0F0xE4_PIF_0013.Value,
+      FALSE,
+      Pcie
+      );
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
new file mode 100644
index 0000000000..d0c2a81b73
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
@@ -0,0 +1,147 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe PIF initialization routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEPIFSERVICES_H_
+#define _PCIEPIFSERVICES_H_
+
+VOID
+PciePifApplyGanging (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerDown (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllInitForDdi (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollPifForCompeletion (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifDisableFifoReset (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetLs2ExitTime (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetPllModeForL1 (
+  IN      UINT32                LaneBitmap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetRxDetectPowerMode (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifSetPllRampTime (
+  IN      PCIE_PLL_RAMPUP_TIME  Rampup,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePifPllPowerControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PciePifFullPowerStateControl (
+  IN      PCIE_PIF_POWER_CONTROL  Control,
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
new file mode 100644
index 0000000000..d02fbf6a06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
@@ -0,0 +1,257 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe port indirect register
+ * space.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "PciePortRegAcc.h"
+#include  "GnbCommonLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe port indirect register.
+ *
+ * Support for unify register access through index/data pair on PCIe port
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Register Value
+ */
+
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  Value       New register value
+ * @param[in]  S3Save      Save for S3 flag
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ */
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ASSERT (S3Save == TRUE || S3Save == FALSE);
+
+  IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, "    *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n",
+    Engine->Type.Port.Address.Address.Bus,
+    Engine->Type.Port.Address.Address.Device,
+    Engine->Type.Port.Address.Address.Function,
+    Address,
+    Value
+    );
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  S3Save      Save for S3 flag
+ * @param[in]  Value       New register value
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ */
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Data;
+  UINT32  Mask;
+  Data = PciePortRegisterRead (Engine, Address, Pcie);
+  Mask = (1 << FieldWidth) - 1;
+  Value &= Mask;
+  Data &= (~(Mask << FieldOffset));
+  PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe Port Indirect register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Register Field Value.
+ */
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PciePortRegisterRead (Engine, Address, Pcie);
+  Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1);
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe port register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Engine      Pointer to Engine descriptor for this port
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PciePortRegisterRead (Engine, Address, Pcie);
+  Value = (Value & (~AndMask)) | OrMask;
+  PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
new file mode 100644
index 0000000000..426f3b8cba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe port indirect register space.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTREGACC_H_
+#define _PCIEPORTREGACC_H_
+
+UINT32
+PciePortRegisterRead (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWrite (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterWriteField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PciePortRegisterReadField (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePortRegisterRMW (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      UINT16                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
new file mode 100644
index 0000000000..456b2552cd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
@@ -0,0 +1,533 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set completion timeout
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS,
+    AccessWidth32,
+    0xffffffff,
+    0x6 << DxF0x80_CplTimeoutValue_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_x20_ADDRESS,
+      DxF0xE4_x20_TxFlushTlpDis_OFFSET,
+      DxF0xE4_x20_TxFlushTlpDis_WIDTH,
+      0x0,
+      TRUE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init hotplug port
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  DxF0xE4_xB5_STRUCT  DxF0xE4_xB5;
+  if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
+    DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
+    DxF0xE4_xB5.Field.line521  = 0x3;
+    DxF0xE4_xB5.Field.line522  = 0x3;
+    DxF0xE4_xB5.Field.line519  = 0x1;
+    PciePortRegisterWrite (
+      Engine,
+      DxF0xE4_xB5_ADDRESS,
+      DxF0xE4_xB5.Value,
+      TRUE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
+      D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
+      D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
+      0x5,
+      TRUE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, 0x8011 ),
+      16 ,
+      1 ,
+      0x1,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << DxF0x6C_HotplugCapable_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_x20_ADDRESS,
+      DxF0xE4_x20_TxFlushTlpDis_OFFSET,
+      DxF0xE4_x20_TxFlushTlpDis_WIDTH,
+      0x0,
+      TRUE,
+      Pcie
+      );
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_x70_ADDRESS,
+      DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
+      DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set misc slot capability
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS,
+    AccessWidth32,
+    0xffffffff,
+    1 << DxF0x58_SlotImplemented_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciRMW (
+    Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS,
+    AccessWidth32,
+    0xffffffff,
+    1 << DxF0x3C_IntPin_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Safe mode to force link advertize Gen1 only capability in TS
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  //Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1;
+  PcieFmSetLinkSpeedCap (PcieGen1, Engine, Pcie);
+  PciePortRegisterRMW (
+    Engine,
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcUpconfigureDis_MASK,
+    (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET),
+    FALSE,
+    Pcie
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterRMW (
+    Engine,
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcUpconfigureDis_MASK,
+    0,
+    FALSE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ex548_STRUCT   ex548 ;
+  DxF0xE4_xC0_STRUCT  DxF0xE4_xC0;
+  DxF0x88_STRUCT      DxF0x88;
+  GnbLibPciRead (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+  ex548.Value = PciePortRegisterRead (
+                        Engine,
+                        0xa4 ,
+                        Pcie
+                        );
+  DxF0xE4_xC0.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xC0_ADDRESS,
+                        Pcie
+                        );
+
+  switch (LinkSpeedCapability) {
+  case PcieGen2:
+    ex548.Field.LcGen2EnStrap = 0x1;
+    ex548.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
+    DxF0x88.Field.TargetLinkSpeed = 0x2;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
+    break;
+  case PcieGen1:
+    ex548.Field.LcGen2EnStrap = 0x0;
+    ex548.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
+    DxF0x88.Field.TargetLinkSpeed = 0x1;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+  PciePortRegisterWrite (
+    Engine,
+    0xa4 ,
+    ex548.Value,
+    FALSE,
+    Pcie
+    );
+  PciePortRegisterWrite (
+    Engine,
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0.Value,
+    FALSE,
+    Pcie
+    );
+  GnbLibPciWrite (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Force compliance
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) {
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+      AccessWidth32,
+      0xffffffff,
+      0x1 << DxF0x88_EnterCompliance_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+  } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) {
+    PciePortRegisterWriteField (
+      Engine,
+      DxF0xE4_xC0_ADDRESS,
+      DxF0xE4_xC0_StrapForceCompliance_OFFSET,
+      DxF0xE4_xC0_StrapForceCompliance_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set slot power limit
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @param[in]  Pcie                Pointer to PCIe configuration
+ */
+
+
+VOID
+PcieEnableSlotPowerLimit (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !PcieConfigIsSbPcieEngine (Engine)) {
+    IDS_HDT_CONSOLE (PCIE_MISC, "   Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
+    GnbLibPciIndirectRMW (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      (0x51  + (Engine->Type.Port.Address.Address.Device - 2) * 2) | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      0xffffffff,
+      1 << 20 ,
+      GnbLibGetHeader (Pcie)
+    );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable ASPM on SB link
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) {
+    if (PcieConfigIsSbPcieEngine (Engine)) {
+      SbPcieLinkAspmControl (Engine, Pcie);
+    }
+  }
+}
+
+
+UINT8 L1State = 0x1b;
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for link to get into L1
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkHwStateHistory[8];
+  do {
+    PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie);
+  } while (!PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), &L1State, sizeof (L1State)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Poll for link to get into L1
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkHwStateHistory[4];
+  do {
+    PcieUtilGetLinkHwStateHistory (Engine, &LinkHwStateHistory[0], sizeof (LinkHwStateHistory), Pcie);
+  } while (LinkHwStateHistory[0] != 0x10);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
new file mode 100644
index 0000000000..9ac8ce8346
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTSERVICES_H_
+#define _PCIEPORTSERVICES_H_
+
+
+VOID
+PcieSetLinkSpeedCap (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetLinkWidthCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSafeMode (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieCompletionTimeout (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkSetSlotCap (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieLinkInitHotplug (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieForceCompliance (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieEnableSlotPowerLimit (
+  IN      PCIe_ENGINE_CONFIG     *Engine,
+  IN      PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieEnableAspm (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL1Entry (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePollLinkForL0Exit (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
new file mode 100644
index 0000000000..f15a582b5b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
@@ -0,0 +1,424 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes and plls
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrPowerDownUnusedLanes (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT32              UnusedLanes;
+  UINT32              AllLanes;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n");
+  if (Wrapper->Features.PowerOffUnusedPlls != 0) {
+    AllLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper);
+    UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Wrapper);
+    if (AllLanes != UnusedLanes) {
+      //Some lanes end up beeing used. We should keep master PLL powered up
+      UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, Wrapper);
+    }
+    PciePifPllPowerDown (
+      UnusedLanes,
+      Wrapper,
+      Pcie
+      );
+  }
+  if (Wrapper->Features.PowerOffUnusedLanes != 0) {
+    UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE, Wrapper);
+    PcieTopologyLaneControl (
+      DisableLanes,
+      UnusedLanes,
+      Wrapper,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lane bitmam to enable PLL power down in L1
+ *
+ *
+ * @param[in]  PllPowerUpLatency  Pointer to wrapper config descriptor
+ * @param[in]  Wrapper            Pointer to wrapper config descriptor
+ * @param[in]  Pcie               Pointer to global PCIe configuration
+ * @retval     Lane bitmap for which PLL can be powered down in L1
+ */
+
+UINT32
+PcieLanesToPowerDownPllInL1 (
+  IN       UINT8                  PllPowerUpLatency,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT8               LaneGroupExitLatency [4];
+  UINT32              LaneBitmapForPllOffInL1;
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINTN               Index;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n");
+  LaneBitmapForPllOffInL1 = 0;
+  if (PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper) != 0) {
+    if (Wrapper->Features.PllOffInL1 != 0) {
+      LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie));
+      EngineList = PcieConfigGetChildEngine (Wrapper);
+      while (EngineList != NULL) {
+        PCIe_ASPM_LATENCY_INFO  LinkLatencyInfo;
+        UINT32                  ActiveLanesBitmap;
+        UINT32                  HotplugLanesBitmap;
+        if (EngineList->EngineData.EngineType == PciePortEngine) {
+          LinkLatencyInfo.MaxL1ExitLatency = 0;
+          LinkLatencyInfo.MaxL0sExitLatency = 0;
+          ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, EngineList);
+          HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, EngineList);
+          if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !PcieConfigIsSbPcieEngine (EngineList)) {
+            PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
+          }
+          if (HotplugLanesBitmap != 0 || PcieConfigIsSbPcieEngine (EngineList)) {
+            LinkLatencyInfo.MaxL1ExitLatency = 0xff;
+          }
+          IDS_HDT_CONSOLE (GNB_TRACE, "  Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap);
+          for (Index = 0; Index < 4; Index++) {
+            if ((ActiveLanesBitmap  & (0xF << (Index * 4))) != 0) {
+              if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) {
+                IDS_HDT_CONSOLE (GNB_TRACE, "  Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
+                LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency;
+              }
+            }
+          }
+        }
+        EngineList = PcieLibGetNextDescriptor (EngineList);
+      }
+      LaneBitmapForPllOffInL1 = 0;
+      for (Index = 0; Index < 4; Index++) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
+        if (LaneGroupExitLatency[Index] > PllPowerUpLatency) {
+          LaneBitmapForPllOffInL1 |= (0xF << (Index * 4));
+        }
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "  Lane bitmap %04x\n", LaneBitmapForPllOffInL1);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n");
+  return LaneBitmapForPllOffInL1;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Auto-Power Down electrical Idle detector
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrAutoPowerDownElectricalIdleDetector (
+  IN       PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  UINT8   Pif;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n");
+  for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
+      D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
+      0x0,
+      TRUE,
+      Pcie
+      );
+
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, 0x10 ),
+      20 ,
+      3 /*D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH*/,
+      0x2,
+      TRUE,
+      Pcie
+      );
+
+    PcieRegisterWriteField (
+      Wrapper,
+      PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
+      D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
+      D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
+      0x1,
+      TRUE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clock gating
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrClockGating (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  ex501_STRUCT   ex501 ;
+  D0F0xE4_WRAP_8012_STRUCT  D0F0xE4_WRAP_8012;
+  D0F0xE4_WRAP_8014_STRUCT  D0F0xE4_WRAP_8014;
+  D0F0xE4_WRAP_8015_STRUCT  D0F0xE4_WRAP_8015;
+  ex688_STRUCT   ex688 ;
+  UINT8                     CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
+  D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+                              Pcie
+                              );
+
+  D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+                              Pcie
+                              );
+
+  ex501.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, 0x8011 ),
+                              Pcie
+                              );
+
+  if (Wrapper->Features.ClkGating == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
+
+
+    ex501.Field.TxclkDynGateEnable = 0x1;
+    ex501.Field.TxclkRegsGateEnable = 0x1;
+    ex501.Field.TxclkLcntGateEnable = 0x1;
+    ex501.Field.RcvrDetClkEnable = 0x1;
+    ex501.Field.TxclkPermGateEven = 0x1;
+    ex501.Field.TxclkDynGateLatency = 0x3f;
+    ex501.Field.TxclkRegsGateLatency = 0x3f;
+    ex501.Field.TxclkPermGateLatency = 0x3f;
+
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
+
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
+
+    D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
+  }
+  if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+    D0F0xE4_WRAP_8014.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+    D0F0xE4_WRAP_8015.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+    D0F0xE4_WRAP_8012.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, 0x8011 ),
+    ex501.Value,
+    TRUE,
+    Pcie
+    );
+  for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      CORE_SPACE (CoreId, 0x11 ),
+      0 ,
+      4 ,
+      0xf,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Wrapper->Features.LclkGating == 0x1) {
+    ex688.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, 0x8016 ),
+                                Pcie
+                                );
+    ex688.Field.LclkDynGateEnable = 0x1;
+    ex688.Field.LclkGateFree = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, 0x8016 ),
+      ex688.Value,
+      TRUE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
new file mode 100644
index 0000000000..3d237e0e81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERSAVINGFEATURES_H_
+#define _PCIEPOWERSAVINGFEATURES_H_
+
+
+VOID
+PciePwrPowerDownUnusedLanes (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieLanesToPowerDownPllInL1 (
+  IN       UINT8                  PllPowerUpLatency,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PciePwrAutoPowerDownElectricalIdleDetector (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePwrClockGating (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
new file mode 100644
index 0000000000..56b4aa71a0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieService.esl
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 49911 $   @e \$Date: 2011-03-30 02:43:29 -0700 (Wed, 30 Mar 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Get current link speed
+   *
+   *  Arg0 - Port Index
+   *
+   */
+
+
+  Method (procPciePortGetCurrentLinkSpeed, 1, NotSerialized) {
+    Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcLinkCtrlLocal1)
+    ShiftRight (varLcLinkCtrlLocal1, 11, varCurrenLinkSpeedLocal2)
+    And (varCurrenLinkSpeedLocal2, 0x1, varCurrenLinkSpeedLocal2)
+    Increment (varCurrenLinkSpeedLocal2)
+    return (varCurrenLinkSpeedLocal2)
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
new file mode 100644
index 0000000000..010aae492c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
@@ -0,0 +1,284 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe complex initialization services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Gen1 voltage Index
+ *
+ *
+ *
+ *
+ * @param[in]  StdHeader           Standard configuration header
+ */
+UINT8
+PcieSiliconGetGen1VoltageIndex (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8   Index;
+  UINT8   Gen1VidIndex;
+  UINT8   SclkVidArray[4];
+  GnbLibPciRead (
+    MAKE_SBDFO ( 0, 0, 0x18, 3, 0x15c ),
+    AccessWidth32,
+    &SclkVidArray[0],
+    StdHeader
+    );
+  Gen1VidIndex = 0;
+  for (Index = 0; Index < 4; Index++) {
+    if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
+      Gen1VidIndex = Index;
+    }
+  }
+  return Gen1VidIndex;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request Pcie voltage change
+ *
+ *
+ *
+ * @param[in]  VidIndex            The request VID index
+ * @param[in]  StdHeader           Standard configuration header
+ */
+VOID
+PcieSiliconRequestVoltage (
+  IN      UINT8                 VidIndex,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  ex488_STRUCT     ex488 ;
+  ex489_STRUCT     ex489 ;
+
+  //Enable voltage client
+  GnbLibPciIndirectRead (
+    MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+    0x6a  | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &ex488.Value,
+    StdHeader
+  );
+
+  ex488.Field.VoltageChangeEn = 0x1;
+
+  GnbLibPciIndirectWrite (
+    MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+    0x6a  | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &ex488.Value,
+    StdHeader
+  );
+
+  ex488.Field.VoltageLevel = VidIndex;
+  ex488.Field.VoltageChangeReq = !ex488.Field.VoltageChangeReq;
+
+  GnbLibPciIndirectWrite (
+    MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+    0x6a  | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &ex488.Value,
+    StdHeader
+    );
+  do {
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      0x6b  | IOC_WRITE_ENABLE,
+      AccessS3SaveWidth32,
+      &ex489.Value,
+      StdHeader
+    );
+  } while (ex488.Field.VoltageChangeReq != ex489.Field.VoltageChangeAck);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Unhide all ports
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configuration descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieSiliconUnHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
+    0x0,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~BIT6,
+    BIT6,
+    GnbLibGetHeader (Pcie)
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Hide unused ports
+ *
+ *
+ *
+ * @param[in]  Silicon             Pointer to silicon configuration data area
+ * @param[in]  Pcie                Pointer to data area up to 256 byte
+ */
+
+VOID
+PcieSiliconHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0x64_x0C_STRUCT    D0F0x64_x0C;
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  D0F0x64_x0C.Value =  0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Enter\n");
+
+  D0F0x64_x0C.Value =  BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7;
+  WrapperList = PcieConfigGetChildWrapper (Silicon);
+  while (WrapperList != NULL) {
+    PCIe_ENGINE_CONFIG   *EngineList;
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieConfigIsPcieEngine (EngineList)) {
+        if (PcieConfigIsActivePcieEngine (EngineList) && !PcieConfigIsSbPcieEngine (EngineList)) {
+          D0F0x64_x0C.Value &= ~(1 << EngineList->Type.Port.Address.Address.Device);
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    WrapperList = PcieLibGetNextDescriptor (WrapperList);
+  }
+
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
+    D0F0x64_x0C.Value,
+    GnbLibGetHeader (Pcie)
+    );
+  GnbLibPciIndirectRMW (
+    Silicon->Address.AddressValue | D0F0x60_ADDRESS,
+    D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    (UINT32)~BIT6,
+    0x0,
+    GnbLibGetHeader (Pcie)
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n");
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
new file mode 100644
index 0000000000..22d07a113d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
@@ -0,0 +1,99 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Complex Services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIESILICONSERVICES_H_
+#define _PCIESILICONSERVICES_H_
+
+UINT8
+PcieSiliconGetGen1VoltageIndex (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+PcieSiliconRequestVoltage (
+  IN      UINT8                 VidIndex,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+PcieSiliconUnHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconHidePorts (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
new file mode 100644
index 0000000000..3c46ef675b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
@@ -0,0 +1,244 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU indirect register read
+   *
+   *  Arg0 - Smu register offset
+   *
+   */
+  Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) {
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
+    // Access 32 bit width
+    Increment (Arg0)
+    // Reverse ReqToggle
+    Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
+    // Assign Address and ReqType = 0
+    Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0)
+
+    procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
+
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU indirect register Write
+   *
+   *  Arg0 - Smu register offset
+   *  Arg1 - Value
+   *  Arg2 - Width, 0 = 16, 1 = 32
+   *
+   */
+  Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) {
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
+    // Get low 16 bit value
+    Store (And (Arg1, 0xFFFF), Local1)
+    // Reverse ReqToggle
+    Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
+    // Assign Address
+    Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0)
+    // ReqType = 1
+    Or (Local0, 0x02000000, Local0)
+    // Assign Low 16 bit value
+    Or (Local0, Local1, Local0)
+
+    procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
+
+    if (LEqual (Arg2, 1)) {
+      // Get high 16 bit value
+      Store (ShiftRight (Arg1, 16), Local1)
+      // Reverse ReqToggle
+      Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
+      // Assign Address
+      Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0)
+      // Assign High 16 bit value
+      Or (Local0, Local1, Local0)
+
+      procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
+    }
+
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU Service request
+   *
+   *  Arg0 - Smu service id
+   *  Arg1 - Flags - Poll Ack = 1, Poll down = 2
+   *
+   */
+  Method (procNbSmuServiceRequest, 2, NotSerialized) {
+    Store ("NbSmuServiceRequest Enter", Debug)
+    Store ("Request id =", Debug)
+    Store (Arg0, Debug)
+
+    Or (ShiftLeft (Arg0, 3), 0x1, Local0)
+    procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
+
+    if (LAnd (Arg1, 1)) {
+      while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
+        Store ("--Wait Ack--", Debug)
+      }
+    }
+    if (LAnd (Arg1, 2)) {
+      while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) {
+        Store ("--Wait Done--", Debug)
+      }
+    }
+    // Clear IRQ register
+    procNbSmuIndirectRegisterWrite (0x3, 0, 1)
+    Store ("NbSmuServiceRequest Exit", Debug)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Write RCU register
+   *
+   *  Arg0 - Register Address
+   *  Arg1 - Register Data
+   *
+   */
+  Method (procSmuRcuWrite, 2, NotSerialized) {
+     procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
+     procNbSmuIndirectRegisterWrite (0x5, Arg1, 1)
+
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  Read RCU register
+   *
+   *  Arg0  - Register Address
+   *  Retval    - RCU register value
+   */
+  Method (procSmuRcuRead, 1, NotSerialized) {
+    procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
+    Store (procNbSmuIndirectRegisterRead (0x5), Local0)
+    return (Local0)
+  }
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU SRBM Register Read
+   *
+   *  Arg0 - FCR register address
+   *
+   */
+  Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) {
+    //SMUx0B_x8600
+    Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
+    //SMUx0B_x8604
+    Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
+    //SMUx0B_x8608
+    Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
+    //Write SMU RCU
+    procSmuRcuWrite (0x8600, Local0)
+    procSmuRcuWrite (0x8604, Local1)
+    procSmuRcuWrite (0x8608, Local2)
+    // ServiceId
+    if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) {
+      procNbSmuServiceRequest (0xD, 0x3)
+    }
+    if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) {
+      procNbSmuServiceRequest (0xB, 0x3)
+    }
+    return (procSmuRcuRead(0x8650))
+  }
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU SRBM Register Write
+   *
+   *  Arg0 - FCR register address
+   *  Arg1 - Value
+   *
+   */
+  Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) {
+    //SMUx0B_x8600
+    Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
+    //SMUx0B_x8604
+    Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
+    //SMUx0B_x8608
+    Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
+    Or (Local2, ShiftLeft (1, 16), Local2)
+    //Write SMU RCU
+    procSmuRcuWrite (0x8600, Local0)
+    procSmuRcuWrite (0x8604, Local1)
+    procSmuRcuWrite (0x8608, Local2)
+    //Write Data
+    procSmuRcuWrite (0x8650, Arg1)
+    // ServiceId
+    procNbSmuServiceRequest (0xB, 0x3)
+  }
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl
new file mode 100644
index 0000000000..14a474d0e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuVidReq.esl
@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 61048 $   @e \$Date: 2011-10-31 12:20:41 +0800 (Mon, 31 Oct 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Request VID
+   *
+   *  Arg0 - 1 - GEN1 2 - GEN2
+   *  Arg1 - 0 = do not wait intil voltage is set
+   *         1 = wait until voltage is set
+   */
+  Method (procPcieSetVoltage, 2, Serialized) {
+    Store ("PcieSetVoltage Enter", Debug)
+    Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1)
+    //Enable voltage change
+    Or (Local1, 0x2, Local1)
+    procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
+    //Clear voltage index
+    And (Local1, Not (ShiftLeft (0x3, 3)), Local1)
+
+    if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) {
+      Store (varGen1Vid, Local3)
+    } else {
+      Store (varGen2Vid, Local3)
+    }
+
+    Store (Concatenate ("  Voltage Index:", ToHexString (Local3), Local6), Debug)
+    //Set new voltage index
+    Or (Local1, ShiftLeft (Local3, 3), Local1)
+    //Togle request
+    And (Not (Local1), 0x4, Local2)
+    Or (And (Local1, Not (0x4)), Local2, Local1)
+    procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
+    if (LNotEqual (Arg1, 0)) {
+      while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
+        And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1)
+      }
+    }
+    Store ("PcieSetVoltage Exit", Debug)
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
new file mode 100644
index 0000000000..49cea04a02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe timer access procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbTimerLib.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCIe timer timestamp
+ *
+ *
+ *
+ * @param[in]  Pcie        Pointer to internal configuration data area
+ * @retval                 Time stamp value
+ */
+
+UINT32
+PcieTimerGetTimeStamp (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  return GnbLibTimeStamp (GnbLibGetHeader (Pcie));
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
new file mode 100644
index 0000000000..dfdf414f71
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe timer access procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETIMER_H_
+#define _PCIETIMER_H_
+
+UINT32
+PcieTimerGetTimeStamp (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2))
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
new file mode 100644
index 0000000000..0a9c7b3fed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
@@ -0,0 +1,804 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 66529 $   @e \$Date: 2012-03-09 08:32:22 -0600 (Fri, 09 Mar 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Cleanup reconfig
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyCleanUpReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062_ConfigXferMode_MASK,
+      1 << D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare for reconfiguration
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyPrepareForReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  UINT8                     CoreId;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        CORE_SPACE (CoreId, 0x11 ),
+        0 ,
+        4 ,
+        0xf,
+        FALSE,
+        Pcie
+        );
+    }
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                 Wrapper,
+                                 WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                 Pcie
+                                 );
+
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
+    D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+
+UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate mux array index
+ *
+ *
+ *
+ * @param[in, out]  LaneMuxSelectorArrayPtr     Pointer to mux selector array
+ * @param[in]       LaneMuxValue                The value that match to array
+ * @retval          Index                       Index successfully mapped
+ */
+STATIC UINT8
+PcieTopologyLocateMuxIndex (
+  IN OUT   UINT8 *LaneMuxSelectorArrayPtr,
+  IN       UINT8  LaneMuxValue
+  )
+{
+  UINT8  Index;
+  for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) {
+    if (LaneMuxSelectorArrayPtr [Index] ==  LaneMuxValue) {
+      return Index;
+    }
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Apply lane mux
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieTopologyApplyLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  UINT8               CurrentPhyLane;
+  UINT8               CurrentCoreLane;
+  UINT8               CoreLaneIndex;
+  UINT8               PhyLaneIndex;
+  UINT8               NumberOfPhyLane;
+  UINT8               TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
+  UINT8               RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
+  UINT8               Index;
+  UINT32              TxMaxSelectorValue;
+  UINT32              RxMaxSelectorValue;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n");
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    EngineList = PcieConfigGetChildEngine (Wrapper);
+    LibAmdMemCopy (
+      &TxLaneMuxSelectorArray[0],
+      &LaneMuxSelectorTable[0],
+      sizeof (LaneMuxSelectorTable),
+      GnbLibGetHeader (Pcie)
+      );
+    LibAmdMemCopy (
+      &RxLaneMuxSelectorArray[0],
+      &LaneMuxSelectorTable[0],
+      sizeof (LaneMuxSelectorTable),
+      GnbLibGetHeader (Pcie)
+      );
+    while (EngineList != NULL) {
+      if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
+        CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
+        NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
+        CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
+        if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
+          CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane;
+        }
+        for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) {
+          CoreLaneIndex = (CurrentCoreLane + Index) / 2;
+          PhyLaneIndex = (CurrentPhyLane + Index) / 2;
+
+          if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) {
+            RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex];
+            RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex;
+          }
+          if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) {
+            TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] =  TxLaneMuxSelectorArray [PhyLaneIndex];
+            TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex;
+          }
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+    RxMaxSelectorValue = 0;
+    TxMaxSelectorValue = 0;
+    for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) {
+      RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4));
+      TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4));
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS),
+      TxMaxSelectorValue,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS),
+      RxMaxSelectorValue,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Select master PLL
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[out] ConfigChanged       Pointer to boolean indicator that configuration was changed
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieTopologySelectMasterPll (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  UINT16                    MasterLane;
+  UINT16                    MasterHotplugLane;
+  D0F0xE4_WRAP_8013_STRUCT  D0F0xE4_WRAP_8013;
+  D0F0xE4_WRAP_8013_STRUCT  D0F0xE4_WRAP_8013_BASE;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
+  MasterLane = 0xFFFF;
+  MasterHotplugLane = 0xFFFF;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) {
+      if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+        MasterHotplugLane = PcieConfigGetPcieEngineMasterLane (EngineList);
+      } else {
+        MasterLane = PcieConfigGetPcieEngineMasterLane (EngineList);
+        if (PcieConfigIsSbPcieEngine (EngineList)) {
+          break;
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+
+  if (MasterLane == 0xffff) {
+    if (MasterHotplugLane != 0xffff) {
+      MasterLane = MasterHotplugLane;
+    } else {
+      MasterLane = 0x0;
+    }
+  }
+
+  D0F0xE4_WRAP_8013.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value;
+  if ( MasterLane <= 3 ) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xA;
+  } else if (MasterLane <= 7) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xB;
+  } else if (MasterLane <= 11) {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
+    Wrapper->MasterPll = 0xC;
+  } else {
+    D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
+    D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1;
+    Wrapper->MasterPll = 0xD;
+  }
+  if (ConfigChanged != NULL) {
+    *ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
+    D0F0xE4_WRAP_8013.Value,
+    FALSE,
+    Pcie
+    );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute/clean up reconfiguration
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyExecuteReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  D0F0xE4_WRAP_8060_STRUCT  D0F0xE4_WRAP_8060;
+
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n");
+
+    PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+                                Pcie
+                                );
+
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+      D0F0xE4_WRAP_8060.Value,
+      FALSE,
+      Pcie
+      );
+    do {
+      D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
+                                  Wrapper,
+                                  WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
+                                  Pcie
+                                  );
+
+    } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1);
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable lane reversal
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologySetLinkReversal (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n");
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (PcieLibIsPcieEngine (EngineList)) {
+        if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) {
+            PciePortRegisterWriteField (
+              EngineList,
+              0xc1 ,
+              4 ,
+              1 ,
+              0x1,
+              FALSE,
+              Pcie
+              );
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Reduce link width
+ *
+ *
+ * @param[in]  LinkWidth           Link width
+ * @param[in]  Engine              Pointer to Engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyReduceLinkWidth (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG       *Wrapper;
+  UINT32                    LinkReversed;
+  UINT8                     DeltaLinkWidthBitmap;
+  UINT32                    LanesToDisable;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
+
+  DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
+  LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane +  LinkWidth)));
+
+  PcieTopologyLaneControl (
+    DisableLanes,
+    LanesToDisable,
+    Wrapper,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lanes enable/disable control
+ *
+ * @param[in]   Control             Lane control action
+ * @param[in]   LaneBitMap          Core lanes bitmap
+ * @param[in]   Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyLaneControl (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+    )
+{
+  D0F0xE4_WRAP_8023_STRUCT  D0F0xE4_WRAP_8023;
+  D0F0xE4_WRAP_8023.Value = PcieRegisterRead (
+                            Wrapper,
+                            WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
+                            Pcie
+                            );
+
+  if (Control == EnableLanes) {
+    D0F0xE4_WRAP_8023.Value |= LaneBitMap;
+  } else if (Control == DisableLanes) {
+    D0F0xE4_WRAP_8023.Value &= (~LaneBitMap);
+  }
+  D0F0xE4_WRAP_8023.Value &= ((1 << Wrapper->NumberOfLanes) - 1);
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
+    D0F0xE4_WRAP_8023.Value,
+    TRUE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SRBM reset
+ *
+ * @param[in]  SrbmResetEnable     SRBM reset enable flag.
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyInitSrbmReset (
+  IN      BOOLEAN               SrbmResetEnable,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8063_STRUCT  D0F0xE4_WRAP_8063;
+  D0F0xE4_WRAP_8063.Value = PcieRegisterRead (
+                               Wrapper,
+                               WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS),
+                               Pcie
+                               );
+  if (SrbmResetEnable) {
+    D0F0xE4_WRAP_8063.Field.line331  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line332  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line338  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line339  = 0x1;
+    D0F0xE4_WRAP_8063.Field.line340  = 0x1;
+  } else {
+    D0F0xE4_WRAP_8063.Field.line331  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line332  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line338  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line339  = 0x0;
+    D0F0xE4_WRAP_8063.Field.line340  = 0x0;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8063_ADDRESS),
+    D0F0xE4_WRAP_8063.Value,
+    FALSE,
+    Pcie
+    );
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set core configuration according to PCIe port topology
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[out] ConfigChanged       Pointer to boolean indicator that configuration was changed
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+PcieTopologySetCoreConfig (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                     CoreId;
+  AGESA_STATUS              Status;
+  D0F0xE4_WRAP_0080_STRUCT  D0F0xE4_WRAP_0080;
+
+  Status = AGESA_SUCCESS;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      UINT64  ConfigurationSignature;
+      UINT8   NewConfigurationValue;
+      ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
+      Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
+      if (Status == AGESA_SUCCESS) {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
+          PcieFmDebugGetWrapperNameString (Wrapper),
+          CoreId,
+          PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
+          );
+        D0F0xE4_WRAP_0080.Value = PcieRegisterRead (
+                                    Wrapper,
+                                    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
+                                    Pcie
+                                    );
+        if (ConfigChanged != NULL) {
+          if (D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig != NewConfigurationValue) {
+            *ConfigChanged = TRUE;
+          }
+        }
+        D0F0xE4_WRAP_0080.Field.StrapBifLinkConfig = NewConfigurationValue;
+        PcieRegisterWrite (
+          Wrapper,
+          WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
+          D0F0xE4_WRAP_0080.Value,
+          FALSE,
+          Pcie
+          );
+      } else {
+        IDS_HDT_CONSOLE (PCIE_MISC, "  ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
+          PcieFmDebugGetWrapperNameString (Wrapper),
+          ((UINT32*)&ConfigurationSignature)[1],
+          ((UINT32*)&ConfigurationSignature)[0]
+          );
+        PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+      }
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Relinquish control to DDI for specific lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PcieSetDdiOwnPhy (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  ex502_STRUCT   ex502 ;
+  UINT32                    LaneBitmap;
+
+  if (PcieLibIsDdiWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n");
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    ex502.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, 0x8040 ),
+                                Pcie
+                                );
+    if ((LaneBitmap & BIT0) != 0) {
+      ex502.Field.OwnPhyA = 0x1;
+    }
+    if ((LaneBitmap & BIT4) != 0) {
+      ex502.Field.OwnPhyB = 0x1;
+    }
+    if ((LaneBitmap & BIT8) != 0) {
+      ex502.Field.OwnPhyC = 0x1;
+    }
+    if ((LaneBitmap & BIT12) != 0) {
+      ex502.Field.OwnPhyD = 0x1;
+    }
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, 0x8040 ),
+      ex502.Value,
+      FALSE,
+      Pcie
+      );
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set TX control for PCIe lanes
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieWrapSetTxS1CtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8025_STRUCT  D0F0xE4_WRAP_8025;
+  UINT32                    LaneBitmap;
+  UINTN                     Index;
+  D0F0xE4_WRAP_8025.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+                              Pcie
+                              );
+  Index = 0;
+  LaneBitmap =  PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
+  while (LaneBitmap != 0) {
+    if ((LaneBitmap & 0xf) != 0) {
+      D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8)));
+      D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8));
+    }
+    LaneBitmap >>= 4;
+    ++Index;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+    D0F0xE4_WRAP_8025.Value,
+    FALSE,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set TX control for lane muxes
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieWrapSetTxOffCtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+    0x1f1f1f1f,
+    FALSE,
+    Pcie
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
new file mode 100644
index 0000000000..59c4ffcd94
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe topology initialization service procedures.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETOPOLOGYSERVICES_H_
+#define _PCIETOPOLOGYSERVICES_H_
+
+/// Lane Control
+typedef enum {
+  EnableLanes,              ///< Enable Lanes
+  DisableLanes              ///< Disable Lanes
+} LANE_CONTROL;
+
+VOID
+PcieTopologyCleanUpReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyPrepareForReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+AGESA_STATUS
+PcieTopologySetCoreConfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT  BOOLEAN               *ConfigChanged,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyApplyLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+ );
+
+VOID
+PcieTopologySelectMasterPll (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+     OUT   BOOLEAN               *ConfigChanged,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyExecuteReconfig (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologySetLinkReversal (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+
+VOID
+PcieTopologyReduceLinkWidth (
+  IN      UINT8                 LinkWidth,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyLaneControl (
+  IN      LANE_CONTROL          Control,
+  IN      UINT32                LaneBitMap,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTopologyInitSrbmReset (
+  IN      BOOLEAN               SrbmResetEnable,
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetDdiOwnPhy (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieWrapSetTxS1CtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieWrapSetTxOffCtrlForLaneMux (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
new file mode 100644
index 0000000000..29dc02473b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
@@ -0,0 +1,688 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe utility. Various supporting functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/// Lane type
+typedef enum {
+  LaneTypeCore,         ///< Core Lane
+  LaneTypePhy,          ///< Package Phy Lane
+  LaneTypeNativePhy     ///< Native Phy Lane
+} LANE_TYPE;
+
+/// Lane Property
+typedef enum {
+  LanePropertyConfig,   ///< Configuration
+  LanePropertyActive,   ///< Active
+  LanePropertyAllocated ///< Allocated
+} LANE_PROPERTY;
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct {
+  UINT32               Flags;
+  PCIE_LINK_SPEED_CAP  LinkSpeedCapability;
+} PCIE_GLOBAL_GEN_CAP_WORKSPACE;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link state history from HW state machine
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @param[out]  History             Buffer to save history
+ * @param[in]   Length              Buffer length
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieUtilGetLinkHwStateHistory (
+  IN       PCIe_ENGINE_CONFIG        *Engine,
+     OUT   UINT8                     *History,
+  IN       UINT8                     Length,
+  IN       PCIe_PLATFORM_CONFIG      *Pcie
+  )
+{
+  UINT8   ReadLength;
+  UINT32  LocalHistory [6];
+  UINT16  Index;
+  ASSERT (Length <= 16);
+  ASSERT (Length > 0);
+  if (Length > 6*4) {
+    Length = 6*4;
+  }
+  ReadLength = (Length + 3) / 4;
+  for (Index = 0; Index < ReadLength; Index++) {
+    LocalHistory[Index] = PciePortRegisterRead (
+                            Engine,
+                            DxF0xE4_xA5_ADDRESS + Index,
+                            Pcie
+                            );
+  }
+  LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Search array for specific pattern
+ *
+ *
+ * @param[in]  Buf1           Pointer to source buffer which will be subject of search
+ * @param[in]  Buf1Length     Length of the source buffer
+ * @param[in]  Buf2           Pointer to pattern buffer
+ * @param[in]  Buf2Length     Length of the pattern buffer
+ * @retval     TRUE           Pattern found
+ * @retval     TRUE           Pattern not found
+ */
+
+BOOLEAN
+PcieUtilSearchArray (
+  IN      UINT8                         *Buf1,
+  IN      UINTN                         Buf1Length,
+  IN      UINT8                         *Buf2,
+  IN      UINTN                         Buf2Length
+  )
+{
+  UINT8 *CurrentBuf1Ptr;
+  CurrentBuf1Ptr = Buf1;
+  while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
+    UINT8 *SourceBufPtr;
+    UINT8 *PatternBufPtr;
+    UINTN PatternBufLength;
+    SourceBufPtr = CurrentBuf1Ptr;
+    PatternBufPtr = Buf2;
+    PatternBufLength = Buf2Length;
+    while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
+    if (PatternBufLength == 0) {
+      return TRUE;
+    }
+    CurrentBuf1Ptr++;
+  }
+  return FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link reversed
+ *
+ *
+ * @param[in]  HwLinkState  Check for HW auto link reversal
+ * @param[in]  Engine       Pointer to engine config descriptor
+ * @param[in]  Pcie         Pointer to PCIe config descriptor
+ * @retval                 TRUE if link reversed
+ */
+BOOLEAN
+PcieUtilIsLinkReversed (
+  IN      BOOLEAN               HwLinkState,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 LinkReversal;
+
+  LinkReversal  = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0;
+  if (HwLinkState)  {
+    DxF0xE4_x50_STRUCT  DxF0xE4_x50;
+    DxF0xE4_x50.Value = PciePortRegisterRead (
+                          Engine,
+                          DxF0xE4_x50_ADDRESS,
+                          Pcie
+                          );
+    LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal;
+  }
+  return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link width detected during training
+ *
+ *
+ *
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ * @retval                          Link width
+ */
+UINT8
+PcieUtilGetLinkWidth (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8               LinkWidth;
+  DxF0xE4_xA2_STRUCT  DxF0xE4_xA2;
+  DxF0xE4_xA2.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xA2_ADDRESS,
+                        Pcie
+                        );
+  switch (DxF0xE4_xA2.Field.LcLinkWidthRd) {
+  case 0x6:
+    LinkWidth = 16;
+    break;
+  case 0x5:
+    LinkWidth = 12;
+    break;
+  case 0x4:
+    LinkWidth = 8;
+    break;
+  case 0x3:
+    LinkWidth = 4;
+    break;
+  case 0x2:
+    LinkWidth = 2;
+    break;
+  case 0x1:
+    LinkWidth = 1;
+    break;
+  default:
+    LinkWidth = 0;
+  }
+  return LinkWidth;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of PCIE engine lane of requested type
+ *
+ *
+ * @param[in]   LaneType            Lane type
+ * @param[in]   LaneProperty        Lane Property
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetPcieEngineLaneBitMap (
+  IN      LANE_TYPE                      LaneType,
+  IN      LANE_PROPERTY                  LaneProperty,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32                LaneBitmap;
+  UINT8                 Width;
+  UINT16                Offset;
+  UINT16                LoPhylane;
+  UINT16                HiPhylane;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+
+  Width = 0;
+  Offset = 0;
+  LaneBitmap = 0;
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+
+  if (PcieConfigIsPcieEngine (Engine)) {
+    if (LaneType == LaneTypeCore && LaneProperty == LanePropertyConfig) {
+      Width = PcieConfigGetNumberOfCoreLane (Engine);
+      Offset = Engine->Type.Port.StartCoreLane;
+      LaneBitmap = ((1 << Width) - 1) << Offset;
+    } else if (PcieConfigIsEngineAllocated (Engine)) {
+      if (LaneType == LaneTypeNativePhy) {
+        LaneBitmap = PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
+        LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
+      } else {
+        if (LaneType == LaneTypeCore) {
+          if (LaneProperty == LanePropertyActive) {
+            Width = PcieUtilGetLinkWidth (Engine, Pcie);
+            Offset = PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
+          } else if (LaneProperty == LanePropertyAllocated) {
+            Width = PcieConfigGetNumberOfPhyLane (Engine);
+            Offset = PcieUtilIsLinkReversed (FALSE, Engine, Pcie) ? (Engine->Type.Port.EndCoreLane - Width + 1) : Engine->Type.Port.StartCoreLane;
+          }
+        }
+        if (LaneType == LaneTypePhy) {
+          LoPhylane = PcieLibGetLoPhyLane (Engine);
+          HiPhylane = PcieLibGetHiPhyLane (Engine);
+          if (LaneProperty == LanePropertyActive) {
+            Width = PcieUtilGetLinkWidth (Engine, Pcie);
+            Offset = (PcieUtilIsLinkReversed (TRUE, Engine, Pcie) ? (HiPhylane - Width + 1) : LoPhylane) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+          } else if (LaneProperty == LanePropertyAllocated) {
+            Width = PcieConfigGetNumberOfPhyLane (Engine);
+            Offset = LoPhylane - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+          }
+        }
+        LaneBitmap = ((1 << Width) - 1) << Offset;
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of PCIE engine lane of requested type
+ *
+ *
+ * @param[in]   LaneType            Lane type
+ * @param[in]   LaneProperty        Lane Property
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetDdiEngineLaneBitMap (
+  IN      LANE_TYPE                      LaneType,
+  IN      LANE_PROPERTY                  LaneProperty,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitmap;
+  UINT8   Width;
+  UINT16  Offset;
+  Width = 0;
+  Offset = 0;
+  LaneBitmap = 0;
+  if (PcieConfigIsDdiEngine (Engine)) {
+    if (PcieConfigIsEngineAllocated (Engine)) {
+      if (LaneType == LaneTypePhy && ((LaneProperty == LanePropertyActive && (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE)) || (LaneProperty == LanePropertyAllocated))) {
+        Width = PcieConfigGetNumberOfPhyLane (Engine);
+        Offset = PcieLibGetLoPhyLane (Engine) - PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+        LaneBitmap = ((1 << Width) - 1) << Offset;
+      }
+      if (LaneType == LaneTypeNativePhy) {
+        LaneBitmap = PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LaneProperty, Engine);
+        LaneBitmap = PcieFmGetNativePhyLaneBitmap (LaneBitmap, Engine);
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get  bitmap of engine lane of requested type
+ *
+ *
+ * @param[in]   IncludeLaneType     Include Lane type
+ * @param[in]   ExcludeLaneType     Exclude Lane type
+ * @param[in]   Engine              Pointer to engine config descriptor
+ * @retval                          Lane bitmap
+ */
+
+UINT32
+PcieUtilGetEngineLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  )
+{
+  UINT32  LaneBitmap;
+  LaneBitmap = 0;
+  if (IncludeLaneType & LANE_TYPE_PCIE_LANES) {
+    if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) {
+      if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
+        LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+      } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+        } else {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine);
+        }
+      }
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_PHY) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) {
+      if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
+        LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+      } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+        } else {
+          LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
+        }
+      }
+    }
+    if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
+      LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+  }
+  if (IncludeLaneType & LANE_TYPE_DDI_LANES) {
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
+    }
+    if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) {
+      LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
+    }
+  }
+  if (ExcludeLaneType != 0) {
+    LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine));
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of phy lane confugred for master pll
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @retval     Lane bitmap
+ */
+
+STATIC UINT32
+PcieUtilGetMasterPllLaneBitMap (
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  if (Wrapper->MasterPll != 0) {
+    return 0xf << (Wrapper->MasterPll - 0xA) * 4;
+  }
+  return 0;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of Wrapper lane of requested type
+ *
+ *
+ * @param[in]  IncludeLaneType Include Lane type
+ * @param[in]  ExcludeLaneType Exclude Lane type
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @retval     Lane bitmap
+ */
+
+UINT32
+PcieUtilGetWrapperLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  )
+{
+  PCIe_ENGINE_CONFIG        *EngineList;
+  UINT32                    LaneBitmap;
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  LaneBitmap = 0;
+  if ((IncludeLaneType | ExcludeLaneType) != 0) {
+    if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) {
+      LaneBitmap = (1 << (Wrapper->NumberOfLanes)) - 1;
+      if (ExcludeLaneType != 0) {
+        LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper));
+      }
+    } else {
+      while (EngineList != NULL) {
+        LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList);
+        EngineList = PcieLibGetNextDescriptor (EngineList);
+      }
+      if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
+        LaneBitmap |= PcieUtilGetMasterPllLaneBitMap (Wrapper);
+      }
+      if ((ExcludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL) != 0) {
+        LaneBitmap &= (~PcieUtilGetMasterPllLaneBitMap (Wrapper));
+      }
+    }
+  }
+  return LaneBitmap;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program port register table
+ *
+ *
+ *
+ * @param[in]  Table           Pointer to table
+ * @param[in]  Length          number of entries
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  S3Save          Save for S3 flag
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PciePortProgramRegisterTable (
+  IN      PCIE_PORT_REGISTER_ENTRY    *Table,
+  IN      UINTN                       Length,
+  IN      PCIe_ENGINE_CONFIG          *Engine,
+  IN      BOOLEAN                     S3Save,
+  IN      PCIe_PLATFORM_CONFIG        *Pcie
+  )
+{
+  UINTN   Index;
+  UINT32  Value;
+  for (Index = 0; Index < Length; Index++) {
+    Value = PciePortRegisterRead (
+              Engine,
+              Table[Index].Reg,
+              Pcie
+              );
+    Value &= (~Table[Index].Mask);
+    Value |= Table[Index].Data;
+    PciePortRegisterWrite (
+      Engine,
+      Table[Index].Reg,
+      Value,
+      S3Save,
+      Pcie
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Lock registers
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PcieLockRegisters (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  UINT8   CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      PcieRegisterWriteField (
+        Wrapper,
+        CORE_SPACE (CoreId, D0F0xE4_CORE_0010_ADDRESS),
+        D0F0xE4_CORE_0010_HwInitWrLock_OFFSET,
+        D0F0xE4_CORE_0010_HwInitWrLock_WIDTH,
+        0x1,
+        TRUE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training state handling
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Indicate if engine in non final state
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieUtilGlobalGenCapabilityCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability;
+  PCIE_LINK_SPEED_CAP           LinkSpeedCapability;
+  PCIE_HOTPLUG_TYPE             HotPlugType;
+  UINT32                        Flags;
+
+  Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS;
+  GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer;
+  LinkSpeedCapability = PcieGen1;
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+    Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS;
+  }
+  HotPlugType = Engine->Type.Port.PortData.LinkHotplug;
+  if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) {
+    Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS;
+  }
+  if ((GlobalGenCapability->Flags & Flags) != 0) {
+    ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0);
+    LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine);
+    if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) {
+      GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine global GEN capability
+ *
+ *
+ * @param[in]  Flags           global GEN capability flags
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+PCIE_LINK_SPEED_CAP
+PcieUtilGlobalGenCapability (
+  IN      UINT32                         Flags,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP             GlobalCapability;
+  PCIE_GLOBAL_GEN_CAP_WORKSPACE   GlobalGenCap;
+
+  GlobalGenCap.LinkSpeedCapability = PcieGen1;
+  GlobalGenCap.Flags = Flags;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieUtilGlobalGenCapabilityCallback,
+    &GlobalGenCap,
+    Pcie
+    );
+
+  GlobalCapability = GlobalGenCap.LinkSpeedCapability;
+
+  return GlobalCapability;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
new file mode 100644
index 0000000000..207aeb6efe
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
@@ -0,0 +1,158 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe utility. Various supporting functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEUTILLIB_H_
+#define _PCIEUTILLIB_H_
+
+/// Core lanes
+typedef enum {
+  AllCoreLanes,           ///< All core lanes
+  AllocatedCoreLanes,     ///< Allocated core lanes
+  ActiveCoreLanes,        ///< Active core lanes
+  HotplugCoreLanes,       ///< Hot plug core lanes
+  SbCoreLanes,            ///< South bridge core lanes
+} CORE_LANES;
+
+/// DDI lanes
+typedef enum {
+  DdiAllLanes,            ///< All DDI Lanes
+  DdiActiveLanes          ///< Active DDI Lanes
+} DDI_LANES;
+
+BOOLEAN
+PcieUtilSearchArray (
+  IN      UINT8                         *Buf1,
+  IN      UINTN                         Buf1Length,
+  IN      UINT8                         *Buf2,
+  IN      UINTN                         Buf2Length
+  );
+
+VOID
+PcieUtilGetLinkHwStateHistory (
+  IN       PCIe_ENGINE_CONFIG            *Engine,
+     OUT   UINT8                         *History,
+  IN       UINT8                         Length,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+
+BOOLEAN
+PcieUtilIsLinkReversed (
+  IN      BOOLEAN                        HwLinkState,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+
+UINT8
+PcieUtilGetLinkWidth (
+  IN      PCIe_ENGINE_CONFIG            *Engine,
+  IN      PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+
+UINT32
+PcieUtilGetEngineLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_ENGINE_CONFIG             *Engine
+  );
+
+UINT32
+PcieUtilGetWrapperLaneBitMap (
+  IN      UINT32                         IncludeLaneType,
+  IN      UINT32                         ExcludeLaneType,
+  IN      PCIe_WRAPPER_CONFIG            *Wrapper
+  );
+
+VOID
+PciePortProgramRegisterTable (
+  IN      PCIE_PORT_REGISTER_ENTRY       *Table,
+  IN      UINTN                          Length,
+  IN      PCIe_ENGINE_CONFIG             *Engine,
+  IN      BOOLEAN                        S3Save,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+VOID
+PcieLockRegisters (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  );
+
+PCIE_LINK_SPEED_CAP
+PcieUtilGlobalGenCapability (
+  IN      UINT32                         Flags,
+  IN      PCIe_PLATFORM_CONFIG           *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
new file mode 100644
index 0000000000..a76bc5e0f5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
@@ -0,0 +1,324 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register Value
+ */
+UINT32
+PcieRegisterRead (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Silicon     Pointer to silicon descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register Value
+ */
+
+UINT32
+PcieSiliconRegisterRead (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32              Value;
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]   Wrapper     Pointer to wrapper descriptor
+ * @param[in]   Address     Register address
+ * @param[in]   Value       New register value
+ * @param[in]   S3Save      Save register for S3 (True/False)
+ * @param[in]   Pcie        Pointer to global PCIe configuration
+ */
+VOID
+PcieRegisterWrite (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) {
+    Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000);
+  }
+  PcieSiliconRegisterWrite (
+     PcieConfigGetParentSilicon (Wrapper),
+     Address,
+     Value,
+     S3Save,
+     Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register value.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]   Silicon     Pointer to silicon descriptor
+ * @param[in]   Address     Register address
+ * @param[in]   Value       New register value
+ * @param[in]   S3Save      Save register for S3 (True/False)
+ * @param[in]   Pcie        Pointer to global PCIe configuration
+ */
+VOID
+PcieSiliconRegisterWrite (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, "    *WR %s (%d:%d:%d):0x%08x = 0x%08x\n",
+    PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)),
+    Silicon->Address.Address.Bus,
+    Silicon->Address.Address.Device,
+    Silicon->Address.Address.Function,
+    Address,
+    Value
+    );
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
+  GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCIe register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ * @retval                 Register field value
+ */
+
+UINT32
+PcieRegisterReadField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PcieRegisterRead (Wrapper, Address, Pcie);
+  Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth));
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCIe register field.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  FieldOffset Field offset
+ * @param[in]  FieldWidth  Field width
+ * @param[in]  Value       Value to write
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+
+VOID
+PcieRegisterWriteField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  TempValue;
+  UINT32  Mask;
+  TempValue = PcieRegisterRead (Wrapper, Address, Pcie);
+  Mask = (~(0xFFFFFFFF << FieldWidth));
+  Value &= Mask;
+  TempValue &= (~(Mask << FieldOffset));
+  PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Wrapper     Pointer to wrapper descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PcieRegisterRMW (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieSiliconRegisterRMW (
+    PcieConfigGetParentSilicon (Wrapper),
+    Address,
+    AndMask,
+    OrMask,
+    S3Save,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write PCIe register.
+ *
+ * Support for unify register access through index/data pair on GNB
+ *
+ * @param[in]  Silicon     Pointer to silicon descriptor
+ * @param[in]  Address     Register address
+ * @param[in]  AndMask     Value & (~AndMask)
+ * @param[in]  OrMask      Value | OrMask
+ * @param[in]  S3Save      Save register for S3 (True/False)
+ * @param[in]  Pcie        Pointer to global PCIe configuration
+ */
+
+VOID
+PcieSiliconRegisterRMW (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32  Value;
+  Value = PcieSiliconRegisterRead (Silicon, Address, Pcie);
+  Value = (Value & (~AndMask)) | OrMask;
+  PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie);
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
new file mode 100644
index 0000000000..c0e4e2ff60
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
@@ -0,0 +1,154 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEWRAPPERREGACC_H_
+#define _PCIEWRAPPERREGACC_H_
+
+//#define WRAP_SPACE(w, x)   (0x01300000ul | (w << 16) | (x))
+//#define CORE_SPACE(c, x)   (0x00010000ul | (c << 24) | (x))
+//#define PHY_SPACE(w, p, x) (0x00200000ul | ((p + 1) << 24) | (w << 16) | (x))
+//#define PIF_SPACE(w, p, x) (0x00100000ul | ((p + 1) << 24) | (w << 16) | (x))
+#define IMP_SPACE(x) (0x01080000ul | (x))
+
+UINT32
+PcieRegisterRead (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterWrite (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieRegisterReadField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterWriteField (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT8                 FieldOffset,
+  IN      UINT8                 FieldWidth,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieRegisterRMW (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT32
+PcieSiliconRegisterRead (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconRegisterWrite (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                Value,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSiliconRegisterRMW (
+  IN      PCIe_SILICON_CONFIG   *Silicon,
+  IN      UINT32                Address,
+  IN      UINT32                AndMask,
+  IN      UINT32                OrMask,
+  IN      BOOLEAN               S3Save,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h
new file mode 100644
index 0000000000..6b156fe300
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/GnbPcieInitLibV4.h
@@ -0,0 +1,79 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe Init Library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIEINITLIBV4_H_
+#define _GNBPCIEINITLIBV4_H_
+
+#include "PcieWrapperServicesV4.h"
+#include "PciePowerMgmtV4.h"
+#include "PciePortServicesV4.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
new file mode 100644
index 0000000000..fe5430672e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
@@ -0,0 +1,322 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Configure Max Payload
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision:
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "PcieMaxPayloadV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEMAXPAYLOADV4_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef struct {
+  GNB_PCI_SCAN_DATA       ScanData;
+  UINT8                   MaxPayload;
+} PCIE_MAX_PAYLOAD_DATA;
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+SCAN_STATUS
+PcieGetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+SCAN_STATUS
+PcieSetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  );
+
+AGESA_STATUS
+PciePayloadBlackListFeature (
+  IN       PCI_ADDR               Device,
+  IN       UINT8                  *MaxPayload,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine maximum payload size for PCIe segment
+ *
+ *  Scan through all link in segment to determine maximum payload by EPs.
+ *
+ * @param[in]   DownstreamPort    PCI address of PCIe port
+ * @param[in]   StdHeader         Standard configuration header
+ *
+ */
+
+VOID
+PcieSetMaxPayload (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  PCIE_MAX_PAYLOAD_DATA  PcieMaxPayloadData;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayload for Device = %d:%d:%d\n",
+    DownstreamPort.Address.Bus,
+    DownstreamPort.Address.Device,
+    DownstreamPort.Address.Function
+    );
+  PcieMaxPayloadData.MaxPayload = MAX_PAYLOAD;
+  PcieMaxPayloadData.ScanData.StdHeader = StdHeader;
+  PcieMaxPayloadData.ScanData.GnbScanCallback = PcieGetMaxPayloadCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData);
+  PcieMaxPayloadData.ScanData.GnbScanCallback = PcieSetMaxPayloadCallback;
+  GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData);
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayloadExit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieGetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_MAX_PAYLOAD_DATA   *PcieMaxPayloadData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT32                  Value;
+  UINT8                   PcieCapPtr;
+  UINT8                   DeviceMaxPayload;
+
+  PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieGetMaxPayloadCallback for Device = %d:%d:%d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function
+    );
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRead (
+      Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER),
+      AccessWidth32,
+      &Value,
+      ScanData->StdHeader
+    );
+    DeviceMaxPayload = (UINT8) (Value & 0x7);
+    PciePayloadBlackListFeature (Device, &DeviceMaxPayload, ScanData->StdHeader);
+    IDS_HDT_CONSOLE (GNB_TRACE, "  Found DeviceMaxPayload as %d (Value = %x\n", DeviceMaxPayload, Value);
+    if (DeviceMaxPayload < PcieMaxPayloadData->MaxPayload) {
+      PcieMaxPayloadData->MaxPayload = DeviceMaxPayload;
+    }
+  }
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure the Max Payload setting to all devices in the PCIe Segment
+ *
+ *
+ *
+ * @param[in]     Device          PCI Address
+ * @param[in,out] ScanData        Scan configuration data
+ * @retval                        Scan Status of 0
+ */
+
+SCAN_STATUS
+PcieSetMaxPayloadCallback (
+  IN       PCI_ADDR             Device,
+  IN OUT   GNB_PCI_SCAN_DATA    *ScanData
+  )
+{
+  SCAN_STATUS             ScanStatus;
+  PCIE_MAX_PAYLOAD_DATA   *PcieMaxPayloadData;
+  PCIE_DEVICE_TYPE        DeviceType;
+  UINT8                   PcieCapPtr;
+
+  PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData;
+  ScanStatus = SCAN_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "  PcieSetMaxPayloadCallback for Device = %d:%d:%d to %d\n",
+    Device.Address.Bus,
+    Device.Address.Device,
+    Device.Address.Function,
+    PcieMaxPayloadData->MaxPayload
+    );
+  PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
+  if (PcieCapPtr != 0) {
+    GnbLibPciRMW (
+      Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CTRL_REGISTER),
+      AccessWidth32,
+      ~(UINT32) (0x7 << 5),
+      ((UINT32)PcieMaxPayloadData->MaxPayload << 5),
+      ScanData->StdHeader
+    );
+  }
+  DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
+  switch (DeviceType) {
+  case  PcieDeviceRootComplex:
+  case  PcieDeviceDownstreamPort:
+  case  PcieDeviceUpstreamPort:
+    GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData);
+    break;
+  case  PcieDeviceEndPoint:
+  case  PcieDeviceLegacyEndPoint:
+    break;
+  default:
+    break;
+  }
+  return SCAN_SUCCESS;
+}
+
+UINT16  PayloadBlacklistDeviceTable[] = {
+  0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Max_Payload_Size Black List
+ *
+ *
+ *
+ * @param[in] Device              PCI_ADDR of PCIe Device to evaluate
+ * @param[in] MaxPayload          Pointer to Max_Payload_Size value
+ * @param[in] StdHeader           Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PciePayloadBlackListFeature (
+  IN       PCI_ADDR               Device,
+  IN       UINT8                  *MaxPayload,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32  TargetDeviceId;
+  UINTN   i;
+  UINT32  DeviceId;
+  UINT32  VendorId;
+
+  GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader);
+  for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    VendorId = PayloadBlacklistDeviceTable[i];
+    DeviceId = PayloadBlacklistDeviceTable[i + 1];
+    if (VendorId == (UINT16)TargetDeviceId) {
+      if (DeviceId == 0xFFFF || DeviceId == (TargetDeviceId >> 16)) {
+        *MaxPayload = (UINT8) PayloadBlacklistDeviceTable[i + 2];
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h
new file mode 100644
index 0000000000..470235e4cc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Configure Max Payload
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEMAXPAYLOADV4_H_
+#define _PCIEMAXPAYLOADV4_H_
+
+VOID
+PcieSetMaxPayload (
+  IN       PCI_ADDR                DownstreamPort,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
new file mode 100644
index 0000000000..d90d6cdce7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c
@@ -0,0 +1,215 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "PciePortServicesV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set current link speed
+ *
+ *
+ * @param[in]  LinkSpeedCapability  Link Speed Capability
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetLinkSpeedCapV4 (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  DxF0xE4_xA4_STRUCT  DxF0xE4_xA4;
+  DxF0xE4_xC0_STRUCT  DxF0xE4_xC0;
+  DxF0x88_STRUCT      DxF0x88;
+  GnbLibPciRead (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+  DxF0xE4_xA4.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xA4_ADDRESS,
+                        Pcie
+                        );
+  DxF0xE4_xC0.Value = PciePortRegisterRead (
+                        Engine,
+                        DxF0xE4_xC0_ADDRESS,
+                        Pcie
+                        );
+
+  switch (LinkSpeedCapability) {
+  case PcieGen2:
+    DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
+    DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
+    DxF0x88.Field.TargetLinkSpeed = 0x2;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
+    break;
+  case PcieGen1:
+    DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0;
+    DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
+    DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
+    DxF0x88.Field.TargetLinkSpeed = 0x1;
+    DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (Engine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
+      D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
+      0,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+  PciePortRegisterWrite (
+    Engine,
+    DxF0xE4_xA4_ADDRESS,
+    DxF0xE4_xA4.Value,
+    FALSE,
+    Pcie
+    );
+  PciePortRegisterWrite (
+    Engine,
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0.Value,
+    FALSE,
+    Pcie
+    );
+  GnbLibPciWrite (
+    Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
+    AccessWidth32,
+    &DxF0x88.Value,
+    GnbLibGetHeader (Pcie)
+   );
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable passing TLP prefix to IOMMU if IOMMU enabled
+ *
+ *
+ * @param[in]  Engine               Pointer to engine configuration descriptor
+ * @param[in]  Pcie                 Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieInitPortForIommuV4 (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterRMW (
+    Engine,
+    DxF0xE4_xC1_ADDRESS,
+    DxF0xE4_xC1_StrapE2EPrefixEn_MASK | DxF0xE4_xC1_StrapExtendedFmtSupported_MASK,
+    (1 << DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET),
+    TRUE,
+    Pcie
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
new file mode 100644
index 0000000000..1420e4712b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe port initialization service procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPORTSERVICESV4_H_
+#define _PCIEPORTSERVICESV4_H_
+
+
+VOID
+PcieSetLinkSpeedCapV4 (
+  IN      PCIE_LINK_SPEED_CAP   LinkSpeedCapability,
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieInitPortForIommuV4 (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
new file mode 100644
index 0000000000..30a901191f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.c
@@ -0,0 +1,328 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clock gating
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrClockGatingV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  D0F0xE4_WRAP_8011_STRUCT  D0F0xE4_WRAP_8011;
+  D0F0xE4_WRAP_8012_STRUCT  D0F0xE4_WRAP_8012;
+  D0F0xE4_WRAP_8014_STRUCT  D0F0xE4_WRAP_8014;
+  D0F0xE4_WRAP_8015_STRUCT  D0F0xE4_WRAP_8015;
+  D0F0xE4_WRAP_8016_STRUCT  D0F0xE4_WRAP_8016;
+  UINT8                     CoreId;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Enter\n");
+  D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+                              Pcie
+                              );
+  D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+                              Pcie
+                              );
+
+  D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+                              Pcie
+                              );
+
+  D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
+                              Wrapper,
+                              WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
+                              Pcie
+                              );
+
+  if (Wrapper->Features.ClkGating == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
+
+
+    D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
+    D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
+    D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
+    D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
+
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
+    D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
+
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
+    D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
+    D0F0xE4_WRAP_8015.Field.line477  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line478  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line479  = 0x3;
+    D0F0xE4_WRAP_8015.Field.line480  = 0x1;
+    D0F0xE4_WRAP_8015.Field.line482  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line483  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line484  = 0x0;
+    D0F0xE4_WRAP_8015.Field.line485  = 0x1;
+    D0F0xE4_WRAP_8015.Field.line486  = 0x1;
+
+    D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigCEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGateDigDEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
+    D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
+  }
+  if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
+    D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
+  }
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
+    D0F0xE4_WRAP_8014.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
+    D0F0xE4_WRAP_8015.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
+    D0F0xE4_WRAP_8012.Value,
+    TRUE,
+    Pcie
+    );
+  PcieRegisterWrite (
+    Wrapper,
+    WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
+    D0F0xE4_WRAP_8011.Value,
+    TRUE,
+    Pcie
+    );
+  for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+    PcieRegisterWriteField (
+      Wrapper,
+      CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
+      D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
+      D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
+      0xf,
+      TRUE,
+      Pcie
+      );
+  }
+  if (Wrapper->Features.LclkGating == 0x1) {
+    D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
+    D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
+      D0F0xE4_WRAP_8016.Value,
+      TRUE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down DDI plls
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePwrPowerDownDdiPllsV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Enter\n");
+  if (PcieConfigIsDdiWrapper (Wrapper) && !PcieConfigIsPcieWrapper (Wrapper)) {
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS),
+      D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK,
+      0x1 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET,
+      FALSE,
+      Pcie
+      );
+    PciePollPifForCompeletion (Wrapper, Pcie);
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+      D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK,
+      (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x1 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET),
+      FALSE,
+      Pcie
+      );
+    PciePollPifForCompeletion (Wrapper, Pcie);
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
+      D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK | D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK,
+      (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET) | (0x7 << D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET),
+      FALSE,
+      Pcie
+      );
+    PcieRegisterRMW (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8020_ADDRESS),
+      D0F0xE4_WRAP_8020_PrbsPcieLbSelect_MASK,
+      0x0 << D0F0xE4_WRAP_8020_PrbsPcieLbSelect_OFFSET,
+      FALSE,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownDdiPllsV4 Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h
new file mode 100644
index 0000000000..447571edbb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PciePowerMgmtV4.h
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Power saving features/services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERSAVINGFEATURESV4_H_
+#define _PCIEPOWERSAVINGFEATURESV4_H_
+
+VOID
+PciePwrClockGatingV4 (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PciePwrPowerDownDdiPllsV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl
new file mode 100644
index 0000000000..d7ea99ffbc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieServiceV4.esl
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 55681 $   @e \$Date: 2011-06-24 14:34:00 -0700 (Fri, 24 Jun 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+
+/*----------------------------------------------------------------------------------------*/
+  /**
+   *  Get current link speed
+   *
+   *  Arg0 - Port Index
+   *
+   */
+
+
+  Method (procPciePortGetCurrentLinkSpeed, 1, NotSerialized) {
+    Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcLinkCtrlLocal1)
+    ShiftRight (varLcLinkCtrlLocal1, 13, varCurrenLinkSpeedLocal2)
+    And (varCurrenLinkSpeedLocal2, 0x3, varCurrenLinkSpeedLocal2);
+    Increment (varCurrenLinkSpeedLocal2)
+    return (varCurrenLinkSpeedLocal2)
+  }
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
new file mode 100644
index 0000000000..5486edbc97
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuServiceV4.esl
@@ -0,0 +1,105 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *  SMU Service request
+   *
+   *  Arg0 - Smu service id
+   *
+   */
+  Method (procNbSmuServiceRequest, 1, NotSerialized) {
+    Store ("NbSmuServiceRequest Enter", Debug)
+    Store (Concatenate ("  Request id = ", ToHexString (Arg0), Local6), Debug)
+
+    while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x2), 0x2)) {
+      Store ("--Wait Init Done--", Debug)
+    }
+
+    Store (procIndirectRegisterRead (0x0, 0xB8, 0xE0003000), Local0)
+    // Reverse IntToggle[0], clean ServiceIndex[16:1]
+    Or (And (Local0, 0xFFFE0000), And (Not (And (Local0, 0x00000001)), 0x1), Local0)
+    // Assign ID
+    Or (Local0, ShiftLeft (Arg0, 1), Local0)
+    procIndirectRegisterWrite (0x0, 0xB8, 0xE0003000, Local0)
+
+    while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x1), 0x1)) {
+      Store ("--Wait Init Ack--", Debug)
+    }
+
+    while (LNotEqual (And (procIndirectRegisterRead (0x0, 0xB8, 0xE0003004), 0x2), 0x2)) {
+      Store ("--Wait Init Done--", Debug)
+    }
+
+    Store ("NbSmuServiceRequest Exit", Debug)
+  }
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl
new file mode 100644
index 0000000000..b91ea6c028
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieSmuVidReqV4.esl
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * ALIB PSPP Pcie Smu Lib V1
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+
+
+  /*----------------------------------------------------------------------------------------*/
+  /**
+   *   Request VID
+   *
+   *  Arg0 - 1 - GEN1 2 - GEN2
+   *  Arg1 - 0 = do not wait intil voltage is set
+   *         1 = wait until voltage is set
+   */
+  Method (procPcieSetVoltage, 2, Serialized) {
+    Store ("PcieSetVoltage Enter", Debug)
+    // Get real vid by index
+    if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) {
+      Store (DeRefOf (Index (varSclkVid, varGen1Vid)), local3)
+    } else {
+      Store (DeRefOf (Index (varSclkVid, varGen2Vid)), local3)
+    }
+
+    // GMMx63C/GMMx640 -- CG_Reg = reg - 0x600
+    // Store REQ in local2
+    And (procIndirectRegisterRead (0x0, 0xB8, 0xE000203C), 0x4, Local2)
+    // Store ACK in local1
+    And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1)
+    // Compare REQ with ACK
+    while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
+      And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1)
+    }
+    Store (procIndirectRegisterRead (0x0, 0xB8, 0xE000203C), Local1)
+    //Enable voltage change
+    if (LEqual (Arg0, DEF_LINK_SPEED_GEN1)) {
+      And (Local1, 0xFFFFFFFD, Local1)
+    } else {
+      Or (Local1, 0x2, Local1)
+    }
+    procIndirectRegisterWrite (0x0, 0xB8, 0xE000203C, Local1)
+    //Clear voltage index
+    And (Local1, Not (ShiftLeft (0xFF, 8)), Local1)
+
+    Store (Concatenate ("  Voltage Index:", ToHexString (local3), Local6), Debug)
+    //Set new voltage index
+    Or (Local1, ShiftLeft (local3, 8), Local1)
+    //Togle request
+    And (Not (Local1), 0x4, Local2)
+    Or (And (Local1, Not (0x4)), Local2, Local1)
+    procIndirectRegisterWrite (0x0, 0xB8, 0xE000203C, Local1)
+    if (LNotEqual (Arg1, 0)) {
+      while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
+        And (procIndirectRegisterRead (0x0, 0xB8, 0xE0002040), 0x1, Local1)
+      }
+    }
+    Store ("PcieSetVoltage Exit", Debug)
+  }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
new file mode 100644
index 0000000000..15cabc76d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c
@@ -0,0 +1,277 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe wrapper services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "PcieWrapperServicesV4.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Relinquish control to DDI for specific lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PcieSetDdiOwnPhyV4 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+
+  UINT32  LaneBitmap;
+  UINT8   Slice;
+  if (PcieLibIsDdiWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n");
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    for (Slice = 0; Slice < 4; Slice++) {
+      if ((LaneBitmap & (1 << (Slice * 4))) != 0) {
+        PcieRegisterRMW (
+          Wrapper,
+          WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice),
+          D0F0xE4_WRAP_8040_OwnSlice_MASK,
+          1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET,
+          FALSE,
+          Pcie
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Execute/clean up reconfiguration
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologyExecuteReconfigV4 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xE4_WRAP_8062_STRUCT  D0F0xE4_WRAP_8062;
+  PCIe_SILICON_CONFIG       *Silicon;
+
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n");
+
+    PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
+
+    D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
+                                Wrapper,
+                                WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+                                Pcie
+                                );
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+
+    Silicon = PcieConfigGetParentSilicon (Wrapper);
+
+    GnbLibPciIndirectRMW (
+      Silicon->Address.AddressValue | D0F0xB8_ADDRESS,
+      D0F0xBC_x1F630_ADDRESS,
+      AccessWidth32,
+      (UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK,
+      Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+
+    GnbSmuServiceRequestV4 (
+      Silicon->Address,
+      SMC_MSG_RECONFIGURE,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+
+    D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
+    D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
+      D0F0xE4_WRAP_8062.Value,
+      FALSE,
+      Pcie
+      );
+    PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SSID
+ *
+ *
+ * @param[in]  Ssid            SSID
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PcieSetSsidV4 (
+  IN       UINT32                        Ssid,
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    PcieRegisterWrite (
+      Wrapper,
+      WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0046_ADDRESS),
+      Ssid,
+      FALSE,
+      Pcie
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable lane reversal
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieTopologySetLinkReversalV4 (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_ENGINE_CONFIG  *EngineList;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n");
+  EngineList = PcieConfigGetChildEngine (Wrapper);
+  while (EngineList != NULL) {
+    if (PcieLibIsEngineAllocated (EngineList)) {
+      if (PcieLibIsPcieEngine (EngineList)) {
+        if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) {
+            PciePortRegisterWriteField (
+              EngineList,
+              DxF0xE4_xC1_ADDRESS,
+              DxF0xE4_xC1_StrapReverseLanes_OFFSET,
+              DxF0xE4_xC1_StrapReverseLanes_WIDTH,
+              0x1,
+              FALSE,
+              Pcie
+              );
+        }
+      }
+    }
+    EngineList = PcieLibGetNextDescriptor (EngineList);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
new file mode 100644
index 0000000000..533f80b906
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.h
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe wrapper services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEWRAPPERSERVICESV4_H_
+#define _PCIEWRAPPERSERVICESV4_H_
+
+
+VOID
+PcieSetDdiOwnPhyV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+
+VOID
+PcieTopologyExecuteReconfigV4 (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieSetSsidV4 (
+  IN       UINT32                 Ssid,
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieTopologySetLinkReversalV4 (
+  IN      PCIe_WRAPPER_CONFIG     *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+#endif
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h
new file mode 100644
index 0000000000..71d852fbb3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe training library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBPCIETRAININGV1_H_
+#define _GNBPCIETRAININGV1_H_
+
+#include "PcieTraining.h"
+#include "PcieWorkarounds.h"
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
new file mode 100644
index 0000000000..8f7cbdaaf2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
@@ -0,0 +1,907 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  PCIe link training
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "GeneralServices.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "PcieWorkarounds.h"
+#include  "PcieTraining.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+PcieSetResetStateOnEngines (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingCheckResetDuration (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingDeassertReset (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingBrokenLine (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingGen2Fail (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+GNB_DEBUG_CODE (
+VOID
+STATIC
+PcieTrainingDebugDumpPortState (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+);
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set link State
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  State               State to set
+ * @param[in]  UpdateTimeStamp     Update time stamp
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieTrainingSetPortState (
+  IN      PCIe_ENGINE_CONFIG        *CurrentEngine,
+  IN      PCIE_LINK_TRAINING_STATE  State,
+  IN      BOOLEAN                   UpdateTimeStamp,
+  IN      PCIe_PLATFORM_CONFIG      *Pcie
+  )
+{
+  UINT32 TimeStamp;
+  CurrentEngine->Type.Port.State = (UINT8) State;
+  if (UpdateTimeStamp) {
+    TimeStamp = PcieTimerGetTimeStamp (Pcie);
+    CurrentEngine->Type.Port.TimeStamp = TimeStamp;
+  }
+  GNB_DEBUG_CODE (
+    PcieTrainingDebugDumpPortState (CurrentEngine, Pcie)
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set state for all engines connected to same reset ID
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Pointer to Reset Id
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieSetResetStateOnEngines (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 ResetId;
+  ResetId = *(UINT8 *)Buffer;
+  if (Engine->Type.Port.PortData.ResetId == ResetId && !PcieConfigIsSbPcieEngine (Engine)) {
+    PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie);
+    GnbLibPciRMW (
+      Engine->Type.Port.Address.AddressValue | DxF0x68_ADDRESS,
+      AccessWidth32,
+      (UINT32) ~DxF0x68_LinkDis_MASK,
+      1 << DxF0x68_LinkDis_OFFSET,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Assert GPIO port reset.
+ *
+ *  Transition to LinkStateResetDuration state
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingAssertReset (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_SLOT_RESET_INFO ResetInfo;
+  ResetInfo.ResetControl = AssertSlotReset;
+  ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
+  LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieSetResetStateOnEngines,
+    (VOID *)&CurrentEngine->Type.Port.PortData.ResetId,
+    Pcie
+    );
+  AgesaPcieSlotResetControl (0, &ResetInfo);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check for reset duration
+ *
+ *  Transition to LinkStateResetDuration state
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieTrainingCheckResetDuration (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 TimeStamp;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Deassert GPIO port reset.
+ *
+ *  Transition to LinkStateResetDuration state
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Platform configuration
+ *
+ */
+VOID
+PcieTrainingDeassertReset (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_SLOT_RESET_INFO ResetInfo;
+  ResetInfo.ResetControl = DeassertSlotReset;
+  ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
+  LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
+  AgesaPcieSlotResetControl (0, &ResetInfo);
+  GnbLibPciRMW (
+    CurrentEngine->Type.Port.Address.AddressValue | DxF0x68_ADDRESS,
+    AccessWidth32,
+    (UINT32) ~DxF0x68_LinkDis_MASK,
+    0 << DxF0x68_LinkDis_OFFSET,
+    GnbLibGetHeader (Pcie)
+    );
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check for after reset deassertion timeout
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCheckResetTimeout (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32 TimeStamp;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Release training
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingRelease (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   LinkTrainingState;
+  PcieRegisterWriteField (
+    PcieConfigGetParentWrapper (CurrentEngine),
+    WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
+    D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
+    D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
+    0,
+    FALSE,
+    Pcie
+    );
+  if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    LinkTrainingState = LinkStateCompliance;
+  } else {
+    LinkTrainingState = LinkStateDetectPresence;
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Detect presence of any EP on the link
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingDetectPresence (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   LinkHwStateHistory[4];
+  UINT32  TimeStamp;
+  PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie);
+  if (LinkHwStateHistory[0] > 4) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
+    return;
+  }
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
+  }
+}
+
+UINT8 FailPattern1 [] = {0x2a, 0x6};
+UINT8 FailPattern2 [] = {0x2a, 0x9};
+UINT8 FailPattern3 [] = {0x2a, 0xb};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Detect Link State
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingDetectLinkState (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   LinkHwStateHistory[16];
+  UINT32  TimeStamp;
+  UINT8   LinkTrainingState;
+  PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie);
+  if (LinkHwStateHistory[0] == 0x10) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie);
+    return;
+  };
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) {
+    LinkTrainingState = LinkStateTrainingFail;
+    PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie);
+    if (LinkHwStateHistory[0] == 0x7) {
+      LinkTrainingState = LinkStateCompliance;
+    } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) {
+      LinkTrainingState = LinkStateBrokenLane;
+    } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) {
+      LinkTrainingState = LinkStateGen2Fail;
+    } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern3, sizeof (FailPattern3))) {
+      LinkTrainingState = LinkStateGen2Fail;
+    }
+    PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Broken Lane
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+PcieTrainingBrokenLine (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 CurrentLinkWidth;
+  UINT8 LinkTrainingState;
+  CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie);
+  if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) {
+    CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY;
+    PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie);
+    LinkTrainingState = LinkStateResetAssert;
+    PutEventLog (
+      AGESA_WARNING,
+      GNB_EVENT_BROKEN_LANE_RECOVERY,
+      CurrentEngine->Type.Port.Address.AddressValue,
+      0,
+      0,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+  } else {
+    LinkTrainingState = LinkStateGen2Fail;
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link fail because device does not support Gen2
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+PcieTrainingGen2Fail (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8 LinkTrainingState;
+  if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) {
+    PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0);
+    CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1;
+    PcieLinkSafeMode (CurrentEngine, Pcie);
+    LinkTrainingState = LinkStateResetAssert;
+    PutEventLog (
+      AGESA_WARNING,
+      GNB_EVENT_BROKEN_LANE_RECOVERY,
+      CurrentEngine->Type.Port.Address.AddressValue,
+      0,
+      0,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+  } else {
+    LinkTrainingState = LinkStateTrainingFail;
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Link in L0
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieCheckLinkL0 (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if link fail because device does not support Gen X
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCheckVcoNegotiation (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32          TimeStamp;
+  DxF0x128_STRUCT DxF0x128;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+  GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie));
+  if (DxF0x128.Field.VcNegotiationPending == 0) {
+    UINT16  NumberOfPhyLane;
+    NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine);
+    if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) {
+      // Limit exposure of workaround to x8 and x16 port.
+      PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie);
+    } else {
+      PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie);
+    }
+    return;
+  }
+  if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) {
+    PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if for GFX workaround condition
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingGfxWorkaround (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32                TimeStamp;
+  GFX_WORKAROUND_STATUS GfxWorkaroundStatus;
+  TimeStamp = PcieTimerGetTimeStamp (Pcie);
+
+  GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie));
+  switch (GfxWorkaroundStatus) {
+  case GFX_WORKAROUND_DEVICE_NOT_READY:
+    if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= (3 * 1000000)) {
+      PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie);
+    }
+    break;
+  case GFX_WORKAROUND_SUCCESS:
+    PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie);
+    break;
+  case GFX_WORKAROUND_RESET_DEVICE:
+    if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) {
+      CurrentEngine->Type.Port.GfxWrkRetryCount++;
+      PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie);
+    } else {
+      PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie);
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Retrain link
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingRetrainLink (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortRegisterWriteField (
+    CurrentEngine,
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcReconfigNow_OFFSET,
+    DxF0xE4_xA2_LcReconfigNow_WIDTH,
+    1,
+    FALSE,
+    Pcie
+    );
+  PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training fail on this port
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingFail (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0);
+  PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Links training success
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingSuccess (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0);
+  PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Links in compliance
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCompliance (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieConfigUpdatePortStatus (CurrentEngine,  INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0);
+  PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCie EP not present
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingNotPresent (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) {
+  } else {
+    PcieRegisterWriteField (
+      PcieConfigGetParentWrapper (CurrentEngine),
+      WRAP_SPACE (PcieConfigGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
+      D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
+      D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
+      1,
+      FALSE,
+      Pcie
+      );
+  }
+  PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Final state. Port training completed.
+ *
+ * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+VOID
+STATIC
+PcieTrainingCompleted (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Training state handling
+ *
+ *
+ *
+ * @param[in]       Engine              Pointer to engine config descriptor
+ * @param[in, out]  Buffer              Indicate if engine in non final state
+ * @param[in]       Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieTrainingPortCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  BOOLEAN *TrainingComplete;
+  TrainingComplete = (BOOLEAN *) Buffer;
+  if (Engine->Type.Port.State < Pcie->TrainingExitState) {
+    *TrainingComplete = FALSE;
+  } else {
+    return;
+  }
+  switch (Engine->Type.Port.State) {
+  case LinkStateResetAssert:
+    PcieTrainingAssertReset (Engine, Pcie);
+    break;
+  case LinkStateResetDuration:
+    PcieTrainingCheckResetDuration (Engine, Pcie);
+    break;
+  case LinkStateResetExit:
+    PcieTrainingDeassertReset (Engine, Pcie);
+    break;
+  case LinkTrainingResetTimeout:
+    PcieTrainingCheckResetTimeout (Engine, Pcie);
+    break;
+  case LinkStateReleaseTraining:
+    PcieTrainingRelease (Engine, Pcie);
+    break;
+  case LinkStateDetectPresence:
+    PcieTrainingDetectPresence (Engine, Pcie);
+    break;
+  case LinkStateDetecting:
+    PcieTrainingDetectLinkState (Engine, Pcie);
+    break;
+  case LinkStateBrokenLane:
+    PcieTrainingBrokenLine (Engine, Pcie);
+    break;
+  case LinkStateGen2Fail:
+    PcieTrainingGen2Fail (Engine, Pcie);
+    break;
+  case LinkStateL0:
+    PcieCheckLinkL0 (Engine, Pcie);
+    break;
+  case LinkStateVcoNegotiation:
+    PcieTrainingCheckVcoNegotiation (Engine, Pcie);
+    break;
+  case LinkStateRetrain:
+    PcieTrainingRetrainLink (Engine, Pcie);
+    break;
+  case LinkStateTrainingFail:
+    PcieTrainingFail (Engine, Pcie);
+    break;
+  case LinkStateGfxWorkaround:
+    PcieTrainingGfxWorkaround (Engine, Pcie);
+    break;
+  case LinkStateTrainingSuccess:
+    PcieTrainingSuccess (Engine, Pcie);
+    break;
+  case LinkStateCompliance:
+    PcieTrainingCompliance (Engine, Pcie);
+    break;
+  case LinkStateDeviceNotPresent:
+    PcieTrainingNotPresent (Engine, Pcie);
+    break;
+  case LinkStateTrainingCompleted:
+    PcieTrainingCompleted (Engine, Pcie);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Main link training procedure
+ *
+ *  Port end up in three possible state  LinkStateTrainingNotPresent/LinkStateCompliance/
+ *                                       LinkStateTrainingSuccess
+ *
+ * @param[in]   Pcie                Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+PcieTraining (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  BOOLEAN       TrainingComplete;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n");
+  do {
+    TrainingComplete = TRUE;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      PcieTrainingPortCallback,
+      &TrainingComplete,
+      Pcie
+      );
+  } while (!TrainingComplete);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Helper function to dump port state on state transition
+ *
+ *
+ * @param[in]  CurrentEngine       Pointer to engine config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ *
+ */
+
+GNB_DEBUG_CODE (
+VOID
+STATIC
+PcieTrainingDebugDumpPortState (
+  IN      PCIe_ENGINE_CONFIG    *CurrentEngine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Port %d:%d:%d State [%s] Time Stamp [%d]\n",
+    CurrentEngine->Type.Port.Address.Address.Bus,
+    CurrentEngine->Type.Port.Address.Address.Device,
+    CurrentEngine->Type.Port.Address.Address.Function,
+    (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail    " : (
+    (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : (
+    (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance      " : (
+    (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" :  (
+    (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert     " :  (
+    (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration   " :  (
+    (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit       " :  (
+    (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " :  (
+    (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " :  (
+    (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence  " :  (
+    (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting       " :  (
+    (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane      " :  (
+    (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail        " :  (
+    (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0              " :  (
+    (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation  " :  (
+    (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround   " : (
+    (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : (
+    (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain         " : (
+    (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit       " : "Unknown")))))))))))))))))),
+    CurrentEngine->Type.Port.TimeStamp
+    );
+}
+)
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
new file mode 100644
index 0000000000..c84b522d7c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *  PCIe link training
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIETRAINING_H_
+#define _PCIETRAINING_H_
+
+
+AGESA_STATUS
+PcieTraining (
+  IN     PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieTrainingSetPortState (
+  IN      PCIe_ENGINE_CONFIG        *CurrentEngine,
+  IN      PCIE_LINK_TRAINING_STATE  State,
+  IN      BOOLEAN                   UpdateTimeStamp,
+  IN      PCIe_PLATFORM_CONFIG      *Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
new file mode 100644
index 0000000000..858dcbe4e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
@@ -0,0 +1,402 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various workarounds
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbRegistersLN.h"
+#include  "PcieWorkarounds.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieConfigureBridgeResources (
+  IN      PCI_ADDR             Port,
+  IN      AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+VOID
+PcieFreeBridgeResources (
+  IN      PCI_ADDR             Port,
+  IN      AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+GFX_WORKAROUND_STATUS
+PcieDeskewWorkaround (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+GFX_WORKAROUND_STATUS
+PcieNvWorkaround (
+  IN      PCI_ADDR            Device,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+PcieProgramCpuMmio (
+  OUT    UINT32              *SaveValues,
+  IN     AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+PcieRestoreCpuMmio (
+  IN     UINT32              *RestoreValues,
+  IN     AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+BOOLEAN
+PcieIsDeskewCardDetected (
+  IN      UINT16             DeviceId
+  );
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ATI RV370/RV380 card workaround
+ *
+ *
+ *
+ * @param[in]  Port        PCI addreses of the port
+ * @param[in]  StdHeader   Standard configuration header
+ * @retval     GFX_WORKAROUND_STATUS   Return the GFX Card Workaround status
+ */
+GFX_WORKAROUND_STATUS
+PcieGfxCardWorkaround (
+  IN     PCI_ADDR               Port,
+  IN     AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GFX_WORKAROUND_STATUS   Status;
+  UINT16                  DeviceId;
+  UINT16                  VendorId;
+  UINT8                   DevClassCode;
+  UINT32                  SaveValueData[2];
+  PCI_ADDR                Ep;
+
+  Status = GFX_WORKAROUND_SUCCESS;
+
+  Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0);
+  if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) {
+    GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader);
+    Status = GFX_WORKAROUND_DEVICE_NOT_READY;
+    if (DeviceId != 0xffff) {
+      GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader);
+      if (VendorId != 0xffff) {
+        GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader);
+        Status = GFX_WORKAROUND_SUCCESS;
+        if (DevClassCode == 3) {
+          PcieProgramCpuMmio (SaveValueData, StdHeader);
+          if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) {
+            Status = PcieDeskewWorkaround (Ep, StdHeader);
+          } else if (VendorId == 0x10DE) {
+            Status = PcieNvWorkaround (Ep, StdHeader);
+          }
+          PcieRestoreCpuMmio (SaveValueData, StdHeader);
+        }
+      }
+    }
+    PcieFreeBridgeResources (Port, StdHeader);
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RV370/RV380 Deskew workaround
+ *
+ *
+ *
+ * @param[in] Device     Pcie Address of ATI RV370/RV380 card.
+ * @param[in] StdHeader  Standard configuration header
+ */
+GFX_WORKAROUND_STATUS
+PcieDeskewWorkaround (
+  IN      PCI_ADDR              Device,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINTN       MmioBase;
+  UINT16      MmioData1;
+  UINT32      MmioData2;
+
+  MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
+  if (MmioBase == 0) {
+    return GFX_WORKAROUND_SUCCESS;
+  }
+  GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , (UINT32)~BIT1, (UINT32)BIT1, StdHeader);
+  GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader);
+  GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader);
+  if (MmioData1 == 0xb700) {
+    GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader);
+    GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader);
+    if (MmioData2 == 0x13) {
+      GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader);
+      if (MmioData2 & BIT8) {
+        return  GFX_WORKAROUND_RESET_DEVICE;
+      }
+    }
+  }
+  GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, (UINT32)~BIT1, 0x0, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader);
+
+  return GFX_WORKAROUND_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  NV43 card workaround (lost SSID)
+ *
+ *
+ *
+ * @param[in] Device     Pcie Address of NV43 card.
+ * @param[in] StdHeader  Standard configuration header
+ */
+GFX_WORKAROUND_STATUS
+PcieNvWorkaround (
+  IN     PCI_ADDR              Device,
+  IN     AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32      DeviceSSID;
+  UINTN       MmioBase;
+  UINT32      MmioData3;
+
+  MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
+  if (MmioBase == 0) {
+    return GFX_WORKAROUND_SUCCESS;
+  }
+  GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader);
+  GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader);
+  GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader);
+  if (DeviceSSID != MmioData3) {
+    GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader);
+  }
+  GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader);
+  GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader);
+  return GFX_WORKAROUND_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Allocate temporary resources for Pcie P2P bridge
+ *
+ *
+ *
+ * @param[in] Port         Pci Address of Port to initialize.
+ * @param[in] StdHeader    Standard configuration header
+ */
+AGESA_STATUS
+PcieConfigureBridgeResources (
+  IN      PCI_ADDR              Port,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32      Value;
+  UINT32      MmioBase;
+
+  MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
+  if (MmioBase == 0) {
+    return AGESA_WARNING;
+  }
+  Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16);
+  GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader);
+  Value = MmioBase + (MmioBase >> 16);
+  GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader);
+  Value = 0x000fff0;
+  GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader);
+  Value = 0x2;
+  GnbLibPciWrite (Port.AddressValue | 0x4 , AccessWidth8, &Value, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Free temporary resources for Pcie P2P bridge
+ *
+ *
+ *
+ * @param[in] Port       Pci Address of Port to clear resource allocation.
+ * @param[in] StdHeader  Standard configuration header
+ */
+VOID
+PcieFreeBridgeResources (
+  IN      PCI_ADDR            Port,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32 Value;
+
+  Value = 0;
+  GnbLibPciWrite (Port.AddressValue | 0x4 , AccessWidth8,  &Value, StdHeader);
+  GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader);
+  GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader);
+  GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader);
+
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Save CPU MMIO register
+ *
+ *
+ *
+ * @param[out] UINT32        SaveValues
+ * @param[in]  StdHeader     Standard configuration header
+ *
+ */
+VOID
+PcieProgramCpuMmio (
+     OUT   UINT32             *SaveValues,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  //Save CPU MMIO Register
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader);
+
+  //Write Temp Pcie MMIO to CPU
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader);
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Restore CPU MMIO register
+ *
+ *
+ *
+ * @param[in] PCIe_PLATFORM_CONFIG    Pcie
+ * @param[in] StdHeader               Standard configuration header
+ */
+VOID
+PcieRestoreCpuMmio (
+  IN      UINT32                *RestoreValues,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  //Restore CPU MMIO Register
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader);
+  GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if card required test for deskew workaround
+ *
+ *
+ *
+ * @param[in] DeviceId    Device ID
+ */
+
+BOOLEAN
+PcieIsDeskewCardDetected (
+  IN      UINT16    DeviceId
+  )
+{
+  if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) ||
+     (DeviceId == 0x3E50) || (DeviceId == 0x3E54) ||
+     ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8)  == 0x5B60)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h
new file mode 100644
index 0000000000..3f67635c20
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various workarounds
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEWORKAROUNDS_H_
+#define _PCIEWORKAROUNDS_H_
+
+GFX_WORKAROUND_STATUS
+PcieGfxCardWorkaround (
+  IN     PCI_ADDR               Port,
+  IN     AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
new file mode 100644
index 0000000000..64f8df5576
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c
@@ -0,0 +1,178 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CNB library.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuServices.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbLib.h"
+#include  "GnbLibPciAcc.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Host bridge PCI Address
+ *
+ *
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      PCI address of GNB for a given socket/silicon.
+ */
+
+PCI_ADDR
+GnbFmGetPciAddress (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Gnb;
+  Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  return Gnb;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bus range decoded by GNB
+ *
+ * Final bus allocation can not be assumed until AmdInitMid
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  StartBusNumber  Beggining of the Bus Range
+ * @param[out]  EndBusNumber    End of the Bus Range
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+
+AGESA_STATUS
+GnbFmGetBusDecodeRange (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *StartBusNumber,
+     OUT   UINT8                      *EndBusNumber,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  *StartBusNumber = 0x0;
+  *EndBusNumber = 0xff;
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get link to which GNB connected to
+ *
+ *
+ * @param[in]   GnbHandle       GNB handle
+ * @param[out]  LinkId          Link to which GNB connected to
+ * @param[in]   StdHeader       Standard configuration header
+ * @retval                      Satus
+ */
+
+AGESA_STATUS
+GnbFmGetLinkId (
+  IN       GNB_HANDLE                 *GnbHandle,
+     OUT   UINT8                      *LinkId,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+
+  *LinkId = 0x00;
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
new file mode 100644
index 0000000000..5a1db75fd9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.c
@@ -0,0 +1,146 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbIommu.h"
+#include  "GnbCommonLib.h"
+#include  "GnbIvrsLib.h"
+#include  "GnbSbIommuLib.h"
+#include  "GnbSbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHD entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+SbCreateIvhdEntries (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Start;
+  PCI_ADDR  End;
+  PCI_ADDR  PciAddress;
+  UINT32    Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Entry\n");
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 4, 0);
+// P2P alias entry
+  GnbLibPciRead (PciAddress.AddressValue | 0x18, AccessWidth32, &Value, StdHeader);
+  Start.AddressValue = MAKE_SBDFO (0, (Value >> 8) & 0xff, 0, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, (Value >> 16) & 0xff, 0x1f, 0x7, 0);
+  GnbIvhdAddDeviceAliasRangeEntry (Start, End, PciAddress, 0, Ivhd, StdHeader);
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0);
+// HPET
+  GnbIvhdAddSpecialDeviceEntry (IvhdSpecialDeviceHpet, PciAddress, 0, 0, Ivhd, StdHeader);
+// APIC
+  GnbIvhdAddSpecialDeviceEntry (
+    IvhdSpecialDeviceIoapic,
+    PciAddress,
+    GnbLiGetIoapicId (SbGetSbIoApicBaseAddress (StdHeader), StdHeader),
+    0xD7,
+    Ivhd,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "SbCreateIvhdEntries Exit\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h
new file mode 100644
index 0000000000..264c48e74f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbIommuLib/GnbSbIommuLib.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBSBIOMMULIB_H_
+#define _GNBSBIOMMULIB_H_
+
+
+VOID
+SbCreateIvhdEntries (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
new file mode 100644
index 0000000000..15da5f28ca
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c
@@ -0,0 +1,159 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbSbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Get SB IOAPIC Base Address
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     APIC base address
+ */
+UINT32
+SbGetSbIoApicBaseAddress (
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT32 ApicBaseAddress;
+  GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x34, 4, &ApicBaseAddress, StdHeader);
+  return ApicBaseAddress & 0xfffffff8;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Get SB MMIO Base Address
+ *
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     MMIO base address
+ */
+UINT32
+SbGetSbMmioBaseAddress (
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT32 MmioBaseAddress;
+  GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x24, 4, &MmioBaseAddress, StdHeader);
+  return MmioBaseAddress & 0xfffffffc;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Alink config address
+ *
+ * @param[in]  StdHeader       Standard configuration header
+ * @retval     Alink base address
+ */
+/*----------------------------------------------------------------------------------------*/
+
+UINT16
+SbGetAlinkIoAddress (
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+
+  UINT16 AlinkPortAddress;
+  GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0xE0, 2, &AlinkPortAddress, StdHeader);
+  return  AlinkPortAddress;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h
new file mode 100644
index 0000000000..3ba80d462e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * SB services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBSBLIB_H_
+#define _GNBSBLIB_H_
+
+#include "GnbPcie.h"
+
+UINT32
+SbGetSbIoApicBaseAddress (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+UINT32
+SbGetSbMmioBaseAddress (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+UINT16
+SbGetAlinkIoAddress (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+SbPcieInitAspm (
+  IN      PCIE_ASPM_TYPE            Aspm,
+  IN      AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+AGESA_STATUS
+SbPcieLinkAspmControl (
+  IN      PCIe_ENGINE_CONFIG        *Engine,
+  IN      PCIe_PLATFORM_CONFIG      *Pcie
+  );
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
new file mode 100644
index 0000000000..a592041fe5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c
@@ -0,0 +1,169 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB-SB link procedure
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbSbLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable/Disable ASPM on GNB-SB link
+ *
+ *
+ *
+ * @param[in]  Engine          Pointer to engine config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+AGESA_STATUS
+SbPcieLinkAspmControl (
+  IN      PCIe_ENGINE_CONFIG    *Engine,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS    Status;
+  PCIE_ASPM_TYPE  Aspm;
+
+  Aspm = Engine->Type.Port.PortData.LinkAspm;
+
+  Status = SbPcieInitAspm (Aspm, GnbLibGetHeader (Pcie));
+  if (Status != AGESA_SUCCESS) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PcieAspmEnableOnFunction (Engine->Type.Port.Address, Aspm, GnbLibGetHeader (Pcie));
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SB ASPM.
+ * Enable ASPM states on SB
+ *
+ *
+ * @param[in] Aspm       ASPM bitmap.
+ * @param[in] StdHeader  Standard configuration header
+ */
+/*----------------------------------------------------------------------------------------*/
+
+AGESA_STATUS
+SbPcieInitAspm (
+  IN      PCIE_ASPM_TYPE       Aspm,
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT16        AlinkPort;
+
+  AlinkPort = SbGetAlinkIoAddress (StdHeader);
+  ASSERT (AlinkPort != 0);
+  if (AlinkPort == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader);
+  GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader);
+  GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader);
+  GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader);
+  GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader);
+  GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader);
+  return AGESA_SUCCESS;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
new file mode 100644
index 0000000000..bb0a47ca40
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbSview/GnbSview.c
@@ -0,0 +1,155 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Interface to initialize Graphics Controller at mid POST
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersLN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+GfxInitSview (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SVIEW configuration
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxInitSview (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status =  GfxLocateConfigData (StdHeader, &Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    if (GfxLibIsControllerPresent (StdHeader)) {
+      if (!GfxFmIsVbiosPosted (Gfx)) {
+        GFX_VBIOS_IMAGE_INFO  VbiosImageInfo;
+        LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
+        VbiosImageInfo.ImagePtr = NULL;
+        VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress;
+        VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST;
+        GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader);
+        Status = AgesaGetVbiosImage (0, &VbiosImageInfo);
+        if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) {
+          GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx);
+        } else {
+          GfxFmDisableController (StdHeader);
+          AgesaStatus = AGESA_ERROR;
+        }
+        GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xf8, BIT1 | BIT2, StdHeader);
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
new file mode 100644
index 0000000000..8d7d5dbb02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c
@@ -0,0 +1,384 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "Gnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbLib.h"
+#include  "GnbTimerLib.h"
+#include  "GnbFamServices.h"
+#include  "GnbTable.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+STATIC
+GnbProcessTableRegisterRmw (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_REGISTER_SERVICE  *GnbRegisterAccessProtocol,
+  IN      GNB_RMW_BLOCK         *Data,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process table
+ *
+ * @param[in] GnbHandle       Gnb handle
+ * @param[in] Table           Table pointer
+ * @param[in] Property        Property
+ * @param[in] Flags           Flags
+ * @param[in] StdHeader       Standard configuration header
+ */
+
+AGESA_STATUS
+GnbProcessTable (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_TABLE             *Table,
+  IN      UINT32                Property,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8                   *EntryPointer;
+  UINT64                  Data;
+  UINT64                  Temp;
+  UINT64                  Mask;
+  UINT32                  WriteAccFlags;
+  GNB_REGISTER_SERVICE    *GnbRegisterAccessProtocol;
+  CPU_LOGICAL_ID          LogicalId;
+  AGESA_STATUS            Status;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Enter\n");
+  IDS_HDT_CONSOLE (GNB_TRACE, " Property - 0x%08x\n", Property);
+
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader);
+  EntryPointer = (UINT8 *) Table;
+  WriteAccFlags = 0;
+  if ((Flags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) {
+    WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE;
+  }
+
+  Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader);
+  ASSERT (Status == AGESA_SUCCESS);
+
+  while (*EntryPointer != GnbEntryTerminate) {
+    Data = 0;
+    Temp = 0;
+    switch (*EntryPointer) {
+    case GnbEntryWr:
+      GnbRegisterAccessProtocol->Write (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_WR*) EntryPointer)->RegisterSpaceType,
+        ((GNB_TABLE_ENTRY_WR*) EntryPointer)->Address,
+        &((GNB_TABLE_ENTRY_WR*) EntryPointer)->Value,
+        WriteAccFlags,
+        StdHeader
+        );
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_WR);
+      break;
+    case GnbEntryPropertyWr:
+      if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Property) != 0) {
+        GnbRegisterAccessProtocol->Write (
+          GnbHandle,
+          ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->RegisterSpaceType,
+          ((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Address,
+          &((GNB_TABLE_ENTRY_PROPERTY_WR *) EntryPointer)->Value,
+          WriteAccFlags,
+          StdHeader
+          );
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_WR);
+      break;
+    case GnbEntryFullWr:
+      if ((Property & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Property) != 0) {
+        if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Revision) != 0) {
+          GnbRegisterAccessProtocol->Write (
+            GnbHandle,
+            ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->RegisterSpaceType,
+            ((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Address,
+            &((GNB_TABLE_ENTRY_FULL_WR*) EntryPointer)->Value,
+            WriteAccFlags,
+            StdHeader
+            );
+        }
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_WR);
+      break;
+    case GnbEntryRmw:
+      GnbProcessTableRegisterRmw (
+        GnbHandle,
+        GnbRegisterAccessProtocol,
+        &((GNB_TABLE_ENTRY_RMW *) EntryPointer)->Data,
+        WriteAccFlags,
+        StdHeader
+        );
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_RMW);
+      break;
+    case GnbEntryPropertyRmw:
+      if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Property) != 0) {
+        GnbProcessTableRegisterRmw (
+          GnbHandle,
+          GnbRegisterAccessProtocol,
+          &((GNB_TABLE_ENTRY_PROPERTY_RMW *) EntryPointer)->Data,
+          WriteAccFlags,
+          StdHeader
+          );
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_RMW);
+      break;
+    case GnbEntryRevRmw:
+      if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Revision) != 0) {
+        GnbProcessTableRegisterRmw (
+          GnbHandle,
+          GnbRegisterAccessProtocol,
+          &((GNB_TABLE_ENTRY_REV_RMW *) EntryPointer)->Data,
+          WriteAccFlags,
+          StdHeader
+          );
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_REV_RMW);
+      break;
+    case GnbEntryFullRmw:
+      if ((Property & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Property) != 0) {
+        if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) {
+          GnbProcessTableRegisterRmw (
+            GnbHandle,
+            GnbRegisterAccessProtocol,
+            &((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Data,
+            WriteAccFlags,
+            StdHeader
+            );
+        }
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_RMW);
+      break;
+    case GnbEntryPoll:
+      do {
+        GnbRegisterAccessProtocol->Read (
+          GnbHandle,
+          ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->RegisterSpaceType,
+          ((GNB_TABLE_ENTRY_POLL *) EntryPointer)->Address,
+          &Data,
+          0,
+          StdHeader
+          );
+      } while ((Data & ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_POLL*) EntryPointer)->CompareValue);
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_POLL);
+      break;
+    case GnbEntryPropertyPoll:
+      if ((Property & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Property) != 0) {
+        do {
+          GnbRegisterAccessProtocol->Read (
+            GnbHandle,
+            ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->RegisterSpaceType,
+            ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->Address,
+            &Data,
+            0,
+            StdHeader
+            );
+        } while ((Data & ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_PROPERTY_POLL *) EntryPointer)->CompareValue);
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_PROPERTY_POLL);
+      break;
+    case GnbEntryFullPoll:
+      if ((Property & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Property) != 0) {
+        if ((LogicalId.Revision & ((GNB_TABLE_ENTRY_FULL_RMW *) EntryPointer)->Revision) != 0) {
+          do {
+            GnbRegisterAccessProtocol->Read (
+              GnbHandle,
+              ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->RegisterSpaceType,
+              ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->Address,
+              &Data,
+              0,
+              StdHeader
+              );
+          } while ((Data & ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->AndMask) != ((GNB_TABLE_ENTRY_FULL_POLL *) EntryPointer)->CompareValue);
+        }
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_FULL_POLL);
+      break;
+    case GnbEntryCopy:
+      GnbRegisterAccessProtocol->Read (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcRegisterSpaceType,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcAddress,
+        &Data,
+        0,
+        StdHeader
+        );
+      Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldWidth) - 1;
+      Data = (Data >> ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->SrcFieldOffset) & Mask;
+      GnbRegisterAccessProtocol->Read (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress,
+        &Temp,
+        0,
+        StdHeader
+        );
+      Mask = (1ull << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldWidth) - 1;
+      Temp = Temp & ( ~ (Mask << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset));
+      Temp = Temp | ((Data & Mask) << ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestFieldOffset);
+      GnbRegisterAccessProtocol->Write (
+        GnbHandle,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestRegisterSpaceType,
+        ((GNB_TABLE_ENTRY_COPY*) EntryPointer)->DestAddress,
+        &Temp,
+        WriteAccFlags,
+        StdHeader
+        );
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_COPY);
+      break;
+    case GnbEntryStall:
+      if ((WriteAccFlags & GNB_TABLE_FLAGS_FORCE_S3_SAVE) != 0) {
+        GnbLibStallS3Save (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader);
+      } else {
+        GnbLibStall (((GNB_TABLE_ENTRY_STALL*) EntryPointer)->Microsecond, StdHeader);
+      }
+      EntryPointer = EntryPointer + sizeof (GNB_TABLE_ENTRY_STALL);
+      break;
+    default:
+      ASSERT (FALSE);
+      IDS_HDT_CONSOLE (NB_MISC, "  ERROR!!! Regiter table parse\n");
+      return AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbProcessTableExt Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Supporting function for register read modify write
+ *
+ * @param[in] GnbHandle                 Gnb handle
+ * @param[in] GnbRegisterAccessProtocol Register access protocol
+ * @param[in] Data                      Data pointer
+ * @param[in] Flags                     Flags
+ * @param[in] StdHeader                 Standard configuration header
+ */
+
+VOID
+STATIC
+GnbProcessTableRegisterRmw (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_REGISTER_SERVICE  *GnbRegisterAccessProtocol,
+  IN      GNB_RMW_BLOCK         *Data,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT64  Value;
+  Value = 0;
+  GnbRegisterAccessProtocol->Read (
+    GnbHandle,
+    Data->RegisterSpaceType,
+    Data->Address,
+    &Value,
+    0,
+    StdHeader
+    );
+  Value = (Value & (~ (UINT64) Data->AndMask)) | Data->OrMask;
+  GnbRegisterAccessProtocol->Write (
+    GnbHandle,
+    Data->RegisterSpaceType,
+    Data->Address,
+    &Value,
+    Flags,
+    StdHeader
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h
new file mode 100644
index 0000000000..02b0f52b46
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.h
@@ -0,0 +1,265 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Service procedure to access PCI config space registers
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBTABLE_H_
+#define _GNBTABLE_H_
+
+#include "GnbPcie.h"
+
+#pragma pack (push, 1)
+
+#define GNB_TABLE_FLAGS_FORCE_S3_SAVE  0x00000001ul
+
+typedef UINT8 GNB_TABLE;
+
+#define __DATA(x) x
+
+#define _DATA32(Data) (__DATA(Data)) & 0xFF, ((__DATA(Data)) >> 8) & 0xFF, ((__DATA(Data)) >> 16) & 0xFF, ((__DATA(Data)) >> 24) & 0xFF
+#define _DATA64(Data) _DATA32(Data & 0xfffffffful) , _DATA32(Data >> 32)
+
+/// Entry type
+typedef enum {
+  GnbEntryWr,                     ///< Write register
+  GnbEntryPropertyWr,             ///< Write register check property
+  GnbEntryFullWr,                 ///< Write Rgister check revision and property
+  GnbEntryRmw,                    ///< Read Modify Write register
+  GnbEntryPropertyRmw,            ///< Read Modify Write register check property
+  GnbEntryRevRmw,                 ///< Read Modify Write register check revision
+  GnbEntryFullRmw,                ///< Read Modify Write register check revision and property
+  GnbEntryPoll,                   ///< Poll register
+  GnbEntryPropertyPoll,           ///< Poll register check property
+  GnbEntryFullPoll,               ///< Poll register check property
+  GnbEntryCopy,                   ///< Copy field from one register to another
+  GnbEntryStall,                  ///< Copy field from one register to another
+  GnbEntryTerminate = 0xFF        ///< Terminate table
+} GNB_TABLE_ENTRY_TYPE;
+
+#define GNB_ENTRY_WR(RegisterSpaceType, Address, Value) \
+  GnbEntryWr, RegisterSpaceType, _DATA32 (Address), _DATA32 (Value)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  Value;                  ///< Value
+} GNB_TABLE_ENTRY_WR;
+
+#define GNB_ENTRY_PROPERTY_WR(Property, RegisterSpaceType, Address, Value) \
+  GnbEntryPropertyWr, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  Value;                  ///< Value
+} GNB_TABLE_ENTRY_PROPERTY_WR;
+
+
+#define GNB_ENTRY_RMW(RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryRmw, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+///Read Modify Write data Block
+typedef struct {
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< And Mask
+  UINT32  OrMask;                 ///< Or Mask
+} GNB_RMW_BLOCK;
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_RMW;
+
+#define GNB_ENTRY_FULL_WR(Property, Revision, RegisterSpaceType, Address, Value) \
+   GnbEntryFullWr, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (Value)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT64  Revision;               ///< Revision
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  Value;                  ///< Value
+} GNB_TABLE_ENTRY_FULL_WR;
+
+
+#define GNB_ENTRY_PROPERTY_RMW(Property,  RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryPropertyRmw, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  UINT32          Property;       ///< Property
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_PROPERTY_RMW;
+
+#define GNB_ENTRY_REV_RMW(Rev,  RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryRevRmw, _DATA64 (Rev), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  UINT64          Revision;       ///< revision
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_REV_RMW;
+
+#define GNB_ENTRY_FULL_RMW(Property, Revision, RegisterSpaceType, Address, AndMask, OrMask) \
+  GnbEntryFullRmw, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (OrMask)
+
+/// Read Modify Write register entry
+typedef struct {
+  UINT8           EntryType;      ///< Entry type
+  UINT32          Property;       ///< Property
+  UINT64          Revision;       ///< Revision
+  GNB_RMW_BLOCK   Data;           ///< Data
+} GNB_TABLE_ENTRY_FULL_RMW;
+
+#define GNB_ENTRY_POLL(RegisterSpaceType, Address, AndMask, CompareValue) \
+  GnbEntryPoll, RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue)
+/// Poll register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< End mask
+  UINT32  CompareValue;           ///< Compare value
+} GNB_TABLE_ENTRY_POLL;
+
+#define GNB_ENTRY_PROPERTY_POLL(Property, RegisterSpaceType, Address, AndMask, CompareValue) \
+  GnbEntryPropertyPoll, _DATA32 (Property), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue)
+/// Poll register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< End mask
+  UINT32  CompareValue;           ///< Compare value
+} GNB_TABLE_ENTRY_PROPERTY_POLL;
+
+#define GNB_ENTRY_FULL_POLL(Property, Revision, RegisterSpaceType, Address, AndMask, CompareValue) \
+  GnbEntryFullPoll, _DATA32 (Property), _DATA64 (Revision), RegisterSpaceType, _DATA32 (Address), _DATA32 (AndMask), _DATA32 (CompareValue)
+/// Poll register entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT32  Property;               ///< Property
+  UINT64  Revision;               ///< Revision
+  UINT8   RegisterSpaceType;      ///< Register space
+  UINT32  Address;                ///< Register address
+  UINT32  AndMask;                ///< End mask
+  UINT32  CompareValue;           ///< Compare value
+} GNB_TABLE_ENTRY_FULL_POLL;
+
+#define GNB_ENTRY_COPY(DestRegSpaceType, DestAddress, DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, SrcAddress, SrcFieldOffset, SrcFieldWidth) \
+  GnbEntryCopy, DestRegSpaceType, _DATA32 (DestAddress), DestFieldOffset, DestFieldWidth, SrcRegisterSpaceType, _DATA32 (SrcAddress), SrcFieldOffset, SrcFieldWidth
+
+/// Copy regster entry
+typedef struct {
+  UINT8   EntryType;              ///< Entry type
+  UINT8   DestRegisterSpaceType;  ///< Register space
+  UINT32  DestAddress;            ///< Register address
+  UINT8   DestFieldOffset;        ///< Field Offset
+  UINT8   DestFieldWidth;         ///< Field Width
+  UINT8   SrcRegisterSpaceType;   ///< Register space
+  UINT32  SrcAddress;             ///< Register address
+  UINT8   SrcFieldOffset;         ///< Field Offset
+  UINT8   SrcFieldWidth;          ///< Field Width
+} GNB_TABLE_ENTRY_COPY;
+
+#define GNB_ENTRY_STALL(Microsecond) \
+  GnbEntryStall, _DATA32 (Microsecond)
+
+/// Write register entry
+typedef struct {
+  UINT8   EntryType;               ///< Entry type
+  UINT32  Microsecond;             ///< Value
+} GNB_TABLE_ENTRY_STALL;
+
+#define GNB_ENTRY_TERMINATE GnbEntryTerminate
+
+AGESA_STATUS
+GnbProcessTable (
+  IN      GNB_HANDLE            *GnbHandle,
+  IN      GNB_TABLE             *Table,
+  IN      UINT32                Property,
+  IN      UINT32                Flags,
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#pragma pack (pop)
+
+#endif