AGESA F15tn: AMD family15 AGESA code for Trinity

AMD AGESA code for trinity. Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
author: zbao <fishbaozi@gmail.com> 2012-07-02 14:19:14 +0800
committer: Patrick Georgi <patrick@georgi-clan.de> 2012-07-03 09:36:35 +0200
commit: 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc (patch)
tree: b0b385455992f0ad3ca6dbbd3266a7a386a80d4f /src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN
parent: 78efc4c36c68b51b3e73acdb721a12ec23ed0369 (diff)
42 files changed, 31632 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
new file mode 100644
index 0000000000..037eadd02a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxEnvInitTN.c
@@ -0,0 +1,493 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbHandleLib.h"
+#include  "GnbTimerLib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA      GfxEnvInitTableTN[];
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Shut Down Disabled SIMDs
+ *
+ * @param[in] Property        GNB property
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxShutDownDisabledSimdsTN (
+  IN      UINT32                Property,
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1006_STRUCT  ex1006 ;
+  ex1009_STRUCT   ex1009;
+  D0F0xBC_xE03002F8_STRUCT  D0F0xBC_xE03002F8;
+  D0F0xBC_xE03002FC_STRUCT  D0F0xBC_xE03002FC;
+  D0F0xBC_xE0300054_STRUCT  GfxChainPgfsmConfig;
+  UINT8                     n;
+  UINT32                    Mask;
+  CPU_LOGICAL_ID            LogicalId;
+  GNB_HANDLE                *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Enter\n");
+
+  GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Gfx));
+
+  GfxChainPgfsmConfig.Value = 0;
+  GfxChainPgfsmConfig.Field.PowerDown = 1;
+  GfxChainPgfsmConfig.Field.P2Select = 1;
+  GfxChainPgfsmConfig.Field.FsmAddr = 0xFF;
+
+  //Step 1: Read fuse to see which SIMD(s) have been disabled
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx));
+
+  //Step 2: Check which SIMD has been disabled
+  for (n = 0; n < 6; n++) {
+    if (((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) || ((ex1006.Field.ex1006_0  >> n) & 0x1)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Disable SIMD %d\n", n);
+      //Step 3: Make sure PGFSM has been programmed in GFX Power Island.
+      //Step 4: Make sure SCLK frequency is below 400Mhz
+      //Step 5: Enable PGFSM clock
+      GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+      ex1009.Value |= (0x1 << (0  + n));
+      GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+      //Step 6
+      GnbRegisterWriteTN (TYPE_D0F0xBC, (D0F0xBC_xE0300054_ADDRESS + (n * 0x1C)), &GfxChainPgfsmConfig.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+      //Step 7
+      Mask = (UINT32) (0x1F << (n * 5));
+      do {
+        GnbRegisterReadTN (D0F0xBC_xE03002F8_TYPE, D0F0xBC_xE03002F8_ADDRESS, &D0F0xBC_xE03002F8.Value, 0, GnbLibGetHeader (Gfx));
+      } while ((D0F0xBC_xE03002F8.Value & Mask )!= 0);
+      //Step 8: Restore previous SCLK divider
+      if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
+        do {
+          GnbRegisterReadTN (D0F0xBC_xE03002FC_TYPE, D0F0xBC_xE03002FC_ADDRESS, &D0F0xBC_xE03002FC.Value, 0, GnbLibGetHeader (Gfx));
+        } while ((D0F0xBC_xE03002FC.Value & Mask )!= Mask);
+      } else {
+      }
+      //Step 10: Turn off PGFSM clock
+      GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+      ex1009.Value &= (~ (UINT64) (0x1 << (0  + n)));
+      GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledSimdsTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Shut Down Disabled SIMDs
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxShutDownDisabledRbsTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1006_STRUCT  ex1006 ;
+  D0F0xBC_xE0003024_STRUCT  D0F0xBC_xE0003024;
+  D0F0xBC_xE03000FC_STRUCT  D0F0xBC_xE03000FC;
+  D0F0xBC_xE0300100_STRUCT  D0F0xBC_xE0300100;
+  ex1009_STRUCT   ex1009 ;
+  D0F0xBC_xE03002F4_STRUCT  D0F0xBC_xE03002F4;
+  D0F0xBC_xE03002E4_STRUCT  D0F0xBC_xE03002E4;
+  UINT8                     i;
+  UINT8                     RbNumber;
+  UINT32                    Mask1;
+  UINT32                    Mask2;
+
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.WriteOp = 1;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Enter\n");
+
+  //Step 1: Read fuse to see which SIMD(s) have been disabled
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe000101c , &ex1006.Value, 0, GnbLibGetHeader (Gfx));
+
+  //Step 2: Power down disabled RB
+  if (ex1006.Field.ex1006_1  == 0x1) {
+    RbNumber = 0;
+    Mask1 = 0x3FFFA;
+    Mask2 = 0x5;
+  } else if (ex1006.Field.ex1006_1  == 0x2) {
+    RbNumber = 1;
+    Mask1 = 0x3FFF5;
+    Mask2 = 0xA;
+  } else {
+    return AGESA_SUCCESS;
+  }
+  //Step 3: Enable PGFSM commands during reset
+  GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE0003024.Value |= 0x1;
+  GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 4: Make sure PGFSM has been programmed before sending power down command.
+  //CB0 = 0, DB0 = 2, CB1 = 1, DB1 = 3
+  for (i = RbNumber; i < 4; i += 2) {
+    D0F0xBC_xE0300100.Value = (5 << 16 ) | (4 << 8 ) | (10 << 0 ); //reg0
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.FsmAddr = i;
+    D0F0xBC_xE03000FC.Field.RegAddr = 2 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+    D0F0xBC_xE0300100.Value = (50 << 0 ) | (50 << 12 ); //reg1
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.RegAddr = 3 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+    D0F0xBC_xE0300100.Value = 0; //control
+    GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    D0F0xBC_xE03000FC.Field.RegAddr = 1 ;
+    GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+  }
+  //Step 5: Make sure SCLK frequency is below 400Mhz
+  //Step 6: Enable PGFSM clock
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+  ex1009.Field.ex1009_1  = 1;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 7
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.PowerDown = 1;
+  D0F0xBC_xE03000FC.Field.P1Select = 1;
+  D0F0xBC_xE03000FC.Field.P2Select = 1;
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 8
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 9: Wait for isolation to be asserted for RB0/RB1
+  do {
+    GnbRegisterReadTN (D0F0xBC_xE03002F4_TYPE, D0F0xBC_xE03002F4_ADDRESS, &D0F0xBC_xE03002F4.Value, 0, GnbLibGetHeader (Gfx));
+  } while ((D0F0xBC_xE03002F4.Value & Mask1 )!= 0);
+  //Step 10: Restore previous SCLK divider
+  //Step 11: Wait for PSO daughter to be asserted for RB0/RB1
+  do {
+    GnbRegisterReadTN (D0F0xBC_xE03002E4_TYPE, D0F0xBC_xE03002E4_ADDRESS, &D0F0xBC_xE03002E4.Value, 0, GnbLibGetHeader (Gfx));
+  } while ((D0F0xBC_xE03002E4.Value & Mask2 )!= Mask2);
+
+  //Step 12: Set PGFSM power up override bits so SMU will not power up disabled RB
+  D0F0xBC_xE0300100.Value = 0x3 << 11;
+  D0F0xBC_xE03000FC.Value = 0;
+  D0F0xBC_xE03000FC.Field.RegAddr = 1 ;
+  GnbRegisterWriteTN (D0F0xBC_xE0300100_TYPE, D0F0xBC_xE0300100_ADDRESS, &D0F0xBC_xE0300100.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE03000FC.Field.FsmAddr = RbNumber + 1;
+  GnbRegisterWriteTN (D0F0xBC_xE03000FC_TYPE, D0F0xBC_xE03000FC_ADDRESS, &D0F0xBC_xE03000FC.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbLibStallS3Save (1, GnbLibGetHeader (Gfx));
+
+  //Step 13: Turn off PGFSM clock
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, 0, GnbLibGetHeader (Gfx));
+  ex1009.Field.ex1009_1  = 1;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0xe0300328 , &ex1009.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  //Step 14: Disable PGFSM commands during reset
+  GnbRegisterReadTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, 0, GnbLibGetHeader (Gfx));
+  D0F0xBC_xE0003024.Value &= 0xFFFFFFFE;
+  GnbRegisterWriteTN (D0F0xBC_xE0003024_TYPE, D0F0xBC_xE0003024_ADDRESS, &D0F0xBC_xE0003024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxShutDownDisabledRbsTN Exit\n");
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GFX straps.
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxEnvInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D0F0x64_x1C_STRUCT  D0F0x64_x1C;
+  D0F0x64_x1D_STRUCT  D0F0x64_x1D;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Enter\n");
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectRead (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0;
+  D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0;
+
+  D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1;
+  D0F0x64_x1C.Field.RcieEn = 0x1;
+
+  D0F0x64_x1D.Field.VgaEn = 0x1;
+
+  D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio;
+  D0F0x64_x1C.Field.F0En = 0x1;
+  D0F0x64_x1C.Field.RegApSize = 0x1;
+
+  if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x1;
+  } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x0;
+  } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) {
+    D0F0x64_x1C.Field.MemApSize = 0x2;
+  } else {
+    D0F0x64_x1C.Field.MemApSize = 0x3;
+  }
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1D.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  D0F0x64_x1C.Field.WriteDis = 0x1;
+
+  GnbLibPciIndirectWrite (
+    GNB_SBDFO | D0F0x60_ADDRESS,
+    D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
+    AccessS3SaveWidth32,
+    &D0F0x64_x1C.Value,
+    GnbLibGetHeader (Gfx)
+    );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInitTN Exit\n");
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Env Post.
+ *
+ *
+ *
+ * @param[in] StdHeader     Standard configuration header
+ * @retval    AGESA_STATUS
+  */
+
+
+AGESA_STATUS
+GfxEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  GNB_HANDLE            *GnbHandle;
+  UINT32                Property;
+  BOOLEAN               ShutDownDisabledSimd;
+  BOOLEAN               ShutDownDisabledRb;
+  UINT8                 SclkDid;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Property = TABLE_PROPERTY_DEAFULT;
+  ShutDownDisabledSimd = GnbBuildOptions.CfgUnusedSimdPowerGatingEnable;
+  ShutDownDisabledRb = GnbBuildOptions.CfgUnusedRbPowerGatingEnable;
+
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnvInitTN (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      ASSERT (Status == AGESA_SUCCESS);
+    } else {
+      GfxFmDisableController (StdHeader);
+      Property |= TABLE_PROPERTY_IGFX_DISABLED;
+    }
+  } else {
+    GfxFmDisableController (StdHeader);
+    Property |= TABLE_PROPERTY_IGFX_DISABLED;
+  }
+  //
+  // Set sclk to 100Mhz
+  //
+  SclkDid = GfxRequestSclkTNS3Save (
+              GfxLibCalculateDidTN (98 * 100, StdHeader),
+              StdHeader
+              );
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GfxEnvInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  if (ShutDownDisabledSimd == TRUE) {
+    GfxShutDownDisabledSimdsTN (Property, Gfx);
+  }
+
+  if ((Property & TABLE_PROPERTY_IGFX_DISABLED) != 0) {
+    if (ShutDownDisabledRb == TRUE) {
+      GfxShutDownDisabledRbsTN (Gfx);
+    }
+  }
+  //
+  // Restore Sclk
+  //
+  GfxRequestSclkTNS3Save (
+    SclkDid,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxEnvInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
new file mode 100644
index 0000000000..1cd96d3d83
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
@@ -0,0 +1,595 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64152 $   @e \$Date: 2012-01-16 21:38:07 -0600 (Mon, 16 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbRegisterAccTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbRegistersTN.h"
+#include  "GfxLibTN.h"
+#include  "GfxGmcInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [];
+extern GNB_TABLE ROMDATA GfxGmcInitTableTN [];
+extern GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [];
+
+
+#define GNB_GFX_DRAM_CH_0_PRESENT 1
+#define GNB_GFX_DRAM_CH_1_PRESENT 2
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+DCT_REGISTER_ENTRY DctRegisterTable [] = {
+  {
+    TYPE_D18F2_dct0,
+    D18F2x94_dct0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct0)
+  },
+  {
+    TYPE_D18F2_dct1,
+    D18F2x94_dct1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x94_dct1)
+  },
+  {
+    TYPE_D18F2_dct0,
+    D18F2x2E0_dct0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct0)
+  },
+  {
+    TYPE_D18F2_dct1,
+    D18F2x2E0_dct1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x2E0_dct1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x200_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x200_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x200_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x200_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x200_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x204_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x204_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x204_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x204_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x204_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x22C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x22C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x22C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x22C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x22C_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x21C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x21C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x21C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x21C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x21C_dct1_mp1)
+  },
+  {
+    TYPE_D18F2_dct0_mp0,
+    D18F2x20C_dct0_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp0)
+  },
+  {
+    TYPE_D18F2_dct0_mp1,
+    D18F2x20C_dct0_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct0_mp1)
+  },
+  {
+    TYPE_D18F2_dct1_mp0,
+    D18F2x20C_dct1_mp0_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp0)
+  },
+  {
+    TYPE_D18F2_dct1_mp1,
+    D18F2x20C_dct1_mp1_ADDRESS,
+    (UINT16) offsetof (DCT_CHANNEL_INFO, D18F2x20C_dct1_mp1)
+  }
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Fb location
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeFbLocationTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx2024_STRUCT   GMMx2024;
+  GMMx2068_STRUCT   GMMx2068;
+  GMMx2C04_STRUCT   GMMx2C04;
+  GMMx5428_STRUCT   GMMx5428;
+  UINT64            FBBase;
+  UINT64            FBTop;
+  FBBase = 0x0F00000000;
+  FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1;
+  GMMx2024.Value = 0;
+  GMMx2C04.Value = 0;
+  GMMx2024.Field.FB_BASE = (UINT16) (FBBase >> 24);
+  GMMx2024.Field.FB_TOP = (UINT16) (FBTop >> 24);
+  GMMx2068.Field.FB_OFFSET = (UINT32) (Gfx->UmaInfo.UmaBase >> 22);
+  GMMx2C04.Field.NONSURF_BASE = (UINT32) (FBBase >> 8);
+  GMMx5428.Field.CONFIG_MEMSIZE = Gfx->UmaInfo.UmaSize >> 20;
+  GnbRegisterWriteTN (GMMx2024_TYPE, GMMx2024_ADDRESS, &GMMx2024.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx2068_TYPE, GMMx2068_ADDRESS, &GMMx2068.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx2C04_TYPE, GMMx2C04_ADDRESS, &GMMx2C04.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (GMMx5428_TYPE, GMMx5428_ADDRESS, &GMMx5428.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Sequencer model info
+ *
+ *
+ * @param[out] DctChannelInfo  Various DCT/GMM info
+ * @param[in]  Gfx             Pointer to global GFX configuration
+ */
+
+STATIC VOID
+GfxGmcDctMemoryChannelInfoTN (
+     OUT   DCT_CHANNEL_INFO              *DctChannelInfo,
+  IN       GFX_PLATFORM_CONFIG           *Gfx
+  )
+{
+
+  UINT32       Index;
+  UINT32       Value;
+
+  for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) {
+    GnbRegisterReadTN (
+      DctRegisterTable[Index].RegisterSpaceType,
+      DctRegisterTable[Index].Address,
+      &Value,
+      0,
+      GnbLibGetHeader (Gfx)
+    );
+    *(UINT32 *)((UINT8 *) DctChannelInfo + DctRegisterTable[Index].DctChannelInfoTableOffset) = Value;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize sequencer model
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeSequencerTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+
+  UINT32                    memps0_freq;
+  UINT32                    memps1_freq;
+  UINT32                    scale_mp0;
+  UINT32                    scale_mp1;
+  UINT8                     DramChannelPresent;
+  ex1047_STRUCT      ex1047      ;
+  ex1048_STRUCT          ex1048 ;
+  ex1060_STRUCT        ex1060    ;
+  ex1061_STRUCT        ex1061    ;
+  ex1062_STRUCT        ex1062    ;
+  DCT_CHANNEL_INFO          DctChannel;
+  D18F5x170_STRUCT          D18F5x170;
+  ex1012_STRUCT         ex1012  ;
+  ex1034_STRUCT        ex1034    ;
+
+  GfxGmcDctMemoryChannelInfoTN (&DctChannel, Gfx);
+
+  DramChannelPresent = 0;
+  if (!DctChannel.D18F2x94_dct1.Field.DisDramInterface) {
+    DramChannelPresent |= GNB_GFX_DRAM_CH_1_PRESENT;
+  }
+
+  if (!DctChannel.D18F2x94_dct0.Field.DisDramInterface) {
+    //if (channel 0 present)
+    //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[0]>[4:0] encoding
+    //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[0]>[28:24] encoding
+    DramChannelPresent |= GNB_GFX_DRAM_CH_0_PRESENT;
+    memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct0.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+    memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+  } else {
+    //memps0_freq = extract frequency from DRAM Configuration High <D18F2x094_dct[1]>[4:0] encoding
+    //memps1_freq = extract frequency from Memory P-state Control Status <D18F2x2E0_dct[1]>[28:24] encoding
+    memps0_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x94_dct1.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+    memps1_freq = GfxLibExtractDramFrequency ((UINT8) DctChannel.D18F2x2E0_dct1.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+  }
+
+  GnbRegisterReadTN (D18F5x170_TYPE, D18F5x170_ADDRESS, &D18F5x170.Value, 0, GnbLibGetHeader (Gfx));
+  if (D18F5x170.Field.MemPstateDis == 1) {
+    memps1_freq = memps0_freq;
+  }
+
+  //scale_mp0 = sclk_max_freq / memps0_freq
+  //scale_mp1 = sclk_max_freq / memps1_freq
+  //Multiply it by 100 to avoid dealing with floating point values
+  scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq;
+  scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq;
+
+  GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x27f0 , &ex1060.Value, 0, GnbLibGetHeader (Gfx));
+  GnbRegisterReadTN (TYPE_GMM , 0x27fc , &ex1061.Value, 0, GnbLibGetHeader (Gfx));
+
+  if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
+    ex1047.Field.ex1047_0 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trcd, DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = (MIN ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd),
+                                     (DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd)) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (MIN (DctChannel.D18F2x204_dct0_mp0.Field.Trc, DctChannel.D18F2x204_dct1_mp0.Field.Trc) * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (MIN (DctChannel.D18F2x200_dct0_mp0.Field.Trp, DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp),
+                                    (DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp)) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO),
+                                     (DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO)) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trcd, DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = (MIN ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd),
+                                     (DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd)) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (MIN (DctChannel.D18F2x204_dct0_mp1.Field.Trc, DctChannel.D18F2x204_dct1_mp1.Field.Trc) * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (MIN (DctChannel.D18F2x200_dct0_mp1.Field.Trp, DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = (MIN ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp),
+                                    (DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp)) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = ((MIN ((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO),
+                                     (DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO)) / 2) * scale_mp1) / 100;
+
+  } else if ((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) {
+    ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct0_mp0.Field.Trcd * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct0_mp0.Field.Trc - DctChannel.D18F2x200_dct0_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct0_mp0.Field.Trc * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct0_mp0.Field.Trp * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct0_mp0.Field.Twr + DctChannel.D18F2x200_dct0_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct0_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp0.Field.Twtr + DctChannel.D18F2x21C_dct0_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct0_mp1.Field.Trcd * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct0_mp1.Field.Trc - DctChannel.D18F2x200_dct0_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct0_mp1.Field.Trc * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct0_mp1.Field.Trp * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct0_mp1.Field.Twr + DctChannel.D18F2x200_dct0_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct0_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct0_mp1.Field.Twtr + DctChannel.D18F2x21C_dct0_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100;
+
+  } else {
+    ex1047.Field.ex1047_0 = (DctChannel.D18F2x200_dct1_mp0.Field.Trcd * scale_mp0) / 100;
+    ex1047.Field.ex1047_1 = ex1047.Field.ex1047_0;
+    ex1047.Field.ex1047_2 = ((DctChannel.D18F2x204_dct1_mp0.Field.Trc - DctChannel.D18F2x200_dct1_mp0.Field.Trcd) * scale_mp0) / 100;
+    ex1047.Field.ex1047_3 = ex1047.Field.ex1047_2;
+
+    ex1048.Field.ex1048_0 = (DctChannel.D18F2x204_dct1_mp0.Field.Trc * scale_mp0) / 100;
+    ex1048.Field.ex1048_1 = (DctChannel.D18F2x200_dct1_mp0.Field.Trp * scale_mp0) / 100;
+    ex1048.Field.ex1048_2 = ((DctChannel.D18F2x22C_dct1_mp0.Field.Twr + DctChannel.D18F2x200_dct1_mp0.Field.Trp) * scale_mp0) / 100;
+    ex1048.Field.ex1048_3 = (((DctChannel.D18F2x20C_dct1_mp0.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp0.Field.Twtr + DctChannel.D18F2x21C_dct1_mp0.Field.TrwtTO) / 2) * scale_mp0) / 100;
+
+    ex1060.Field.ex1060_0 = (DctChannel.D18F2x200_dct1_mp1.Field.Trcd * scale_mp1) / 100;
+    ex1060.Field.ex1060_1 = ex1060.Field.ex1060_0;
+    ex1060.Field.ex1060_2 = ((DctChannel.D18F2x204_dct1_mp1.Field.Trc - DctChannel.D18F2x200_dct1_mp1.Field.Trcd) * scale_mp1) / 100;
+    ex1060.Field.ex1060_3 = ex1060.Field.ex1060_2;
+
+    ex1061.Field.ex1061_0 = (DctChannel.D18F2x204_dct1_mp1.Field.Trc * scale_mp1) / 100;
+    ex1061.Field.ex1061_1 = (DctChannel.D18F2x200_dct1_mp1.Field.Trp * scale_mp1) / 100;
+    ex1061.Field.ex1061_2 = ((DctChannel.D18F2x22C_dct1_mp1.Field.Twr + DctChannel.D18F2x200_dct1_mp1.Field.Trp) * scale_mp1) / 100;
+    ex1061.Field.ex1061_3 = (((DctChannel.D18F2x20C_dct1_mp1.Field.Tcwl + 4 + DctChannel.D18F2x20C_dct1_mp1.Field.Twtr + DctChannel.D18F2x21C_dct1_mp1.Field.TrwtTO) / 2) * scale_mp1) / 100;
+  }
+
+  GnbRegisterWriteTN (TYPE_GMM , 0x2774 , &ex1047.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2778 , &ex1048.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x27f0 , &ex1060.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x27fc , &ex1061.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  ex1062.Field.ex1062_0  = GfxLibGetNumberOfSclkPerDramBurst (scale_mp0, GnbLibGetHeader (Gfx));
+  ex1062.Field.ex1062_1  = GfxLibGetNumberOfSclkPerDramBurst (scale_mp1, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2808 , &ex1062.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+
+  //MC Performance settings base on memory channel configuration
+  //If 1 channel
+  ex1012.Value = 0x210;
+  ex1034.Value = 0x3;
+  if (((DramChannelPresent & GNB_GFX_DRAM_CH_0_PRESENT) != 0) && ((DramChannelPresent & GNB_GFX_DRAM_CH_1_PRESENT) != 0)) {
+    //If 2 channels
+    ex1012.Value = 0x1210;
+    ex1034.Value = 0xC3;
+  }
+  GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *
+ * @param[in] Gfx         Pointer to global GFX configuration
+ */
+
+STATIC VOID
+GfxGmcSecureGarlicAccessTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  ex1064_STRUCT    ex1064 ;
+  ex1065_STRUCT    ex1065 ;
+  GMMx287C_STRUCT   GMMx287C;
+
+  ex1064.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
+  GnbRegisterWriteTN (TYPE_GMM , 0x2868 , &ex1064.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  ex1065.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1);
+  GnbRegisterWriteTN (TYPE_GMM , 0x286c , &ex1065.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  // Areag FB - 32K reserved by VBIOS for SBIOS to use
+  GMMx287C.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 32 * 1024) >> 12);
+  GnbRegisterWriteTN (GMMx287C_TYPE, GMMx287C_ADDRESS, &GMMx287C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize C6 aperture location
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxGmcInitializeC6LocationTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  D18F2x118_STRUCT    D18F2x118;
+  D18F1x44_STRUCT     D18F1x44;
+  GMMx2870_STRUCT     GMMx2870;
+  GMMx2874_STRUCT     GMMx2874;
+
+  // From D18F1x[144:140,44:40] DRAM Base/Limit,
+  // {DramBase[47:24], 00_0000h} <= address[47:0] <= {DramLimit[47:24], FF_FFFFh}.
+  GnbRegisterReadTN (D18F1x44_TYPE, D18F1x44_ADDRESS, &D18F1x44.Value, 0, GnbLibGetHeader (Gfx));
+  //
+  // base 39:20, base = Dram Limit + 1
+  // ex: system 256 MB on Node 0, D18F1x44.Field.DramLimit_39_24_ = 0xE (240MB -1)
+  // Node DRAM     D18F1x[144:140,44:40]    CC6DRAMRange         D18F4x128   D18F1x120 D18F1x124
+  //    0 256MB    0MB ~ 240 MB - 1        240 MB ~ 256 MB - 1     0           0 MB,    256 MB - 1
+  //
+
+  // base 39:20
+  GMMx2870.Value = ((D18F1x44.Field.DramLimit_39_24_ + 1) << 4);
+  // top 39:20
+  GMMx2874.Value = (((D18F1x44.Field.DramLimit_39_24_ + 1) << 24) + (16 * 0x100000) - 1) >> 20;
+
+  // Check C6 enable,  D18F2x118[CC6SaveEn]
+  GnbRegisterReadTN (TYPE_D18F2 , 0x118 , &D18F2x118.Value, 0, GnbLibGetHeader (Gfx));
+
+  if (D18F2x118.Field.CC6SaveEn) {
+
+    GnbRegisterWriteTN (GMMx2874_TYPE, GMMx2874_ADDRESS, &GMMx2874.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+    GnbRegisterWriteTN (GMMx2870_TYPE, GMMx2870_ADDRESS, &GMMx2870.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize GMC
+ *
+ *
+ *
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ *
+ */
+
+AGESA_STATUS
+GfxGmcInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  GMMx28D8_STRUCT   GMMx28D8;
+  ex1017_STRUCT    ex1017 ;
+  GNB_HANDLE        *GnbHandle;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Enter\n");
+   GnbHandle = GnbGetHandle (GnbLibGetHeader (Gfx));
+   ASSERT (GnbHandle != NULL);
+   GnbProcessTable (
+     GnbHandle,
+     GfxGmcColockGatingDisableTN,
+     0,
+     GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+     GnbLibGetHeader (Gfx)
+     );
+   GfxGmcInitializeSequencerTN (Gfx);
+   GfxGmcInitializeFbLocationTN (Gfx);
+   GfxGmcSecureGarlicAccessTN (Gfx);
+   GfxGmcInitializeC6LocationTN (Gfx);
+   GnbProcessTable (
+     GnbHandle,
+     GfxGmcInitTableTN,
+     0,
+     GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+     GnbLibGetHeader (Gfx)
+     );
+   if (Gfx->GmcClockGating) {
+     GnbProcessTable (
+       GnbHandle,
+       GfxGmcColockGatingEnableTN,
+       0,
+       GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+       GnbLibGetHeader (Gfx)
+       );
+   }
+   if (Gfx->UmaSteering == excel993 ) {
+     ex1017.Value = 0x2;
+     GnbRegisterWriteTN (TYPE_GMM , 0x206c , &ex1017.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+   }
+   IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx));
+   if (Gfx->GmcLockRegisters) {
+     GnbRegisterReadTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, 0, GnbLibGetHeader (Gfx));
+     GMMx28D8.Field.CRITICAL_REGS_LOCK = 1;
+     GnbRegisterWriteTN (GMMx28D8_TYPE, GMMx28D8_ADDRESS, &GMMx28D8.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+   }
+   if (Gfx->GmcPowerGating != GmcPowerGatingDisabled) {
+   }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInitTN Exit\n");
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h
new file mode 100644
index 0000000000..91de2f7475
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.h
@@ -0,0 +1,121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXGMCINITTN_H_
+#define _GFXGMCINITTN_H_
+
+#include  "GnbRegistersTN.h"
+
+AGESA_STATUS
+GfxGmcInitTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+
+#pragma pack (push, 1)
+
+/// DCT channel information
+typedef struct {
+  D18F2x94_dct0_STRUCT      D18F2x94_dct0;       ///< Register 0x94
+  D18F2x94_dct1_STRUCT      D18F2x94_dct1;       ///< Register 0x94
+  D18F2x2E0_dct0_STRUCT     D18F2x2E0_dct0;      ///< Register 0x2E0
+  D18F2x2E0_dct1_STRUCT     D18F2x2E0_dct1;      ///< Register 0x2E0
+  D18F2x200_dct0_mp0_STRUCT D18F2x200_dct0_mp0;  ///< Register 0x200
+  D18F2x200_dct0_mp1_STRUCT D18F2x200_dct0_mp1;  ///< Register 0x200
+  D18F2x200_dct1_mp0_STRUCT D18F2x200_dct1_mp0;  ///< Register 0x200
+  D18F2x200_dct1_mp1_STRUCT D18F2x200_dct1_mp1;  ///< Register 0x200
+  D18F2x204_dct0_mp0_STRUCT D18F2x204_dct0_mp0;  ///< Register 0x204
+  D18F2x204_dct0_mp1_STRUCT D18F2x204_dct0_mp1;  ///< Register 0x204
+  D18F2x204_dct1_mp0_STRUCT D18F2x204_dct1_mp0;  ///< Register 0x204
+  D18F2x204_dct1_mp1_STRUCT D18F2x204_dct1_mp1;  ///< Register 0x204
+  D18F2x22C_dct0_mp0_STRUCT D18F2x22C_dct0_mp0;  ///< Register 0x22C
+  D18F2x22C_dct0_mp1_STRUCT D18F2x22C_dct0_mp1;  ///< Register 0x22C
+  D18F2x22C_dct1_mp0_STRUCT D18F2x22C_dct1_mp0;  ///< Register 0x22C
+  D18F2x22C_dct1_mp1_STRUCT D18F2x22C_dct1_mp1;  ///< Register 0x22C
+  D18F2x21C_dct0_mp0_STRUCT D18F2x21C_dct0_mp0;  ///< Register 0x21C
+  D18F2x21C_dct0_mp1_STRUCT D18F2x21C_dct0_mp1;  ///< Register 0x21C
+  D18F2x21C_dct1_mp0_STRUCT D18F2x21C_dct1_mp0;  ///< Register 0x21C
+  D18F2x21C_dct1_mp1_STRUCT D18F2x21C_dct1_mp1;  ///< Register 0x21C
+  D18F2x20C_dct0_mp0_STRUCT D18F2x20C_dct0_mp0;  ///< Register 0x20C
+  D18F2x20C_dct0_mp1_STRUCT D18F2x20C_dct0_mp1;  ///< Register 0x20C
+  D18F2x20C_dct1_mp0_STRUCT D18F2x20C_dct1_mp0;  ///< Register 0x20C
+  D18F2x20C_dct1_mp1_STRUCT D18F2x20C_dct1_mp1;  ///< Register 0x20C
+} DCT_CHANNEL_INFO;
+
+/// DCT_CHANNEL_INFO field entry
+typedef struct {
+  UINT8                 RegisterSpaceType;              ///< Register type
+  UINT32                Address;                        ///< Register address
+  UINT16                DctChannelInfoTableOffset;      ///< destination offset in DCT_CHANNEL_INFO table
+} DCT_REGISTER_ENTRY;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
new file mode 100644
index 0000000000..15c0109566
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
@@ -0,0 +1,922 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64730 $   @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "GeneralServices.h"
+#include  "Gnb.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbSbLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GfxConfigLib.h"
+#include  "GfxLibTN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#define GFX_REFCLK                        100     // (in MHz) Reference clock is 100 MHz
+#define GFX_NCLK_MIN                      700     // (in MHz) Minimum value for NCLK is 700 MHz
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxIntInfoTableInterfaceTN (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+CONST UINT8  DdiLaneConfigArrayTN [][4] = {
+  {31, 24, 1, 0},
+  {24, 31, 0, 1},
+  {24, 27, 0, 0},
+  {27, 24, 0, 0},
+  {28, 31, 1, 1},
+  {31, 28, 1, 1},
+  {32, 38, 2, 2},
+  {32, 35, 2, 2},
+  {35, 32, 2, 2},
+  {8 , 15, 3, 3},
+  {15, 8 , 3, 3},
+  {12, 15, 3, 3},
+  {15, 12, 3, 3},
+  {16, 19, 4, 4},
+  {19, 16, 4, 4},
+  {16, 23, 4, 5},
+  {23, 16, 5, 4},
+  {20, 23, 5, 5},
+  {23, 20, 5, 5},
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init TN Support for eDP to Lvds translators
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegrateducEDPToLVDSRxIdCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8    *uceDPToLVDSRxId;
+  uceDPToLVDSRxId = (UINT8*) Buffer;
+  // APU output DP signal to a 3rd party DP translator chip (Analogix, Parade etc),
+  // the chip is handled by the 3rd party DP Rx firmware and it does not require the AMD SW to have a special
+  // initialize/enable/disable sequence to control this chip, the AMD SW just follows the eDP spec
+  // to enable the LVDS panel through this chip.
+
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToLvds) {
+    *uceDPToLVDSRxId = eDP_TO_LVDS_COMMON_ID;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found 3rd party common EDPToLvds Connector\n");
+  }
+  // APU output DP signal to a 3rd party DP translator chip which requires a AMD SW one time initialization
+  // to the chip based on the LVDS panel parameters ( such as power sequence time and panel SS parameter etc ).
+  // After that, the AMD SW does not need any specific enable/disable sequences to control this chip and just
+  // follows the eDP spec. to control the panel.
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDPToRealtecLvds) {
+    *uceDPToLVDSRxId = eDP_TO_LVDS_REALTEK_ID;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found Realtec EDPToLvds Connector\n");
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN Nb p-State MemclkFreq
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillNbPstateMemclkFreqTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F2x94_dct0_STRUCT            D18F2x94;
+  D18F2x2E0_dct0_STRUCT           D18F2x2E0;
+  D18F5x160_STRUCT                NbPstate;
+  UINT8                           i;
+  UINT8                           Channel;
+  ULONG                           memps0_freq;
+  ULONG                           memps1_freq;
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x94_dct0_TYPE : D18F2x94_dct1_TYPE),
+    ((Channel == 0) ? D18F2x94_dct0_ADDRESS : D18F2x94_dct1_ADDRESS),
+    &D18F2x94.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x2E0_dct0_TYPE : D18F2x2E0_dct1_TYPE),
+    ((Channel == 0) ? D18F2x2E0_dct0_ADDRESS : D18F2x2E0_dct1_ADDRESS),
+    &D18F2x2E0.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  memps0_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x94.Field.MemClkFreq, GnbLibGetHeader (Gfx));
+  memps1_freq = 100 * GfxLibExtractDramFrequency ((UINT8) D18F2x2E0.Field.M1MemClkFreq, GnbLibGetHeader (Gfx));
+
+  for (i = 0; i < 4; i++) {
+    NbPstate.Value = 0;
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      (D18F5x160_ADDRESS + (i * 4)),
+      &NbPstate.Value,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    if (NbPstate.Field.NbPstateEn == 1) {
+      IntegratedInfoTable->ulNbpStateMemclkFreq[i] = (NbPstate.Field.MemPstate == 0) ? memps0_freq : memps1_freq;
+    }
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN HTC Data
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillHtcDataTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  D18F3x64_STRUCT  D18F3x64;
+
+  GnbRegisterReadTN (
+    D18F3x64_TYPE,
+    D18F3x64_ADDRESS,
+    &D18F3x64.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+    );
+
+  if (D18F3x64.Field.HtcEn == 1) {
+    IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
+    IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
+  } else {
+    IntegratedInfoTable->ucHtcTmpLmt = 0;
+    IntegratedInfoTable->ucHtcHystLmt = 0;
+  }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get TN CSR phy self refresh power down mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    CsrPhySrPllPdMode
+ */
+STATIC UINT32
+GfxLibGetMemPhyPllPdModeTN (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2xA8_dct0_STRUCT     D18F2xA8;
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2xA8_dct0_TYPE : D18F2xA8_dct1_TYPE),
+    ((Channel == 0) ? D18F2xA8_dct0_ADDRESS : D18F2xA8_dct1_ADDRESS),
+    &D18F2xA8.Value,
+    0,
+    StdHeader
+  );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "MemPhyPllPdMode : %x\n", D18F2xA8.Field.MemPhyPllPdMode);
+  return  D18F2xA8.Field.MemPhyPllPdMode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get TN disable DLL shutdown in self-refresh mode.
+ *
+ *
+ * @param[in] Channel    DCT controller index
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    DisDllShutdownSR
+ */
+STATIC UINT32
+GfxLibGetDisDllShutdownSRTN (
+  IN       UINT8       Channel,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D18F2x90_dct0_STRUCT D18F2x90;
+
+  GnbRegisterReadTN (
+    ((Channel == 0) ? D18F2x90_dct0_TYPE : D18F2x90_dct1_TYPE),
+    ((Channel == 0) ? D18F2x90_dct0_ADDRESS : D18F2x90_dct1_ADDRESS),
+    &D18F2x90.Value,
+    0,
+    StdHeader
+  );
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "DisDllShutdownSR : %x\n", D18F2x90.Field.DisDllShutdownSR);
+  return  D18F2x90.Field.DisDllShutdownSR;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init TN NbPstateVid
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxFillNbPStateVidTN (
+  IN OUT   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  //TN Register Mapping for D18F5x1[6C:60]
+  D18F5x160_STRUCT  NbPstate[4];
+  D0F0xBC_x1F428_STRUCT  D0F0xBC_x1F428;
+  UINT8             MinNclkIndex;
+  UINT8             i;
+
+  MinNclkIndex = 0;
+  IntegratedInfoTable->ucNBDPMEnable = 0;
+
+
+  GnbRegisterReadTN (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    &D0F0xBC_x1F428.Value,
+    0,
+    GnbLibGetHeader (Gfx)
+  );
+  // Check if NbPstate enbale
+  if (D0F0xBC_x1F428.Field.EnableNbDpm == 1) {
+    //1: enable 0: not enable
+    IntegratedInfoTable->ucNBDPMEnable = 1;
+  }
+
+  for (i = 0; i < 4; i++) {
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      (D18F5x160_ADDRESS + (i * 4)),
+      &NbPstate[i].Value,
+      0,
+      GnbLibGetHeader (Gfx)
+    );
+    if (NbPstate[i].Field.NbPstateEn == 1) {
+      MinNclkIndex = i;
+    }
+    IntegratedInfoTable->ulNbpStateNClkFreq[i] = GfxLibGetNclkTN ((UINT8) NbPstate[i].Field.NbFid, (UINT8) NbPstate[i].Field.NbDid);
+  }
+  IntegratedInfoTable->usNBP0Voltage = (USHORT) ((NbPstate[0].Field.NbVid_7_ << 7) | NbPstate[0].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP1Voltage = (USHORT) ((NbPstate[1].Field.NbVid_7_ << 7) | NbPstate[1].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP2Voltage = (USHORT) ((NbPstate[2].Field.NbVid_7_ << 7) | NbPstate[2].Field.NbVid_6_0_);
+  IntegratedInfoTable->usNBP3Voltage = (USHORT) ((NbPstate[3].Field.NbVid_7_ << 7) | NbPstate[3].Field.NbVid_6_0_);
+
+  IntegratedInfoTable->ulMinimumNClk = GfxLibGetNclkTN ((UINT8) NbPstate[MinNclkIndex].Field.NbFid, (UINT8) NbPstate[MinNclkIndex].Field.NbDid);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize display path for given engine
+ *
+ *
+ *
+ * @param[in]   Engine            Engine configuration info
+ * @param[out]  DisplayPathList   Display path list
+ * @param[in]   Gfx               Pointer to global GFX configuration
+ */
+
+AGESA_STATUS
+GfxFmMapEngineToDisplayPath (
+  IN       PCIe_ENGINE_CONFIG          *Engine,
+     OUT   EXT_DISPLAY_PATH            *DisplayPathList,
+  IN       GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  AGESA_STATUS      Status;
+  UINT8             PrimaryDisplayPathId;
+  UINT8             SecondaryDisplayPathId;
+  UINTN             DisplayPathIndex;
+  PrimaryDisplayPathId = 0xff;
+  SecondaryDisplayPathId = 0xff;
+  for (DisplayPathIndex = 0; DisplayPathIndex <  (sizeof (DdiLaneConfigArrayTN) / 4); DisplayPathIndex++) {
+    if (DdiLaneConfigArrayTN[DisplayPathIndex][0] == Engine->EngineData.StartLane &&
+        DdiLaneConfigArrayTN[DisplayPathIndex][1] == Engine->EngineData.EndLane) {
+      PrimaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][2];
+      SecondaryDisplayPathId = DdiLaneConfigArrayTN[DisplayPathIndex][3];
+      break;
+    }
+  }
+  if (PrimaryDisplayPathId != 0xff) {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
+    Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE;
+    GfxIntegratedCopyDisplayInfo (
+      Engine,
+      &DisplayPathList[PrimaryDisplayPathId],
+      (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL,
+      Gfx
+      );
+    Status = AGESA_SUCCESS;
+  } else {
+    IDS_HDT_CONSOLE (GFX_MISC, "  Error!!! Map DDI lanes %d - %d to display path failed\n",
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane
+      );
+    PutEventLog (
+      AGESA_ERROR,
+      GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION,
+      Engine->EngineData.StartLane,
+      Engine->EngineData.EndLane,
+      0,
+      0,
+      GnbLibGetHeader (Gfx)
+      );
+    Status = AGESA_ERROR;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Copy memory content to FB
+ *
+ *
+ * @param[in] SystemInfoTableV2Ptr    Pointer to integrated info table
+ * @param[in] Gfx                     Pointer to global GFX configuration
+ *
+ */
+STATIC VOID
+GfxIntInfoTabablePostToFb (
+  IN       ATOM_FUSION_SYSTEM_INFO_V2     *SystemInfoTableV2Ptr,
+  IN       GFX_PLATFORM_CONFIG            *Gfx
+  )
+{
+  UINT32      Index;
+  UINT32      TableOffset;
+  UINT32      FbAddress;
+
+  TableOffset = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V2)) | 0x80000000;
+  for (Index = 0; Index < sizeof (ATOM_FUSION_SYSTEM_INFO_V2); Index = Index + 4 ) {
+    FbAddress = TableOffset + Index;
+    GnbLibMemWrite (Gfx->GmmBase + GMMx00_ADDRESS, AccessWidth32, &FbAddress, GnbLibGetHeader (Gfx));
+    GnbLibMemWrite (Gfx->GmmBase + GMMx04_ADDRESS, AccessWidth32, (UINT8*) SystemInfoTableV2Ptr + Index, GnbLibGetHeader (Gfx));
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Dispclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxIntInfoTableInitDispclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN   Index;
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->DisplclkDid[Index] != 0) {
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxFmCalculateClock (
+                                                                             PpFuseArray->DisplclkDid[Index],
+                                                                             GnbLibGetHeader (Gfx)
+                                                                             );
+      IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index;
+    }
+  }
+  IntegratedInfoTable->ucDPMState0VclkFid = PpFuseArray->VclkDid[0];
+  IntegratedInfoTable->ucDPMState1VclkFid = PpFuseArray->VclkDid[1];
+  IntegratedInfoTable->ucDPMState2VclkFid = PpFuseArray->VclkDid[2];
+  IntegratedInfoTable->ucDPMState3VclkFid = PpFuseArray->VclkDid[3];
+  IntegratedInfoTable->ucDPMState0DclkFid = PpFuseArray->DclkDid[0];
+  IntegratedInfoTable->ucDPMState1DclkFid = PpFuseArray->DclkDid[1];
+  IntegratedInfoTable->ucDPMState2DclkFid = PpFuseArray->DclkDid[2];
+  IntegratedInfoTable->ucDPMState3DclkFid = PpFuseArray->DclkDid[3];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Init Sclk <-> VID table
+ *
+ *
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ */
+
+STATIC VOID
+GfxIntInfoTableInitSclkTable (
+  IN       PP_FUSE_ARRAY                    *PpFuseArray,
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx
+  )
+{
+  UINTN                       Index;
+  UINTN                       AvailSclkIndex;
+  ATOM_AVAILABLE_SCLK_LIST    *AvailSclkList;
+  BOOLEAN                     Sorting;
+  AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0];
+
+  AvailSclkIndex = 0;
+  for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+    if (PpFuseArray->SclkDpmDid[Index] != 0) {
+      AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], GnbLibGetHeader (Gfx));
+      AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index];
+      AvailSclkList[AvailSclkIndex].usVoltageID = PpFuseArray->SclkVid[PpFuseArray->SclkDpmVid[Index]];
+      AvailSclkIndex++;
+    }
+  }
+  //Sort by VoltageIndex & ulSupportedSCLK
+  if (AvailSclkIndex > 1) {
+    do {
+      Sorting = FALSE;
+      for (Index = 0; Index < (AvailSclkIndex - 1); Index++) {
+        ATOM_AVAILABLE_SCLK_LIST  Temp;
+        BOOLEAN                   Exchange;
+        Exchange = FALSE;
+        if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) {
+          Exchange = TRUE;
+        }
+        if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) &&
+            (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) {
+          Exchange = TRUE;
+        }
+        if (Exchange) {
+          Sorting = TRUE;
+          LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+          LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
+        }
+      }
+    } while (Sorting);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Read GFX PGFSM register
+ *
+ *
+ * @param[in]  RegisterAddress     Index of PGFSM register
+ * @param[out] Value               Pointer to value
+ * @param[in]  StdHeader           Standard configuration header
+ */
+
+STATIC VOID
+GfxPgfsmRegisterReadTN (
+  IN       UINT32                 RegisterAddress,
+     OUT   UINT32                 *Value,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32      RegisterWriteValue;
+  UINT32      RegisterReadValue;
+  RegisterWriteValue = (RegisterAddress << D0F0xBC_xE0300000_RegAddr_OFFSET) +
+                       (1 << D0F0xBC_xE0300000_ReadOp_OFFSET) +
+                       (0 << D0F0xBC_xE0300000_FsmAddr_OFFSET);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Read PGFSM Register %d\n", RegisterAddress);
+  GnbRegisterWriteTN (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    &RegisterWriteValue,
+    0,
+    StdHeader);
+  do {
+    GnbRegisterReadTN (
+      D0F0xBC_xE0300008_TYPE,
+      D0F0xBC_xE0300008_ADDRESS,
+      &RegisterReadValue,
+      0,
+      StdHeader);
+  } while ((RegisterReadValue & D0F0xBC_xE0300008_ReadValid_MASK) == 0);
+  *Value = RegisterReadValue & D0F0xBC_xE0300008_ReadValue_MASK;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *Calculate ulGMCRestoreResetTime
+ *
+ *
+ * @param[in] IntegratedInfoTable Integrated info table pointer
+ * @param[in] Gfx                 Gfx configuration info
+ * @param[in] PpFuseArray         Fuse array pointer
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxCalculateRestoreResetTimeTN (
+  IN       ATOM_INTEGRATED_SYSTEM_INFO_V1_7 *IntegratedInfoTable,
+  IN       GFX_PLATFORM_CONFIG              *Gfx,
+  IN       PP_FUSE_ARRAY                    *PpFuseArray
+  )
+{
+  UINT8      MaxDid;
+  ULONG      FreqSclk;
+  UINTN      Index;
+  UINT32     TSclk;
+  UINT32     TRefClk;
+  UINT32     TNclkHalf;
+  UINT32     PgfsmDelayReg0;
+  UINT32     PgfsmDelayReg1;
+  UINT32     ResetTime;
+  UINT32     IsoTime;
+  UINT32     MemSd;
+  UINT32     MotherPso;
+  UINT32     DaughterPso;
+  UINT32     THandshake;
+  UINT32     TGmcSync;
+  UINT32     TPuCmd;
+  UINT32     TPgfsmCmdSerialization;
+  UINT32     TReset;
+  UINT32     TMoPso;
+  UINT32     TDaPso;
+  UINT32     TMemSd;
+  UINT32     TIso;
+  UINT32     TRegRestore;
+  UINT32     TPgfsmCleanUp;
+  UINT32     TGmcPu;
+  UINT32     TGmcPd;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Enter\n");
+  // Find FreqSclk = MIN of frequencies SclkDpmDid (0 to 4) and SclkThermDid
+  // First find the highest Did
+  MaxDid = PpFuseArray->SclkThermDid;
+  for (Index = 0; Index < 4; Index++) {
+    // Compare with SclkDpmDid[x] - These are stored in:
+    // IntegratedInfoTable-> sDISPCLK_Voltage[Index].ulMaximumSupportedCLK
+    MaxDid = MAX (MaxDid, PpFuseArray->SclkDpmDid[Index]);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "MaxDid = %d\n", MaxDid);
+  FreqSclk = GfxFmCalculateClock (MaxDid, GnbLibGetHeader (Gfx));
+  // FreqSclk is in 10KHz units - need calculations in nS
+  // For accuracy, do calculations in .01nS, then convert at the end
+  TSclk = (100 * (1000000000 / 10000)) / FreqSclk;
+  // FreqRefClk frequency of reference clock
+  // Caclculate period in .01 nS
+  TRefClk = (100 * 1000) / GFX_REFCLK;
+  // FreqNclkHalf = half of Minimum NCLK value
+  // Calculate period in .01 nS
+  TNclkHalf = (100 * 1000) / (GFX_NCLK_MIN / 2);
+
+  // Read delay time values from PGFSM registers
+  GfxPgfsmRegisterReadTN (2 , &PgfsmDelayReg0, GnbLibGetHeader (Gfx));
+  GfxPgfsmRegisterReadTN (3 , &PgfsmDelayReg1, GnbLibGetHeader (Gfx));
+  ResetTime = (PgfsmDelayReg0 & 0x000000FF ) >> 0 ;
+  IsoTime = (PgfsmDelayReg0 & 0x0000FF00 ) >> 8 ;
+  MemSd = (PgfsmDelayReg0 & 0x00FF0000 ) >> 16 ;
+  MotherPso = (PgfsmDelayReg1 & 0x00000FFF ) >> 0 ;
+  DaughterPso = (PgfsmDelayReg1 & 0x00FFF000 ) >> 12 ;
+  IDS_HDT_CONSOLE (GNB_TRACE, "ResetTime = %d\n", ResetTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "IsoTime = %d\n", IsoTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "MemSd = %d\n", MemSd);
+  IDS_HDT_CONSOLE (GNB_TRACE, "MotherPso = %d\n", MotherPso);
+  IDS_HDT_CONSOLE (GNB_TRACE, "DaughterPso = %d\n", DaughterPso);
+
+  // Calculate various timing values required for the final calculation
+  // THandshake = 10*1/FreqNclkHalf
+  THandshake = 10 * TNclkHalf;
+  // TGmcSync = 2.5*(1/FreqRefclk+1/FreqSclk)
+  TGmcSync = (25 * (TRefClk + TSclk)) / 10;
+  // TPuCmd =9*1/FreqSclk
+  TPuCmd = 9 * TSclk;
+  // TPgfsmCmdSerialization = 82*1/FreqSclk
+  TPgfsmCmdSerialization = 82 * TSclk;
+  // TReset = (RESET_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TGmcSync
+  TReset = ((ResetTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TMoPso = (MOTHER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TMoPso = ((MotherPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TDaPso = (DAUGHTER_PSO+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TDaPso = ((DaughterPso + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TMemSD = (MEM_SD+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TMemSd = ((MemSd + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TIso = (ISO_TIME+3)*1/FreqRefclk+3*1/FreqSclk+TgmcSync
+  TIso = ((IsoTime + 3) * TRefClk) + (3 * TSclk) + TGmcSync;
+  // TRegRestore = 508*1/FreqSclk
+  TRegRestore = 508 * TSclk;
+  // TPgfsmCleanUp = 3*1/FreqSclk
+  TPgfsmCleanUp = 3 * TSclk;
+  // TGmcPu = TPUCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSD + TIso + TRegRestore
+  TGmcPu = TPuCmd + TPgfsmCmdSerialization + TReset + TMoPso + TDaPso + TMemSd + TIso + TRegRestore;
+  // TGmcPd = THandshake + TPgfsmCmdSerialization + Tiso + TmemSD + TMoPso + TDaPso + TpgfsmCleanUp + 3*TReset
+  TGmcPd = THandshake + TPgfsmCmdSerialization + TIso + TMemSd + TMoPso + TDaPso + TPgfsmCleanUp + (3 * TReset);
+  // ulGMCRestoreResetTime = TGmcPu + TGmcPd
+  // All calculated times are in .01nS for accuracy.  We can now correct that.
+  // By adding 99 and dividing by 100, value is rounded up to next 1 nS
+  IntegratedInfoTable->ulGMCRestoreResetTime = (TGmcPd + TGmcPu + 99) / 100;
+  IDS_HDT_CONSOLE (GNB_TRACE, "ulGMCRestoreResetTime = %d\n", IntegratedInfoTable->ulGMCRestoreResetTime);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxCalculateRestoreResetTimeTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *
+ *
+ *
+ * @param[in] Gfx             Gfx configuration info
+ * @retval    AGESA_STATUS
+ */
+AGESA_STATUS
+STATIC
+GfxIntInfoTableInitTN (
+  IN      GFX_PLATFORM_CONFIG     *Gfx
+  )
+{
+  AGESA_STATUS                    Status;
+  AGESA_STATUS                    AgesaStatus;
+  ATOM_FUSION_SYSTEM_INFO_V2      SystemInfoTableV2;
+  PP_FUSE_ARRAY                   *PpFuseArray;
+  PCIe_PLATFORM_CONFIG            *Pcie;
+  ATOM_PPLIB_POWERPLAYTABLE3      *PpTable;
+  UINT8                           Channel;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n");
+  LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx));
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7);
+  ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512);
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7;
+  SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
+  SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
+  SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3;     //DDR3
+  SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100;    //Set default engine clock to 200MhZ
+  SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
+  SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100;
+  SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
+  SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
+  //Locate PCIe configuration data to get definitions of display connectors
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
+  SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo);
+  SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx));
+
+  SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
+
+  SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
+  if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) {
+    SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429  = Gfx->gfxplmcfg0 ;
+    IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 );
+  }
+
+  SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
+
+  // LVDS
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
+  SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
+  SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
+  SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    Status = GfxIntegratedEnumerateAllConnectors (
+               &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
+               Pcie,
+               Gfx
+               );
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+
+  SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+    GfxIntegrateducEDPToLVDSRxIdCallback,
+    &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
+    Pcie
+    );
+
+  // Build PP table
+  PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable;
+  // Build PP table
+  Status = GfxPowerPlayBuildTable (PpTable,  Gfx);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  // Assign usFormatID to 0x000B to represent Trinity
+  PpTable->usFormatID = 0xB;
+  // Build info from fuses
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    // Build Display clock info
+    GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+    // Build Sclk info table
+    GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  } else {
+    Status = AGESA_ERROR;
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  //@todo review if thouse parameters needed
+  // Fill in Nb P-state MemclkFreq Data
+  GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in HTC Data
+  GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in NB P states VID
+  GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
+  // Fill in NCLK info
+  //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Fill in the M3 arbitration control tables
+  //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  // Family specific data update
+
+  // Determine ulGMCRestoreResetTime
+  Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
+  SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
+  SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
+
+  if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
+    Channel = 0;
+  } else {
+    Channel = 1;
+  }
+  if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2;
+  }
+  if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1;
+  }
+  if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
+    SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0;
+  }
+  SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig);
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
+  //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
+  GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build integrated info table
+ *  GMC FB access requred
+ *
+ *
+ * @param[in]   StdHeader     Standard configuration header
+ * @retval      AGESA_STATUS
+ */
+AGESA_STATUS
+GfxIntInfoTableInterfaceTN (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  AGESA_STATUS                    AgesaStatus;
+  AGESA_STATUS                    Status;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  if (GfxLibIsControllerPresent (StdHeader)) {
+    Status = GfxLocateConfigData (StdHeader, &Gfx);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    if (Status != AGESA_FATAL) {
+      Status = GfxIntInfoTableInitTN (Gfx);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus);
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
new file mode 100644
index 0000000000..8aace220c3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
@@ -0,0 +1,478 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "S3SaveState.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GfxLibTN.h"
+#include  "GnbCommonLib.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = {
+{0 ,  0 ,  0 ,  0 ,  333,  0,  400,  0 },
+{0 ,  0 ,  533,  0 ,  0 ,  0 ,  667,  0 },
+{0 ,  0 ,   800,  0 ,  0 ,  0 ,  0 ,  0 },
+{0 , 1050, 1066, 0 , 0,    0 , 0,    1200}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GfxFmDisableController (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable GFX controller
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ */
+
+VOID
+GfxFmDisableController (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  GnbLibPciRMW (
+    MAKE_SBDFO (0, 0, 0, 0,D0F0x7C_ADDRESS),
+    AccessS3SaveWidth32,
+    0xffffffff,
+    1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get system PLL COF
+ *
+ *
+ *
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    System PLL COF
+ */
+UINT32
+GfxLibGetSytemPllCofTN (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  D0F0xBC_xFF000000_STRUCT  D0F0xBC_xFF000000;
+  GnbRegisterReadTN (D0F0xBC_xFF000000_TYPE,  D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader);
+  return 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 0x10);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate COF for DFS out of Main PLL
+ *
+ *
+ *
+ * @param[in] Did         Did
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                COF in 10khz
+ */
+
+UINT32
+GfxFmCalculateClock (
+  IN       UINT8                       Did,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32  Divider;
+  UINT32  SystemPllCof;
+  SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100;
+  if (Did >= 8 && Did <= 0x3F) {
+    Divider = Did * 25;
+  } else if (Did > 0x3F && Did <= 0x5F) {
+    Divider = (Did - 64) * 50 + 1600;
+  } else if (Did > 0x5F && Did <= 0x7E) {
+    Divider = (Did - 96) * 100 + 3200;
+  } else if (Did == 0x7f) {
+    Divider = 128 * 100;
+  } else {
+    ASSERT (FALSE);
+    return 200 * 100;
+  }
+  ASSERT (Divider != 0);
+  return (((SystemPllCof * 100) + (Divider - 1)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set idle voltage mode for GFX
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+BOOLEAN
+GfxFmIsVbiosPosted (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32  Value;
+
+  GnbRegisterReadTN (GMMx670_TYPE, GMMx670_ADDRESS, &Value, 0, GnbLibGetHeader (Gfx));
+  return ((Value & BIT16) == 0) ? TRUE : FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Extract DRAM frequency
+ *
+ *
+ *
+ * @param[in] Encoding   Memory Clock Frequency Value Definition
+ * @param[in] StdHeader  Standard configuration header
+ * @retval    Dram fraquency Mhz
+ */
+UINT32
+GfxLibExtractDramFrequency (
+  IN       UINT8                  Encoding,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  if (Encoding >= (sizeof (GfxMemClockFrequencyDefinitionTable) / sizeof (UINT16))) {
+    ASSERT (FALSE);
+    return 0;
+  }
+  return GfxMemClockFrequencyDefinitionTable[Encoding / 8][Encoding % 8];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max SCLK
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    Max SCLK in Mhz
+ */
+UINT32
+GfxLibGetMaxSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32                    MaxSclkClk;
+  D0F0xBC_xFF000000_STRUCT  D0F0xBC_xFF000000;
+  D0F0xBC_xE0003048_STRUCT  D0F0xBC_xE0003048;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xFF000000_ADDRESS, &D0F0xBC_xFF000000.Value, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0003048_ADDRESS, &D0F0xBC_xE0003048.Value, 0, StdHeader);
+  //sclk_max_freq = 100 * (GCLK_PLL_FUSES.MainPllOptFreqIdStartup + 16) /
+  //                (((SCLK_MIN_DIV.INT<<12 + SCLK_MIN_DIV.FRAC)>>12)
+  MaxSclkClk = 100 * (D0F0xBC_xFF000000.Field.MainPllOpFreqIdStartup + 16);
+  MaxSclkClk /= ((D0F0xBC_xE0003048.Field.Intv << 12) + D0F0xBC_xE0003048.Field.Fracv) >> 12;
+  return MaxSclkClk;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get number of SCLK Dram burst
+ *
+ *
+ * @param[in] ScaleMp         Scaled number of sclk_max_freq / memps_freq
+ * @param[in] StdHeader       Standard configuration header
+ * @retval                    number of sclks (*2) per dram burst, except (0,1,2,3)=(1,1.25,1.5,1.75)
+ */
+UINT32
+GfxLibGetNumberOfSclkPerDramBurst (
+  IN       UINT32                ScaleMp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+
+  if ((2 * ScaleMp)  < 125) {
+    return 0; //STATE0 = 0
+  } else if ((2 * ScaleMp)  < 150) {
+    return 1; //STATE0 = 1
+  } else if ((2 * ScaleMp)  < 175) {
+    return 2; //STATE0 = 2
+  } else if ((2 * ScaleMp)  < 200) {
+    return 3; //STATE0 = 3
+  } else {
+    //STATE0 = floor(4*scale_mp[0] )
+    return ((4 * ScaleMp) / 100);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate TN NCLK clock
+ *
+ *
+ *
+ * @param[in] NbFid         NbFid
+ * @param[in] NbDid         NbDid
+ * @retval                  Clock in 10KHz
+ */
+
+UINT32
+GfxLibGetNclkTN (
+  IN      UINT8                   NbFid,
+  IN      UINT8                   NbDid
+  )
+{
+  UINT32  Divider;
+  //i.e. NBCOF[0] = (100 * (D18F5x160[NbFid] + 4h) / (2^D18F5x160[NbDid])) Mhz
+  if (NbDid == 1) {
+    Divider = 2;
+  } else if (NbDid == 0) {
+    Divider = 1;
+  } else {
+    Divider = 1;
+  }
+  ASSERT (NbDid == 0 || NbDid == 1);
+  return ((10000 * (NbFid + 4)) / Divider);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set VID through CG client
+ *
+ *
+ * @param[in] Vid             VID code
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxRequestVoltageTN (
+  IN       UINT8                 Vid,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  GMMx770_STRUCT  GMMx770;
+  GMMx774_STRUCT  GMMx774;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Enter\n");
+
+  GnbRegisterReadTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, 0, StdHeader);
+  GMMx770.Field.VoltageChangeEn = 1;
+  GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  GMMx770.Field.VoltageLevel = Vid;
+  GMMx770.Field.VoltageChangeReq = ~GMMx770.Field.VoltageChangeReq;
+  GnbRegisterWriteTN (GMMx770_TYPE, GMMx770_ADDRESS, &GMMx770, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  do {
+    GnbRegisterReadTN (GMMx774_TYPE, GMMx774_ADDRESS, &GMMx774, 0, StdHeader);
+  } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxRequestVoltageTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SCLK
+ *
+ *
+ * @param[in] Did             Devider
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    previous DID
+ */
+
+UINT8
+GfxRequestSclkTNS3Save (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, GfxRequestSclkTNS3Script_ID, sizeof (Did), &Did);
+  return GfxRequestSclkTN (Did, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set SCLK
+ *
+ *
+ * @param[in] Did             Devider
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+UINT8
+GfxRequestSclkTN (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  GMMx600_STRUCT  GMMx600;
+  GMMx604_STRUCT  GMMx604;
+  UINT8           OriginalDid;
+  do {
+    GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader);
+  } while (GMMx604.Field.SclkStatus == 0);
+  GnbRegisterReadTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader);
+  OriginalDid = (UINT8) GMMx600.Field.IndClkDiv;
+  GMMx600.Field.IndClkDiv = Did;
+  GnbRegisterWriteTN (GMMx600_TYPE, GMMx600_ADDRESS, &GMMx600, 0, StdHeader);
+  do {
+    GnbRegisterReadTN (GMMx604_TYPE, GMMx604_ADDRESS, &GMMx604, 0, StdHeader);
+  } while (GMMx604.Field.SclkStatus == 0);
+  return OriginalDid;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Sclk in S3 script
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        pointer to UINT32 number of us
+ */
+VOID
+GfxRequestSclkTNS3Script (
+  IN      AMD_CONFIG_PARAMS    *StdHeader,
+  IN      UINT16               ContextLength,
+  IN      VOID*                Context
+  )
+{
+  GfxRequestSclkTN (* ((UINT8*) Context), StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate did from main VCO
+ *
+ *
+ *
+ * @param[in] Vco           Vco in 10Khz
+ * @param[in] StdHeader     Standard configuration header
+ * @retval                  DID
+ */
+
+UINT8
+GfxLibCalculateDidTN (
+  IN       UINT32                Vco,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32  Divider;
+  UINT32  SystemPllCof;
+  UINT8   Did;
+  ASSERT (Vco != 0);
+  SystemPllCof = GfxLibGetSytemPllCofTN (StdHeader) * 100;
+  Divider = ((SystemPllCof * 100) + (Vco - 1)) / Vco;
+  Did = 0;
+  if (Divider < 200) {
+  } else if (Divider <= 1575) {
+    Did = (UINT8) (Divider / 25);
+  } else if (Divider <= 3150) {
+    Did = (UINT8) ((Divider - 1600) / 50) + 64;
+  } else if (Divider <= 6200) {
+    Did = (UINT8) ((Divider - 3200) / 100) + 96;
+  } else {
+    Did = 0x7f;
+  }
+  return Did;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h
new file mode 100644
index 0000000000..69dd6477eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.h
@@ -0,0 +1,134 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GFXLIBTN_H_
+#define _GFXLIBTN_H_
+
+UINT32
+GfxLibGetSytemPllCofTN (
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibExtractDramFrequency (
+  IN       UINT8                  Encoding,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT32
+GfxLibGetMaxSclk (
+  IN      AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT32
+GfxLibGetNumberOfSclkPerDramBurst (
+  IN       UINT32                ScaleMp,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT32
+GfxLibGetNclkTN (
+  IN      UINT8                  NbFid,
+  IN      UINT8                  NbDid
+  );
+
+AGESA_STATUS
+GfxRequestVoltageTN (
+  IN       UINT8                 Vid,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT8
+GfxRequestSclkTN (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+UINT8
+GfxRequestSclkTNS3Save (
+  IN       UINT8                 Did,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+VOID
+GfxRequestSclkTNS3Script (
+  IN      AMD_CONFIG_PARAMS      *StdHeader,
+  IN      UINT16                 ContextLength,
+  IN      VOID*                  Context
+  );
+
+UINT8
+GfxLibCalculateDidTN (
+  IN       UINT32                Vco,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
new file mode 100644
index 0000000000..4e3efa5466
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxMidInitTN.c
@@ -0,0 +1,304 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65199 $   @e \$Date: 2012-02-09 21:36:06 -0600 (Thu, 09 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbGfx.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbGfxFamServices.h"
+#include  "GfxLibTN.h"
+#include  "GfxGmcInitTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "PcieConfigData.h"
+#include  "PcieConfigLib.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbHandleLib.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAudioConnectors (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  );
+
+AGESA_STATUS
+GfxMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+VOID
+exec803 /* GfxAzWorkaroundTN */ (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ * @retval    AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GfxSetBootUpVoltageTN (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltageTN Enter\n");
+  GfxRequestVoltageTN (GnbLocateHighestVidCode (GnbLibGetHeader (Gfx)), GnbLibGetHeader (Gfx));
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set boot up voltage
+ *
+ *
+ * @param[in] Gfx             Pointer to global GFX configuration
+ */
+
+VOID
+exec803 /* GfxAzWorkaroundTN */ (
+  IN      GFX_PLATFORM_CONFIG   *Gfx
+  )
+{
+  UINT32                  i;
+  UINT32                  Address;
+  UINT32                  Data;
+
+
+  Data = 0x156;
+  for (i = 0; i < 6; i++) {
+    Address = 0x5E00 + (i * 0x18);
+    GnbLibMemWrite (Gfx->GmmBase + Address, AccessS3SaveWidth32, &Data, GnbLibGetHeader (Gfx));
+    GnbLibMemRMW (Gfx->GmmBase + Address + 4, AccessS3SaveWidth32, 0xFFFFFF00, 0xF0, GnbLibGetHeader (Gfx));
+  }
+
+  return;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Mid Post.
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GfxMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status =  GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_FATAL) {
+    GfxFmDisableController (StdHeader);
+  } else {
+    if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
+      Status = GfxEnableGmmAccess (Gfx);
+      ASSERT (Status == AGESA_SUCCESS);
+      AGESA_STATUS_UPDATE (Status, AgesaStatus);
+      if (Status != AGESA_SUCCESS) {
+        // Can not initialize GMM registers going to disable GFX controller
+        IDS_HDT_CONSOLE (GNB_TRACE, "  Fail to establish GMM access\n");
+        Gfx->UmaInfo.UmaMode = UMA_NONE;
+        GfxFmDisableController (StdHeader);
+      } else {
+        Status = GfxGmcInitTN (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxSetBootUpVoltageTN (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxInitSsid (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        Status = GfxIntegratedEnumerateAudioConnectors (Gfx);
+        AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+        exec803 /* GfxAzWorkaroundTN */ (Gfx);
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine number of audio ports for each connector
+ *
+ *
+ *
+ * @param[in]     Engine  Engine configuration info
+ * @param[in,out] Buffer  Buffer pointer
+ * @param[in]     Pcie    PCIe configuration info
+ */
+VOID
+STATIC
+GfxIntegratedAudioEnumCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8    *AudioCount;
+  AudioCount = (UINT8*) Buffer;
+  if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "Found HDMI Connector\n");
+    (*AudioCount)++;
+  } else if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) {
+    if ((Engine->Type.Ddi.DdiData.Flags & DDI_DATA_FLAGS_DP1_1_ONLY) == 0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.2 Connector\n");
+      *AudioCount += 4;
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Found DP1.1 Connector\n");
+      (*AudioCount)++;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "New AudioCount = %d\n", *AudioCount);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enumerate all display connectors with audio capability and configure number of ports
+ *
+ *
+ *
+ * @param[in]     Gfx             Gfx configuration info
+ */
+AGESA_STATUS
+GfxIntegratedEnumerateAudioConnectors (
+  IN      GFX_PLATFORM_CONFIG         *Gfx
+  )
+{
+  UINT8                   AudioCount;
+  AGESA_STATUS            Status;
+  GMMx5F50_STRUCT         GMMx5F50;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Enter\n");
+
+  Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
+  if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) {
+    AudioCount = 0;
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
+      GfxIntegratedAudioEnumCallback,
+      &AudioCount,
+      Pcie
+      );
+    if (AudioCount > 4) {
+      AudioCount = 4;
+    }
+    GMMx5F50.Value = 0x00;
+    GMMx5F50.Field.PortConnectivity = (7 - AudioCount);
+    GMMx5F50.Field.PortConnectivityOverrideEnable = 1;
+    GnbRegisterWriteTN (GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n");
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
new file mode 100644
index 0000000000..36e013ef3c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxPostInitTN.c
@@ -0,0 +1,155 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbGfx.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbFuseTable.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GfxPostInterfaceTN (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GFX at Post.
+ *
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header
+ * @retval        AGESA_STATUS
+ */
+
+
+AGESA_STATUS
+GfxPostInterfaceTN (
+  IN       AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_POST_PARAMS       *PostParamsPtr;
+  GFX_CARD_CARD_INFO    GfxDiscreteCardInfo;
+  AGESA_STATUS          Status;
+  GFX_PLATFORM_CONFIG   *Gfx;
+  PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Enter\n");
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  ASSERT (Status == AGESA_SUCCESS);
+  if (Status == AGESA_SUCCESS) {
+    if (GfxLibIsControllerPresent (StdHeader)) {
+      if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
+        LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader);
+        GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader);
+        if (((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) ||
+          (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != GfxDiscreteCardInfo.PcieGfxCardBitmap)) ||
+          ((PostParamsPtr->GnbPostConfig.IgpuEnableDisablePolicy == IGPU_DISABLE_ANY_PCIE)  &&
+          ((GfxDiscreteCardInfo.PciGfxCardBitmap != 0) || (GfxDiscreteCardInfo.PcieGfxCardBitmap != 0)))) {
+          PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+          IDS_HDT_CONSOLE (GFX_MISC, "  GfxDisabled due dGPU policy\n");
+        }
+      }
+    } else {
+      PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+      Gfx->GfxFusedOff = TRUE;
+    }
+  } else {
+    PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GfxPostInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
new file mode 100644
index 0000000000..876614e510
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxTablesTN.c
@@ -0,0 +1,1096 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GFx tables
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64726 $   @e \$Date: 2012-01-30 01:00:01 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbRegistersTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbInitTN.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [] = {
+  //2.1 Disable clock-gating
+  GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00000C80),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00000400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00001401),
+  GNB_ENTRY_TERMINATE
+};
+
+
+GNB_TABLE ROMDATA GfxGmcInitTableTN [] = {
+  GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET),
+  //2.2 System memory address translation
+  GNB_ENTRY_COPY (GMMx2814_TYPE, GMMx2814_ADDRESS,  0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2818_TYPE, GMMx2818_ADDRESS,  0, 32, D18F2x40_dct1_TYPE, D18F2x40_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx281C_TYPE, GMMx281C_ADDRESS,  0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2820_TYPE, GMMx2820_ADDRESS,  0, 32, D18F2x44_dct1_TYPE, D18F2x44_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2824_TYPE, GMMx2824_ADDRESS,  0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2828_TYPE, GMMx2828_ADDRESS,  0, 32, D18F2x48_dct1_TYPE, D18F2x48_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx282C_TYPE, GMMx282C_ADDRESS,  0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2830_TYPE, GMMx2830_ADDRESS,  0, 32, D18F2x4C_dct1_TYPE, D18F2x4C_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2834_TYPE, GMMx2834_ADDRESS,  0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2838_TYPE, GMMx2838_ADDRESS,  0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx283C_TYPE, GMMx283C_ADDRESS,  0, 32, D18F2x60_dct1_TYPE, D18F2x60_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2840_TYPE, GMMx2840_ADDRESS,  0, 32, D18F2x64_dct1_TYPE, D18F2x64_dct1_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS,  0,  8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS,  0,  8),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 16,  1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22,  1),
+  GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 19,  1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20,  1),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS,  0,  8, D18F2x80_dct1_TYPE, D18F2x80_dct1_ADDRESS,  0,  8),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 16,  1, D18F2x94_dct1_TYPE, D18F2x94_dct1_ADDRESS, 22,  1),
+  GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 19,  1, D18F2xA8_dct1_TYPE, D18F2xA8_dct1_ADDRESS, 20,  1),
+  GNB_ENTRY_COPY (GMMx284C_TYPE, GMMx284C_ADDRESS,  0, 32, TYPE_D18F2 , 0x110 ,  0, 32),
+  GNB_ENTRY_COPY (GMMx2850_TYPE, GMMx2850_ADDRESS,  0, 32, D18F2x114_TYPE, D18F2x114_ADDRESS,  0, 32),
+  GNB_ENTRY_COPY (GMMx2854_TYPE, GMMx2854_ADDRESS,  0, 32, D18F1xF0_TYPE,  D18F1xF0_ADDRESS,   0, 32),
+  //GNB_ENTRY_COPY (GMMx2858_TYPE, GMMx2858_ADDRESS,  0, 32, ????, ????,  0, 32),
+  GNB_ENTRY_COPY (GMMx285C_TYPE, GMMx285C_ADDRESS,  0, 32, TYPE_D18F2 , 0x10c ,  0, 32),
+  // 2.4 RENG init
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001b0a05),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000001D),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00080500),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000027),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001050c),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x1000051e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010536),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000031),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001053e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000034),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010546),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000037),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a054e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000053),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001056f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000056),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010572),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000059),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020575),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000800),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a0801),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007b),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001082a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0014082d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000094),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00040843),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000009a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00170851),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000b3),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001d086a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d2),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000891),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d4),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000893),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d6),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020895),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000da),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020899),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000de),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0002089d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e2),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000208a1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e6),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x006808cd),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000150),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0016094d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000168),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d096d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000177),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0009097f),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000182),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000a098a),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000018e),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d0998),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000019d),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000409a7),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001a3),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x003709cd),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001dc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000f0a21),
+  GNB_ENTRY_WR (GMMx28D4_TYPE, GMMx28D4_ADDRESS, 0x7b1ec000),
+  GNB_ENTRY_WR (GMMx28D8_TYPE, GMMx28D8_ADDRESS, 0x200cf01d),
+  // 2.5
+  GNB_ENTRY_RMW (GMMx5490_TYPE, GMMx5490_ADDRESS, GMMx5490_FB_WRITE_EN_MASK | GMMx5490_FB_READ_EN_MASK, (1 << GMMx5490_FB_READ_EN_OFFSET) | (1 << GMMx5490_FB_WRITE_EN_OFFSET)),
+  // 2.6 Perfromance tuning
+  GNB_ENTRY_WR (TYPE_GMM , 0x27d0 , 0x10734847),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27c0 , 0x00032005),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27c4 , 0x00C12008),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27d4 , 0x00003d3c),
+  GNB_ENTRY_WR (TYPE_GMM , 0x277c , 0x00000007),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2198 , 0x000221b1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080A20),
+  GNB_ENTRY_WR (TYPE_GMM , 0x201c , 0x66660006),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2020 , 0x70770007),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2018 , 0x66070050),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2014 , 0x77550000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2794 , 0xfcfcfdfc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2798 , 0xfcfcfdfc),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27a4 , 0x00ffffff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x27a8 , 0x00ffffff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x278c , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2790 , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2628 , 0x44111222),
+  GNB_ENTRY_WR (TYPE_GMM , 0x25e0 , 0x00000004),
+  GNB_ENTRY_WR (TYPE_GMM , 0x262c , 0x11222111),
+  GNB_ENTRY_WR (TYPE_GMM , 0x25e4 , 0x00000002),
+  //2.7 Miscellaneous programming
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b4 , 0x00000000),
+  //2.8 Enabling garlic interface
+  GNB_ENTRY_RMW (TYPE_GMM , 0x2878 , 0x1 , 1 << 0 ),
+  // Limit number of garlic credits to 12
+  GNB_ENTRY_WR (TYPE_GMM , 0x276c , 0x000000ff),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2898 , 0x01800360),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x289c , 0x8000 , 1 << 15 ),
+  GNB_ENTRY_REV_RMW (0x0000000000000100ull , TYPE_GMM , 0x289c , 0x8000 , 0 << 15 ),
+  GNB_ENTRY_RMW (GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 0 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET),
+  GNB_ENTRY_REV_RMW (0x0000000000000100ull , GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 1 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET),
+  //2.10 UVD and VCE latency
+  //These settings are to improve UVD and VCE latency.
+  //They need these settings to get good memory performance.
+  GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080200),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2190 , 0x001EA1A1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2180 , 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x218c , 0x000FA1E1),
+  GNB_ENTRY_WR (GMMx2188_TYPE, GMMx2188_ADDRESS, 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f0 , 0x0000A1F1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21ec , 0x0000A1F1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f8 , 0x0000A1E1),
+  GNB_ENTRY_WR (TYPE_GMM , 0x21f4 , 0x0000A1E1),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x690 , 0x20000000 , 1 << 29 ),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x21a8 , 0x4 , 0),
+//MC Performance settings base on memory channel configuration, so, move settings to GfxGmcInitializeSequencerTN()
+//  GNB_ENTRY_WR (TYPE_GMM , 0x2214 , 0x00000003),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2218 , 0x0000000C),
+  GNB_ENTRY_WR (GMMx2888_TYPE, GMMx2888_ADDRESS, 0x000007DE),
+  GNB_ENTRY_WR (GMMx25C8_TYPE, GMMx25C8_ADDRESS, 0x00403932),
+  GNB_ENTRY_WR (GMMx2114_TYPE, GMMx2114_ADDRESS, 0x00000015),
+  //2.11 Remove blackout
+  GNB_ENTRY_WR (GMMx25C0_TYPE, GMMx25C0_ADDRESS, 0x00000000),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20ec , 0x000001DC),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20d4 , 0x00000016),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20ac , 0x00000000),
+  GNB_ENTRY_RMW (TYPE_GMM , 0x2760 , 0x3 , 1 << 0 ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [] = {
+  GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00040c80),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00040400),
+  GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00041401),
+  //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
+  //Implement in GnbCgttOverrideTN
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GfxEnvInitTableTN [] = {
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_GMM ,
+    0xe60 ,
+    0x0,
+    (0x1 << 1 ) | (0x1 << 0 ) |
+    (0x1 << 5 )  | (0x1 << 2 ) |
+    (0x1 << 7 ) | (0x1 << 6 ) |
+    (0x1 << 9 ) | (0x1 << 8 ) |
+    (0x1 << 11 )  | (0x1 << 10 ) |
+    (0x1 << 14 ) | (0x1 << 13 ) |
+    (0x1 << 17 ) | (0x1 << 15 ) |
+    (0x1 << 19 ) | (0x1 << 18 ) |
+    (0x1 << 24 ) | (0x1 << 20 )
+    ),
+//---------------------------------------------------------------------------
+// Configure GMC Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    (10 << 0 ) | (4 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    (90 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300004_TYPE,
+    D0F0xBC_xE0300004_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300000_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown GMC if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300000_TYPE,
+    D0F0xBC_xE0300000_ADDRESS,
+    (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300000_P1Select_OFFSET) | (1 << D0F0xBC_xE0300000_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300200_TYPE,
+    D0F0xBC_xE0300200_ADDRESS,
+    D0F0xBC_xE0300200_P1IsoN_MASK,
+    0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Configure UVD Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300040_TYPE,
+    D0F0xBC_xE0300040_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030003C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown UVD if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030003C_TYPE,
+    D0F0xBC_xE030003C_ADDRESS,
+    (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE030003C_P1Select_OFFSET) | (1 << D0F0xBC_xE030003C_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300218_TYPE,
+    D0F0xBC_xE0300218_ADDRESS,
+    D0F0xBC_xE0300218_P1IsoN_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Configure VCE Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300028_TYPE,
+    D0F0xBC_xE0300028_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300024_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+// Shutdown VCE if integrated GFX disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300024_TYPE,
+    D0F0xBC_xE0300024_ADDRESS,
+    (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300024_P1Select_OFFSET) | (1 << D0F0xBC_xE0300024_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030020C_TYPE,
+    D0F0xBC_xE030020C_ADDRESS,
+    D0F0xBC_xE030020C_P1IsoN_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_VcePgfsmClockEn_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+
+//---------------------------------------------------------------------------
+// Configure DCE Power Island
+  // Step 1: Take control over DC2 PGFSM. By default display sends power up/down commands.
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03002DC_TYPE,
+    D0F0xBC_xE03002DC_ADDRESS,
+    (1 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET)
+    ),
+  //Step 2: Read CC_RCU_FUSES register
+  //If Internal GPU is fused off go to Step 3, ELSE Go to Step 4.
+
+  //Step 3: Enable PGFSM commands during reset
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  //Step 4:
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300030_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300030_WriteOp_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300034_TYPE,
+    D0F0xBC_xE0300034_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  //Step 5: IF (cc_rcu_fuses.f.gpu_dis == 0x1) Skip Step6 ELSE Go to Step 6
+  //Step 6: Disable PGFSM commands during reset. Move to after shutdown DCE.
+  //Step 7: Release control over DC2 PGFSM. Move to after shutdown DCE.
+
+// Shutdown DCE if integrated GFX disabled
+  //Step 1: Take control over DC2 PGFSM. By default display sends power up down commands.
+  //Step 2: Read CC_RCU_FUSES register
+  //Step 3: Enable PGFSM commands during reset
+  //Step 4: Make sure SCLK frequency is below 400Mhz
+  //Step 5: Enable PGFSM clock
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK,
+    (1 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET)
+    ),
+  //Step 6
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300030_TYPE,
+    D0F0xBC_xE0300030_ADDRESS,
+    (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300030_P1Select_OFFSET) | (1 << D0F0xBC_xE0300030_P2Select_OFFSET)
+    ),
+  //Step 7
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300210_TYPE,
+    D0F0xBC_xE0300210_ADDRESS,
+    D0F0xBC_xE0300210_P1IsoN_MASK,
+    (0 << D0F0xBC_xE0300210_P1IsoN_OFFSET)
+    ),
+  //Step 8: Restore previous SCLK divider
+  //Step 9: Wait PSO daughter to be asserted
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300210 ,
+    0x2000 ,
+    (1 << 13 )
+    ),
+  //Step 10: Turn off PGFSM clock
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300324_TYPE,
+    D0F0xBC_xE0300324_ADDRESS,
+    D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK,
+    (0 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET)
+    ),
+  //Step 11: Disable PGFSM commands during reset. Same final 2 step as DCE power island
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03002DC_TYPE,
+    D0F0xBC_xE03002DC_ADDRESS,
+    (0 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET)
+    ),
+
+//---------------------------------------------------------------------------
+// Configure GFX Power Island
+
+  //Step 3
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300058_TYPE,
+    D0F0xBC_xE0300058_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300054_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 4
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300074_TYPE,
+    D0F0xBC_xE0300074_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300070_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 5
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300090_TYPE,
+    D0F0xBC_xE0300090_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE030008C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 6
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000AC_TYPE,
+    D0F0xBC_xE03000AC_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000A8_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 7
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C8_TYPE,
+    D0F0xBC_xE03000C8_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000C4_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 8
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E4_TYPE,
+    D0F0xBC_xE03000E4_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000E0_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 9
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    (5 << 16 ) | (4 << 8 ) |
+    (10 << 0 ) //reg0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    (50 << 0 ) | (50 << 12 ) //reg1
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300100_TYPE,
+    D0F0xBC_xE0300100_ADDRESS,
+    0 // control
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE03000FC_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  // Step 10
+    GNB_ENTRY_RMW (
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    0x0
+    ),
+  // Step 12
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+// Shutdown Gfx if integrated GFX disabled
+  // Step 2
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x1
+    ),
+  // Step 3: Save current SCLK. Make sure SCLK frequency is below 400Mhz
+  // Step 5
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    (1 << 0 ) | (1 << 1 ) |
+    (1 << 2 ) | (1 << 3 ) |
+    (1 << 4 ) | (1 << 5 ) |
+    (1 << 6 )
+    ),
+  // Step 6
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300054_TYPE,
+    D0F0xBC_xE0300054_ADDRESS,
+    (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300054_P1Select_OFFSET) | (1 << D0F0xBC_xE0300054_P2Select_OFFSET)
+    ),
+  // Step 7
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0300070_TYPE,
+    D0F0xBC_xE0300070_ADDRESS,
+    (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300070_P1Select_OFFSET) | (1 << D0F0xBC_xE0300070_P2Select_OFFSET)
+    ),
+  // Step 8
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE030008C_TYPE,
+    D0F0xBC_xE030008C_ADDRESS,
+    (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE030008C_P1Select_OFFSET) | (1 << D0F0xBC_xE030008C_P2Select_OFFSET)
+    ),
+  // Step 9
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000A8_TYPE,
+    D0F0xBC_xE03000A8_ADDRESS,
+    (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000A8_P1Select_OFFSET) | (1 << D0F0xBC_xE03000A8_P2Select_OFFSET)
+    ),
+  // Step 10
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000C4_TYPE,
+    D0F0xBC_xE03000C4_ADDRESS,
+    (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000C4_P1Select_OFFSET) | (1 << D0F0xBC_xE03000C4_P2Select_OFFSET)
+    ),
+  // Step 11
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000E0_TYPE,
+    D0F0xBC_xE03000E0_ADDRESS,
+    (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000E0_P1Select_OFFSET) | (1 << D0F0xBC_xE03000E0_P2Select_OFFSET)
+    ),
+  // Step 12
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03000FC_TYPE,
+    D0F0xBC_xE03000FC_ADDRESS,
+    (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE03000FC_P1Select_OFFSET) | (1 << D0F0xBC_xE03000FC_P2Select_OFFSET)
+    ),
+  // Step 13
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03002F4_TYPE,
+    D0F0xBC_xE03002F4_ADDRESS,
+    0xFFFFFFFF,
+    0
+    ),
+  // Step 14
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE03002F0_TYPE,
+    D0F0xBC_xE03002F0_ADDRESS,
+    0xFFFFFFFF,
+    0
+    ),
+  // Step 15: Restore SCLK that is saved in step 4
+  // Step 16
+  GNB_ENTRY_FULL_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */,
+    D0F0xBC_xE03002FC_TYPE,
+    D0F0xBC_xE03002FC_ADDRESS,
+    0xFFFFFFFF,
+    0x3FFFFFFF
+    ),
+  // Step 17
+  GNB_ENTRY_FULL_POLL (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */,
+    D0F0xBC_xE03002E4_TYPE,
+    D0F0xBC_xE03002E4_ADDRESS,
+    0xFFFFFFFF,
+    0x3FFFF
+    ),
+  // Step 18
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300328 ,
+    0x1  | 0x2  |
+    0x4  | 0x8  |
+    0x10  | 0x20  |
+    0x40 ,
+    0
+    ),
+  // Step 19
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003024_TYPE,
+    D0F0xBC_xE0003024_ADDRESS,
+    0x1,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+// Isolate DC, SYS and CP tile when Internal Graphics is disabled
+  // Step 2: Reduce SCLK frequency to 100Mhz. Save current SCLK divider.
+  // Step 3
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F0xBC_xE0003034_TYPE,
+    D0F0xBC_xE0003034_ADDRESS,
+    D0F0xBC_xE0003034_SysIso_MASK | D0F0xBC_xE0003034_CpIso_MASK |
+    D0F0xBC_xE0003034_Dc0Iso_MASK | D0F0xBC_xE0003034_Dc1Iso_MASK |
+    D0F0xBC_xE0003034_DciIso_MASK | D0F0xBC_xE0003034_DcipgIso_MASK,
+    (1 << D0F0xBC_xE0003034_SysIso_OFFSET) | (1 << D0F0xBC_xE0003034_CpIso_OFFSET) |
+    (1 << D0F0xBC_xE0003034_Dc0Iso_OFFSET) | (1 << D0F0xBC_xE0003034_Dc1Iso_OFFSET) |
+    (1 << D0F0xBC_xE0003034_DciIso_OFFSET) | (1 << D0F0xBC_xE0003034_DcipgIso_OFFSET)
+    ),
+  //Step 4: Restore pervious SCLK frequency
+
+//---------------------------------------------------------------------------
+// For IOMMU add logic of GfxDis
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    D0F2xF4_x57_TYPE,
+    D0F2xF4_x57_ADDRESS,
+    D0F2xF4_x57_L1ImuIntGfxDis_MASK,
+    (0x1 << D0F2xF4_x57_L1ImuIntGfxDis_OFFSET)
+    ),
+
+  GNB_ENTRY_TERMINATE
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
new file mode 100644
index 0000000000..b8dc935f43
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.c
@@ -0,0 +1,353 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe early post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALC_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#define GnbFpLibGetExp(V)  ((INT32) ((*((UINT64*) &Value) >> 52) & 0x7FF) - (1023 + 52))
+#define GnbFpLibGetMnts(V) (INT64) ((*((UINT64*) &Value) & ((1ull << 52) - 1)) | (1ull << 52))
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+INT32 _fltused = 0;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calculate power of
+ *
+ *
+ * @param[in]  Value    value
+ * @param[in]  Pow      power
+ * @retval  Value^Pow
+ */
+
+STATIC DOUBLE
+GnbBapmPowerOf (
+  IN      DOUBLE    Value,
+  IN      UINTN     Pow
+  )
+{
+  DOUBLE Result;
+  Result = Value;
+  while ( --Pow > 0) {
+    Result *= Value;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode R from fuse
+ *
+ *
+ * @param[in]  FuseR    R fused value
+ * @retval  R
+ */
+STATIC DOUBLE
+GnbBapmDecodeR (
+  IN      UINT32  FuseR
+  )
+{
+  DOUBLE Value;
+  Value = ((DOUBLE) (FuseR & 0x1ff)) / (2 << (8 - 1));
+  Value = GnbBapmPowerOf (Value, 4);
+  return ((FuseR & 0x200) != 0) ? (-1) * Value : Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode Tau from fuse
+ *
+ *
+ * @param[in]  FuseTau    Tau fused value
+ * @retval  Tau
+ */
+STATIC DOUBLE
+GnbBapmDecodeTau (
+  IN      UINT32  FuseTau
+  )
+{
+  DOUBLE  Value;
+  Value = FuseTau;
+  Value = GnbBapmPowerOf (Value / (2 << (9 - 1)), 16);
+  return  Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calaculate X
+ *
+ *
+ * @param[in]  Ts         Samplig rate
+ * @param[in]  Tau        Tau value
+ * @param[in]  R          R value
+ * @retval  X
+ */
+STATIC DOUBLE
+GnbBapmCalculateX (
+  IN      DOUBLE  Ts,
+  IN      DOUBLE  Tau,
+  IN      DOUBLE  R
+  )
+{
+  //X=(R*Ts)/(2*Tau+Ts);
+  DOUBLE Result;
+  Result = (R * Ts) / (2 * Tau + Ts);
+  return (Result * GnbBapmPowerOf (2, 36)) + 0.5;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calaculate Y
+ *
+ *
+ * @param[in]  Ts         Samplig rate
+ * @param[in]  Tau        Tau value
+ * @retval  Y
+ */
+STATIC DOUBLE
+GnbBapmCalculateY (
+  IN      DOUBLE  Ts,
+  IN      DOUBLE  Tau
+  )
+{
+  //Y=(2*Tau-Ts)/(2*Tau+Ts);
+  DOUBLE Result;
+  Result = (2 * Tau - Ts) / (2 * Tau + Ts);
+  return (Result *  GnbBapmPowerOf (2, 32)) + 0.5;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set X & Y value
+ *
+ *
+ * @param[in]  X          X value
+ * @param[in]  Y          Y value
+ * @param[in]  AddrOffset Offset of address
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmSetYAndX (
+  IN       INT32              X,
+  IN       INT32              Y,
+  IN       UINT32             AddrOffset,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  GnbRegisterWriteTN (
+    D0F0xBC_x1F480_TYPE,
+    D0F0xBC_x1F480_ADDRESS + AddrOffset,
+    &X,
+    0,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "X: 0x%08x\n", X);
+  GnbRegisterWriteTN (
+    D0F0xBC_x1F480_TYPE,
+    D0F0xBC_x1F480_ADDRESS + AddrOffset + 4,
+    &Y,
+    0,
+    StdHeader
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "Y: 0x%08x\n", Y);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Extract INt32 from DOUBLE
+ *
+ *
+ *
+ * @param[in]  Value  Double value
+ * @retval     int32
+ */
+INT32
+GnbFpLibDoubleToInt32 (
+  IN      DOUBLE  Value
+  )
+{
+  INT64   Mantissa;
+  INT32   Exponent;
+  Mantissa = GnbFpLibGetMnts (Value);
+  Exponent = GnbFpLibGetExp (Value);
+  if (Exponent < -64) {
+    Mantissa = 0;
+  } else if (Exponent < 0) {
+    Mantissa >>=  - Exponent;
+  } else {
+    Mantissa <<= Exponent;
+  }
+  return (INT32) ((Value < 0) ? - Mantissa :  Mantissa);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Calcuate BAPM coefficient
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+VOID
+GnbBapmCalculateCoeffsTN (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32  RFuse1;
+  UINT32  TauFuse1;
+  UINT32  Index;
+  DOUBLE  R;
+  DOUBLE  Tau;
+  DOUBLE  Ts;
+  INT32   X;
+  INT32   Y;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Enter\n");
+
+  LibAmdFinit ();
+
+  Ts = ((DOUBLE) (D0F0xBC_x1F468_TimerPeriod_Value * D0F0xBC_x1F46C_BapmPeriod_Value) / 100) / 1000000;
+
+  for (Index = 0; Index < 15; Index++) {
+    GnbRegisterReadTN (
+      TYPE_D0F0xBC ,
+      0xe01040c4  + Index * 4,
+      &RFuse1,
+      0,
+      StdHeader
+      );
+    GnbRegisterReadTN (
+      TYPE_D0F0xBC ,
+      0xe01040c4  + (Index + 15) * 4,
+      &TauFuse1,
+      0,
+      StdHeader
+      );
+
+    R = GnbBapmDecodeR (RFuse1 & 0x3FF);
+    Tau = GnbBapmDecodeTau (TauFuse1 & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+    GnbBapmSetYAndX (X, Y, Index * 2 * 4, StdHeader);
+
+    R = GnbBapmDecodeR ((RFuse1 >> 10) & 0x3FF);
+    Tau = GnbBapmDecodeTau ((TauFuse1 >> 10) & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+
+    GnbBapmSetYAndX (X, Y, (Index * 2 + 30) * 4 , StdHeader);
+
+    R = GnbBapmDecodeR ((RFuse1 >> 20) & 0x3FF);
+    Tau = GnbBapmDecodeTau ((TauFuse1 >> 20) & 0x3FF);
+
+    X = GnbFpLibDoubleToInt32 (GnbBapmCalculateX (Ts, Tau, R));
+    Y = GnbFpLibDoubleToInt32 (GnbBapmCalculateY (Ts, Tau));
+
+    GnbBapmSetYAndX (X, Y, (Index * 2 + 60) * 4 , StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmCalculateCoeffsTN Exit\n");
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h
new file mode 100644
index 0000000000..3ed7b4807f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbBapmCoeffCalcTN.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CAC weights table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBBAPMCOEFFCALCTN_H_
+#define _GNBBAPMCOEFFCALCTN_H_
+
+typedef double DOUBLE;
+
+VOID
+GnbBapmCalculateCoeffsTN (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+INT32
+GnbFpLibDoubleToInt32 (
+  IN      DOUBLE  Value
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
new file mode 100644
index 0000000000..bf17ad1601
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
@@ -0,0 +1,175 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB CAC weights table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBCACWEIGHTSTABLETN_H_
+#define _GNBCACWEIGHTSTABLETN_H_
+
+UINT32 CacWeightsTN[] = {
+  0xD65,
+  0x289A,
+  0x289A,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x16F,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x16A5,
+  0x592,
+  0x0,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0x0,
+  0xE60,
+  0xEC9,
+  0xEC9,
+  0x41A,
+  0x41A,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0xF15,
+  0x79,
+  0x79,
+  0x79,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x3F2,
+  0x3F2,
+  0x0,
+  0x0,
+  0x123,
+  0x0,
+  0x0,
+  0x0,
+  0x123,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x195B,
+  0x629,
+  0x0,
+  0x0,
+  0x195B,
+  0x629,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x755,
+  0x0,
+  0x88B,
+  0x1206,
+  0x0,
+  0x88B,
+  0x1206,
+  0x0,
+  0x0
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
new file mode 100644
index 0000000000..b3b3101072
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
@@ -0,0 +1,888 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe early post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64732 $   @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "OptionGnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbTable.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbSmuFirmwareTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GfxLibTN.h"
+#include  "GnbCacWeightsTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "GnbHandleLib.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "GnbInitTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_TABLE ROMDATA      GnbEarlyInitTableTN [];
+extern GNB_TABLE ROMDATA      GnbEarlierInitTableBeforeSmuTN [];
+extern GNB_TABLE ROMDATA      GnbEarlierInitTableAfterSmuTN [];
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern BUILD_OPT_CFG          UserOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+GnbEarlierInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+);
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
+
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbAdjustSmuVidBeforeSmuTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_xE0001008_STRUCT  D0F0xBC_xE0001008;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+  D0F0xBC_xE0001008.Field.SClkVid3 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid2 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid1 -= 4;
+  D0F0xBC_xE0001008.Field.SClkVid0 -= 4;
+  GnbRegisterWriteTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidBeforeSmuTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Decrease all of the SMU VIDs by 4 (+25mV)
+
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbAdjustSmuVidAfterSmuTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F88C_STRUCT                   D0F0xBC_x1F88C;
+  D0F0xBC_x1F8DC_STRUCT                   D0F0xBC_x1F8DC;
+  D0F0xBC_x1F8E0_STRUCT                   D0F0xBC_x1F8E0;
+  D0F0xBC_x1F8E4_STRUCT                   D0F0xBC_x1F8E4;
+  D0F0xBC_x1F8E8_STRUCT                   D0F0xBC_x1F8E8;
+  D0F0xBC_x1F400_STRUCT                   D0F0xBC_x1F400;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Enter\n");
+
+  //Adjust SMU VIDs
+  GnbRegisterReadTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader);
+
+  D0F0xBC_x1F88C.Field.NbVid_3 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_2 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_1 -= 4;
+  D0F0xBC_x1F88C.Field.NbVid_0 -= 4;
+
+  D0F0xBC_x1F8DC.Field.SClkVid3 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid2 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid1 -= 4;
+  D0F0xBC_x1F8DC.Field.SClkVid0 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_2 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_1 -= 4;
+  D0F0xBC_x1F8E0.Field.BapmSclkVid_0 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmNbVid_1 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmNbVid_0 -= 4;
+  D0F0xBC_x1F8E4.Field.BapmSclkVid_3 -= 4;
+  D0F0xBC_x1F8E8.Field.BapmNbVid_3 -= 4;
+  D0F0xBC_x1F8E8.Field.BapmNbVid_2 -= 4;
+
+  GnbRegisterWriteTN (D0F0xBC_x1F88C_TYPE, D0F0xBC_x1F88C_ADDRESS, &D0F0xBC_x1F88C, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E0_TYPE, D0F0xBC_x1F8E0_ADDRESS, &D0F0xBC_x1F8E0, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E4_TYPE, D0F0xBC_x1F8E4_ADDRESS, &D0F0xBC_x1F8E4, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F8E8_TYPE, D0F0xBC_x1F8E8_ADDRESS, &D0F0xBC_x1F8E8, 0, StdHeader);
+
+  //D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV)
+  GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+  D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader);
+
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbAdjustSmuVidAfterSmuTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb SMU LHTC support
+ *
+ * Part of BAPM enablement.
+ * When BAPM is disabled in battery mode firmware will enable LHTC.
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmLhtcInitTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F638_STRUCT            D0F0xBC_x1F638;
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+  D0F0xBC_x1F86C_STRUCT            D0F0xBC_x1F86C;
+  D0F0xBC_x1F628_STRUCT            D0F0xBC_x1F628;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+
+  //1. Set HTC period to 10 in PM_TIMERS_2 register
+  //Still need to keep PM_CONFIG.Enable_HTC_Limit to 0
+  D0F0xBC_x1F428.Field.field_4  = 0;
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F638.Field.HtcPeriod = 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F638_TYPE, D0F0xBC_x1F638_ADDRESS, &D0F0xBC_x1F638, 0, StdHeader);
+
+  //2. Read BapmLhtcCap fuse
+  GnbRegisterReadTN (D0F0xBC_x1F86C_TYPE, D0F0xBC_x1F86C_ADDRESS, &D0F0xBC_x1F86C, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader);
+  if (D0F0xBC_x1F86C.Field.BapmLhtcCap == 0) {
+    D0F0xBC_x1F628.Field.HtcActivePstateLimit = 0;
+  } else {
+    D0F0xBC_x1F628.Field.HtcActivePstateLimit = D0F0xBC_xE0104188.Field.LhtcPstateLimit;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F628_TYPE, D0F0xBC_x1F628_ADDRESS, &D0F0xBC_x1F628, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmLhtcInitTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Measured temperature with BAPM
+ *
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbBapmMeasuredTempTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+  D0F0xBC_x1F844_STRUCT            D0F0xBC_x1F844;
+  D0F0xBC_x1F848_STRUCT            D0F0xBC_x1F848;
+  D0F0xBC_x1F84C_STRUCT            D0F0xBC_x1F84C;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+
+  //Measured temperature with BAPM
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F428.Field.line180  = 0;
+  if (D0F0xBC_xE0104188.Field.BapmMeasuredTemp == 1) {
+    D0F0xBC_x1F844.Value = 0x38B;
+    GnbRegisterWriteTN (D0F0xBC_x1F844_TYPE, D0F0xBC_x1F844_ADDRESS, &D0F0xBC_x1F844, 0, StdHeader);
+    D0F0xBC_x1F848.Value = 0x38D;
+    GnbRegisterWriteTN (D0F0xBC_x1F848_TYPE, D0F0xBC_x1F848_ADDRESS, &D0F0xBC_x1F848, 0, StdHeader);
+    D0F0xBC_x1F84C.Value = 0x389;
+    GnbRegisterWriteTN (D0F0xBC_x1F84C_TYPE, D0F0xBC_x1F84C_ADDRESS, &D0F0xBC_x1F84C, 0, StdHeader);
+
+    D0F0xBC_x1F428.Field.line180  = 1;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbBapmMeasuredTempTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb SMU LHTC Enable
+ *
+ * Part of BAPM enablement.
+ * When BAPM is disabled in battery mode firmware will enable LHTC.
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbLhtcEnableTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F428_STRUCT            D0F0xBC_x1F428;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Enter\n");
+
+  GnbRegisterReadTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+  D0F0xBC_x1F428.Field.field_4  = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F428_TYPE, D0F0xBC_x1F428_ADDRESS, &D0F0xBC_x1F428, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLhtcEnableTN Exit\n");
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb TN Update BAPMTI_TjOffset
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbTjOffsetUpdateTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F870_STRUCT             D0F0xBC_x1F870;
+
+  CPU_LOGICAL_ID                    LogicalId;
+  GNB_HANDLE                        *GnbHandle;
+  D0F0xBC_xE0104040_STRUCT          D0F0xBC_xE0104040;
+  D0F0xBC_x1F85C_STRUCT             D0F0xBC_x1F85C;
+  ex1075_STRUCT           ex1075 ;
+  UINT32                            TimerPeriod;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Enter\n");
+
+
+  TimerPeriod = D0F0xBC_x1F468_TimerPeriod_Value;
+  GnbRegisterReadTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0xe010413c , &ex1075, 0, StdHeader);
+  // Determine desired AgingRate:
+  // PM_FUSES4.TdpAgeRate * Fuse[BAPMTI_Ts] (encoded in us)
+  // Re-encode TdpAgeRate with 1ms BAPM interval
+  D0F0xBC_x1F85C.Field.TdpAgeRate = (D0F0xBC_x1F85C.Field.TdpAgeRate * ex1075.Field.ex1075_0 ) / (TimerPeriod / 100);
+  GnbRegisterWriteTN (D0F0xBC_x1F85C_TYPE, D0F0xBC_x1F85C_ADDRESS, &D0F0xBC_x1F85C, 0, StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader);
+  if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision);
+    return;
+  }
+  GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+  //9900h=FS1r2/FP2 Devastator
+  //9903h=FS1r2/FP2 Devastator Lite
+  //9990h=FS1r2/FP2 Scrapper
+  //9901h=FM2 Devastator
+  //9904h=FM2 Devastator Lite
+  //9991h=FM2 Scrapper
+  if ((D0F0xBC_xE0104040.Field.DeviceID == 0x9900) || (D0F0xBC_xE0104040.Field.DeviceID == 0x9903)) {
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x26;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x26;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x26;
+  } else if (D0F0xBC_xE0104040.Field.DeviceID == 0x9990) {
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0 = 0x2E;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1 = 0x2E;
+    D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2 = 0x2E;
+  } else {
+    IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Skip DID- %x\n", D0F0xBC_xE0104040.Field.DeviceID);
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbTjOffsetUpdateTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * GPU CAC enablement and weights programming
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+STATIC VOID
+GnbCacEnablement (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F464_STRUCT   D0F0xBC_x1F464;
+  ex1071_STRUCT    ex1071 ;
+  ex1072_STRUCT    ex1072 ;
+  PCI_ADDR                PciAddress;
+  UINT8                   Index;
+  ex1073_STRUCT    ex1073 ;
+  D18F5x160_STRUCT        D18F5x160;
+  DOUBLE                  UnbCac;
+  GMMx898_STRUCT          GMMx898;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader);
+  ex1072.Field.ex1072_2  = 0x29;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f920 , &ex1072, 0, StdHeader);
+
+  //UNB_CAC_VALUE.UNB_CAC = 2.3734E-04 * FNBPS0 (in MHz) * 2^GPU_CAC_AVRG_CNTL.WEIGHT_PREC
+  GnbRegisterReadTN (D18F5x160_TYPE, D18F5x160_ADDRESS, &D18F5x160.Value, 0, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "NBP0 10khz %x (%d)\n", GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid), GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid));
+  UnbCac = 0.00000204831536 * (1 << ex1072.Field.ex1072_0 ) * GfxLibGetNclkTN ((UINT8) D18F5x160.Field.NbFid, (UINT8) D18F5x160.Field.NbDid);
+  ex1073.Field.ex1073_0  = (UINT32) GnbFpLibDoubleToInt32 (UnbCac);
+  IDS_HDT_CONSOLE (GNB_TRACE, "UnbCac %x (%d)\n", ex1073.Field.ex1073_0 , ex1073.Field.ex1073_0 );
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f91c , &ex1073.Value, 0, StdHeader);
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader);
+  ex1071.Field.ex1071_0  = 0x1;
+  ex1071.Field.ex1071_3  = 0x4;
+  ex1071.Field.ex1071_4  = 0x25;
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f160 , &ex1071, 0, StdHeader);
+
+  GnbRegisterReadTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader);
+  GMMx898.Field.Threshold = 0x31;
+  GnbRegisterWriteTN (GMMx898_TYPE, GMMx898_ADDRESS, &GMMx898, 0, StdHeader);
+
+  // Set CAC/TDP interval
+  GnbRegisterReadTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader);
+  D0F0xBC_x1F464.Field.TdpCntl = 1;
+  GnbRegisterWriteTN (D0F0xBC_x1F464_TYPE, D0F0xBC_x1F464_ADDRESS, &D0F0xBC_x1F464, 0, StdHeader);
+
+  // Program GPU CAC weights
+
+  for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) {
+    GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0  + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader);
+  }
+
+  // Call BIOS service SMC_MSG_CONFIG_TDP_CNTL
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  GnbSmuServiceRequestV4 (
+    PciAddress,
+    SMC_MSG_CONFIG_TDP_CNTL,
+    0,
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode power of CPU out of Watt
+ *
+ *
+ *
+ * @param[in] Encode      PwrCpu encode
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                mWatt
+ */
+STATIC INT32
+CpuPowerDecode (
+  IN      UINT8                           Encode,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT32                   Power;
+  ex1002_STRUCT    ex1002 ;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader);
+
+  //TdpWatt = TdpWattEncode / 1024
+  //PwrCpu / TdpWatt = Encode
+  //PwrCpu = Encode * TdpWattEncode / 1024
+
+  Power = (INT32) ((Encode * ex1002.Field.ex1002_0  *1000) / 1024);
+
+  return Power;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Encode the offset of power of CPU
+ *
+ *
+ *
+ * @param[in] NewPower    New power of mWatt
+ * @param[in] OrgPower    Original power of mWatt
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                Encode
+ */
+STATIC UINT8
+CpuPowerOffsetEncode (
+  IN      INT32                           NewPower,
+  IN      INT32                           OrgPower,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT8                    PowerOffsetEncode;
+  INT32                   PowerOffset;
+  ex1002_STRUCT    ex1002 ;
+  BOOLEAN                 Postive;
+
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f850 , &ex1002, 0, StdHeader);
+  if (NewPower > OrgPower) {
+    PowerOffset = NewPower - OrgPower;
+    Postive = TRUE;
+  } else {
+    PowerOffset = OrgPower - NewPower;
+    Postive = FALSE;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu New Pwr %x (%d)\n", NewPower, NewPower);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu org Pwr %x (%d)\n", OrgPower, OrgPower);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Tdp2Watt %x, (%d)\n", ex1002.Field.ex1002_0 , ex1002.Field.ex1002_0 );
+  //Ceil of (mWatt *1024 / TdpWattEncode) / 1000 = Encode in watt
+  PowerOffset = (((PowerOffset * 1024) / ex1002.Field.ex1002_0 ) + 500) / 1000;
+
+  if (Postive) {
+    PowerOffsetEncode = (INT8) PowerOffset;
+  } else {
+    PowerOffsetEncode = 0 - (INT8) PowerOffset;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PowerOffsetEncode %x\n", PowerOffsetEncode);
+  return (UINT8) PowerOffsetEncode;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode power of GPU out of Watt
+ *
+ *
+ *
+ * @param[in] Encode      PwrGpu encode
+ * @param[in] StdHeader   Standard Configuration Header
+ * @retval                mWatt
+ */
+STATIC INT16
+GpuPowerDecode (
+  IN      UINT16                          Encode,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  INT16                   Power;
+
+  Power = (INT16) Encode;
+
+
+  return Power;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Decode Max Tj
+ *
+ *
+ *
+ * @param[in] Encode      Tj encode
+ * @retval                100 x Tj
+ */
+STATIC INT16
+TjMaxDecode (
+  IN      UINT8               Encode
+  )
+{
+  INT16    TjMax;
+
+  TjMax = (INT16) Encode;
+
+  return (TjMax * 100);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * for BAPMTI_TjOffset decoding
+ *
+ *
+ *
+ * @param[in] Encode      Tj encode
+ * @retval                100 x Tjoffset
+ */
+STATIC INT16
+TjOffsetDecode (
+  IN      UINT8               Encode
+  )
+{
+  UINT16      Number;
+  UINT8       Floating;
+  BOOLEAN     Postive;
+  UINT8       TjOffsetEncode;
+
+  TjOffsetEncode = Encode;
+  Postive = TRUE;
+
+  if (Encode == 0) {
+    return 0;
+  }
+
+  if ((TjOffsetEncode & 0x80) != 0) {
+    Postive = FALSE;
+    TjOffsetEncode = (UINT8) (~(Encode - 1));
+  }
+
+  Number = ((TjOffsetEncode >> 2) & 0x1F) * 100;
+
+  Floating = (TjOffsetEncode & 0x3);
+  if (Floating == 1) {
+    Number += 25;
+  } else if (Floating == 2) {
+    Number += 50;
+  } else if (Floating == 3) {
+    Number += 75;
+  } else {
+  }
+
+  if (Postive) {
+    return  (INT16) Number;
+  } else {
+    return (INT16) (0 - Number);
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Trinity SMU supports a software-writeable TjOffset (called swTjOffset) that can be programmed to
+ * account for underspec thermal solutions.
+ * There is a mechanism for customers to adjust TjOffset (via BAPM_PARAMETERS3.TjOffset)
+ * for under-performing thermal solutions.
+ * BIOS will adjust NomPow/MidPow/MaxPow based on this software-programmable TjOffset (called swTjOffset).
+ * SMU firmware will add this value to Fuse[TjOffset] for all TE's during BAPM calculations.
+ *
+ * Tj stands for junction temperature of the processor. However, here is a general description of
+ * our software-programmable TjOffset for BAPM (Birdirectional Application Power Management):
+ * "swTjOffset is an adjustable offset for BAPM thermal calculations to account for changes in
+ * junction temperature, TjOffset. For further details, see Thermal Guide."
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ */
+STATIC VOID
+GnbSoftwareTjOffsetTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  D0F0xBC_x1F860_STRUCT   D0F0xBC_x1F860;
+  D0F0xBC_x1F864_STRUCT   D0F0xBC_x1F864;
+  ex999_STRUCT    ex999 ;
+  D0F0xBC_x1F870_STRUCT   D0F0xBC_x1F870;
+  ex1000_STRUCT    ex1000 ;
+  ex1001_STRUCT    ex1001 ;
+
+  ex996_STRUCT   ex996;
+  ex997_STRUCT    ex997 ;
+  D0F0xBC_x1F6B4_STRUCT   D0F0xBC_x1F6B4;
+  ex998_STRUCT    ex998 ;
+  INT8                    SwTjOffset;
+  INT16                   Delta_T_org;
+  INT16                   Delta_T_new;
+  INT32                   Cpu_New_Pwr;
+  INT32                   Gpu_New_Pwr;
+
+  SwTjOffset = (INT8) UserOptions.CfgGnbSwTjOffset;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Enter\n");
+
+  IDS_OPTION_HOOK (IDS_GNB_PMM_SWTJOFFSET, &SwTjOffset, StdHeader);
+  if (SwTjOffset == 0) {
+    return;
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "User Input Tj Offset %x\n", SwTjOffset);
+  GnbRegisterReadTN (D0F0xBC_x1F860_TYPE, D0F0xBC_x1F860_ADDRESS, &D0F0xBC_x1F860, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F864_TYPE, D0F0xBC_x1F864_ADDRESS, &D0F0xBC_x1F864, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f868 , &ex999, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_x1F870_TYPE, D0F0xBC_x1F870_ADDRESS, &D0F0xBC_x1F870, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f898 , &ex1000, 0, StdHeader);
+  GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f8c0 , &ex1001, 0, StdHeader);
+
+  //Tjoffset_new = Tjoffset_org + SwTjOffset
+  //Delta_T_org = T_die - Tjoffset_org - 45
+
+  //Delta_T_new = T_die - Tjoffset_new - 45
+  //            = T_die - (Tjoffset_org + SwTjOffset) - 45
+  //            = T_die - Tjoffset_org - SwTjOffset - 45
+
+  //Pwr_new = Pwr_org * (Delta_T_new/Delta_T_org)
+  //        = Pwr_org * (T_org - TjOffset) / T_org
+
+  //Cpu0
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_0) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_0) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu0 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_2 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_3 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_3 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_2 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_2  = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_2 , StdHeader), StdHeader);
+
+  //Cpu1
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F860.Field.BAPMTI_TjMax_1) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_1) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Cpu1 Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_0 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_1, StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex996.Field.ex996_1 = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex999.Field.ex999_0 , StdHeader), StdHeader);
+  Cpu_New_Pwr = (CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_1  = CpuPowerOffsetEncode (Cpu_New_Pwr, CpuPowerDecode ((UINT8) ex1001.Field.ex1001_1 , StdHeader), StdHeader);
+
+  //GPU
+  Delta_T_org = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - 4500;
+  Delta_T_new = TjMaxDecode ((UINT8) D0F0xBC_x1F864.Field.BAPMTI_GpuTjMax) - TjOffsetDecode ((UINT8) D0F0xBC_x1F870.Field.BAPMTI_TjOffset_2) - (SwTjOffset * 100) - 4500;
+  IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T org %x (%d)\n", Delta_T_org, Delta_T_org);
+  IDS_HDT_CONSOLE (GNB_TRACE, "Gpu Delta T New %x (%d)\n", Delta_T_new, Delta_T_new);
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex997.Field.ex997_0  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_1 , StdHeader));
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex997.Field.ex997_1  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1000.Field.ex1000_0 , StdHeader));
+  Gpu_New_Pwr = (GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader) * Delta_T_new) / Delta_T_org;
+  ex998.Field.ex998_0  = (UINT16) (Gpu_New_Pwr - GpuPowerDecode ((UINT16) ex1001.Field.ex1001_0 , StdHeader));
+
+  //SwTjOffset
+  D0F0xBC_x1F6B4.Field.TjOffset = SwTjOffset;
+
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6ac , &ex996, 0, StdHeader);
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1f6b0 , &ex997, 0, StdHeader);
+  GnbRegisterWriteTN (D0F0xBC_x1F6B4_TYPE, D0F0xBC_x1F6B4_ADDRESS, &D0F0xBC_x1F6B4, 0, StdHeader);
+  GnbRegisterWriteTN (TYPE_D0F0xBC , 0x1F6B8 , &ex998, 0, StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbSoftwareTjOffsetTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init TDC
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC VOID
+GnbInitTdc (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AMD_EARLY_PARAMS        *EarlyParams;
+  D0F0xBC_x1F62C_STRUCT   D0F0xBC_x1F62C;
+  D0F0xBC_x1F840_STRUCT   D0F0xBC_x1F840;
+
+  EarlyParams = (AMD_EARLY_PARAMS *) StdHeader;
+  D0F0xBC_x1F62C.Field.Idd = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit / 10;
+  D0F0xBC_x1F62C.Field.Iddnb = EarlyParams->PlatformConfig.VrmProperties[NbVrm].CurrentLimit / 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F62C_TYPE, D0F0xBC_x1F62C_ADDRESS, &D0F0xBC_x1F62C, 0, StdHeader);
+
+  D0F0xBC_x1F840.Field.IddspikeOCP = EarlyParams->PlatformConfig.VrmProperties[CoreVrm].SviOcpLevel / 10;
+  D0F0xBC_x1F840.Field.IddNbspikeOCP = EarlyParams->PlatformConfig.VrmProperties[NbVrm].SviOcpLevel / 10;
+  GnbRegisterWriteTN (D0F0xBC_x1F840_TYPE, D0F0xBC_x1F840_ADDRESS, &D0F0xBC_x1F840, 0, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS                     Status;
+  GNB_HANDLE                       *GnbHandle;
+  UINT32                           Property;
+  D0F0xBC_xE0104188_STRUCT         D0F0xBC_xE0104188;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Enter\n");
+  Property = TABLE_PROPERTY_DEAFULT;
+
+  //Check fuse to support BAPM disabled.
+  GnbRegisterReadTN (D0F0xBC_xE0104188_TYPE, D0F0xBC_xE0104188_ADDRESS, &D0F0xBC_xE0104188, 0, StdHeader);
+  if (D0F0xBC_xE0104188.Field.BapmDisable == 0) {
+    Property |= GnbBuildOptions.CfgBapmSupport ? TABLE_PROPERTY_BAPM : 0;
+  }
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  // SMU LHTC support init
+  GnbBapmLhtcInitTN (StdHeader);
+
+  if ((Property & TABLE_PROPERTY_BAPM) == TABLE_PROPERTY_BAPM) {
+    GnbTjOffsetUpdateTN (StdHeader);
+    GnbSoftwareTjOffsetTN (StdHeader);
+    GnbBapmCalculateCoeffsTN (StdHeader);
+    GnbCacEnablement (StdHeader);
+    GnbBapmMeasuredTempTN (StdHeader);
+  } else {
+    //  If BAPM is disabled (either through fusing or CBS option), AGESA should enable LHTC algorithm.
+    //  Right now, LHTC is only enabled in the "DisableBAPM()" firmware routine, so unless Driver specifically calls this message,
+    //  LHTC will never be enabled if BAPM is disabled from the start.
+    GnbLhtcEnableTN (StdHeader);
+  }
+
+  GnbInitTdc (StdHeader);
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlyInitTableTN,
+             Property,
+             0,
+             StdHeader
+             );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEarlierInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  GNB_HANDLE                *GnbHandle;
+  D0F0xBC_xE0107060_STRUCT  D0F0xBC_xE0107060;
+  D0F0xBC_xE0001008_STRUCT  D0F0xBC_xE0001008;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Enter\n");
+
+  GnbAdjustSmuVidBeforeSmuTN (StdHeader);
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GnbRegisterReadTN (D0F0xBC_xE0107060_TYPE, D0F0xBC_xE0107060_ADDRESS, &D0F0xBC_xE0107060, 0, StdHeader);
+  GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, StdHeader);
+  GfxRequestVoltageTN ((UINT8) D0F0xBC_xE0001008.Field.SClkVid1, StdHeader);
+  GfxRequestSclkTN ((UINT8) D0F0xBC_xE0107060.Field.SClkDpmDid1, StdHeader);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlierInitTableBeforeSmuTN,
+             0,
+             0,
+             StdHeader
+             );
+  GnbSmuFirmwareLoadV4 (GnbHandle->Address, (FIRMWARE_HEADER_V4*) &FirmwareTN[0], StdHeader);
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEarlierInitTableAfterSmuTN,
+             0,
+             0,
+             StdHeader
+             );
+
+  GnbAdjustSmuVidAfterSmuTN (StdHeader);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
new file mode 100644
index 0000000000..f98884dcf9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEnvInitTN.c
@@ -0,0 +1,197 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbFuseTableTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "heapManager.h"
+#include  "GnbFuseTable.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern GNB_TABLE ROMDATA      GnbEnvInitTableTN [];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS                   Status;
+  AMD_ENV_PARAMS                 *EnvParamsPtr;
+  UINT32                         Property;
+  GNB_HANDLE                     *GnbHandle;
+  D18F5x170_STRUCT               D18F5x170;
+  D0F0xBC_x1F8DC_STRUCT          D0F0xBC_x1F8DC;
+  PP_FUSE_ARRAY                  *PpFuseArray;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n");
+  Property = TABLE_PROPERTY_DEAFULT;
+  EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader;
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+  GnbLoadFuseTableTN (StdHeader);
+  Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader);
+  GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader);
+  GnbClumpUnitIdV4 (GnbHandle, StdHeader);
+  GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader);
+  Property |= GnbBuildOptions.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0;
+  Property |= GnbBuildOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0;
+  if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) {
+    Property |= TABLE_PROPERTY_IOMMU_DISABLED;
+  }
+
+  if (GnbBuildOptions.CfgNbdpmEnable) {
+    GnbRegisterReadTN (
+      TYPE_D18F5,
+      D18F5x170_ADDRESS,
+      &D18F5x170.Value,
+      0,
+      StdHeader
+    );
+    // Check if NbPstate enbale
+    if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) {
+      Property |= TABLE_PROPERTY_NBDPM;
+      PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+      if (PpFuseArray != NULL) {
+        // NBDPM is requesting SclkVid0 from the register.
+        // Write them back if SclkVid has been changed in PpFuseArray.
+        GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader);
+        if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) ||
+            (D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) {
+          D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0];
+          D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1];
+          D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2];
+          D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3];
+          GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        }
+      }
+    }
+  }
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbEnvInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
new file mode 100644
index 0000000000..c2bb8823ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
@@ -0,0 +1,1000 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Gnb fuse table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbFuseTable.h"
+#include  "GnbFuseTableTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbFuseTableDebugDumpTN (
+  IN       PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+
+
+PP_FUSE_ARRAY  ex907  = {
+  0,                              // PP table revision
+  {1,    0,  0,  0,  0, 0},       // Valid DPM states
+  {0x40, 0,  0,  0,  0, 0},       // Sclk DPM DID
+  {0,    0,  0,  0,  0, 0},       // Sclk DPM VID
+  {0,    0,  0,  0,  0},          // Sclk DPM Cac
+  {1,    0,  0,  0,  0,  0},      // State policy flags
+  {2,    0,  0,  0,  0,  0},      // State policy label
+  {0x40, 0,  0,  0},              // VCLK DID
+  {0x40, 0,  0,  0},              // DCLK DID
+  8,                              // Thermal SCLK
+  {0,    0,  0,  0,  0,  0},      // Vclk/Dclk selector
+  {0,    0,  0,  0},              // Valid Lclk DPM states
+  {0x40, 0x40, 0x40, 0},          // Lclk DPM DID
+  {0x40, 0x40, 0x40, 0},          // Lclk DPM VID
+  {0,    0,  0,  0},              // Displclk DID
+  3,                              // Pcie Gen 2 VID
+  0x10,                           // Main PLL id for 3200 VCO
+  0,                              // WRCK SMU clock Divisor
+  {0x24, 0x24, 0x24, 0x24},       // SCLK VID
+  0,                              // GPU boost cap
+  {0, 0, 0, 0, 0, 0},             // Sclk DPM TDP limit
+  0,                              // TDP limit PG
+  0,                              // Boost margin
+  0,                              // Throttle margin
+  TRUE,                           // Support VCE in PP table
+  {0x3, 0xC, 0x30, 0xC0},         // VCE Flags
+  {0, 1, 0, 1},                   // MCLK for VCE
+  {0, 0, 0, 0},                   // SCLK selector for VCE
+  {0x40, 0x40, 0x40, 0x40}        // Eclk DID
+};
+
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104158_TABLE [] = {
+  {
+    D0F0xBC_xE0104158_EClkDid0_OFFSET,
+    D0F0xBC_xE0104158_EClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[0])
+  },
+  {
+    D0F0xBC_xE0104158_EClkDid1_OFFSET,
+    D0F0xBC_xE0104158_EClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[1])
+  },
+  {
+    D0F0xBC_xE0104158_EClkDid2_OFFSET,
+    D0F0xBC_xE0104158_EClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010415B_TABLE [] = {
+  {
+    D0F0xBC_xE010415B_EClkDid3_OFFSET,
+    D0F0xBC_xE010415B_EClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, EclkDid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104184_TABLE [] = {
+  {
+    D0F0xBC_xE0104184_VCEFlag0_OFFSET,
+    D0F0xBC_xE0104184_VCEFlag0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[0])
+  },
+  {
+    D0F0xBC_xE0104184_VCEFlag1_OFFSET,
+    D0F0xBC_xE0104184_VCEFlag1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104187_TABLE [] = {
+  {
+    D0F0xBC_xE0104187_VCEFlag2_OFFSET,
+    D0F0xBC_xE0104187_VCEFlag2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0104188_TABLE [] = {
+  {
+    D0F0xBC_xE0104188_VCEFlag3_OFFSET,
+    D0F0xBC_xE0104188_VCEFlag3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceFlags[3])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel0_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[0])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel1_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[1])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel2_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[2])
+  },
+  {
+    D0F0xBC_xE0104188_ReqSclkSel3_OFFSET,
+    D0F0xBC_xE0104188_ReqSclkSel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceReqSclkSel[3])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 0,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[0])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 1,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[1])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 2,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[2])
+  },
+  {
+    D0F0xBC_xE0104188_VCEMclk_OFFSET + 3,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VceMclk[3])
+  },
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106020_TABLE [] = {
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel0_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0])
+  },
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel1_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1])
+  },
+  {
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel2_OFFSET,
+    D0F0xBC_xE0106020_PowerplayDClkVClkSel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106023_TABLE [] = {
+  {
+    D0F0xBC_xE0106023_PowerplayDClkVClkSel3_OFFSET,
+    D0F0xBC_xE0106023_PowerplayDClkVClkSel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0106024_TABLE [] = {
+  {
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel4_OFFSET,
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4])
+  },
+  {
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel5_OFFSET,
+    D0F0xBC_xE0106024_PowerplayDClkVClkSel5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705C_TABLE [] = {
+  {
+    D0F0xBC_xE010705C_PowerplayTableRev_OFFSET,
+    D0F0xBC_xE010705C_PowerplayTableRev_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PPlayTableRev)
+  },
+  {
+    D0F0xBC_xE010705C_SClkThermDid_OFFSET,
+    D0F0xBC_xE010705C_SClkThermDid_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkThermDid)
+  },
+  {
+    D0F0xBC_xE010705C_PcieGen2Vid_OFFSET,
+    D0F0xBC_xE010705C_PcieGen2Vid_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PcieGen2Vid)
+  }
+};
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010705F_TABLE [] = {
+  {
+    D0F0xBC_xE010705F_SClkDpmVid0_OFFSET,
+    D0F0xBC_xE010705F_SClkDpmVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0])
+  },
+  {
+    D0F0xBC_xE010705F_SClkDpmVid0_OFFSET,
+    D0F0xBC_xE010705F_SClkDpmVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107060_TABLE [] = {
+  {
+    D0F0xBC_xE0107060_SClkDpmVid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmVid[2])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid3_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmVid4_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmVid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid0_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid1_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1])
+  },
+  {
+    D0F0xBC_xE0107060_SClkDpmDid2_OFFSET,
+    D0F0xBC_xE0107060_SClkDpmDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107063_TABLE [] = {
+  {
+    D0F0xBC_xE0107063_SClkDpmDid3_OFFSET,
+    D0F0xBC_xE0107063_SClkDpmDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107064_TABLE [] = {
+  {
+    D0F0xBC_xE0107064_SClkDpmDid4_OFFSET,
+    D0F0xBC_xE0107064_SClkDpmDid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107067_TABLE [] = {
+  {
+    D0F0xBC_xE0107067_DispClkDid0_OFFSET,
+    D0F0xBC_xE0107067_DispClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107068_TABLE [] = {
+  {
+    D0F0xBC_xE0107068_DispClkDid1_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[1])
+  },
+  {
+    D0F0xBC_xE0107068_DispClkDid2_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107068_DispClkDid3_OFFSET,
+    D0F0xBC_xE0107068_DispClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DisplclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107068_LClkDpmDid0_OFFSET,
+    D0F0xBC_xE0107068_LClkDpmDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706B_TABLE [] = {
+  {
+    D0F0xBC_xE010706B_LClkDpmDid1_OFFSET,
+    D0F0xBC_xE010706B_LClkDpmDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706C_TABLE [] = {
+  {
+    D0F0xBC_xE010706C_LClkDpmDid2_OFFSET,
+    D0F0xBC_xE010706C_LClkDpmDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmDid3_OFFSET,
+    D0F0xBC_xE010706C_LClkDpmDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 0,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 1,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 2,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2])
+  },
+  {
+    D0F0xBC_xE010706C_LClkDpmValid_OFFSET + 3,
+    1,
+    (UINT16) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3])
+  },
+  {
+    D0F0xBC_xE010706C_DClkDid0_OFFSET,
+    D0F0xBC_xE010706C_DClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010706F_TABLE [] = {
+  {
+    D0F0xBC_xE010706F_DClkDid1_OFFSET,
+    D0F0xBC_xE010706F_DClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[1])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107070_TABLE [] = {
+  {
+    D0F0xBC_xE0107070_DClkDid2_OFFSET,
+    D0F0xBC_xE0107070_DClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107070_DClkDid3_OFFSET,
+    D0F0xBC_xE0107070_DClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, DclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107070_VClkDid0_OFFSET,
+    D0F0xBC_xE0107070_VClkDid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107073_TABLE [] = {
+  {
+    D0F0xBC_xE0107073_VClkDid1_OFFSET,
+    D0F0xBC_xE0107073_VClkDid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[1])
+  },
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107074_TABLE [] = {
+  {
+    D0F0xBC_xE0107074_VClkDid2_OFFSET,
+    D0F0xBC_xE0107074_VClkDid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[2])
+  },
+  {
+    D0F0xBC_xE0107074_VClkDid3_OFFSET,
+    D0F0xBC_xE0107074_VClkDid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, VclkDid[3])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid0_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid1_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1])
+  },
+  {
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid2_OFFSET,
+    D0F0xBC_xE0107074_PowerplaySclkDpmValid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107077_TABLE [] = {
+  {
+    D0F0xBC_xE0107077_PowerplaySclkDpmValid3_OFFSET,
+    D0F0xBC_xE0107077_PowerplaySclkDpmValid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0107078_TABLE [] = {
+  {
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid4_OFFSET,
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid5_OFFSET,
+    D0F0xBC_xE0107078_PowerplaySclkDpmValid5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel0_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[0])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel1_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[1])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel2_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[2])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel3_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[3])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel4_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[4])
+  },
+  {
+    D0F0xBC_xE0107078_PowerplayPolicyLabel5_OFFSET,
+    D0F0xBC_xE0107078_PowerplayPolicyLabel5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyLabel[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707B_TABLE [] = {
+  {
+    D0F0xBC_xE010707B_PowerplayStateFlag0_OFFSET,
+    D0F0xBC_xE010707B_PowerplayStateFlag0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[0])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707C_TABLE [] = {
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag1_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[1])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag2_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[2])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag3_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[3])
+  },
+  {
+    D0F0xBC_xE010707C_PowerplayStateFlag4_OFFSET,
+    D0F0xBC_xE010707C_PowerplayStateFlag4_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[4])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE010707F_TABLE [] = {
+  {
+    D0F0xBC_xE010707F_PowerplayStateFlag5_OFFSET,
+    D0F0xBC_xE010707F_PowerplayStateFlag5_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, PolicyFlags[5])
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xFF000000_TABLE [] = {
+  {
+    D0F0xBC_xFF000000_MainPllOpFreqIdStartup_OFFSET,
+    D0F0xBC_xFF000000_MainPllOpFreqIdStartup_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, MainPllId)
+  }
+};
+
+FUSE_REGISTER_ENTRY_TN D0F0xBC_xE0001008_TABLE [] = {
+  {
+    D0F0xBC_xE0001008_SClkVid0_OFFSET,
+    D0F0xBC_xE0001008_SClkVid0_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[0])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid1_OFFSET,
+    D0F0xBC_xE0001008_SClkVid1_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[1])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid2_OFFSET,
+    D0F0xBC_xE0001008_SClkVid2_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[2])
+  },
+  {
+    D0F0xBC_xE0001008_SClkVid3_OFFSET,
+    D0F0xBC_xE0001008_SClkVid3_WIDTH,
+    (UINT16) offsetof (PP_FUSE_ARRAY, SclkVid[3])
+  }
+};
+
+
+FUSE_TABLE_ENTRY_TN  FuseRegisterTableTN [] = {
+  {
+    D0F0xBC_xE0104158_TYPE,
+    D0F0xBC_xE0104158_ADDRESS,
+    sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104158_TABLE
+  },
+  {
+    D0F0xBC_xE010415B_TYPE,
+    D0F0xBC_xE010415B_ADDRESS,
+    sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010415B_TABLE
+  },
+  {
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104184_TABLE
+  },
+  {
+    D0F0xBC_xE0104187_TYPE,
+    D0F0xBC_xE0104187_ADDRESS,
+    sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104187_TABLE
+  },
+  {
+    D0F0xBC_xE0104188_TYPE,
+    D0F0xBC_xE0104188_ADDRESS,
+    sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0104188_TABLE
+  },
+  {
+    D0F0xBC_xE0106020_TYPE,
+    D0F0xBC_xE0106020_ADDRESS,
+    sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106020_TABLE
+  },
+  {
+    D0F0xBC_xE0106023_TYPE,
+    D0F0xBC_xE0106023_ADDRESS,
+    sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106023_TABLE
+  },
+  {
+    D0F0xBC_xE0106024_TYPE,
+    D0F0xBC_xE0106024_ADDRESS,
+    sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0106024_TABLE
+  },
+  {
+    D0F0xBC_xE010705C_TYPE,
+    D0F0xBC_xE010705C_ADDRESS,
+    sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010705C_TABLE
+  },
+  {
+    D0F0xBC_xE010705F_TYPE,
+    D0F0xBC_xE010705F_ADDRESS,
+    sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010705F_TABLE
+  },
+  {
+    D0F0xBC_xE0107060_TYPE,
+    D0F0xBC_xE0107060_ADDRESS,
+    sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107060_TABLE
+  },
+  {
+    D0F0xBC_xE0107063_TYPE,
+    D0F0xBC_xE0107063_ADDRESS,
+    sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107063_TABLE
+  },
+  {
+    D0F0xBC_xE0107064_TYPE,
+    D0F0xBC_xE0107064_ADDRESS,
+    sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107064_TABLE
+  },
+  {
+    D0F0xBC_xE0107067_TYPE,
+    D0F0xBC_xE0107067_ADDRESS,
+    sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107067_TABLE
+  },
+  {
+    D0F0xBC_xE0107068_TYPE,
+    D0F0xBC_xE0107068_ADDRESS,
+    sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107068_TABLE
+  },
+  {
+    D0F0xBC_xE010706B_TYPE,
+    D0F0xBC_xE010706B_ADDRESS,
+    sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706B_TABLE
+  },
+  {
+    D0F0xBC_xE010706C_TYPE,
+    D0F0xBC_xE010706C_ADDRESS,
+    sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706C_TABLE
+  },
+  {
+    D0F0xBC_xE010706F_TYPE,
+    D0F0xBC_xE010706F_ADDRESS,
+    sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010706F_TABLE
+  },
+  {
+    D0F0xBC_xE0107070_TYPE,
+    D0F0xBC_xE0107070_ADDRESS,
+    sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107070_TABLE
+  },
+  {
+    D0F0xBC_xE0107073_TYPE,
+    D0F0xBC_xE0107073_ADDRESS,
+    sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107073_TABLE
+  },
+  {
+    D0F0xBC_xE0107074_TYPE,
+    D0F0xBC_xE0107074_ADDRESS,
+    sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107074_TABLE
+  },
+  {
+    D0F0xBC_xE0107077_TYPE,
+    D0F0xBC_xE0107077_ADDRESS,
+    sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107077_TABLE
+  },
+  {
+    D0F0xBC_xE0107078_TYPE,
+    D0F0xBC_xE0107078_ADDRESS,
+    sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0107078_TABLE
+  },
+  {
+    D0F0xBC_xE010707B_TYPE,
+    D0F0xBC_xE010707B_ADDRESS,
+    sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707B_TABLE
+  },
+  {
+    D0F0xBC_xE010707C_TYPE,
+    D0F0xBC_xE010707C_ADDRESS,
+    sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707C_TABLE
+  },
+  {
+    D0F0xBC_xE010707F_TYPE,
+    D0F0xBC_xE010707F_ADDRESS,
+    sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE010707F_TABLE
+  },
+  {
+    D0F0xBC_xFF000000_TYPE,
+    D0F0xBC_xFF000000_ADDRESS,
+    sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xFF000000_TABLE
+  },
+  {
+    D0F0xBC_xE0001008_TYPE,
+    D0F0xBC_xE0001008_ADDRESS,
+    sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    D0F0xBC_xE0001008_TABLE
+  }
+};
+
+FUSE_TABLE_TN  FuseTableTN = {
+  sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN),
+  FuseRegisterTableTN
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Load Fuse Table TN
+ *
+ *
+ * @param[out] PpFuseArray      Pointer to save fuse table
+ * @param[in]  StdHeader        Pointer to Standard configuration
+ * @retval     AGESA_STATUS
+ */
+
+STATIC VOID
+NbFuseLoadFuseTableTN (
+     OUT   PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  FUSE_TABLE_TN             *FuseTable;
+  UINTN                     RegisterIndex;
+  FuseTable = &FuseTableTN;
+  for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) {
+    UINTN   FieldIndex;
+    UINTN   FuseRegisterTableLength;
+    UINT32  FuseValue;
+    FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength;
+
+    GnbRegisterReadTN (
+      FuseTable->FuseTable[RegisterIndex].RegisterSpaceType,
+      FuseTable->FuseTable[RegisterIndex].Register,
+      &FuseValue,
+      0,
+      StdHeader
+    );
+    for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength;  FieldIndex++) {
+      FUSE_REGISTER_ENTRY_TN   RegisterEntry;
+      RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex];
+      *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) &
+                                                            ((1 << RegisterEntry.FieldWidth) - 1));
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gnb load fuse table
+ *
+ *
+ *
+ * @param[in] StdHeader        Pointer to Standard configuration
+ * @retval    AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbLoadFuseTableTN (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PP_FUSE_ARRAY          *PpFuseArray;
+  AGESA_STATUS           Status;
+  D18F3xA0_STRUCT        D18F3xA0;
+
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Enter\n");
+
+  PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader);
+  ASSERT (PpFuseArray != NULL);
+  if (PpFuseArray != NULL) {
+    //Support for real fuste table
+    GnbRegisterReadTN (D18F3xA0_TYPE, D18F3xA0_ADDRESS, &D18F3xA0.Value, 0, StdHeader);
+    if ((D18F3xA0.Field.CofVidProg) && (GnbBuildOptions.GnbLoadRealFuseTable)) {
+      NbFuseLoadFuseTableTN (PpFuseArray, StdHeader);
+      PpFuseArray->VceSateTableSupport = TRUE;
+      IDS_HDT_CONSOLE (NB_MISC, "  Processor Fused\n");
+    } else {
+      LibAmdMemCopy (PpFuseArray, &ex907 , sizeof (PP_FUSE_ARRAY), StdHeader);
+      IDS_HDT_CONSOLE (NB_MISC, "  Processor Unfuse\n");
+    }
+  } else {
+    Status = AGESA_ERROR;
+  }
+  IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader);
+  GnbFuseTableDebugDumpTN (PpFuseArray, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLoadFuseTableTN Exit [0x%x]\n", Status);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Debug dump fuse table
+ *
+ *
+ * @param[out] PpFuseArray      Pointer to save fuse table
+ * @param[in]  StdHeader        Pointer to Standard configuration
+ */
+
+VOID
+GnbFuseTableDebugDumpTN (
+  IN       PP_FUSE_ARRAY       *PpFuseArray,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINTN   Index;
+
+  IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n");
+  for (Index = 0; Index < 4; Index++) {
+    if (PpFuseArray->LclkDpmValid[Index]  != 0) {
+      IDS_HDT_CONSOLE (
+        NB_MISC,
+        "  LCLK DID[%d] - 0x%02x (%dMHz)\n",
+        Index,
+        PpFuseArray->LclkDpmDid[Index],
+        (PpFuseArray->LclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->LclkDpmDid[Index], StdHeader) / 100) : 0
+        );
+      IDS_HDT_CONSOLE (NB_MISC, "  LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]);
+    }
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->VclkDid[Index],
+      (PpFuseArray->VclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->VclkDid[Index], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  DCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->DclkDid[Index],
+      (PpFuseArray->DclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DclkDid[Index], StdHeader) / 100) : 0
+    );
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  DISPCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->DisplclkDid[Index],
+      (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->DisplclkDid[Index], StdHeader) / 100) : 0
+      );
+  }
+  for (Index = 0; Index < 4; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  ECLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->EclkDid[Index],
+      (PpFuseArray->EclkDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->EclkDid[Index], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCE SCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]],
+      (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[PpFuseArray->VceReqSclkSel[Index]], StdHeader) / 100) : 0
+      );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  VCE Flags[ % d] - 0x % 02x\n",
+      Index,
+      PpFuseArray->VceFlags[Index]
+      );
+  }
+  for (Index = 0; Index < 6; Index++) {
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  SCLK DID[%d] - 0x%02x (%dMHz)\n",
+      Index,
+      PpFuseArray->SclkDpmDid[Index],
+      (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxFmCalculateClock (PpFuseArray->SclkDpmDid[Index], StdHeader) / 100) : 0
+    );
+    IDS_HDT_CONSOLE (
+      NB_MISC,
+      "  SCLK TDP[%d] - 0x%x \n",
+      Index,
+      PpFuseArray->SclkDpmTdpLimit[Index]
+    );
+    IDS_HDT_CONSOLE (NB_MISC, "  SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]);
+  }
+  for (Index = 0; Index < 6; Index++) {
+    IDS_HDT_CONSOLE (NB_MISC, "  State #%d\n", Index);
+  }
+  IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n");
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h
new file mode 100644
index 0000000000..5d6177f1e0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Fuse table initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBFUSETABLETN_H_
+#define _GNBFUSETABLETN_H_
+
+#pragma pack (push, 1)
+
+/// Fuse field entry
+typedef struct {
+  UINT8                    FieldOffset;              ///< Field offset in fuse register
+  UINT8                    FieldWidth;               ///< Width of field
+  UINT16                   FuseOffset;               ///< destination offset in translation table
+} FUSE_REGISTER_ENTRY_TN;
+
+/// Fuse register entry
+typedef struct {
+  UINT8                    RegisterSpaceType;        ///< Register type
+  UINT32                   Register;                 ///< FCR register address
+  UINT8                    FuseRegisterTableLength;  ///< Length of field table for this register
+  FUSE_REGISTER_ENTRY_TN   *FuseRegisterTable;       ///< Pointer to field table
+} FUSE_TABLE_ENTRY_TN;
+
+/// Fuse translation table
+typedef struct {
+  UINT8                    FuseTableLength;          ///< Length of translation table
+  FUSE_TABLE_ENTRY_TN      *FuseTable;               ///< Pointer to register table
+} FUSE_TABLE_TN;
+
+#pragma pack (pop)
+
+AGESA_STATUS
+GnbLoadFuseTableTN (
+  IN      AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h
new file mode 100644
index 0000000000..76196f1c08
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTN.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Various TN definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBINITTN_H_
+#define _GNBINITTN_H_
+
+#define D0F0xBC_x1F468_TimerPeriod_Value  100000
+#define D0F0xBC_x1F46C_BapmPeriod_Value   1
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h
new file mode 100644
index 0000000000..e6ac431378
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h
@@ -0,0 +1,200 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Tn service installation file
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNB_INIT_TN_INSTALL_H_
+#define _GNB_INIT_TN_INSTALL_H_
+
+//-----------------------------------------------------------------------
+// Specify definition used by module services
+//-----------------------------------------------------------------------
+
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbFamServices.h"
+
+//-----------------------------------------------------------------------
+// Export services
+//-----------------------------------------------------------------------
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE)
+  extern F_PCIEFMGETCOMPLEXDATALENGTH             PcieGetComplexDataLengthTN;
+  extern F_PCIEFMBUILDCOMPLEXCONFIGURATION        PcieBuildComplexConfigurationTN;
+  extern F_PCIEFMCONFIGUREENGINESLANEALLOCATION   PcieConfigureEnginesLaneAllocationTN;
+  extern F_PCIEFMCHECKPORTPCIDEVICEMAPPING        PcieCheckPortPciDeviceMappingTN;
+  extern F_PCIEFMMAPPORTPCIADDRESS                PcieMapPortPciAddressTN;
+  extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED      PcieCheckPortPcieLaneCanBeMuxedTN;
+  extern F_PCIEFMGETSBCONFIGINFO                  PcieGetSbConfigInfoTN;
+  PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = {
+    PcieGetComplexDataLengthTN,
+    PcieBuildComplexConfigurationTN,
+    PcieConfigureEnginesLaneAllocationTN,
+    PcieCheckPortPciDeviceMappingTN,
+    PcieMapPortPciAddressTN,
+    PcieCheckPortPcieLaneCanBeMuxedTN,
+    PcieGetSbConfigInfoTN
+  };
+
+  GNB_SERVICE GnbPcieCongigServicesTN = {
+    GnbPcieFamConfigService,
+    AMD_FAMILY_TN,
+    &GnbPcieConfigProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbPcieCongigServicesTN
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  extern F_PCIEFMGETCORECONFIGURATIONVALUE        PcieGetCoreConfigurationValueTN;
+  extern F_PCIEFMGETLINKSPEEDCAP                  PcieGetLinkSpeedCapTN;
+  extern F_PCIEFMGETNATIVEPHYLANEBITMAP           PcieGetNativePhyLaneBitmapTN;
+  extern F_PCIEFMSETLINKSPEEDCAP                  PcieSetLinkSpeedCapV4;
+
+  PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = {
+    PcieGetCoreConfigurationValueTN,
+    PcieGetLinkSpeedCapTN,
+    PcieGetNativePhyLaneBitmapTN,
+    PcieSetLinkSpeedCapV4
+  };
+
+  GNB_SERVICE GnbPcieInitServicesTN = {
+    GnbPcieFamInitService,
+    AMD_FAMILY_TN,
+    &GnbPcieInitProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbPcieInitServicesTN
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  #if IDSOPT_IDS_ENABLED == TRUE
+    #if IDSOPT_TRACING_ENABLED == TRUE
+      extern F_PCIEFMDEBUGGETHOSTREGADDRESSSPACESTRING  PcieDebugGetHostRegAddressSpaceStringTN;
+      extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING          PcieDebugGetWrapperNameStringTN;
+      extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING    PcieDebugGetCoreConfigurationStringTN;
+
+      PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = {
+        PcieDebugGetHostRegAddressSpaceStringTN,
+        PcieDebugGetWrapperNameStringTN,
+        PcieDebugGetCoreConfigurationStringTN
+      };
+
+      GNB_SERVICE GnbPcieDebugServicesTN = {
+        GnbPcieFamDebugService,
+        AMD_FAMILY_TN,
+        &GnbPcieDebugProtocolTN,
+        SERVICES_POINTER
+      };
+      #undef  SERVICES_POINTER
+      #define SERVICES_POINTER  &GnbPcieDebugServicesTN
+    #endif
+  #endif
+#endif
+
+#if  (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  extern F_GNB_REGISTER_ACCESS  GnbRegisterReadServiceTN;
+  extern F_GNB_REGISTER_ACCESS  GnbRegisterWriteServiceTN;
+
+  GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = {
+    GnbRegisterReadServiceTN,
+    GnbRegisterWriteServiceTN
+  };
+
+  GNB_SERVICE GnbRegisterAccessServicesTN = {
+    GnbRegisterAccessService,
+    AMD_FAMILY_TN,
+    &GnbRegiterAccessProtocol,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbRegisterAccessServicesTN
+
+  extern F_GNBFMCREATEIVRSENTRY    GnbCreateIvrsEntryTN;
+  extern F_GNBFMCHECKIOMMUPRESENT  GnbCheckIommuPresentTN;
+
+  GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = {
+    GnbCheckIommuPresentTN,
+    GnbCreateIvrsEntryTN
+  };
+
+  GNB_SERVICE GnbIommuConfigServicesTN = {
+    GnbIommuService,
+    AMD_FAMILY_TN,
+    &GnbIommuConfigProtocolTN,
+    SERVICES_POINTER
+  };
+  #undef  SERVICES_POINTER
+  #define SERVICES_POINTER  &GnbIommuConfigServicesTN
+
+#endif
+#endif  // _GNB_INIT_TN_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
new file mode 100644
index 0000000000..8f176d77b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbIommuIvrsTN.c
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "cpuLateInit.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbIommu.h"
+#include  "GnbIvrsLib.h"
+#include  "GnbSbIommuLib.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbIommuIvrs.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbCreateIvhdHeaderTN (
+  IN       IVRS_BLOCK_TYPE            Type,
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbCreateIvhdTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+VOID
+GnbCreateIvhdrTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+AGESA_STATUS
+GnbCreateIvrsEntryTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+BOOLEAN
+GnbCheckIommuPresentTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU unit present and enabled
+ *
+ *
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+BOOLEAN
+GnbCheckIommuPresentTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  if (GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 0, 2, 0), StdHeader)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  GnbHandle       Gnb handle
+ * @param[in]  Type            Entry type
+ * @param[in]  Ivrs            IVRS table pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+
+AGESA_STATUS
+GnbCreateIvrsEntryTN (
+  IN       GNB_HANDLE                 *GnbHandle,
+  IN       IVRS_BLOCK_TYPE            Type,
+  IN       VOID                       *Ivrs,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  IVRS_IVHD_ENTRY                   *Ivhd;
+  UINT8                             IommuCapabilityOffset;
+  UINT32                            Value;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Entry\n");
+  if (Type == IvrsIvhdBlock || Type == IvrsIvhdrBlock) {
+    // Update IVINFO
+    IommuCapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
+    GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, IommuCapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
+    ((IOMMU_IVRS_HEADER *) Ivrs)->IvInfo = Value & (IVINFO_HTATSRESV_MASK | IVINFO_VASIZE_MASK | IVINFO_GASIZE_MASK | IVINFO_PASIZE_MASK);
+
+    // Address of IVHD entry
+    Ivhd = (IVRS_IVHD_ENTRY*) ((UINT8 *)Ivrs + ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength);
+    GnbCreateIvhdHeaderTN (Type, Ivhd, StdHeader);
+    if (Type == IvrsIvhdBlock) {
+      GnbCreateIvhdTN (Ivhd, StdHeader);
+    } else {
+      GnbCreateIvhdrTN (Ivhd, StdHeader);
+    }
+    ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength = ((IOMMU_IVRS_HEADER *) Ivrs)->TableLength + Ivhd->Length;
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbFmCreateIvrsEntry Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVRS entry
+ *
+ *
+ * @param[in]  Type            Block type
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdHeaderTN (
+  IN       IVRS_BLOCK_TYPE            Type,
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  UINT32    Value;
+  Ivhd->Type = (UINT8) Type;
+  Ivhd->Flags = IVHD_FLAG_COHERENT | IVHD_FLAG_IOTLBSUP | IVHD_FLAG_ISOC | IVHD_FLAG_RESPASSPW | IVHD_FLAG_PASSPW | IVHD_FLAG_PPRSUB | IVHD_FLAG_PREFSUP;
+  Ivhd->Length = sizeof (IVRS_IVHD_ENTRY);
+  Ivhd->DeviceId = 0x2;
+  Ivhd->CapabilityOffset = GnbLibFindPciCapability (MAKE_SBDFO (0, 0, 0, 2, 0), IOMMU_CAP_ID, StdHeader);
+  Ivhd->PciSegment = 0;
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x4), AccessWidth32, &Ivhd->BaseAddress, StdHeader);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x8), AccessWidth32, (UINT8 *) &Ivhd->BaseAddress + 4, StdHeader);
+  Ivhd->BaseAddress = Ivhd->BaseAddress & 0xfffffffffffffffe;
+  ASSERT (Ivhd->BaseAddress != 0x0);
+  GnbLibPciRead (MAKE_SBDFO (0, 0, 0, 2, Ivhd->CapabilityOffset + 0x10), AccessWidth32, &Value, StdHeader);
+  Ivhd->IommuInfo = (UINT16) (Value & 0x1f) | (0x13 << IVHD_INFO_UNITID_OFFSET);
+  Ivhd->IommuEfr = (0 << IVHD_EFR_XTSUP_OFFSET) | (0 << IVHD_EFR_NXSUP_OFFSET) | (1 << IVHD_EFR_GTSUP_OFFSET) |
+                   (0 << IVHD_EFR_GLXSUP_OFFSET) | (1 << IVHD_EFR_IASUP_OFFSET) | (0 << IVHD_EFR_GASUP_OFFSET) |
+                   (0 << IVHD_EFR_HESUP_OFFSET) | (0x8 << IVHD_EFR_PASMAX_OFFSET) | (0 << IVHD_EFR_MSINUMPPR_OFFSET) |
+                   (4 << IVHD_EFR_PNCOUNTERS_OFFSET) | (2 << IVHD_EFR_PNBANKS_OFFSET);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHD entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+  PCI_ADDR  Start;
+  PCI_ADDR  End;
+  Start.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
+  End.AddressValue = MAKE_SBDFO (0, 0xFF, 0x1F, 6, 0);
+  GnbIvhdAddDeviceRangeEntry (Start, End, 0, Ivhd, StdHeader);
+  SbCreateIvhdEntries (Ivhd, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create IVHDR entry
+ *
+ *
+ * @param[in]  Ivhd            IVHD header pointer
+ * @param[in]  StdHeader       Standard configuration header
+ *
+ */
+VOID
+GnbCreateIvhdrTN (
+     OUT   IVRS_IVHD_ENTRY            *Ivhd,
+  IN       AMD_CONFIG_PARAMS          *StdHeader
+  )
+{
+
+
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
new file mode 100644
index 0000000000..626f33d3aa
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbMidInitTN.c
@@ -0,0 +1,574 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64352 $   @e \$Date: 2012-01-19 03:54:04 -0600 (Thu, 19 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbFuseTable.h"
+#include  "heapManager.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbNbInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbGfxInitLibV1.h"
+#include  "GnbGfxConfig.h"
+#include  "GnbTable.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "OptionGnb.h"
+#include  "GfxLibTN.h"
+#include  "GnbFamServices.h"
+#include  "GnbGfxFamServices.h"
+#include  "GnbBapmCoeffCalcTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+extern GNB_TABLE ROMDATA      GnbMidInitTableTN[];
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUM_DPM_STATES 8
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Registers needs to be set if no GFX PCIe ports beeing us
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to PCIe_PLATFORM_CONFIG
+ */
+
+VOID
+STATIC
+GnbIommuMidInitCheckGfxPciePorts (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIe_WRAPPER_CONFIG   *WrapperList;
+  BOOLEAN               GfxPciePortUsed;
+  D0F2xF4_x57_STRUCT    D0F2xF4_x57;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n");
+  GfxPciePortUsed = FALSE;
+
+  WrapperList = PcieConfigGetChildWrapper (Pcie);
+  ASSERT (WrapperList != NULL);
+  if (WrapperList->WrapId == GFX_WRAP_ID) {
+    PCIe_ENGINE_CONFIG   *EngineList;
+    EngineList = PcieConfigGetChildEngine (WrapperList);
+    while (EngineList != NULL) {
+      if (PcieConfigIsPcieEngine (EngineList)) {
+        IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber);
+        if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+           ((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) {
+          // GFX PCIe ports beeing used
+          GfxPciePortUsed = TRUE;
+          IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n");
+          break;
+        }
+      }
+      EngineList = PcieLibGetNextDescriptor (EngineList);
+    }
+  }
+
+  if (!GfxPciePortUsed) {
+    //D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set
+    GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie));
+    D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1;
+    GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to for each PCIe port
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+GnbIommuMidInitOnPortCallback (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GNB_TOPOLOGY_INFO           TopologyInfo;
+  D0F2xFC_x07_L1_STRUCT       D0F2xFC_x07_L1;
+  D0F2xFC_x0D_L1_STRUCT       D0F2xFC_x0D_L1;
+  UINT8                       L1cfgSel;
+  TopologyInfo.PhantomFunction = FALSE;
+  TopologyInfo.PcieToPciexBridge = FALSE;
+  if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    TopologyInfo.PhantomFunction = TRUE;
+    TopologyInfo.PcieToPciexBridge = TRUE;
+  } else {
+    if (PcieConfigIsSbPcieEngine (Engine)) {
+      PCI_ADDR  StartSbPcieDev;
+      PCI_ADDR  EndSbPcieDev;
+      StartSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 0, 0);
+      EndSbPcieDev.AddressValue = MAKE_SBDFO (0, 0, 0x15, 7, 0);
+      GnbGetTopologyInfoV4 (StartSbPcieDev, EndSbPcieDev, &TopologyInfo, GnbLibGetHeader (Pcie));
+    } else {
+      GnbGetTopologyInfoV4 (Engine->Type.Port.Address, Engine->Type.Port.Address, &TopologyInfo, GnbLibGetHeader (Pcie));
+    }
+  }
+  L1cfgSel = (Engine->Type.Port.CoreId == 1) ? 1 : 0;
+  if (TopologyInfo.PhantomFunction) {
+    GnbRegisterReadTN (
+      D0F2xFC_x07_L1_TYPE,
+      D0F2xFC_x07_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x07_L1.Value,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+    D0F2xFC_x07_L1.Value |= BIT0;
+    GnbRegisterWriteTN (
+      D0F2xFC_x07_L1_TYPE,
+      D0F2xFC_x07_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x07_L1.Value,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  if (TopologyInfo.PcieToPciexBridge) {
+    GnbRegisterReadTN (
+      D0F2xFC_x0D_L1_TYPE,
+      D0F2xFC_x0D_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x0D_L1.Value,
+      0,
+      GnbLibGetHeader (Pcie)
+      );
+    D0F2xFC_x0D_L1.Field.VOQPortBits = 0x7;
+    GnbRegisterWriteTN (
+      D0F2xFC_x0D_L1_TYPE,
+      D0F2xFC_x0D_L1_ADDRESS (L1cfgSel),
+      &D0F2xFC_x0D_L1.Value,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Orb/Ioc Cgtt Override setting
+ *
+ *
+ * @param[in]  Property   Property
+ * @param[in]  StdHeader  Standard configuration header
+ */
+
+VOID
+STATIC
+GnbCgttOverrideTN (
+  IN      UINT32                          Property,
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  UINT32                          CGINDx0_Value;
+  UINT32                          CGINDx1_Value;
+  GFX_PLATFORM_CONFIG             *Gfx;
+  AGESA_STATUS                    Status;
+  D0F0x64_x23_STRUCT              D0F0x64_x23;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Enter\n");
+
+  CGINDx0_Value = 0xFFFFFFFF;
+  //When orb clock gating is enabled in the BIOS clear CG_ORB_cgtt_lclk_override - bit 13
+  CGINDx1_Value = 0xFFFFFFFF;
+  if ((Property & TABLE_PROPERTY_ORB_CLK_GATING) == TABLE_PROPERTY_ORB_CLK_GATING) {
+    CGINDx1_Value &= 0xFFFFDFFF;
+  }
+  //When ioc clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 15
+  if ((Property & TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) == TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING) {
+    CGINDx1_Value &= 0xFFFF7FFF;
+    if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) != TABLE_PROPERTY_IOMMU_DISABLED) {
+      //only IOMMU enabled and IOC clock gating enable
+      GnbRegisterReadTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, 0, StdHeader);
+      D0F0x64_x23.Field.SoftOverrideClk0 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk1 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk3 = 1;
+      D0F0x64_x23.Field.SoftOverrideClk4 = 1;
+      GnbRegisterWriteTN (D0F0x64_x23_TYPE, D0F0x64_x23_ADDRESS, &D0F0x64_x23.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+    }
+  }
+  //When smu sclk clock gating is enabled in the BIOS clear CG_IOC_cgtt_lclk_override - bit 18
+  if ((Property & TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) == TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING) {
+    CGINDx1_Value &= 0xFFFBFFFF;
+  }
+
+  Status = GfxLocateConfigData (StdHeader, &Gfx);
+  if (Status != AGESA_FATAL) {
+    if (Gfx->GmcClockGating) {
+      //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks
+      // CGINDx0, clear bit 27, bit 28
+      CGINDx0_Value &= 0xE7FFFFFF;
+      GnbRegisterWriteTN (TYPE_CGIND, 0x0, &CGINDx0_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+      // CGINDx1, clear bit 11
+      CGINDx1_Value &= 0xFFFFF7FF;
+    }
+
+  }
+
+  if (CGINDx1_Value != 0xFFFFFFFF) {
+    GnbRegisterWriteTN (TYPE_CGIND, 0x1, &CGINDx1_Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbCgttOverrideTN Exit\n");
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * IOMMU Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GnbIommuMidInit (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n");
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  if (Status == AGESA_SUCCESS) {
+    PcieConfigRunProcForAllEngines (
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+      GnbIommuMidInitOnPortCallback,
+      NULL,
+      Pcie
+      );
+  }
+
+  GnbIommuMidInitCheckGfxPciePorts (Pcie);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * IOMMU Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+STATIC AGESA_STATUS
+GnbLclkDpmInitTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS              Status;
+  PCIe_PLATFORM_CONFIG      *Pcie;
+  PP_FUSE_ARRAY             *PpFuseArray;
+  PCI_ADDR                  GnbPciAddress;
+  UINT32                    Index;
+  UINT8                     LclkDpmMode;
+  D0F0xBC_x1F200_STRUCT     D0F0xBC_x1F200[NUM_DPM_STATES];
+  D0F0xBC_x1F208_STRUCT     D0F0xBC_x1F208[NUM_DPM_STATES];
+  D0F0xBC_x1F210_STRUCT     D0F0xBC_x1F210[NUM_DPM_STATES];
+  D0F0xBC_x1F300_STRUCT     D0F0xBC_x1F300;
+  ex1003_STRUCT      ex1003 [NUM_DPM_STATES];
+  DOUBLE                    PcieCacLut;
+  ex1072_STRUCT      ex1072 ;
+  D0F0xBC_x1FE00_STRUCT     D0F0xBC_x1FE00;
+  D0F0xBC_x1F30C_STRUCT     D0F0xBC_x1F30C;
+  D18F3x64_STRUCT           D18F3x64;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n");
+  Status = AGESA_SUCCESS;
+  LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
+  IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
+  if (LclkDpmMode == LclkDpmRcActivity) {
+    PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+    if (PpFuseArray != NULL) {
+      Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+      if (Status == AGESA_SUCCESS) {
+        GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+        //Clear DPM_EN bit in LCLK_DPM_CNTL register
+        //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM
+        GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
+        D0F0xBC_x1F300.Field.LclkDpmEn = 0x0;
+        GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        GnbSmuServiceRequestV4 (
+          GnbPciAddress,
+          SMC_MSG_CONFIG_LCLK_DPM,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          StdHeader
+          );
+
+        //Initialize LCLK states
+        LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader);
+        LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
+        LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader);
+
+        D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0];
+        D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]];
+        D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf;
+
+        D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1];
+        D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]];
+        D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32;
+        D0F0xBC_x1F200[5].Field.StateValid = 0x1;
+
+        D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2];
+        D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]];
+        D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa;
+        D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32;
+        D0F0xBC_x1F200[6].Field.StateValid = 0x1;
+
+        GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader);
+        PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 );
+        IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
+        D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader));
+        GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+        PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 );
+        ex1003[6].Field.ex1003_0  = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
+        IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader));
+
+        for (Index = 0; Index < NUM_DPM_STATES; ++Index) {
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F200_TYPE,
+            D0F0xBC_x1F200_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F200[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F208_TYPE,
+            D0F0xBC_x1F208_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F208[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            D0F0xBC_x1F210_TYPE,
+            D0F0xBC_x1F210_ADDRESS + Index * 0x20,
+            &D0F0xBC_x1F210[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+          GnbRegisterWriteTN (
+            TYPE_D0F0xBC ,
+            0x1f940  + Index * 4,
+            &ex1003[Index].Value,
+            GNB_REG_ACC_FLAG_S3SAVE,
+            StdHeader
+            );
+        }
+        //Enable LCLK DPM Voltage Scaling
+        GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader);
+        D0F0xBC_x1F300.Field.VoltageChgEn = 0x1;
+        D0F0xBC_x1F300.Field.LclkDpmEn = 0x1;
+        D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5;
+        GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+
+        //Programming Lclk Thermal Throttling Threshold
+        GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader);
+        GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader);
+        D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8);
+        D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8);
+        GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader);
+
+        GnbSmuServiceRequestV4 (
+          GnbPciAddress,
+          SMC_MSG_CONFIG_LCLK_DPM,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          StdHeader
+          );
+      }
+    } else {
+      Status = AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Mid Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS      Status;
+  UINT32            Property;
+  AGESA_STATUS      AgesaStatus;
+  GNB_HANDLE        *GnbHandle;
+  UINT8             SclkDid;
+
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Enter\n");
+
+  GnbHandle = GnbGetHandle (StdHeader);
+  ASSERT (GnbHandle != NULL);
+
+  Property = TABLE_PROPERTY_DEAFULT;
+  Property |= GfxLibIsControllerPresent (StdHeader) ? 0 : TABLE_PROPERTY_IGFX_DISABLED;
+  Property |= GnbBuildOptions.LclkDeepSleepEn ? TABLE_PROPERTY_LCLK_DEEP_SLEEP : 0;
+  Property |= GnbBuildOptions.CfgOrbClockGatingEnable ? TABLE_PROPERTY_ORB_CLK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIocLclkClockGatingEnable ? TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING : 0;
+  Property |= GnbBuildOptions.CfgIocSclkClockGatingEnable ? TABLE_PROPERTY_IOC_SCLK_CLOCK_GATING : 0;
+  Property |= GnbFmCheckIommuPresent (GnbHandle, StdHeader) ? 0: TABLE_PROPERTY_IOMMU_DISABLED;
+  Property |= GnbBuildOptions.SmuSclkClockGatingEnable ? TABLE_PROPERTY_SMU_SCLK_CLOCK_GATING : 0;
+
+  IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
+
+  if ((Property & TABLE_PROPERTY_IOMMU_DISABLED) == 0) {
+    Status = GnbEnableIommuMmioV4 (GnbHandle, StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    Status = GnbIommuMidInit (StdHeader);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  }
+  //
+  // Set sclk to 100Mhz
+  //
+  SclkDid = GfxRequestSclkTNS3Save (
+              GfxLibCalculateDidTN (98 * 100, StdHeader),
+              StdHeader
+              );
+
+  Status = GnbProcessTable (
+             GnbHandle,
+             GnbMidInitTableTN,
+             Property,
+             GNB_TABLE_FLAGS_FORCE_S3_SAVE,
+             StdHeader
+             );
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  //
+  // Restore Sclk
+  //
+  GfxRequestSclkTNS3Save (
+    SclkDid,
+    StdHeader
+    );
+
+  GnbCgttOverrideTN (Property, StdHeader);
+
+  Status = GnbLclkDpmInitTN (StdHeader);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
new file mode 100644
index 0000000000..efa2af1256
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbPostInitTN.c
@@ -0,0 +1,128 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbNbInitLibV1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbPostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+GnbPostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS     Status;
+  PCI_ADDR         GnbAddress;
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Enter\n");
+  GnbAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+  Status = GnbSetTom (GnbAddress, StdHeader);
+  IDS_HDT_CONSOLE (GNB_TRACE, "GnbPostInterfaceTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
new file mode 100644
index 0000000000..8d36a1f620
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c
@@ -0,0 +1,1334 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize PP/DPM fuse table.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64211 $   @e \$Date: 2012-01-17 23:00:25 -0600 (Tue, 17 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegisterAccTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define GNB_IGNORED_PARAM             0xFF
+#define ORB_WRITE_ENABLE              0x100
+#define IOMMU_L1_WRITE_ENABLE         0x80000000ul
+#define IOMMU_L2_WRITE_ENABLE         0x100
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GnbRegisterWriteTNDump (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value
+  );
+AGESA_STATUS
+GnbRegisterReadServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GnbRegisterWriteServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Config Dct and Mp.
+ *
+ *
+ *
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[in] StdHeader          Standard configuration header
+ *
+ * @return          true - Memory Pstate context has been changed
+ * @return          false - Memory Pstate context has not been changed
+ */
+STATIC BOOLEAN
+GnbDctMpConfigTN (
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  // Select DCT and memory P-state, D18F1x10C[DctCfgSel], D18F1x10C[MemPsSel]
+  D18F1x10C_STRUCT      D18F1x10C;
+  BOOLEAN               MemPsChangd;
+  ACCESS_WIDTH          Width;
+
+  MemPsChangd = FALSE;
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS),
+    Width,
+    &D18F1x10C.Value,
+    StdHeader
+  );
+
+  if ((DctCfgSel != 0xFF) && (DctCfgSel < 2)) {
+    D18F1x10C.Field.DctCfgSel = DctCfgSel;
+  }
+
+  if ((MemPsSel != 0xFF) && (MemPsSel < 2) && (D18F1x10C.Field.MemPsSel != MemPsSel)) {
+    //Switches Mem Pstate
+    D18F1x10C.Field.MemPsSel = MemPsSel;
+    MemPsChangd = TRUE;
+  }
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 1, D18F1x10C_ADDRESS),
+    Width,
+    &D18F1x10C.Value,
+    StdHeader
+  );
+
+  return MemPsChangd;
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to Read Dct Additional Data.
+ *
+ *
+ *
+ * @param[in] Address            D18F2x9c Register offset
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[out] Value             Read value
+ * @param[in] StdHeader          Standard configuration header
+ */
+STATIC VOID
+GnbDctAdditionalDataReadTN (
+  IN       UINT32              Address,
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+     OUT   VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  D18F2x98_dct0_STRUCT  D18F2x98;
+  BOOLEAN               PstateChanged;
+  ACCESS_WIDTH          Width;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  PstateChanged = GnbDctMpConfigTN (
+                    DctCfgSel,
+                    MemPsSel,
+                    Flags,
+                    StdHeader
+                  );
+
+  // Clear DctAccessWrite
+  D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF;
+  D18F2x98.Field.DctAccessWrite = 0;
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)),
+    Width,
+    &D18F2x98.Value,
+    StdHeader
+  );
+
+  GnbLibPciRead (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)),
+    Width,
+    Value,
+    StdHeader
+  );
+
+  if (PstateChanged) {
+    GnbDctMpConfigTN (
+      DctCfgSel,
+      ((MemPsSel == 0) ? 1 : 0),
+      Flags,
+      StdHeader
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to Write Dct Additional Data.
+ *
+ *
+ *
+ * @param[in] Address            D18F2x9c Register offset
+ * @param[in] DctCfgSel          Dct0/Dct1
+ * @param[in] MemPsSel           Mp0/Mp1
+ * @param[in] Value              Write value
+ * @param[in] StdHeader          Standard configuration header
+ */
+STATIC VOID
+GnbDctAdditionalDataWriteTN (
+  IN       UINT32              Address,
+  IN       UINT8               DctCfgSel,
+  IN       UINT8               MemPsSel,
+  IN       UINT32              Flags,
+  IN       VOID                *Value,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  D18F2x98_dct0_STRUCT  D18F2x98;
+  BOOLEAN               PstateChanged;
+  ACCESS_WIDTH          Width;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+
+  PstateChanged = GnbDctMpConfigTN (
+                    DctCfgSel,
+                    MemPsSel,
+                    Flags,
+                    StdHeader
+                  );
+
+  // Put write data on
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x9C_dct0_ADDRESS : D18F2x9C_dct1_ADDRESS)),
+    Width,
+    Value,
+    StdHeader
+  );
+
+  // Set DctAccessWrite
+  D18F2x98.Field.DctOffset = Address & 0x3FFFFFFF;
+  D18F2x98.Field.DctAccessWrite = 1;
+
+  GnbLibPciWrite (
+    MAKE_SBDFO (0, 0, 0x18, 2, ((DctCfgSel == 0) ? D18F2x98_dct0_ADDRESS : D18F2x98_dct1_ADDRESS)),
+    Width,
+    &D18F2x98.Value,
+    StdHeader
+  );
+
+  if (PstateChanged) {
+    GnbDctMpConfigTN (
+      DctCfgSel,
+      ((MemPsSel == 0) ? 1 : 0),
+      Flags,
+      StdHeader
+      );
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to read all register spaces.
+ *
+ *
+ *
+ * @param[in] GnbHandle          GNB handle
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             Return value
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterReadServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return GnbRegisterReadTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to read all register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             Return value
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterReadTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  ACCESS_WIDTH          Width;
+  UINT32                TempValue;
+  UINT32                TempAddress;
+  BOOLEAN               PstateChanged;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+  TempAddress = 0;
+  TempValue = 0;
+
+
+  switch (RegisterSpaceType) {
+  case TYPE_D0F0:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D0F2:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F0:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 1, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F1:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 1, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_DxF0:
+    // Treat it as complete address for ports
+    GnbLibPciRead (
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F1:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F2:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F3:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 3, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F4:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 4, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F5:
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 5, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x64:
+    // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00]
+    // Write enable bit7
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x98:
+    // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00]
+    // Write enable bit8
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xBC:
+    {
+    //SMU, access D0F0xBC_x[FFFFFFFF:00000000]
+    // No write enable
+      UINT64  TempData;
+      //ASSERT ((Address < 0xE0100000 || Address > 0xE0108FFFF) && (Address & 0x3) == 0);
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS),
+        (Address & (~0x3ull)),
+        Width,
+        &TempData,
+        StdHeader
+      );
+      if ((Address & 0x3) != 0) {
+        //Non aligned access allowed to fuse block
+        GnbLibPciIndirectRead (
+          MAKE_SBDFO (0, 0, 0, 0, D0F0xB8_ADDRESS),
+          (Address & (~0x3ull)) + 4,
+          Width,
+          ((UINT32 *) &TempData) + 1,
+          StdHeader
+        );
+      }
+      * ((UINT32*) Value) = (UINT32) (TempData >> ((Address & 0x3) * 8));
+      break;
+    }
+  case TYPE_D0F0xE4:
+    // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000]
+    // No write enable
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xF4:
+    // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00].
+    // Write enable bit8
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xFC:
+    // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0]
+    // Write enable bit31
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_DxF0xE4:
+    // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00]
+    // No write enable
+    TempValue = ((Address >> 16) & 0xFF);
+    TempAddress = Address & 0xFF;
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS
+      TempAddress,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_MSR:
+    LibAmdMsrRead  (Address, Value, StdHeader);
+    break;
+
+  case TYPE_GMM:
+    ASSERT (Address < 0x40000);
+
+    if ((Address >= 0x600) && (Address <= 0x8FF)) {
+      // CG
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0xE0002000 | (Address - 0x600)),
+        Width,
+        Value,
+        StdHeader
+      );
+    } else {
+      // SRBM
+      GnbLibPciIndirectRead (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0x80080000 | (Address & 0x3FFFF)),
+        Width,
+        Value,
+        StdHeader
+      );
+    }
+    break;
+
+  case TYPE_D18F2x9C_dct0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      0,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp0:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp1:
+    GnbDctAdditionalDataReadTN (
+      Address,
+      1,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0:
+    GnbDctMpConfigTN (
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct0_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1:
+    GnbDctMpConfigTN (
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct1_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciRead (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_CGIND:
+    // CG index
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8F8 - 0x600)),
+      Width,
+      &Address,
+      StdHeader
+    );
+    // CG data
+    GnbLibPciIndirectRead (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8FC - 0x600)),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+
+
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to write all register spaces.
+ *
+ *
+ *
+ * @param[in] GnbHandle          GnbHandle
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             The value to write
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterWriteServiceTN (
+  IN       GNB_HANDLE          *GnbHandle,
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  return GnbRegisterWriteTN (RegisterSpaceType, Address, Value, Flags, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to write all register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset, but PortDevice
+ * @param[out] Value             The value to write
+ * @param[in] Flags              Flags - BIT0 indicates S3 save/restore
+ * @param[in] StdHeader          Standard configuration header
+ */
+AGESA_STATUS
+GnbRegisterWriteTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+
+  ACCESS_WIDTH          Width;
+  UINT32                TempValue;
+  UINT32                TempAddress;
+  PCI_ADDR              PciAddress;
+  BOOLEAN               PstateChanged;
+
+  Width = (Flags == GNB_REG_ACC_FLAG_S3SAVE) ? AccessS3SaveWidth32 : AccessWidth32;
+  TempAddress = 0;
+  TempValue = 0;
+
+  GNB_DEBUG_CODE (
+    GnbRegisterWriteTNDump (RegisterSpaceType, Address, Value);
+  );
+
+  switch (RegisterSpaceType) {
+  case TYPE_D0F0:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D0F2:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F0:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 1, 0, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D1F1:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 1, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_DxF0:
+    // Treat it as complete address for ports
+    GnbLibPciWrite (
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F1:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 1, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F2:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F3:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 3, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F4:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 4, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_D18F5:
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 5, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x64:
+    // Miscellaneous Index Data, access the registers D0F0x64_x[FF:00]
+    // Write enable bit7
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
+      Address | IOC_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0x98:
+    // Northbridge ORB Configuration Offset, access D0F0x98_x[FF:00]
+    // Write enable bit8
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0x94_ADDRESS),
+      Address | ORB_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xBC:
+    //SMU, access D0F0xBC_x[FFFFFFFF:00000000]
+    // No write enable
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F0xE4:
+    // D0F0xE0 Link Index Address, access D0F0xE4_x[FFFF_FFFF:0000_0000]
+    // No write enable
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, D0F0xE0_ADDRESS),
+      Address,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xF4:
+    // IOMMU L2 Config Index, to access the registers D0F2xF4_x[FF:00].
+    // Write enable bit8
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF0),//D0F2xF0_ADDRESS
+      Address | IOMMU_L2_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D0F2xFC:
+    // IOMMU L1 Config Index, access the registers D0F2xFC_x[FFFF:0000]_L1[3:0]
+    // Write enable bit31
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 2, 0xF8),//D0F2xF8_ADDRESS
+      Address | IOMMU_L1_WRITE_ENABLE,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_DxF0xE4:
+    // D[8:2]F0xE0 Root Port Index, access the registers D[8:2]F0xE4_x[FF:00]
+    // No write enable
+    TempValue = ((Address >> 16) & 0xFF);
+    TempAddress = Address & 0xFF;
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, (TempValue), 0, 0xE0),//DxF0xE0_ADDRESS
+      TempAddress,
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_MSR:
+    LibAmdMsrWrite  (Address, Value, StdHeader);
+    break;
+
+  case TYPE_GMM:
+    ASSERT (Address < 0x40000);
+
+    if ((Address >= 0x600) && (Address <= 0x8FF)) {
+      // CG
+      GnbLibPciIndirectWrite (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0xE0002000 | (Address - 0x600)),
+        Width,
+        Value,
+        StdHeader
+      );
+    } else {
+      // SRBM
+      GnbLibPciIndirectWrite (
+        MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+        (0x80080000 | (Address & 0x3FFFF)),
+        Width,
+        Value,
+        StdHeader
+      );
+    }
+    break;
+
+  case TYPE_D18F2x9C_dct0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct0_mp1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      0,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp0:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      0,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2x9C_dct1_mp1:
+    GnbDctAdditionalDataWriteTN (
+      Address,
+      1,
+      1,
+      Flags,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0:
+    GnbDctMpConfigTN (
+      0,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct0_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct0_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+                      0,
+                      1,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        0,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1:
+    GnbDctMpConfigTN (
+      1,
+      GNB_IGNORED_PARAM,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+
+  case TYPE_D18F2_dct1_mp0:
+    PstateChanged = GnbDctMpConfigTN (
+                      1,
+                      0,
+                      Flags,
+                      StdHeader
+                    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        1,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_D18F2_dct1_mp1:
+    PstateChanged = GnbDctMpConfigTN (
+      1,
+      1,
+      Flags,
+      StdHeader
+    );
+    GnbLibPciWrite (
+      MAKE_SBDFO (0, 0, 0x18, 2, Address),
+      Width,
+      Value,
+      StdHeader
+    );
+    if (PstateChanged) {
+      GnbDctMpConfigTN (
+        1,
+        0,
+        Flags,
+        StdHeader
+        );
+    }
+    break;
+
+  case TYPE_CGIND:
+    // CG index
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8F8 - 0x600)),
+      Width,
+      &Address,
+      StdHeader
+    );
+    // CG data
+    GnbLibPciIndirectWrite (
+      MAKE_SBDFO (0, 0, 0, 0, 0xB8),
+      (0xE0002000 | (0x8FC - 0x600)),
+      Width,
+      Value,
+      StdHeader
+    );
+    break;
+  case TYPE_SMU_MSG:
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
+    GnbSmuServiceRequestV4 (PciAddress, (UINT8) Address, Flags, StdHeader);
+    break;
+  default:
+    ASSERT (FALSE);
+    break;
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ *  Routine to dump all write register spaces.
+ *
+ *
+ *
+ * @param[in] RegisterSpaceType  Register space type
+ * @param[in] Address            Register offset
+ * @param[in] Value              The value to write
+ */
+VOID
+GnbRegisterWriteTNDump (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value
+  )
+{
+  IDS_HDT_CONSOLE (NB_MISC, "  R WRITE Space %s  Address 0x%04x, Value 0x%04x\n",
+    (RegisterSpaceType == TYPE_D0F0) ? "TYPE_D0F0" : (
+    (RegisterSpaceType == TYPE_D0F0x64) ? "TYPE_D0F0x64" : (
+    (RegisterSpaceType == TYPE_D0F0x98) ? "TYPE_D0F0x98" : (
+    (RegisterSpaceType == TYPE_D0F0xBC) ? "TYPE_D0F0xBC" : (
+    (RegisterSpaceType == TYPE_D0F0xE4) ? "TYPE_D0F0xE4" : (
+    (RegisterSpaceType == TYPE_DxF0) ? "TYPE_DxF0" : (
+    (RegisterSpaceType == TYPE_DxF0xE4) ? "TYPE_DxF0xE4" : (
+    (RegisterSpaceType == TYPE_D0F2) ? "TYPE_D0F2" : (
+    (RegisterSpaceType == TYPE_D0F2xF4) ? "TYPE_D0F2xF4" : (
+    (RegisterSpaceType == TYPE_D0F2xFC) ? "TYPE_D0F2xFC" : (
+    (RegisterSpaceType == TYPE_D18F1) ? "TYPE_D18F1" : (
+    (RegisterSpaceType == TYPE_D18F2) ? "TYPE_D18F2" : (
+    (RegisterSpaceType == TYPE_D18F3) ? "TYPE_D18F3" : (
+    (RegisterSpaceType == TYPE_D18F4) ? "TYPE_D18F4" : (
+    (RegisterSpaceType == TYPE_D18F5) ? "TYPE_D18F5" : (
+    (RegisterSpaceType == TYPE_MSR) ? "TYPE_MSR" : (
+    (RegisterSpaceType == TYPE_D1F0) ? "TYPE_D1F0" : (
+    (RegisterSpaceType == TYPE_D1F1) ? "TYPE_D1F1" : (
+    (RegisterSpaceType == TYPE_GMM) ? "TYPE_GMM" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0) ? "TYPE_D18F2x9C_dct0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp0) ? "TYPE_D18F2x9C_dct0_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct0_mp1) ? "TYPE_D18F2x9C_dct0_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1) ? "TYPE_D18F2x9C_dct1" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp0) ? "TYPE_D18F2x9C_dct1_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2x9C_dct1_mp1) ? "TYPE_D18F2x9C_dct1_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0) ? "TYPE_D18F2_dct0" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0_mp0) ? "TYPE_D18F2_dct0_mp0" : (
+    (RegisterSpaceType == TYPE_D18F2_dct0_mp1) ? "TYPE_D18F2_dct0_mp1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1) ? "TYPE_D18F2_dct1" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1_mp0) ? "TYPE_D18F2_dct1_mp0" : (
+    (RegisterSpaceType == TYPE_SMU_MSG) ? "TYPE_SMU_MSG" : (
+    (RegisterSpaceType == TYPE_D18F2_dct1_mp1) ? "TYPE_D18F2_dct1_mp1" : "Invalid"))))))))))))))))))))))))))))))),
+    Address,
+    *((UINT32*)Value)
+  );
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h
new file mode 100644
index 0000000000..6de5c469ae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h
@@ -0,0 +1,101 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * various service procedures
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _GNBREGISTERACCTN_H_
+#define _GNBREGISTERACCTN_H_
+
+AGESA_STATUS
+GnbRegisterWriteTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+  IN       VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+GnbRegisterReadTN (
+  IN       UINT8               RegisterSpaceType,
+  IN       UINT32              Address,
+     OUT   VOID                *Value,
+  IN       UINT32              Flags,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+// Marco
+// DxF0 Port space
+#define PORT_SPACE(Dev, Offset) MAKE_SBDFO (0, 0, Dev, 0, Offset)
+
+// DxF0xE4 Port indirect space
+#define PORTINDT_SPACE(Dev , Func, Offset) ((((UINT32) (Dev)) << 16) | (((UINT32) (Func)) << 8) | \
+                                             ((UINT32)(Offset)))
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
new file mode 100644
index 0000000000..8c44a71d89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
@@ -0,0 +1,14126 @@
+/**
+ * @file
+ *
+ * SMU firmware
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65874 $   @e \$Date: 2012-02-26 21:24:59 -0600 (Sun, 26 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBSMUFIRMWARETN_H_
+#define _GNBSMUFIRMWARETN_H_
+
+UINT32  FirmwareTN[] = {
+ 0x000a0004,
+ 0x00000040,
+ 0x000036a1,
+ 0x00010100,
+ 0xeee2b111,
+ 0x724cbe84,
+ 0xf7cde4cd,
+ 0xbf04e85e,
+ 0x9bdebdfc,
+ 0x0001d7f4,
+ 0x0001d904,
+ 0x00000000,
+ 0x0001d925,
+ 0x0001d934,
+ 0x0001d848,
+ 0x0001da6c,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0xaa55aa55,
+ 0x98000000,
+ 0x98000000,
+ 0xd0000000,
+ 0x78010001,
+ 0x38210100,
+ 0xd0e10000,
+ 0xd1210000,
+ 0xf8000039,
+ 0x5b9d0000,
+ 0xf8000062,
+ 0xf80033ff,
+ 0xe0000098,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf8000044,
+ 0xf8003456,
+ 0xe000007d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0xf8000052,
+ 0xf800344e,
+ 0xe0000088,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf8000034,
+ 0xf8003458,
+ 0xe000006d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf800002c,
+ 0xf8003462,
+ 0xe0000065,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0xf8000025,
+ 0x34010002,
+ 0xf8003476,
+ 0xe000005d,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x5b9d0000,
+ 0x37de0004,
+ 0xf800001c,
+ 0xf8003464,
+ 0xe0000055,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x98000000,
+ 0x781c0001,
+ 0x3b9cebfc,
+ 0x781a0002,
+ 0x3b5a5b80,
+ 0x78010001,
+ 0x3821db84,
+ 0x78030001,
+ 0x3863e038,
+ 0x44230004,
+ 0x58200000,
+ 0x34210004,
+ 0xe3fffffd,
+ 0x34010000,
+ 0x34020000,
+ 0x78030001,
+ 0x3863fe80,
+ 0x58610000,
+ 0x58610018,
+ 0x34030000,
+ 0xf80002b5,
+ 0xf800013d,
+ 0x379cff80,
+ 0x5b810004,
+ 0x5b820008,
+ 0x5b83000c,
+ 0x5b840010,
+ 0x5b850014,
+ 0x5b860018,
+ 0x5b87001c,
+ 0x5b880020,
+ 0x5b890024,
+ 0x5b8a0028,
+ 0x5b9e0078,
+ 0x5b9f007c,
+ 0x2b810080,
+ 0x5b810074,
+ 0xbb800800,
+ 0x34210080,
+ 0x5b810070,
+ 0x98210800,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x379cff80,
+ 0x5b810004,
+ 0x5b820008,
+ 0x5b83000c,
+ 0x5b840010,
+ 0x5b850014,
+ 0x5b860018,
+ 0x5b87001c,
+ 0x5b880020,
+ 0x5b890024,
+ 0x5b8a0028,
+ 0x5b8b002c,
+ 0x5b8c0030,
+ 0x5b8d0034,
+ 0x5b8e0038,
+ 0x5b8f003c,
+ 0x5b900040,
+ 0x5b910044,
+ 0x5b920048,
+ 0x5b93004c,
+ 0x5b940050,
+ 0x5b950054,
+ 0x5b960058,
+ 0x5b97005c,
+ 0x5b980060,
+ 0x5b990064,
+ 0x5b9a0068,
+ 0x5b9b006c,
+ 0x5b9e0078,
+ 0x5b9f007c,
+ 0x2b810080,
+ 0x5b810074,
+ 0xbb800800,
+ 0x34210080,
+ 0x5b810070,
+ 0x98210800,
+ 0xd0010000,
+ 0xc3a00000,
+ 0x34010002,
+ 0xd0010000,
+ 0x2b810004,
+ 0x2b820008,
+ 0x2b83000c,
+ 0x2b840010,
+ 0x2b850014,
+ 0x2b860018,
+ 0x2b87001c,
+ 0x2b880020,
+ 0x2b890024,
+ 0x2b8a0028,
+ 0x2b9d0074,
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+ 0x34020000,
+ 0x38c60124,
+ 0x3884d925,
+ 0x396bd848,
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+ 0xa0411000,
+ 0x34a50100,
+ 0x00a50009,
+ 0x14630008,
+ 0x00420013,
+ 0xb4a32800,
+ 0x34140000,
+ 0x7c420001,
+ 0x0c85000a,
+ 0xba80b000,
+ 0x5c540022,
+ 0x78010001,
+ 0x3821f844,
+ 0x28210000,
+ 0x7804e020,
+ 0x38840000,
+ 0x3c210002,
+ 0x78020001,
+ 0xb4240800,
+ 0x28210000,
+ 0x3842f848,
+ 0x78030001,
+ 0x202107ff,
+ 0x3421fe78,
+ 0x3c210011,
+ 0x3863f84c,
+ 0x5b810064,
+ 0x28410000,
+ 0x3c210002,
+ 0xb4240800,
+ 0x28210000,
+ 0x202107ff,
+ 0x3421fe78,
+ 0x3c210011,
+ 0x5b810068,
+ 0x28610000,
+ 0x3c210002,
+ 0xb4240800,
+ 0x28210000,
+ 0x202107ff,
+ 0x3421fe78,
+ 0x3c210011,
+ 0x5b81006c,
+ 0xe000006e,
+ 0x780d0001,
+ 0x39adde40,
+ 0x29a10000,
+ 0xbb208000,
+ 0x3ece0003,
+ 0x3a10dd2c,
+ 0x2e030000,
+ 0x2e020002,
+ 0xb5c10800,
+ 0x28210000,
+ 0x378b005c,
+ 0xb4621000,
+ 0xb9601800,
+ 0xfbfffeac,
+ 0x3401000c,
+ 0xb9601000,
+ 0xfbfffc79,
+ 0x29a20000,
+ 0x3ecc0002,
+ 0x78010001,
+ 0x3821dd8c,
+ 0xb5816000,
+ 0xb5c21000,
+ 0x28410004,
+ 0x378f0054,
+ 0xb9e01800,
+ 0x29820000,
+ 0x3791004c,
+ 0x36d60003,
+ 0xfbfffe7f,
+ 0xb9600800,
+ 0xb9e01000,
+ 0xba201800,
+ 0xfbfffc7a,
+ 0x2b820050,
+ 0x2b81004c,
+ 0x29a30000,
+ 0x0042001f,
+ 0x2e040004,
+ 0xb4220800,
+ 0xb5c31800,
+ 0x59810000,
+ 0x28610008,
+ 0x2e020006,
+ 0xb9601800,
+ 0xb4821000,
+ 0xfbfffe8b,
+ 0x3401000c,
+ 0xb9601000,
+ 0xfbfffc58,
+ 0x29a10000,
+ 0x29820004,
+ 0xb9e01800,
+ 0xb5c10800,
+ 0x2821000c,
+ 0xfbfffe65,
+ 0xb9600800,
+ 0xb9e01000,
+ 0xba201800,
+ 0xfbfffc60,
+ 0x2b820050,
+ 0x2b81004c,
+ 0x29a30000,
+ 0x0042001f,
+ 0x2e04000a,
+ 0xb4220800,
+ 0xb5c31800,
+ 0x59810004,
+ 0x28610010,
+ 0x2e020008,
+ 0xb9601800,
+ 0xb4441000,
+ 0xfbfffe71,
+ 0x3401000c,
+ 0xb9601000,
+ 0xfbfffc3e,
+ 0x29a10000,
+ 0x29820008,
+ 0xb9e01800,
+ 0xb5c17000,
+ 0x29c10014,
+ 0xfbfffe4b,
+ 0xb9600800,
+ 0xb9e01000,
+ 0xba201800,
+ 0xfbfffc46,
+ 0x34040005,
+ 0x8e842000,
+ 0x2b810050,
+ 0x29850004,
+ 0x29830000,
+ 0x2b82004c,
+ 0x0021001f,
+ 0x14630004,
+ 0xb4411000,
+ 0x14a50004,
+ 0x14410004,
+ 0xb4651800,
+ 0xb4611800,
+ 0x37810074,
+ 0x59820008,
+ 0x3c840002,
+ 0x36940001,
+ 0xb4812000,
+ 0x2881fff0,
+ 0x7682000e,
+ 0xb4230800,
+ 0x5881fff0,
+ 0x4440ff94,
+ 0x2b830064,
+ 0x2b820068,
+ 0x2b81006c,
+ 0x14630004,
+ 0x14420004,
+ 0x14210004,
+ 0x5b830064,
+ 0x5b820068,
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+ 0x2a410050,
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+ 0x2a410050,
+ 0x2021000c,
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+ 0x5b810068,
+ 0x780c0001,
+ 0x2b830064,
+ 0x2b840068,
+ 0x2b85006c,
+ 0xb9800800,
+ 0x3821dd2c,
+ 0x5825001c,
+ 0x58230014,
+ 0x58240018,
+ 0x2a420010,
+ 0xb9803800,
+ 0x00410018,
+ 0x3c210010,
+ 0x4c61000a,
+ 0x00410008,
+ 0x202100ff,
+ 0x3c210010,
+ 0x4c810006,
+ 0x2a410014,
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+ 0x4ca10002,
+ 0xe000004b,
+ 0x34010001,
+ 0x32a10001,
+ 0x780c0001,
+ 0xb9800800,
+ 0x3821de44,
+ 0x2823000c,
+ 0x28250018,
+ 0x40240003,
+ 0x2a420028,
+ 0x206300ff,
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+ 0x3821dd2c,
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+ 0x0c25002e,
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+ 0x2b86006c,
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+ 0x3c420010,
+ 0xc8260800,
+ 0xb9801800,
+ 0x48220005,
+ 0x2b810068,
+ 0xc8260800,
+ 0x48220002,
+ 0xe000000e,
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+ 0x3821de44,
+ 0x28220010,
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+ 0x2824001c,
+ 0x204200ff,
+ 0x3c420008,
+ 0xb8e00800,
+ 0x206300ff,
+ 0x3821dd2c,
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+ 0x28450018,
+ 0x58250004,
+ 0x28420018,
+ 0x78010001,
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+ 0x58220010,
+ 0x42a10000,
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+ 0x5c20003e,
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+ 0x780b0001,
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+ 0x28a10014,
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+ 0x78010001,
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+ 0x29610080,
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+ 0x78010001,
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+ 0x78010001,
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+ 0x3821dd25,
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+ 0xa0611800,
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+ 0x38c6f428,
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+ 0x3402fffd,
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+ 0x28610000,
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+ 0x379c0010,
+ 0xc3a00000,
+ 0x78020001,
+ 0x3842debc,
+ 0x28430000,
+ 0xb8202800,
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+ 0x379c0020,
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+ 0x379cffe8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x780c0001,
+ 0x398cdecc,
+ 0x298b0000,
+ 0x780d0001,
+ 0x780e0001,
+ 0x29610068,
+ 0x39adf5f8,
+ 0x39cef5fc,
+ 0xf8001891,
+ 0x78020001,
+ 0x5961006c,
+ 0x3842dec4,
+ 0x40410000,
+ 0x78030001,
+ 0x3863dec5,
+ 0x40620000,
+ 0xb8220800,
+ 0x202500ff,
+ 0x5ca0004f,
+ 0x29880000,
+ 0x78060001,
+ 0x38c6dec0,
+ 0x2904006c,
+ 0x29030074,
+ 0xb8a00800,
+ 0x00840003,
+ 0x00630013,
+ 0x34020001,
+ 0x20630003,
+ 0x20840003,
+ 0x780b0001,
+ 0x780f0001,
+ 0x5c640040,
+ 0x30c50000,
+ 0x2904006c,
+ 0x29a30000,
+ 0x3401ffe7,
+ 0xa0813000,
+ 0x20620003,
+ 0x3401ff3f,
+ 0x00630002,
+ 0xa0813800,
+ 0x3c420003,
+ 0x29090068,
+ 0x00840003,
+ 0x20630003,
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+ 0x3c650006,
+ 0xb9200800,
+ 0x20840003,
+ 0xb8c01000,
+ 0x4c83000e,
+ 0x5906006c,
+ 0xf8001856,
+ 0x29850000,
+ 0x29a40000,
+ 0x3403ff3f,
+ 0x28a2006c,
+ 0x3c840004,
+ 0x28a10068,
+ 0xa0431000,
+ 0x208400c0,
+ 0xb8441000,
+ 0x58a2006c,
+ 0xe0000010,
+ 0xb8e53800,
+ 0xb9200800,
+ 0xb8e01000,
+ 0x5907006c,
+ 0xf8001846,
+ 0x29840000,
+ 0x29a30000,
+ 0x3401ffe7,
+ 0x2882006c,
+ 0x20630003,
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+ 0xa0411000,
+ 0x28810068,
+ 0xb8431000,
+ 0x5882006c,
+ 0xf800183b,
+ 0x78010001,
+ 0x3821d8f8,
+ 0x34020000,
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+ 0x29c10000,
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+ 0x38210002,
+ 0x59c10000,
+ 0x29610000,
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+ 0x5b9d0004,
+ 0x78010001,
+ 0x78020001,
+ 0x3821dec4,
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+ 0x40210000,
+ 0x40420000,
+ 0x78030001,
+ 0x780a0001,
+ 0xb8220800,
+ 0x3863decc,
+ 0x394af5fc,
+ 0x202500ff,
+ 0x5ca0001f,
+ 0x28630000,
+ 0x78090001,
+ 0x78080001,
+ 0x2864006c,
+ 0x78070001,
+ 0x341d0001,
+ 0x28630074,
+ 0x00840006,
+ 0x78060001,
+ 0x00630013,
+ 0x3929ded0,
+ 0x3908dec0,
+ 0x38e7d8f8,
+ 0x38c66528,
+ 0xb8a01000,
+ 0xbba00800,
+ 0x20840003,
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+ 0x5c64000b,
+ 0x29210000,
+ 0x30fd0004,
+ 0x31050000,
+ 0x58260028,
+ 0x31450000,
+ 0x29410000,
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+ 0xa0220800,
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+ 0xe0000002,
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+ 0x2b9d0004,
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+ 0xc3a00000,
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+ 0x5b8b0010,
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+ 0x5b8d0008,
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+ 0x780c0001,
+ 0x78058000,
+ 0x78010001,
+ 0x3821f6c0,
+ 0x40420008,
+ 0x40210003,
+ 0x780d0001,
+ 0x398cdecc,
+ 0x38a50000,
+ 0x39adf5fc,
+ 0x4841002b,
+ 0x29840000,
+ 0x2883006c,
+ 0x28810068,
+ 0xb8651800,
+ 0xb8601000,
+ 0x5883006c,
+ 0xf80017d9,
+ 0x298b0000,
+ 0x29610070,
+ 0xf80017e4,
+ 0x59610074,
+ 0x29810000,
+ 0x34070003,
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+ 0x2822006c,
+ 0x78040001,
+ 0x340a0001,
+ 0x28210074,
+ 0x00420006,
+ 0x38c6671c,
+ 0x00210013,
+ 0x34090000,
+ 0x38846788,
+ 0x34080002,
+ 0xa0270800,
+ 0xa0471000,
+ 0x78050001,
+ 0x78030001,
+ 0x5c220008,
+ 0x3863ded0,
+ 0x28610000,
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+ 0x30aa0006,
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+ 0x31a80000,
+ 0xe0000007,
+ 0x3863ded0,
+ 0x28610000,
+ 0x38a5d8f8,
+ 0x30a90004,
+ 0x58240028,
+ 0x31a70000,
+ 0x2b8b0010,
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+ 0x379c0010,
+ 0xc3a00000,
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+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f5f8,
+ 0x28210000,
+ 0x780c0001,
+ 0x78030001,
+ 0x00210012,
+ 0x78047fff,
+ 0x20210001,
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+ 0x780d0001,
+ 0xb9803000,
+ 0x64210000,
+ 0x3863decc,
+ 0x3884ffff,
+ 0x396bf5fc,
+ 0x39adf850,
+ 0x38c6ded8,
+ 0x5c200018,
+ 0x29a10090,
+ 0x28c20000,
+ 0x78050001,
+ 0x00210018,
+ 0x78040001,
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+ 0x29610000,
+ 0x28c20000,
+ 0x38a5ded0,
+ 0x38210001,
+ 0x59610000,
+ 0x29a10090,
+ 0x40420008,
+ 0x38846310,
+ 0x00210018,
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+ 0xfbffff95,
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+ 0x28a10000,
+ 0x58240028,
+ 0x31630000,
+ 0xe0000010,
+ 0x28630000,
+ 0x398cded8,
+ 0x2862006c,
+ 0x28610068,
+ 0xa0441000,
+ 0x5862006c,
+ 0xf800177b,
+ 0x29610000,
+ 0x3402ffef,
+ 0xa0220800,
+ 0x59610000,
+ 0x29a1008c,
+ 0x29820000,
+ 0x00210018,
+ 0x30410002,
+ 0x2b8b0010,
+ 0x2b8c000c,
+ 0x2b8d0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78060001,
+ 0x38c6f5f8,
+ 0x78010001,
+ 0x3821dec8,
+ 0x28c20000,
+ 0x28210000,
+ 0x78050001,
+ 0x38a5f5fc,
+ 0x204200ff,
+ 0x78030001,
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+ 0x3842d8f8,
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+ 0x5c20000b,
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+ 0x28c20000,
+ 0x00410010,
+ 0x20210001,
+ 0x5c200005,
+ 0x78010001,
+ 0x3821d8f8,
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+ 0x20210001,
+ 0x5c200007,
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+ 0xe0000002,
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+ 0x44200022,
+ 0x00410008,
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+ 0x00410001,
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+ 0x5c200003,
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+ 0x5c20000f,
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+ 0x78020001,
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+ 0x58410028,
+ 0x30a30000,
+ 0xe000002c,
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+ 0xe0000006,
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+ 0x58a10000,
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+ 0x78010001,
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+ 0x58410028,
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+ 0x78020001,
+ 0x3821dec4,
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+ 0x40210000,
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+ 0x78050001,
+ 0xb8220800,
+ 0x78040001,
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+ 0x3884f5fc,
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+ 0x3821d902,
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+ 0xe000000a,
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+ 0x39ad0004,
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+ 0x3401fff7,
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+ 0x2b900024,
+ 0x2b910020,
+ 0x2b92001c,
+ 0x2b930018,
+ 0x2b940014,
+ 0x2b950010,
+ 0x2b96000c,
+ 0x2b970008,
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+ 0x41a20003,
+ 0x2041000f,
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+ 0x204100f0,
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+ 0x2041000f,
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+ 0x38210000,
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+ 0x38210000,
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+ 0x5ca00002,
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+ 0x34040000,
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+ 0x204100f0,
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+ 0x34040000,
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+ 0x41a20004,
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+ 0x204100f0,
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+ 0xb8801000,
+ 0xfbfff94a,
+ 0x340c0000,
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+ 0x78010001,
+ 0x3821d7cc,
+ 0xb4411800,
+ 0xb60c0800,
+ 0x40210000,
+ 0x358c0001,
+ 0x340200ff,
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+ 0x4420fff3,
+ 0x340c0000,
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+ 0x78010001,
+ 0x3821d7e0,
+ 0xb4615800,
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+ 0x78020001,
+ 0x40210000,
+ 0x3842df20,
+ 0xb4626800,
+ 0x358c0001,
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+ 0x296b0000,
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+ 0x3561000b,
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+ 0x29a20014,
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+ 0x5b8b001c,
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+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
+ 0x5b9d0004,
+ 0xf8000eae,
+ 0xb8206000,
+ 0xfbffeb76,
+ 0x78080001,
+ 0x780b0001,
+ 0xb9006800,
+ 0x396bf438,
+ 0x3908f610,
+ 0x41020000,
+ 0x41630000,
+ 0x780f0001,
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+ 0xb8208000,
+ 0x39eff43c,
+ 0x39cef6bc,
+ 0x34090000,
+ 0x44690011,
+ 0x29840014,
+ 0x00810008,
+ 0x208800ff,
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+ 0x20650001,
+ 0x20410001,
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+ 0x00660001,
+ 0x89052000,
+ 0x64210000,
+ 0x204200ff,
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+ 0x44200002,
+ 0x88e52000,
+ 0xb5244800,
+ 0x5c60fff5,
+ 0x78080001,
+ 0x356b0001,
+ 0x3908f614,
+ 0x34070002,
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+ 0xb5071000,
+ 0x40230000,
+ 0x40420000,
+ 0x44600011,
+ 0x2984001c,
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+ 0x20650001,
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+ 0x40230000,
+ 0x40420000,
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+ 0x4465001c,
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+ 0x34bd0001,
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+ 0x2984001c,
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+ 0x94451000,
+ 0x208100ff,
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+ 0x20420001,
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+ 0xbba02800,
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+ 0x5b90001c,
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+ 0x5b930010,
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+ 0x78100001,
+ 0x34010000,
+ 0x3a10f3c4,
+ 0x78140001,
+ 0x780c0001,
+ 0x78130001,
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+ 0xb8206800,
+ 0x33810038,
+ 0xb840a800,
+ 0x3a94f438,
+ 0x3a73f710,
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+ 0x398cf6c8,
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+ 0x44200016,
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+ 0x78160001,
+ 0x34010000,
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+ 0xb840c000,
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+ 0x5b810048,
+ 0xb8207000,
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+ 0x41a10000,
+ 0x34110000,
+ 0xba20c800,
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+ 0x41a10005,
+ 0x4431008a,
+ 0x42010038,
+ 0x7c2100ff,
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+ 0x42010040,
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+ 0x5c200030,
+ 0x78130001,
+ 0x3dcf0002,
+ 0xba600800,
+ 0x3821d7e0,
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+ 0x282c0000,
+ 0x780b0001,
+ 0x396bdf20,
+ 0x3581000b,
+ 0xfbfff747,
+ 0xb5eb5800,
+ 0x59610000,
+ 0x3581000c,
+ 0xfbfff743,
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+ 0x5c40000c,
+ 0x780b0001,
+ 0x396bdf48,
+ 0x3581400f,
+ 0xfbfff73c,
+ 0xb5eb5800,
+ 0x59610000,
+ 0x3581400a,
+ 0xfbfff738,
+ 0x3402fffd,
+ 0xa0220800,
+ 0x59610014,
+ 0xba206000,
+ 0xba600800,
+ 0x3821d7e0,
+ 0xb5e10800,
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+ 0x3d830007,
+ 0x78020001,
+ 0x3dcb0003,
+ 0x3842dee8,
+ 0xb4230800,
+ 0xb5625800,
+ 0x34216005,
+ 0xfbfff728,
+ 0xb56c5800,
+ 0x00210018,
+ 0x358c0001,
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+ 0x31610000,
+ 0x4440ffef,
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+ 0xb68e3000,
+ 0xb8220800,
+ 0x202100ff,
+ 0x23070001,
+ 0x44200018,
+ 0x40a20000,
+ 0x34030001,
+ 0x41a10000,
+ 0xbc621000,
+ 0x41a40005,
+ 0xa4401000,
+ 0xa0411000,
+ 0x31a20000,
+ 0x40c10000,
+ 0xbc610800,
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+ 0x40c20000,
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+ 0xa4601800,
+ 0xa0230800,
+ 0xe0000019,
+ 0x3781005c,
+ 0xb42e1000,
+ 0x34010001,
+ 0x3041ffec,
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+ 0x31a10005,
+ 0x40c20000,
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+ 0x31a10005,
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+ 0x5c20000b,
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+ 0x37810050,
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+ 0xa0621000,
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+ 0x64210000,
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+ 0x42020040,
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+ 0xb6ce2800,
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+ 0x340107d0,
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+ 0xbae07800,
+ 0xb9c08000,
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+ 0xb6ce6000,
+ 0x41a50000,
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+ 0x41830000,
+ 0x41820008,
+ 0x37910058,
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+ 0x40210000,
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+ 0xa0651800,
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+ 0x98461000,
+ 0xb8431000,
+ 0xb8240800,
+ 0x204200ff,
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+ 0x44200029,
+ 0x28eb0000,
+ 0x39610002,
+ 0xfbfff66c,
+ 0x41810038,
+ 0x5c200006,
+ 0x41830040,
+ 0x39610010,
+ 0x3402fffe,
+ 0x5c600002,
+ 0xfbfff66c,
+ 0x78010001,
+ 0x3821d7e0,
+ 0xb6012800,
+ 0xb62e0800,
+ 0x40210000,
+ 0xb6171800,
+ 0xb64e2000,
+ 0x44200005,
+ 0x41a20005,
+ 0x40610003,
+ 0xb8220800,
+ 0x30610003,
+ 0x40810000,
+ 0x44200005,
+ 0x41e10001,
+ 0x41a20000,
+ 0xb8220800,
+ 0x31e10001,
+ 0x28a10000,
+ 0x29e20000,
+ 0x38210012,
+ 0xfbfff645,
+ 0x41e10003,
+ 0x41e20001,
+ 0xb76e2000,
+ 0x40830000,
+ 0xa0220800,
+ 0xa4200800,
+ 0xa0230800,
+ 0x30810000,
+ 0x35ce0001,
+ 0x75c10004,
+ 0x35ad0001,
+ 0x36100004,
+ 0x35ef0004,
+ 0x4420ffbc,
+ 0xfbfffd24,
+ 0x2b8b0044,
+ 0x2b8c0040,
+ 0x2b8d003c,
+ 0x2b8e0038,
+ 0x2b8f0034,
+ 0x2b900030,
+ 0x2b91002c,
+ 0x2b920028,
+ 0x2b930024,
+ 0x2b940020,
+ 0x2b95001c,
+ 0x2b960018,
+ 0x2b970014,
+ 0x2b980010,
+ 0x2b99000c,
+ 0x2b9b0008,
+ 0x2b9d0004,
+ 0x379c005c,
+ 0xc3a00000,
+ 0x379cffe4,
+ 0x5b8b001c,
+ 0x5b8c0018,
+ 0x5b8d0014,
+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
+ 0x5b9d0004,
+ 0x780c0001,
+ 0x398cf6c4,
+ 0x29820000,
+ 0x780100ff,
+ 0x38210000,
+ 0x780d0001,
+ 0x39addf10,
+ 0xa0410800,
+ 0x5c2000b6,
+ 0x780eff00,
+ 0xb9c00800,
+ 0x3821ffff,
+ 0xa0410800,
+ 0x442000b1,
+ 0x78020001,
+ 0x3842f604,
+ 0x28410000,
+ 0x38210002,
+ 0x58410000,
+ 0xfbfff5d2,
+ 0x7801e030,
+ 0x38210000,
+ 0x340206ff,
+ 0x5822000c,
+ 0xb8201000,
+ 0x28410204,
+ 0x20210400,
+ 0x4420fffe,
+ 0x7803e030,
+ 0x78020008,
+ 0x38630000,
+ 0x38420000,
+ 0x28610204,
+ 0xa0220800,
+ 0x4420fffe,
+ 0x7810e000,
+ 0xba005800,
+ 0x396b000c,
+ 0x29640000,
+ 0x3402fffb,
+ 0x78010132,
+ 0xa0822000,
+ 0x78022000,
+ 0x7803f000,
+ 0x59640000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff602,
+ 0x29610000,
+ 0x340ffffe,
+ 0x78020001,
+ 0xa02f0800,
+ 0x59610000,
+ 0x3842f3a0,
+ 0x28420000,
+ 0x78010131,
+ 0x3821fff0,
+ 0xfbfff5e0,
+ 0x29a20000,
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+ 0x38210012,
+ 0xfbfff5dc,
+ 0x29a20004,
+ 0x78010111,
+ 0x38210013,
+ 0xfbfff5d8,
+ 0x29a20008,
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+ 0x38210012,
+ 0xfbfff5d4,
+ 0x29a2000c,
+ 0x78010211,
+ 0x38210013,
+ 0xfbfff5d0,
+ 0x78010131,
+ 0x38218040,
+ 0x34020001,
+ 0xfbfff5cc,
+ 0x78010131,
+ 0x38218041,
+ 0x34020001,
+ 0xfbfff5c8,
+ 0x78010131,
+ 0x38218042,
+ 0x34020001,
+ 0xfbfff5c4,
+ 0x78010131,
+ 0x38218043,
+ 0x34020001,
+ 0xfbfff5c0,
+ 0x4182003d,
+ 0x41830045,
+ 0x78010111,
+ 0x38210002,
+ 0xb8431000,
+ 0xa4401000,
+ 0x204200ff,
+ 0xfbfff5c2,
+ 0x4181003d,
+ 0x340d0000,
+ 0x5c2d0003,
+ 0x41810045,
+ 0x442d0006,
+ 0x78010111,
+ 0x34020001,
+ 0x38210010,
+ 0xfbfff5b9,
+ 0xe000000a,
+ 0x78010111,
+ 0x340200ff,
+ 0x38210002,
+ 0xfbfff5b4,
+ 0x78010131,
+ 0x38218070,
+ 0xb9e01000,
+ 0x340d0001,
+ 0xfbfff5b6,
+ 0x4182003e,
+ 0x41830046,
+ 0x78010211,
+ 0x38210002,
+ 0xb8431000,
+ 0xa4401000,
+ 0x204200ff,
+ 0xfbfff5a7,
+ 0x4181003e,
+ 0x5c200008,
+ 0x418b0046,
+ 0x5d600006,
+ 0x78010131,
+ 0x3402fffe,
+ 0x38218074,
+ 0xfbfff5a6,
+ 0xe0000007,
+ 0x78010211,
+ 0x65ab0000,
+ 0x38210010,
+ 0x34020001,
+ 0xfbfff599,
+ 0x5d600005,
+ 0x78010131,
+ 0x38218062,
+ 0x3802a000,
+ 0xfbfff594,
+ 0x78010132,
+ 0x7803f000,
+ 0x38630000,
+ 0x34020000,
+ 0x38218014,
+ 0xfbfff59c,
+ 0x78010130,
+ 0x7803f000,
+ 0x38630000,
+ 0x34020000,
+ 0x38218014,
+ 0xfbfff596,
+ 0xba001000,
+ 0x3842000c,
+ 0x28430000,
+ 0x3404fffd,
+ 0x78010131,
+ 0xa0641800,
+ 0x58430000,
+ 0x38218060,
+ 0x34020004,
+ 0xfbfff595,
+ 0x5d600006,
+ 0x78010131,
+ 0x7802ffff,
+ 0x38218062,
+ 0x38425fff,
+ 0xfbfff57f,
+ 0x78010311,
+ 0x38210011,
+ 0x34020300,
+ 0xfbfff56a,
+ 0x78010131,
+ 0x38218023,
+ 0x34020000,
+ 0xfbfff566,
+ 0x78030001,
+ 0x3863f6c4,
+ 0x28620000,
+ 0x39ceffff,
+ 0x78010001,
+ 0xa04e1000,
+ 0x38210000,
+ 0xb8411000,
+ 0x58620000,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b9d0004,
+ 0x379c001c,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f47c,
+ 0x40230003,
+ 0x78040001,
+ 0x78020001,
+ 0x7c610001,
+ 0x3884f39c,
+ 0x3842f6c4,
+ 0x5c200006,
+ 0x30430000,
+ 0x28810000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbffff22,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cffd0,
+ 0x5b8b0020,
+ 0x5b8c001c,
+ 0x5b8d0018,
+ 0x5b8e0014,
+ 0x5b8f0010,
+ 0x5b90000c,
+ 0x5b910008,
+ 0x5b9d0004,
+ 0x78100001,
+ 0xba000800,
+ 0x3821f6c4,
+ 0x28250000,
+ 0x78070001,
+ 0x38e7f478,
+ 0x34010000,
+ 0x3381002d,
+ 0x33810024,
+ 0x33810025,
+ 0x33810026,
+ 0x33810027,
+ 0x33810028,
+ 0x33810029,
+ 0x3381002a,
+ 0x3381002b,
+ 0x3381002c,
+ 0x28e20000,
+ 0x780f00ff,
+ 0xb9e02000,
+ 0x00410018,
+ 0xb8403000,
+ 0x3c210002,
+ 0x204cffff,
+ 0x34210008,
+ 0x202100ff,
+ 0x38840000,
+ 0x3c220010,
+ 0x7803ff00,
+ 0xa0a42800,
+ 0x3863ffff,
+ 0x00a50010,
+ 0xa1836000,
+ 0x3c210018,
+ 0x00c40010,
+ 0xb9826000,
+ 0x780e0001,
+ 0xb9816000,
+ 0x39cef6c8,
+ 0x20b100ff,
+ 0x208400ff,
+ 0x340b0000,
+ 0x01810010,
+ 0x948b1000,
+ 0x34210001,
+ 0x202100ff,
+ 0x356b0001,
+ 0x20420001,
+ 0x3c210010,
+ 0x75650003,
+ 0x64420000,
+ 0x44400004,
+ 0xa1836000,
+ 0xb9816000,
+ 0x44a0fff4,
+ 0x01820010,
+ 0x01810018,
+ 0x204200ff,
+ 0xc8410800,
+ 0x342b0001,
+ 0x780100ff,
+ 0xb8201800,
+ 0x3c420018,
+ 0x3863ffff,
+ 0xa1836000,
+ 0x75610003,
+ 0xb9826000,
+ 0x5c200010,
+ 0x00c10010,
+ 0xb8602800,
+ 0x202400ff,
+ 0x948b1000,
+ 0x01810018,
+ 0x356b0001,
+ 0x34210001,
+ 0x20420001,
+ 0x3c210018,
+ 0x75630003,
+ 0x64420000,
+ 0x5c400004,
+ 0xa1856000,
+ 0xb9816000,
+ 0x4460fff5,
+ 0x40e10000,
+ 0x68210003,
+ 0x5c20000d,
+ 0x21810007,
+ 0x4420000b,
+ 0x01820010,
+ 0x01810018,
+ 0x204200ff,
+ 0xfbfff82a,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffeb4,
+ 0x21810003,
+ 0x44200038,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210008,
+ 0x5c200033,
+ 0x378d0024,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfff833,
+ 0x340b0001,
+ 0x37850029,
+ 0xb5ab0800,
+ 0xb4ab1000,
+ 0x40210000,
+ 0x40420000,
+ 0xb5cb2000,
+ 0xb8220800,
+ 0x202100ff,
+ 0x202300f0,
+ 0x2021000f,
+ 0x44200005,
+ 0x40810010,
+ 0x202100f0,
+ 0x30810010,
+ 0xe0000006,
+ 0xb5cb1000,
+ 0x44600004,
+ 0x40410010,
+ 0x2021000f,
+ 0x30410010,
+ 0x356b0001,
+ 0x75610004,
+ 0x4420ffeb,
+ 0x78010131,
+ 0x38218014,
+ 0xfbfff4b5,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff4aa,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfffc0e,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfff906,
+ 0xb9a00800,
+ 0xb9801000,
+ 0xfbfff9eb,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff49d,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e200016,
+ 0x3a10f6c4,
+ 0x2a010000,
+ 0x39ef0000,
+ 0xa02f0800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba205800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff487,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff47e,
+ 0x2b8b0020,
+ 0x2b8c001c,
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+ 0x2b8e0014,
+ 0x2b8f0010,
+ 0x2b90000c,
+ 0x2b910008,
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+ 0x379c0030,
+ 0xc3a00000,
+ 0x379cffcc,
+ 0x5b8b0024,
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+ 0x5b8e0018,
+ 0x5b8f0014,
+ 0x5b900010,
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+ 0xba202000,
+ 0x3884f6c4,
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+ 0x34010000,
+ 0x78020001,
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+ 0x3842f478,
+ 0x40420000,
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+ 0xba000800,
+ 0x38210000,
+ 0xa0611800,
+ 0x204c00ff,
+ 0x00630010,
+ 0x21810001,
+ 0x780e0001,
+ 0x64210000,
+ 0x39cef6c8,
+ 0x207200ff,
+ 0x5c200003,
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+ 0x202c00ff,
+ 0x3d810002,
+ 0x68430003,
+ 0x34210008,
+ 0x202100ff,
+ 0x34220007,
+ 0x3c420018,
+ 0x3c2d0010,
+ 0xb9a26800,
+ 0x5c600009,
+ 0x78010001,
+ 0x3821f39c,
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+ 0x34020001,
+ 0x30820000,
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+ 0xfbfffe17,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f39c,
+ 0x28210000,
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+ 0x344c0001,
+ 0x5c200043,
+ 0xb5cc5800,
+ 0x41610010,
+ 0x642100ff,
+ 0x5c20003f,
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+ 0x3402ffff,
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+ 0x31630020,
+ 0x31620010,
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+ 0x78010001,
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+ 0xe0000007,
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+ 0x5c200006,
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+ 0x40230000,
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+ 0x39ad0003,
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+ 0xfbfff77c,
+ 0x41610038,
+ 0xb5cc1000,
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+ 0xa4200800,
+ 0x30410000,
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+ 0xa4200800,
+ 0x3061fff9,
+ 0x40420000,
+ 0xb8220800,
+ 0x202100ff,
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+ 0x38218014,
+ 0xfbfff409,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff3fe,
+ 0xb9c00800,
+ 0xb9a01000,
+ 0xfbfffb62,
+ 0xb9c00800,
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+ 0xfbfff85a,
+ 0xb9a01000,
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+ 0xfbfff93f,
+ 0xb9c00800,
+ 0xfbfff79e,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff3ef,
+ 0x39eff39c,
+ 0x29e10000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e400016,
+ 0x3a31f6c4,
+ 0x2a210000,
+ 0x3a100000,
+ 0xa0300800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba405800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff3da,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff3d1,
+ 0x2b8b0024,
+ 0x2b8c0020,
+ 0x2b8d001c,
+ 0x2b8e0018,
+ 0x2b8f0014,
+ 0x2b900010,
+ 0x2b91000c,
+ 0x2b920008,
+ 0x2b9d0004,
+ 0x379c0034,
+ 0xc3a00000,
+ 0x379cffd4,
+ 0x5b8b001c,
+ 0x5b8c0018,
+ 0x5b8d0014,
+ 0x5b8e0010,
+ 0x5b8f000c,
+ 0x5b900008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f6c4,
+ 0x28220000,
+ 0x780e00ff,
+ 0x780d0001,
+ 0x34010000,
+ 0x33810029,
+ 0x33810020,
+ 0x33810021,
+ 0x33810022,
+ 0x33810023,
+ 0x33810024,
+ 0x33810025,
+ 0x33810026,
+ 0x33810027,
+ 0x33810028,
+ 0xb9c00800,
+ 0x38210000,
+ 0x39adf39c,
+ 0xa0411000,
+ 0x29a30000,
+ 0x00420010,
+ 0x20610007,
+ 0x205000ff,
+ 0x44200009,
+ 0x00620010,
+ 0x00610018,
+ 0x204200ff,
+ 0xfbfff6ee,
+ 0x29a10000,
+ 0x20210010,
+ 0x5c200002,
+ 0xfbfffd7a,
+ 0x29a20000,
+ 0x20410003,
+ 0x4420001d,
+ 0x20410008,
+ 0x5c20001b,
+ 0x78010131,
+ 0x38218014,
+ 0xfbfff399,
+ 0xb8205800,
+ 0x78010131,
+ 0x3402ffc3,
+ 0x38218014,
+ 0xa1621000,
+ 0xfbfff38e,
+ 0x29a20000,
+ 0x378c0020,
+ 0xb9800800,
+ 0xfbfff6f2,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfffaee,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfff7e6,
+ 0x29a20000,
+ 0xb9800800,
+ 0xfbfff8cb,
+ 0x78010131,
+ 0x38218014,
+ 0xb9601000,
+ 0xfbfff37d,
+ 0x29a10000,
+ 0x20210010,
+ 0x5c20001b,
+ 0x780d0131,
+ 0x780c0001,
+ 0x39ad8010,
+ 0x398cf688,
+ 0x5e000016,
+ 0x39eff6c4,
+ 0x29e10000,
+ 0x39ce0000,
+ 0xa02e0800,
+ 0x00210010,
+ 0x7c210001,
+ 0x5c20000f,
+ 0xba005800,
+ 0x29820000,
+ 0xb5ab0800,
+ 0x356b0001,
+ 0xfbfff369,
+ 0x75610007,
+ 0x358c0004,
+ 0x4420fffa,
+ 0x78010001,
+ 0x3821f6a8,
+ 0x28220000,
+ 0x78010201,
+ 0x38210011,
+ 0xfbfff360,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b9d0004,
+ 0x379c002c,
+ 0xc3a00000,
+ 0x379cffe8,
+ 0x5b8b0018,
+ 0x5b8c0014,
+ 0x5b8d0010,
+ 0x5b8e000c,
+ 0x5b8f0008,
+ 0x5b9d0004,
+ 0x780f0001,
+ 0xb9e00800,
+ 0x3821f6c4,
+ 0x28220000,
+ 0x780d0131,
+ 0x780b0001,
+ 0x780100ff,
+ 0x38210000,
+ 0x39ad8010,
+ 0x396bf688,
+ 0xa0410800,
+ 0x44200084,
+ 0x780eff00,
+ 0xb9c00800,
+ 0x3821ffff,
+ 0xa0410800,
+ 0x5c20007f,
+ 0xb8206000,
+ 0xb5ac0800,
+ 0xfbfff341,
+ 0x59610000,
+ 0x358c0001,
+ 0x75810007,
+ 0x356b0004,
+ 0x4420fffa,
+ 0x78010201,
+ 0x38210011,
+ 0x780b0001,
+ 0xfbfff338,
+ 0x396bf6a8,
+ 0x59610000,
+ 0x78010111,
+ 0x38210012,
+ 0x780b0001,
+ 0xfbfff332,
+ 0x396bdf10,
+ 0x59610000,
+ 0x78010111,
+ 0x38210013,
+ 0xfbfff32d,
+ 0x59610004,
+ 0x78010211,
+ 0x38210012,
+ 0xfbfff329,
+ 0x59610008,
+ 0x78010211,
+ 0x38210013,
+ 0xfbfff325,
+ 0x5961000c,
+ 0x78010321,
+ 0x78028100,
+ 0x38420000,
+ 0x38210009,
+ 0xfbfff324,
+ 0x78010321,
+ 0x78028100,
+ 0x38420000,
+ 0x3821000a,
+ 0xfbfff31f,
+ 0x78010131,
+ 0x34020100,
+ 0x38218011,
+ 0xfbfff31b,
+ 0x78010132,
+ 0x78022000,
+ 0x7803f000,
+ 0x38420000,
+ 0x38630000,
+ 0x38218014,
+ 0xfbfff322,
+ 0x78010130,
+ 0x78021000,
+ 0x7803f000,
+ 0x38420000,
+ 0x38630000,
+ 0x38218014,
+ 0xfbfff31b,
+ 0x78010130,
+ 0x78021000,
+ 0x7803f000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff314,
+ 0x78010111,
+ 0x3402fffe,
+ 0x38210010,
+ 0xfbfff309,
+ 0x78010211,
+ 0x3402fffe,
+ 0x38210010,
+ 0xfbfff305,
+ 0x78010132,
+ 0x78023000,
+ 0x7803f000,
+ 0x38630000,
+ 0x38420000,
+ 0x38218014,
+ 0xfbfff305,
+ 0x78010132,
+ 0x34020001,
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+ 0xfbfff30a,
+ 0x7801e000,
+ 0x38212028,
+ 0x28220000,
+ 0x34010064,
+ 0x204b007f,
+ 0xf80003c1,
+ 0xf80003ac,
+ 0x7804e000,
+ 0xb8801800,
+ 0x3863000c,
+ 0x28610000,
+ 0x7802e030,
+ 0x38420000,
+ 0x38210004,
+ 0x58610000,
+ 0x340105ff,
+ 0x5841000c,
+ 0x28410204,
+ 0x20210400,
+ 0x5c20fffe,
+ 0xb8801800,
+ 0x3863000c,
+ 0x28620000,
+ 0xb9600800,
+ 0x39ceffff,
+ 0x38420003,
+ 0x58620000,
+ 0xf8000397,
+ 0x78020001,
+ 0x3842f604,
+ 0x28410000,
+ 0x3403fffd,
+ 0xa0230800,
+ 0x58410000,
+ 0xfbfff291,
+ 0xb9e01000,
+ 0x3842f6c4,
+ 0x28410000,
+ 0xa02e0800,
+ 0x58410000,
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+ 0x2b8c0014,
+ 0x2b8d0010,
+ 0x2b8e000c,
+ 0x2b8f0008,
+ 0x2b9d0004,
+ 0x379c0018,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f39c,
+ 0x28210000,
+ 0x20210010,
+ 0x5c200003,
+ 0xfbffff5b,
+ 0xfbfff99e,
+ 0x2b9d0004,
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+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f47c,
+ 0x40210003,
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+ 0x78020001,
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+ 0x34040000,
+ 0x3863f39c,
+ 0x3842f6c4,
+ 0x5c240006,
+ 0x30440000,
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+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cffd8,
+ 0x5b8b0018,
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+ 0x5b8d0010,
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+ 0x780e0001,
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+ 0x3c210002,
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+ 0xa1836000,
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+ 0x780f0001,
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+ 0x39adf6c8,
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+ 0x34050000,
+ 0x01810010,
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+ 0x34210001,
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+ 0x20420001,
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+ 0xa1836000,
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+ 0x44c0fff4,
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+ 0x34250001,
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+ 0x37860022,
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+ 0xb8617000,
+ 0x0c4e0024,
+ 0x288f40ac,
+ 0x01ee000d,
+ 0x0c4e0026,
+ 0x288f40ac,
+ 0x289040b0,
+ 0x01e3001d,
+ 0x3e010003,
+ 0xb8617000,
+ 0x304e0029,
+ 0x288f40b0,
+ 0x01ee0005,
+ 0x304e002b,
+ 0x288f40b0,
+ 0x01ee000d,
+ 0x304e0008,
+ 0x288f40b0,
+ 0x01ee0015,
+ 0x21c10007,
+ 0x3c210015,
+ 0xb8a12800,
+ 0x5845000c,
+ 0x288f40b0,
+ 0x3401c0ff,
+ 0x01ee0018,
+ 0x304e000c,
+ 0x288f40b4,
+ 0x0c4f002e,
+ 0x288f40b4,
+ 0x01ee0010,
+ 0x0c4e0036,
+ 0x0c4e0034,
+ 0x288f40b8,
+ 0x0c4f0032,
+ 0x288f40b8,
+ 0x01ee0010,
+ 0x0c4e0038,
+ 0x288f40bc,
+ 0x28430028,
+ 0x28450004,
+ 0x0c4f0030,
+ 0x288f40bc,
+ 0xa0611800,
+ 0xa0ac2800,
+ 0x01ee0010,
+ 0x0c4e002c,
+ 0x288f40c0,
+ 0x21e1003f,
+ 0x3c210008,
+ 0xb8611800,
+ 0x58430028,
+ 0x288f40c0,
+ 0x01ee0006,
+ 0x304e0028,
+ 0x288f413c,
+ 0x21e107ff,
+ 0x3c21000d,
+ 0xb8a12800,
+ 0x58450004,
+ 0x288f413c,
+ 0x01ee000b,
+ 0x304e0020,
+ 0x288f413c,
+ 0x01ee0013,
+ 0x304e0021,
+ 0x288f413c,
+ 0x28904140,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0022,
+ 0x288f4140,
+ 0x01ee0003,
+ 0x304e0010,
+ 0x288f4140,
+ 0x01ee000b,
+ 0x304e0012,
+ 0x288f4140,
+ 0x01ee0013,
+ 0x304e0011,
+ 0x288f4140,
+ 0x28904144,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0013,
+ 0x288f4144,
+ 0x01ee0003,
+ 0x304e0014,
+ 0x288f4144,
+ 0x01ee000b,
+ 0x304e0015,
+ 0x288f4148,
+ 0x01ee000b,
+ 0x304e0050,
+ 0x288f4148,
+ 0x01ee0013,
+ 0x304e0051,
+ 0x288f4148,
+ 0x2890414c,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x304e0052,
+ 0x288f414c,
+ 0x01ee0003,
+ 0x21ce0fff,
+ 0x0c4e0054,
+ 0x288f414c,
+ 0x01ee000f,
+ 0x21ce0fff,
+ 0x0c4e0056,
+ 0x288f414c,
+ 0x28904150,
+ 0x01e3001b,
+ 0x3e010005,
+ 0xb8617000,
+ 0x21ce0fff,
+ 0x0c4e0058,
+ 0x288f4150,
+ 0x01ee0007,
+ 0x21ce0fff,
+ 0x0c4e005a,
+ 0x288f4150,
+ 0x01ee0013,
+ 0x21ce0fff,
+ 0x0c4e005c,
+ 0x288f4150,
+ 0x28904154,
+ 0x01e3001f,
+ 0x3e010001,
+ 0xb8617000,
+ 0x21ce0fff,
+ 0x0c4e005e,
+ 0x288f4154,
+ 0x3401c000,
+ 0x01ee000b,
+ 0x304e004c,
+ 0x288f4154,
+ 0x01ee0013,
+ 0x304e004d,
+ 0x288f4154,
+ 0x28904158,
+ 0x2843004c,
+ 0x01e6001b,
+ 0x3e050005,
+ 0xa0611800,
+ 0xb8c57000,
+ 0x21c13fff,
+ 0xb8611800,
+ 0x5843004c,
+ 0x288f4158,
+ 0x01ee0009,
+ 0x21c10001,
+ 0x3c210017,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f415c,
+ 0xa0ed3800,
+ 0x01ee0006,
+ 0x21ce003f,
+ 0x304e0060,
+ 0x288f415c,
+ 0x01ee000c,
+ 0x21ce003f,
+ 0x304e0061,
+ 0x288f415c,
+ 0x01ee0012,
+ 0x21ce003f,
+ 0x304e0062,
+ 0x288f415c,
+ 0x01ee0018,
+ 0x21ce003f,
+ 0x304e0063,
+ 0x288f415c,
+ 0x28904160,
+ 0x01e3001e,
+ 0x3e010002,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0064,
+ 0x288f4160,
+ 0x01ee0004,
+ 0x21ce003f,
+ 0x304e0065,
+ 0x288f4160,
+ 0x01ee000a,
+ 0x21ce003f,
+ 0x304e0066,
+ 0x288f4160,
+ 0x01ee0010,
+ 0x21ce003f,
+ 0x304e0067,
+ 0x288f4160,
+ 0x01ee0016,
+ 0x21ce003f,
+ 0x304e0068,
+ 0x288f4160,
+ 0x28904164,
+ 0x01e3001c,
+ 0x3e010004,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0069,
+ 0x288f4164,
+ 0x01ee0002,
+ 0x21ce003f,
+ 0x304e006a,
+ 0x288f4164,
+ 0x01ee0008,
+ 0x21ce003f,
+ 0x304e006b,
+ 0x288f4164,
+ 0x01ee000e,
+ 0x21ce003f,
+ 0x304e006c,
+ 0x288f4164,
+ 0x01ee0014,
+ 0x21ce003f,
+ 0x304e006d,
+ 0x288f4164,
+ 0x01ee001a,
+ 0x304e006e,
+ 0x288f4168,
+ 0x21ee003f,
+ 0x304e006f,
+ 0x288f4170,
+ 0x01ee000e,
+ 0x304e0023,
+ 0x288f4174,
+ 0x01ee0008,
+ 0x304f0084,
+ 0x304e0085,
+ 0x01ee0010,
+ 0x304e0086,
+ 0x01ee0018,
+ 0x304e0087,
+ 0x288f4178,
+ 0x01ee0008,
+ 0x304f0088,
+ 0x304e0089,
+ 0x01ee0010,
+ 0x304e008a,
+ 0x01ee0018,
+ 0x304e008b,
+ 0x288f417c,
+ 0x01ee0008,
+ 0x304f0091,
+ 0x304e0092,
+ 0x01ee0010,
+ 0x304e0093,
+ 0x01ee0018,
+ 0x304e0094,
+ 0x288f4180,
+ 0x01ee0008,
+ 0x304f0096,
+ 0x304e0097,
+ 0x01ee0010,
+ 0x304e0098,
+ 0x01ee0018,
+ 0x304e0099,
+ 0x288f6000,
+ 0x01ee0018,
+ 0x304e003c,
+ 0x288f6004,
+ 0x01ee0008,
+ 0x304f003d,
+ 0x304e003e,
+ 0x01ee0010,
+ 0x304e003f,
+ 0x288f6008,
+ 0x01ee0008,
+ 0x304f0040,
+ 0x304e0041,
+ 0x01ee0010,
+ 0x304e0042,
+ 0x01ee0018,
+ 0x304e0043,
+ 0x288f600c,
+ 0x01ee0008,
+ 0x304f0044,
+ 0x304e0045,
+ 0x01ee0010,
+ 0x304e0046,
+ 0x01ee0018,
+ 0x304e0047,
+ 0x288f6014,
+ 0x01ee0008,
+ 0x3dc1001f,
+ 0xb8e13800,
+ 0x5847001c,
+ 0x288f6020,
+ 0x01ee0003,
+ 0x21c103ff,
+ 0xb9615800,
+ 0x584b0000,
+ 0x288f7048,
+ 0x01ee000b,
+ 0x01e3001d,
+ 0x21ce003f,
+ 0x304e0074,
+ 0x01ee0011,
+ 0x21ce003f,
+ 0x304e0075,
+ 0x01ee0017,
+ 0x21ce003f,
+ 0x304e0076,
+ 0x2890704c,
+ 0x3e010003,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0077,
+ 0x020e0003,
+ 0x0203001b,
+ 0x21ce003f,
+ 0x304e0078,
+ 0x020e0009,
+ 0x21ce003f,
+ 0x304e0079,
+ 0x020e000f,
+ 0x21ce003f,
+ 0x304e007a,
+ 0x020e0015,
+ 0x21ce003f,
+ 0x304e007b,
+ 0x28907050,
+ 0x3e010005,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e007c,
+ 0x020e0001,
+ 0x0203001f,
+ 0x21ce003f,
+ 0x304e007d,
+ 0x020e0007,
+ 0x21ce003f,
+ 0x304e007e,
+ 0x020e000d,
+ 0x21ce003f,
+ 0x304e007f,
+ 0x020e0013,
+ 0x21ce003f,
+ 0x304e0080,
+ 0x020e0019,
+ 0x21ce003f,
+ 0x304e0081,
+ 0x28907054,
+ 0x3e010001,
+ 0xb8617000,
+ 0x21ce003f,
+ 0x304e0082,
+ 0x020e0005,
+ 0x21ce003f,
+ 0x304e0083,
+ 0x288f705c,
+ 0x01ee0003,
+ 0x304e0004,
+ 0x288f70e0,
+ 0x01ee0015,
+ 0x30480095,
+ 0x21c1000f,
+ 0x30410053,
+ 0x30480090,
+ 0x3d210002,
+ 0xb42a1000,
+ 0x28420000,
+ 0xb4310800,
+ 0x35290001,
+ 0x58220000,
+ 0x75210026,
+ 0x4420fff9,
+ 0x2b8b001c,
+ 0x2b8c0018,
+ 0x2b8d0014,
+ 0x2b8e0010,
+ 0x2b8f000c,
+ 0x2b900008,
+ 0x2b910004,
+ 0x379c001c,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0008,
+ 0x5b9d0004,
+ 0x34020000,
+ 0x780b0001,
+ 0x78058000,
+ 0x396bfe80,
+ 0x38a50338,
+ 0x5b82000c,
+ 0xbbe01800,
+ 0x3401fffc,
+ 0xa0611800,
+ 0xb8402000,
+ 0xb8203800,
+ 0x3c820002,
+ 0x34860001,
+ 0xb4451000,
+ 0x28410000,
+ 0xa0270800,
+ 0x58410000,
+ 0x44230014,
+ 0x20c400ff,
+ 0x74810003,
+ 0x4420fff7,
+ 0x4161001b,
+ 0x202200ff,
+ 0x7c410001,
+ 0x5c200012,
+ 0xd1020000,
+ 0x34010001,
+ 0x3161001a,
+ 0x4161001a,
+ 0x7c210001,
+ 0x4420fffe,
+ 0x4161001b,
+ 0x202100ff,
+ 0x5c200037,
+ 0xd1010000,
+ 0xfbffcc9d,
+ 0xe0000034,
+ 0x37810010,
+ 0xb4241000,
+ 0x34010001,
+ 0x3041fffc,
+ 0xe3ffffec,
+ 0x4381000c,
+ 0x44200009,
+ 0x28a10000,
+ 0xd2010000,
+ 0x34010001,
+ 0x31610003,
+ 0x41610003,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe0000025,
+ 0x4381000d,
+ 0x44200009,
+ 0x28a10004,
+ 0xd2210000,
+ 0x34010001,
+ 0x31610002,
+ 0x41610002,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe000001b,
+ 0x4381000e,
+ 0x44200009,
+ 0x28a10008,
+ 0xd2410000,
+ 0x34010001,
+ 0x31610001,
+ 0x41610001,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe0000011,
+ 0x4381000f,
+ 0x44200009,
+ 0x28a1000c,
+ 0xd2610000,
+ 0x34010001,
+ 0x31610000,
+ 0x41610000,
+ 0x7c210001,
+ 0x4420fffe,
+ 0xe0000007,
+ 0xfbffcc6e,
+ 0x34010002,
+ 0x31610003,
+ 0x41610003,
+ 0x7c210002,
+ 0x4420fffe,
+ 0x2b8b0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884fe80,
+ 0xbbe01800,
+ 0x4081000f,
+ 0x3402fffc,
+ 0x3c630002,
+ 0xa0220800,
+ 0x38210001,
+ 0x3081000f,
+ 0x2881000c,
+ 0x20210003,
+ 0xb8230800,
+ 0x5881000c,
+ 0x4081000f,
+ 0x20210003,
+ 0x7c210001,
+ 0x4420fffd,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884fe80,
+ 0xbbe01800,
+ 0x40810013,
+ 0x3402fffc,
+ 0x3c630002,
+ 0xa0220800,
+ 0x38210001,
+ 0x30810013,
+ 0x28810010,
+ 0x20210003,
+ 0xb8230800,
+ 0x58810010,
+ 0x40810013,
+ 0x20210003,
+ 0x7c210001,
+ 0x4420fffd,
+ 0xc3a00000,
+ 0x78040001,
+ 0x3884fe80,
+ 0xbbe01800,
+ 0x4081000b,
+ 0x3402fffc,
+ 0x3c630002,
+ 0xa0220800,
+ 0x38210001,
+ 0x3081000b,
+ 0x28810008,
+ 0x20210003,
+ 0xb8230800,
+ 0x58810008,
+ 0x4081000b,
+ 0x20210003,
+ 0x7c210001,
+ 0x4420fffd,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x7801e000,
+ 0x38210124,
+ 0x34020001,
+ 0x58220000,
+ 0x78030001,
+ 0x3863d848,
+ 0x34010000,
+ 0x30610003,
+ 0xc3a00000,
+ 0x379cfff0,
+ 0x5b8b0010,
+ 0x5b8c000c,
+ 0x5b8d0008,
+ 0x5b9d0004,
+ 0x780d0001,
+ 0xb9a01800,
+ 0x3863e028,
+ 0x40610000,
+ 0x78028001,
+ 0x38420000,
+ 0x34210001,
+ 0x30610000,
+ 0x28410058,
+ 0x5c200068,
+ 0x780b8001,
+ 0xb9601000,
+ 0x38420000,
+ 0x2844005c,
+ 0x34010001,
+ 0xb960e800,
+ 0xbc242800,
+ 0xb9604800,
+ 0x6881001f,
+ 0xb9606000,
+ 0x5c200003,
+ 0x58450050,
+ 0xe0000002,
+ 0x58450054,
+ 0x7c860028,
+ 0x7c81001d,
+ 0x3c8a0002,
+ 0xa0c10800,
+ 0x6488001e,
+ 0x64210000,
+ 0x78070001,
+ 0x5c200027,
+ 0xb9201800,
+ 0x78050001,
+ 0x78020001,
+ 0x38630000,
+ 0x38a5db74,
+ 0x3842db80,
+ 0x34090004,
+ 0x5d00001f,
+ 0x28610000,
+ 0x28420000,
+ 0x58a10000,
+ 0x28610004,
+ 0x58a10004,
+ 0x58620000,
+ 0x28a10004,
+ 0x20210100,
+ 0x58610004,
+ 0x28610004,
+ 0xd0490000,
+ 0x34010001,
+ 0xd0010000,
+ 0x78010001,
+ 0x3c820002,
+ 0x3821da6c,
+ 0xb4411000,
+ 0x28410000,
+ 0xd8200000,
+ 0x34010000,
+ 0xd0010000,
+ 0x78020001,
+ 0x3842db74,
+ 0x28430000,
+ 0xb9800800,
+ 0x38210000,
+ 0x58230000,
+ 0x28420004,
+ 0x58220004,
+ 0xe0000028,
+ 0xbba01800,
+ 0x78040001,
+ 0x78020001,
+ 0x38630000,
+ 0x3884db6c,
+ 0x3842db80,
+ 0x34050004,
+ 0x5cc0001b,
+ 0x28610000,
+ 0x28420000,
+ 0x58810000,
+ 0x28610004,
+ 0x58810004,
+ 0x58620000,
+ 0x58660004,
+ 0x28610004,
+ 0xd0450000,
+ 0x34010001,
+ 0xd0010000,
+ 0x38e7da6c,
+ 0xb5470800,
+ 0x28210000,
+ 0xd8200000,
+ 0x34010000,
+ 0xd0010000,
+ 0x78010001,
+ 0x3821db6c,
+ 0x28220000,
+ 0xb9601800,
+ 0x38630000,
+ 0x58620000,
+ 0x28210004,
+ 0x58610004,
+ 0xe0000006,
+ 0xd0450000,
+ 0x38e7da6c,
+ 0xb5470800,
+ 0x28210000,
+ 0xd8200000,
+ 0x78018001,
+ 0x38210000,
+ 0x28210058,
+ 0xe3ffff99,
+ 0xb9a01800,
+ 0x3863e028,
+ 0x40610000,
+ 0x34040001,
+ 0x3422ffff,
+ 0x202100ff,
+ 0x50810008,
+ 0x30620000,
+ 0x2b8b0010,
+ 0x2b8c000c,
+ 0x2b8d0008,
+ 0x2b9d0004,
+ 0x379c0010,
+ 0xc3a00000,
+ 0x30620000,
+ 0x204100ff,
+ 0x5c20ff7f,
+ 0x78018000,
+ 0x38210000,
+ 0x58240008,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0x34000000,
+ 0xe3ffff76,
+ 0x78060001,
+ 0x38c6f1a0,
+ 0x78050001,
+ 0x38a5d7f4,
+ 0x30c1000b,
+ 0x28a70028,
+ 0xb8202000,
+ 0x34080000,
+ 0x34030003,
+ 0x48e30009,
+ 0x28a10038,
+ 0x34220060,
+ 0x40410003,
+ 0x3442ffe0,
+ 0x5c200010,
+ 0x3463ffff,
+ 0x48e30002,
+ 0xe3fffffb,
+ 0x28a10010,
+ 0x4501000f,
+ 0x7c810010,
+ 0x5c20000b,
+ 0x40c10002,
+ 0x34020000,
+ 0x30c10008,
+ 0x40c10000,
+ 0x30c10009,
+ 0x78010001,
+ 0x3821db7c,
+ 0xe000000c,
+ 0xb8604000,
+ 0xe3fffff3,
+ 0x7c810020,
+ 0x5c20001a,
+ 0x40c10003,
+ 0x34020001,
+ 0x30c10008,
+ 0x40c10001,
+ 0x30c10009,
+ 0x78010001,
+ 0x3821db7c,
+ 0x7804e000,
+ 0x30220000,
+ 0x38842018,
+ 0x28820000,
+ 0x40c10008,
+ 0x3405ff80,
+ 0xa0451000,
+ 0x2021007f,
+ 0xb8411000,
+ 0x7803e000,
+ 0x58820000,
+ 0x38632010,
+ 0x40c20009,
+ 0x28610000,
+ 0x2042007f,
+ 0xa0250800,
+ 0xb8220800,
+ 0x58610000,
+ 0xc3a00000,
+ 0x379cfffc,
+ 0x5b9d0004,
+ 0x78010001,
+ 0x3821f150,
+ 0x40210002,
+ 0x78028000,
+ 0x78038008,
+ 0x78040001,
+ 0x38420010,
+ 0x38630000,
+ 0x3884f1a0,
+ 0x4420000a,
+ 0x28420000,
+ 0x34010000,
+ 0x58610220,
+ 0x4083000a,
+ 0x20420030,
+ 0xb8400800,
+ 0x3082000b,
+ 0x44430002,
+ 0xfbffffb0,
+ 0x2b9d0004,
+ 0x379c0004,
+ 0xc3a00000,
+ 0x379cfff4,
+ 0x5b8b000c,
+ 0x5b8c0008,
+ 0x5b9d0004,
+ 0xfbffd231,
+ 0xb8206000,
+ 0x780b0001,
+ 0xfbffd232,
+ 0x396bf1a0,
+ 0x41620007,
+ 0x78030001,
+ 0x3863db7c,
+ 0x3022000f,
+ 0x78010001,
+ 0x3182000f,
+ 0x3821f150,
+ 0x40210002,
+ 0x34020010,
+ 0x44200007,
+ 0x40610000,
+ 0x7c210001,
+ 0x5c200002,
+ 0x34020020,
+ 0xb8400800,
+ 0xfbffff94,
+ 0x2b8b000c,
+ 0x2b8c0008,
+ 0x2b9d0004,
+ 0x379c000c,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0xc3a00000,
+ 0x01300000,
+ 0x01310000,
+ 0x01310000,
+ 0x01320000,
+ 0x01330000,
+ 0x01100000,
+ 0x01110000,
+ 0x02110000,
+ 0x01120000,
+ 0x01130000,
+ 0x01200000,
+ 0x01210000,
+ 0x02210000,
+ 0x01220000,
+ 0x01230000,
+ 0x00000100,
+ 0x00000000,
+ 0x000a0003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000007,
+ 0x0001f000,
+ 0x0001f000,
+ 0x0001f000,
+ 0x000113dc,
+ 0x00011318,
+ 0x01010101,
+ 0x01010101,
+ 0x7fff0000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x000a0003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000007,
+ 0x0001f200,
+ 0x0001f200,
+ 0x0001f200,
+ 0x00011bf8,
+ 0x00011b58,
+ 0x0001f8f0,
+ 0x00015000,
+ 0x0001420c,
+ 0x00010e64,
+ 0x00011928,
+ 0x0001b748,
+ 0x0001b8dc,
+ 0x00000000,
+ 0x00017510,
+ 0x000156bc,
+ 0x00015d18,
+ 0x00016528,
+ 0x000169d0,
+ 0x00016e2c,
+ 0x000174d0,
+ 0x00012f3c,
+ 0x0001d6d4,
+ 0x0000ea60,
+ 0x00004e20,
+ 0x64000000,
+ 0x000186a0,
+ 0x0001f480,
+ 0x80402010,
+ 0x08040200,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x01010000,
+ 0x01000100,
+ 0x00000000,
+ 0x00000000,
+ 0x01010101,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x0001f120,
+ 0x00000000,
+ 0x04000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00003178,
+ 0x00000000,
+ 0x00003171,
+ 0x00000000,
+ 0x00003172,
+ 0x00000000,
+ 0x00007103,
+ 0x00000000,
+ 0x00007116,
+ 0x00000000,
+ 0x0000317d,
+ 0x00000000,
+ 0x00007103,
+ 0x00000000,
+ 0x0000712e,
+ 0x00000000,
+ 0x0000710f,
+ 0x00000000,
+ 0x00007110,
+ 0x00000000,
+ 0x00007111,
+ 0x00000000,
+ 0x00007112,
+ 0x00000000,
+ 0x00007113,
+ 0x00000000,
+ 0x0000715c,
+ 0x00000000,
+ 0x0000715d,
+ 0x00000000,
+ 0x00007162,
+ 0x00000000,
+ 0x00007117,
+ 0x00000000,
+ 0x00007157,
+ 0x00000000,
+ 0x00007106,
+ 0x00000000,
+ 0x0001ab20,
+ 0x00010788,
+ 0x0001a8d8,
+ 0x00019fec,
+ 0x0001a4a0,
+ 0x00019a00,
+ 0x0001a450,
+ 0x000199b4,
+ 0x0001a420,
+ 0x00011d94,
+ 0x00010418,
+ 0x00010430,
+ 0x00013138,
+ 0x00013d5c,
+ 0x00012398,
+ 0x00015970,
+ 0x0001244c,
+ 0x0001bb5c,
+ 0x0001b864,
+ 0x00012c48,
+ 0x00012300,
+ 0x00012354,
+ 0x00016834,
+ 0x00012530,
+ 0x00016e2c,
+ 0x0001a984,
+ 0x0001396c,
+ 0x0001aa60,
+ 0x00011e80,
+ 0x0001d380,
+ 0x00011bf8,
+ 0x00011b58,
+ 0x00014c0c,
+ 0x00014e28,
+ 0x0001a704,
+ 0x00019d34,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001c1a8,
+ 0x0001c1e0,
+ 0x00012f3c,
+ 0x0001724c,
+ 0x0001aab8,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001af7c,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001adb4,
+ 0x00012f34,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x0001d7ac,
+ 0x0001d7b0,
+ 0x00010788,
+ 0x000121b8,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00013340,
+ 0x0001420c,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00010788,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
new file mode 100644
index 0000000000..75f8c9cb56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c
@@ -0,0 +1,1121 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbTable.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbInitTN.h"
+#include  "cpuFamRegisters.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = {
+  GNB_ENTRY_RMW (
+    D0F0x98_x07_TYPE,
+    D0F0x98_x07_ADDRESS,
+    D0F0x98_x07_SMUCsrIsocEn_MASK,
+    (1 << D0F0x98_x07_SMUCsrIsocEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x1E_TYPE,
+    D0F0x98_x1E_ADDRESS,
+    D0F0x98_x1E_HiPriEn_MASK,
+    (1 << D0F0x98_x1E_HiPriEn_OFFSET)
+    ),
+
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = {
+ // Config GFX to legacy mode initially
+  GNB_ENTRY_RMW (
+    D0F0x64_x1D_TYPE,
+    D0F0x64_x1D_ADDRESS,
+    D0F0x64_x1D_IntGfxAsPcieEn_MASK,
+    0
+    ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F87C_TYPE,
+    D0F0xBC_x1F87C_ADDRESS,
+    D0F0xBC_x1F87C_LL_PCIE_LoadStep_MASK | D0F0xBC_x1F87C_LL_VddNbLoadStepBase_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F880_TYPE,
+    D0F0xBC_x1F880_ADDRESS,
+    D0F0xBC_x1F880_LL_VCE_LoadStep_MASK | D0F0xBC_x1F880_LL_UVD_LoadStep_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F884_TYPE,
+    D0F0xBC_x1F884_ADDRESS,
+    D0F0xBC_x1F884_LL_DCE2_LoadStep_MASK | D0F0xBC_x1F884_LL_DCE_LoadStep_MASK,
+    0
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F888_TYPE,
+    D0F0xBC_x1F888_ADDRESS,
+    D0F0xBC_x1F888_LL_GPU_LoadStep_MASK,
+    0
+  ),
+ // Configure load line VID
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F3D8_TYPE,
+    D0F0xBC_x1F3D8_ADDRESS,
+    (0x00 << D0F0xBC_x1F3D8_LoadLineTrim3_OFFSET) |
+    (0xFE << D0F0xBC_x1F3D8_LoadLineTrim2_OFFSET) |
+    (0xFC << D0F0xBC_x1F3D8_LoadLineTrim1_OFFSET) |
+    (0xF6 << D0F0xBC_x1F3D8_LoadLineTrim0_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F3DC_TYPE,
+    D0F0xBC_x1F3DC_ADDRESS,
+    (0x08 << D0F0xBC_x1F3DC_LoadLineTrim7_OFFSET) |
+    (0x06 << D0F0xBC_x1F3DC_LoadLineTrim6_OFFSET) |
+    (0x04 << D0F0xBC_x1F3DC_LoadLineTrim5_OFFSET) |
+    (0x02 << D0F0xBC_x1F3DC_LoadLineTrim4_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_x1F404_TYPE,
+    D0F0xBC_x1F404_ADDRESS,
+    (0x19 << D0F0xBC_x1F404_LoadLineOffset3_OFFSET) |
+    (0x00 << D0F0xBC_x1F404_LoadLineOffset2_OFFSET) |
+    (0xE7 << D0F0xBC_x1F404_LoadLineOffset1_OFFSET) |
+    (0x00 << D0F0xBC_x1F404_LoadLineOffset0_OFFSET)
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviInitLoadLineVdd_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVdd_WIDTH,
+    D0F0xBC_xE01040A8_TYPE,
+    D0F0xBC_xE01040A8_ADDRESS,
+    D0F0xBC_xE01040A8_SviLoadLineVdd_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviInitLoadLineVddNB_OFFSET, D0F0xBC_x1F3F8_SviInitLoadLineVddNB_WIDTH,
+    D0F0xBC_xE01040A8_TYPE,
+    D0F0xBC_xE01040A8_ADDRESS,
+    D0F0xBC_xE01040A8_SviLoadLineVddNb_OFFSET, D0F0xBC_xE01040A8_SviLoadLineVddNb_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVdd_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH
+  ),
+ GNB_ENTRY_COPY (
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreLoadLineTrim_OFFSET, D18F5x12C_CoreLoadLineTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET, D0F0xBC_x1F3F8_SviTrimValueVddNB_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D18F5x188_TYPE,
+    D18F5x188_ADDRESS,
+    D18F5x188_NbLoadLineTrim_OFFSET, D18F5x188_NbLoadLineTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineTrimVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineTrimVddNb_WIDTH
+  ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F3FC_TYPE,
+    D0F0xBC_x1F3FC_ADDRESS,
+    D0F0xBC_x1F3FC_SviVidStepBase_MASK | D0F0xBC_x1F3FC_SviVidStep_MASK,
+    (0x1838 << D0F0xBC_x1F3FC_SviVidStepBase_OFFSET) | (0x19 << D0F0xBC_x1F3FC_SviVidStep_OFFSET)
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVdd_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreOffsetTrim_OFFSET, D18F5x12C_CoreOffsetTrim_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVdd_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVdd_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET, D0F0xBC_x1F400_SviLoadLineOffsetVddNB_WIDTH,
+    D0F0xBC_xE0104184_TYPE,
+    D0F0xBC_xE0104184_ADDRESS,
+    D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_SviLoadLineOffsetVddNB_MASK | D0F0xBC_x1F400_SviLoadLineOffsetVdd_MASK,
+    (2 << D0F0xBC_x1F400_SviLoadLineOffsetVddNB_OFFSET) | (2 << D0F0xBC_x1F400_SviLoadLineOffsetVdd_OFFSET)
+  ),
+//  GNB_ENTRY_COPY (
+//    D18F5x188_TYPE,
+//    D18F5x188_ADDRESS,
+//    D18F5x188_NbOffsetTrim_OFFSET, D18F5x188_NbOffsetTrim_WIDTH,
+//    D0F0xBC_xE0104184_TYPE,
+//    D0F0xBC_xE0104184_ADDRESS,
+//    D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_OFFSET, D0F0xBC_xE0104184_SviLoadLineOffsetVddNb_WIDTH
+//  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D18F5x188_TYPE,
+    D18F5x188_ADDRESS,
+    D18F5x188_NbLoadLineTrim_MASK,// | D18F5x188_NbOffsetTrim_MASK,
+    (3 << D18F5x188_NbLoadLineTrim_OFFSET)// | (2 << D18F5x188_NbOffsetTrim_OFFSET)
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D18F5x12C_TYPE,
+    D18F5x12C_ADDRESS,
+    D18F5x12C_CoreLoadLineTrim_MASK | D18F5x12C_CoreOffsetTrim_MASK,
+    (3 << D18F5x12C_CoreLoadLineTrim_OFFSET) | (2 << D18F5x12C_CoreOffsetTrim_OFFSET)
+  ),
+  GNB_ENTRY_REV_RMW (
+    0x0000000000000100ull ,
+    D0F0xBC_x1F3F8_TYPE,
+    D0F0xBC_x1F3F8_ADDRESS,
+    D0F0xBC_x1F3F8_SviTrimValueVdd_MASK | D0F0xBC_x1F3F8_SviTrimValueVddNB_MASK,
+    (3 << D0F0xBC_x1F3F8_SviTrimValueVdd_OFFSET) | (3 << D0F0xBC_x1F3F8_SviTrimValueVddNB_OFFSET)
+  ),
+  // Enable SVI2
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_SviMode_MASK,
+    (1 << D0F0xBC_x1F428_SviMode_OFFSET)
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = {
+  GNB_ENTRY_WR (
+    D0F0x04_TYPE,
+    D0F0x04_ADDRESS,
+    (0x1 << D0F0x04_MemAccessEn_OFFSET) | (0x1 << D0F0x04_BusMasterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x4C_TYPE,
+    D0F0x4C_ADDRESS,
+    D0F0x4C_CfgRdTime_MASK,
+    0x2 << D0F0x4C_CfgRdTime_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x84_TYPE,
+    D0F0x84_ADDRESS,
+    D0F0x84_Ev6Mode_MASK,
+    0x1 << D0F0x84_Ev6Mode_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x64_x46_TYPE,
+    D0F0x64_x46_ADDRESS,
+    0x6 ,
+    1 << D0F0x64_x46_Msi64bitEn_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x0C_TYPE,
+    D0F0x98_x0C_ADDRESS,
+    D0F0x98_x0C_StrictSelWinnerEn_MASK,
+    1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET
+    ),
+  // Configure PM timer
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F468_TYPE,
+    D0F0xBC_x1F468_ADDRESS,
+    D0F0xBC_x1F468_TimerPeriod_MASK,
+    D0F0xBC_x1F468_TimerPeriod_Value << D0F0xBC_x1F468_TimerPeriod_OFFSET
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_EN_PM_CNTL,
+    0
+    ),
+  //Enable voltage controller
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_VoltageCntl_MASK,
+    1 << D0F0xBC_x1F460_VoltageCntl_OFFSET
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F384_TYPE,
+    D0F0xBC_x1F384_ADDRESS,
+    D0F0xBC_x1F384_FirmwareVid_OFFSET,
+    D0F0xBC_x1F384_FirmwareVid_WIDTH,
+    D0F0xBC_xE0001008_TYPE ,
+    D0F0xBC_xE0001008_ADDRESS,
+    D0F0xBC_xE0001008_SClkVid0_OFFSET,
+    D0F0xBC_xE0001008_SClkVid0_WIDTH
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_VOLTAGE_CNTL,
+    0
+    ),
+  GNB_ENTRY_POLL (
+    GMMx7B0_TYPE,
+    GMMx7B0_ADDRESS,
+    GMMx7B0_SMU_VOLTAGE_EN_MASK,
+    0x1 << GMMx7B0_SMU_VOLTAGE_EN_OFFSET
+    ),
+  // Enable thermal controller
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_ThermalCntl_MASK,
+    30 << D0F0xBC_x1F460_ThermalCntl_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F388_TYPE,
+    D0F0xBC_x1F388_ADDRESS,
+    D0F0xBC_x1F388_CsrAddr_MASK | D0F0xBC_x1F388_TcenId_MASK,
+    (0x9 << D0F0xBC_x1F388_CsrAddr_OFFSET) | (0xE << D0F0xBC_x1F388_TcenId_OFFSET)
+    ),
+  GNB_ENTRY_WR (
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_THERMAL_CNTL,
+    0
+    ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F400_TYPE,
+    D0F0xBC_x1F400_ADDRESS,
+    D0F0xBC_x1F400_PstateMax_OFFSET,
+    D0F0xBC_x1F400_PstateMax_WIDTH,
+    TYPE_D18F3 ,
+    0xdc ,
+    8 ,
+    3
+    ),
+  // Configure VPC
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableVpcAccumulators_MASK,
+    (1 << D0F0xBC_x1F428_EnableVpcAccumulators_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_PstateAllCpusIdle_MASK | D0F0xBC_x1F428_NbPstateAllCpusIdle_MASK,
+    (1 << D0F0xBC_x1F428_NbPstateAllCpusIdle_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_VpcPeriod_MASK,
+    (0x1B58 << D0F0xBC_x1F46C_VpcPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_VPC_ACCUMULATOR,
+    0
+    ),
+ // Enable TDC
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableTdcLimit_MASK,
+    (1 << D0F0xBC_x1F428_EnableTdcLimit_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F638_TYPE,
+    D0F0xBC_x1F638_ADDRESS,
+    D0F0xBC_x1F638_TdcPeriod_MASK,
+    (0x1 << D0F0xBC_x1F638_TdcPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_TDC_LIMIT,
+    0
+    ),
+
+  // Enable LPMx
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableLpmx_MASK,
+    (1 << D0F0xBC_x1F428_EnableLpmx_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_LpmxPeriod_MASK,
+    (1 << D0F0xBC_x1F46C_LpmxPeriod_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_LPMx,
+    0
+    ),
+  // Enable BAPM
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_BapmCoeffOverride_MASK,
+    (0x1 << D0F0xBC_x1F428_BapmCoeffOverride_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_BAPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableBapm_MASK,
+    (1 << D0F0xBC_x1F428_EnableBapm_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F46C_TYPE,
+    D0F0xBC_x1F46C_ADDRESS,
+    D0F0xBC_x1F46C_BapmPeriod_MASK,
+    (D0F0xBC_x1F46C_BapmPeriod_Value << D0F0xBC_x1F46C_BapmPeriod_OFFSET)
+    ),
+ // Config BAPM
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_BAPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_BAPM,
+    0
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbEnvInitTableTN [] = {
+//---------------------------------------------------------------------------
+// ORB Init
+//D0F0x98_x07[IocBwOptEn]
+//D0F0x98_x07[DropZeroMaskWrEn]
+//D0F0x98_x28[ForceCoherentIntr] = 1
+//D0F0x98_x07[UnadjustThrottlingStpclk ] = 1
+//D0F0x98_x07[MSIHTIntConversionEn] = 0
+//D0F0x98_x07[IommuBwOptEn] = 1
+//D0F0x98_x07[IommuIsocPassPWMode] = 1
+//D0F0x98_x08[NpWrrLenC] = 1
+//D0F0x98_x28[ForceCoherentIntr] = 1
+//D0F0x98_x2C[NBOutbWakeMask] = 1
+//D0F0x98_x2C[OrbRxIdlesMask] = 1
+
+  GNB_ENTRY_RMW (
+    D0F0x98_x07_TYPE,
+    D0F0x98_x07_ADDRESS,
+    D0F0x98_x07_UnadjustThrottlingStpclk_MASK | D0F0x98_x07_MSIHTIntConversionEn_MASK |
+    D0F0x98_x07_IommuBwOptEn_MASK | D0F0x98_x07_IommuIsocPassPWMode_MASK |
+    D0F0x98_x07_IocBwOptEn_MASK | D0F0x98_x07_DropZeroMaskWrEn_MASK,
+    (0x1 << D0F0x98_x07_UnadjustThrottlingStpclk_OFFSET) | (0x0 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) |
+    (0x1 << D0F0x98_x07_IommuBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_IommuIsocPassPWMode_OFFSET) |
+    (0x1 << D0F0x98_x07_IocBwOptEn_OFFSET) | (0x1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x08_TYPE,
+    D0F0x98_x08_ADDRESS,
+    D0F0x98_x08_NpWrrLenC_MASK,
+    0x1 << D0F0x98_x08_NpWrrLenC_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x28_TYPE,
+    D0F0x98_x28_ADDRESS,
+    D0F0x98_x28_ForceCoherentIntr_MASK,
+    0x1 << D0F0x98_x28_ForceCoherentIntr_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x98_x2C_TYPE,
+    D0F0x98_x2C_ADDRESS,
+    D0F0x98_x2C_NBOutbWakeMask_MASK | D0F0x98_x2C_OrbRxIdlesMask_MASK,
+    (0x1 << D0F0x98_x2C_NBOutbWakeMask_OFFSET) | (0x1 << D0F0x98_x2C_OrbRxIdlesMask_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+//IOMMU L2 Initialization
+  GNB_ENTRY_RMW (
+    D0F2xF4_x10_TYPE,
+    D0F2xF4_x10_ADDRESS,
+    D0F2xF4_x10_DTCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x10_DTCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x11_TYPE,
+    D0F2xF4_x11_ADDRESS,
+    D0F2xF4_x11_DtcAddressMask_MASK | D0F2xF4_x11_DtcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x11_DtcAddressMask_OFFSET) | (0x1 << D0F2xF4_x11_DtcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x14_TYPE,
+    D0F2xF4_x14_ADDRESS,
+    D0F2xF4_x14_ITCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x14_ITCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x15_TYPE,
+    D0F2xF4_x15_ADDRESS,
+    D0F2xF4_x15_ITCAddressMask_MASK | D0F2xF4_x15_ItcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x15_ITCAddressMask_OFFSET) | (1 << D0F2xF4_x15_ItcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x18_TYPE,
+    D0F2xF4_x18_ADDRESS,
+    D0F2xF4_x18_PTCAInvalidationSel_MASK,
+    0x2 << D0F2xF4_x18_PTCAInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x19_TYPE,
+    D0F2xF4_x19_ADDRESS,
+    D0F2xF4_x19_PTCAAddressMask_MASK | D0F2xF4_x19_PtcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x19_PTCAAddressMask_OFFSET) | (1 << D0F2xF4_x19_PtcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x30_TYPE,
+    D0F2xF4_x30_ADDRESS,
+    D0F2xF4_x30_ERRRuleLock1_MASK,
+    0x1 << D0F2xF4_x30_ERRRuleLock1_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x34_TYPE,
+    D0F2xF4_x34_ADDRESS,
+    D0F2xF4_x34_L2aregHostPgsize_MASK | D0F2xF4_x34_L2aregGstPgsize_MASK,
+    (0x2 << D0F2xF4_x34_L2aregHostPgsize_OFFSET) | (0x2 <<  D0F2xF4_x34_L2aregGstPgsize_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x47_TYPE,
+    D0F2xF4_x47_ADDRESS,
+    D0F2xF4_x47_TwAtomicFilterEn_MASK | D0F2xF4_x47_TwNwEn_MASK,
+    (0x1 << D0F2xF4_x47_TwAtomicFilterEn_OFFSET) | (1 << D0F2xF4_x47_TwNwEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x4C_TYPE,
+    D0F2xF4_x4C_ADDRESS,
+    D0F2xF4_x4C_GstPartialPtcCntrl_MASK,
+    0x3 << D0F2xF4_x4C_GstPartialPtcCntrl_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x50_TYPE,
+    D0F2xF4_x50_ADDRESS,
+    D0F2xF4_x50_PDCInvalidationSel_MASK,
+    0x2 << D0F2xF4_x50_PDCInvalidationSel_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x51_TYPE,
+    D0F2xF4_x51_ADDRESS,
+    D0F2xF4_x51_PDCAddressMask_MASK | D0F2xF4_x51_PdcAltHashEn_MASK,
+    (0x0 << D0F2xF4_x51_PDCAddressMask_OFFSET) | (1 << D0F2xF4_x51_PdcAltHashEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x56_TYPE,
+    D0F2xF4_x56_ADDRESS,
+    D0F2xF4_x56_CPFlushOnInv_MASK | D0F2xF4_x56_CPFlushOnWait_MASK,
+    (0x0 << D0F2xF4_x56_CPFlushOnInv_OFFSET) | (1 << D0F2xF4_x56_CPFlushOnWait_OFFSET)
+    ),
+
+  GNB_ENTRY_RMW (
+    D0F2xF4_x80_TYPE,
+    D0F2xF4_x80_ADDRESS,
+    D0F2xF4_x80_ERRRuleLock0_MASK,
+    0x1 << D0F2xF4_x80_ERRRuleLock0_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x90_TYPE,
+    D0F2xF4_x90_ADDRESS,
+    D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK,
+    (0x1 << D0F2xF4_x90_CKGateL2BMiscDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BDynamicDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BRegsDisable_OFFSET) | (0x1 << D0F2xF4_x90_CKGateL2BCacheDisable_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x92_TYPE,
+    D0F2xF4_x92_ADDRESS,
+    D0F2xF4_x92_PprIntcoallesceEn_MASK | D0F2xF4_x92_PprIntreqdelay_MASK | D0F2xF4_x92_PprInttimedelay_MASK,
+    (0x0 << D0F2xF4_x92_PprIntcoallesceEn_OFFSET) | (0x20 << D0F2xF4_x92_PprIntreqdelay_OFFSET) | (0x15 << D0F2xF4_x92_PprInttimedelay_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xF4_x94_TYPE,
+    D0F2xF4_x94_ADDRESS,
+    D0F2xF4_x94_L2bregHostPgsize_MASK | D0F2xF4_x94_L2bregGstPgsize_MASK,
+    (0x2 << D0F2xF4_x94_L2bregHostPgsize_OFFSET) | (0x2ull << D0F2xF4_x94_L2bregGstPgsize_OFFSET)
+    ),
+//IOMMU L1 Initialization
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x0C_L1_TYPE,
+    D0F2xFC_x0C_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x0C_L1_L1VirtOrderQueues_MASK,
+    0x4 << D0F2xFC_x0C_L1_L1VirtOrderQueues_OFFSET
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x32_L1_TYPE,
+    D0F2xFC_x32_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x32_L1_AtsMultipleL1toL2En_MASK | D0F2xFC_x32_L1_AtsMultipleRespEn_MASK | D0F2xFC_x32_L1_TimeoutPulseExtEn_MASK,
+    (0x1 << D0F2xFC_x32_L1_AtsMultipleL1toL2En_OFFSET) | (0x1 << D0F2xFC_x32_L1_AtsMultipleRespEn_OFFSET) | (0x1 << D0F2xFC_x32_L1_TimeoutPulseExtEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F2xFC_x07_L1_TYPE,
+    D0F2xFC_x07_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x07_L1_L1NwEn_MASK | D0F2xFC_x07_L1_AtsPhysPageOverlapDis_MASK |
+    D0F2xFC_x07_L1_AtsSeqNumEn_MASK | D0F2xFC_x07_L1_SpecReqFilterEn_MASK,
+    (0x1 << D0F2xFC_x07_L1_L1NwEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_AtsPhysPageOverlapDis_OFFSET) |
+    (0x1 << D0F2xFC_x07_L1_AtsSeqNumEn_OFFSET) | (0x1 << D0F2xFC_x07_L1_SpecReqFilterEn_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// IOMMU Initialization
+  GNB_ENTRY_RMW (
+    D0F2x70_TYPE,
+    D0F2x70_ADDRESS,
+    D0F2x70_PcSupW_MASK,
+    (0x0 << D0F2x70_PcSupW_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0x64_x0D_TYPE,
+    D0F0x64_x0D_ADDRESS,
+    D0F0x64_x0D_PciDev0Fn2RegEn_MASK,
+    (0x1 << D0F0x64_x0D_PciDev0Fn2RegEn_OFFSET)
+    ),
+// IOMMU L2 clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING,
+    D0F2xF4_x33_TYPE,
+    D0F2xF4_x33_ADDRESS,
+    D0F2xF4_x33_CKGateL2ARegsDisable_MASK | D0F2xF4_x33_CKGateL2ADynamicDisable_MASK | D0F2xF4_x33_CKGateL2ACacheDisable_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING,
+    D0F2xF4_x90_TYPE,
+    D0F2xF4_x90_ADDRESS,
+    D0F2xF4_x90_CKGateL2BRegsDisable_MASK | D0F2xF4_x90_CKGateL2BDynamicDisable_MASK | D0F2xF4_x90_CKGateL2BMiscDisable_MASK | D0F2xF4_x90_CKGateL2BCacheDisable_MASK,
+    0x0
+    ),
+// IOMMU L1 clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GFX),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GPPSB),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_GBIF),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING,
+    D0F2xFC_x33_L1_TYPE,
+    D0F2xFC_x33_L1_ADDRESS (L1_SEL_INTGEN),
+    D0F2xFC_x33_L1_L1DmaClkgateEn_MASK | D0F2xFC_x33_L1_L1CacheClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1CpslvClkgateEn_MASK | D0F2xFC_x33_L1_L1DmaInputClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1PerfClkgateEn_MASK | D0F2xFC_x33_L1_L1MemoryClkgateEn_MASK |
+    D0F2xFC_x33_L1_L1RegClkgateEn_MASK | D0F2xFC_x33_L1_L1L2ClkgateEn_MASK,
+    (0x1 << D0F2xFC_x33_L1_L1DmaClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1CacheClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1CpslvClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1DmaInputClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1PerfClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1MemoryClkgateEn_OFFSET) |
+    (0x1 << D0F2xFC_x33_L1_L1RegClkgateEn_OFFSET) | (0x1 << D0F2xFC_x33_L1_L1L2ClkgateEn_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// Configure IOMMU Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030001C_TYPE,
+    D0F0xBC_xE030001C_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_WriteOp_OFFSET) |
+    (1  << D0F0xBC_xE0300018_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    0x0
+    ),
+// Hide IOMMU function if disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0x64_x0D_TYPE,
+    D0F0x64_x0D_ADDRESS,
+    D0F0x64_x0D_PciDev0Fn2RegEn_MASK,
+    0x0
+    ),
+  //NB P-state Configuration for Runtime
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_NBDPM,
+    D0F0xBC_x1F428_TYPE,
+    D0F0xBC_x1F428_ADDRESS,
+    D0F0xBC_x1F428_EnableNbDpm_MASK,
+    (1 << D0F0xBC_x1F428_EnableNbDpm_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F638_TYPE,
+    D0F0xBC_x1F638_ADDRESS,
+    D0F0xBC_x1F638_NbdpmPeriod_MASK | D0F0xBC_x1F638_PginterlockPeriod_MASK,
+    (1 << D0F0xBC_x1F638_NbdpmPeriod_OFFSET) | (1 << D0F0xBC_x1F638_PginterlockPeriod_OFFSET)
+    ),
+
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Dpm0PgNbPsLo_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsLo_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Dpm0PgNbPsHi_OFFSET, D0F0xBC_x1F5F8_Dpm0PgNbPsHi_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_DpmXNbPsLo_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsLo_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateLo_OFFSET, D0F0xBC_xE010703C_NbPstateLo_WIDTH
+  ),
+  GNB_ENTRY_COPY (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_DpmXNbPsHi_OFFSET, D0F0xBC_x1F5F8_DpmXNbPsHi_WIDTH,
+    D0F0xBC_xE010703C_TYPE,
+    D0F0xBC_xE010703C_ADDRESS,
+    D0F0xBC_xE010703C_NbPstateHi_OFFSET, D0F0xBC_xE010703C_NbPstateHi_WIDTH
+  ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F5F8_TYPE,
+    D0F0xBC_x1F5F8_ADDRESS,
+    D0F0xBC_x1F5F8_Hysteresis_MASK | D0F0xBC_x1F5F8_SkipDPM0_MASK |
+    D0F0xBC_x1F5F8_SkipPG_MASK | D0F0xBC_x1F5F8_EnableNbPsi1_MASK | D0F0xBC_x1F5F8_EnableDpmPstatePoll_MASK,
+    (10 << D0F0xBC_x1F5F8_Hysteresis_OFFSET) | (1 << D0F0xBC_x1F5F8_SkipDPM0_OFFSET) |
+    (1 << D0F0xBC_x1F5F8_EnableNbPsi1_OFFSET) | (1 << D0F0xBC_x1F5F8_EnableDpmPstatePoll_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F6E4_TYPE,
+    D0F0xBC_x1F6E4_ADDRESS,
+    D0F0xBC_x1F6E4_DdrVoltFloor_MASK | D0F0xBC_x1F6E4_BapmDdrVoltFloor_MASK,
+    (0xFF << D0F0xBC_x1F6E4_DdrVoltFloor_OFFSET) | (0xFF << D0F0xBC_x1F6E4_BapmDdrVoltFloor_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_NBDPM,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_NBDPM,
+    0
+    ),
+
+//---------------------------------------------------------------------------
+// Configure PCIe Power Island
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    (10 << 0 ) | (50 << 8 ) |
+    (5 << 16 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) |
+    (2  << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    (50 << 0 ) | (50 << 12 )
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) |
+    (3  << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE0300010_TYPE,
+    D0F0xBC_xE0300010_ADDRESS,
+    0x0
+    ),
+  GNB_ENTRY_WR (
+    D0F0xBC_xE030000C_TYPE,
+    D0F0xBC_xE030000C_ADDRESS,
+    (0xff << D0F0xBC_xE030000C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030000C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030000C_RegAddr_OFFSET)
+    ),
+  GNB_ENTRY_STALL (1),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LOADLINE_ENABLE,
+    TYPE_D0F0xBC ,
+    0x1f428 ,
+    0x40 ,
+    (1 << 6 )
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_LOADLINE_ENABLE,
+    SMU_MSG_TYPE,
+    SMC_MSG_CONFIG_LOADLINE,
+    0
+    ),
+  GNB_ENTRY_TERMINATE
+};
+
+GNB_TABLE ROMDATA GnbMidInitTableTN [] = {
+//---------------------------------------------------------------------------
+// Enable LCLK Deep Sleep
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LCLK_DEEP_SLEEP,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_DivId_MASK | GMMx7A0_RampDis_MASK | GMMx7A0_Hysteresis_MASK | GMMx7A0_SclkRunningMask_MASK | GMMx7A0_SmuBusyMask_MASK | GMMx7A0_PcieLclkIdle1Mask_MASK | GMMx7A0_PcieLclkIdle2Mask_MASK | GMMx7A0_L1imugfxIdleMask_MASK | GMMx7A0_L1imugppsbIdleMask_MASK | GMMx7A0_L1imubifIdleMask_MASK | GMMx7A0_L1imuintgenIdleMask_MASK | GMMx7A0_L2imuIdleMask_MASK | GMMx7A0_OrbIdleMask_MASK | GMMx7A0_OnInbWakeMask_MASK | GMMx7A0_OnInbWakeAckMask_MASK | GMMx7A0_OnOutbWakeMask_MASK | GMMx7A0_OnOutbWakeAckMask_MASK | GMMx7A0_DmaactiveMask_MASK,
+    (0x5 << GMMx7A0_DivId_OFFSET) | (0x0 << GMMx7A0_RampDis_OFFSET) | (0xF << GMMx7A0_Hysteresis_OFFSET) | (0x1 << GMMx7A0_SclkRunningMask_OFFSET) | (0x1 << GMMx7A0_SmuBusyMask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle1Mask_OFFSET) | (0x1 << GMMx7A0_PcieLclkIdle2Mask_OFFSET) | (0x1 << GMMx7A0_L1imugfxIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imugppsbIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imubifIdleMask_OFFSET) | (0x1 << GMMx7A0_L1imuintgenIdleMask_OFFSET) | (0x1 << GMMx7A0_L2imuIdleMask_OFFSET) | (0x1 << GMMx7A0_OrbIdleMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnInbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeMask_OFFSET) | (0x1 << GMMx7A0_OnOutbWakeAckMask_OFFSET) | (0x1 << GMMx7A0_DmaactiveMask_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IGFX_DISABLED,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_SclkRunningMask_MASK,
+    0x0
+    ),
+// Reset : 0, Enable : 1
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_LCLK_DEEP_SLEEP,
+    TYPE_GMM,
+    GMMx7A0_ADDRESS,
+    GMMx7A0_EnableDs_MASK,
+    (0x1 << GMMx7A0_EnableDs_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// LCLK DPM init
+  GNB_ENTRY_RMW (
+    D0F0xBC_xE0000120_TYPE,
+    D0F0xBC_xE0000120_ADDRESS,
+    D0F0xBC_xE0000120_BusyCntSel_MASK | D0F0xBC_xE0000120_ActivityCntRst_MASK |
+    D0F0xBC_xE0000120_PeriodCntRst_MASK | D0F0xBC_xE0000120_EnOrbUsCnt_MASK |
+    D0F0xBC_xE0000120_EnOrbDsCnt_MASK,
+    (0x3 << D0F0xBC_xE0000120_BusyCntSel_OFFSET) | (0 << D0F0xBC_xE0000120_ActivityCntRst_OFFSET) |
+    (0x0 << D0F0xBC_xE0000120_PeriodCntRst_OFFSET) | (0x1 << D0F0xBC_xE0000120_EnOrbUsCnt_OFFSET) |
+    (0x1 << D0F0xBC_xE0000120_EnOrbDsCnt_OFFSET)
+    ),
+  //Programming Lclk Thermal Throttling Threshold in GnbLclkDpmInitTN()
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F308_TYPE,
+    D0F0xBC_x1F308_ADDRESS,
+    D0F0xBC_x1F308_LclkThermalThrottlingEn_MASK,
+    (0x1 << D0F0xBC_x1F308_LclkThermalThrottlingEn_OFFSET)
+    ),
+  GNB_ENTRY_RMW (
+    D0F0xBC_x1F460_TYPE,
+    D0F0xBC_x1F460_ADDRESS,
+    D0F0xBC_x1F460_LclkDpm_MASK,
+    (0x1 << D0F0xBC_x1F460_LclkDpm_OFFSET)
+    ),
+//---------------------------------------------------------------------------
+// ORB clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_ORB_CLK_GATING,
+    D0F0x98_x49_TYPE,
+    D0F0x98_x49_ADDRESS,
+    D0F0x98_x49_SoftOverrideClk6_MASK | D0F0x98_x49_SoftOverrideClk5_MASK | D0F0x98_x49_SoftOverrideClk4_MASK | D0F0x98_x49_SoftOverrideClk3_MASK | D0F0x98_x49_SoftOverrideClk2_MASK | D0F0x98_x49_SoftOverrideClk1_MASK | D0F0x98_x49_SoftOverrideClk0_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_ORB_CLK_GATING,
+    D0F0x98_x4A_TYPE,
+    D0F0x98_x4A_ADDRESS,
+    D0F0x98_x4A_SoftOverrideClk6_MASK | D0F0x98_x4A_SoftOverrideClk5_MASK | D0F0x98_x4A_SoftOverrideClk4_MASK | D0F0x98_x4A_SoftOverrideClk3_MASK | D0F0x98_x4A_SoftOverrideClk2_MASK | D0F0x98_x4A_SoftOverrideClk1_MASK | D0F0x98_x4A_SoftOverrideClk0_MASK,
+    (1 << D0F0x98_x4A_SoftOverrideClk0_OFFSET)
+    ),
+
+//---------------------------------------------------------------------------
+// IOC clock gating
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING,
+    D0F0x64_x22_TYPE,
+    D0F0x64_x22_ADDRESS,
+    D0F0x64_x22_SoftOverrideClk4_MASK | D0F0x64_x22_SoftOverrideClk3_MASK | D0F0x64_x22_SoftOverrideClk2_MASK | D0F0x64_x22_SoftOverrideClk1_MASK | D0F0x64_x22_SoftOverrideClk0_MASK,
+    0x0
+    ),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOC_LCLK_CLOCK_GATING,
+    D0F0x64_x23_TYPE,
+    D0F0x64_x23_ADDRESS,
+    D0F0x64_x23_SoftOverrideClk4_MASK | D0F0x64_x23_SoftOverrideClk3_MASK | D0F0x64_x23_SoftOverrideClk2_MASK | D0F0x64_x23_SoftOverrideClk1_MASK | D0F0x64_x23_SoftOverrideClk0_MASK,
+    0x0
+    ),
+
+//---------------------------------------------------------------------------
+// Shutdown IOMMU if disabled
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    1 << D0F0xBC_xE0300320_IommuPgfsmClockEn_OFFSET
+    ),
+  GNB_ENTRY_PROPERTY_WR (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300018_TYPE,
+    D0F0xBC_xE0300018_ADDRESS,
+    (0xff << D0F0xBC_xE0300018_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300018_PowerDown_OFFSET) |
+    (1 << D0F0xBC_xE0300018_P1Select_OFFSET) | (1 << D0F0xBC_xE0300018_P2Select_OFFSET)
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300208_TYPE,
+    0xe0300208 ,
+    D0F0xBC_xE0300208_P1IsoN_MASK,
+    0 << D0F0xBC_xE0300208_P1IsoN_OFFSET
+    ),
+  GNB_ENTRY_PROPERTY_POLL (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    TYPE_D0F0xBC ,
+    0xe0300208 ,
+    0x2000 ,
+    1 << 13
+    ),
+  GNB_ENTRY_STALL (10),
+  GNB_ENTRY_PROPERTY_RMW (
+    TABLE_PROPERTY_IOMMU_DISABLED,
+    D0F0xBC_xE0300320_TYPE,
+    D0F0xBC_xE0300320_ADDRESS,
+    D0F0xBC_xE0300320_IommuPgfsmClockEn_MASK,
+    0x0
+    ),
+//---------------------------------------------------------------------------
+  GNB_ENTRY_TERMINATE
+};
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
new file mode 100644
index 0000000000..f3bf14af5a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
@@ -0,0 +1,242 @@
+/**
+ * @file
+ *
+ * ALIB SSDT table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63659 $   @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBSSDTTNFM2_H_
+#define _PCIEALIBSSDTTNFM2_H_
+
+UINT8  AlibSsdtTNFM2[] = {
+  0x53, 0x53, 0x44, 0x54, 0x1F, 0x05, 0x00, 0x00,
+  0x02, 0xE2, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+  0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
+  0x00, 0x00, 0x00, 0x04, 0x10, 0x4A, 0x4F, 0x5C,
+  0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, 0x30,
+  0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, 0x31,
+  0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, 0x44,
+  0x30, 0x31, 0x41, 0x30, 0x31, 0x33, 0x14, 0x31,
+  0x41, 0x30, 0x30, 0x36, 0x0A, 0x72, 0x41, 0x30,
+  0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C, 0x00, 0x60,
+  0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, 0x30,
+  0x31, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, 0x81,
+  0x0B, 0x41, 0x30, 0x31, 0x34, 0x03, 0x41, 0x30,
+  0x31, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x31, 0x35,
+  0x14, 0x32, 0x41, 0x30, 0x30, 0x37, 0x0B, 0x72,
+  0x41, 0x30, 0x31, 0x33, 0x79, 0x68, 0x0A, 0x0C,
+  0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80,
+  0x41, 0x30, 0x31, 0x34, 0x00, 0x60, 0x0A, 0x04,
+  0x5B, 0x81, 0x0B, 0x41, 0x30, 0x31, 0x34, 0x03,
+  0x41, 0x30, 0x31, 0x35, 0x20, 0x70, 0x6A, 0x41,
+  0x30, 0x31, 0x35, 0x14, 0x1C, 0x41, 0x30, 0x31,
+  0x36, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x36, 0x68,
+  0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B,
+  0x60, 0x41, 0x30, 0x30, 0x37, 0x68, 0x69, 0x60,
+  0x5B, 0x01, 0x41, 0x30, 0x31, 0x37, 0x00, 0x14,
+  0x32, 0x41, 0x30, 0x31, 0x38, 0x02, 0x5B, 0x23,
+  0x41, 0x30, 0x31, 0x37, 0xFF, 0xFF, 0x70, 0x79,
+  0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00,
+  0x60, 0x41, 0x30, 0x30, 0x37, 0x60, 0x0A, 0xE0,
+  0x69, 0x70, 0x41, 0x30, 0x30, 0x36, 0x60, 0x0A,
+  0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x31, 0x37,
+  0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x31, 0x39,
+  0x03, 0x5B, 0x23, 0x41, 0x30, 0x31, 0x37, 0xFF,
+  0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00,
+  0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30, 0x37,
+  0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30, 0x37,
+  0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, 0x30,
+  0x31, 0x37, 0x14, 0x1C, 0x41, 0x30, 0x32, 0x30,
+  0x04, 0x70, 0x41, 0x30, 0x31, 0x38, 0x68, 0x69,
+  0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, 0x60,
+  0x41, 0x30, 0x31, 0x39, 0x68, 0x69, 0x60, 0x5B,
+  0x01, 0x41, 0x30, 0x32, 0x31, 0x00, 0x14, 0x29,
+  0x41, 0x30, 0x30, 0x38, 0x03, 0x5B, 0x23, 0x41,
+  0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41, 0x30, 0x30,
+  0x37, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, 0x60,
+  0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0xA4, 0x60,
+  0x14, 0x26, 0x41, 0x30, 0x31, 0x32, 0x04, 0x5B,
+  0x23, 0x41, 0x30, 0x32, 0x31, 0xFF, 0xFF, 0x41,
+  0x30, 0x30, 0x37, 0x68, 0x69, 0x6A, 0x41, 0x30,
+  0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00,
+  0x6B, 0x5B, 0x27, 0x41, 0x30, 0x32, 0x31, 0x14,
+  0x1E, 0x41, 0x30, 0x32, 0x32, 0x05, 0x70, 0x41,
+  0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x60, 0x7D,
+  0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, 0x30,
+  0x31, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, 0x42,
+  0x05, 0x41, 0x30, 0x32, 0x33, 0x02, 0x70, 0x0A,
+  0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x60,
+  0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, 0x7B,
+  0x41, 0x30, 0x30, 0x36, 0x68, 0x61, 0x0A, 0xFF,
+  0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A, 0x00,
+  0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, 0x30,
+  0x36, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, 0x70,
+  0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, 0xA4,
+  0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x32, 0x34,
+  0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, 0x01,
+  0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, 0x10,
+  0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, 0x52,
+  0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, 0x5B,
+  0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, 0x4D,
+  0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, 0x42,
+  0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, 0x46,
+  0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, 0x08,
+  0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, 0x03,
+  0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, 0x44,
+  0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, 0x17,
+  0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, 0x00,
+  0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, 0x41,
+  0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, 0x22,
+  0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, 0x42,
+  0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, 0x60,
+  0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, 0xFF,
+  0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, 0x44,
+  0x41, 0x08, 0x41, 0x30, 0x32, 0x35, 0x11, 0x04,
+  0x0B, 0x00, 0x01, 0x14, 0x46, 0x08, 0x41, 0x30,
+  0x30, 0x39, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B,
+  0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00,
+  0x0A, 0x02, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x00, 0x30, 0x00, 0xE0,
+  0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0xFE,
+  0xFF, 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0A, 0x01,
+  0x00, 0x00, 0x0A, 0x01, 0x00, 0x60, 0x7D, 0x60,
+  0x79, 0x68, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30,
+  0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00,
+  0x30, 0x00, 0xE0, 0x60, 0xA2, 0x16, 0x92, 0x93,
+  0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x01,
+  0x00, 0x0A, 0x01, 0xA2, 0x16, 0x92, 0x93, 0x7B,
+  0x41, 0x30, 0x30, 0x38, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x04, 0x30, 0x00, 0xE0, 0x0A, 0x02, 0x00,
+  0x0A, 0x02, 0x08, 0x41, 0x30, 0x30, 0x32, 0x0A,
+  0x00, 0x08, 0x41, 0x30, 0x30, 0x33, 0x0A, 0x00,
+  0x08, 0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x14,
+  0x46, 0x0B, 0x41, 0x30, 0x30, 0x35, 0x01, 0x70,
+  0x7D, 0x79, 0x0A, 0x18, 0x0A, 0x03, 0x00, 0x0A,
+  0x04, 0x00, 0x62, 0xA0, 0x1C, 0x93, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x62, 0x0B, 0x24, 0x01, 0x41, 0x30, 0x30,
+  0x33, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x34,
+  0x70, 0x41, 0x30, 0x30, 0x36, 0x62, 0x0B, 0x24,
+  0x01, 0x63, 0xA0, 0x13, 0x93, 0x68, 0x0A, 0x00,
+  0x7D, 0x63, 0x7B, 0x41, 0x30, 0x30, 0x33, 0x0C,
+  0x00, 0x00, 0x40, 0x00, 0x00, 0x63, 0xA1, 0x09,
+  0x7B, 0x63, 0x0C, 0xFF, 0xFF, 0xBF, 0xFF, 0x63,
+  0x41, 0x30, 0x30, 0x37, 0x62, 0x0B, 0x24, 0x01,
+  0x63, 0xA0, 0x36, 0x93, 0x41, 0x30, 0x30, 0x32,
+  0x0A, 0x00, 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x08, 0x0A, 0x00, 0x0C, 0xFF, 0xFF,
+  0xFF, 0xFF, 0x7B, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00,
+  0x0A, 0x02, 0x61, 0xA0, 0x0C, 0x93, 0x61, 0x0A,
+  0x02, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x30, 0x32,
+  0xA0, 0x1D, 0x93, 0x41, 0x30, 0x30, 0x32, 0x0A,
+  0x01, 0xA0, 0x09, 0x93, 0x68, 0x0A, 0x00, 0x70,
+  0x0A, 0x20, 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x21,
+  0x60, 0x41, 0x30, 0x30, 0x39, 0x60, 0x08, 0x41,
+  0x30, 0x31, 0x30, 0x0A, 0x00, 0x08, 0x41, 0x30,
+  0x31, 0x31, 0x0A, 0x00, 0x14, 0x48, 0x07, 0x41,
+  0x57, 0x41, 0x4B, 0x01, 0xA0, 0x40, 0x07, 0x93,
+  0x68, 0x0A, 0x03, 0xA0, 0x2E, 0x93, 0x41, 0x30,
+  0x31, 0x30, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x60, 0x41,
+  0x30, 0x30, 0x37, 0x0A, 0xC5, 0x0B, 0x70, 0x01,
+  0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01, 0x0A, 0x0E,
+  0x00, 0x00, 0x00, 0x70, 0x0A, 0x00, 0x41, 0x30,
+  0x31, 0x30, 0xA0, 0x3A, 0x93, 0x41, 0x30, 0x31,
+  0x31, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01,
+  0x00, 0x60, 0x41, 0x30, 0x31, 0x32, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00, 0x7D,
+  0x60, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00,
+  0x41, 0x30, 0x30, 0x39, 0x0A, 0x16, 0x70, 0x0A,
+  0x00, 0x41, 0x30, 0x31, 0x31, 0x14, 0x49, 0x08,
+  0x41, 0x50, 0x54, 0x53, 0x01, 0xA0, 0x41, 0x08,
+  0x93, 0x68, 0x0A, 0x03, 0x41, 0x30, 0x30, 0x35,
+  0x0A, 0x01, 0x70, 0x41, 0x30, 0x30, 0x38, 0x0A,
+  0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01, 0x00,
+  0x60, 0xA0, 0x33, 0x92, 0x93, 0x7B, 0x60, 0x79,
+  0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x28, 0xF4, 0x01, 0x00, 0x7B, 0x60, 0x80,
+  0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x00, 0x00,
+  0x41, 0x30, 0x30, 0x39, 0x0A, 0x16, 0x70, 0x0A,
+  0x01, 0x41, 0x30, 0x31, 0x31, 0x70, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x60,
+  0xA0, 0x26, 0x93, 0x7B, 0x60, 0x79, 0x0A, 0x01,
+  0x0A, 0x0E, 0x00, 0x00, 0x0A, 0x00, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0xC5, 0x0B, 0x70, 0x01, 0x7D,
+  0x60, 0x79, 0x0A, 0x01, 0x0A, 0x0E, 0x00, 0x00,
+  0x70, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x30
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
new file mode 100644
index 0000000000..e9776d0be3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
@@ -0,0 +1,1065 @@
+/**
+ * @file
+ *
+ * ALIB SSDT table
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65976 $   @e \$Date: 2012-02-27 22:24:12 -0600 (Mon, 27 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
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+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIEALIBSSDTTNFS1_H_
+#define _PCIEALIBSSDTTNFS1_H_
+
+UINT8  AlibSsdtTNFS1[] = {
+  0x53, 0x53, 0x44, 0x54, 0xD4, 0x1E, 0x00, 0x00,
+  0x02, 0x5C, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+  0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
+  0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
+  0x00, 0x00, 0x00, 0x04, 0x10, 0x8F, 0xEA, 0x01,
+  0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30,
+  0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30,
+  0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x32,
+  0x41, 0x30, 0x32, 0x39, 0x08, 0x41, 0x44, 0x30,
+  0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x33,
+  0x41, 0x30, 0x33, 0x30, 0x08, 0x41, 0x44, 0x30,
+  0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x34,
+  0x41, 0x30, 0x33, 0x31, 0x08, 0x41, 0x44, 0x30,
+  0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x35,
+  0x41, 0x30, 0x33, 0x32, 0x08, 0x41, 0x44, 0x30,
+  0x36, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
+  0x36, 0x41, 0x30, 0x33, 0x33, 0x08, 0x41, 0x44,
+  0x30, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44,
+  0x30, 0x38, 0x41, 0x30, 0x33, 0x34, 0x08, 0x41,
+  0x30, 0x33, 0x35, 0x0A, 0x00, 0x08, 0x41, 0x30,
+  0x33, 0x36, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33,
+  0x37, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x33, 0x38,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33, 0x39,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x30,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x30, 0x39,
+  0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x39,
+  0x41, 0x30, 0x31, 0x39, 0x08, 0x41, 0x30, 0x34,
+  0x31, 0x12, 0x12, 0x08, 0x0A, 0x01, 0x0A, 0x01,
+  0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01,
+  0x0A, 0x01, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x34,
+  0x32, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+  0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31,
+  0x37, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x31, 0x30,
+  0x12, 0x0A, 0x04, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x31, 0x30,
+  0x41, 0x30, 0x34, 0x34, 0x14, 0x44, 0x09, 0x41,
+  0x30, 0x34, 0x35, 0x09, 0x70, 0x83, 0x88, 0x68,
+  0x0A, 0x02, 0x00, 0x61, 0x70, 0x41, 0x30, 0x30,
+  0x33, 0x60, 0x70, 0x61, 0x41, 0x30, 0x33, 0x36,
+  0x7D, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x79,
+  0x0A, 0x01, 0x0A, 0x06, 0x00, 0x62, 0x7D, 0x79,
+  0x41, 0x30, 0x33, 0x36, 0x0A, 0x05, 0x00, 0x79,
+  0x41, 0x30, 0x33, 0x37, 0x0A, 0x06, 0x00, 0x63,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0x60,
+  0x0A, 0xF4, 0x80, 0x62, 0x00, 0x7B, 0x62, 0x63,
+  0x00, 0xA0, 0x07, 0x93, 0x61, 0x60, 0xA4, 0x0A,
+  0x00, 0x41, 0x30, 0x31, 0x33, 0x41, 0x30, 0x33,
+  0x36, 0xA0, 0x0E, 0x93, 0x41, 0x30, 0x32, 0x39,
+  0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01,
+  0xA0, 0x15, 0x91, 0x92, 0x94, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x04, 0xA4, 0x0A, 0x00, 0xA0, 0x0B,
+  0x93, 0x41, 0x30, 0x33, 0x35, 0x0A, 0x00, 0xA4,
+  0x0A, 0x00, 0x41, 0x30, 0x34, 0x36, 0xA4, 0x0A,
+  0x00, 0x14, 0x24, 0x41, 0x30, 0x34, 0x37, 0x01,
+  0x70, 0x41, 0x30, 0x34, 0x38, 0x68, 0x67, 0x70,
+  0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x60, 0xA0,
+  0x08, 0x92, 0x93, 0x60, 0x0A, 0x02, 0xA4, 0x67,
+  0x41, 0x30, 0x34, 0x36, 0xA4, 0x67, 0x14, 0x4E,
+  0x1B, 0x41, 0x30, 0x34, 0x38, 0x01, 0x08, 0x41,
+  0x30, 0x34, 0x39, 0x0A, 0x00, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x37, 0x70, 0x11, 0x03, 0x0A,
+  0x0A, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30,
+  0x35, 0x30, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x35,
+  0x30, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x35,
+  0x31, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x35, 0x31,
+  0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x32,
+  0x39, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, 0x93,
+  0x41, 0x30, 0x33, 0x35, 0x0A, 0x00, 0xA4, 0x67,
+  0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x35, 0x32,
+  0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x35, 0x33,
+  0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, 0x34,
+  0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x35, 0x35,
+  0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x35, 0x36,
+  0x7B, 0x7A, 0x41, 0x30, 0x35, 0x32, 0x0A, 0x08,
+  0x00, 0x0A, 0xFF, 0x41, 0x30, 0x34, 0x39, 0xA2,
+  0x47, 0x05, 0x92, 0x94, 0x41, 0x30, 0x31, 0x37,
+  0x41, 0x30, 0x30, 0x31, 0xA0, 0x45, 0x04, 0x93,
+  0x41, 0x30, 0x31, 0x38, 0x41, 0x30, 0x31, 0x37,
+  0x0A, 0x01, 0x70, 0x41, 0x30, 0x31, 0x34, 0x79,
+  0x72, 0x41, 0x30, 0x31, 0x37, 0x0A, 0x02, 0x00,
+  0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, 0x7A,
+  0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, 0x7B,
+  0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x61,
+  0xA0, 0x11, 0x90, 0x92, 0x95, 0x41, 0x30, 0x34,
+  0x39, 0x61, 0x92, 0x94, 0x41, 0x30, 0x34, 0x39,
+  0x62, 0xA5, 0x75, 0x41, 0x30, 0x31, 0x37, 0xA0,
+  0x0C, 0x94, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30,
+  0x30, 0x31, 0xA4, 0x67, 0xA0, 0x1E, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x38, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x35,
+  0x32, 0x88, 0x41, 0x30, 0x33, 0x38, 0x41, 0x30,
+  0x31, 0x37, 0x00, 0xA1, 0x16, 0xA0, 0x14, 0x92,
+  0x93, 0x83, 0x88, 0x41, 0x30, 0x33, 0x38, 0x41,
+  0x30, 0x31, 0x37, 0x00, 0x41, 0x30, 0x35, 0x32,
+  0xA4, 0x67, 0x70, 0x0A, 0x00, 0x88, 0x41, 0x30,
+  0x34, 0x32, 0x41, 0x30, 0x31, 0x37, 0x00, 0xA0,
+  0x15, 0x93, 0x41, 0x30, 0x35, 0x36, 0x0A, 0x00,
+  0x70, 0x0A, 0x00, 0x88, 0x41, 0x30, 0x33, 0x38,
+  0x41, 0x30, 0x31, 0x37, 0x00, 0xA0, 0x15, 0x93,
+  0x41, 0x30, 0x35, 0x36, 0x0A, 0x01, 0x70, 0x0A,
+  0x01, 0x88, 0x41, 0x30, 0x34, 0x32, 0x41, 0x30,
+  0x31, 0x37, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30,
+  0x35, 0x36, 0x0A, 0x02, 0x70, 0x0A, 0x01, 0x88,
+  0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x31, 0x37,
+  0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x35, 0x36,
+  0x0A, 0x03, 0x70, 0x0A, 0x02, 0x88, 0x41, 0x30,
+  0x34, 0x30, 0x41, 0x30, 0x31, 0x37, 0x00, 0xA0,
+  0x24, 0x93, 0x7B, 0x41, 0x30, 0x35, 0x33, 0x41,
+  0x30, 0x35, 0x34, 0x00, 0x0A, 0x01, 0x70, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x33, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x88, 0x41, 0x30, 0x34, 0x30, 0x41,
+  0x30, 0x31, 0x37, 0x00, 0x70, 0x0A, 0x02, 0x41,
+  0x30, 0x35, 0x31, 0xA4, 0x67, 0x14, 0x19, 0x41,
+  0x30, 0x31, 0x38, 0x09, 0xA0, 0x0F, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x33, 0x68, 0x00, 0x0A,
+  0x00, 0xA4, 0x0A, 0x00, 0xA4, 0x0A, 0x01, 0x14,
+  0x4F, 0x13, 0x41, 0x30, 0x35, 0x37, 0x09, 0x70,
+  0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x70, 0x0A,
+  0x03, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x70, 0x0A,
+  0x00, 0x88, 0x67, 0x0A, 0x01, 0x00, 0x70, 0x0A,
+  0x00, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x70, 0x83,
+  0x88, 0x68, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x33,
+  0x35, 0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00,
+  0x0A, 0x60, 0x0A, 0xF4, 0x60, 0xA0, 0x19, 0x93,
+  0x41, 0x30, 0x33, 0x35, 0x0A, 0x01, 0xA0, 0x0B,
+  0x93, 0x7B, 0x60, 0x0A, 0x01, 0x00, 0x0A, 0x01,
+  0xA4, 0x67, 0x7D, 0x60, 0x0A, 0x01, 0x60, 0xA0,
+  0x1B, 0x93, 0x41, 0x30, 0x33, 0x35, 0x0A, 0x00,
+  0xA0, 0x0B, 0x93, 0x7B, 0x60, 0x0A, 0x01, 0x00,
+  0x0A, 0x00, 0xA4, 0x67, 0x7B, 0x60, 0x80, 0x0A,
+  0x01, 0x00, 0x60, 0x7D, 0x60, 0x79, 0x41, 0x30,
+  0x32, 0x39, 0x0A, 0x01, 0x00, 0x60, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xF4,
+  0x60, 0x41, 0x30, 0x35, 0x38, 0x71, 0x41, 0x30,
+  0x33, 0x39, 0x71, 0x41, 0x30, 0x33, 0x38, 0x41,
+  0x30, 0x31, 0x33, 0x41, 0x30, 0x33, 0x36, 0xA0,
+  0x0E, 0x93, 0x41, 0x30, 0x32, 0x39, 0x0A, 0x04,
+  0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, 0xA0, 0x4E,
+  0x08, 0x90, 0x94, 0x41, 0x30, 0x32, 0x39, 0x0A,
+  0x01, 0x95, 0x41, 0x30, 0x32, 0x39, 0x0A, 0x04,
+  0xA0, 0x46, 0x05, 0x93, 0x41, 0x30, 0x32, 0x39,
+  0x0A, 0x02, 0x41, 0x30, 0x35, 0x38, 0x71, 0x41,
+  0x30, 0x33, 0x33, 0x71, 0x41, 0x30, 0x31, 0x39,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0xA2,
+  0x37, 0x92, 0x94, 0x41, 0x30, 0x31, 0x37, 0x41,
+  0x30, 0x30, 0x31, 0xA0, 0x26, 0x92, 0x93, 0x83,
+  0x88, 0x41, 0x30, 0x33, 0x34, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41,
+  0x30, 0x33, 0x34, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x88, 0x41, 0x30, 0x31, 0x39, 0x41, 0x30, 0x31,
+  0x37, 0x00, 0x75, 0x41, 0x30, 0x31, 0x37, 0xA1,
+  0x21, 0x41, 0x30, 0x35, 0x38, 0x71, 0x41, 0x30,
+  0x34, 0x31, 0x71, 0x41, 0x30, 0x31, 0x39, 0x70,
+  0x83, 0x88, 0x41, 0x30, 0x33, 0x33, 0x0A, 0x06,
+  0x00, 0x88, 0x41, 0x30, 0x31, 0x39, 0x0A, 0x06,
+  0x00, 0x41, 0x30, 0x34, 0x36, 0xA4, 0x67, 0x08,
+  0x41, 0x30, 0x35, 0x39, 0x12, 0x12, 0x08, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+  0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x14,
+  0x46, 0x11, 0x41, 0x30, 0x34, 0x36, 0x08, 0x70,
+  0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30,
+  0x35, 0x38, 0x71, 0x41, 0x30, 0x34, 0x31, 0x71,
+  0x41, 0x30, 0x35, 0x39, 0xA2, 0x30, 0x92, 0x94,
+  0x41, 0x30, 0x31, 0x37, 0x41, 0x30, 0x30, 0x31,
+  0xA0, 0x1F, 0x93, 0x41, 0x30, 0x31, 0x38, 0x41,
+  0x30, 0x31, 0x37, 0x0A, 0x01, 0x70, 0x41, 0x30,
+  0x36, 0x30, 0x41, 0x30, 0x31, 0x37, 0x88, 0x41,
+  0x30, 0x35, 0x39, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x75, 0x41, 0x30, 0x31, 0x37, 0xA0, 0x1F, 0x92,
+  0x93, 0x89, 0x41, 0x30, 0x34, 0x32, 0x01, 0x0A,
+  0x01, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41,
+  0x30, 0x35, 0x38, 0x71, 0x41, 0x30, 0x34, 0x31,
+  0x71, 0x41, 0x30, 0x35, 0x39, 0xA0, 0x1F, 0x92,
+  0x93, 0x89, 0x41, 0x30, 0x35, 0x39, 0x01, 0x0A,
+  0x02, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41,
+  0x30, 0x36, 0x31, 0x0A, 0x02, 0x0A, 0x01, 0x41,
+  0x30, 0x30, 0x32, 0x0A, 0x02, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x31, 0x37, 0xA2, 0x4E, 0x05, 0x92,
+  0x94, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30, 0x30,
+  0x31, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x31, 0x38,
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+  0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF,
+  0x0A, 0x01, 0x41, 0x30, 0x30, 0x34, 0x0A, 0x00,
+  0x0A, 0xB8, 0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C,
+  0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01, 0x41, 0x30,
+  0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0,
+  0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF,
+  0x0A, 0x00, 0xA1, 0x3D, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x41, 0x30, 0x30, 0x34, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0xA0, 0xF2, 0x01, 0x00, 0x0C, 0xFE, 0xFF,
+  0xFF, 0xFF, 0x0A, 0x00, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0xC0, 0xF2, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0xFF, 0xFF, 0x0A, 0x01,
+  0x70, 0x0A, 0x01, 0x66, 0x41, 0x30, 0x30, 0x34,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x00, 0xF3, 0x01,
+  0x00, 0x0C, 0xFE, 0xFF, 0x00, 0xFF, 0x66, 0x41,
+  0x30, 0x30, 0x35, 0x0A, 0x09, 0x14, 0x47, 0x07,
+  0x41, 0x30, 0x30, 0x38, 0x03, 0xA0, 0x0A, 0x94,
+  0x68, 0x69, 0x70, 0x69, 0x63, 0x70, 0x68, 0x64,
+  0xA1, 0x07, 0x70, 0x68, 0x63, 0x70, 0x69, 0x64,
+  0x70, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A,
+  0xB8, 0x0C, 0x9C, 0xF3, 0x01, 0x00, 0x60, 0x7B,
+  0x60, 0x0A, 0x18, 0x60, 0xA0, 0x18, 0x93, 0x6A,
+  0x0A, 0x00, 0x7D, 0x7D, 0x79, 0x64, 0x0A, 0x18,
+  0x00, 0x79, 0x63, 0x0A, 0x10, 0x00, 0x00, 0x7D,
+  0x60, 0x0A, 0x03, 0x00, 0x60, 0xA0, 0x18, 0x93,
+  0x6A, 0x0A, 0x01, 0x7D, 0x7D, 0x79, 0x64, 0x0A,
+  0x18, 0x00, 0x79, 0x63, 0x0A, 0x10, 0x00, 0x00,
+  0x7D, 0x60, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30,
+  0x30, 0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x9C,
+  0xF3, 0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x35,
+  0x74, 0x0A, 0x03, 0x6A, 0x00, 0x14, 0x06, 0x41,
+  0x30, 0x30, 0x39, 0x01, 0x08, 0x41, 0x30, 0x31,
+  0x30, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x31,
+  0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x32, 0x0A,
+  0x00, 0x14, 0x46, 0x0B, 0x41, 0x30, 0x31, 0x33,
+  0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, 0x0A, 0x03,
+  0x00, 0x0A, 0x04, 0x00, 0x62, 0xA0, 0x1C, 0x93,
+  0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0x70, 0x41,
+  0x30, 0x31, 0x34, 0x62, 0x0B, 0x24, 0x01, 0x41,
+  0x30, 0x31, 0x31, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x31, 0x32, 0x70, 0x41, 0x30, 0x31, 0x34, 0x62,
+  0x0B, 0x24, 0x01, 0x63, 0xA0, 0x13, 0x93, 0x68,
+  0x0A, 0x00, 0x7D, 0x63, 0x7B, 0x41, 0x30, 0x31,
+  0x31, 0x0C, 0x00, 0x00, 0x40, 0x00, 0x00, 0x63,
+  0xA1, 0x09, 0x7B, 0x63, 0x0C, 0xFF, 0xFF, 0xBF,
+  0xFF, 0x63, 0x41, 0x30, 0x31, 0x35, 0x62, 0x0B,
+  0x24, 0x01, 0x63, 0xA0, 0x36, 0x93, 0x41, 0x30,
+  0x31, 0x30, 0x0A, 0x00, 0xA0, 0x2D, 0x93, 0x41,
+  0x30, 0x31, 0x34, 0x0A, 0x08, 0x0A, 0x00, 0x0C,
+  0xFF, 0xFF, 0xFF, 0xFF, 0x7B, 0x41, 0x30, 0x30,
+  0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4,
+  0x01, 0x00, 0x0A, 0x02, 0x61, 0xA0, 0x0C, 0x93,
+  0x61, 0x0A, 0x02, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x31, 0x30, 0xA0, 0x1D, 0x93, 0x41, 0x30, 0x31,
+  0x30, 0x0A, 0x01, 0xA0, 0x09, 0x93, 0x68, 0x0A,
+  0x00, 0x70, 0x0A, 0x20, 0x60, 0xA1, 0x05, 0x70,
+  0x0A, 0x21, 0x60, 0x41, 0x30, 0x30, 0x35, 0x60,
+  0x14, 0x48, 0x08, 0x41, 0x30, 0x31, 0x36, 0x00,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x37, 0x70,
+  0x0A, 0x00, 0x61, 0xA2, 0x3E, 0x92, 0x94, 0x41,
+  0x30, 0x31, 0x37, 0x41, 0x30, 0x30, 0x31, 0xA0,
+  0x12, 0x93, 0x41, 0x30, 0x31, 0x38, 0x41, 0x30,
+  0x31, 0x37, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x31,
+  0x37, 0x9F, 0xA0, 0x1A, 0x93, 0x83, 0x88, 0x41,
+  0x30, 0x31, 0x39, 0x41, 0x30, 0x31, 0x37, 0x00,
+  0x0A, 0x02, 0x7D, 0x41, 0x30, 0x32, 0x30, 0x41,
+  0x30, 0x31, 0x37, 0x61, 0x61, 0x75, 0x41, 0x30,
+  0x31, 0x37, 0x70, 0x79, 0x61, 0x0A, 0x18, 0x00,
+  0x62, 0x7D, 0x7B, 0x7A, 0x61, 0x0A, 0x08, 0x00,
+  0x0B, 0x00, 0xFF, 0x00, 0x62, 0x62, 0x7D, 0x7B,
+  0x79, 0x61, 0x0A, 0x08, 0x00, 0x0C, 0x00, 0x00,
+  0xFF, 0x00, 0x00, 0x62, 0x62, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x10, 0xF6,
+  0x01, 0x00, 0x62, 0x41, 0x30, 0x30, 0x35, 0x0A,
+  0x08, 0x14, 0x4E, 0x0E, 0x41, 0x30, 0x32, 0x30,
+  0x01, 0x70, 0x41, 0x30, 0x32, 0x31, 0x68, 0x67,
+  0x70, 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41,
+  0x30, 0x32, 0x32, 0x70, 0x83, 0x88, 0x67, 0x0A,
+  0x01, 0x00, 0x41, 0x30, 0x32, 0x33, 0x70, 0x83,
+  0x88, 0x67, 0x0A, 0x02, 0x00, 0x41, 0x30, 0x32,
+  0x34, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x03, 0x00,
+  0x41, 0x30, 0x32, 0x35, 0x70, 0x7D, 0x79, 0x83,
+  0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01, 0x00,
+  0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67, 0x0A,
+  0x05, 0x00, 0x00, 0x41, 0x30, 0x32, 0x36, 0x70,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xE0,
+  0x7D, 0x79, 0x41, 0x30, 0x32, 0x36, 0x0A, 0x10,
+  0x00, 0x0B, 0x23, 0x80, 0x00, 0x65, 0x7A, 0x65,
+  0x41, 0x30, 0x32, 0x34, 0x65, 0x79, 0x0A, 0x01,
+  0x72, 0x74, 0x41, 0x30, 0x32, 0x35, 0x41, 0x30,
+  0x32, 0x34, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x74,
+  0x62, 0x0A, 0x01, 0x62, 0x7B, 0x65, 0x62, 0x65,
+  0xA0, 0x26, 0x94, 0x41, 0x30, 0x32, 0x32, 0x41,
+  0x30, 0x32, 0x33, 0x70, 0x41, 0x30, 0x32, 0x33,
+  0x63, 0x70, 0x41, 0x30, 0x32, 0x32, 0x64, 0x74,
+  0x74, 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x32,
+  0x34, 0x00, 0x74, 0x64, 0x63, 0x00, 0x61, 0xA1,
+  0x11, 0x70, 0x41, 0x30, 0x32, 0x33, 0x64, 0x70,
+  0x41, 0x30, 0x32, 0x32, 0x63, 0x70, 0x0A, 0x00,
+  0x61, 0x79, 0x0A, 0x01, 0x72, 0x74, 0x64, 0x63,
+  0x00, 0x0A, 0x01, 0x00, 0x62, 0x79, 0x74, 0x62,
+  0x0A, 0x01, 0x00, 0x61, 0x62, 0x7B, 0x62, 0x80,
+  0x65, 0x00, 0x62, 0x79, 0x74, 0x62, 0x0A, 0x01,
+  0x00, 0x74, 0x63, 0x61, 0x00, 0x62, 0xA4, 0x62,
+  0x08, 0x41, 0x30, 0x32, 0x37, 0x0A, 0x00, 0x08,
+  0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x14, 0x43,
+  0x08, 0x41, 0x57, 0x41, 0x4B, 0x01, 0xA0, 0x40,
+  0x07, 0x93, 0x68, 0x0A, 0x03, 0xA0, 0x2E, 0x93,
+  0x41, 0x30, 0x32, 0x37, 0x0A, 0x01, 0x70, 0x41,
+  0x30, 0x31, 0x34, 0x0A, 0xC5, 0x0B, 0x70, 0x01,
+  0x60, 0x41, 0x30, 0x31, 0x35, 0x0A, 0xC5, 0x0B,
+  0x70, 0x01, 0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01,
+  0x0A, 0x0E, 0x00, 0x00, 0x00, 0x70, 0x0A, 0x00,
+  0x41, 0x30, 0x32, 0x37, 0xA0, 0x3A, 0x93, 0x41,
+  0x30, 0x32, 0x38, 0x0A, 0x01, 0x70, 0x41, 0x30,
+  0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28,
+  0xF4, 0x01, 0x00, 0x60, 0x41, 0x30, 0x30, 0x36,
+  0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4, 0x01,
+  0x00, 0x7D, 0x60, 0x79, 0x0A, 0x01, 0x0A, 0x05,
+  0x00, 0x00, 0x41, 0x30, 0x30, 0x35, 0x0A, 0x16,
+  0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x38, 0x70,
+  0x41, 0x30, 0x30, 0x33, 0x61, 0x41, 0x30, 0x31,
+  0x33, 0x61, 0x14, 0x49, 0x08, 0x41, 0x50, 0x54,
+  0x53, 0x01, 0xA0, 0x41, 0x08, 0x93, 0x68, 0x0A,
+  0x03, 0x41, 0x30, 0x31, 0x33, 0x0A, 0x01, 0x70,
+  0x41, 0x30, 0x30, 0x37, 0x0A, 0x00, 0x0A, 0xB8,
+  0x0C, 0x28, 0xF4, 0x01, 0x00, 0x60, 0xA0, 0x33,
+  0x92, 0x93, 0x7B, 0x60, 0x79, 0x0A, 0x01, 0x0A,
+  0x05, 0x00, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x30,
+  0x36, 0x0A, 0x00, 0x0A, 0xB8, 0x0C, 0x28, 0xF4,
+  0x01, 0x00, 0x7B, 0x60, 0x80, 0x79, 0x0A, 0x01,
+  0x0A, 0x05, 0x00, 0x00, 0x00, 0x41, 0x30, 0x30,
+  0x35, 0x0A, 0x16, 0x70, 0x0A, 0x01, 0x41, 0x30,
+  0x32, 0x38, 0x70, 0x41, 0x30, 0x31, 0x34, 0x0A,
+  0xC5, 0x0B, 0x70, 0x01, 0x60, 0xA0, 0x26, 0x93,
+  0x7B, 0x60, 0x79, 0x0A, 0x01, 0x0A, 0x0E, 0x00,
+  0x00, 0x0A, 0x00, 0x41, 0x30, 0x31, 0x35, 0x0A,
+  0xC5, 0x0B, 0x70, 0x01, 0x7D, 0x60, 0x79, 0x0A,
+  0x01, 0x0A, 0x0E, 0x00, 0x00, 0x70, 0x0A, 0x01,
+  0x41, 0x30, 0x32, 0x37
+};
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
new file mode 100644
index 0000000000..862909513e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "PcieAlibSsdtTNFM2.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID *
+PcieAlibGetBaseTableTNFM2 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get base SSDT table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        pointer to SSTD table
+ */
+VOID *
+PcieAlibGetBaseTableTNFM2 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  return &AlibSsdtTNFM2[0];
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
new file mode 100644
index 0000000000..49bae5f302
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFM2.esl
@@ -0,0 +1,196 @@
+/**
+ * @file
+ *
+ * ALIB ASL library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63659 $   @e \$Date: 2012-01-03 00:42:47 -0600 (Tue, 03 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+DefinitionBlock (
+  "PcieAlibSsdtTN.aml",
+  "SSDT",
+  2,
+  "AMD",
+  "ALIB",
+  0x1
+  )
+{
+  Scope(\_SB) {
+
+    Name (varMaxPortIndexNumber, 6)
+
+    include ("PcieAlibMmioData.asl")
+    include ("PcieAlibPciLib.asl")
+    include ("PcieAlibDebugLib.asl")
+    include ("PcieSmuServiceV4.asl")
+
+
+    Name (varBapmControl, 0)
+    Name (varCstateIntControlState, 0)
+    Name (varIsStateInitialized, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  APM/PDM stub
+     *
+     *  Arg0 - AC/DC state
+     *
+     */
+    Method (procApmPdmActivate, 1, NotSerialized) {
+      Store (Or(ShiftLeft (0x18, 3), 4), Local2)
+      if (LEqual (varIsStateInitialized, 0)) {
+        Store (procPciDwordRead (Local2, 0x124), varCstateIntControlState)
+        Store (1, varIsStateInitialized)
+      }
+
+      Store (procPciDwordRead (Local2, 0x124), Local3)
+      if (LEqual (Arg0,DEF_PSPP_STATE_AC)) {
+        // Disable PC6 on AC
+        Or (Local3, And (varCstateIntControlState, 0x00400000), Local3)
+      } else {
+        // Enable PC6 on DC
+        And (Local3, 0xFFBFFFFF, Local3)
+      }
+      procPciDwordWrite (Local2, 0x124, Local3)
+
+      if (LEqual (varBapmControl, 0)) {
+        // If GFX present driver manage BAPM if not ALIB manage BAPM
+        if (LEqual (procPciDwordRead (0x08, 0x00), 0xffffffff)) {
+          And (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), 0x2, Local1);
+          // check if BAPM was enable during BIOS post
+          if (LEqual (Local1, 0x2)) {
+            Store (1, varBapmControl)
+          }
+        }
+      }
+      if (LEqual (varBapmControl,1)) {
+        if (LEqual (Arg0,DEF_PSPP_STATE_AC)) {
+          // Enable BAPM on AC
+          Store (32, Local0)
+        } else {
+          // Disable BAPM on DC
+          Store (33, Local0)
+        }
+        procNbSmuServiceRequest (Local0);
+      }
+    }
+
+    Name (varRestoreNbps, 0)
+    Name (varRestoreNbDpmState, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  _WAK
+     *
+     *
+     *
+     */
+    Method (AWAK, 1) {
+      if (LEqual (Arg0, 3)) {
+        // Clear D18F5x170 [SwNbPstateLoDis] only if it was 0 in APTS
+        if (LEqual (varRestoreNbps, 1)) {
+          Store (procPciDwordRead (0xC5, 0x170), Local0)
+          procPciDwordWrite (0xC5, 0x170, And (Local0, Not (ShiftLeft (1, 14))))
+           Store (0, varRestoreNbps);
+        }
+        if (LEqual (varRestoreNbDpmState, 1)) {
+          Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0)
+          procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, Or (Local0, ShiftLeft (1, 5)))
+          procNbSmuServiceRequest (22);
+          Store (0, varRestoreNbDpmState)
+        }
+      }
+    }
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  _PTS
+     *
+     *
+     *
+     */
+    Method (APTS, 1) {
+      if (LEqual (Arg0, 3)) {
+         procApmPdmActivate (DEF_PSPP_STATE_DC);
+         // Disable NBDPM
+         Store (procIndirectRegisterRead (0x0, 0xB8, 0x1F428), Local0)
+         if (LNotEqual (And (Local0, ShiftLeft (1, 5)), 0)) {
+           // NBDPM enabled lets disable it
+           procIndirectRegisterWrite (0x0, 0xB8, 0x1F428, And (Local0, Not (ShiftLeft (1, 5))))
+           procNbSmuServiceRequest (22);
+           // Indicate needs to restore NBDPM
+           Store (1, varRestoreNbDpmState);
+         }
+         // Save state of D18F5x170 [SwNbPstateLoDis]
+         Store (procPciDwordRead (0xC5, 0x170), Local0)
+         if (LEqual (And (Local0, ShiftLeft (1, 14)), 0)) {
+          // Set D18F5x170 [SwNbPstateLoDis] = 1
+          procPciDwordWrite (0xC5, 0x170, Or (Local0, ShiftLeft (1, 14)))
+           Store (1, varRestoreNbps);
+         }
+      }
+    }
+  } //End of Scope(\_SB)
+}   //End of DefinitionBlock
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
new file mode 100644
index 0000000000..baa0f85ac1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibTNFS1.c
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe ALIB
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "PcieAlibSsdtTNFS1.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID *
+PcieAlibGetBaseTableTNFS1 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get base SSDT table
+ *
+ *
+ *
+ * @param[in]     StdHeader       Standard Configuration Header
+ * @retval        pointer to SSTD table
+ */
+VOID *
+PcieAlibGetBaseTableTNFS1 (
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  return &AlibSsdtTNFS1[0];
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
new file mode 100644
index 0000000000..9c55714b93
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c
@@ -0,0 +1,491 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe configuration data definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECOMPLEXDATATN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+TN_COMPLEX_CONFIG ComplexDataTN = {
+  //Silicon
+  {
+    {
+      DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      0,
+      0,
+      offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon)
+    },
+    0,
+    0
+  },
+  //Gfx Wrapper
+  {
+    {
+      DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper)
+    },
+
+    GFX_WRAP_ID,
+    GFX_NUMBER_OF_PIFs,
+    GFX_START_PHY_LANE,
+    GFX_END_PHY_LANE,
+    GFX_CORE_ID,
+    GFX_CORE_ID,
+    16,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      1,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //Gpp Wrapper
+  {
+    {
+      DESCRIPTOR_PCIE_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper)
+    },
+    GPP_WRAP_ID,
+    GPP_NUMBER_OF_PIFs,
+    GPP_START_PHY_LANE,
+    GPP_END_PHY_LANE,
+    GPP_CORE_ID,
+    GPP_CORE_ID,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      1,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //DDI Wrapper
+  {
+    {
+      DESCRIPTOR_DDI_WRAPPER,
+      offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper)
+    },
+    DDI_WRAP_ID,
+    DDI_NUMBER_OF_PIFs,
+    DDI_START_PHY_LANE,
+    DDI_END_PHY_LANE,
+    0xf,
+    0x0,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      0,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //DDI2 Wrapper
+  {
+    {
+      DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon),
+      0,
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper)
+    },
+    DDI2_WRAP_ID,
+    DDI2_NUMBER_OF_PIFs,
+    DDI2_START_PHY_LANE,
+    DDI2_END_PHY_LANE,
+    0xf,
+    0x0,
+    8,
+    {
+      1,  //PowerOffUnusedLanesEnabled,
+      1,  //PowerOffUnusedPllsEnabled
+      1,  //ClkGating
+      1,  //LclkGating
+      1,  //TxclkGatingPllPowerDown
+      0,  //PllOffInL1
+      0   //AccessEncoding
+    },
+  },
+  //Port 2
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, Port2),
+      0
+    },
+    { PciePortEngine, 8, 23},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        0,
+        15,
+        2,
+        0,
+        GFX_CORE_ID,
+        0,
+        {0},
+        LinkStateResetExit,
+        0,
+        2,
+        1
+      },
+    },
+  },
+  //Port 3
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, Port3),
+      0
+    },
+    { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        UNUSED_LANE_ID,
+        UNUSED_LANE_ID,
+        3,
+        0,
+        GFX_CORE_ID,
+        1,
+        {0},
+        LinkStateResetExit,
+        1,
+        3,
+        1
+      },
+    },
+  },
+  //DdiB
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, DpB),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DdiC
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, DpC),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                               //Initialization Status
+    0xFF                                             //Scratch
+  },
+  //DdiD
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, DpD),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                               //Initialization Status
+    0xFF                                             //Scratch
+  },
+
+  //Port 4
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, Port4),
+      0
+    },
+    { PciePortEngine, 4, 4},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        4,
+        4,
+        4,
+        0,
+        GPP_CORE_ID,
+        1,
+        {0},
+        LinkStateResetExit,
+        2,
+        0,
+        0
+      },
+    },
+  },
+  //Port 5
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, Port5),
+      0
+    },
+    { PciePortEngine, 5, 5},
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        5,
+        5,
+        5,
+        0,
+        GPP_CORE_ID,
+        2,
+        {0},
+        LinkStateResetExit,
+        3,
+        0,
+        0
+      },
+    },
+  },
+  //Port 6
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, Port6),
+      0
+    },
+    { PciePortEngine, 6, 6 },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        6,
+        6,
+        6,
+        0,
+        GPP_CORE_ID,
+        3,
+        {0},
+        LinkStateResetExit,
+        4,
+        0,
+        0
+      },
+    },
+  },
+  //Port 7
+  {
+    {
+      DESCRIPTOR_PCIE_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, Port7),
+      0
+    },
+    { PciePortEngine, 7, 7 },
+    0,                                              //Initialization Status
+    0xFF,                                           //Scratch
+    {
+      {
+        {0},
+        7,
+        7,
+        7,
+        0,
+        GPP_CORE_ID,
+        4,
+        {0},
+        LinkStateResetExit,
+        5,
+        0,
+        0
+      },
+    },
+  },
+  //Port 8
+  {
+    {
+      DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, GppWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, Port8),
+      0
+    },
+    { PciePortEngine, 0, 3 },
+    INIT_STATUS_PCIE_TRAINING_SUCCESS,            //Initialization Status
+    0xFF,                                         //Scratch
+    {
+      {
+        {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}},
+        0,
+        3,
+        8,
+        0,
+        GPP_CORE_ID,
+        0,
+        {MAKE_SBDFO (0, 0, 8, 0, 0)},
+        LinkStateTrainingSuccess,
+        6,
+        0,
+        0
+      },
+    },
+  },
+  //DpE
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE,
+      offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DpE),
+      0
+    },
+   {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DpF
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST,
+      offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper),
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, DpF),
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //DpA
+  {
+    {
+      DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY,
+      offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper),
+      0,
+      0
+    },
+    {PcieDdiEngine},
+    0,                                              //Initialization Status
+    0xFF                                            //Scratch
+  },
+  //F12 specific Silicon
+  {
+    OscFuses,
+    {0, 0, 0, 0, 0, 0}
+  }
+};
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h
new file mode 100644
index 0000000000..623636cc06
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.h
@@ -0,0 +1,160 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIECOMPLEXDATATN_H_
+#define _PCIECOMPLEXDATATN_H_
+
+#define SOCKET_ID             0
+
+#define MAX_NUM_PHYs          2
+#define MAX_NUM_LANE_PER_PHY  8
+
+#define NUMBER_OF_PORTS     8
+#define NUMBER_OF_GPP_PORTS 5
+#define NUMBER_OF_GFX_PORTS 2
+#define NUMBER_OF_GFX_DDIS  3
+#define NUMBER_OF_DDIS      2
+#define NUMBER_OF_DDIS2     1
+#define NUMBER_OF_WRAPPERS  3
+#define NUMBER_OF_SILICONS  1
+
+#define GFX_WRAP_ID         1
+#define GFX_NUMBER_OF_PIFs  2
+#define GFX_START_PHY_LANE  8
+#define GFX_END_PHY_LANE    23
+#define GFX_CORE_ID         2
+
+#define GFX_CORE_x16        ((16 << 8) | 0)
+#define GFX_CORE_x8x8       ((8 << 8) | 8)
+
+#define GPP_WRAP_ID         0
+#define GPP_NUMBER_OF_PIFs  1
+#define GPP_START_PHY_LANE  0
+#define GPP_END_PHY_LANE    7
+#define GPP_CORE_ID         1
+
+#define GPP_CORE_x4x1x1x1x1   ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x1x1     ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x1x1_ST  ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x2       ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x2x2_ST    ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0))
+#define GPP_CORE_x4x4         ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
+
+#define DDI_WRAP_ID           2
+#define DDI_NUMBER_OF_PIFs    1
+#define DDI_START_PHY_LANE    24
+#define DDI_END_PHY_LANE      31
+
+#define DDI2_WRAP_ID          3
+#define DDI2_NUMBER_OF_PIFs   1
+#define DDI2_START_PHY_LANE   32
+#define DDI2_END_PHY_LANE     38
+
+///Gen2 capability
+typedef enum {
+  OscFuses,                   ///< Not capable
+  OscRO,                      ///< Gen2 with RO
+  OscLC,                      ///< Gen2 with LC
+  OscDefault,                 ///< Skip initialization of OSC
+} OSC_MODE;
+
+///Family specific silicon configuration
+typedef struct {
+  OSC_MODE  OscMode;          ///<OSC mode
+  UINT8     PortDevMap[6];    ///< Device number that has beed allocated already
+} TN_PCIe_SILICON_CONFIG;
+
+
+/// Complex Configuration
+typedef struct {
+  PCIe_SILICON_CONFIG     Silicon;                ///< Silicon
+  PCIe_WRAPPER_CONFIG     GfxWrapper;             ///< Graphics Wrapper
+  PCIe_WRAPPER_CONFIG     GppWrapper;             ///< General Purpose Port
+  PCIe_WRAPPER_CONFIG     DdiWrapper;             ///< DDI
+  PCIe_WRAPPER_CONFIG     Ddi2Wrapper;            ///< DDI
+  PCIe_ENGINE_CONFIG      Port2;                  ///< Port 2
+  PCIe_ENGINE_CONFIG      Port3;                  ///< Port 3
+  PCIe_ENGINE_CONFIG      DpB;                    ///< DPB
+  PCIe_ENGINE_CONFIG      DpC;                    ///< DPC
+  PCIe_ENGINE_CONFIG      DpD;                    ///< DPD
+  PCIe_ENGINE_CONFIG      Port4;                  ///< Port 4
+  PCIe_ENGINE_CONFIG      Port5;                  ///< Port 5
+  PCIe_ENGINE_CONFIG      Port6;                  ///< Port 6
+  PCIe_ENGINE_CONFIG      Port7;                  ///< Port 7
+  PCIe_ENGINE_CONFIG      Port8;                  ///< Port 8
+  PCIe_ENGINE_CONFIG      DpE;                    ///< DPE
+  PCIe_ENGINE_CONFIG      DpF;                    ///< DPF
+  PCIe_ENGINE_CONFIG      DpA;                    ///< DPA
+  TN_PCIe_SILICON_CONFIG  FmSilicon;               ///< Fm Silicon
+} TN_COMPLEX_CONFIG;
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
new file mode 100644
index 0000000000..8d687d910a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c
@@ -0,0 +1,1002 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family specific PCIe wrapper configuration services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "amdlib.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern TN_COMPLEX_CONFIG      ComplexDataTN;
+extern PCIe_PORT_DESCRIPTOR   DefaultSbPort;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+PcieConfigureEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureGppEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdi2EnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  );
+
+AGESA_STATUS
+PcieGetCoreConfigurationValueTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  );
+
+BOOLEAN
+PcieCheckPortPciDeviceMappingTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  );
+
+CONST CHAR8*
+PcieDebugGetCoreConfigurationStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  );
+
+CONST CHAR8*
+PcieDebugGetWrapperNameStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  );
+
+CONST CHAR8*
+PcieDebugGetHostRegAddressSpaceStringTN (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  );
+
+BOOLEAN
+PcieCheckPortPcieLaneCanBeMuxedTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  );
+
+AGESA_STATUS
+PcieMapPortPciAddressTN (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  );
+
+AGESA_STATUS
+PcieGetComplexDataLengthTN (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+AGESA_STATUS
+PcieBuildComplexConfigurationTN (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+UINT32
+PcieGetNativePhyLaneBitmapTN (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  );
+
+AGESA_STATUS
+PcieGetSbConfigInfoTN (
+  IN       UINT8                         SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR          *SbPort,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   No more configuration available for given engine type
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+AGESA_STATUS
+PcieConfigureEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_ERROR;
+  switch (Wrapper->WrapId) {
+  case GFX_WRAP_ID:
+    Status = PcieConfigureGfxEnginesLaneAllocationTN (Wrapper, EngineType, ConfigurationId);
+    break;
+  case GPP_WRAP_ID:
+    if (EngineType != PciePortEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureGppEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case DDI_WRAP_ID:
+    if (EngineType != PcieDdiEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case DDI2_WRAP_ID:
+    if (EngineType != PcieDdiEngine) {
+      return AGESA_UNSUPPORTED;
+    }
+    Status = PcieConfigureDdi2EnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return Status;
+}
+
+CONST UINT8 GfxPortLaneConfigurationTable [][NUMBER_OF_GFX_PORTS * 2] = {
+{0,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+{0,   7, 8,              15}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxPortEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  UINTN               CoreLaneIndex;
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  if (ConfigurationId > ((sizeof (GfxPortLaneConfigurationTable) / (NUMBER_OF_GFX_PORTS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  CoreLaneIndex = 0;
+  while (EnginesList != NULL) {
+    if (PcieLibIsPcieEngine (EnginesList)) {
+      PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+      EnginesList->Type.Port.StartCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+      EnginesList->Type.Port.EndCoreLane = GfxPortLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    }
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+CONST UINT8 GfxDdiLaneConfigurationTable [][NUMBER_OF_GFX_DDIS * 2] = {
+  {0,   7, 8,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+  {4,   7, 8,  15, UNUSED_LANE_ID, UNUSED_LANE_ID},
+  {0,   7, 8,  11, 12,             15},
+  {4,   7, 8,  11, 12,             15}
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  UINTN               LaneIndex;
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  if (ConfigurationId > ((sizeof (GfxDdiLaneConfigurationTable) / (NUMBER_OF_GFX_DDIS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  while (EnginesList != NULL) {
+    if (PcieLibIsDdiEngine (EnginesList)) {
+      PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+      EnginesList->EngineData.StartLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+      EnginesList->EngineData.EndLane = GfxDdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    }
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  EngineType          Engine Type
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_UNSUPPORTED   Configuration not applicable
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+AGESA_STATUS
+STATIC
+PcieConfigureGfxEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      PCIE_ENGINE_TYPE              EngineType,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  AGESA_STATUS  Status;
+
+  switch (EngineType) {
+  case PciePortEngine:
+    Status = PcieConfigureGfxPortEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  case PcieDdiEngine:
+    Status = PcieConfigureGfxDdiEnginesLaneAllocationTN (Wrapper, ConfigurationId);
+    break;
+  default:
+    Status = AGESA_UNSUPPORTED;
+  }
+  return Status;
+}
+
+
+
+CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
+//4     5                                6                               7                                8 (SB)
+  {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID,  UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, 6,              7,               UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID,  6,              7,              UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, 6,              6,               7,              7,              UNUSED_LANE_ID, UNUSED_LANE_ID,  0, 3},
+  {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID,  6,              6,              7,              7,               0, 3},
+  {4, 4, 5,              5,               6,              6,              7,              7,               0, 3}
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure GFX engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureGppEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               CoreLaneIndex;
+  UINTN               PortIdIndex;
+  if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  CoreLaneIndex = 0;
+  PortIdIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
+  {0,  3,   4,              7},
+  {0,  7,   UNUSED_LANE_ID, UNUSED_LANE_ID}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure DDI engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdiEnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               LaneIndex;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+CONST UINT8 Ddi2LaneConfigurationTable [][NUMBER_OF_DDIS2 * 2] = {
+  {0,  6},
+  {0,  3}
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure DDI engine list to support lane allocation according to configuration ID.
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  ConfigurationId     Configuration ID
+ * @retval     AGESA_SUCCESS       Configuration successfully applied
+ * @retval     AGESA_ERROR         Requested configuration not supported
+ */
+
+
+AGESA_STATUS
+STATIC
+PcieConfigureDdi2EnginesLaneAllocationTN (
+  IN      PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN      UINT8                         ConfigurationId
+  )
+{
+  PCIe_ENGINE_CONFIG  *EnginesList;
+  UINTN               LaneIndex;
+  EnginesList = PcieConfigGetChildEngine (Wrapper);
+  if (ConfigurationId > ((sizeof (Ddi2LaneConfigurationTable) / (NUMBER_OF_DDIS2 * 2)) - 1)) {
+    return AGESA_ERROR;
+  }
+  LaneIndex = 0;
+  while (EnginesList != NULL) {
+    PcieConfigResetDescriptorFlags (EnginesList, DESCRIPTOR_ALLOCATED);
+    EnginesList->EngineData.StartLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList->EngineData.EndLane = Ddi2LaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane;
+    EnginesList = PcieLibGetNextDescriptor (EnginesList);
+  }
+  return  AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get configuration Value for GFX wrapper
+ *
+ *
+ *
+ * @param[in]   ConfigurationSignature  Configuration signature
+ * @param[out]  ConfigurationValue      Configuration value
+ * @retval     AGESA_SUCCESS            Correct core configuration value returned by in *ConfigurationValue
+ * @retval     AGESA_ERROR              ConfigurationSignature is incorrect.
+ */
+STATIC AGESA_STATUS
+PcieGetGfxConfigurationValueTN (
+  IN       UINT64    ConfigurationSignature,
+     OUT   UINT8     *ConfigurationValue
+  )
+{
+  switch (ConfigurationSignature) {
+  case GFX_CORE_x16:
+    *ConfigurationValue = 0;
+    break;
+  case GFX_CORE_x8x8:
+    *ConfigurationValue = 0x5;
+    break;
+  default:
+    ASSERT (FALSE);
+    return  AGESA_ERROR;
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get configuration Value for GPP wrapper
+ *
+ *
+ *
+ * @param[in]   ConfigurationSignature  Configuration signature
+ * @param[out]  ConfigurationValue      Configuration value
+ * @retval      AGESA_SUCCESS           Correct core configuration value returned by in *ConfigurationValue
+ * @retval      AGESA_ERROR             ConfigurationSignature is incorrect
+ */
+STATIC AGESA_STATUS
+PcieGetGppConfigurationValueTN (
+  IN       UINT64    ConfigurationSignature,
+     OUT   UINT8     *ConfigurationValue
+  )
+{
+  switch (ConfigurationSignature) {
+  case GPP_CORE_x4x1x1x1x1:
+    *ConfigurationValue = 0x4;
+    break;
+  case GPP_CORE_x4x2x1x1:
+    *ConfigurationValue = 0x3;
+    break;
+  case GPP_CORE_x4x2x2:
+    *ConfigurationValue = 0x2;
+    break;
+  case GPP_CORE_x4x4:
+    *ConfigurationValue = 0x1;
+    break;
+  default:
+    ASSERT (FALSE);
+    return  AGESA_ERROR;
+  }
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration value
+ *
+ *
+ *
+ * @param[in]  Wrapper                Pointer to internal configuration data area
+ * @param[in]  CoreId                 Core ID
+ * @param[in]  ConfigurationSignature Configuration signature
+ * @param[out] ConfigurationValue     Configuration value (for core configuration)
+ * @retval     AGESA_SUCCESS          Configuration successfully applied
+ * @retval     AGESA_ERROR            Core configuration value can not be determined
+ */
+AGESA_STATUS
+PcieGetCoreConfigurationValueTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 CoreId,
+  IN      UINT64                ConfigurationSignature,
+  IN      UINT8                 *ConfigurationValue
+  )
+{
+  AGESA_STATUS  Status;
+
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+    Status = PcieGetGfxConfigurationValueTN (ConfigurationSignature, ConfigurationValue);
+  } else if (Wrapper->WrapId == GPP_WRAP_ID) {
+    Status = PcieGetGppConfigurationValueTN (ConfigurationSignature, ConfigurationValue);
+  } else {
+    Status = AGESA_ERROR;
+  }
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if engine can be remapped to Device/function number requested by user
+ * defined engine descriptor
+ *
+ *   Function only called if requested device/function does not much native device/function
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Descriptor can be mapped to engine
+ * @retval     FALSE               Descriptor can NOT be mapped to engine
+ */
+
+BOOLEAN
+PcieCheckPortPciDeviceMappingTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  BOOLEAN   Result;
+  if (PortDescriptor->Port.DeviceNumber >= 2 && PortDescriptor->Port.DeviceNumber <= 7 && PortDescriptor->Port.FunctionNumber == 0 && !PcieConfigIsSbPcieEngine (Engine)) {
+    Result = TRUE;
+  } else {
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get core configuration string
+ *
+ *   Debug function for logging configuration
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @param[in] ConfigurationValue   Configuration value
+ * @retval                         Configuration string
+ */
+
+CONST CHAR8*
+PcieDebugGetCoreConfigurationStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      UINT8                 ConfigurationValue
+  )
+{
+  switch (ConfigurationValue) {
+  case 0:
+    return "1x16";
+  case 5:
+    return "2x8";
+  case 4:
+    return "1x4, 4x1";
+  case 3:
+    return "1x4, 1x2, 2x1";
+  case 2:
+    return "1x4, 2x2";
+  case 1:
+    return "1x4, 1x4";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get wrapper name
+ *
+ *  Debug function for logging wrapper name
+ *
+ * @param[in] Wrapper              Pointer to internal configuration data area
+ * @retval                         Wrapper Name string
+ */
+
+CONST CHAR8*
+PcieDebugGetWrapperNameStringTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper
+  )
+{
+  switch (Wrapper->WrapId) {
+  case  GPP_WRAP_ID:
+    return "GPPSB";
+  case  GFX_WRAP_ID:
+    return "GFX";
+  case  DDI_WRAP_ID:
+    return "DDI";
+  case  DDI2_WRAP_ID:
+    return "DDI2";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get register address name
+ *
+ *  Debug function for logging register trace
+ *
+ * @param[in] Silicon              Silicon config descriptor
+ * @param[in] AddressFrame         Address Frame
+ * @retval                         Register address name
+ */
+CONST CHAR8*
+PcieDebugGetHostRegAddressSpaceStringTN (
+  IN      PCIe_SILICON_CONFIG    *Silicon,
+  IN      UINT16                 AddressFrame
+  )
+{
+  switch (AddressFrame) {
+  case  0x130:
+    return "GPP  WRAP";
+  case  0x131:
+    return "GFX  WRAP";
+  case  0x132:
+    return "DDI  WRAP";
+  case  0x133:
+    return "DDI2 WRAP";
+  case  0x110:
+    return "GPP  PIF0";
+  case  0x111:
+    return "GFX  PIF0";
+  case  0x211:
+    return "GFX  PIF1";
+  case  0x112:
+    return "DDI  PIF0";
+  case  0x113:
+    return "DDI2 PIF0";
+  case  0x120:
+    return "GPP  PHY0";
+  case  0x121:
+    return "GFX  PHY0";
+  case  0x221:
+    return "GFX  PHY1";
+  case  0x122:
+    return "DDI  PHY0";
+  case  0x123:
+    return "DDI2 PHY0";
+  case  0x101:
+    return "GPP  CORE";
+  case  0x201:
+    return "GFX  CORE";
+  default:
+    break;
+  }
+  return " !!! Something Wrong !!!";
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if the lane can be muxed by link width requested by user
+ * defined engine descriptor
+ *
+ *    Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
+ *    Check Engine StartCoreLane could be aligned by user requested link width x2.
+ *
+ * @param[in]  PortDescriptor      Pointer to user defined engine descriptor
+ * @param[in]  Engine              Pointer engine configuration
+ * @retval     TRUE                Lane can be muxed
+ * @retval     FALSE               Lane can NOT be muxed
+ */
+
+BOOLEAN
+PcieCheckPortPcieLaneCanBeMuxedTN (
+  IN      PCIe_PORT_DESCRIPTOR  *PortDescriptor,
+  IN      PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  UINT16                DescriptorHiLane;
+  UINT16                DescriptorLoLane;
+  UINT16                DescriptorNumberOfLanes;
+  PCIe_WRAPPER_CONFIG   *Wrapper;
+  UINT16                NormalizedLoPhyLane;
+  BOOLEAN               Result;
+
+  Result  = FALSE;
+  Wrapper = PcieConfigGetParentWrapper (Engine);
+  DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
+  DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
+  DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
+
+  NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane;
+
+  if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) {
+    Result = TRUE;
+  } else {
+    if (((PortDescriptor->Port.MiscControls.SbLink == 0x0) && ((Engine->Type.Port.StartCoreLane % 2) == 0)) || (Engine->Type.Port.StartCoreLane == 0)) {
+      if (NormalizedLoPhyLane == 0) {
+        Result = TRUE;
+      } else {
+        if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) {
+          Result = TRUE;
+        }
+      }
+    }
+  }
+  return Result;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Map engine to specific PCI device address
+ *
+ *
+ *
+ * @param[in]  Engine              Pointer to engine configuration
+ * @retval     AGESA_ERROR         Fail to map PCI device address
+ * @retval     AGESA_SUCCESS       Successfully allocate PCI address
+ */
+
+AGESA_STATUS
+PcieMapPortPciAddressTN (
+  IN      PCIe_ENGINE_CONFIG     *Engine
+  )
+{
+  AGESA_STATUS            Status;
+  TN_COMPLEX_CONFIG       *ComplexConfig;
+  PCIe_PLATFORM_CONFIG    *Pcie;
+  UINT8                   PortDevMap[6];
+  UINT8                   FreeDevMap[6];
+  UINT8                   PortIndex;
+  UINT8                   EnginePortIndex;
+  UINT8                   FreeIndex;
+  D0F0x64_x20_STRUCT      D0F0x64_x20;
+  D0F0x64_x21_STRUCT      D0F0x64_x21;
+  Status = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Enter\n");
+  if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
+    Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
+    Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
+  }
+  if (!PcieConfigIsSbPcieEngine (Engine)) {
+    ComplexConfig = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
+    Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+    LibAmdMemFill (&FreeDevMap[0], 0x0, sizeof (FreeDevMap), GnbLibGetHeader (Pcie));
+    LibAmdMemCopy (&PortDevMap[0], &ComplexConfig->FmSilicon.PortDevMap, sizeof (PortDevMap), GnbLibGetHeader (Pcie));
+    for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
+      if (PortDevMap[PortIndex] != 0) {
+        FreeDevMap[PortDevMap[PortIndex] - 2] = 1;
+      }
+    }
+    EnginePortIndex = Engine->Type.Port.PortData.DeviceNumber - 2;
+    if (FreeDevMap[EnginePortIndex] == 0) {
+      // Dev number not yet allocated
+      ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
+      FreeDevMap[EnginePortIndex] = 1;
+      PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
+      for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
+        if (PortDevMap[PortIndex] == 0) {
+          for (FreeIndex = 0; FreeIndex < sizeof (FreeDevMap); FreeIndex++) {
+            if (FreeDevMap[FreeIndex] == 0) {
+              FreeDevMap[FreeIndex] = 1;
+              break;
+            }
+          }
+          PortDevMap[PortIndex] = FreeIndex + 2;
+        }
+      }
+
+      GnbRegisterReadTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x20.Field.ProgDevMapEn = 0;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      GnbRegisterReadTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x21.Field.GfxPortADevmap = PortDevMap[2 - 2];
+      D0F0x64_x21.Field.GfxPortBDevmap = PortDevMap[3 - 2];
+      D0F0x64_x20.Field.GppPortBDevmap = PortDevMap[4 - 2];
+      D0F0x64_x20.Field.GppPortCDevmap = PortDevMap[5 - 2];
+      D0F0x64_x20.Field.GppPortDDevmap = PortDevMap[6 - 2];
+      D0F0x64_x20.Field.GppPortEDevmap = PortDevMap[7 - 2];
+      D0F0x64_x20.Field.ProgDevMapEn = 0x1;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+      GnbRegisterWriteTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
+      D0F0x64_x20.Field.ProgDevMapEn = 1;
+      GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Fail device %d to port %d\n", Engine->Type.Port.PortData.DeviceNumber, Engine->Type.Port.NativeDevNumber);
+      Status = AGESA_ERROR;
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Exit [0x%x]\n", Status);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get total number of silicons/wrappers/engines for this complex
+ *
+ *
+ *
+ * @param[in]  SocketId              Socket ID.
+ * @param[out] Length                Length of configuration info block
+ * @param[out] StdHeader             Standard configuration header
+ * @retval     AGESA_SUCCESS         Configuration data length is correct
+ */
+AGESA_STATUS
+PcieGetComplexDataLengthTN (
+  IN       UINT8                         SocketId,
+     OUT   UINTN                         *Length,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  *Length = sizeof (TN_COMPLEX_CONFIG);
+  return  AGESA_SUCCESS;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build configuration
+ *
+ *
+ *
+ * @param[in]  SocketId         Socket ID.
+ * @param[out] Buffer           Pointer to buffer to build internal complex data structure
+ * @param[out] StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieBuildComplexConfigurationTN (
+  IN       UINT8                         SocketId,
+     OUT   VOID                          *Buffer,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  LibAmdMemCopy (Buffer, &ComplexDataTN, sizeof (TN_COMPLEX_CONFIG), StdHeader);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  get native PHY lane bitmap
+ *
+ *
+ * @param[in]  PhyLaneBitmap  Package PHY lane bitmap
+ * @param[in]  Engine         Standard configuration header.
+ * @retval     Native PHY lane bitmap
+ */
+UINT32
+PcieGetNativePhyLaneBitmapTN (
+  IN       UINT32                        PhyLaneBitmap,
+  IN       PCIe_ENGINE_CONFIG            *Engine
+  )
+{
+  return PhyLaneBitmap;
+}
+
+STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = {
+  0,
+  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0)
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build default SB configuration descriptor
+ *
+ *
+ * @param[in]  SocketId         Socket Id
+ * @param[out] SbPort           Pointer to SB configuration descriptor
+ * @param[in]  StdHeader        Standard configuration header.
+ * @retval     AGESA_SUCCESS    Configuration data build successfully
+ */
+AGESA_STATUS
+PcieGetSbConfigInfoTN (
+  IN       UINT8                         SocketId,
+     OUT   PCIe_PORT_DESCRIPTOR          *SbPort,
+  IN       AMD_CONFIG_PARAMS             *StdHeader
+  )
+{
+  LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader);
+  return AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
new file mode 100644
index 0000000000..642f41ff89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEarlyInitTN.c
@@ -0,0 +1,810 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 64781 $   @e \$Date: 2012-01-30 21:19:50 -0600 (Mon, 30 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbCommonLib.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbNbInitLibV4.h"
+#include  "PcieLibTN.h"
+#include  "PcieComplexDataTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "cpuFamilyTranslation.h"
+#include  "cpuFamRegisters.h"
+#include  "F15TnPackageType.h"
+#include  "GeneralServices.h"
+#include  "Filecode.h"
+
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern BUILD_OPT_CFG UserOptions;
+extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN;
+extern CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN;
+extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY lane parameter Init
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PciePhyLaneInitInitCallbackTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      VOID                  *Buffer,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8   Phy;
+  UINT8   PhyLaneIndex;
+  UINT8   Lane;
+  UINT32  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper);
+  for (Lane = 0; Lane < Wrapper->NumberOfLanes; ++Lane) {
+    if ((LaneBitmap & (1 << Lane)) != 0) {
+      Phy = Lane / MAX_NUM_LANE_PER_PHY;
+      PhyLaneIndex = Lane - Phy * MAX_NUM_LANE_PER_PHY;
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_400A_ADDRESS + PhyLaneIndex * 0x80),
+        D0F0xE4_PHY_400A_BiasDisInLs2_MASK | D0F0xE4_PHY_400A_Ls2ExitTime_MASK,
+        (1 << D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET) | (1 << D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET),
+        FALSE,
+        Pcie
+        );
+      PcieRegisterRMW (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_4002_ADDRESS + PhyLaneIndex * 0x80),
+        D0F0xE4_PHY_4002_LfcMax_MASK,
+        (8 << D0F0xE4_PHY_4002_LfcMax_OFFSET),
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLaneInitInitCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Satic init for various registers.
+ *
+ *
+ *
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+STATIC
+PcieEarlyStaticInitTN (
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINTN Index;
+
+  for (Index = 0; Index < PcieInitEarlyTableTN.Length; Index++) {
+    GnbLibPciIndirectRMW (
+      MAKE_SBDFO (0,0,0,0, D0F0xE0_ADDRESS),
+      PcieInitEarlyTableTN.Table[Index].Reg,
+      AccessWidth32,
+      (UINT32)~PcieInitEarlyTableTN.Table[Index].Mask,
+      PcieInitEarlyTableTN.Table[Index].Data,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init core registers.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+STATIC
+PcieEarlyCoreInitTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINT8   CoreId;
+  UINTN   Index;
+  if (PcieLibIsPcieWrapper (Wrapper)) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Enter\n");
+    for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
+      for (Index = 0; Index < CoreInitTableTN.Length; Index++) {
+        UINT32 Value;
+        Value = PcieRegisterRead (
+                  Wrapper,
+                  CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
+                  Pcie
+                  );
+        Value &= (~CoreInitTableTN.Table[Index].Mask);
+        Value |= CoreInitTableTN.Table[Index].Data;
+        PcieRegisterWrite (
+          Wrapper,
+          CORE_SPACE (CoreId, CoreInitTableTN.Table[Index].Reg),
+          Value,
+          FALSE,
+          Pcie
+          );
+      }
+    }
+    IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyCoreInitTN Exit\n");
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Dll Cap based on fuses
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper configuration data area
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+STATIC VOID
+PcieSetDllCapTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D18F3x1FC_STRUCT           D18F3x1FC;
+  D0F0xE4_PHY_500F_STRUCT    D0F0xE4_PHY_500F;
+  D0F0xE4_PHY_4010_STRUCT    D0F0xE4_PHY_4010;
+  D0F0xE4_PHY_4011_STRUCT    D0F0xE4_PHY_4011;
+  UINT32                     Gen1Index;
+  UINT32                     Gen2Index;
+  CPU_LOGICAL_ID             LogicalId;
+  GNB_HANDLE                 *GnbHandle;
+
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Enter\n");
+
+  D0F0xE4_PHY_500F.Value = 0;
+  GnbHandle = GnbGetHandle (GnbLibGetHeader (Pcie));
+  ASSERT (GnbHandle != NULL);
+  GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, GnbLibGetHeader (Pcie));
+
+  //Read SWDllCapTableEn
+  GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC, 0, GnbLibGetHeader (Pcie));
+  IDS_HDT_CONSOLE (GNB_TRACE, "Read D18F3x1FC value %x\n", D18F3x1FC.Value);
+
+  if ((D18F3x1FC.Field.SWDllCapTableEn != 0) || ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull  )) {
+    IDS_HDT_CONSOLE (GNB_TRACE, "Executing DLL configuration\n");
+    // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]0 Phy Receiver Functional Fuse Control (FuseFuncDllProcessCompCtl[1:0])
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4010 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS));
+    D0F0xE4_PHY_4010.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4010_ADDRESS), Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Read 4010 value = %x\n", D0F0xE4_PHY_4010.Value);
+    // Read D0F0xE4_x0[2:1]2[1:0]_[5:4][7:6,3:0][9,1]1 Phy Receiver Process Fuse Control (FuseProcDllProcessComp[2:0])
+    IDS_HDT_CONSOLE (GNB_TRACE, "Reading 0x4011 from PHY_SPACE %x\n", PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS));
+    D0F0xE4_PHY_4011.Value = PcieRegisterRead (Wrapper, PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_4011_ADDRESS), Pcie);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Read 4011 value = %x\n", D0F0xE4_PHY_4011.Value);
+
+    // If FuseProcDllProcessCompCtl[1:0] == 2'b11 Then Gen1Index[3:0] = FuseProcDllProcessComp[2:0], 0
+    // Else...
+    // If FuseProcDllProcessComp[2:0] == 3'b000 Then Gen1Index[3:0] =4'b1101 //Typical
+    // If FuseProcDllProcessComp[2:0] == 3'b001 Then Gen1Index[3:0] =4'b1111 //Fast
+    // If FuseProcDllProcessComp[2:0] == 3'b010 Then Gen1Index[3:0] =4'b1010 //Slow
+    IDS_HDT_CONSOLE (GNB_TRACE, "FuseFuncDllProcessCompCtl %x\n", D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl);
+    if (D0F0xE4_PHY_4010.Field.FuseFuncDllProcessCompCtl == 3) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from FuseFuncDllProcessComp %x\n", D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp);
+      Gen1Index = D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp << 1;
+    } else {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Setting Gen1Index from switch case...");
+      switch (D0F0xE4_PHY_4011.Field.FuseProcDllProcessComp) {
+      case 0:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 0 - using 0xd\n");
+        Gen1Index = 0xd;
+        break;
+      case 1:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 1 - using 0xf\n");
+        Gen1Index = 0xf;
+        break;
+      case 2:
+        IDS_HDT_CONSOLE (GNB_TRACE, "case 2 - using 0xa\n");
+        Gen1Index = 0xa;
+        break;
+      default:
+        IDS_HDT_CONSOLE (GNB_TRACE, "default - using 0xd\n");
+        Gen1Index = 0xd; //Use typical for default case
+        break;
+      }
+    }
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex1 = Gen1Index;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen1Index to %x\n", Gen1Index);
+    // Bits  3:0 = Gen1Index[3:0]
+    // Bits 10:7 = DllProcessFreqCtlIndex2Rate50[3:0]
+    if (D18F3x1FC.Field.SWDllCapTableEn != 0) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Gen2Index - using DllProcFreqCtlIndex2Rate50 = %x\n", D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50);
+      Gen2Index = D18F3x1FC.Field.DllProcFreqCtlIndex2Rate50;
+    } else {
+      Gen2Index = 0x03; // Hard coded default
+    }
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlIndex2 = Gen2Index;
+    IDS_HDT_CONSOLE (GNB_TRACE, "Set Gen2Index to %x\n", Gen2Index);
+    PcieRegisterWrite (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
+      D0F0xE4_PHY_500F.Value,
+      FALSE,
+      Pcie
+      );
+    // Set DllProcessFreqCtlOverride on second write
+    D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
+    PcieRegisterWrite (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, 0, D0F0xE4_PHY_500F_ADDRESS),
+      D0F0xE4_PHY_500F.Value,
+      FALSE,
+      Pcie
+      );
+    if (Wrapper->WrapId == 1) {
+      // For Wrapper 1, configure PHY0 and PHY1
+      D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 0;
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
+        D0F0xE4_PHY_500F.Value,
+        FALSE,
+        Pcie
+        );
+      // Set DllProcessFreqCtlOverride on second write
+      D0F0xE4_PHY_500F.Field.DllProcessFreqCtlOverride = 1;
+      PcieRegisterWrite (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, 1, D0F0xE4_PHY_500F_ADDRESS),
+        D0F0xE4_PHY_500F.Value,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDllCapTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * TN FP2 PCIE allocation x8 check
+ *
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+
+STATIC AGESA_STATUS
+PcieFP2x8CheckCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  UINT32                    LaneBitmap;
+  AGESA_STATUS              Status;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Enter\n");
+
+  Status = AGESA_SUCCESS;
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+
+    LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper);
+    IDS_HDT_CONSOLE (GNB_TRACE, "FP2 GFX Wrpper phy LaneBitmap = %x\n", LaneBitmap);
+
+    if (((LaneBitmap & 0xFF) != 0) && ((LaneBitmap & 0xFF00) != 0)) {
+      IDS_HDT_CONSOLE (GNB_TRACE, "Error!! FP2 GFX Wrpper cannot use both phy#\n");
+      Status = AGESA_ERROR;
+      PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
+      PutEventLog (
+        AGESA_ERROR,
+        GNB_EVENT_INVALID_LANES_CONFIGURATION,
+        (LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane),
+        (LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane),
+        0,
+        0,
+        GnbLibGetHeader (Pcie)
+        );
+
+      ASSERT (FALSE);
+    }
+  }
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2x8CheckCallbackTN Exit\n");
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * TN FP2 PCIE critera check
+ *
+ *
+ *
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ */
+
+
+STATIC AGESA_STATUS
+PcieFP2CriteriaTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS              Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Enter\n");
+
+  // PACKAGE_TYPE_FP2    1
+  // PACKAGE_TYPE_FS1r2  2
+  // PACKAGE_TYPE_FM2    4
+  if (LibAmdGetPackageType (GnbLibGetHeader (Pcie)) != PACKAGE_TYPE_FP2) {
+    return AGESA_SUCCESS;
+  }
+  // FP2 force gen1
+  Pcie->PsppPolicy = PsppPowerSaving;
+  // FP2 only use x8 on the same PHY
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieFP2x8CheckCallbackTN, NULL, Pcie);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Exit\n");
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RX offset cancellation enablement
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper configuration data area
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+STATIC VOID
+PcieOffsetCancelCalibration (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT32                LaneBitmap;
+  D0F0xBC_x1F39C_STRUCT D0F0xBC_x1F39C;
+
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper);
+  if ((Wrapper->WrapId != GFX_WRAP_ID) && (Wrapper->WrapId != GPP_WRAP_ID)) {
+    return;
+  }
+
+  if (LaneBitmap != 0) {
+    D0F0xBC_x1F39C.Value = 0;
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + Wrapper->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + Wrapper->StartPhyLane;
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Wrapper)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Wrapper)->Address,
+      SMC_MSG_PHY_LN_ON,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PcieInitSrbmCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
+  PcieOffsetCancelCalibration (Wrapper, Pcie);
+  PciePifApplyGanging (Wrapper, Pcie);
+  PciePhyApplyGanging (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PHY Pll Personality Init Callback
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+STATIC AGESA_STATUS
+PciePhyLetPllPersonalityInitCallbackTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      VOID                  *Buffer,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Enter\n");
+  PciePifPllPowerControl (PowerDownPifs, Wrapper, Pcie);
+  PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieSetPhyPersonalityTN (Wrapper, Pcie);
+  PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePifPllPowerControl (PowerUpPifs, Wrapper, Pcie);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyLetPllPersonalityInitCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Init prior training.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+AGESA_STATUS
+STATIC
+PcieEarlyInitCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  BOOLEAN       CoreConfigChanged;
+  BOOLEAN       PllConfigChanged;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Enter\n");
+  CoreConfigChanged = FALSE;
+  PllConfigChanged = FALSE;
+  PcieTopologyPrepareForReconfig (Wrapper, Pcie);
+  Status = PcieTopologySetCoreConfig (Wrapper, &CoreConfigChanged, Pcie);
+  ASSERT (Status == AGESA_SUCCESS);
+  PcieTopologyApplyLaneMux (Wrapper, Pcie);
+  PciePifSetRxDetectPowerMode (Wrapper, Pcie);
+  PciePifSetLs2ExitTime (Wrapper, Pcie);
+  PcieTopologySelectMasterPll (Wrapper, &PllConfigChanged, Pcie);
+  if (CoreConfigChanged || PllConfigChanged) {
+    PcieTopologyExecuteReconfigV4 (Wrapper, Pcie);
+  }
+  PcieTopologyCleanUpReconfig (Wrapper, Pcie);
+  PcieTopologySetLinkReversalV4 (Wrapper, Pcie);
+
+  if (Wrapper->Features.PowerOffUnusedPlls != 0) {
+    PciePifPllPowerDown (
+      PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC | LANE_TYPE_DDI_PHY_NATIVE, Wrapper),
+      Wrapper,
+      Pcie
+      );
+    PciePifPllInitForDdi (Wrapper, Pcie);
+    PciePwrPowerDownDdiPllsV4 (Wrapper, Pcie);
+  }
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieSetDdiOwnPhyV4 (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePhyAvertClockPickers (Wrapper, Pcie);
+  PcieEarlyCoreInitTN (Wrapper, Pcie);
+  PcieSetSsidV4 (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie);
+  if (PcieConfigIsPcieWrapper (Wrapper)) {
+    PcieSetDllCapTN (Wrapper, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackTN Exit [%x]\n", Status);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Init
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PcieEarlyInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS        Status;
+  AGESA_STATUS        AgesaStatus;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieFP2CriteriaTN (Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieEarlyStaticInitTN (Pcie);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieOscInitTN (Pcie);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  PcieSetVoltageTN (PcieGen1, Pcie);
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieEarlyPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n");
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie);
+  PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
+  PcieSetLinkWidthCap (Engine, Pcie);
+  PcieCompletionTimeout (Engine, Pcie);
+  PcieLinkSetSlotCap (Engine, Pcie);
+  PcieLinkInitHotplug (Engine, Pcie);
+  //PciePhyChannelCharacteristic (Engine, Pcie);
+  if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
+      (Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
+       Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
+       Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
+    ASSERT (!PcieConfigIsSbPcieEngine (Engine));
+    //
+    //  Pass endpoint tstaus in scratch
+    //
+    PciePortRegisterRMW (
+      Engine,
+      DxF0xE4_x01_ADDRESS,
+      0x1,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
+  }
+  if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PcieEarlyPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
+  if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+    Pcie->TrainingExitState = LinkStateResetExit;
+  }
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieEarlyPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Early Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+
+AGESA_STATUS
+PcieEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          Status;
+  AGESA_STATUS          AgesaStatus;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  AgesaStatus = AGESA_SUCCESS;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Enter\n");
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PcieEarlyInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieEarlyPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
new file mode 100644
index 0000000000..f0cf287a7f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieEnvInitTN.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "S3SaveState.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Env Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PcieEnvInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  S3_SAVE_DISPATCH (StdHeader, PcieLateRestoreTNS3Script_ID, 0, NULL);
+  return  AGESA_SUCCESS;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
new file mode 100644
index 0000000000..3d00bdb6e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.c
@@ -0,0 +1,639 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * TN specific PCIe configuration data services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Ids.h"
+#include  "heapManager.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbFuseTable.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbCommonLib.h"
+#include  "GnbSbLib.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbNbInitLibV1.h"
+#include  "PcieComplexDataTN.h"
+#include  "PcieLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+PCIE_LINK_SPEED_CAP
+PcieGetLinkSpeedCapTN (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Control port visibility in PCI config space
+ *
+ *
+ * @param[in]  Control         Make port Hide/Unhide ports
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+VOID
+PciePortsVisibilityControlTN (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  )
+{
+  PCIe_SILICON_CONFIG *Silicon;
+  Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  ASSERT (Silicon != NULL);
+  switch (Control) {
+  case UnhidePorts:
+    PcieSiliconUnHidePorts (Silicon, Pcie);
+    break;
+  case HidePorts:
+    PcieSiliconHidePorts (Silicon, Pcie);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down inactive lanes
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper config descriptor
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+
+VOID
+PciePowerDownPllInL1TN (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  )
+{
+
+  UINT32              LaneBitmapForPllOffInL1;
+  UINT32              ActiveLaneBitmap;
+  UINT8               PllPowerUpLatency;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Enter\n");
+  ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Wrapper);
+  if (ActiveLaneBitmap != 0) {
+    PllPowerUpLatency = PciePifGetPllPowerUpLatencyTN (Wrapper, Pcie);
+    LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie);
+    if ((LaneBitmapForPllOffInL1 != 0) && ((ActiveLaneBitmap & LaneBitmapForPllOffInL1) == ActiveLaneBitmap)) {
+      LaneBitmapForPllOffInL1 &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PHY_NATIVE_ALL, 0, Wrapper);
+      LaneBitmapForPllOffInL1 |= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL, 0, Wrapper);
+      PciePifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie);
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerDownPllInL1TN Exit\n");
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request boot up voltage
+ *
+ *
+ *
+ * @param[in]  LinkCap             Global GEN capability
+ * @param[in]  Pcie                Pointer to PCIe configuration data area
+ */
+VOID
+PcieSetVoltageTN (
+  IN      PCIE_LINK_SPEED_CAP   LinkCap,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                      TargetVid;
+  D0F0xBC_xE010705C_STRUCT   D0F0xBC_xE010705C;
+  GMMx63C_STRUCT             GMMx63C;
+  GMMx640_STRUCT             GMMx640;
+  UINT8                      MinVidIndex;
+  D0F0xBC_xE0001008_STRUCT   D0F0xBC_xE0001008;
+  UINT8                      SclkVid[4];
+  UINT8                      Index;
+  PP_FUSE_ARRAY              *PpFuseArray;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Enter\n");
+  PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie));
+  if (PpFuseArray == NULL) {
+    GnbRegisterReadTN (D0F0xBC_xE0001008_TYPE, D0F0xBC_xE0001008_ADDRESS, &D0F0xBC_xE0001008, 0, GnbLibGetHeader (Pcie));
+    SclkVid[0] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid0;
+    SclkVid[1] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid1;
+    SclkVid[2] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid2;
+    SclkVid[3] = (UINT8) D0F0xBC_xE0001008.Field.SClkVid3;
+    GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010705C_ADDRESS, &D0F0xBC_xE010705C, 0, GnbLibGetHeader (Pcie));
+    Index = (UINT8) D0F0xBC_xE010705C.Field.PcieGen2Vid;
+  } else {
+    SclkVid[0] = PpFuseArray->SclkVid[0];
+    SclkVid[1] = PpFuseArray->SclkVid[1];
+    SclkVid[2] = PpFuseArray->SclkVid[2];
+    SclkVid[3] = PpFuseArray->SclkVid[3];
+    Index = PpFuseArray->PcieGen2Vid;
+  }
+  if (LinkCap > PcieGen1) {
+    ASSERT (SclkVid[Index] != 0);
+    TargetVid = SclkVid[Index];
+  } else {
+
+    MinVidIndex = 0;
+    for (Index = 0; Index < 4; Index++) {
+      if (SclkVid[Index] > SclkVid[MinVidIndex]) {
+        MinVidIndex = (UINT8) Index;
+      }
+    }
+    ASSERT (SclkVid[MinVidIndex] != 0);
+    TargetVid = SclkVid[MinVidIndex];
+  }
+  IDS_HDT_CONSOLE (PCIE_MISC, "  Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid);
+
+  GnbRegisterReadTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, 0, GnbLibGetHeader (Pcie));
+  //Wait for voltage change to complete before it can issue next voltage change request
+  do {
+    GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie));
+  } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq);
+  //Enable voltage client
+  if (LinkCap == PcieGen1) {
+    GMMx63C.Field.VoltageChangeEn = 0;
+  } else {
+    GMMx63C.Field.VoltageChangeEn = 1;
+  }
+  GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  //Program level and toggle request
+  GMMx63C.Field.VoltageLevel = TargetVid;
+  GMMx63C.Field.VoltageChangeReq = !GMMx63C.Field.VoltageChangeReq;
+  GnbRegisterWriteTN (GMMx63C_TYPE, GMMx63C_ADDRESS, &GMMx63C, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  //Wait for voltage change to complete before it can issue next voltage change request
+  do {
+    GnbRegisterReadTN (GMMx640_TYPE, GMMx640_ADDRESS, &GMMx640, 0, GnbLibGetHeader (Pcie));
+  } while (GMMx640.Field.VoltageChangeAck != GMMx63C.Field.VoltageChangeReq);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PLL power up latency
+ *
+ *
+ * @param[in]  Wrapper     Pointer to Wrapper config descriptor
+ * @param[in]  Pcie        Pointer to PICe configuration data area
+ * @retval                 Pll wake up latency in us
+ */
+UINT8
+PciePifGetPllPowerUpLatencyTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  return 35;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get max link speed capability supported by this port
+ *
+ *
+ *
+ * @param[in]  Flags              See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
+ * @param[in]  Engine             Pointer to engine config descriptor
+ * @retval     PcieGen1/PcieGen2  Max supported link gen capability
+ */
+PCIE_LINK_SPEED_CAP
+PcieGetLinkSpeedCapTN (
+  IN       UINT32                Flags,
+  IN       PCIe_ENGINE_CONFIG    *Engine
+  )
+{
+  PCIE_LINK_SPEED_CAP   LinkSpeedCapability;
+  TN_COMPLEX_CONFIG     *ComplexData;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+
+  ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen);
+  Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
+  LinkSpeedCapability = PcieGen2;
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
+  if (ComplexData->FmSilicon.OscMode == OscRO || ComplexData->FmSilicon.OscMode == OscLC || ComplexData->FmSilicon.OscMode == OscDefault) {
+    LinkSpeedCapability = PcieGen2;
+  } else {
+    LinkSpeedCapability = PcieGen1;
+  }
+  if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) {
+    Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability;
+  }
+  if (Pcie->PsppPolicy == PsppPowerSaving) {
+    LinkSpeedCapability = PcieGen1;
+  }
+  if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) {
+    LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
+  }
+  if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
+    if ((Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) {
+      LinkSpeedCapability = PcieGen1;
+    }
+  }
+  return LinkSpeedCapability;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set PLL personality
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to wrapper config descriptor
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+VOID
+PcieSetPhyPersonalityTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Phy;
+  UINT8                   Mode;
+  if (Wrapper->WrapId == GFX_WRAP_ID || Wrapper->WrapId == DDI_WRAP_ID || Wrapper->WrapId == DDI2_WRAP_ID) {
+    for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
+      if (Wrapper->WrapId == GFX_WRAP_ID) {
+        Mode = (Phy == 0)? 0x1 : 0;
+      } else {
+        Mode = 0x2;
+      }
+      PcieRegisterWriteField (
+        Wrapper,
+        PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2005_ADDRESS),
+        D0F0xE4_PHY_2005_PllMode_OFFSET,
+        D0F0xE4_PHY_2005_PllMode_WIDTH,
+        Mode,
+        FALSE,
+        Pcie
+        );
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * DCC recalibration
+ *
+ *
+ *
+ * @param[in]     Wrapper           Pointer to internal configuration data area
+ * @param[in,out] Buffer            Pointer to buffer
+ * @param[in]     Pcie              Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieForceDccRecalibrationCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePhyForceDccRecalibration (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare for Osc switch
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscPifInitPrePowerdownCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePifFullPowerStateControl (PowerDownPifs, Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    DisableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_SB_CORE_CONFIG, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PciePifSetPllRampTime (LongRampup, Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Do Osc switch
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscInitPllModeCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  TN_COMPLEX_CONFIG         *ComplexData;
+  TN_PCIe_SILICON_CONFIG    *FmSilicon;
+  UINT8                     Phy;
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetParentSilicon (Wrapper);
+  ASSERT (ComplexData != NULL);
+  FmSilicon = &ComplexData->FmSilicon;
+  if (Wrapper->WrapId == GFX_WRAP_ID) {
+    Phy = 1;
+  } else if (Wrapper->WrapId == GPP_WRAP_ID) {
+    Phy = 0;
+  } else {
+    ASSERT (FALSE);
+    return AGESA_ERROR;
+  }
+  switch (FmSilicon->OscMode) {
+  case  OscLC:
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_IsLc_OFFSET,
+      D0F0xE4_PHY_2002_IsLc_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    break;
+  case  OscRO:
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_RoCalEn_OFFSET,
+      D0F0xE4_PHY_2002_RoCalEn_WIDTH,
+      0x0,
+      FALSE,
+      Pcie
+      );
+    PcieRegisterWriteField (
+      Wrapper,
+      PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_2002_ADDRESS),
+      D0F0xE4_PHY_2002_RoCalEn_OFFSET,
+      D0F0xE4_PHY_2002_RoCalEn_WIDTH,
+      0x1,
+      FALSE,
+      Pcie
+      );
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post Osc init
+ *
+ *
+ *
+ * @param[in]  Wrapper             Pointer to Wrapper config descriptor
+ * @param[in]  Buffer              Pointer to buffer
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+STATIC AGESA_STATUS
+PcieOscPifInitPostPowerdownCallback (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PcieWrapSetTxS1CtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PcieTopologyLaneControl (
+    EnableLanes,
+    PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, 0, Wrapper),
+    Wrapper,
+    Pcie
+    );
+  PcieWrapSetTxOffCtrlForLaneMux (Wrapper, Pcie);
+  PciePollPifForCompeletion (Wrapper, Pcie);
+  PciePifSetPllRampTime (NormalRampup, Wrapper, Pcie);
+  PciePifFullPowerStateControl (PowerUpPifs, Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare PHY for Gen2
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ */
+
+VOID
+PcieOscInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  TN_COMPLEX_CONFIG         *ComplexData;
+  TN_PCIe_SILICON_CONFIG    *FmSilicon;
+  D0F0xE4_WRAP_FFF1_STRUCT  D0F0xE4_WRAP_FFF1;
+  AGESA_STATUS              Status;
+  UINT8                     SaveSbLinkAspm;
+  UINT32                    Value;
+
+  Value = 0;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Enter\n");
+  ComplexData = (TN_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
+  ASSERT (ComplexData != NULL);
+  FmSilicon = &ComplexData->FmSilicon;
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "  OSC Mode - %s\n",
+    (FmSilicon->OscMode == OscFuses) ? "Fuses" : (
+    (FmSilicon->OscMode == OscRO) ? "RO" : (
+    (FmSilicon->OscMode == OscLC) ? "LC" : (
+    (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown")))
+    );
+
+  if (FmSilicon->OscMode == OscFuses) {
+    D0F0xE4_WRAP_FFF1.Value = PcieRegisterRead (
+                                &ComplexData->GppWrapper,
+                                WRAP_SPACE (ComplexData->GppWrapper.WrapId, D0F0xE4_WRAP_FFF1_ADDRESS),
+                                Pcie
+                                );
+
+    if (D0F0xE4_WRAP_FFF1.Field.ROSupportGen2) {
+      FmSilicon->OscMode = OscRO;
+    } else if (D0F0xE4_WRAP_FFF1.Field.LcSupportGen2) {
+      FmSilicon->OscMode = OscLC;
+    } else {
+      FmSilicon->OscMode = OscDefault;
+    }
+
+    IDS_HDT_CONSOLE (GNB_TRACE, "  OSC Mode From Fuses - %s\n",
+      (FmSilicon->OscMode == OscFuses) ? "Fuses" : (
+      (FmSilicon->OscMode == OscRO) ? "RO" : (
+      (FmSilicon->OscMode == OscLC) ? "LC" : (
+      (FmSilicon->OscMode == OscDefault) ? "Skip" : "Unknown")))
+      );
+  }
+  if (FmSilicon->OscMode != OscDefault) {
+
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscPifInitPrePowerdownCallback,
+      NULL,
+      Pcie
+      );
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscInitPllModeCallback,
+      NULL,
+      Pcie
+      );
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieForceDccRecalibrationCallbackTN,
+      NULL,
+      Pcie
+      );
+
+    SaveSbLinkAspm = ComplexData->Port8.Type.Port.PortData.LinkAspm;
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmL1;
+
+    Status = SbPcieLinkAspmControl (&ComplexData->Port8, Pcie);
+    ASSERT (Status == AGESA_SUCCESS);
+#ifdef  USE_L1_POLLING
+    //Use L1 Entry pooling
+    PciePollLinkForL1Entry (&ComplexData->Port8, Pcie);
+#else
+    {
+      D0F0xBC_x1F630_STRUCT  D0F0xBC_x1F630;
+
+      GnbRegisterReadTN (D0F0xBC_x1F630_TYPE,  D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie));
+      D0F0xBC_x1F630.Field.RECONF_WAIT = 60;
+      GnbRegisterWriteTN (D0F0xBC_x1F630_TYPE,  D0F0xBC_x1F630_ADDRESS, &D0F0xBC_x1F630.Value, 0, GnbLibGetHeader (Pcie));
+
+      GnbSmuServiceRequestV4 (
+        ComplexData->Silicon.Address,
+        SMC_MSG_PCIE_PLLSWITCH,
+        0,
+        GnbLibGetHeader (Pcie)
+      );
+    }
+#endif
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = AspmDisabled;
+
+    SbPcieLinkAspmControl (&ComplexData->Port8, Pcie);
+    PciePollLinkForL0Exit (&ComplexData->Port8, Pcie);
+
+    ComplexData->Port8.Type.Port.PortData.LinkAspm = SaveSbLinkAspm;
+
+    PcieConfigRunProcForAllWrappers (
+      DESCRIPTOR_PCIE_WRAPPER,
+      PcieOscPifInitPostPowerdownCallback,
+      NULL,
+      Pcie
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieOscInitTN Exit\n");
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h
new file mode 100644
index 0000000000..1f65ce2ecf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieLibTN.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * TN specific PCIe configuration data services
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+
+#ifndef _PCIELIBTN_H_
+#define _PCIELIBTN_H_
+
+VOID
+PciePortsVisibilityControlTN (
+  IN      PCIE_PORT_VISIBILITY    Control,
+  IN      PCIe_PLATFORM_CONFIG    *Pcie
+  );
+
+VOID
+PciePowerDownPllInL1TN (
+  IN       PCIe_WRAPPER_CONFIG    *Wrapper,
+  IN       PCIe_PLATFORM_CONFIG   *Pcie
+  );
+
+VOID
+PcieSetVoltageTN (
+  IN      PCIE_LINK_SPEED_CAP   LinkCap,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+UINT8
+PciePifGetPllPowerUpLatencyTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieSetPhyPersonalityTN (
+  IN      PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+VOID
+PcieOscInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
new file mode 100644
index 0000000000..2a751be1b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c
@@ -0,0 +1,283 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "GnbFamServices.h"
+#include  "PcieLibTN.h"
+#include  "PciePowerGateTN.h"
+#include  "PciePortServicesV4.h"
+#include  "PcieMaxPayloadV4.h"
+#include  "OptionGnb.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS  GnbBuildOptions;
+extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieMidPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie);
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
+    PcieEnableSlotPowerLimit (Engine, Pcie);
+    if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
+      PcieInitPortForIommuV4 (Engine, Pcie);
+    }
+  }
+  PcieEnableAspm (Engine,  Pcie);
+  if (GnbBuildOptions.CfgMaxPayloadEnable) {
+    PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie));
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PcieMidPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS         Status;
+  PCIE_LINK_SPEED_CAP  GlobalSpeedCap;
+
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PcieMidPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+
+  GlobalSpeedCap = PcieUtilGlobalGenCapability (
+                     PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
+                     Pcie
+                     );
+
+
+  PcieSetVoltageTN (GlobalSpeedCap, Pcie);
+
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Per wrapper Pcie Late Init.
+ *
+ *
+ * @param[in]  Wrapper         Pointer to wrapper configuration descriptor
+ * @param[in]  Buffer          Pointer buffer
+ * @param[in]  Pcie            Pointer to global PCIe configuration
+ */
+AGESA_STATUS
+STATIC
+PcieMidInitCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG           *Wrapper,
+  IN OUT   VOID                          *Buffer,
+  IN       PCIe_PLATFORM_CONFIG          *Pcie
+  )
+{
+  PciePwrPowerDownUnusedLanes (Wrapper, Pcie);
+  PciePowerDownPllInL1TN (Wrapper, Pcie);
+  PciePwrClockGatingV4 (Wrapper, Pcie);
+  PcieLockRegisters (Wrapper, Pcie);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Late Init
+ *
+ *   Late PCIe initialization
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PcieMidInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+
+  Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  Status = PciePowerGateTN (Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Mid Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PcieMidInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PcieMidPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieMidInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
new file mode 100644
index 0000000000..b30e92b437
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c
@@ -0,0 +1,498 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63818 $   @e \$Date: 2012-01-09 03:02:03 -0600 (Mon, 09 Jan 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieTrainingV1.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbPcieInitLibV4.h"
+#include  "PcieLibTN.h"
+#include  "GnbRegistersTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PciePostEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PciePostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+AGESA_STATUS
+PciePostS3InterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  );
+
+VOID
+PcieLateRestoreInitTNS3Script (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  IN      UINT16                          ContextLength,
+  IN      VOID*                           Context
+  );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePostPortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP LinkSpeedCapability;
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+  if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+    PcieLinkSafeMode (Engine, Pcie);
+  }
+  LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
+  PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
+  if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !PcieConfigIsSbPcieEngine (Engine)) {
+    PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie);
+    PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+  }
+  if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+    PcieForceCompliance (Engine, Pcie);
+    PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePostS3PortInitCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP       LinkSpeedCapability;
+  PCIE_LINK_TRAINING_STATE  State;
+
+  ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+
+  LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
+  PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
+
+  if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+    PcieLinkSafeMode (Engine, Pcie);
+  }
+
+  if (!PcieConfigIsSbPcieEngine (Engine)) {
+    //
+    // General Port
+    //
+    State = LinkStateDeviceNotPresent;
+    if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) {
+      //
+      // Non hotplug device: we only check status from previous boot
+      //
+      if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+        State = LinkStateResetExit;
+      }
+    } else {
+      UINT32  PcieScratch;
+      //
+      //  Get endpoint staus from scratch
+      //
+      PcieScratch = PciePortRegisterRead (Engine, DxF0xE4_x01_ADDRESS, Pcie);
+      //
+      // Hotplug device: we check ep status if reported
+      //
+      if ((PcieScratch & 0x1) == 0) {
+        State = LinkStateResetExit;
+      }
+    }
+    //
+    // For compialnce we always leave link in enabled state
+    //
+    if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) {
+      State = LinkStateResetExit;
+    }
+    PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+  } else {
+    //
+    // SB port
+    //
+    State = LinkStateTrainingSuccess;
+  }
+  PcieTrainingSetPortState (Engine, State, FALSE, Pcie);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostEarlyPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  // Distributed Training started at PciePortInit complete it now to get access to PCIe devices
+  if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+    Pcie->TrainingExitState = LinkStateTrainingCompleted;
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostPortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PciePostPortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in]   Pcie            Pointer to global PCIe configuration
+ * @retval      AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePostS3PortInitTN (
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    PciePostS3PortInitCallbackTN,
+    NULL,
+    Pcie
+    );
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Init
+ *
+ *
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ * @retval     AGESA_ERROR         Topology can not be mapped
+ */
+
+AGESA_STATUS
+STATIC
+PciePostInitTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  PCIE_LINK_SPEED_CAP  GlobalSpeedCap;
+
+  GlobalSpeedCap = PcieUtilGlobalGenCapability (
+                     PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
+                     Pcie
+                     );
+
+
+  PcieSetVoltageTN (GlobalSpeedCap, Pcie);
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostEarlyInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostEarlyPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostInterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PciePostPortInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in]  StdHeader  Standard configuration header
+ * @retval     AGESA_STATUS
+ */
+AGESA_STATUS
+PciePostS3InterfaceTN (
+  IN      AMD_CONFIG_PARAMS               *StdHeader
+  )
+{
+  AGESA_STATUS          AgesaStatus;
+  AGESA_STATUS          Status;
+  PCIe_PLATFORM_CONFIG  *Pcie;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Enter\n");
+  AgesaStatus = AGESA_SUCCESS;
+  Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+  AGESA_STATUS_UPDATE (Status, AgesaStatus);
+  if (Status == AGESA_SUCCESS) {
+    PciePortsVisibilityControlTN (UnhidePorts, Pcie);
+
+    Status = PciePostInitTN (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+      Status = PciePostS3PortInitTN (Pcie);
+    } else {
+      Status = PciePostPortInitTN (Pcie);
+    }
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    Status = PcieTraining (Pcie);
+    AGESA_STATUS_UPDATE (Status, AgesaStatus);
+    ASSERT (Status == AGESA_SUCCESS);
+
+    PciePortsVisibilityControlTN (HidePorts, Pcie);
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceTN Exit [0x%x]\n", AgesaStatus);
+  return  AgesaStatus;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe S3 restore
+ *
+ *
+ *
+ * @param[in]  StdHeader      Standard configuration header
+ * @param[in]  ContextLength  Context Length (not used)
+ * @param[in]  Context        Context pointer (not used)
+ */
+VOID
+PcieLateRestoreInitTNS3Script (
+  IN      AMD_CONFIG_PARAMS               *StdHeader,
+  IN      UINT16                          ContextLength,
+  IN      VOID*                           Context
+  )
+{
+  PciePostS3InterfaceTN (StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
new file mode 100644
index 0000000000..4197fd842c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c
@@ -0,0 +1,383 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe power gate initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "amdlib.h"
+#include  "Ids.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "OptionGnb.h"
+#include  "GnbPcieConfig.h"
+#include  "GnbPcieFamServices.h"
+#include  "GnbPcieInitLibV1.h"
+#include  "GnbNbInitLibV4.h"
+#include  "GnbRegistersTN.h"
+#include  "GnbRegisterAccTN.h"
+#include  "Filecode.h"
+#define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern GNB_BUILD_OPTIONS      GnbBuildOptions;
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Report used lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePowerGateReportActiveLanesCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  UINT32                  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, 0, Engine);
+  if (LaneBitmap != 0) {
+    D0F0xBC_x1F39C.Value = 0;
+    D0F0xBC_x1F39C.Field.Tx = 0;
+    D0F0xBC_x1F39C.Field.Rx = 0;
+    D0F0xBC_x1F39C.Field.Core = 0;
+    D0F0xBC_x1F39C.Field.SkipPhy = 1;
+    D0F0xBC_x1F39C.Field.SkipCore = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    if (PcieConfigIsPcieEngine (Engine) && PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine) == PcieGen2) {
+      D0F0xBC_x1F610_STRUCT  D0F0xBC_x1F610;
+      UINT32                 Gen2LaneBitmap;
+      Gen2LaneBitmap = ((1 << (D0F0xBC_x1F39C.Field.UpperLaneID - D0F0xBC_x1F39C.Field.LowerLaneID + 1)) - 1) << D0F0xBC_x1F39C.Field.LowerLaneID;
+      GnbRegisterReadTN (D0F0xBC_x1F610_TYPE, D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, 0, GnbLibGetHeader (Pcie));
+      D0F0xBC_x1F610.Field.GFXH |= (Gen2LaneBitmap >> 16) & 0xFF;
+      D0F0xBC_x1F610.Field.GFXL |= (Gen2LaneBitmap >> 8) & 0xFF;
+      D0F0xBC_x1F610.Field.GPPSB |= (Gen2LaneBitmap  & 0xFF );
+      GnbRegisterWriteTN (D0F0xBC_x1F610_TYPE,  D0F0xBC_x1F610_ADDRESS, &D0F0xBC_x1F610.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    }
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_ON,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateReportActiveLanesCallbackTN Exit\n");
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Wrapper         Pointer to wrapper configuration
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ * @retval          AGESA_SUCCESS
+ *
+ */
+
+AGESA_STATUS
+STATIC
+PciePowerGatePowerDownUnusedLanesCallbackTN (
+  IN       PCIe_WRAPPER_CONFIG   *Wrapper,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   Index;
+  UINTN                   State;
+  UINT32                  LaneBitmap;
+  UINT16                  StartLane;
+  UINT16                  EndLane;
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Enter\n");
+
+  LaneBitmap = PcieUtilGetWrapperLaneBitMap (
+                 LANE_TYPE_PHY_NATIVE_ALL,
+                 LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG,
+                 Wrapper
+                 );
+  IDS_HDT_CONSOLE (GNB_TRACE, " Lane Bitmap 0x%x\n", LaneBitmap);
+  if (LaneBitmap != 0) {
+    State = 0;
+    StartLane = 0;
+    EndLane = 0;
+    for (Index = 0; Index <= (LibAmdBitScanReverse (LaneBitmap) + 1); Index++) {
+      if ((State == 0) && ((LaneBitmap & (1 << Index)) != 0)) {
+        StartLane = Index;
+        State = 1;
+      } else if ((State == 1) && ((LaneBitmap & (1 << Index)) == 0)) {
+        EndLane = Index - 1;
+        State = 0;
+        GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+        D0F0xBC_x1F39C.Field.Tx = 1;
+        D0F0xBC_x1F39C.Field.Rx = 1;
+        D0F0xBC_x1F39C.Field.Core = 1;
+        D0F0xBC_x1F39C.Field.LowerLaneID = StartLane + Wrapper->StartPhyLane;
+        D0F0xBC_x1F39C.Field.UpperLaneID = EndLane + Wrapper->StartPhyLane;
+        IDS_HDT_CONSOLE (
+          PCIE_MISC,
+          "  LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+          D0F0xBC_x1F39C.Field.LowerLaneID,
+          D0F0xBC_x1F39C.Field.UpperLaneID,
+          D0F0xBC_x1F39C.Field.Tx,
+          D0F0xBC_x1F39C.Field.Rx,
+          D0F0xBC_x1F39C.Field.Core
+          );
+        GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+        GnbSmuServiceRequestV4 (
+          PcieConfigGetParentSilicon (Wrapper)->Address,
+          SMC_MSG_PHY_LN_OFF,
+          GNB_REG_ACC_FLAG_S3SAVE,
+          GnbLibGetHeader (Pcie)
+          );
+      }
+    }
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownUnusedLanesCallbackTN Exit\n");
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power down unused lanes
+ *
+ *
+ *
+ *
+ * @param[in]       Engine          Pointer to engine config descriptor
+ * @param[in, out]  Buffer          Not used
+ * @param[in]       Pcie            Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePowerGatePowerDownLanesCallbackTN (
+  IN       PCIe_ENGINE_CONFIG    *Engine,
+  IN OUT   VOID                  *Buffer,
+  IN       PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  UINT32                  LaneBitmap;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Enter\n");
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG, LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, Engine);
+  if (LaneBitmap != 0) {
+    GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.Core = 0;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  PCIe Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE_ACTIVE, 0, Engine);
+  if (LaneBitmap != 0) {
+    GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+    D0F0xBC_x1F39C.Field.Tx = 1;
+    D0F0xBC_x1F39C.Field.Rx = 1;
+    D0F0xBC_x1F39C.Field.Core = 1;
+    D0F0xBC_x1F39C.Field.UpperLaneID = LibAmdBitScanReverse (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    D0F0xBC_x1F39C.Field.LowerLaneID = LibAmdBitScanForward (LaneBitmap) + PcieConfigGetParentWrapper (Engine)->StartPhyLane;
+    IDS_HDT_CONSOLE (
+      PCIE_MISC,
+      "  DDI Lanes LowerLaneID - %02d UpperLaneID - %02d Tx - %d  Rx - %d Core - %d Exit\n",
+      D0F0xBC_x1F39C.Field.LowerLaneID,
+      D0F0xBC_x1F39C.Field.UpperLaneID,
+      D0F0xBC_x1F39C.Field.Tx,
+      D0F0xBC_x1F39C.Field.Rx,
+      D0F0xBC_x1F39C.Field.Core
+      );
+    GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+    GnbSmuServiceRequestV4 (
+      PcieConfigGetParentSilicon (Engine)->Address,
+      SMC_MSG_PHY_LN_OFF,
+      GNB_REG_ACC_FLAG_S3SAVE,
+      GnbLibGetHeader (Pcie)
+      );
+  }
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePowerDownLanesCallbackTN Exit\n");
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Pcie Power gate init
+ *
+ *   Late PCIe initialization
+ *
+ * @param[in]  Pcie                Pointer to global PCIe configuration
+ * @retval     AGESA_SUCCESS       Topology successfully mapped
+ */
+
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  UINT8                   PowerGatingFlags;
+  D0F0xBC_x1F39C_STRUCT   D0F0xBC_x1F39C;
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Enter\n");
+  PowerGatingFlags = GnbBuildOptions.CfgPciePowerGatingFlags;
+  // Report used lanes
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE,
+    PciePowerGateReportActiveLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+
+  IDS_OPTION_HOOK (IDS_GNB_PCIE_POWER_GATING, &PowerGatingFlags, GnbLibGetHeader (Pcie));
+
+  // Update flags
+  GnbRegisterReadTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, 0, GnbLibGetHeader (Pcie));
+  if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_CORE) == 0) {
+    D0F0xBC_x1F39C.Field.SkipCore = 0;
+  }
+  if ((PowerGatingFlags & PCIE_POWERGATING_SKIP_PHY) == 0) {
+    D0F0xBC_x1F39C.Field.SkipPhy = 0;
+  }
+  GnbRegisterWriteTN (D0F0xBC_x1F39C_TYPE,  D0F0xBC_x1F39C_ADDRESS, &D0F0xBC_x1F39C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
+  // Power down unused lanes
+  PcieConfigRunProcForAllWrappers (
+    DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER,
+    PciePowerGatePowerDownUnusedLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+  //Power down hotplug lanes
+  PcieConfigRunProcForAllEngines (
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_DDI_ENGINE,
+    PciePowerGatePowerDownLanesCallbackTN,
+    NULL,
+    Pcie
+    );
+  IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateTN Exit\n");
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
new file mode 100644
index 0000000000..b8d2116a96
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe power gate initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+#ifndef _PCIEPOWERGATETN_H_
+#define _PCIEPOWERGATETN_H_
+
+AGESA_STATUS
+PciePowerGateTN (
+  IN      PCIe_PLATFORM_CONFIG  *Pcie
+  );
+
+#endif
+
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
new file mode 100644
index 0000000000..faa2fa8f80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
@@ -0,0 +1,258 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PCIe late post initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 65061 $   @e \$Date: 2012-02-06 23:48:39 -0600 (Mon, 06 Feb 2012) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+*
+* AMD is granting you permission to use this software (the Materials)
+* pursuant to the terms and conditions of your Software License Agreement
+* with AMD.  This header does *NOT* give you permission to use the Materials
+* or any rights under AMD's intellectual property.  Your use of any portion
+* of these Materials shall constitute your acceptance of those terms and
+* conditions.  If you do not agree to the terms and conditions of the Software
+* License Agreement, please do not use any portion of these Materials.
+*
+* CONFIDENTIALITY:  The Materials and all other information, identified as
+* confidential and provided to you by AMD shall be kept confidential in
+* accordance with the terms and conditions of the Software License Agreement.
+*
+* LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+* PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+* WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+* MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+* OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+* IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+* INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+* GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+* RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+* THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+* EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+* THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+*
+* AMD does not assume any responsibility for any errors which may appear in
+* the Materials or any other related information provided to you by AMD, or
+* result from use of the Materials or any related information.
+*
+* You agree that you will not reverse engineer or decompile the Materials.
+*
+* NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+* further information, software, technical information, know-how, or show-how
+* available to you.  Additionally, AMD retains the right to modify the
+* Materials at any time, without notice, and is not obligated to provide such
+* modified Materials to you.
+*
+* U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+* "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+* subject to the restrictions as set forth in FAR 52.227-14 and
+* DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+* Government constitutes acknowledgement of AMD's proprietary rights in them.
+*
+* EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+* direct product thereof will be exported directly or indirectly, into any
+* country prohibited by the United States Export Administration Act and the
+* regulations thereunder, without the required authorization from the U.S.
+* government nor will be used for any purpose prohibited by the same.
+* ***************************************************************************
+*
+*/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include  "AGESA.h"
+#include  "Gnb.h"
+#include  "GnbPcie.h"
+#include  "PcieComplexDataTN.h"
+#include  "GnbRegistersTN.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           T A B L E S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
+  {
+    WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS),
+    D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
+    0
+  },
+  {
+    PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (DDI_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  },
+  {
+    PHY_SPACE (DDI2_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
+    D0F0xE4_PHY_2008_VdDetectEn_MASK,
+    0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
+  }
+ };
+
+CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN  = {
+  &PcieInitEarlyTable[0],
+  sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
+};
+
+STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
+  {
+    D0F0xE4_CORE_0020_ADDRESS,
+    D0F0xE4_CORE_0020_CiRcOrderingDis_MASK |
+    D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK,
+    (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0010_ADDRESS,
+    D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK,
+    (0x4 << D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_001C_ADDRESS,
+    D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
+    D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
+    D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
+    (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
+    (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
+    (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0040_ADDRESS,
+    D0F0xE4_CORE_0040_PElecIdleMode_MASK,
+    (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_0002_ADDRESS,
+    D0F0xE4_CORE_0002_HwDebug_0__MASK,
+    (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET)
+  },
+  {
+    D0F0xE4_CORE_00C1_ADDRESS,
+    D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
+    D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
+    (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
+    (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
+  },
+  {
+    D0F0xE4_CORE_00B0_ADDRESS,
+    D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK,
+    (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
+  }
+};
+
+CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN  = {
+  &CoreInitTable[0],
+  sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
+};
+
+
+STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
+  {
+    DxF0xE4_x02_ADDRESS,
+    DxF0xE4_x02_RegsLcAllowTxL1Control_MASK,
+    (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET)
+  },
+  {
+    DxF0xE4_x70_ADDRESS,
+    DxF0xE4_x70_RxRcbCplTimeoutMode_MASK,
+    (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET)
+  },
+  {
+    DxF0xE4_xA0_ADDRESS,
+    DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK | DxF0xE4_xA0_LcL0sInactivity_MASK,
+    (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) |
+    (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) |
+    (0x6 << DxF0xE4_xA0_LcL0sInactivity_OFFSET)
+  },
+  {
+    DxF0xE4_xA1_ADDRESS,
+    DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK,
+    (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET)
+  },
+  {
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK,
+    (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) |
+    (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET)
+  },
+  {
+    DxF0xE4_xA3_ADDRESS,
+    DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK,
+    (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET)
+  },
+  {
+    DxF0xE4_xB1_ADDRESS,
+    DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK,
+    (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) |
+    (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET)
+  }
+};
+
+CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN  = {
+  &PortInitEarlyTable[0],
+  sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
+};
+
+
+STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
+  {
+    DxF0xE4_xA2_ADDRESS,
+    DxF0xE4_xA2_LcDynLanesPwrState_MASK,
+    (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET)
+  },
+  {
+    DxF0xE4_xC0_ADDRESS,
+    DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK,
+    (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET)
+  }
+};
+
+CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN  = {
+  &PortInitMidTable[0],
+  sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
+};
author	zbao <fishbaozi@gmail.com>	2012-07-02 14:19:14 +0800
committer	Patrick Georgi <patrick@georgi-clan.de>	2012-07-03 09:36:35 +0200
commit	7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc (patch)
tree	b0b385455992f0ad3ca6dbbd3266a7a386a80d4f /src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN
parent	78efc4c36c68b51b3e73acdb721a12ec23ed0369 (diff)