diff options
| author | zbao <fishbaozi@gmail.com> | 2012-07-02 14:19:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-03 09:36:35 +0200 |
| commit | 7d94cf93eec15dfb8eef9cd044fe39319d4ee9bc (patch) | |
| tree | b0b385455992f0ad3ca6dbbd3266a7a386a80d4f /src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN | |
| parent | 78efc4c36c68b51b3e73acdb721a12ec23ed0369 (diff) | |
AGESA F15tn: AMD family15 AGESA code for Trinity
AMD AGESA code for trinity.
Change-Id: I847a54b15e8ce03ad5dbc17b95ee6771a9da0592
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN')
29 files changed, 11765 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c new file mode 100644 index 0000000000..77243c2d7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnC6State.c @@ -0,0 +1,224 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity C6 C-state feature support functions. + * + * Provides the functions necessary to initialize the C6 feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFeatures.h" +#include "cpuC6State.h" +#include "cpuApicUtilities.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuEarlyInit.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +F15TnReloadMicrocodePatchAfterMemInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Is C6 supported on this CPU + * + * @param[in] C6Services Pointer to this CPU's C6 family services. + * @param[in] Socket This core's zero-based socket number. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE C6 state is supported. + * @retval FALSE C6 state is not supported. + * + */ +BOOLEAN +STATIC +F15TnIsC6Supported ( + IN C6_FAMILY_SERVICES *C6Services, + IN UINT32 Socket, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + ASSERT (IsFeatureEnabled (CacheFlushOnHalt, PlatformConfig, StdHeader) == TRUE); + // Assuming CFOH is always enabled. + return (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable C6 on a family 15h CPU. + * + * @param[in] C6Services Pointer to this CPU's C6 family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeC6 ( + IN C6_FAMILY_SERVICES *C6Services, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CSTATE_CTRL1_REGISTER CstateCtrl1; + POPUP_PSTATE_REGISTER PopDownPstate; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + + if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { + // Initialize F4x118 + PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + // Set C-state Action Field 0 + CstateCtrl1.PwrGateEnCstAct0 = 1; + CstateCtrl1.PwrOffEnCstAct0 = 1; + CstateCtrl1.NbPwrGate0 = 1; + CstateCtrl1.NbClkGate0 = 1; + CstateCtrl1.SelfRefr0 = 1; + CstateCtrl1.CpuPrbEnCstAct0 = 1; + // Set C-state Action Field 1 + CstateCtrl1.PwrGateEnCstAct1 = 1; + CstateCtrl1.PwrOffEnCstAct1 = 1; + CstateCtrl1.NbPwrGate1 = 1; + CstateCtrl1.NbClkGate1 = 1; + CstateCtrl1.SelfRefr1 = 1; + CstateCtrl1.CpuPrbEnCstAct1 = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + + // Initialize F3xA8[PopDownPstate] = F3xDC[PstateMaxVal] + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &PopDownPstate, StdHeader); + PopDownPstate.PopDownPstate = ClkPwrTimingCtrl2.PstateMaxVal; + LibAmdPciWrite (AccessWidth32, PciAddress, &PopDownPstate, StdHeader); + } + + return AGESA_SUCCESS; +} + +/** + * Reload microcode patch after memory is initialized. + * + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +F15TnReloadMicrocodePatchAfterMemInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LoadMicrocodePatch (StdHeader); +} + +CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support = +{ + 0, + F15TnIsC6Supported, + F15TnInitializeC6, + F15TnReloadMicrocodePatchAfterMemInit +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c new file mode 100644 index 0000000000..0089c04960 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnCpb.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 CPB Initialization + * + * Enables core performance boost. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/F15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "cpuCpb.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for checking whether or not CPB is supported. + * + * @param[in] CpbServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] Socket Zero based socket number to check. + * @param[in] StdHeader Config handle for library and services. + * + * @retval TRUE CPB is supported. + * @retval FALSE CPB is not supported. + * + */ +BOOLEAN +STATIC +F15TnIsCpbSupported ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPB_CTRL_REGISTER CpbControl; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + return (BOOLEAN) (CpbControl.NumBoostStates != 0); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * BSC entry point for for enabling Core Performance Boost. + * + * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG. + * + * @param[in] CpbServices The current CPU's family services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] EntryPoint Current CPU feature dispatch point. + * @param[in] Socket Zero based socket number to check. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeCpb ( + IN CPB_FAMILY_SERVICES *CpbServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN UINT64 EntryPoint, + IN UINT32 Socket, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPB_CTRL_REGISTER CpbControl; + PCI_ADDR PciAddress; + F15_PSTATE_MSR PstateMsrData; + UINT32 Pbx; + + if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + if (CpbControl.NumBoostStates == 0) { + CpbControl.ApmMasterEn = 0; + } else { + CpbControl.ApmMasterEn = 1; + } + LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); + + } else if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader); + if ((CpbControl.BoostSrc == 0) && (CpbControl.NumBoostStates != 0)) { + // If any boosted P-state is still enabled, set BoostSrc = 1. + for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) { + LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader); + if (PstateMsrData.PsEnable == 1) { + CpbControl.BoostSrc = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader); + break; + } + } + } + } + return AGESA_SUCCESS; +} + +CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport = +{ + 0, + F15TnIsCpbSupported, + F15TnInitializeCpb +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c new file mode 100644 index 0000000000..407455b7dc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnEquivalenceTable.c @@ -0,0 +1,155 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Equivalence Table related data + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "amdlib.h" +#include "cpuRegisters.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST UINT16 ROMDATA CpuF15TnMicrocodeEquivalenceTable[] = +{ + 0x6101, 0x6101, + 0x6100, 0x6100 +}; + +// Unencrypted equivalent +STATIC CONST UINT16 ROMDATA CpuF15TnUnEncryptedMicrocodeEquivalenceTable[] = +{ + 0x6101, 0x6901, + 0x6100, 0x6900 +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate microcode patch equivalent ID table. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] TnEquivalenceTablePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15TnMicrocodeEquivalenceTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnEquivalenceTablePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrDeCfg; + + LibAmdMsrRead (MSR_DE_CFG, &MsrDeCfg, StdHeader); + if ((MsrDeCfg & 0x80000) == 0) { + *NumberOfElements = ((sizeof (CpuF15TnUnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *TnEquivalenceTablePtr = CpuF15TnUnEncryptedMicrocodeEquivalenceTable; + } else { + *NumberOfElements = ((sizeof (CpuF15TnMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2); + *TnEquivalenceTablePtr = CpuF15TnMicrocodeEquivalenceTable; + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c new file mode 100644 index 0000000000..8a41eb86a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c @@ -0,0 +1,315 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Initialize the Family 15h Trinity specific way of running early initialization. + * + * Returns the table of initialization steps to perform at + * AmdInitEarly. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/FAMILY/0x15/TN + * @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" +#include "heapManager.h" +#include "Fch.h" +#include "Gnb.h" +#include "GnbLib.h" +#include "cpuEarlyInit.h" +#include "cpuF15TnPowerMgmt.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +F15TnLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetF15TnEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +ApplyWorkaroundForFchErratum39 ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnNbPstateForceBeforeApLaunchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE F15SetBrandIdRegistersAtEarly; +extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly; + +CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F15TnEarlyInitOnCoreTable[] = +{ + {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F15SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F15TnLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION}, + {F15TnNbPstateForceBeforeApLaunchAtEarly, PERFORM_EARLY_WARM_RESET}, + {NULL, 0} +}; + +/*------------------------------------------------------------------------------------*/ +/** + * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a + * processor that uses the standard initialization steps should take. + * + * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[out] Table Table of appropriate init steps for the executing core. + * @param[in] EarlyParams Service Interface structure to initialize. + * @param[in] StdHeader Opaque handle to standard config header. + * + */ +VOID +GetF15TnEarlyInitOnCoreTable ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *Table = F15TnEarlyInitOnCoreTable; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Update microcode patch in current processor for Family15h TN. + * + * This function acts as a wrapper for calling the LoadMicrocodePatch + * routine at AmdInitEarly. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnLoadMicrocodePatchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsPatchLoaded; + + AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader); + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + IsPatchLoaded = LoadMicrocodePatch (StdHeader); + } + + // After microcode patch has been loaded, apply the workaround for FCH erratum 39 + ApplyWorkaroundForFchErratum39 (StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Apply the workaround for FCH H2/H3 erratum #39. + * + * This function detects the FCH version and applies the appropriate workaround, if + * required. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +ApplyWorkaroundForFchErratum39 ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MiscReg51; + UINT8 RevisionId; + UINT16 AcpiPmTmrBlk; + UINT32 VendorIdDeviceId; + UINT64 MsrValue; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + CPU_LOGICAL_ID LogicalId; + + // Read Vendor ID / Device ID + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0); + LibAmdPciRead (AccessWidth32, PciAddress, &VendorIdDeviceId, StdHeader); + + // For Hudson based system, perform workaround + if (VendorIdDeviceId == 0x780B1022) { + PciAddress.Address.Register = 0x8; + LibAmdPciRead (AccessWidth8, PciAddress, &RevisionId, StdHeader); + if ((RevisionId == 0x14) && IsBsp (StdHeader, &IgnoredSts)) { + // Enable hardware workaround by setting Misc_reg x51[0] + LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader); + MiscReg51 |= BIT0; + LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + 0x51), &MiscReg51, StdHeader); + } else if (RevisionId == 0x13) { + GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); + if ((LogicalId.Revision & AMD_F15_TN_GT_A0) != 0) { + // For revs A1+, set up the C0010055 MSR + GnbLibIndirectIoBlockRead (0xCD6, 0xCD7, AccessWidth8, 0x64, 2, &AcpiPmTmrBlk, StdHeader); + LibAmdMsrRead (0xC0010055, &MsrValue, StdHeader); + MsrValue |= BIT30; + MsrValue |= AcpiPmTmrBlk; + LibAmdMsrWrite (0xC0010055, &MsrValue, StdHeader); + } + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Prevent NB P-state transitions prior to AP launch on Family 15h TN. + * + * This function determines the current NB P-state and forces the NB to remain + * in that P-state. + * + * @param[in] FamilyServices The current Family Specific Services. + * @param[in] EarlyParams Service parameters. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnNbPstateForceBeforeApLaunchAtEarly ( + IN CPU_SPECIFIC_SERVICES *FamilyServices, + IN AMD_CPU_EARLY_PARAMS *EarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrValue; + UINT64 PerfCtrlSave; + UINT64 PerfStsSave; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + ALLOCATE_HEAP_PARAMS Alloc; + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + + if (IsBsp (StdHeader, &IgnoredSts) && FamilyServices->IsNbPstateEnabled (FamilyServices, &EarlyParams->PlatformConfig, StdHeader)) { + LibAmdMsrRead (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader); + MsrValue = 0x00000006004004E9; + LibAmdMsrRead (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader); + LibAmdMsrWrite (MSR_NB_PERF_CTL3, &MsrValue, StdHeader); + MsrValue = 0; + LibAmdMsrWrite (MSR_NB_PERF_CTR3, &MsrValue, StdHeader); + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + Alloc.RequestedBufferSize = sizeof (NB_PSTATE_CTRL_REGISTER); + Alloc.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE; + Alloc.Persist = 0; + if (HeapAllocateBuffer (&Alloc, StdHeader) == AGESA_SUCCESS) { + *((NB_PSTATE_CTRL_REGISTER *) Alloc.BufferPtr) = NbPsCtrl; + } else { + ASSERT (FALSE); + } + LibAmdMsrRead (MSR_NB_PERF_CTR3, &MsrValue, StdHeader); + if (MsrValue == 0) { + NbPsCtrl.SwNbPstateLoDis = 1; + } else { + NbPsCtrl.SwNbPstateLoDis = 0; + NbPsCtrl.NbPstateDisOnP0 = 0; + NbPsCtrl.NbPstateThreshold = 0; + } + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + LibAmdMsrWrite (MSR_NB_PERF_CTL3, &PerfCtrlSave, StdHeader); + LibAmdMsrWrite (MSR_NB_PERF_CTR3, &PerfStsSave, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c new file mode 100644 index 0000000000..acbf23edb1 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnIoCstate.c @@ -0,0 +1,402 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity IO C-state feature support functions. + * + * Provides the functions necessary to initialize the IO C-state feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFeatures.h" +#include "cpuIoCstate.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuLateInit.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "CommonReturns.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnInitializeIoCstateOnCore ( + IN VOID *CstateBaseMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnIsCsdObjGenerated ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable; + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable IO Cstate on a family 15h Trinity CPU. + * Implement BIOS Requirements for Initialization of C-states + * + * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @return AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeIoCstate ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + AP_TASK TaskPtr; + PCI_ADDR PciAddress; + CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1; + + if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) { + // Initialize F4x128 + // bit[1] CoreCstatePolicy = 0 + // bit[4:2] HaltCstateIndex = 0 + // bit[31] CstateMsgDis = 1 + PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + CstatePolicyCtrl1.CoreCstatePolicy = 0; + CstatePolicyCtrl1.HaltCstateIndex = 0; + CstatePolicyCtrl1.CstateMsgDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + + // Initialize MSRC001_0073[CstateAddr] on each core to a region of + // the IO address map with 8 consecutive available addresses. + LocalMsrRegister = 0; + + IDS_HDT_CONSOLE (CPU_TRACE, " Init IO C-state Base at 0x%x\n", PlatformConfig->CStateIoBaseAddress); + ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress; + + TaskPtr.FuncAddress.PfApTaskI = F15TnInitializeIoCstateOnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 2; + TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL); + } + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Enable CState on a family 15h Trinity core. + * + * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F15TnInitializeIoCstateOnCore ( + IN VOID *CstateBaseMsr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // Initialize MSRC001_0073[CstateAddr] on each core + LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the size of CST object + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data + * @param[in] StdHeader Config Handle for library, services. + * + * @retval CstObjSize Size of CST Object + * + */ +UINT32 +STATIC +F15TnGetAcpiCstObj ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN GenerateCsdObj; + UINT32 CStateAcpiObjSize; + IO_CSTATE_FAMILY_SERVICES *FamilyServices; + ACPI_CST_GET_INPUT CstGetInput; + + CstGetInput.IoCstateServices = IoCstateServices; + CstGetInput.PlatformConfig = PlatformConfig; + CstGetInput.CStateAcpiObjSizePtr = &CStateAcpiObjSize; + + IDS_SKIP_HOOK (IDS_CST_SIZE, &CstGetInput, StdHeader) { + CStateAcpiObjSize = CST_HEADER_SIZE + CST_BODY_SIZE; + + // If CSD Object is generated, add the size of CSD Object to the total size of + // CState ACPI Object size + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); + + if (GenerateCsdObj) { + CStateAcpiObjSize += CSD_HEADER_SIZE + CSD_BODY_SIZE; + } + } + return CStateAcpiObjSize; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Routine to generate the C-State ACPI objects + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] LocalApicId Local Apic Id for each core. + * @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F15TnCreateAcpiCstObj ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN UINT8 LocalApicId, + IN OUT VOID **PstateAcpiBufferPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrData; + BOOLEAN GenerateCsdObj; + CST_HEADER_STRUCT *CstHeaderPtr; + CST_BODY_STRUCT *CstBodyPtr; + CSD_HEADER_STRUCT *CsdHeaderPtr; + CSD_BODY_STRUCT *CsdBodyPtr; + IO_CSTATE_FAMILY_SERVICES *FamilyServices; + ACPI_CST_CREATE_INPUT CstInput; + + CstInput.IoCstateServices = IoCstateServices; + CstInput.LocalApicId = LocalApicId; + CstInput.PstateAcpiBufferPtr = PstateAcpiBufferPtr; + + IDS_SKIP_HOOK (IDS_CST_CREATE, &CstInput, StdHeader) { + // Read from MSR C0010073 to obtain CstateAddr + LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader); + + // Typecast the pointer + CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr; + + // Set CST Header + CstHeaderPtr->NameOpcode = NAME_OPCODE; + CstHeaderPtr->CstName_a__ = CST_NAME__; + CstHeaderPtr->CstName_a_C = CST_NAME_C; + CstHeaderPtr->CstName_a_S = CST_NAME_S; + CstHeaderPtr->CstName_a_T = CST_NAME_T; + + // Typecast the pointer + CstHeaderPtr++; + CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr; + + // Set CST Body + CstBodyPtr->PkgOpcode = PACKAGE_OPCODE; + CstBodyPtr->PkgLength = CST_LENGTH; + CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS; + CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; + CstBodyPtr->Count = CST_COUNT; + CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; + CstBodyPtr->PkgLength2 = CST_PKG_LENGTH; + CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS; + CstBodyPtr->BufferOpcode = BUFFER_OPCODE; + CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH; + CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS; + CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE; + CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION; + CstBodyPtr->GdrLength = CST_GDR_LENGTH; + CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO; + CstBodyPtr->RegBitWidth = 0x08; + CstBodyPtr->RegBitOffset = 0x00; + CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS; + CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1; + CstBodyPtr->EndTag = 0x0079; + CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; + CstBodyPtr->Type = CST_C2_TYPE; + CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE; + CstBodyPtr->Latency = 100; + CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; + CstBodyPtr->Power = 0; + + CstBodyPtr++; + //Update the pointer + *PstateAcpiBufferPtr = CstBodyPtr; + + + // Check whether CSD object should be generated + GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); + ASSERT (FamilyServices != NULL); + GenerateCsdObj = FamilyServices->IsCsdObjGenerated (FamilyServices, StdHeader); + + if (GenerateCsdObj) { + CsdHeaderPtr = (CSD_HEADER_STRUCT *) *PstateAcpiBufferPtr; + + // Set CSD Header + CsdHeaderPtr->NameOpcode = NAME_OPCODE; + CsdHeaderPtr->CsdName_a__ = CST_NAME__; + CsdHeaderPtr->CsdName_a_C = CST_NAME_C; + CsdHeaderPtr->CsdName_a_S = CST_NAME_S; + CsdHeaderPtr->CsdName_a_D = CSD_NAME_D; + + CsdHeaderPtr++; + CsdBodyPtr = (CSD_BODY_STRUCT *) CsdHeaderPtr; + + // Set CSD Body + CsdBodyPtr->PkgOpcode = PACKAGE_OPCODE; + CsdBodyPtr->PkgLength = CSD_BODY_SIZE - 1; + CsdBodyPtr->PkgElements = 1; + CsdBodyPtr->PkgOpcode2 = PACKAGE_OPCODE; + CsdBodyPtr->PkgLength2 = CSD_BODY_SIZE - 4; // CSD_BODY_SIZE - Package() - Package Opcode + CsdBodyPtr->PkgElements2 = 6; + CsdBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE; + CsdBodyPtr->NumEntries = 6; + CsdBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE; + CsdBodyPtr->Revision = 0; + CsdBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE; + CsdBodyPtr->Domain = (LocalApicId & 0xFE) >> 1; + CsdBodyPtr->DWordPrefix2 = DWORD_PREFIX_OPCODE; + CsdBodyPtr->CoordType = CSD_COORD_TYPE_HW_ALL; + CsdBodyPtr->DWordPrefix3 = DWORD_PREFIX_OPCODE; + CsdBodyPtr->NumProcessors = 0x2; + CsdBodyPtr->DWordPrefix4 = DWORD_PREFIX_OPCODE; + CsdBodyPtr->Index = 0x0; + + CsdBodyPtr++; + + // Update the pointer + *PstateAcpiBufferPtr = CsdBodyPtr; + } + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Routine to check whether CSD object should be created. + * + * @param[in] IoCstateServices IO Cstate services. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE CSD Object should be created. + * @retval FALSE CSD Object should not be created. + * + */ +BOOLEAN +F15TnIsCsdObjGenerated ( + IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // CSD Object should only be created when there are two cores per compute unit + if (GetComputeUnitMapping (StdHeader) == EvenCoresMapping) { + return TRUE; + } + return FALSE; +} + +CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport = +{ + 0, + (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue, + F15TnInitializeIoCstate, + F15TnGetAcpiCstObj, + F15TnCreateAcpiCstObj, + F15TnIsCsdObjGenerated +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c new file mode 100644 index 0000000000..931f27f2ac --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnLogicalIdTables.c @@ -0,0 +1,134 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Logical ID Table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **TnIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF15TnLogicalIdAndRevArray[] = +{ + { + 0x6101, + AMD_F15_TN_A1 + }, + { + 0x6100, + 0x0000000000000100ull + } +}; + +VOID +GetF15TnLogicalIdAndRev ( + OUT CONST CPU_LOGICAL_ID_XLAT **TnIdPtr, + OUT UINT8 *NumberOfElements, + OUT UINT64 *LogicalFamily, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF15TnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)); + *TnIdPtr = CpuF15TnLogicalIdAndRevArray; + *LogicalFamily = AMD_FAMILY_15_TN; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c new file mode 100644 index 0000000000..dbd9ee2020 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c @@ -0,0 +1,2701 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD F15Tn Microcode patch. + * + * F15Tn Microcode Patch rev 0600110F for 6101 or equivalent. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 64060 $ @e \$Date: 2012-01-15 21:36:26 -0600 (Sun, 15 Jan 2012) $ + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + * + ***************************************************************************/ + + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +UCODE_VS_FLAG (0600110F_Enc) + +// Encrypt Patch code 0600110F for 6101 and equivalent + +CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600110F_Enc [IDS_PAD_4K] = +{ + 0x12, + 0x20, + 0x11, + 0x01, + 0x0f, + 0x11, + 0x00, + 0x06, + 0x02, + 0x80, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x61, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xd4, + 0x3d, + 0x97, + 0xf0, + 0xd2, + 0x1a, + 0xcf, + 0x44, + 0x1d, + 0x45, + 0x82, + 0x13, + 0xec, + 0xcd, + 0x52, + 0x24, + 0x2d, + 0x26, + 0x73, + 0x9f, + 0x0e, + 0x38, + 0x80, + 0x5b, + 0x02, + 0x6a, + 0xd3, + 0x80, + 0x97, + 0xc0, + 0xe8, + 0x08, + 0xaf, + 0x52, + 0x2e, + 0xe4, + 0x54, + 0xa6, + 0xb3, + 0xb3, + 0x9b, + 0x21, + 0xb9, + 0xe1, + 0xa8, + 0xa4, + 0xed, + 0x9a, + 0x76, + 0xf7, + 0x62, + 0x13, + 0x3b, + 0xf8, + 0x21, + 0xc4, + 0xf3, + 0xff, + 0xb5, + 0x20, + 0xbd, + 0x8c, + 0x3a, + 0x4b, + 0x7e, + 0x44, + 0x88, + 0x9e, + 0x21, + 0xf3, + 0x32, + 0xad, + 0x96, + 0xf9, + 0x1d, + 0xe4, + 0xce, + 0xdd, + 0xb7, + 0x58, + 0x6c, + 0x3c, + 0x78, + 0x00, + 0x9f, + 0x9f, + 0x76, + 0x6e, + 0x92, + 0x80, + 0xb9, + 0x6a, + 0xcf, + 0x66, + 0x2b, + 0x7e, + 0x1d, + 0xbf, + 0x2d, + 0xca, + 0xde, + 0x58, + 0x1b, + 0xc6, + 0xb8, + 0x5e, + 0x82, + 0xc3, + 0xdf, + 0x8b, + 0xd8, + 0xdb, + 0xca, + 0x43, + 0xf2, + 0x75, + 0x40, + 0xb6, + 0xbf, + 0xdb, + 0x5f, + 0xb8, + 0xd2, + 0xdd, + 0x81, + 0xeb, + 0xa6, + 0x7f, + 0x01, + 0xbc, + 0x37, + 0x07, + 0x4e, + 0x73, + 0x13, + 0xcf, + 0x08, + 0xb9, + 0xd6, + 0xda, + 0xe6, + 0x10, + 0xd7, + 0x2c, + 0xfe, + 0x49, + 0x3e, + 0x4b, + 0xa0, + 0xfa, + 0xc1, + 0x81, + 0xe9, + 0xdb, + 0x70, + 0xfd, + 0x46, + 0xc4, + 0x44, + 0x4c, + 0x14, + 0xc2, + 0x1a, + 0x46, + 0xa5, + 0x2c, + 0xb3, + 0x04, + 0x15, + 0xda, + 0x53, + 0x74, + 0x41, + 0x61, + 0xcc, + 0xda, + 0x40, + 0x53, + 0x03, + 0x4a, + 0x51, + 0xc2, + 0x4f, + 0x81, + 0x34, + 0x89, + 0x4f, + 0x7c, + 0x7e, + 0xa0, + 0x50, + 0x7a, + 0xc8, + 0xf3, + 0xd0, + 0xfc, + 0x7f, + 0xda, + 0xa8, + 0x61, + 0x6c, + 0x46, + 0xb3, + 0xc9, + 0x05, + 0x0b, + 0x9f, + 0x5e, + 0xb1, + 0x43, + 0x9d, + 0xc0, + 0x3a, + 0xbe, + 0x6e, + 0x05, + 0x30, + 0x3d, + 0xf1, + 0xee, + 0x0e, + 0xcf, + 0x63, + 0x40, + 0xe9, + 0xd3, + 0x27, + 0x2c, + 0x0a, + 0x48, + 0xe8, + 0xae, + 0xc0, + 0x38, + 0xae, + 0x3b, + 0x41, + 0x21, + 0x5a, + 0xa2, + 0xc0, + 0x20, + 0x77, + 0x18, + 0x9b, + 0x7f, + 0xdd, + 0x95, + 0x4b, + 0x8b, + 0x83, + 0x2c, + 0xfb, + 0x49, + 0xd8, + 0x25, + 0xf2, + 0x21, + 0x6e, + 0x54, + 0xe5, + 0x01, + 0x22, + 0xd5, + 0xf8, + 0x99, + 0x1f, + 0x83, + 0x69, + 0x52, + 0xa1, + 0x9a, + 0x67, + 0x73, + 0x55, + 0xa2, + 0x98, + 0x82, + 0x8c, + 0xff, + 0xed, + 0x9c, + 0x0a, + 0x07, + 0x33, + 0x6f, + 0x16, + 0x39, + 0x79, + 0xcc, + 0xe3, + 0x5a, + 0xa0, + 0x2d, + 0xa6, + 0xdf, + 0x2e, + 0x4b, + 0xab, + 0x6c, + 0x6f, + 0xd4, + 0x6e, + 0x70, + 0x9b, + 0x9a, + 0xf3, + 0xb3, + 0x52, + 0xb8, + 0x05, + 0x53, + 0xba, + 0x79, + 0x08, + 0x6a, + 0xb1, + 0x5e, + 0xf7, + 0x85, + 0xc1, + 0xfc, + 0xd8, + 0xb5, + 0x3d, + 0xbb, + 0xb9, + 0x3d, + 0xa3, + 0x98, + 0x13, + 0x61, + 0xed, + 0x1e, + 0xc0, + 0x45, + 0x6c, + 0x98, + 0xfc, + 0x87, + 0x2c, + 0xb8, + 0x99, + 0x97, + 0xb8, + 0xc7, + 0x5f, + 0x2e, + 0x6d, + 0x28, + 0x79, + 0xaf, + 0x0b, + 0xf9, + 0x84, + 0x7e, + 0x34, + 0xd8, + 0x86, + 0x61, + 0x22, + 0xdb, + 0xf4, + 0xef, + 0x58, + 0x0d, + 0x4e, + 0xcf, + 0x02, + 0x8a, + 0xf8, + 0x17, + 0xab, + 0x7d, + 0x79, + 0x98, + 0x38, + 0x35, + 0x59, + 0xdf, + 0x03, + 0xff, + 0xed, + 0xc7, + 0x1f, + 0x25, + 0xe3, + 0x26, + 0x05, + 0xde, + 0x7f, + 0xbb, + 0xe4, + 0xff, + 0xbf, + 0x6d, + 0xc6, + 0xc2, + 0x2e, + 0x02, + 0x45, + 0x85, + 0x5f, + 0x43, + 0xdb, + 0xb8, + 0xd2, + 0x13, + 0xd7, + 0x52, + 0xde, + 0x53, + 0x49, + 0xda, + 0x7f, + 0x0b, + 0xb8, + 0x76, + 0x70, + 0xf9, + 0xfe, + 0xf0, + 0x27, + 0xb7, + 0xc9, + 0xd4, + 0x83, + 0x6d, + 0x80, + 0xaa, + 0x34, + 0x46, + 0xf5, + 0xe3, + 0x1f, + 0xd7, + 0x0f, + 0xf2, + 0xee, + 0x5a, + 0xb2, + 0xcd, + 0x08, + 0x47, + 0xe6, + 0xf7, + 0x99, + 0xd1, + 0x05, + 0x55, + 0x0f, + 0x5f, + 0x1d, + 0xab, + 0xd6, + 0xb3, + 0x32, + 0xaf, + 0xa1, + 0x57, + 0x4d, + 0x32, + 0x00, + 0x4f, + 0xf6, + 0x6f, + 0x6e, + 0x79, + 0x8a, + 0x7c, + 0xc2, + 0xef, + 0x7e, + 0xcd, + 0x83, + 0xac, + 0x85, + 0x0e, + 0x53, + 0x2c, + 0xd9, + 0x92, + 0xf5, + 0x55, + 0xf6, + 0xc9, + 0x41, + 0xed, + 0xf5, + 0x4e, + 0x41, + 0xea, + 0x97, + 0xca, + 0x3b, + 0x14, + 0xca, + 0x0d, + 0x4e, + 0xb9, + 0x5f, + 0x54, + 0x23, + 0xf1, + 0xdc, + 0x8b, + 0xa4, + 0xc1, + 0x52, + 0xe2, + 0x7a, + 0x8f, + 0xdf, + 0x3f, + 0x93, + 0xa1, + 0x84, + 0x5c, + 0xca, + 0x6a, + 0x3a, + 0x42, + 0x95, + 0x2e, + 0x71, + 0xf6, + 0xa2, + 0x88, + 0x56, + 0x32, + 0xe8, + 0x98, + 0x2a, + 0xb8, + 0xf0, + 0x65, + 0x95, + 0x01, + 0xb8, + 0xc8, + 0x23, + 0xe9, + 0x30, + 0x52, + 0x94, + 0xeb, + 0xfa, + 0x9f, + 0x67, + 0x53, + 0xf0, + 0x63, + 0x10, + 0x70, + 0x1b, + 0x01, + 0x71, + 0x21, + 0xb3, + 0x27, + 0x4e, + 0x37, + 0x04, + 0xdc, + 0x74, + 0x6f, + 0xf3, + 0x08, + 0x00, + 0x72, + 0x21, + 0x96, + 0xe5, + 0xc6, + 0x75, + 0xa8, + 0x14, + 0x6f, + 0xcf, + 0xd8, + 0x86, + 0xe3, + 0xb7, + 0xf3, + 0x8c, + 0xe4, + 0x71, + 0x03, + 0x60, + 0xd4, + 0x53, + 0xff, + 0x5a, + 0x07, + 0xc4, + 0xe5, + 0x6b, + 0xf4, + 0x8d, + 0x80, + 0x55, + 0x78, + 0x4f, + 0xf5, + 0x55, + 0x04, + 0x2e, + 0x61, + 0x05, + 0x46, + 0x51, + 0x56, + 0xf8, + 0x0a, + 0xf5, + 0x6e, + 0x08, + 0x85, + 0xfd, + 0x01, + 0x9a, + 0x90, + 0x5a, + 0xed, + 0x0e, + 0x44, + 0x49, + 0xff, + 0x48, + 0xbe, + 0x5b, + 0xc4, + 0xea, + 0xbb, + 0x38, + 0xa9, + 0x04, + 0xf3, + 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0xb0, + 0xd9, + 0x68, + 0x27, + 0x8c, + 0x93, + 0x47, + 0x3e, + 0x4f, + 0xc0, + 0xa8, + 0x86, + 0x68, + 0x4b, + 0x1a, + 0xf5, + 0x93, + 0xdd, + 0x16, + 0xed, + 0x8e, + 0x27, + 0x66, + 0x4d, + 0x59, + 0xf0, + 0x27, + 0x1b, + 0x37, + 0xa0, + 0x25, + 0x9a, + 0x62, + 0xb4, + 0x6f, + 0xbd, + 0x83, + 0x28, + 0x0b, + 0x26, + 0xa9, + 0x07, + 0xac, + 0xb5, + 0x91, + 0x93, + 0x91, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c new file mode 100644 index 0000000000..c2ea312fb9 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatchTables.c @@ -0,0 +1,138 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity microcode patches + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "cpuRegisters.h" +#include "cpuEarlyInit.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +extern CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15TnMicroCodePatchArray[]; +extern CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns a table containing the appropriate microcode patches. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] TnUcodePtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15TnMicroCodePatchesStruct ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **TnUcodePtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = CpuF15TnNumberOfMicrocodePatches; + *TnUcodePtr = &CpuF15TnMicroCodePatchArray[0]; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c new file mode 100644 index 0000000000..1be61540cc --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMsrTables.c @@ -0,0 +1,324 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity MSR tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63495 $ @e \$Date: 2011-12-23 01:30:59 -0600 (Fri, 23 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15TnPowerMgmt.h" +#include "F15TnPackageType.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +SetTopologyExtensions ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +SetForceSmcCheckFlwStDis ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_NB_CFG (0xC001001F) +// bit[23] = 1, erratum #663 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_NB_CFG, // MSR Address + 0x0000000000800000, // OR Mask + 0x0000000000800000, // NAND Mask + }} + }, + +// MSR_LS_CFG2 (0xC001102D) +// bit[23] DisScbThreshold = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_LS_CFG2, // MSR Address + 0x0000000000800000, // OR Mask + 0x0000000000800000, // NAND Mask + }} + }, +// MSR_HWCR (0xC0010015) +// bit[27] EffFreqReadOnlyLock = 1 +// bit[12] HltXSpCycEn = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_HWCR, // MSR Address + 0x0000000008001000, // OR Mask + 0x0000000008001000, // NAND Mask + }} + }, +// MSR_OSVW_ID_Length (0xC0010140) +// bit[15:0] = 4 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_OSVW_ID_Length, // MSR Address + 0x0000000000000004, // OR Mask + 0x000000000000FFFF, // NAND Mask + }} + }, +// MSR 0xC0011000 +// bit[17] = 1, Disable Erratum #671 +// bit[16] = 1, Erratum #608 for all TN revisions + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + 0xC0011000, // MSR Address + 0x0000000000030000, // OR Mask + 0x0000000000030000, // NAND Mask + }} + }, +// MSR_CPUID_EXT_FEATS (0xC0011005) +// bit[51] NodeId = 1 + { + MsrRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CPUID_EXT_FEATS, // MSR Address + 0x0008000000000000, // OR Mask + 0x0008000000000000, // NAND Mask + }} + }, +}; + +CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable = { + AllCores, + (sizeof (F15TnMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnMsrRegisters, +}; + +// MSR with Special Programming Requirements Table + +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnMsrWorkarounds[] = +{ +// MSR_C001_1005 + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + SetTopologyExtensions, // function call + 0x00000000, // data + }} + }, +// MSR_C001_102D + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + SetForceSmcCheckFlwStDis, // function call + 0x00000000, // data + }} + }, +}; + +CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable = { + AllCores, + (sizeof (F15TnMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) F15TnMsrWorkarounds, +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * MSR special programming requirements for MSR_C001_1005 + * + * AGESA should program MSR_C001_1005[54, TopologyExtensions] as follows: + * IF (CPUID Fn8000_0001_EBX[PkgType]==0010b) THEN 0 ELSE 1 ENDIF. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +SetTopologyExtensions ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 PkgType; + UINT64 CpuMsrData; + + PkgType = LibAmdGetPackageType (StdHeader); + LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); + CpuMsrData &= ~(BIT54); + if (PkgType == PACKAGE_TYPE_FM2) { + CpuMsrData |= BIT54; + } + LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * MSR special programming requirements for MSR_C001_102D + * + * AGESA should program MSR_C001_102D[14] with the fused value from F3x1FC[23] + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +SetForceSmcCheckFlwStDis ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PRODUCT_INFO_REGISTER ProductInfo; + LS_CFG2_MSR LsCfg2; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &ProductInfo, StdHeader); + + LibAmdMsrRead (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader); + + LsCfg2.ForceSmcCheckFlwStDis = ProductInfo.ForceSmcCheckFlwStDis; + LibAmdMsrWrite (MSR_LS_CFG2, (UINT64 *) &LsCfg2, StdHeader); + + return; +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h new file mode 100644 index 0000000000..bb8a04a6f8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPackageType.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Package Type Definitions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _F15_TN_PACKAGE_TYPE_H_ +#define _F15_TN_PACKAGE_TYPE_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + +// Below equates are defined to cooperate with LibAmdGetPackageType. +#define PACKAGE_TYPE_FP2 (1 << 0) +#define PACKAGE_TYPE_FS1r2 (1 << 1) +#define PACKAGE_TYPE_FM2 (1 << 2) + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +#endif // _F15_TN_PACKAGE_TYPE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c new file mode 100644 index 0000000000..c04ce1e109 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPciTables.c @@ -0,0 +1,849 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity PCI tables with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 64462 $ @e \$Date: 2012-01-21 10:59:15 -0600 (Sat, 21 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15TnPowerMgmt.h" +#include "Table.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +SetEnCstateBoostBlockCC6Exit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +Erratum687Workaround ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +// P C I T a b l e s +// ---------------------- + +STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15TnPciRegisters[] = +{ +// F0x68 - Link Transaction Control +// bits[22:21] DsNpReqLmt = 01b +// bit [19] ApicExtSpur = 1 +// bit [18] ApicExtId = 1 +// bit [17] ApicExtBrdCst = 1 +// bit [15] LimitCldtCfg = 1 +// bit [10] DisFillP = 0 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address + 0x002E8000, // regData + 0x006E8400, // regMask + }} + }, +// F0x6C - Link Initialization Control +// bit[0] RouteTblDis = 0 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address + 0x00000000, // regData + 0x00000001, // regMask + }} + }, +// F0x84 - Link Control +// bit [12] IsocEn = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x84), // Address + 0x00001000, // regData + 0x00001000, // regMask + }} + }, +// F0x90 - Upstream Base Channel Buffer Count +// bits[27:25] FreeData = 0 +// bits[24:20] FreeCmd = 0 +// bits[19:18] RspData = 1 +// bits[17:16] NpReqData = 1 +// bits[15:12] ProbeCmd = 0 +// bits[11:8] RspCmd = 2 +// bits[7:5] PReq = 5 +// bits[4:0] NpReqCmd = 8 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address + 0x000502A8, // regData + 0x0FFFFFFF, // regMask + }} + }, +// F0x94 - Link Isochronous Channel Buffer Count +// bits[28:27] IsocRspData = 0 +// bits[26:25] IsocNpReqData = 1 +// bits[24:22] IsocRspCmd = 0 +// bits[21:19] IsocpReq = 0 +// bits[18:16] IsocNpReqCmd = 1 +// bits[15:8] SecBusNum = 0 (F1XE0 [BaseBusNum]) + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94), // Address + 0x02010000, // regData + 0x1FFFFF00, // regMask + }} + }, +// F1xE0 - Configuration Map +// bits[31:24] BusNumLimit = F8 +// bits[23:16] BaseBusNum = 0 +// bit [1] WE = 1 +// bit [0] RE = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_1, 0xE0),// Address + 0xF8000003, // regData + 0xFFFF0003, // regMask + }} + }, +// F3x44 - MCA NB Configuration +// +// bit[30] SyncFloodOnDramAdrParErr = 1 +// bit[27] NbMcaToMstCpuEn = 1 +// bit[21] SyncFloodOnAnyUcErr = 1 +// bit[20] SyncFloodOnWDT = 1 + + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address + 0x48300000, // regData + 0x48300000, // regMask + }} + }, +// F3x70 - SRI_to_XBAR Command Buffer Count +// bits[30:28] IsocRspCBC = 1 +// bits[26:24] IsocPreqCBC = 0 +// bits[22:20] IsocReqCBC = 1 +// bits[18:16] UpRspCBC = 7 +// bits[14:12] DnPreqCBC = 1 +// bits[10:8] UpPreqCBC = 1 +// bits[7:6] DnRspCBC = 1 +// bits[5:4] DnReqCBC = 1 +// bits[2:0] UpReqCBC = 7 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address + 0x10171157, // regData + 0x777777F7, // regMask + }} + }, +// F3x74 - XBAR_to_SRI Command Buffer Count +// bits[31:28] DRReqCBC = 0 +// bits[26:24] IsocPreqCBC = 1 +// bits[23:20] IsocReqCBC = 1 +// bits[19:16] ProbeCBC = 8 +// bits[14:12] DnPreqCBC = 0 +// bits[10:8] UpPreqCBC = 1 +// bits[6:4] DnReqCBC = 0 +// bits[2:0] UpReqCBC = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address + 0x01180101, // regData + 0xF7FF7777, // regMask + }} + }, +// F3x7C - Free List Buffer Count +// bits[26:23] ExtSrqFreeList = 8 +// bits[22:20] Sri2XbarFreeRspDBC = 0 +// bits[19:16] Sri2XbarFreeXreqDBC = 5 +// bits[15:12] Sri2XbarFreeRspCBC = 0 +// bits[11:8] Sri2XbarFreeXreqCBC = 0xE +// bits[4:0] Xbar2SriFreeListCBC = 18h + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address + 0x04050E18, // regData + 0x07FFFF1F, // regMask + }} + }, +// F3x84 - ACPI Power State Control High +// ACPI State S3 +// bit[1] NbLowPwrEnSmafAct4 = 1 +// bit[7:5] ClkDivisorSmafAct4 = 7 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address + 0x000000E2, // regData + 0x000000E2, // regMask + }} + }, +// F3xA0 - Power Control Miscellaneous +// bit[14] Svi2HighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE + { + ProfileFixup, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address + 0x00004000, // regData + 0x00004000, // regMask + }} + }, +// F3xD4 - Clock Power Timing Control 0 +// bit [31] NbClkDivApplyAll = 1 +// bits[30:28] NbClkDiv = 4 +// bits[27:24] PowerStepUp = 8 +// bits[23:20] PowerStepDown = 8 +// bit [14] CacheFlushImmOnAllHalt = 0 +// bit [12] ClkRampHystCtl = 0 +// bits[11:8] ClkRampHystSel = 0xF + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address + 0xC8800F00, // regData + 0xFFF05F00, // regMask + }} + }, +// F3xD8 - Clock Power Timing Control 1 +// bits[6:4] VSRampSlamTime = 100b + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address + 0x00000040, // regData + 0x00000070, // regMask + }} + }, +// F3xDC - Clock Power Timing Control 2 +// bits[14:12] NbsynPtrAdj = 5 + { + PciRegister, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address + 0x00005000, // regData + 0x00007000, // regMask + }} + }, +// F3x140 - SRI_to_XCS Token Count +// bits[23:20] FreeTok = 0xA +// bits[17:16] IsocRspTok = 1 +// bits[15:14] IsocPreqTok = 0 +// bits[13:12] IsocReqTok = 1 +// bits[11:10] DnRspTok = 1 +// bits[9:8] UpRspTok = 1 +// bits[7:6] DnPreqTok = 1 +// bits[5:4] UpPreqTok = 1 +// bits[3:2] DnReqTok = 1 +// bits[1:0] UpReqTok = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address + 0x00A11555, // regData + 0x00F3FFFF, // regMask + }} + }, +// F3x144 - MCT_to_XCS Token Count +// bits[7:4] ProbeTok = 7 +// bits[3:0] RspTok = 7 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address + 0x00000077, // regData + 0x000000FF, // regMask + }} + }, +// F3x148 - Link_to_XCS Token Count +// bits[31:30] FreeTok[3:2] = FreeTok[1:0] = 0 +// bit [28] IsocRspTok1 = 0 +// bit [26] IsocPreqTok1 = 0 +// bit [24] IsocReqTok1 = 0 +// bits[23:22] ProbeTok1 = 0 +// bits[21:20] RspTok1 = 0 +// bits[19:18] PReqTok1 = 0 +// bits[17:16] ReqTok1 = 0 +// bits[15:14] FreeTok[1:0] = 0 +// bits[13:12] IsocRspTok0 = 0 +// bits[11:10] IsocPreqTok0 = 1 +// bits[9:8] IsocReqTok0 = 1 +// bits[7:6] ProbeTok0 = 0 +// bits[5:4] RspTok0 = 2 +// bits[3:2] PReqTok0 = 2 +// bits[1:0] ReqTok0 = 2 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address + 0x0000052A, // regData + 0xD5FFFFFF // regMask + }} + }, +// F3x17C - Extended Freelist Buffer Count +// bits[3:0] SPQPrbFreeCBC = 4 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platform Features + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address + 0x00000004, // regData + 0x0000000F // regMask + }} + }, +// F3x180 - NB Extended Configuration +// bit[24] McaLogErrAddrWdtErr = 1 +// bit[22] SyncFloodOnTblWalkErr = 1 +// bit[21] SyncFloodOnCpuLeakErr = 1 +// bit[20] SyncFloodOnL3LeakErr = 1 +// bit[9] SyncFloodOnUCNbAry = 1 +// bit[8] SyncFloodOnHtProt = 1 +// bit[7] SyncFloodOnTgtAbortErr = 1 +// bit[6] SyncFloodOnDatErr = 1 +// bit[5] DisPciCfgCpuMstAbortRsp = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address + 0x017003E0, // regData + 0x017003E0, // regMask + }} + }, +// F3x1A0 - Core to NB Buffer Count +// bit[17:16] CpuToNbFreeBufCnt = 3 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address + 0x00030000, // regData + 0x00030000, // regMask + }} + }, +// F4x110 - Sample and Residency Timer +// bits[11:0] CSampleTimer = 2 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address + 0x00000002, // regData + 0x00000FFF, // regMask + }} + }, +// F4x124 - C-state Interrupt Control +// bits[26:23] IntMonPC6Limit = 0 +// bit [22] IntMonPC6En = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address + 0x00400000, // regData + 0x07C00000, // regMask + }} + }, +// F4x16C - Erratum #667 +// bit [1] = 1 +// bit [4] = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address + 0x00000012, // regData + 0x00000012, // regMask + }} + }, +// F5xAC - Erratum #667 +// bit [3] = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0xAC), // Address + 0x00000008, // regData + 0x00000008, // regMask + }} + }, +// F5x88 - Northbridge Configuration 4 +// bit[24] DisHbNpReqBusLock = 1 +// bit[2] IntStpClkHaltExitEn = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address + 0x01000004, // regData + 0x01000004, // regMask + }} + }, +// F5xE0 - Processor TDP Running Average +// bits[3:0] RunAvgRange = 0x2 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address + 0x00000002, // regData + 0x0000000F, // regMask + }} + }, +// F5x128 - Clock Power/Timing Control 3 +// bits[13:12] PwrGateTmr = 1 +// bits[11:10] PllVddOutUpTime = 3 +// bit [9] FastSlamTimeDown = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x128), // Address + 0x00001E00, // regData + 0x00003E00, // regMask + }} + }, +// F5x12C - Clock Power/Timing Control 4 +// bit [5] CorePsi1En = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x12C), // Address + 0x00000020, // regData + 0x00000020, // regMask + }} + }, +// F5x178 - Northbridge Fusion Configuration +// bit [18] CstateFusionHsDis = 1 +// bit [17] Dis2ndGnbAllowPsWait = 1 +// bit [11] AllowSelfRefrS3Dis = 1 +// bit [10] InbWakeS3Dis = 1 +// bit [2] CstateFusionDis = 1 + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_5, 0x178), // Address + 0x00060C04, // regData + 0x00060C04, // regMask + }} + }, +// F0x90 - Upstream Base Channel Buffer Count +// bit [31] LockBc = 1 +// +// NOTE: The entry is intended to be programmed after other bits of D18F0x[90, 94] is programmed and before D18F0x6C[30] is programmed. + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address + 0x80000000, // regData + 0x80000000, // regMask + }} + }, +// F0x6C - Link Initialization Control +// bit [30] RlsLnkFullTokCntImm = 1 +// bit [28] RlsIntFullTokCntImm = 1 +// +// NOTE: The entry is intended to be after D18F0x[90, 94] and D18F0x[70, 74, 78, 7C, 140, 144, 148, 17C, 1A0] are programmed. + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address + 0x50000000, // regData + 0x50000000, // regMask + }} + }, +// F0x6C - Link Initialization Control +// bit [27] ApplyIsocModeEnNow = 1 +// +// NOTE: The entry is intended to be after D18F0x6C[30, 28] are programmed. + { + PciRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address + 0x08000000, // regData + 0x08000000, // regMask + }} + }, +}; + + +// PCI with Special Programming Requirements Table + +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPciWorkarounds[] = +{ +// D18F5x88 + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_GT_A0 // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + SetEnCstateBoostBlockCC6Exit, // function call + 0x00000000, // data + }} + }, +// D18F5x88 and D18F2x408 + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + Erratum687Workaround, // function call + 0x00000000, // data + }} + }, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable = { + PrimaryCores, + (sizeof (F15TnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + F15TnPciRegisters, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable = { + PrimaryCores, + (sizeof (F15TnPciWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) F15TnPciWorkarounds, +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Workaround for Non-A0 TN processors. + * + * AGESA should program F5x88[18] with the fused value from F3x1FC[20] for non-RevA0 parts. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +SetEnCstateBoostBlockCC6Exit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PRODUCT_INFO_REGISTER ProductInfo; + NB_CFG_4_REGISTER NbCfg4; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader); + + PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); + + NbCfg4.EnCstateBoostBlockCC6Exit = ProductInfo.EnCstateBoostBlockCC6Exit; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Workaround for Erratum #687 for TN processors. + * + * AGESA should program F5x88[14] with the fused value from F3x1FC[29] and + * program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +Erratum687Workaround ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PRODUCT_INFO_REGISTER ProductInfo; + NB_CFG_4_REGISTER NbCfg4; + GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2; + UINT32 DctSelCnt; + DCT_CFG_SEL_REGISTER DctCfgSel; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader); + + PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); + NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader); + + for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) { + PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader); + GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader); + + PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader); + DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel; + LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c new file mode 100644 index 0000000000..c9b6b6b04b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerMgmtSystemTables.c @@ -0,0 +1,195 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Models 0x10 - 0x1F Power Management related initialization table + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63692 $ @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuPowerMgmtSystemTables.h" +#include "cpuF15TnCoreAfterReset.h" +#include "cpuF15TnNbAfterReset.h" +#include "F15TnPowerPlane.h" +#include "cpuF15TnPowerCheck.h" +#include "F15TnUtilities.h" +#include "IdsF15TnAllService.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +GetF15TnSysPmTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **SysPmTblPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* Family 15h Only Table */ +/* ---------------------- */ +CONST SYS_PM_TBL_STEP ROMDATA CpuF15TnSysPmTableArray[] = +{ + IDS_INITIAL_F15_TN_PM_STEP + + // Step 1 - Configure F3x[84:80]. Handled by PCI register table. + // Step 2 - Power Plane Initialization + // Execute both cold & warm + { + 0, // ExeFlags + F15TnPmPwrPlaneInit // Function Pointer + }, + + // Step 3 - Adjust NB VID + // Execute only after cold reset + { + PM_EXEFLAGS_COLD_ONLY, // ExeFlags + F15TnNbPstateVidAdjustAfterReset // Function Pointer + }, + + // Step 4 - Disable NB Pstate, if required + // Execute both cold & warm + { + 0, // ExeFlags + F15TnNbPstateDis // Function Pointer + }, + + // Step 5 - Core Minimum P-state Transition Sequence After Warm Reset + // Execute only after warm reset + { + PM_EXEFLAGS_WARM_ONLY, // ExeFlags + F15TnPmCoreAfterReset // Function Pointer + }, + + // Step 6 - NB P-state COF and VID Synchronization After Warm Reset + // Execute only after warm reset + { + PM_EXEFLAGS_WARM_ONLY, // ExeFlags + F15TnPmNbAfterReset // Function Pointer + }, + + // Step 7 - Power Check + // Execute both cold & warm + { + 0, // ExeFlags + F15TnPmPwrCheck // Function Pointer + }, + + IDS_F15_TN_PM_CUSTOM_STEP + +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the appropriate table of steps to perform to initialize the power management + * subsystem. + * + * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] SysPmTblPtr Points to the first entry in the table. + * @param[out] NumberOfElements Number of valid entries in the table. + * @param[in] StdHeader Header for library and services. + * + */ +VOID +GetF15TnSysPmTable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT CONST VOID **SysPmTblPtr, + OUT UINT8 *NumberOfElements, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + *NumberOfElements = (sizeof (CpuF15TnSysPmTableArray) / sizeof (SYS_PM_TBL_STEP)); + *SysPmTblPtr = CpuF15TnSysPmTableArray; +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c new file mode 100644 index 0000000000..dbf0ab9626 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c @@ -0,0 +1,207 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Models 0x10 - 0x1F Power Plane Initialization + * + * Performs the "BIOS Requirements for Power Plane Initialization" as described + * in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuApicUtilities.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "Table.h" +#include "F15TnPowerPlane.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +// Register encodings for D18F3xD8[VSRampSlamTime] +STATIC CONST UINT32 ROMDATA F15TnVSRampSlamWaitTimes[8] = +{ + 500, // 000b: 5.00us + 375, // 001b: 3.75us + 300, // 010b: 3.00us + 240, // 011b: 2.40us + 200, // 100b: 2.00us + 150, // 101b: 1.50us + 120, // 110b: 1.20us + 100 // 111b: 1.00us +}; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h core 0 entry point for performing power plane initialization. + * + * The steps are as follows: + * 1. Configure D18F3xD8[VSRampSlamTime] based on platform + * requirements. + * 2. Configure F3xD4[PowerStepUp & PowerStepDown] + * 3. Optionally configure F3xA0[PsiVidEn & PsiVid] + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParams Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmPwrPlaneInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + UINT32 SystemSlewRate; + UINT32 WaitTime; + UINT32 VSRampSlamTime; + UINT32 LocalPciRegister; + CLK_PWR_TIMING_CTRL1_REGISTER ClkPwrTimingCtrl1; + BOOLEAN SkipPowerPlan; + + + SkipPowerPlan = FALSE; + IDS_OPTION_CALLOUT (IDS_CALLOUT_POWER_PLAN_INIT, &SkipPowerPlan, StdHeader); + if (!SkipPowerPlan) { + // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements. + // Voltage Ramp Time = maximum time to change voltage by 15mV rounded to the next higher encoding. + SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <= + CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ? + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate : + CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate; + + ASSERT (SystemSlewRate != 0); + + // First, calculate the time it takes to change 15mV using the VRM slew rate. + WaitTime = (15000 * 100) / SystemSlewRate; + if (((15000 * 100) % SystemSlewRate) != 0) { + WaitTime++; + } + + // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds + // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable + // VRM can be. + for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) { + if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) { + break; + } + } + + if (WaitTime > F15TnVSRampSlamWaitTimes[0]) { + // The VRMs on this motherboard are too slow for this CPU. + IDS_ERROR_TRAP; + } + + // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value. + PciAddress.AddressValue = CPTC1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader); + ClkPwrTimingCtrl1.VSRampSlamTime = VSRampSlamTime; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader); + + // Configure PowerStepUp/PowerStepDown + PciAddress.AddressValue = CPTC0_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp = 8; + ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown = 8; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + } +} + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h new file mode 100644 index 0000000000..df17667925 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.h @@ -0,0 +1,103 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Models 0x10 - 0x1F Power Plane related functions and structures + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _F15_TN_POWER_PLANE_H_ +#define _F15_TN_POWER_PLANE_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmPwrPlaneInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _F15_TN_POWER_PLANE_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c new file mode 100644 index 0000000000..b603800ced --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnSharedMsrTable.c @@ -0,0 +1,415 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Shared MSR table with values as defined in BKDG + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +F15TnFpCfgInit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +Update800MHzHtcPstateTo900MHz ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + +// MSR_TOM2 (0xC001001D) +// bits[63:0] TOP_MEM2 = 0 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_TOM2, // MSR Address - Shared + 0x0000000000000000, // OR Mask + 0xFFFFFFFFFFFFFFFF, // NAND Mask + }} + }, + +// MSR_SYS_CFG (0xC0010010) +// bit[21] MtrrTom2En = 1 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_SYS_CFG, // MSR Address - Shared + (1 << 21), // OR Mask + (1 << 21), // NAND Mask + }} + }, + +// MSR_IC_CFG (0xC0011021) +// bit[39] DisLoopPredictor = 1 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_IC_CFG, // MSR Address - Shared + (1ull << 39), // OR Mask + (1ull << 39), // NAND Mask + }} + }, + +// MSR_CU_CFG (0xC0011023) + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CU_CFG, // MSR Address - Shared + 0, // OR Mask + 0x00000400, // NAND Mask + }} + }, + +// MSR_CU_CFG2 (0xC001102A) +// bit[50] RdMmExtCfgQwEn = 1 +// bit[10] VicResyncChkEn = 1 + + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CU_CFG2, // MSR Address - Shared + 0x0004000000000400, // OR Mask + 0x0004000000000400, // NAND Mask + }} + }, +// MSR_CU_CFG3 (0xC001102B) +// bit[42] PwcDisableWalkerSharing = 0 +// bit[22] PfcDoubleStride = 1 + { + MsrRegister, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + MSR_CU_CFG3, // MSR Address + 0x0000000000400000, // OR Mask + 0x0000040000400000, // NAND Mask + }} + }, +}; + + +// Compute Unit Count Dependent MSR Table + +STATIC CONST MSR_CU_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrCuRegisters[] = +{ +// M S R T a b l e s +// ---------------------- + + // MSR_CU_CFG2 (0xC001102A) + // bits[37:36] - ThrottleNbInterface[3:2] = 0 + // bits[7:6] - ThrottleNbInterface[1:0] = 0 + { + CompUnitCountsMsr, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + {(COMPUTE_UNIT_RANGE_0 (1, 1) | COUNT_RANGE_NONE)}, // 1 compute unit + { + MSR_CU_CFG2, // MSR Address - Shared + 0x0000000000000000, // OR Mask + 0x00000030000000C0, // NAND Mask + } + }} + }, + + // MSR_CU_CFG2 (0xC001102A) + // bits[37:36] - ThrottleNbInterface[3:2] = 0 + // bits[7:6] - ThrottleNbInterface[1:0] = 1 + { + CompUnitCountsMsr, + { + AMD_FAMILY_15_TN, // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + {(COMPUTE_UNIT_RANGE_0 (2, 2) | COUNT_RANGE_NONE)}, // 2 compute units + { + MSR_CU_CFG2, // MSR Address - Shared + 0x0000000000000040, // OR Mask + 0x00000030000000C0, // NAND Mask + } + }} + } + +}; + + +// Shared MSRs with Special Programming Requirements Table + +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnSharedMsrWorkarounds[] = +{ + // MSR_FP_CFG (0xC0011028) + // bit[16] - DiDtMode = F3x1FC[0] + // bits[22:18] - DiDtCfg0 = F3x1FC[5:1] + // bits[34:27] - DiDtCfg1 = F3x1FC[13:6] + // bits[26:25] - DiDtCfg2 = F3x1FC[15:14] + // bits[44:42] - DiDtCfg4 = F3x1FC[19:17] + { + FamSpecificWorkaround, + { + AMD_FAMILY_15_TN, + AMD_F15_TN_ALL + }, + {AMD_PF_ALL}, + {{ + F15TnFpCfgInit, + 0x00000000 + }} + }, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable = { + CorePairPrimary, + (sizeof (F15TnSharedMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrRegisters, +}; + + +CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable = { + CorePairPrimary, + (sizeof (F15TnSharedMsrCuRegisters) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrCuRegisters, +}; + +CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable = { + CorePairPrimary, + (sizeof (F15TnSharedMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) &F15TnSharedMsrWorkarounds, +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * Update the FP_CFG MSR in current processor for Family15h TN. + * + * This function satisfies the programming requirements for the FP_CFG MSR. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnFpCfgInit ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 ProductInfo; + UINT64 FpCfg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = PRCT_INFO_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ProductInfo, StdHeader); + + LibAmdMsrRead (MSR_FP_CFG, &FpCfg, StdHeader); + ((FP_CFG_MSR *) &FpCfg)->DiDtMode = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtMode; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg0 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg0; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg1 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg1; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg2 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg2; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg4 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg4; + ((FP_CFG_MSR *) &FpCfg)->DiDtCfg5 = ((PRODUCT_INFO_REGISTER *) &ProductInfo)->DiDtCfg5; + LibAmdMsrWrite (MSR_FP_CFG, &FpCfg, StdHeader); +} + + +// Per-Node MSR with Special Programming Requirements Table +STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPerNodeMsrWorkarounds[] = +{ +// MSR C001_00[6B:64] + { + FamSpecificWorkaround, + { + (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily + AMD_F15_TN_ALL // CpuRevision + }, + {AMD_PF_ALL}, // platformFeatures + {{ + Update800MHzHtcPstateTo900MHz, // function call + 0x00000000, // data + }} + } +}; + + +CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable = { + PrimaryCores, + (sizeof (F15TnPerNodeMsrWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)), + (TABLE_ENTRY_FIELDS *) F15TnPerNodeMsrWorkarounds, +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Workaround for CPUs with a minimum P-state = 800MHz. + * + * AGESA should change the frequency of 800MHz P-states to 900MHz. + * + * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +Update800MHzHtcPstateTo900MHz ( + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + PSTATE_MSR HtcPstate; + PSTATE_MSR HtcPstateMinus1; + HTC_REGISTER HtcRegister; + + PciAddress.AddressValue = HTC_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &HtcRegister, StdHeader); + + LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader); + + if (HtcPstate.CpuFid == 0 && HtcPstate.CpuDid == 1) { + if (HtcRegister.HtcPstateLimit == 0) { + HtcPstateMinus1 = HtcPstate; + } else { + LibAmdMsrRead ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0 - 1), (UINT64 *) &HtcPstateMinus1, StdHeader); + } + HtcPstate.CpuVid = HtcPstateMinus1.CpuVid; + HtcPstate.CpuFid = 2; + LibAmdMsrWrite ((HtcRegister.HtcPstateLimit + MSR_PSTATE_0), (UINT64 *) &HtcPstate, StdHeader); + } +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c new file mode 100644 index 0000000000..022d1b4f7c --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.c @@ -0,0 +1,1031 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 models 10h - 1Fh specific utility functions. + * + * Provides numerous utility functions specific to family 15h TN. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 65284 $ @e \$Date: 2012-02-12 23:29:39 -0600 (Sun, 12 Feb 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. 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Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "F15TnUtilities.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) +#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +F15TnNbPstateDisCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnGetNbFreqNumeratorInMHz ( + IN UINT32 NbFid, + OUT UINT32 *FreqNumeratorInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnGetNbFreqDivisor ( + IN UINT32 NbDid, + OUT UINT32 *FreqDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +STATIC +F15TnCalculateNbFrequencyInMHz ( + IN UINT32 NbFid, + IN UINT32 NbDid, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnCovertVidInuV ( + IN UINT32 Vid, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnCmnGetIddDivisor ( + IN UINT32 IddDiv, + OUT UINT32 *IddDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnCmnCalculateCurrentInmA ( + IN UINT32 IddValue, + IN UINT32 IddDiv, + OUT UINT32 *CurrentInmA, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnSetDownCoreRegister ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Get CPU pstate current. + * + * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}. + * + * This function returns the ProcIddMax. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Pstate The P-state to check. + * @param[out] ProcIddMax P-state current in mA. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE P-state is enabled + * @retval FALSE P-state is disabled + */ +BOOLEAN +F15TnGetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 MsrAddress; + PSTATE_MSR PstateMsr; + BOOLEAN IsPstateEnabled; + PCI_ADDR PciAddress; + NB_CAPS_2_REGISTER NbCap2; + UINT32 ProcIddMaxPerCore; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetProcIddMax - P%d\n", Pstate); + + IsPstateEnabled = FALSE; + + MsrAddress = (UINT32) (Pstate + PS_REG_BASE); + ASSERT (MsrAddress <= PS_MAX_REG); + + LibAmdMsrRead (MsrAddress, (UINT64 *) &PstateMsr, StdHeader); + F15TnCmnCalculateCurrentInmA ((UINT32) PstateMsr.IddValue, (UINT32) PstateMsr.IddDiv, &ProcIddMaxPerCore, StdHeader); + PciAddress.AddressValue = NB_CAPS_REG2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbCap2, StdHeader); + *ProcIddMax = (UINT32) ProcIddMaxPerCore * (NbCap2.CmpCap + 1); + IDS_HDT_CONSOLE (CPU_TRACE, " Pstate %d ProcIddMax %d CmpCap %d\n", Pstate, *ProcIddMax, NbCap2.CmpCap); + if (PstateMsr.PsEnable == 1) { + IsPstateEnabled = TRUE; + } + return IsPstateEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Set down core register on Trinity + * + * This function set F3x190 Downcore Control Register[5:0] + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket Socket ID. + * @param[in] Module Module ID in socket. + * @param[in] LeveledCores Number of core. + * @param[in] CoreLevelMode Core level mode. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Down Core register is updated. + * @retval FALSE Down Core register is not updated. + */ +BOOLEAN +F15TnSetDownCoreRegister ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + UINT32 CoreDisableBits; + PCI_ADDR PciAddress; + BOOLEAN IsUpdated; + AGESA_STATUS AgesaStatus; + + IsUpdated = FALSE; + CoreDisableBits = 0; + + if (CoreLevelMode == CORE_LEVEL_COMPUTE_UNIT) { + // CoreLevelMode == CORE_LVEL_COMPUTE_UNIT is not supported. + } else { + switch (*LeveledCores) { + // Only down core to 2 cores will take effect through a warm reset. + case 2: + CoreDisableBits = DOWNCORE_MASK_DUAL; + break; + } + } + + if (CoreDisableBits != 0) { + if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) { + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_2_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + LocalPciRegister = (LocalPciRegister & 0xFF) + 1; + LocalPciRegister = (1 << LocalPciRegister) - 1; + CoreDisableBits &= LocalPciRegister; + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = DOWNCORE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if ((LocalPciRegister | CoreDisableBits) != LocalPciRegister) { + LocalPciRegister |= CoreDisableBits; + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + IsUpdated = TRUE; + } + } + } + + return IsUpdated; +} + + +CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling = +{ + 0, + F15TnSetDownCoreRegister +}; + + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the NB clock on the desired node. + * + * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] FrequencyInMHz Northbridge clock frequency in MHz. + * @param[in] StdHeader Header for library and services. + * + * @return AGESA_SUCCESS FrequencyInMHz is valid. + */ +AGESA_STATUS +F15TnGetCurrentNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_STS_REGISTER NbPstateStsReg; + PCI_ADDR PciAddress; + AGESA_STATUS ReturnCode; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetCurrentNbFrequency\n"); + + PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateStsReg, StdHeader); + ReturnCode = F15TnCalculateNbFrequencyInMHz ( + NbPstateStsReg.CurNbFid, + NbPstateStsReg.CurNbDid, + FrequencyInMHz, + StdHeader + ); + return ReturnCode; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the node's minimum and maximum northbridge frequency. + * + * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[out] MinFreqInMHz The node's minimum northbridge frequency. + * @param[out] MaxFreqInMHz The node's maximum northbridge frequency. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS Northbridge frequency is valid + */ +AGESA_STATUS +F15TnGetMinMaxNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + OUT UINT32 *MinFreqInMHz, + OUT UINT32 *MaxFreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + INT8 NbPsMaxVal; + UINT8 i; + UINT32 LocalPciRegister; + AGESA_STATUS AgesaStatus; + + AgesaStatus = AGESA_ERROR; + + // Obtain the max NB frequency on the node + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal; + + // Starting from NB Pmax + for (i = 0; i <= NbPsMaxVal; i++) { + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = (NB_PSTATE_0 + (4 * i)); + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + + // Ensure that the NB Pstate is enabled + if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { + AgesaStatus = F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid, + ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid, + MaxFreqInMHz, + StdHeader); + break; + } + } + // If all of NbPstates are disabled, get MaxFreqInMHz from CurNbPstate + if (i > NbPsMaxVal) { + PciAddress->Address.Register = NB_PSTATE_STATUS; + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbFid, + ((NB_PSTATE_STS_REGISTER *) &LocalPciRegister)->CurNbDid, + MaxFreqInMHz, + StdHeader); + // No one NbPstate is enabled, so set Min = Max + *MinFreqInMHz = *MaxFreqInMHz; + ASSERT (FALSE); + } else { + // If platform configuration disable NB P-states, return the NB P0 frequency + // as both the min and max frequency on the node. + if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { + *MinFreqInMHz = *MaxFreqInMHz; + } else { + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + NbPsMaxVal = (INT8) ((NB_PSTATE_CTRL_REGISTER *) &LocalPciRegister)->NbPstateMaxVal; + + // Obtain the min NB frequency on the node, starting from NB Pmin + for (/* NbPsMaxVal */; NbPsMaxVal >= 0; NbPsMaxVal--) { + PciAddress->Address.Function = FUNC_5; + PciAddress->Address.Register = (NB_PSTATE_0 + (4 * NbPsMaxVal)); + LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader); + + // Ensure that the NB Pstate is enabled + if (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbPstateEn == 1) { + AgesaStatus = F15TnCalculateNbFrequencyInMHz (((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbFid, + ((NB_PSTATE_REGISTER *) &LocalPciRegister)->NbDid, + MinFreqInMHz, + StdHeader); + break; + } + } + } + } + IDS_OPTION_HOOK (IDS_NBPS_MIN_FREQ, MinFreqInMHz, StdHeader); + + return AgesaStatus; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Determines the NB clock on the desired node. + * + * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question. + * @param[in] NbPstate The NB P-state number to check. + * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz. + * @param[out] FreqDivisor The desired node's frequency divisor. + * @param[out] VoltageInuV The desired node's voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NbPstate is valid + * @retval FALSE NbPstate is disabled or invalid + */ +BOOLEAN +F15TnGetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NbVid; + BOOLEAN PstateIsValid; + NB_PSTATE_CTRL_REGISTER NbPstateCtrlReg; + NB_PSTATE_REGISTER NbPstateReg; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbPstateInfo - NB P%d\n", NbPstate); + + ASSERT ((PciAddress->Address.Segment == 0) && (PciAddress->Address.Bus == 0) && (PciAddress->Address.Device == 0x18)); + + PstateIsValid = FALSE; + + // If NB P1, P2, or P3 is requested, make sure that NB Pstate is enabled + if ((NbPstate == 0) || (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) { + PciAddress->AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateCtrlReg, StdHeader); + + ASSERT ((NbPstate < NM_NB_PS_REG) && (NbPstateCtrlReg.NbPstateMaxVal < NM_NB_PS_REG)); + if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) { + PciAddress->Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate)); + LibAmdPciRead (AccessWidth32, *PciAddress, &NbPstateReg, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " En:%d Fid:%x Did:%x Vid:%x\n", NbPstateReg.NbPstateEn, NbPstateReg.NbFid, NbPstateReg.NbDid, GetF15TnNbVid (&NbPstateReg)); + + // Check if at least NB P0 is enabled. + ASSERT ((NbPstate == 0) ? (NbPstateReg.NbPstateEn == 1) : TRUE); + // Ensure that requested NbPstate is enabled + if (NbPstateReg.NbPstateEn == 1) { + // Check for P-state Bandwidth Requirements on + // "All NB P-states must be defined such that D18F5x1[6C:60][NbFid] <= 2Eh" + ASSERT (NbPstateReg.NbFid <= 0x2E); + F15TnGetNbFreqNumeratorInMHz (NbPstateReg.NbFid, FreqNumeratorInMHz, StdHeader); + F15TnGetNbFreqDivisor (NbPstateReg.NbDid, FreqDivisor, StdHeader); + // Check for P-state Bandwidth Requirements on + // "NBCOF >= 700MHz" + ASSERT ((*FreqNumeratorInMHz / *FreqDivisor) >= 700); + + NbVid = GetF15TnNbVid (&NbPstateReg); + F15TnCovertVidInuV (NbVid, VoltageInuV, StdHeader); + PstateIsValid = TRUE; + IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstate %d is Valid. NbVid=%d VoltageInuV=%d\n", NbPstate, NbVid, *VoltageInuV); + } + } + } + return PstateIsValid; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get NB pstate current. + * + * @CpuServiceMethod{::F_CPU_GET_NB_IDD_MAX}. + * + * This function returns the NbIddMax. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] NbPstate The NB P-state to check. + * @param[out] NbIddMax NB P-state current in mA. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE NB P-state is enabled, and NbIddMax is valid. + * @retval FALSE NB P-state is disabled + */ +BOOLEAN +F15TnGetNbIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 NbPstate, + OUT UINT32 *NbIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN IsNbPsEnabled; + PCI_ADDR PciAddress; + NB_PSTATE_CTRL_REGISTER NbPstateCtrlReg; + NB_PSTATE_REGISTER NbPstateReg; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbIddMax - NB P%d\n", NbPstate); + + IsNbPsEnabled = FALSE; + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateCtrlReg, StdHeader); + + ASSERT (NbPstate < NM_NB_PS_REG); + if (NbPstate <= NbPstateCtrlReg.NbPstateMaxVal) { + PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate)); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader); + + // Ensure that requested NbPstate is enabled + if (NbPstateReg.NbPstateEn == 1) { + F15TnCmnCalculateCurrentInmA (NbPstateReg.NbIddValue, NbPstateReg.NbIddDiv, NbIddMax, StdHeader); + IsNbPsEnabled = TRUE; + IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstate %d is Valid. NbIddMax %d\n", NbPstate, *NbIddMax); + } + } + return IsNbPsEnabled; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Get the number of physical cores of current processor. + * + * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The number of physical cores. + */ +UINT8 +F15TnGetNumberOfPhysicalCores ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA CpuId; + + // + //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc. + // + LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader); + return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1)); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Use the Mailbox Register to get the Ap Mailbox info for the current core. + * + * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}. + * + * Access the mailbox register used with this NB family. This is valid until the + * point that some init code initializes the mailbox register for its normal use. + * The Machine Check Misc (Thresholding) register is available as both a PCI config + * register and a MSR, so it can be used as a mailbox from HT to other functions. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[out] ApMailboxInfo The AP Mailbox info + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +F15TnGetApMailboxFromHardware ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT AP_MAILBOXES *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + // For Family 15h Trinity, we will return socket 0, node 0, module 0, module type 0, and 0 for + // the system degree + ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000; + ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get this AP's system core number from hardware. + * + * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}. + * + * Returns the system core number from the scratch MSR, where + * it was saved at heap initialization. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return The AP's unique core number + */ +UINT32 +F15TnGetApCoreNumber ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CPUID_DATA Cpuid; + + LibAmdCpuidRead (0x1, &Cpuid, StdHeader); + return ((Cpuid.EBX_Reg >> 24) & 0xFF); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Is the Northbridge PState feature enabled? + * + * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval TRUE The NB PState feature is enabled. + * @retval FALSE The NB PState feature is not enabled. + */ +BOOLEAN +F15TnIsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + BOOLEAN PowerMode; + BOOLEAN SkipHwCfg; + NB_PSTATE_STS_REGISTER NbPstateSts; + NB_PSTATE_CTRL_REGISTER NbPstateCtrl; + + + PciAddress.AddressValue = NB_PSTATE_STATUS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateSts, StdHeader); + if (NbPstateSts.NbPstateDis == 1) { + return FALSE; + } + + SkipHwCfg = FALSE; + IDS_OPTION_HOOK (IDS_NBPSDIS_OVERRIDE, &SkipHwCfg, StdHeader); + if (!SkipHwCfg) { + } + + // Defaults to Power Optimized Mode + PowerMode = TRUE; + + // If system is optimized for performance, disable NB P-States + if (PlatformConfig->PlatformProfile.PlatformPowerPolicy == Performance) { + PowerMode = FALSE; + } + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, (VOID *) &NbPstateCtrl, StdHeader); + if (((NbPstateCtrl.NbPstateMaxVal != 0) || SkipHwCfg) && (PowerMode)) { + return TRUE; + } + return FALSE; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Disable NB P-state. + * - clear F5x1[6C:64] + * - clear F5x170[NbPstateMaxVal] + * - set F5x170[SwNbPstateLoDis] + * - clear MSRC001_00[6B:64][NbPstate] + * + * @param[in] FamilySpecificServices The current Family Specific Services + * @param[in] CpuEarlyParamsPtr Service Parameters + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +F15TnNbPstateDis ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT32 PciData; + UINT32 NbPsCtrl; + UINT32 NbPsCtrlOrg; + UINT32 AndMask; + BOOLEAN SkipNbPsLoPart; + AP_TASK TaskPtr; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnNbPstateDis\n"); + + // Check whether NB P-state is disabled + if (!FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { + + IDS_HDT_CONSOLE (CPU_TRACE, " NB Pstates disabled\n"); + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPsCtrlOrg = NbPsCtrl; + + AndMask = 0x00000000; + // If CurNbPstate is not NB P0, get the Pstate pointed to by CurNbPstate and copy it's value to NB P0 to P3 and clear NbPstateHi + PciAddress.Address.Register = NB_PSTATE_STATUS; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + + SkipNbPsLoPart = FALSE; + + if (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0) { + PciAddress.Address.Register = NB_PSTATE_0 + (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate * 4); + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + + for (i = 1; i < NM_NB_PS_REG; i++) { + PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, PciData, StdHeader); + } + + if (!SkipNbPsLoPart) { + // Program D18F5x170 to transition the NB P-state: + // 1) NbPstateLo = NbPstateMaxVal. + // 2) SwNbPstateLoDis = NbPstateDisOnP0 = NbPstateThreshold = 0. + + PciAddress.Address.Register = NB_PSTATE_CTRL; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateDisOnP0 = 0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateThreshold = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // Wait for D18F5x174[CurNbPstate] to equal NbPstateLo. + PciAddress.Address.Register = NB_PSTATE_STATUS; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateLo); + } + } + + // Program D18F5x170 to force the NB P-state: + // 1) NbPstateHi = target NB P-state. + // 2) SwNbPstateLoDis = 1 + // And clear F5x170[NbPstateMaxVal] + PciAddress.Address.Register = NB_PSTATE_CTRL; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateHi = 0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->NbPstateMaxVal = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrl)->SwNbPstateLoDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // Wait for D18F5x174[CurNbPstate] to equal the target NB P-state. + PciAddress.Address.Register = NB_PSTATE_STATUS; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + } while (((NB_PSTATE_STS_REGISTER *) &PciData)->CurNbPstate != 0); + + // Clear F5x1[6C:64] + AndMask = 0x00000000; + for (i = 1; i < NM_NB_PS_REG; i++) { + PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, AndMask, StdHeader); + } + + // Clear MSRC001_00[6B:64][NbPstate] on cores + TaskPtr.FuncAddress.PfApTask = F15TnNbPstateDisCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.DataTransfer.DataPtr = NULL; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); + + + // BIOS performs the following to release the NB P-state force: + // 1. Restore the initial D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateLo] values. + // 2. Restore the initial D18F5x170[NbPstateThreshold, NbPstateHi] values. + PciAddress.Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateLo = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->SwNbPstateLoDis; + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateDisOnP0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateHi = 0; + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateMaxVal = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &PciData)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOrg)->NbPstateThreshold; + LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader); + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Disable NB P-state on core. + * - clear MSRC001_00[6B:64][NbPstate]. + * + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnNbPstateDisCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT64 MsrData; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnNbPstateDisCore\n"); + + // Only one core per compute unit needs to clear NbPstate in P-state MSRs + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + for (i = MSR_PSTATE_0; i <= MSR_PSTATE_7; i++) { + LibAmdMsrRead (i, &MsrData, StdHeader); + ((PSTATE_MSR *) &MsrData)->NbPstate = 0; + LibAmdMsrWrite (i, &MsrData, StdHeader); + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get NB Frequency Numerator in MHz + * + * @param[in] NbFid NB Frequency ID to convert + * @param[out] FreqNumeratorInMHz The desire NB FID's frequency numerator in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnGetNbFreqNumeratorInMHz ( + IN UINT32 NbFid, + OUT UINT32 *FreqNumeratorInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbFreqNumeratorInMHz - NbFid=%d\n", NbFid); + *FreqNumeratorInMHz = (NbFid + 4) * 100; + IDS_HDT_CONSOLE (CPU_TRACE, " FreqNumeratorInMHz=%d\n", *FreqNumeratorInMHz); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get NB Frequency Divisor + * + * @param[in] NbDid NB Divisor ID to convert. + * @param[out] FreqDivisor The desire NB DID's frequency divisor. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnGetNbFreqDivisor ( + IN UINT32 NbDid, + OUT UINT32 *FreqDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetNbFreqDivisor - NbDid=%d\n", NbDid); + *FreqDivisor = (1 << NbDid); + IDS_HDT_CONSOLE (CPU_TRACE, " FreqDivisor=%d\n", *FreqDivisor); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Calculate NB Frequency in MHz + * + * @param[in] NbFid NB Frequency ID to convert + * @param[in] NbDid NB Divisor ID to convert. + * @param[out] FrequencyInMHz The Northbridge clock frequency in megahertz. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @return AGESA_SUCCESS FrequencyInMHz is valid. + */ +AGESA_STATUS +STATIC +F15TnCalculateNbFrequencyInMHz ( + IN UINT32 NbFid, + IN UINT32 NbDid, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 FreqNumeratorInMHz; + UINT32 FreqDivisor; + AGESA_STATUS ReturnStatus; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCalculateNbFrequencyInMHz - NbFid=%x, NbDid=%x\n", NbFid, NbDid); + + ReturnStatus = AGESA_SUCCESS; + F15TnGetNbFreqNumeratorInMHz (NbFid, &FreqNumeratorInMHz, StdHeader); + F15TnGetNbFreqDivisor (NbDid, &FreqDivisor, StdHeader); + *FrequencyInMHz = FreqNumeratorInMHz / FreqDivisor; + IDS_HDT_CONSOLE (CPU_TRACE, " FrequencyInMHz=%d\n", *FrequencyInMHz); + + return ReturnStatus; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Convert VID to microvolts(uV) + * + * @param[in] Vid The voltage ID of SVI2 encoding to be converted. + * @param[out] VoltageInuV The voltage in microvolts. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + */ +VOID +STATIC +F15TnCovertVidInuV ( + IN UINT32 Vid, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCovertVidInuV\n"); + // Maximum 1.55V, 6.25mV per stpe + *VoltageInuV = ConvertVidInuV(Vid); + IDS_HDT_CONSOLE (CPU_TRACE, " Vid=%x, VoltageInuV=%d\n", Vid, *VoltageInuV); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Get Core/NB Idd Divisor + * + * @param[in] IddDiv Core/NB current divisor to convert. + * @param[out] IddDivisor The desire Core/NB current divisor. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +STATIC +F15TnCmnGetIddDivisor ( + IN UINT32 IddDiv, + OUT UINT32 *IddDivisor, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCmnGetIddDivisor - IddDiv=%d\n", IddDiv); + + switch (IddDiv) { + case 0: + *IddDivisor = 1000; + break; + case 1: + *IddDivisor = 100; + break; + case 2: + *IddDivisor = 10; + break; + default: // IddDiv = 3 is reserved. Use 10 + *IddDivisor = 10; + ASSERT (FALSE); + break; + } + IDS_HDT_CONSOLE (CPU_TRACE, " IddDivisor=%d\n", *IddDivisor); +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Calculate Core/NB current in mA + * + * @param[in] IddValue Core/NB current value. + * @param[in] IddDiv Core/NB current divisor. + * @param[out] CurrentInmA The Core/NB current in milliampere. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + */ +VOID +STATIC +F15TnCmnCalculateCurrentInmA ( + IN UINT32 IddValue, + IN UINT32 IddDiv, + OUT UINT32 *CurrentInmA, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 IddDivisor; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnCmnCalculateCurrentInmA - IddValue=%x, IddDiv=%x\n", IddValue, IddDiv); + + F15TnCmnGetIddDivisor (IddDiv, &IddDivisor, StdHeader); + *CurrentInmA = IddValue * IddDivisor; + + IDS_HDT_CONSOLE (CPU_TRACE, " CurrentInmA=%d\n", *CurrentInmA); +} + + + + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h new file mode 100644 index 0000000000..1b971fb8b8 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnUtilities.h @@ -0,0 +1,177 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity specific utility functions. + * + * Provides numerous utility functions specific to family 15h. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _F15_TN_UTILITES_H_ +#define _F15_TN_UTILITES_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +UINT8 +F15TnGetNumberOfPhysicalCores ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnGetApMailboxFromHardware ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT AP_MAILBOXES *ApMailboxInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnIsNbPstateEnabled ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnNbPstateDis ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnGetProcIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 Pstate, + OUT UINT32 *ProcIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnGetNbIddMax ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN UINT8 NbPstate, + OUT UINT32 *NbIddMax, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetCurrentNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetMinMaxNbFrequency ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + OUT UINT32 *MinFreqInMHz, + OUT UINT32 *MaxFreqInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +F15TnGetNbPstateInfo ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR *PciAddress, + IN UINT32 NbPstate, + OUT UINT32 *FreqNumeratorInMHz, + OUT UINT32 *FreqDivisor, + OUT UINT32 *VoltageInuV, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +F15TnGetApCoreNumber ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c new file mode 100644 index 0000000000..2235eedd2d --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCacheFlushOnHalt.c @@ -0,0 +1,191 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Cache Flush On Halt Function for Family 15h Trinity. + * + * Contains code to initialize Cache Flush On Halt feature for Family 15h Trinity. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + *---------------------------------------------------------------------------- + */ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuPostInit.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +SetF15TnCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * P U B L I C F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * Enable Cpu Cache Flush On Halt Function + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + */ +VOID +SetF15TnCacheFlushOnHaltRegister ( + IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1; + CSTATE_CTRL1_REGISTER CstateCtrl1; + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 + // Set D18F3xDC[CacheFlushOnHaltTmr] + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7; + ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x14; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + + // Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold] + PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + CstatePolicyCtrl1.CacheFlushTmr = 0x14; + CstatePolicyCtrl1.CacheFlushSucMonThreshold = 7; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); + + // Set cache flush bits in D18F4x118 + PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + // Set C-state Action Field 0 + CstateCtrl1.CacheFlushEnCstAct0 = 1; + CstateCtrl1.CacheFlushTmrSelCstAct0 = 2; + CstateCtrl1.ClkDivisorCstAct0 = 0; + // Set C-state Action Field 1 + CstateCtrl1.CacheFlushEnCstAct1 = 1; + CstateCtrl1.CacheFlushTmrSelCstAct1 = 1; + CstateCtrl1.ClkDivisorCstAct1 = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); + + //Override the default setting + IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader); + } +} + +CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt = +{ + 0, + SetF15TnCacheFlushOnHaltRegister +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c new file mode 100644 index 0000000000..64e82ef434 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.c @@ -0,0 +1,280 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for core P-states + * + * Performs the "Core Minimum P-State Transition Sequence After Warm Reset" + * as described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuRegisters.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "OptionMultiSocket.h" +#include "cpuF15TnCoreAfterReset.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnPmCoreAfterResetPhase1OnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnPmCoreAfterResetPhase2OnCore ( + IN VOID *HwPsMaxVal, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h Trinity core 0 entry point for performing the necessary steps for core + * P-states after a warm reset has occurred. + * + * The steps are as follows: + * 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. + * 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + * MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. + * 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all + * cores in the processor. + * 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + * MSRC001_00[6B:64] indexed by MSRC001_0061[PstateMaxVal]. + * 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for + * MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by + * MSRC001_0061[PstateMaxVal]. + * 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParamsPtr Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmCoreAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Core; + UINT32 HwPsMaxVal; + PCI_ADDR PciAddress; + AP_TASK TaskPtr; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterReset\n"); + + GetCurrentCore (&Core, StdHeader); + ASSERT (Core == 0); + + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = CPTC2_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader); + HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; + + // Launch each local core to perform steps 1 through 3. + TaskPtr.FuncAddress.PfApTask = F15TnPmCoreAfterResetPhase1OnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); + + // Launch each local core to perform steps 4 through 6. + TaskPtr.FuncAddress.PfApTaskI = F15TnPmCoreAfterResetPhase2OnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 1; + TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr); +} + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all + * cores of a family 15h socket. + * + * This function implements steps 1 - 3 on each core. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmCoreAfterResetPhase1OnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 CofvidSts; + UINT64 LocalMsrRegister; + UINT64 PstateCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterResetPhase1OnCore\n"); + + // 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor. + PstateCtrl = 0; + LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); + + // 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + // MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit]. + do { + LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader); + LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader); + } while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) || + (((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid)); + + // 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all + // cores in the processor. + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); + ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal; + LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmCoreAfterReset to perform MSR initialization on all + * cores of a family 15h socket. + * + * This function implements steps 4 - 6 on each core. + * + * @param[in] HwPsMaxVal Index of the highest enabled HW P-state. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmCoreAfterResetPhase2OnCore ( + IN VOID *HwPsMaxVal, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 TargetPsMsr; + UINT64 LocalMsrRegister; + UINT64 PstateCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmCoreAfterResetPhase2OnCore\n"); + + // 4. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from + // MSRC001_00[6B:64] indexed by D18F3xDC[PstateMaxVal]. + LibAmdMsrRead ((*(UINT32 *) HwPsMaxVal) + MSR_PSTATE_0, &TargetPsMsr, StdHeader); + do { + LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); + } while ((((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) || + (((COFVID_STS_MSR *) &LocalMsrRegister)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid)); + + // 5. If MSRC001_0071[CurPstateLimit] != MSRC001_0071[CurPstate], wait for + // MSRC001_0071[CurCpuVid] = [CpuVid] from MSRC001_00[6B:64] indexed by + // MSRC001_0061[PstateMaxVal]. + if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstateLimit != ((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate) { + do { + LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader); + } while (GetF15TnCurCpuVid (&LocalMsrRegister) != GetF15TnCpuVid (&TargetPsMsr)); + } + + // 6. Wait for MSRC001_0063[CurPstate] = MSRC001_0062[PstateCmd]. + LibAmdMsrRead (MSR_PSTATE_CTL, &PstateCtrl, StdHeader); + do { + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + } while (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate != ((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h new file mode 100644 index 0000000000..1e5b1ba3a2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnCoreAfterReset.h @@ -0,0 +1,105 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for core P-states + * + * Contains code that provide power management functionality + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_CORE_AFTER_RESET_H_ +#define _CPU_F15_TN_CORE_AFTER_RESET_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmCoreAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_TN_CORE_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c new file mode 100644 index 0000000000..e0240bdeb6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c @@ -0,0 +1,430 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD DMI Record Creation API, and related functions for Family15h Trinity. + * + * Contains code that produce the DMI related information. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 64351 $ @e \$Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $ + * + */ +/***************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuFamilyTranslation.h" +#include "cpuPstateTables.h" +#include "cpuLateInit.h" +#include "cpuF15Dmi.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuServices.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +CONST CHAR8 ROMDATA str_A10[] = "AMD A10-"; +CONST CHAR8 ROMDATA str_A8[] = "AMD A8-"; +CONST CHAR8 ROMDATA str_A6[] = "AMD A6-"; +CONST CHAR8 ROMDATA str_A4[] = "AMD A4-"; +CONST CHAR8 ROMDATA str_PhenomII[] = "AMD Phenom(TM) II"; +CONST CHAR8 ROMDATA str_AthlonII[] = "AMD Athlon(TM) II"; +CONST CHAR8 ROMDATA str_SempronII[] = "AMD Sempron(TM) II"; +CONST CHAR8 ROMDATA str_Sempron[] = "AMD Sempron(TM)"; +/*--------------------------------------------------------------------------------------- + * Processor Family Table + * + * 048h = "A-Series" + * 0ECh = "AMD Phenom(TM) II Processor Family" + * 0EDh = "AMD Athlon(tm) II" + * 085h = "AMD Sempron(tm)" + * 0E5h = "AMD Sempron(tm) II" + + *-------------------------------------------------------------------------------------*/ + +CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFP2T4ProcFamily[] = +{ + {str_A10, 0x48}, + {str_A8, 0x48}, + {str_A6, 0x48}, + {str_A4, 0x48}, +}; + +CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFS1T4ProcFamily[] = +{ + {str_A10, 0x48}, + {str_A8, 0x48}, + {str_A6, 0x48}, + {str_A4, 0x48}, +}; + +CONST CPU_T4_PROC_FAMILY ROMDATA F15TnFM2T4ProcFamily[] = +{ + {str_A10, 0x48}, + {str_A8, 0x48}, + {str_A6, 0x48}, + {str_A4, 0x48}, + {str_PhenomII, 0xEC}, + {str_AthlonII, 0xED}, + {str_SempronII, 0xE5}, + {str_Sempron, 0x85}, +}; +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +DmiF15TnGetInfo ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +DmiF15TnGetT4ProcFamily ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT8 +DmiF15TnGetVoltage ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +DmiF15TnGetMemInfo ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT16 +DmiF15TnGetExtClock ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetInfo + * + * Get CPU type information + * + * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct. + * @param[in] StdHeader Standard Head Pointer + * + */ +VOID +DmiF15TnGetInfo ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 NumOfCoresPerCU; + CPUID_DATA CpuId; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader); + CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20 + CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16 + CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8 + CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4 + CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0 + + CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28 + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfPhysicalCores (FamilySpecificServices, StdHeader); + CpuInfoPtr->TotalCoreNumber--; + + LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader); + CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0 + + switch (CpuInfoPtr->PackageType) { + case TN_SOCKET_FP2: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE; + break; + case TN_SOCKET_FS1: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_FS1; + break; + case TN_SOCKET_FM2: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_FM2; + break; + default: + CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN; + break; + } + + switch (GetComputeUnitMapping (StdHeader)) { + case AllCoresMapping: + NumOfCoresPerCU = 1; + break; + case EvenCoresMapping: + NumOfCoresPerCU = 2; + break; + default: + NumOfCoresPerCU = 2; + } + // L1 Size & Associativity + LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, StdHeader); + CpuInfoPtr->CacheInfo.L1CacheSize = (UINT32) (((UINT8) ((CpuId.ECX_Reg >> 24) * NumOfCoresPerCU) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); + + CpuInfoPtr->CacheInfo.L1CacheAssoc = DMI_ASSOCIATIVE_2_WAY; // Per the BKDG, this is hard-coded to 2-Way. + + // L2 Size & Associativity + LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader); + CpuInfoPtr->CacheInfo.L2CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfoPtr->EnabledCoreNumber + 1) / NumOfCoresPerCU); + + CpuInfoPtr->CacheInfo.L2CacheAssoc = DMI_ASSOCIATIVE_16_WAY; // Per the BKDG, this is hard-coded to 16-Way. + + // L3 Size & Associativity + CpuInfoPtr->CacheInfo.L3CacheSize = 0; + CpuInfoPtr->CacheInfo.L3CacheAssoc = DMI_ASSOCIATIVE_UNKNOWN; + } + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetT4ProcFamily + * + * Get type 4 processor family information + * + * @param[in,out] T4ProcFamily Pointer to type 4 processor family information. + * @param[in] *CpuDmiProcFamilyTable Pointer to DMI family special service + * @param[in] *CpuInfo Pointer to CPU_TYPE_INFO struct + * @param[in] StdHeader Standard Head Pointer + * + */ +VOID +DmiF15TnGetT4ProcFamily ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CHAR8 NameString[49]; + CONST CHAR8 *DmiString; + CONST VOID *DmiStringTable; + UINT8 NumberOfDmiString; + UINT8 i; + + // Get name string from MSR_C001_00[30:35] + GetNameString (NameString, StdHeader); + // Get DMI String + DmiStringTable = NULL; + switch (CpuInfo->PackageType) { + case TN_SOCKET_FP2: + DmiStringTable = (CONST VOID *) &F15TnFP2T4ProcFamily[0]; + NumberOfDmiString = sizeof (F15TnFP2T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); + break; + case TN_SOCKET_FS1: + DmiStringTable = (CONST VOID *) &F15TnFS1T4ProcFamily[0]; + NumberOfDmiString = sizeof (F15TnFS1T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); + break; + case TN_SOCKET_FM2: + DmiStringTable = (CONST VOID *) &F15TnFM2T4ProcFamily[0]; + NumberOfDmiString = sizeof (F15TnFM2T4ProcFamily) / sizeof (CPU_T4_PROC_FAMILY); + break; + default: + DmiStringTable = NULL; + NumberOfDmiString = 0; + break; + } + + // Find out which DMI string matches current processor's name string + *T4ProcFamily = P_FAMILY_UNKNOWN; + if ((DmiStringTable != NULL) && (NumberOfDmiString != 0)) { + for (i = 0; i < NumberOfDmiString; i++) { + DmiString = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).Stringstart; + if (IsSourceStrContainTargetStr (NameString, DmiString, StdHeader)) { + *T4ProcFamily = (((CPU_T4_PROC_FAMILY *) DmiStringTable)[i]).T4ProcFamilySetting; + break; + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetVoltage + * + * Get the voltage value according to SMBIOS SPEC's requirement. + * + * @param[in] StdHeader Standard Head Pointer + * + * @retval Voltage - CPU Voltage. + * + */ +UINT8 +DmiF15TnGetVoltage ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 MaxVid; + UINT8 Voltage; + UINT8 NumberBoostStates; + UINT64 MsrData; + PCI_ADDR TempAddr; + CPB_CTRL_REGISTER CpbCtrl; + + // Voltage = 0x80 + (voltage at boot time * 10) + TempAddr.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C + NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates; + + LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); + MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); + + if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) { + Voltage = 0; + } else { + Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000); + } + + Voltage += 0x80; + return (Voltage); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetMemInfo + * + * Get memory information. + * + * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct. + * @param[in] StdHeader Standard Head Pointer + * + */ +VOID +DmiF15TnGetMemInfo ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + CpuGetMemInfoPtr->EccCapable = FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * DmiF15TnGetExtClock + * + * Get the external clock Speed + * + * @param[in] StdHeader Standard Head Pointer + * + * @retval ExtClock - CPU external clock Speed. + * + */ +UINT16 +DmiF15TnGetExtClock ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + return (EXTERNAL_CLOCK_100MHZ); +} + +/* -----------------------------------------------------------------------------*/ +CONST PROC_FAMILY_TABLE ROMDATA ProcFamily15TnDmiTable = +{ +// This table is for Processor family 15h Trinity + AMD_FAMILY_15_TN, // ID for Family 15h Trinity + DmiF15TnGetInfo, // Transfer vectors for family + DmiF15TnGetT4ProcFamily, // Get type 4 processor family information + DmiF15TnGetVoltage, // specific routines (above) + DmiF15GetMaxSpeed, + DmiF15TnGetExtClock, + DmiF15TnGetMemInfo, // Get memory information + 0, + NULL +}; + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c new file mode 100644 index 0000000000..b1ac32f212 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnHtc.c @@ -0,0 +1,204 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 TN HTC Initialization + * + * Enables Hardware Thermal Control (HTC) feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63692 $ @e \$Date: 2012-01-03 22:13:28 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "CommonReturns.h" +#include "cpuHtc.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNHTC_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +F15TnHtcInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Entry point for enabling Hardware Thermal Control + * + * This function must be run after all P-State routines have been executed + * + * @param[in] HtcServices The current CPU's family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Platform profile/build option config structure. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializeHtc ( + IN HTC_FAMILY_SERVICES *HtcServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + F15TnHtcInit (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader); + } + + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Main entry point for initializing the Thermal Control + * safety net feature. + * + * This must be run by all Family 15h Trinity core 0s in the system. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Platform profile/build option config structure + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + */ +VOID +F15TnHtcInit ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + + PciAddress.AddressValue = NB_CAPS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) { + // Enable HTC + PciAddress.Address.Register = HTC_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) { + // Enable HTC + ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1; + } else { + // Disable HTC + ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 0; + } + IDS_OPTION_HOOK (IDS_HTC_CTRL, &LocalPciRegister, StdHeader); + LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); + } +} + +CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport = +{ + 0, + (PF_HTC_IS_SUPPORTED) CommonReturnTrue, + F15TnInitializeHtc +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c new file mode 100644 index 0000000000..1f23cc5948 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.c @@ -0,0 +1,496 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for NB P-states + * + * Performs the "NB COF and VID Transition Sequence After Warm Reset" + * as described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 64197 $ @e \$Date: 2012-01-17 16:18:33 -0600 (Tue, 17 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "GeneralServices.h" +#include "cpuServices.h" +#include "heapManager.h" +#include "cpuF15TnNbAfterReset.h" +#include "GnbRegisterAccTN.h" +#include "GnbRegistersTN.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnPmNbAfterResetOnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +TransitionToNbLow ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +TransitionToNbHigh ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +WaitForNbTransitionToComplete ( + IN PCI_ADDR PciAddress, + IN UINT32 PstateIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h Trinity core 0 entry point for performing the necessary steps after + * a warm reset has occurred. + * + * The steps are as follows: + * + * 1. Temp1=D18F5x170[SwNbPstateLoDis]. + * 2. Temp2=D18F5x170[NbPstateDisOnP0]. + * 3. Temp3=D18F5x170[NbPstateThreshold]. + * 4. Temp4=D18F5x170[NbPstateGnbSlowDis]. + * 5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11. + * 6. Write 1 to D18F5x170[NbPstateGnbSlowDis]. + * 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + * 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + * 9. Set D18F5x170[SwNbPstateLoDis]=1. + * 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15. + * 11. Write 1 to D18F5x170[SwNbPstateLoDis]. + * 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + * 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + * 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb- + * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + * 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP- + * stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParamsPtr Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmNbAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 TaskedCore; + UINT32 Ignored; + AP_TASK TaskPtr; + PCI_ADDR PciAddress; + AGESA_STATUS IgnoredSts; + LOCATE_HEAP_PTR Locate; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterReset\n"); + + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + + ASSERT (Core == 0); + + if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + Locate.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE; + if (HeapLocateBuffer (&Locate, StdHeader) == AGESA_SUCCESS) { + LibAmdPciWrite (AccessWidth32, PciAddress, Locate.BufferPtr, StdHeader); + } else { + ASSERT (FALSE); + } + } + + // Launch one core per node. + TaskPtr.FuncAddress.PfApTask = F15TnPmNbAfterResetOnCore; + TaskPtr.DataTransfer.DataSizeInDwords = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { + if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { + if (TaskedCore != 0) { + ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); + } + } + } + ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h Trinity core 0 entry point for performing the necessary Nb P-state VID adjustment + * after a cold reset has occurred. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParamsPtr Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnNbPstateVidAdjustAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + BOOLEAN NeitherHiNorLo; + NB_PSTATE_REGISTER NbPsReg; + UINT32 NbPsVid; + UINT32 i; + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + NB_PSTATE_CTRL_REGISTER NbPsCtrlSave; + NB_PSTATE_STS_REGISTER NbPsSts; + CLK_PWR_TIMING_CTRL_5_REGISTER ClkPwrTimgCtrl5; + D0F0xBC_x1F400_STRUCT D0F0xBC_x1F400; + + // Check if D18F5x188[NbOffsetTrim] has been programmed to 01b (-25mV) + PciAddress.AddressValue = CPTC5_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); + if (ClkPwrTimgCtrl5.NbOffsetTrim == 1) { + return; + } + + // Add 25mV (-4 VID steps) to all VddNb VIDs. + PciAddress.AddressValue = NB_PSTATE_0_PCI_ADDR; + + for (i = 0; i < NM_NB_PS_REG; i++) { + PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsReg, StdHeader); + if (NbPsReg.NbPstateEn == 1) { + NbPsVid = GetF15TnNbVid (&NbPsReg); + NbPsVid -= 4; + SetF15TnNbVid (&NbPsReg, &NbPsVid); + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsReg, StdHeader); + } + } + + // Check if D18F5x174[CurNbPstate] equals NbPstateHi or NbPstateLo + PciAddress.Address.Register = NB_PSTATE_STATUS; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); + PciAddress.Address.Register = NB_PSTATE_CTRL; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + // Save NB P-state control setting + NbPsCtrlSave = NbPsCtrl; + + // Force a NB P-state Transition. + NeitherHiNorLo = FALSE; + if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi) { + TransitionToNbLow (PciAddress, StdHeader); + } else if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) { + TransitionToNbHigh (PciAddress, StdHeader); + } else { + NeitherHiNorLo = TRUE; + } + + // Set OffsetTrim to -25mV: + // D18F5x188[NbOffsetTrim]=01b (-25mV) + // D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV) + PciAddress.Address.Register = CPTC5_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); + ClkPwrTimgCtrl5.NbOffsetTrim = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); + + GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1; + GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); + + // Unforce NB P-state back to CurNbPstate value upon entry. + if (NeitherHiNorLo || (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi)) { + TransitionToNbHigh (PciAddress, StdHeader); + } else { + // if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) + TransitionToNbLow (PciAddress, StdHeader); + } + + // Restore NB P-state control setting + PciAddress.Address.Register = NB_PSTATE_CTRL; + NbPsCtrl = NbPsCtrlSave; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); +} + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmNbAfterReset to perform MSR initialization on one + * core of each die in a family 15h socket. + * + * This function implements steps 1 - 15 on each core. + * + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmNbAfterResetOnCore ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NbPsCtrlOnEntry; + UINT32 NbPsCtrlOnExit; + UINT64 LocalMsrRegister; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterResetOnCore\n"); + + // 1. Temp1 = D18F5x170[SwNbPstateLoDis]. + // 2. Temp2 = D18F5x170[NbPstateDisOnP0]. + // 3. Temp3 = D18F5x170[NbPstateThreshold]. + // 4. Temp4 = D18F5x170[NbPstateGnbSlowDis]. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader); + + // Check if NB P-states were disabled, and if so, prevent any changes from occurring. + if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) { + // 5. If MSRC001_0070[NbPstate] = 1, go to step 11 + LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); + if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) { + // 6. Write 1 to D18F5x170[NbPstateGnbSlowDis]. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + + // 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + TransitionToNbLow (PciAddress, StdHeader); + + // 9. Set D18F5x170[SwNbPstateLoDis] = 1. + // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + // Go to step 15. + TransitionToNbHigh (PciAddress, StdHeader); + } else { + // 11. Set D18F5x170[SwNbPstateLoDis] = 1. + // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + TransitionToNbHigh (PciAddress, StdHeader); + + // 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + // 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + TransitionToNbLow (PciAddress, StdHeader); + } + + // 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP- + // stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4. + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold; + ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); + } +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmNbAfterResetOnCore to transition to the low NB P-state. + * + * This function implements steps 7, 8, 13, and 14 as needed. + * + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +TransitionToNbLow ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbLow\n"); + + // 7/13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPsCtrl.SwNbPstateLoDis = 0; + NbPsCtrl.NbPstateDisOnP0 = 0; + NbPsCtrl.NbPstateThreshold = 0; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // 8/14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. + WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmNbAfterResetOnCore to transition to the high NB P-state. + * + * This function implements steps 9, 10, 11, and 12 as needed. + * + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +TransitionToNbHigh ( + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + + IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbHigh\n"); + + // 9/10. Set D18F5x170[SwNbPstateLoDis] = 1. + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPsCtrl.SwNbPstateLoDis = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + + // 11/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, + // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. + WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Support routine for F15TnPmAfterResetCore to wait for NB FID and DID to + * match a specific P-state. + * + * This function implements steps 8, 10, 12, and 14 as needed. + * + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] PstateIndex P-state settings to match. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +WaitForNbTransitionToComplete ( + IN PCI_ADDR PciAddress, + IN UINT32 PstateIndex, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + NB_PSTATE_REGISTER TargetNbPs; + NB_PSTATE_STS_REGISTER NbPsSts; + + IDS_HDT_CONSOLE (CPU_TRACE, " WaitForNbTransitionToComplete\n"); + + PciAddress.Address.Function = FUNC_5; + PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2); + LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader); + PciAddress.Address.Register = NB_PSTATE_STATUS; + do { + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); + } while ((NbPsSts.CurNbPstate != PstateIndex || + (NbPsSts.CurNbFid != TargetNbPs.NbFid)) || + (NbPsSts.CurNbDid != TargetNbPs.NbDid)); +} diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h new file mode 100644 index 0000000000..8fe1fdfb8e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnNbAfterReset.h @@ -0,0 +1,112 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity after warm reset sequence for NB P-states + * + * Contains code that provide power management functionality + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_NB_AFTER_RESET_H_ +#define _CPU_F15_TN_NB_AFTER_RESET_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmNbAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +F15TnNbPstateVidAdjustAfterReset ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_TN_NB_AFTER_RESET_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c new file mode 100644 index 0000000000..8d050b078e --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.c @@ -0,0 +1,486 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Tn P-State power check + * + * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as + * described in the BKDG. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuRegisters.h" +#include "cpuApicUtilities.h" +#include "cpuFamilyTranslation.h" +#include "cpuF15PowerCheck.h" +#include "cpuF15TnPowerCheck.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPOWERCHECK_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnPmPwrCheckCore ( + IN VOID *ErrorData, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +F15TnPmPwrChkCopyPstate ( + IN UINT8 Dest, + IN UINT8 Src, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; +/*---------------------------------------------------------------------------------------*/ +/** + * Family 15h core 0 entry point for performing the family 15h Processor- + * Systemboard Power Delivery Check. + * + * The steps are as follows: + * 1. Starting with P0, loop through all P-states until a passing state is + * found. A passing state is one in which the current required by the + * CPU is less than the maximum amount of current that the system can + * provide to the CPU. If P0 is under the limit, no further action is + * necessary. + * 2. If at least one P-State is under the limit & at least one P-State is + * over the limit, the BIOS must: + * a. If the processor's current P-State is disabled by the power check, + * then the BIOS must request a transition to an enabled P-state + * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] + * to reflect the new value. + * b. Copy the contents of the enabled P-state MSRs to the highest + * performance P-state locations. + * c. Request a P-state transition to the P-state MSR containing the + * COF/VID values currently applied. + * d. If a subset of boosted P-states are disabled, then copy the contents + * of the highest performance boosted P-state still enabled to the + * boosted P-states that have been disabled. + * e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] + * to zero. + * f. Adjust the following P-state parameters affected by the P-state + * MSR copy by subtracting the number of P-states that are disabled + * by the power check. + * 1. F3x64[HtcPstateLimit] + * 2. F3x68[SwPstateLimit] + * 3. F3xDC[PstateMaxVal] + * 3. If all P-States are over the limit, the BIOS must: + * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then + * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for + * MSRC001_0063[CurPstate] to reflect the new value. + * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state + * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR. + * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 + * [CurPstate] to reflect the new value. + * c. Adjust the following P-state parameters to zero: + * 1. F3x64[HtcPstateLimit] + * 2. F3x68[SwPstateLimit] + * 3. F3xDC[PstateMaxVal] + * d. Program D18F4x15C[BoostSrc] to zero. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] CpuEarlyParams Service parameters + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +F15TnPmPwrCheck ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 DisPsNum; + UINT8 PsMaxVal; + UINT8 Pstate; + UINT32 ProcIddMax; + UINT32 LocalPciRegister; + UINT32 Socket; + UINT32 Module; + UINT32 Core; + UINT32 AndMask; + UINT32 OrMask; + UINT32 PstateLimit; + PCI_ADDR PciAddress; + UINT64 LocalMsrRegister; + AP_TASK TaskPtr; + AGESA_STATUS IgnoredSts; + PWRCHK_ERROR_DATA ErrorData; + UINT32 NumModules; + UINT32 HighCore; + UINT32 LowCore; + UINT32 ModuleIndex; + NB_CAPS_REGISTER NbCaps; + HTC_REGISTER HtcReg; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + + // update PstateMaxVal if warranted by HtcPstateLimit + PciAddress.AddressValue = NB_CAPS_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // D18F3xE8 + if (NbCaps.HtcCapable == 1) { + PciAddress.AddressValue = (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)); + LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64 + if (HtcReg.HtcTmpLmt != 0) { + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) { + ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit; + LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC + } + } + } + + // get the socket number + IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); + ErrorData.SocketNumber = (UINT8) Socket; + + ASSERT (Core == 0); + + // get the Max P-state value + for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { + LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); + if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { + break; + } + } + + ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); + + // Starting with P0, loop through all P-states until a passing state is + // found. A passing state is one in which the current required by the + // CPU is less than the maximum amount of current that the system can + // provide to the CPU. If P0 is under the limit, no further action is + // necessary. + DisPsNum = 0; + for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { + if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { + if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { + // Add to event log the Pstate that exceeded the current limit + PutEventLog (AGESA_WARNING, + CPU_EVENT_PM_PSTATE_OVERCURRENT, + Socket, Pstate, 0, 0, StdHeader); + DisPsNum++; + } else { + break; + } + } + } + + ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); + + if (ErrorData.AllowablePstateNumber == 0) { + PutEventLog (AGESA_FATAL, + CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, + Socket, 0, 0, 0, StdHeader); + } + + if (DisPsNum != 0) { + GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); + PciAddress.Address.Function = FUNC_4; + PciAddress.Address.Register = CPB_CTRL_REG; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + + if (DisPsNum >= ErrorData.NumberOfBoostStates) { + // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero. + AndMask = 0xFFFFFFFF; + ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0; + OrMask = 0x00000000; + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C + + ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates; + } else { + ErrorData.NumberOfSwPstatesDisabled = 0; + } + + NumModules = GetPlatformNumberOfModules (); + + // Only execute this loop if this is an MCM. + if (NumModules > 1) { + + // Since the P-State MSRs are shared across a + // node, we only need to set one core in the node for the modified number of supported p-states + // to be reported across all of the cores in the module. + TaskPtr.FuncAddress.PfApTaskI = F15TnPmPwrCheckCore; + TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); + TaskPtr.DataTransfer.DataPtr = &ErrorData; + TaskPtr.DataTransfer.DataTransferFlags = 0; + TaskPtr.ExeFlags = WAIT_FOR_CORE; + + for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) { + // Execute the P-State reduction code on the module's primary core only. + // Skip this code for the BSC's module. + if (ModuleIndex != Module) { + if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) { + ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader); + } + } + } + } + + // Path for SCM and the BSC + F15TnPmPwrCheckCore (&ErrorData, StdHeader); + + // Final Step + // F3x64[HtPstatelimit] -= disPsNum + // F3x68[SwPstateLimit] -= disPsNum + // F3xDC[PstateMaxVal] -= disPsNum + + PciAddress.Address.Function = FUNC_3; + PciAddress.Address.Register = HTC_REG; + AndMask = 0xFFFFFFFF; + ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 + PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64 + + PciAddress.Address.Register = SW_PS_LIMIT_REG; + AndMask = 0xFFFFFFFF; + ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 + PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68 + + PciAddress.Address.Register = CPTC2_REG; + AndMask = 0xFFFFFFFF; + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; + OrMask = 0x00000000; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC + PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; + if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { + PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; + ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; + } + OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Core-level error handler called if any p-states were determined to be out + * of range for the mother board. + * + * This function implements steps 2a-c and 3a-c on each core. + * + * @param[in] ErrorData Details about the error condition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmPwrCheckCore ( + IN VOID *ErrorData, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 HwPsMaxVal; + UINT8 SwPsMaxVal; + UINT8 HwDisPsNum; + UINT8 CurrentSwPs; + UINT8 PsDisableCount; + UINT64 LocalMsrRegister; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { + // P-state MSRs are shared, so only 1 core per compute unit needs to perform this + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); + HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - + ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); + + LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); + CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); + SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal); + PsDisableCount = 0; + + if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { + // All P-States are over the limit. + + // Step 1 + // Transition to Pstate Max if not there already + if (CurrentSwPs != SwPsMaxVal) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, SwPsMaxVal, (BOOLEAN) TRUE, StdHeader); + } + + // Step 2 + // If Pstate Max is not P0, copy Pstate max contents to P0 and switch + // to P0. + if (SwPsMaxVal != 0) { + F15TnPmPwrChkCopyPstate (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates, HwPsMaxVal, StdHeader); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); + } + + // Disable all SW P-states except P0 + PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1; + } else { + // At least one P-State is under the limit & at least one P-State is + // over the limit. + if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) { + // A subset of boosted P-states are disabled. Copy the contents of the + // highest performance boosted P-state still enabled to the boosted + // P-states that have been disabled. + for (i = 0; i < HwDisPsNum; i++) { + F15TnPmPwrChkCopyPstate (i, HwDisPsNum, StdHeader); + } + } else if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) { + // Move remaining P-state register(s) up + // Step 1 + // Transition to a valid Pstate if current Pstate has been disabled + if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) { + FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader); + CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; + } + + // Step 2 + // Move enabled Pstates up and disable the remainder + for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) { + F15TnPmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader); + } + + // Step 3 + // Transition to current COF/VID at shifted location + CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled); + FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSwPs, (BOOLEAN) TRUE, StdHeader); + + // Disable the appropriate number of P-states + PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; + } + } + // Disable the appropriate P-states if any, starting from HW Pmin + for (i = 0; i < PsDisableCount; i++) { + FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader); + } + } +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Copies the contents of one P-State MSR to another. + * + * @param[in] Dest Destination p-state number + * @param[in] Src Source p-state number + * @param[in] StdHeader Config handle for library and services + * + */ +VOID +STATIC +F15TnPmPwrChkCopyPstate ( + IN UINT8 Dest, + IN UINT8 Src, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 LocalMsrRegister; + + LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); + LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); +} + diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h new file mode 100644 index 0000000000..a9d940cd61 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerCheck.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 TN Power related functions and structures + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_POWER_CHECK_H_ +#define _CPU_F15_TN_POWER_CHECK_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ +VOID +F15TnPmPwrCheck ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif // _CPU_F15_TN_POWER_CHECK_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h new file mode 100644 index 0000000000..f192c19b03 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPowerMgmt.h @@ -0,0 +1,609 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Power Management related registers defination + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63661 $ @e \$Date: 2012-01-03 01:02:47 -0600 (Tue, 03 Jan 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +#ifndef _CPU_F15_TN_POWERMGMT_H_ +#define _CPU_F15_TN_POWERMGMT_H_ + +/* + * Family 15h Trinity CPU Power Management MSR definitions + * + */ + + +/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */ +#define MSR_INTPEND 0xC0010055ul + +/// Interrupt Pending and CMP-Halt MSR Register +typedef struct { + UINT64 IoMsgAddr:16; ///< IO message address + UINT64 Intpend1 :8; + UINT64 Intpend2 :1; + UINT64 Intpend3 :1; + UINT64 Intpend4 :1; + UINT64 :37; ///< Reserved +} INTPEND_MSR; + +/* P-state Registers 0xC00100[6B:64] */ + +/// P-state MSR +typedef struct { + UINT64 CpuFid:6; ///< CpuFid + UINT64 CpuDid:3; ///< CpuDid + UINT64 CpuVid:8; ///< CpuVid + UINT64 :5; ///< Reserved + UINT64 NbPstate:1; ///< NbPstate + UINT64 :9; ///< Reserved + UINT64 IddValue:8; ///< IddValue + UINT64 IddDiv:2; ///< IddDiv + UINT64 :21; ///< Reserved + UINT64 PsEnable:1; ///< Pstate Enable +} PSTATE_MSR; + +#define GetF15TnCpuVid(PstateMsr) (((PSTATE_MSR *) PstateMsr)->CpuVid) + + +/* VID operation related macros */ +#define ConvertVidInuV(Vid) (1550000 - (6250 * Vid)) ///< Convert VID in uV. + +/* COFVID Control Register 0xC0010070 */ +#define MSR_COFVID_CTL 0xC0010070ul + +/// COFVID Control MSR Register +typedef struct { + UINT64 CpuFid:6; ///< CpuFid + UINT64 CpuDid:3; ///< CpuDid + UINT64 CpuVid_6_0:7; ///< CpuVid[6:0] + UINT64 PstateId:3; ///< Pstate ID + UINT64 :1; ///< Reserved + UINT64 CpuVid_7:1; ///< CpuVid[7] + UINT64 :1; ///< Reserved + UINT64 NbPstate:1; ///< Northbridge P-state + UINT64 :1; ///< Reserved + UINT64 NbVid:8; ///< NbVid + UINT64 :32; ///< Reserved +} COFVID_CTRL_MSR; + +#define COFVID_CTRL_MSR_CurCpuVid_6_0_OFFSET 9 +#define COFVID_CTRL_MSR_CurCpuVid_6_0_WIDTH 7 +#define COFVID_CTRL_MSR_CurCpuVid_6_0_MASK 0xfe00 +#define COFVID_CTRL_MSR_CurCpuVid_7_OFFSET 20 +#define COFVID_CTRL_MSR_CurCpuVid_7_WIDTH 1 +#define COFVID_CTRL_MSR_CurCpuVid_7_MASK 0x100000ul + +/* SVI VID Encoding */ + +///< Union structure of VID in SVI1/SVI2 modes +typedef union { + UINT32 RawVid; ///< Raw VID value + struct { ///< SVI2 mode VID structure + UINT32 Vid_6_0:7; ///< Vid[6:0] of SVI2 mode + UINT32 Vid_7:1; ///< Vid[7] of SVI2 mode + } SVI2; + struct { ///< SVI1 mode VID structure + UINT32 Vid_LSB_Ignore:1; ///< Ignored LSB of 8bit VID encoding in SVI1 mode + UINT32 Vid_6_0:1; ///< Vid[6:0] of SVI mode + } SVI1; +} SVI_VID; + + +#define SetF15TnCpuVid(CofVidStsMsr, NewCpuVid) ( \ + ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_6_0) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_6_0; \ + ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_7) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_7; \ +) + + +/* COFVID Status Register 0xC0010071 */ +#define MSR_COFVID_STS 0xC0010071ul + +/// COFVID Status MSR Register +typedef struct { + UINT64 CurCpuFid:6; ///< Current CpuFid + UINT64 CurCpuDid:3; ///< Current CpuDid + UINT64 CurCpuVid_6_0:7; ///< Current CpuVid[6:0] + UINT64 CurPstate:3; ///< Current Pstate + UINT64 :1; ///< Reserved + UINT64 CurCpuVid_7:1; ///< Current CpuVid[7] + UINT64 :2; ///< Reserved + UINT64 NbPstateDis:1; ///< NbPstate Disable + UINT64 CurNbVid:8; ///< Current NbVid[7:0] <<<------- check where use it + UINT64 StartupPstate:3; ///< Startup Pstate + UINT64 :14; ///< Reserved + UINT64 MaxCpuCof:6; ///< MaxCpuCof + UINT64 :1; ///< Reserved + UINT64 CurPstateLimit:3; ///< Current Pstate Limit + UINT64 MaxNbCof:5; ///< MaxNbCof +} COFVID_STS_MSR; + +#define COFVID_STS_MSR_CurCpuVid_6_0_OFFSET 9 +#define COFVID_STS_MSR_CurCpuVid_6_0_WIDTH 7 +#define COFVID_STS_MSR_CurCpuVid_6_0_MASK 0xfe00 +#define COFVID_STS_MSR_CurCpuVid_7_OFFSET 20 +#define COFVID_STS_MSR_CurCpuVid_7_WIDTH 1 +#define COFVID_STS_MSR_CurCpuVid_7_MASK 0x100000ul + +#define GetF15TnCurCpuVid(CofVidStsMsr) ( \ + (((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_7 << COFVID_STS_MSR_CurCpuVid_6_0_WIDTH) \ + | ((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_6_0) + + +/* Floating Point Configuration Register 0xC0011028 */ +#define MSR_FP_CFG 0xC0011028ul + +/// Floating Point Configuration MSR Register +typedef struct { + UINT64 :16; ///< Reserved + UINT64 DiDtMode:1; ///< Di/Dt Mode + UINT64 :1; ///< Reserved + UINT64 DiDtCfg0:5; ///< Di/Dt Config 0 + UINT64 :2; ///< Reserved + UINT64 DiDtCfg2:2; ///< Di/Dt Config 2 + UINT64 DiDtCfg1:8; ///< Di/Dt Config 1 + UINT64 :6; ///< Reserved + UINT64 DiDtCfg5:1; ///< Di/Dt Config 5 + UINT64 DiDtCfg4:3; ///< Di/Dt Config 4 + UINT64 :19; ///< Reserved +} FP_CFG_MSR; + +/* Load-Store Configuration 2 0xC001102D */ + +/// Load-Store Configuration 2 MSR Register +typedef struct { + UINT64 :14; ///< Reserved + UINT64 ForceSmcCheckFlwStDis:1; ///< ForceSmcCheckFlwStDis + UINT64 :8; ///< Reserved + UINT64 DisScbThreshold:1; ///< DisScbThreshold + UINT64 :40; ///< Reserved +} LS_CFG2_MSR; + +/* + * Family 15h Trinity CPU Power Management PCI definitions + * + */ + + +/* DRAM Configuration High Register F2x[1,0]94 */ +#define DRAM_CFG_HI_REG0 0x94 +#define DRAM_CFG_HI_REG1 0x194 + +/// DRAM Configuration High PCI Register +typedef struct { + UINT32 MemClkFreq:5; ///< Memory clock frequency + UINT32 :2; ///< Reserved + UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid + UINT32 :2; ///< Reserved + UINT32 ZqcsInterval:2; ///< ZQ calibration short interval + UINT32 :2; ///< Reserved + UINT32 DisDramInterface:1; ///< Disable the DRAM interface + UINT32 PowerDownEn:1; ///< Power down mode enable + UINT32 PowerDownMode:1; ///< Power down mode + UINT32 :2; ///< Reserved + UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable + UINT32 SlowAccessMode:1; ///< Slow access mode + UINT32 FreqChgInProg:1; ///< Frequency change in progress + UINT32 BankSwizzleMode:1; ///< Bank swizzle mode + UINT32 ProcOdtDis:1; ///< Processor on-die termination disable + UINT32 DcqBypassMax:5; ///< DRAM controller queue bypass maximum + UINT32 :3; ///< Reserved +} DRAM_CFG_HI_REGISTER; + +/* DCT Configuration Select D18F1x10C */ +#define DCT_CFG_SEL_REG 0x10C +#define DCT_CFG_SEL_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_1, DCT_CFG_SEL_REG)) + +/// DCT Configuration Select +typedef struct { + UINT32 DctCfgSel:1; ///< DRAM controller configuration select + UINT32 :31; ///< Reserved +} DCT_CFG_SEL_REGISTER; + + +/* GMC to DCT Control 2 D18F2x408_dct[1:0] */ +#define GMC_TO_DCT_CTL_2_REG 0x408 +#define GMC_TO_DCT_CTL_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, GMC_TO_DCT_CTL_2_REG)) + +/// GMC to DCT Control 2 PCI Register +typedef struct { + UINT32 CpuElevPrioDis:1; ///< Cpu elevate priority disable + UINT32 :31; ///< Reserved +} GMC_TO_DCT_CTL_2_REGISTER; + + +/* Power Control Miscellaneous Register F3xA0 */ +#define PW_CTL_MISC_REG 0xA0 +#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG)) + +/// Power Control Miscellaneous PCI Register +typedef struct { + UINT32 PsiVid:7; ///< PSI_L VID threshold VID[6:0] + UINT32 PsiVidEn:1; ///< PSI_L VID enable + UINT32 PsiVid_7:1; ///< PSI_L VID threshold VID[7] + UINT32 :2; ///< Reserved + UINT32 PllLockTime:3; ///< PLL synchronization lock time + UINT32 Svi2HighFreqSel:1; ///< SVI2 high frequency select + UINT32 :1; ///< Reserved + UINT32 ConfigId:12; ///< Configuration ID + UINT32 :3; ///< Reserved + UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed +} POWER_CTRL_MISC_REGISTER; + + +/* Clock Power/Timing Control 0 Register F3xD4 */ +#define CPTC0_REG 0xD4 +#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG)) + +/// Clock Power Timing Control PCI Register +typedef struct { + UINT32 MaxSwPstateCpuCof:6; ///< Maximum software P-state core COF + UINT32 :2; ///< Reserved + UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select + UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control + UINT32 :1; ///< Reserved + UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt + UINT32 :1; ///< Reserved + UINT32 clkpwr0 :2; + UINT32 :2; ///< Reserved + UINT32 PowerStepDown:4; ///< Power Step Down + UINT32 PowerStepUp:4; ///< Power Step Up + UINT32 NbClkDiv:3; ///< NbClkDiv + UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll +} CLK_PWR_TIMING_CTRL_REGISTER; + + +/* Clock Power/Timing Control 1 Register F3xD8 */ +#define CPTC1_REG 0xD8 +#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG)) + +/// Clock Power Timing Control 1 PCI Register +typedef struct { + UINT32 :4; ///< Reserved + UINT32 VSRampSlamTime:3; ///< Voltage stabilization ramp time + UINT32 :25; ///< Reserved +} CLK_PWR_TIMING_CTRL1_REGISTER; + + +/* Northbridge Capabilities Register F3xE8 */ +#define NB_CAPS_REG 0xE8 +#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG)) + +/// Northbridge Capabilities PCI Register +typedef struct { + UINT32 :1; ///< Reserved + UINT32 DualNode:1; ///< Dual-node multi-processor capable + UINT32 EightNode:1; ///< Eight-node multi-processor capable + UINT32 Ecc:1; ///< ECC capable + UINT32 Chipkill:1; ///< Chipkill ECC capable + UINT32 :3; ///< Reserved + UINT32 MctCap:1; ///< Memory controller capable + UINT32 SvmCapable:1; ///< SVM capable + UINT32 HtcCapable:1; ///< HTC capable + UINT32 :3; ///< Reserved + UINT32 MultVidPlane:1; ///< Multiple VID plane capable + UINT32 :4; ///< Reserved + UINT32 x2Apic:1; ///< x2Apic capability + UINT32 :4; ///< Reserved + UINT32 MemPstateCap:1; ///< Memory P-state capable + UINT32 L3Capable:1; ///< L3 capable + UINT32 :6; ///< Reserved +} NB_CAPS_REGISTER; + + +/* Product Info Register F3x1FC */ +#define PRCT_INFO_REG 0x1FC +#define PRCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRCT_INFO_REG)) + +/// Product Information PCI Register +typedef struct { + UINT32 DiDtMode:1; ///< DiDtMode + UINT32 DiDtCfg0:5; ///< DiDtCfg0 + UINT32 DiDtCfg1:8; ///< DiDtCfg1 + UINT32 DiDtCfg2:2; ///< DiDtCfg2 + UINT32 :1; ///< Reserved + UINT32 DiDtCfg4:3; ///< DiDtCfg4 + UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit + UINT32 :1; ///< Reserved + UINT32 DiDtCfg5:1; ///< DiDtCfg5 + UINT32 ForceSmcCheckFlwStDis:1; ///< ForceSmcCheckFlwStDis + UINT32 SWDllCapTableEn:1; ///< SWDllCapTableEn + UINT32 DllProcessFreqCtlIndex2Rate50:4; ///< DllProcessFreqCtlIndex2Rate50 + UINT32 EnDcqChgPriToHigh:1; ///< EnDcqChgPriToHigh + UINT32 :2; ///< Reserved +} PRODUCT_INFO_REGISTER; + + +/* C-state Control 1 Register D18F4x118 */ +#define CSTATE_CTRL1_REG 0x118 +#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG)) + +/// C-state Control 1 Register +typedef struct { + UINT32 CpuPrbEnCstAct0:1; ///< Core direct probe enable + UINT32 CacheFlushEnCstAct0:1; ///< Cache flush enable + UINT32 CacheFlushTmrSelCstAct0:2; ///< Cache flush timer select + UINT32 :1; ///< Reserved + UINT32 ClkDivisorCstAct0:3; ///< Clock divisor + UINT32 PwrGateEnCstAct0:1; ///< Power gate enable + UINT32 PwrOffEnCstAct0:1; ///< C-state action field 3 + UINT32 NbPwrGate0:1; ///< NB power-gating 0 + UINT32 NbClkGate0:1; ///< NB clock-gating 0 + UINT32 SelfRefr0:1; ///< Self-refresh 0 + UINT32 SelfRefrEarly0:1; ///< Allow early self-refresh 0 + UINT32 :2; ///< Reserved + UINT32 CpuPrbEnCstAct1:1; ///< Core direct probe enable + UINT32 CacheFlushEnCstAct1:1; ///< Cache flush eable + UINT32 CacheFlushTmrSelCstAct1:2; ///< Cache flush timer select + UINT32 :1; ///< Reserved + UINT32 ClkDivisorCstAct1:3; ///< Clock divisor + UINT32 PwrGateEnCstAct1:1; ///< Power gate enable + UINT32 PwrOffEnCstAct1:1; ///< C-state action field 3 + UINT32 NbPwrGate1:1; ///< NB power-gating 1 + UINT32 NbClkGate1:1; ///< NB clock-gating 1 + UINT32 SelfRefr1:1; ///< Self-refresh 1 + UINT32 SelfRefrEarly1:1; ///< Allow early self-refresh 1 + UINT32 :2; ///< Reserved +} CSTATE_CTRL1_REGISTER; + + +/* C-state Control 2 Register D18F4x11C */ +#define CSTATE_CTRL2_REG 0x11C +#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG)) + +/// C-state Control 2 Register +typedef struct { + UINT32 CpuPrbEnCstAct2:1; ///< Core direct probe enable + UINT32 CacheFlushEnCstAct2:1; ///< Cache flush eable + UINT32 CacheFlushTmrSelCstAct2:2; ///< Cache flush timer select + UINT32 cstate0 :1; + UINT32 ClkDivisorCstAct2:3; ///< Clock divisor + UINT32 PwrGateEnCstAct2:1; ///< Power gate enable + UINT32 PwrOffEnCstAct2:1; ///< C-state action field 3 + UINT32 NbPwrGate2:1; ///< NB power-gating 2 + UINT32 NbClkGate2:1; ///< NB clock-gating 2 + UINT32 SelfRefr2:1; ///< Self-refresh 2 + UINT32 SelfRefrEarly2:1; ///< Allow early self-refresh 2 + UINT32 :18; ///< Reserved +} CSTATE_CTRL2_REGISTER; + + +/* Cstate Policy Control 1 Register D18F4x128 */ +#define CSTATE_POLICY_CTRL1_REG 0x128 +#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG)) + +/// Cstate Policy Control 1 Register +typedef struct { + UINT32 cstplyc0 :1; + UINT32 CoreCstatePolicy:1; ///< Specified processor arbitration of voltage and frequency + UINT32 HaltCstateIndex:3; ///< Specifies the IO-based C-state that is invoked by a HLT instruction + UINT32 CacheFlushTmr:7; ///< Cache flush timer + UINT32 :6; ///< Reserved + UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold + UINT32 :10; ///< Reserved + UINT32 CstateMsgDis:1; ///< C-state messaging disable +} CSTATE_POLICY_CTRL1_REGISTER; + + +/* Core Performance Boost Control Register D18F4x15C */ + +/// Core Performance Boost Control Register +typedef struct { + UINT32 BoostSrc:2; ///< Boost source + UINT32 NumBoostStates:3; ///< Number of boosted states + UINT32 :2; ///< Reserved + UINT32 ApmMasterEn:1; ///< APM master enable + UINT32 :23; ///< Reserved + UINT32 BoostLock:1; ///< +} CPB_CTRL_REGISTER; + + +/* Northbridge Capabilities 2 F5x84*/ +#define NB_CAPS_REG2 0x84 +#define NB_CAPS_REG2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CAPS_REG2)) + +/// Northbridge Capabilities 2 PCI Register +typedef struct { + UINT32 CmpCap:8; ///< CMP capable + UINT32 :4; ///< Reserved + UINT32 DctEn:2; ///< DCT enabled + UINT32 :2; ///< Reserved + UINT32 DdrMaxRate:5; ///< maximum DDR rate + UINT32 :3; ///< Reserved + UINT32 DdrMaxRateEnf:5; ///< enforced maximum DDR rate: + UINT32 :3; ///< Reserved +} NB_CAPS_2_REGISTER; + +/* Northbridge Configuration 4 F5x88*/ +#define NB_CFG_REG4 0x88 +#define NB_CFG_REG4_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CFG_REG4)) + +/// Northbridge Configuration 4 PCI Register +typedef struct { + UINT32 :2; ///< Reserved + UINT32 IntStpClkHaltExitEn:1; ///< IntStpClkHaltExitEn + UINT32 :11; ///< Reserved + UINT32 Bit14:1; ///< Reserved + UINT32 :3; ///< Reserved + UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit + UINT32 :13; ///< Reserved +} NB_CFG_4_REGISTER; + +/* Northbridge P-state [3:0] F5x1[6C:60] */ + +/// Northbridge P-state Register +typedef struct { + UINT32 NbPstateEn:1; ///< NB P-state enable + UINT32 NbFid:6; ///< NB frequency ID + UINT32 NbDid:1; ///< NB divisor ID + UINT32 :2; ///< Reserved + UINT32 NbVid_6_0:7; ///< NB VID[6:0] + UINT32 :1; ///< Reserved + UINT32 MemPstate:1; ///< Memory P-State + UINT32 :2; ///< Reserved + UINT32 NbVid_7:1; ///< NB VID[7] + UINT32 NbIddDiv:2; ///< northbridge current divisor + UINT32 NbIddValue:8; ///< northbridge current value +} NB_PSTATE_REGISTER; + +#define NB_PSTATE_REGISTER_NbVid_6_0_OFFSET 10 +#define NB_PSTATE_REGISTER_NbVid_6_0_WIDTH 7 +#define NB_PSTATE_REGISTER_NbVid_6_0_MASK 0x0001FC00ul +#define NB_PSTATE_REGISTER_NbVid_7_OFFSET 21 +#define NB_PSTATE_REGISTER_NbVid_7_WIDTH 1 +#define NB_PSTATE_REGISTER_NbVid_7_MASK 0x00200000ul + +#define GetF15TnNbVid(NbPstateRegister) ( \ + (((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 << NB_PSTATE_REGISTER_NbVid_6_0_WIDTH) \ + | ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0) + +#define SetF15TnNbVid(NbPstateRegister, NewNbVid) { \ + ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0 = ((SVI_VID *) NewNbVid)->SVI2.Vid_6_0; \ + ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 = ((SVI_VID *) NewNbVid)->SVI2.Vid_7; \ +} + +/* Northbridge P-state Status */ +#define NB_PSTATE_CTRL 0x170 +#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL)) + +/// Northbridge P-state Control Register +typedef struct { + UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value + UINT32 :1; ///< Reserved + UINT32 NbPstateLo:2; ///< NB P-state low + UINT32 :1; ///< Reserved + UINT32 NbPstateHi:2; ///< NB P-state high + UINT32 :1; ///< Reserved + UINT32 NbPstateThreshold:3; ///< NB P-state threshold + UINT32 :1; ///< Reserved + UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 + UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable + UINT32 :8; ///< Reserved + UINT32 NbPstateGnbSlowDis:1; ///< Disable NB P-state transition take GnbSlow into account. + UINT32 NbPstateLoRes:3; ///< NB P-state low residency timer + UINT32 NbPstateHiRes:3; ///< NB P-state high residency timer + UINT32 :1; ///< Reserved + UINT32 MemPstateDis:1; ///< Memory P-state disable +} NB_PSTATE_CTRL_REGISTER; + + +/* Northbridge P-state Status */ +#define NB_PSTATE_STATUS 0x174 +#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS)) + +/// Northbridge P-state Status Register +typedef struct { + UINT32 NbPstateDis:1; ///< Nb pstate disable + UINT32 StartupNbPstate:2; ///< startup northbridge Pstate number + UINT32 CurNbFid:6; ///< Current NB FID + UINT32 CurNbDid:1; ///< Current NB DID + UINT32 :2; ///< Reserved + UINT32 CurNbVid_6_0:7; ///< Current NB VID[6:0] + UINT32 CurNbPstate:2; ///< Current NB Pstate + UINT32 :2; ///< Reserved + UINT32 CurNbVid_7:1; ///< Current NB VID[7] + UINT32 CurMemPstate:1; ///< Current memory P-state + UINT32 :7; ///< Reserved +} NB_PSTATE_STS_REGISTER; + +#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_OFFSET 12 +#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH 7 +#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_MASK 0x0007F000ul +#define NB_PSTATE_STS_REGISTER_CurNbVid_7_OFFSET 23 +#define NB_PSTATE_STS_REGISTER_CurNbVid_7_WIDTH 1 +#define NB_PSTATE_STS_REGISTER_CurNbVid_7_MASK 0x00800000ul + +#define GetF15TnCurNbVid(NbPstateStsRegister) ( \ + (((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_7 << NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH) \ + | ((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_6_0) + +/* Miscellaneous Voltages */ +#define MISC_VOLTAGES 0x17C +#define MISC_VOLTAGES_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, MISC_VOLTAGES)) + +/// Miscellaneous Voltages Register +typedef struct { + UINT32 MaxVid:8; ///< Maximum Voltage + UINT32 :2; ///< Reserved + UINT32 MinVid:8; ///< Minimum Voltage + UINT32 :5; ///< Reserved + UINT32 NbPsi0Vid:8; ///< Northbridge PSI0_L VID threshold + UINT32 NbPsi0VidEn:1; ///< Northbridge PSI0_L VID enable +} MISC_VOLTAGE_REGISTER; + + +/* Clock Power/Timing Control 5 Register F5x188 */ +#define CPTC5_REG 0x188 +#define CPTC5_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, CPTC5_REG)) + +/// Clock Power Timing Control 5 Register +typedef struct { + UINT32 NbOffsetTrim:2; ///< Northbridge offset trim + UINT32 NbLoadLineTrim:3; ///< Northbridge load line trim + UINT32 NbPsi1:1; ///< Northbridge PSI1_L + UINT32 :26; ///< Reserved +} CLK_PWR_TIMING_CTRL_5_REGISTER; + +#endif /* _CPU_F15_TN_POWERMGMT_H_ */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c new file mode 100644 index 0000000000..d808c50d6b --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPsi.c @@ -0,0 +1,308 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 TN PSI Initialization + * + * Enables Power Status Indicator (PSI) feature + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 65284 $ @e \$Date: 2012-02-12 23:29:39 -0600 (Sun, 12 Feb 2012) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "cpuRegisters.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "cpuFeatures.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "CommonReturns.h" +#include "cpuPsi.h" +#include "OptionMultiSocket.h" +#include "Filecode.h" +CODE_GROUP (G2_PEI) +RDATA_GROUP (G2_PEI) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSI_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +VOID +STATIC +F15TnPmVrmLowPowerModeEnable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; + +/*---------------------------------------------------------------------------------------*/ +/** + * Entry point for enabling Power Status Indicator + * + * This function must be run after all P-State routines have been executed + * + * @param[in] PsiServices The current CPU's family services. + * @param[in] EntryPoint Timepoint designator. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config handle for library and services. + * + * @retval AGESA_SUCCESS Always succeeds. + * + */ +AGESA_STATUS +STATIC +F15TnInitializePsi ( + IN PSI_FAMILY_SERVICES *PsiServices, + IN UINT64 EntryPoint, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); + OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); + // Configure PsiVid + F15TnPmVrmLowPowerModeEnable (FamilySpecificServices, PlatformConfig, PciAddress, StdHeader); + } + + return AGESA_SUCCESS; +} + + +/*---------------------------------------------------------------------------------------*/ +/** + * Sets up PSI_L operation. + * + * This function implements the LowPowerThreshold parameter. + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] PciAddress Segment, bus, device number of the node to transition. + * @param[in] StdHeader Config handle for library and services. + * + */ +VOID +STATIC +F15TnPmVrmLowPowerModeEnable ( + IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN PCI_ADDR PciAddress, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PSTATE_MSR PstateMsr; + CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; + POWER_CTRL_MISC_REGISTER PwrCtrlMisc; + UINT32 CoreVrmLowPowerThreshold; + UINT32 Pstate; + UINT32 HwPstateMaxVal; + UINT32 PstateCurrent; + UINT32 NextPstateCurrent; + UINT32 PreviousVid; + UINT32 CurrentVid; + + NB_PSTATE_REGISTER NbPstateReg; + NB_PSTATE_CTRL_REGISTER NbPsCtrl; + MISC_VOLTAGE_REGISTER MiscVoltageReg; + UINT32 NbVrmLowPowerThreshold; + UINT32 NbPstate; + UINT32 NbPstateMaxVal; + UINT32 NbPstateCurrent; + UINT32 NextNbPstateCurrent; + UINT32 PreviousNbVid; + UINT32 CurrentNbVid; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmVrmLowPowerModeEnable\n"); + + if (PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold != 0) { + // Set up PSI0_L for VDD + CoreVrmLowPowerThreshold = PlatformConfig->VrmProperties[CoreVrm].LowPowerThreshold; + IDS_HDT_CONSOLE (CPU_TRACE, " Core VRM - LowPowerThreshold: %d\n", CoreVrmLowPowerThreshold); + PreviousVid = 0xFF; + CurrentVid = 0xFF; + + PciAddress.AddressValue = CPTC2_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); + HwPstateMaxVal = ClkPwrTimingCtrl2.PstateMaxVal; + ASSERT (HwPstateMaxVal < NM_PS_REG); + + IDS_HDT_CONSOLE (CPU_TRACE, " HwPstateMaxVal %d\n", HwPstateMaxVal); + // Check P-state from P0 to HwPstateMaxVal + for (Pstate = 0; Pstate <= HwPstateMaxVal; Pstate++) { + FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader); + + LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), (UINT64 *) &PstateMsr, StdHeader); + CurrentVid = (UINT32) PstateMsr.CpuVid; + + if (Pstate == HwPstateMaxVal) { + NextPstateCurrent = 0; + } else { + // Check P-state from P1 to HwPstateMaxVal + FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader); + } + + if ((PstateCurrent <= CoreVrmLowPowerThreshold) && + (NextPstateCurrent <= CoreVrmLowPowerThreshold) && + (CurrentVid != PreviousVid)) { + // Program PsiVid and PsiVidEn if PSI state is found and stop searching. + PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader); + PwrCtrlMisc.PsiVid = CurrentVid; + PwrCtrlMisc.PsiVidEn = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &PwrCtrlMisc, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " PsiVid is enabled at P-state %d. PsiVid: %d\n", Pstate, CurrentVid); + break; + } else { + PstateCurrent = NextPstateCurrent; + PreviousVid = CurrentVid; + } + } + } + + if (PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold != 0) { + // Set up NBPSI0_L for VDDNB + NbVrmLowPowerThreshold = PlatformConfig->VrmProperties[NbVrm].LowPowerThreshold; + IDS_HDT_CONSOLE (CPU_TRACE, " NB VRM - LowPowerThreshold: %d\n", NbVrmLowPowerThreshold); + PreviousNbVid = 0xFF; + CurrentNbVid = 0xFF; + + PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); + NbPstateMaxVal = NbPsCtrl.NbPstateMaxVal; + ASSERT (NbPstateMaxVal < NM_NB_PS_REG); + + IDS_HDT_CONSOLE (CPU_TRACE, " NbPstateMaxVal %d\n", NbPstateMaxVal); + for (NbPstate = 0; NbPstate <= NbPstateMaxVal; NbPstate++) { + // Check only valid NB P-state + if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) NbPstate, &NbPstateCurrent, StdHeader) != TRUE) { + continue; + } + + PciAddress.Address.Register = (NB_PSTATE_0 + (sizeof (NB_PSTATE_REGISTER) * NbPstate)); + LibAmdPciRead (AccessWidth32, PciAddress, &NbPstateReg, StdHeader); + CurrentNbVid = (UINT32) GetF15TnNbVid (&NbPstateReg); + + if (NbPstate == NbPstateMaxVal) { + NextNbPstateCurrent = 0; + } else { + // Check only valid NB P-state + if (FamilySpecificServices->GetNbIddMax (FamilySpecificServices, (UINT8) (NbPstate + 1), &NextNbPstateCurrent, StdHeader) != TRUE) { + continue; + } + } + + if ((NbPstateCurrent <= NbVrmLowPowerThreshold) && + (NextNbPstateCurrent <= NbVrmLowPowerThreshold) && + (CurrentNbVid != PreviousNbVid)) { + // Program NbPsi0Vid and NbPsi0VidEn if PSI state is found and stop searching. + PciAddress.AddressValue = MISC_VOLTAGES_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader); + MiscVoltageReg.NbPsi0Vid = CurrentNbVid; + MiscVoltageReg.NbPsi0VidEn = 1; + LibAmdPciWrite (AccessWidth32, PciAddress, &MiscVoltageReg, StdHeader); + IDS_HDT_CONSOLE (CPU_TRACE, " NbPsi0Vid is enabled at NB P-state %d. NbPsi0Vid: %d\n", NbPstate, CurrentNbVid); + break; + } else { + PreviousNbVid = CurrentNbVid; + } + } + } +} + + +CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport = +{ + 0, + (PF_PSI_IS_SUPPORTED) CommonReturnTrue, + F15TnInitializePsi +}; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c new file mode 100644 index 0000000000..7b6321e67a --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnPstate.c @@ -0,0 +1,766 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Family_15 Trinity Pstate feature support functions. + * + * Provides the functions necessary to initialize the Pstate feature. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU/Family/0x15/TN + * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ + * + */ +/* + ****************************************************************************** + * + * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * AMD is granting you permission to use this software (the Materials) + * pursuant to the terms and conditions of your Software License Agreement + * with AMD. This header does *NOT* give you permission to use the Materials + * or any rights under AMD's intellectual property. Your use of any portion + * of these Materials shall constitute your acceptance of those terms and + * conditions. If you do not agree to the terms and conditions of the Software + * License Agreement, please do not use any portion of these Materials. + * + * CONFIDENTIALITY: The Materials and all other information, identified as + * confidential and provided to you by AMD shall be kept confidential in + * accordance with the terms and conditions of the Software License Agreement. + * + * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION + * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED + * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF + * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, + * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS + * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, + * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER + * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE + * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, + * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. + * + * AMD does not assume any responsibility for any errors which may appear in + * the Materials or any other related information provided to you by AMD, or + * result from use of the Materials or any related information. + * + * You agree that you will not reverse engineer or decompile the Materials. + * + * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any + * further information, software, technical information, know-how, or show-how + * available to you. Additionally, AMD retains the right to modify the + * Materials at any time, without notice, and is not obligated to provide such + * modified Materials to you. + * + * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with + * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is + * subject to the restrictions as set forth in FAR 52.227-14 and + * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the + * Government constitutes acknowledgement of AMD's proprietary rights in them. + * + * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any + * direct product thereof will be exported directly or indirectly, into any + * country prohibited by the United States Export Administration Act and the + * regulations thereunder, without the required authorization from the U.S. + * government nor will be used for any purpose prohibited by the same. + ****************************************************************************** + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "amdlib.h" +#include "GeneralServices.h" +#include "cpuPstateTables.h" +#include "cpuRegisters.h" +#include "Table.h" +#include "cpuFamilyTranslation.h" +#include "cpuFamRegisters.h" +#include "cpuF15Utilities.h" +#include "F15TnUtilities.h" +#include "cpuF15PowerMgmt.h" +#include "cpuF15TnPowerMgmt.h" +#include "CommonReturns.h" +#include "Filecode.h" +CODE_GROUP (G3_DXE) +RDATA_GROUP (G3_DXE) + +#define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +VOID +STATIC +F15TnGetPowerStepValueInTime ( + IN OUT UINT32 *PowerStepPtr + ); + +VOID +STATIC +F15TnGetPllValueInTime ( + IN OUT UINT32 *PllLockTimePtr + ); + +AGESA_STATUS +STATIC +F15TnGetFrequencyXlatRegInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 PStateNumber, + IN UINT32 Frequency, + OUT UINT32 *CpuFidPtr, + OUT UINT32 *CpuDidPtr1, + OUT UINT32 *CpuDidPtr2, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateTransLatency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, + IN PCI_ADDR *PciAddress, + OUT UINT32 *TransitionLatency, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateFrequency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstatePower ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *PowerInMw, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateMaxState ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + OUT UINT32 *MaxPStateNumber, + OUT UINT8 *NumberOfBoostStates, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +F15TnGetPstateRegisterInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT32 PState, + OUT BOOLEAN *PStateEnabled, + IN OUT UINT32 *IddVal, + IN OUT UINT32 *IddDiv, + OUT UINT32 *SwPstateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ); + + + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to check if Pstate PSD is dependent. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data. + * @param[in] StdHeader Config Handle for library, services. + * + * @retval TRUE PSD is dependent. + * @retval FALSE PSD is independent. + * + */ +BOOLEAN +STATIC +F15TnIsPstatePsdDependent ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN OUT PLATFORM_CONFIGURATION *PlatformConfig, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + BOOLEAN PsdIsDependent; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnIsPstatePsdDependent\n"); + + // Family 15h Trinity defaults to dependent PSD; allow Platform Configuration to + // overwrite the default setting. + PsdIsDependent = TRUE; + if (PlatformConfig->ForcePstateIndependent == TRUE) { + PsdIsDependent = FALSE; + } + + IDS_HDT_CONSOLE (CPU_TRACE, " P-state PSD is dependent: %d\n", PsdIsDependent); + return PsdIsDependent; +} + +/** + * Family specific call to set core TscFreqSel. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] StdHeader Config Handle for library, services. + * + */ +VOID +STATIC +F15TnSetTscFreqSel ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnSetTscFreqSel\n"); + + //TscFreqSel: TSC frequency select. Read-only. Reset: 1. 1=The TSC increments at the P0 frequency. + //This field uses software P-state numbering. + return; +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to get Pstate Transition Latency. + * + * Calculate TransitionLatency by power step value and pll value. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer + * @param[in] PciAddress Pci address + * @param[out] TransitionLatency The transition latency. + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstateTransLatency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN PSTATE_LEVELING *PStateLevelingBufferStructPtr, + IN PCI_ADDR *PciAddress, + OUT UINT32 *TransitionLatency, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 TempVar_b; + UINT32 TempVar_c; + UINT32 TempVar_d; + UINT32 TempVar8_a; + UINT32 TempVar8_b; + UINT32 Ignored; + UINT32 k; + UINT32 CpuFidSameFlag; + UINT8 PStateMaxValueOnCurrentCore; + UINT32 TransAndBusMastLatency; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateTransLatency\n"); + + CpuFidSameFlag = 1; + + F15TnGetFrequencyXlatRegInfo ( + PstateCpuServices, + 0, + PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq, + &TempVar_b, + &TempVar_c, + &Ignored, + StdHeader + ); + + TempVar_d = TempVar_b; + PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue; + + // + //Check if MSRC001_00[6B:64][CpuFid] is the same value for all P-states where + //MSRC001_00[6B:64][PstateEn]=1 + // + for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) { + if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) { + F15TnGetFrequencyXlatRegInfo ( + PstateCpuServices, + (UINT8) k, + PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq, + &TempVar_b, + &TempVar_c, + &Ignored, + StdHeader + ); + } + + if (TempVar_d != TempVar_b) { + CpuFidSameFlag = 0; + break; + } + } + + PciAddress->Address.Register = 0xD4; + PciAddress->Address.Function = FUNC_3; + LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); + + // PowerStepDown - Bits 20:23 + TempVar8_a = (TempVar_d & 0x00F00000) >> 20; + + // PowerStepUp - Bits 24:27 + TempVar8_b = (TempVar_d & 0x0F000000) >> 24; + + // Convert the raw numbers in TempVar8_a and TempVar8_b into time + F15TnGetPowerStepValueInTime (&TempVar8_a); + F15TnGetPowerStepValueInTime (&TempVar8_b); + + // + //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us + // + TransAndBusMastLatency = + (12 * (TempVar8_a + TempVar8_b) + 999) / 1000; + + if (CpuFidSameFlag == 0) { + // + //+ F3xA0[PllLockTime] + // + PciAddress->Address.Register = 0xA0; + LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader); + + TempVar8_a = (0x00003800 & TempVar_d) >> 11; + F15TnGetPllValueInTime (&TempVar8_a); + TransAndBusMastLatency += TempVar8_a; + } + + *TransitionLatency = TransAndBusMastLatency; + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to calculates the frequency in megahertz of the desired P-state. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] StateNumber The P-State to analyze. + * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always Succeeds. + */ +AGESA_STATUS +F15TnGetPstateFrequency ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *FrequencyInMHz, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 TempValue; + UINT32 CpuDid; + UINT32 CpuFid; + UINT64 LocalMsrRegister; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateFrequency - P%d\n", StateNumber); + + ASSERT (StateNumber < NM_PS_REG); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); + ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); + CpuDid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuDid); + CpuFid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuFid); + + switch (CpuDid) { + case 0: + TempValue = 1; + break; + case 1: + TempValue = 2; + break; + case 2: + TempValue = 4; + break; + case 3: + TempValue = 8; + break; + case 4: + TempValue = 16; + break; + default: + // CpuDid is set to an undefined value. This is due to either a misfused CPU, or + // an invalid P-state MSR write. + ASSERT (FALSE); + TempValue = 1; + break; + } + *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue); + IDS_HDT_CONSOLE (CPU_TRACE, " FrequencyInMHz=%d, CpuFid=%d, CpuDid=%d\n", *FrequencyInMHz, CpuFid, CpuDid); + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to calculates the power in milliWatts of the desired P-state. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] StateNumber Which P-state to analyze + * @param[out] PowerInMw The Power in milliWatts of that P-State + * @param[in] StdHeader Header for library and services + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstatePower ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 StateNumber, + OUT UINT32 *PowerInMw, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 CpuVid; + UINT32 IddValue; + UINT32 IddDiv; + UINT32 V_x100000; + UINT32 Power; + UINT64 LocalMsrRegister; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstatePower - P%d\n", StateNumber); + + ASSERT (StateNumber < NM_PS_REG); + LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &LocalMsrRegister, StdHeader); + ASSERT (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1); + CpuVid = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->CpuVid); + IddValue = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddValue); + IddDiv = (UINT32) (((PSTATE_MSR *) &LocalMsrRegister)->IddDiv); + + if (CpuVid >= 0xF8) { + V_x100000 = 0; + } else { + V_x100000 = 155000L - (625L * CpuVid); + } + + Power = V_x100000 * IddValue; + + switch (IddDiv) { + case 0: + *PowerInMw = Power / 100L; + break; + case 1: + *PowerInMw = Power / 1000L; + break; + case 2: + *PowerInMw = Power / 10000L; + break; + default: + // IddDiv is set to an undefined value. This is due to either a misfused CPU, or + // an invalid P-state MSR write. + ASSERT (FALSE); + *PowerInMw = 0; + break; + } + IDS_HDT_CONSOLE (CPU_TRACE, " PowerInMw=%d, CpuVid=%d, IddValue=%d, IddDiv=%d\n", *PowerInMw, CpuVid, IddValue, IddDiv); + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to get CPU pstate max state. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[out] MaxPStateNumber The max hw pstate value on the current socket. + * @param[out] NumberOfBoostStates The number of boosted P-states on the current socket. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstateMaxState ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + OUT UINT32 *MaxPStateNumber, + OUT UINT8 *NumberOfBoostStates, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 NumBoostStates; + UINT64 MsrValue; + UINT32 LocalPciRegister; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateMaxState\n"); + + LocalPciRegister = 0; + + // For F15 Trinity CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates]. + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + + NumBoostStates = ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + *NumberOfBoostStates = (UINT8) NumBoostStates; + + // + // Read PstateMaxVal [6:4] from MSR C001_0061 + // So, we will know the max pstate state in this socket. + // + LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader); + *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + NumBoostStates; + IDS_HDT_CONSOLE (CPU_TRACE, " MaxPStateNumber=%d, NumBoostStates=%d\n", *MaxPStateNumber, NumBoostStates); + + return (AGESA_SUCCESS); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Family specific call to get CPU pstate register information. + * + * @param[in] PstateCpuServices Pstate CPU services. + * @param[in] PState Input Pstate number for query. + * @param[out] PStateEnabled Boolean flag return pstate enable. + * @param[in,out] IddVal Pstate current value. + * @param[in,out] IddDiv Pstate current divisor. + * @param[out] SwPstateNumber Software P-state number. + * @param[in] StdHeader Handle of Header for calling lib functions and services. + * + * @retval AGESA_SUCCESS Always succeeds. + */ +AGESA_STATUS +F15TnGetPstateRegisterInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT32 PState, + OUT BOOLEAN *PStateEnabled, + IN OUT UINT32 *IddVal, + IN OUT UINT32 *IddDiv, + OUT UINT32 *SwPstateNumber, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 LocalPciRegister; + UINT64 LocalMsrRegister; + PCI_ADDR PciAddress; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPstateRegisterInfo - P%d\n", PState); + + ASSERT (PState < NM_PS_REG); + + // For F15 Trinity CPU, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates]. + PciAddress.AddressValue = CPB_CTRL_PCI_ADDR; + LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C + + // Read PSTATE MSRs + LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrRegister, StdHeader); + + *SwPstateNumber = PState; + + if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { + // PState enable = bit 63 + *PStateEnabled = TRUE; + // + // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE. + // + if (PState < ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates) { + *PStateEnabled = FALSE; + } else { + *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; + } + IDS_HDT_CONSOLE (CPU_TRACE, " Pstate %d is enabled. SwPstateNumber=%d\n", PState, *SwPstateNumber); + } else { + *PStateEnabled = FALSE; + } + + // Bits 39:32 (high 32 bits [7:0]) + *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddValue; + // Bits 41:40 (high 32 bits [9:8]) + *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrRegister)->IddDiv; + + IDS_HDT_CONSOLE (CPU_TRACE, " IddVal=%d, IddDiv=%d\n", *IddVal, *IddDiv); + return (AGESA_SUCCESS); +} + + +CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices = +{ + 0, + (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue, + F15TnIsPstatePsdDependent, + F15TnSetTscFreqSel, + F15TnGetPstateTransLatency, + F15TnGetPstateFrequency, + (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess, + F15TnGetPstatePower, + F15TnGetPstateMaxState, + F15TnGetPstateRegisterInfo +}; + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + + +/** + *--------------------------------------------------------------------------------------- + * + * F15TnGetPowerStepValueInTime + * + * Description: + * Convert power step value in time + * + * Parameters: + * @param[out] *PowerStepPtr + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +STATIC +F15TnGetPowerStepValueInTime ( + IN OUT UINT32 *PowerStepPtr + ) +{ + UINT32 TempVar_a; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPowerStepValueInTime\n"); + + TempVar_a = *PowerStepPtr; + + if (TempVar_a < 0x4) { + *PowerStepPtr = 400 - (TempVar_a * 100); + } else if (TempVar_a < 0x9) { + *PowerStepPtr = 130 - (TempVar_a * 10); + } else { + *PowerStepPtr = 90 - (TempVar_a * 5); + } + IDS_HDT_CONSOLE (CPU_TRACE, " PowerStepPtr=%d\n", *PowerStepPtr); +} + +/** + *--------------------------------------------------------------------------------------- + * + * F15TnGetPllValueInTime + * + * Description: + * Convert PLL Value in time + * + * Parameters: + * @param[out] *PllLockTimePtr + * + * @retval VOID + * + *--------------------------------------------------------------------------------------- + **/ +VOID +STATIC +F15TnGetPllValueInTime ( + IN OUT UINT32 *PllLockTimePtr + ) +{ + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetPllValueInTime\n"); + + if (*PllLockTimePtr < 4) { + *PllLockTimePtr = *PllLockTimePtr + 1; + } else if (*PllLockTimePtr == 4) { + *PllLockTimePtr = 8; + } else if (*PllLockTimePtr == 5) { + *PllLockTimePtr = 16; + } else + *PllLockTimePtr = 0; + IDS_HDT_CONSOLE (CPU_TRACE, " PllLockTimePtr=%d\n", *PllLockTimePtr); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * This function will return the CpuFid and CpuDid in MHz, using the formula + * described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0 + * + * @param[in] PstateCpuServices The current Family Specific Services. + * @param[in] PStateNumber P-state number to check. + * @param[in] Frequency Leveled target frequency for PStateNumber. + * @param[out] *CpuFidPtr New leveled FID. + * @param[out] *CpuDidPtr1 New leveled DID info 1. + * @param[out] *CpuDidPtr2 New leveled DID info 2. + * @param[in] *StdHeader Header for library and services. + * + * @retval AGESA_WARNING This P-State does not need to be modified. + * @retval AGESA_SUCCESS This P-State must be modified to be level. + */ +AGESA_STATUS +STATIC +F15TnGetFrequencyXlatRegInfo ( + IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices, + IN UINT8 PStateNumber, + IN UINT32 Frequency, + OUT UINT32 *CpuFidPtr, + OUT UINT32 *CpuDidPtr1, + OUT UINT32 *CpuDidPtr2, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 i; + UINT32 j; + AGESA_STATUS Status; + UINT32 FrequencyInMHz; + + IDS_HDT_CONSOLE (CPU_TRACE, " F15TnGetFrequencyXlatRegInfo - PstateNumber=%d, Frequency=%d\n", PStateNumber, Frequency); + + FrequencyInMHz = 0; + *CpuDidPtr2 = 0xFFFF; + + Status = AGESA_SUCCESS; + + PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader); + if (FrequencyInMHz == Frequency) { + Status |= AGESA_WARNING; + } + + // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid) + // In this for loop i = 2^CpuDid + + + for (i = 1; i < 17; (i += i)) { + for (j = 0; j < 64; j++) { + if (Frequency == ((100 * (j + 0x10)) / i )) { + *CpuFidPtr = j; + if (i == 1) { + *CpuDidPtr1 = 0; + } else if (i == 2) { + *CpuDidPtr1 = 1; + } else if (i == 4) { + *CpuDidPtr1 = 2; + } else if (i == 8) { + *CpuDidPtr1 = 3; + } else if (i == 16) { + *CpuDidPtr1 = 4; + } else { + *CpuFidPtr = 0xFFFF; + *CpuDidPtr1 = 0xFFFF; + } + IDS_HDT_CONSOLE (CPU_TRACE, " CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2); + // Success + return Status; + } + } + } + + // Error Condition + *CpuFidPtr = 0x00FF; + *CpuDidPtr1 = 0x00FF; + *CpuDidPtr2 = 0x00FF; + + IDS_HDT_CONSOLE (CPU_TRACE, " CpuFidPtr=%d, CpuDidPtr1=0x%x, CpuDidPtr2=0x%x\n", *CpuFidPtr, *CpuDidPtr1, *CpuDidPtr2); + return AGESA_ERROR; +} + |