AGESA f14/f15tn/f16kb: Clean up buildOpts.c files

Until now, the buildOpts.c files were primarily made out of copy-pasted
AGESA options, commented-out definitions and several useless comments;
that is, the materialization of technical debt in GCC-parsable form...

Until now.

It is assumed that the boards in the tree still boot. So, by comparing
their settings, we can extract saner defaults to place into AGESA. Many
of the settings were common across all boards of the same family, so we
promote those values to default settings. In some cases flipping a flag
was required, so the macros to alter that option had to be adapted as
well. Since those AGESA versions are expected to never receive updates,
it should not be a problem to change their files to suit our needs.

As a result, all but two buildOpts.c files now have less than 100 lines.
AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require
about 60 or 70 lines in those files. Hopefully, this will make porting
more mainboards using AGESA f14/f15tn/f16kb a substantially easier task.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>

1 files changed, 41 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
index 4a8237a210..5ea5fd1595 100644
--- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h
@@ -48,6 +48,47 @@
   #define  FCH_SUPPORT   FALSE
 #endif
 
+/* Define the default values for the FCH configuration settings */
+#define DFLT_SMBUS0_BASE_ADDRESS		0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS		0xB20
+/* The AGESA likes to enable 512 bytes region on this base for LPC bus */
+#define DFLT_SIO_PME_BASE_ADDRESS		0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS		0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS		0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS		0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS		0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS		0x820
+#define DFLT_SPI_BASE_ADDRESS			0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS	0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS			0xFED00000
+#define DFLT_SMI_CMD_PORT			0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS		0xFE00
+#define DFLT_GEC_BASE_ADDRESS			0xFED61000
+#define DFLT_AZALIA_SSID			0x780D1022
+#define DFLT_SMBUS_SSID				0x780B1022
+#define DFLT_IDE_SSID				0x780C1022
+#define DFLT_SATA_AHCI_SSID			0x78011022
+#define DFLT_SATA_IDE_SSID			0x78001022
+#define DFLT_SATA_RAID5_SSID			0x78031022
+#define DFLT_SATA_RAID_SSID			0x78021022
+#define DFLT_EHCI_SSID				0x78081022
+#define DFLT_OHCI_SSID				0x78071022
+#define DFLT_LPC_SSID				0x780E1022
+#define DFLT_SD_SSID				0x78061022
+#define DFLT_XHCI_SSID				0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB		FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP		TRUE
+
+#define DFLT_FCH_GPP_LINK_CONFIG		PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT		FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT		FALSE
+
+#define DFLT_FCH_GPP_PORT0_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG		FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG		FALSE
 
 /* ACPI block register offset definitions */
 #define PM1_STATUS_OFFSET              0x00