AGESA F15: AMD family15 AGESA code

AMD AGESA code to support Orochi platform family15 model 00-0fh processores,
AMD C32, G34, and AM3r2 Sockets are supported.

Change-Id: If79392c104ace25f7e01db794fa205f47746bcad
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/554
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 104 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h
new file mode 100644
index 0000000000..c4aae3e533
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h
@@ -0,0 +1,104 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * mmerrhdl.h
+ *
+ * main error handling
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: (Mem)
+ * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ **/
+/*****************************************************************************
+  *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  * ***************************************************************************
+  *
+ */
+
+#ifndef _MMERRHDL_H_
+#define _MMERRHDL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define EXCLUDE_ALL_DCT 0xFF
+#define EXCLUDE_ALL_CHIPSEL  0xFF
+
+/// default times of training
+#define DEFAULT_TRAINING_TIMES 1
+
+/// number of us to wait in parallel training
+#define PARALLEL_TRAINING_TIMEOUT 60000000
+
+/// number of us to wait in PCI space access
+#define PCI_ACCESS_TIMEOUT 10000000
+/// number of us to wait in special PCI space access which takes much longer than others
+#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000
+
+/// Beginning of retrain handling, must be ended with the ending of the handling
+#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit)
+
+/// Ending of retrain handling
+#define ERROR_HANDLE_RETRAIN_END(condition, counter) \
+if (condition) { \
+  counter ++; \
+} else { \
+  break; \
+}
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+MemErrHandle (
+  IN       DIE_STRUCT *MCTPtr,
+  IN       UINT8  DCT,
+  IN       UINT16  ChipSelMask,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  /* _MMERRHDL_H_ */