diff options
author | Kerry Sheh <shekairui@gmail.com> | 2012-01-20 13:57:48 +0800 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-01-26 10:09:22 +0100 |
commit | e8689ed974992b35aede9cd831b428ac37d9be76 (patch) | |
tree | 32ef9887fe057294f7a7fb2be069dd8d39d0c5d6 /src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h | |
parent | d2b31bda6738e370414622bd750cebf2e28e73de (diff) |
AGESA F15: AMD family15 AGESA code
AMD AGESA code to support Orochi platform family15 model 00-0fh processores,
AMD C32, G34, and AM3r2 Sockets are supported.
Change-Id: If79392c104ace25f7e01db794fa205f47746bcad
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/554
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h')
-rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h new file mode 100644 index 0000000000..e40b25c739 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h @@ -0,0 +1,85 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mnS3or.h + * + * S3 resume memory related function for OR. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/OR) + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (C) 2012 Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _MNS3OR_H_ +#define _MNS3OR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of OR +typedef enum { + PCI_LST_ESR_OR, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_OR, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_OR, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_OR, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_OR, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_OR, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_OR, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_OR ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDOr; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define SET_S3_NB_PSTATE_OFFSET(Offset, NBPstate) ((NBPstate << 10) | Offset) + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3OR_H_ |