diff options
| author | Konstantin Aladyshev <aladyshev@nicevt.ru> | 2013-03-06 22:13:42 +0400 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-08 07:30:06 +0100 |
| commit | c2f2bd0a6d00a7f8df4005f148f67373db6d26d6 (patch) | |
| tree | 385ec9b00e6ab35bf6ad36d0b1f4bc3618581f6f /src/vendorcode/amd/agesa/f14/cpcar.inc | |
| parent | 4c1e906e36252db3361d7df4c3764b352f53e2f3 (diff) | |
AGESA: Fix CR0_PE bit define
AGESA code has wrong definition of CR0_PE bit (1 instead of 0).
PE [Protected Mode Enable] is 0 bit in CR0 register
(If PE=1, system is in protected mode, else system is in real mode)
Bit 1 is MP [Monitor co-processor]
(Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)
System uses CR0_PE define, but I didn't expect any consequences because of this bug.
Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2591
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/cpcar.inc')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/cpcar.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/cpcar.inc b/src/vendorcode/amd/agesa/f14/cpcar.inc index b9aaa91a7b..ce33f62402 100644 --- a/src/vendorcode/amd/agesa/f14/cpcar.inc +++ b/src/vendorcode/amd/agesa/f14/cpcar.inc @@ -97,7 +97,7 @@ CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3 COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit -CR0_PE EQU 1 ; Protection Enable +CR0_PE EQU 0 ; Protection Enable CR0_NW EQU 29 ; Not Write-through CR0_CD EQU 30 ; Cache Disable CR0_PG EQU 31 ; Paging Enable |