Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

16 files changed, 163 insertions, 22 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
index d683da8e5d..b3f0a8ee14 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -217,7 +217,7 @@ MemConstructRemoteNBBlockC32 (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
index 143baac643..2f149a212b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -219,7 +219,7 @@ MemConstructRemoteNBBlockDA (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
index d1e241c3b5..f56d02ab3d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
@@ -405,7 +405,7 @@ MemNCapSpeedBatteryLifeDA (
   FamilySpecificServices = NULL;
   DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
   ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
-  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
+  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
   if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
     NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100;  // Calculate the Nb P1 frequency (NbFreq / 2)
     for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
index 33ec0c77c1..17a8427d22 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -219,7 +219,7 @@ MemConstructRemoteNBBlockDR (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
index 651ba7cf56..8a444362a8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -217,7 +217,7 @@ MemConstructRemoteNBBlockHY (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
index dcbbf96969..4af0dfba8c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -120,6 +120,14 @@ MemNS3GetConPCIMaskON (
   IN OUT   MEM_NB_BLOCK *NBPtr,
   IN OUT   DESCRIPTOR_GROUP *DescriptPtr
   );
+
+BOOLEAN
+MemS3ResumeConstructNBBlockON (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
 /*----------------------------------------------------------------------------
  *                          DEFINITIONS AND MACROS
  *
@@ -176,6 +184,11 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = {
   {{1, 1, 1}, DCT0,   BFAddrRxVioLvl, 0x00000018},
   // 4. Frequency Change
   {{4, 3, 1}, DCT0,   BFPllLockTime, 0},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimDByte, 0x7000},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimClk, 0x7000},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimCsOdt, 0x7000},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimAByte2, 0x7000},
+  {{1, 2, 1}, DCT0,   BFReduceLoop, 0x6000},
   {{0, 0, 0}, FUNC_2, 0x94,  0xFFD1CC1F},
   //    NB Pstate Related Register for Pstate 0
   {{0, 0, 0}, FUNC_2, 0x78,  0xFFF63FCF},
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
index c0855b8f43..a3afd55e20 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -149,7 +149,7 @@ MemNAutoConfigON (
     MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
   }
 
-  MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1);
+  MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, (((MemNGetBitFieldNb (NBPtr, BFLowPowerDefault)) == 1) && (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife)) ? 0 : 1);
 
   MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE);
 
@@ -459,7 +459,7 @@ MemNChangeNbFrequencyWrapON (
   if (Status) {
     // When NB frequency change succeeds, TSC rate may have changed.
     // We need to update TSC rate
-    GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+    GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
     FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
   }
   return Status;
@@ -487,4 +487,33 @@ MemNSetDqsODTON (
     MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20);
   }
   return TRUE;
-}
\ No newline at end of file
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function sets reduceloop and trim value for DDR-1333 for C0
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNBeforeMemClkFreqValON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) != 0)) {
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimDByte, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimClk, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimCsOdt, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimAByte2, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFReduceLoop, 0x6000);
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
index b7efd35cbb..f6f170d607 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
@@ -60,6 +60,7 @@
 #include "OptionMemory.h"
 #include "mm.h"
 #include "mn.h"
+#include "mnon.h"
 #include "mt.h"
 #include "Filecode.h"
 #include "GeneralServices.h"
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
index 9e4060af3f..718e52b608 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
@@ -85,6 +85,13 @@
  */
 
 
+BOOLEAN
+MemNIdentifyDimmConstructorON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
index 768d0d7106..17a20198cf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -251,7 +251,7 @@ MemConstructNBBlockON (
   NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
   NBPtr->TechBlockSwitch = MemNTechBlockSwitchON;
   NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW];
+  NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) memNTrainFlowControl[DDR3_TRAIN_FLOW];
   NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
   NBPtr->PollBitField = MemNPollBitFieldNb;
   NBPtr->BrdcstCheck = MemNBrdcstCheckON;
@@ -301,13 +301,21 @@ MemConstructNBBlockON (
   NBPtr->IsSupported[AdjustTwr] = TRUE;
   NBPtr->IsSupported[UnifiedNbFence] = TRUE;
   NBPtr->IsSupported[ChannelPDMode] = TRUE;   // Erratum 435
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_C0) != 0) {
+    NBPtr->IsSupported[AdjustTrc] = TRUE;
+  }
 
   NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON;
   NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb;
   NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb;
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
+    // Do not do phase B enforcement for Rev C
   NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON;
+  }
   NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON;
   NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON;
+  NBPtr->FamilySpecificHook[BfAfExcludeDimm] = MemNBfAfExcludeDimmClientNb;
+  NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] = MemNBeforeMemClkFreqValON;
 
   FeatPtr->InitCPG (NBPtr);
   FeatPtr->InitEarlySampleSupport (NBPtr);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
index e5f8683d36..1523cd6218 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem)
- * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -241,6 +241,12 @@ MemNSetDqsODTON (
   );
 
 BOOLEAN
+MemNBeforeMemClkFreqValON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
 MemNResetRxFifoPtrON (
   IN OUT   MEM_NB_BLOCK *NBPtr,
   IN OUT   VOID *OptParam
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
index d8c9c9df59..7f60a98ef9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
@@ -80,6 +80,11 @@ MemNDetectMemPllErrorON (
  *
  *-----------------------------------------------------------------------------
  */
+VOID
+MemNInitEarlySampleSupportON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
index 3f99b2c590..f85e56dc17 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -348,6 +348,7 @@ MemNInitNBRegTableON (
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31,  0, BFDramHoleAddrReg);
 
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
@@ -486,6 +487,7 @@ MemNInitNBRegTableON (
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31,  0, BFAcpiPwrStsCtrlHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1FC), 2, 2,  BFLowPowerDefault);
 
   MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  2,  0, BFCkeDrvStren);
   MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  6,  4, BFCsOdtDrvStren);
@@ -561,10 +563,15 @@ MemNInitNBRegTableON (
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F,  4,  3, BFCmdRxVioLvl);
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F,  4,  3, BFAddrRxVioLvl);
 
-  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15,  0, BFPhy0x0D080F0C);
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00,  6,  4, BFDQOdt03);
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08,  6,  4, BFDQOdt47);
 
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1E, 14, 12, BFDllCSRBisaTrimDByte);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1E, 14, 12, BFDllCSRBisaTrimClk);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1E, 14, 12, BFDllCSRBisaTrimCsOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FCF1E, 14, 12, BFDllCSRBisaTrimAByte2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F38, 14, 13, BFReduceLoop);
+
   MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11,  8, BFTwrrdSD);
   MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06,  3,  0, BFTrdrdSD);
   MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16,  3,  0, BFTwrwrSD);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
index 32d6f2ce3e..ac103497f6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -978,6 +978,10 @@ MemNProgramCycTimingsClientNb (
       Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8;
     }
 
+    if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) {
+      Value8 -= 5;
+    }
+
     Value8 = Value8 - TmgAdjTab[j].Bias;
     Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
 
@@ -986,7 +990,7 @@ MemNProgramCycTimingsClientNb (
             (BitField == BFTrp ) ? (Value8 <= 9) :
             (BitField == BFTrtp) ? (Value8 <= 4) :
             (BitField == BFTras) ? (Value8 <= 21) :
-            (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) :
+            (BitField == BFTrc ) ? (NBPtr->IsSupported[AdjustTrc] ? ((Value8 >= 4) && (Value8 <= 38)) : ((Value8 >= 9) && (Value8 <= 38))) :
             (BitField == BFTrrd) ? (Value8 <= 4) :
             (BitField == BFTwtr) ? (Value8 <= 4) :
             (BitField == BFTwrDDR3) ? (Value8 <= 7) :
@@ -1857,6 +1861,7 @@ MemNChangeFrequencyUnb (
     //                                                                         THEN 2 ELSE 3 ENDIF (Ontario)
     NBPtr->ProgramNbPsDependentRegs (NBPtr);
 
+    NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr);
     IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
     // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
     MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
index 0779531ac4..d806fa5544 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
@@ -87,6 +87,21 @@ RDATA_GROUP (G1_PEICC)
  */
 
 VOID
+MemNInitCPGNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
 STATIC
 MemNContWritePatternNb (
   IN OUT   MEM_NB_BLOCK *NBPtr,
@@ -203,6 +218,16 @@ MemNContWritePatternUnb (
   IN       UINT16 ClCount
   );
 
+VOID
+MemNInitCPGClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitCPGUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
@@ -924,7 +949,7 @@ MemNGenHwRcvEnReadsUnb (
   //
   // Issue Stream of Reads from the Target Rank
   //
-  NBPtr->ReadPattern (NBPtr, DummyPtr, NULL, NBPtr->TechPtr->PatternLength);
+  NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
 }
 
 /* -----------------------------------------------------------------------------*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
index c6fe85045d..613aadd936 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB)
- * @e \$Revision: 39420 $ @e \$Date: 2010-10-12 00:52:49 +0800 (Tue, 12 Oct 2010) $
+ * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -130,7 +130,6 @@ MemNSyncTargetSpeedNb (
 {
   CONST UINT16 DdrMaxRateTab[] = {
     UNSUPPORTED_DDR_FREQUENCY,
-    DDR1866_FREQUENCY,
     DDR1600_FREQUENCY,
     DDR1333_FREQUENCY,
     DDR1066_FREQUENCY,
@@ -185,8 +184,8 @@ MemNSyncTargetSpeedNb (
           Mode[Dct] = ChnlTmgMod[0];
           // Check if input clock value is valid or not
           ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
-            (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
-            (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
+            ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) :
+            ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY));
           MemClkFreq = ChnlTmgMod[1];
         }
       }
@@ -1182,3 +1181,39 @@ MemNGetMaxDdrRateUnb (
   * (UINT16 * ) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate));
   return TRUE;
 }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function performs the action before and after excluding dimms on CNB
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  *IsBefore   - If the function is called before excluding dimms
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *IsBefore
+  )
+{
+  if (*(BOOLEAN *) IsBefore == TRUE) {
+    NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1);
+    NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  } else {
+    NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1);
+    NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */