diff options
author | efdesign98 <efdesign98@gmail.com> | 2011-06-20 18:12:43 -0700 |
---|---|---|
committer | Marc Jones <marcj303@gmail.com> | 2011-06-22 01:35:45 +0200 |
commit | 621ca384a7a5efb2cc7597504dc17b741cd2df10 (patch) | |
tree | 01871adc6d39f48916b5625b3aa1a4b6d5ab9c92 /src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c | |
parent | 05a89ab922473f375820a3bd68691bb085c62448 (diff) |
Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.
Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c')
-rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c | 292 |
1 files changed, 292 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c new file mode 100644 index 0000000000..378ca7a254 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c @@ -0,0 +1,292 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * mmflowon.c + * + * Main Memory initialization sequence for ON + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main/ON) + * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $ + * + **/ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnon.h" +#include "mt.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#include "GeneralServices.h" + +#define FILECODE PROC_MEM_MAIN_ON_MMFLOWON_FILECODE +/* features */ +#include "mftds.h" + +extern MEM_FEAT_BLOCK_MAIN MemFeatMain; + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function defines the memory initialization flow for + * systems that only support ON processors. + * + * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK + * + * @return AGESA_STATUS + * - AGESA_ALERT + * - AGESA_FATAL + * - AGESA_SUCCESS + * - AGESA_WARNING + */ +AGESA_STATUS +MemMFlowON ( + IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr + ) +{ + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = MemMainPtr->NBPtr; + MemPtr = MemMainPtr->MemPtr; + + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) { + MemPtr->IsFlowControlSupported = FALSE; + return AGESA_FATAL; + } else { + MemPtr->IsFlowControlSupported = TRUE; + } + + //---------------------------------------------------------------- + // Low voltage DDR3 + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.LvDDR3 (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Initialize DRAM and DCTs, and Create Memory Map + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader)); + // Initialize Memory Controller and Dram + IDS_HDT_CONSOLE (MEM_STATUS, "Node 0\n"); + + if (!NBPtr[BSP_DIE].InitMCT (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; //fatalexit + } + + // Create memory map + AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].HtMemMapInit (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------- + // If there is no dimm on the system, do fatal exit + //---------------------------------------------------- + if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) { + PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader)); + ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Synchronize DCTs + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].SyncDctsReady (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // CpuMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Before Training Table values + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeTrn); + + //---------------------------------------------------------------- + // Memory Context Restore + //---------------------------------------------------------------- + if (!MemFeatMain.MemRestore (MemMainPtr)) { + // Do DQS training only if memory context restore fails + + //---------------------------------------------------------------- + // Training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING; + AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader)); + IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) { + if (!MemFeatMain.Training (MemMainPtr)) { + return AGESA_FATAL; + } + } + IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n"); + } + + //---------------------------------------------------------------- + // Disable chipselects that fail training + //---------------------------------------------------------------- + MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING; + MemFeatMain.ExcludeDIMM (MemMainPtr); + MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL; + + //---------------------------------------------------------------- + // OtherTiming + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader)); + if (!NBPtr[BSP_DIE].OtherTiming (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // After Training Table values + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterTrn); + + + //---------------------------------------------------------------- + // Interleave banks + //---------------------------------------------------------------- + if (NBPtr[BSP_DIE].FeatPtr->InterleaveBanks (&NBPtr[BSP_DIE])) { + if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) { + return AGESA_FATAL; + } + } + + //---------------------------------------------------------------- + // After Programming Interleave registers + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterInterleave); + + //---------------------------------------------------------------- + // Memory Clear + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.MemClr (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // C6 Storage Allocation + //---------------------------------------------------------------- + NBPtr[BSP_DIE].AllocateC6Storage (&NBPtr[BSP_DIE]); + + //---------------------------------------------------------------- + // UMA Allocation & UMAMemTyping + //---------------------------------------------------------------- + AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader)); + if (!MemFeatMain.UmaAllocation (MemMainPtr)) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // Finalize MCT + //---------------------------------------------------------------- + if (!NBPtr[BSP_DIE].FinalizeMCT (&NBPtr[BSP_DIE])) { + return AGESA_FATAL; + } + + //---------------------------------------------------------------- + // After Finalize MCT + //---------------------------------------------------------------- + MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterFinalizeMCT); + + + //---------------------------------------------------------------- + // Memory Context Save + //---------------------------------------------------------------- + MemFeatMain.MemSave (MemMainPtr); + + //---------------------------------------------------------------- + // Memory DMI support + //---------------------------------------------------------------- + if (!MemFeatMain.MemDmi (MemMainPtr)) { + return AGESA_CRITICAL; + } + + return AGESA_SUCCESS; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ |