Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

7 files changed, 44 insertions, 6 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 812aa963e4..0f22e1b71e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -86,6 +86,11 @@ MemFDctInterleaveBanks (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 VOID
 STATIC
 CsIntSwap (
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
index b4d17194ea..bcbee65444 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Main)
- * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $
  *
  **/
 /*
@@ -84,6 +84,16 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
@@ -505,7 +515,7 @@ MemFDMISupport2 (
 
           // Form Factor (offset 0Eh)
           FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
-          if ((FormFactor & 0x20) == 4) {
+          if ((FormFactor & 0x04) == 4) {
             DmiTable[DimmIndex].FormFactor = 0x0D;       // SO-DIMM
           } else {
             DmiTable[DimmIndex].FormFactor = 0x09;       // RDIMM or UDIMM
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
index 4ea95e98cd..4344e25663 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
@@ -75,11 +75,18 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
 UINT32
 STATIC
 MemFGetScrubAddr (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
+*/
 
 VOID
 STATIC
@@ -296,6 +303,7 @@ InitECCOverriedeStruct (
  *     @return          Scrubber Address
  */
 
+/*
 UINT32
 STATIC
 MemFGetScrubAddr (
@@ -318,4 +326,4 @@ MemFGetScrubAddr (
   }
   return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
 }
-
+*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
index cdf3568259..75590ede75 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
@@ -75,6 +75,11 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
 STATIC
 IsPowerOfTwo (
   IN       UINT32 TestNumber
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index c6e85ec3f0..bcd069b7ca 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Feat/EXCLUDIMM)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -82,6 +82,11 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
@@ -163,6 +168,8 @@ MemFRASExcludeDIMM (
       IsCSIntlvEnabled = TRUE;
     }
 
+    Flag = TRUE;
+    NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
     for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
       NBPtr->SwitchDCT (NBPtr, Dct);
       if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
@@ -179,6 +186,8 @@ MemFRASExcludeDIMM (
         }
       }
     }
+    Flag = FALSE;
+    NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
 
     // Re-enable chip select interleaving when remapping is done.
     if (IsCSIntlvEnabled) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 9576f8014b..f96841b051 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Feat)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $
  *
  **/
 /*
@@ -160,6 +160,7 @@ AmdIdentifyDimm (
     // NB block has already been constructed by main block.
     // No need to construct it here.
     NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    mmData.NBPtr = NBPtr;
   } else {
     AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
     AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
index b51db06a5b..df2071f5bc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
@@ -703,7 +703,7 @@ MemFS3Wait10ns (
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 
   ASSERT (Count <= 1000000);
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader);
 
   LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);