diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-08-04 12:09:17 -0600 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-08-06 18:06:18 +0200 |
| commit | 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch) | |
| tree | 57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h | |
| parent | 0df0e14fb5b613e76ff022359c55d5df5633b40f (diff) | |
Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus. It also fixes (again) a ton of warnings, although
not all of them are gone. The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.
Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h index 6e65c8d1c9..6d26a4a7a7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $ * */ /* @@ -57,6 +57,15 @@ PciePortPostInit ( IN PCIe_PLATFORM_CONFIG *Pcie ); +AGESA_STATUS +PciePortPostEarlyInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePortPostS3Init ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); #endif |