diff options
author | Patrick Georgi <pgeorgi@google.com> | 2021-02-12 13:49:11 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-15 11:30:40 +0000 |
commit | 6b688f5329e560ef432f6ea281b2fe3d905ef297 (patch) | |
tree | 831ff654f7477b293421e38b8ed880f2cc740386 /src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c | |
parent | 036d66be051c4aeeac3b6220974e93645489c27d (diff) |
src: use ARRAY_SIZE where possible
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c')
-rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c index b83afea231..318bb82566 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c @@ -198,7 +198,7 @@ PcieCommonCoreInit ( if (PcieLibIsPcieWrapper (Wrapper)) { IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { - for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { + for (Index = 0; Index < ARRAY_SIZE(CoreInitTable); Index++) { UINT32 Value; Value = PcieRegisterRead ( Wrapper, |