Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 23 insertions, 3 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
index d33c341048..fbfea63d62 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
@@ -97,6 +97,7 @@ DefinitionBlock (
       }
     }
 
+#ifdef  PCIE_PHY_LANE_POWER_GATE_SUPPORT
     /*----------------------------------------------------------------------------------------*/
     /**
      *  Power gate PCIe phy lanes (hotplug support)
@@ -108,10 +109,10 @@ DefinitionBlock (
     Method (procPcieLanePowerControl, 3, NotSerialized) {
        // stub function
     }
-
+#endif
     /*----------------------------------------------------------------------------------------*/
     /**
-     *  Read RCU register
+     *  Adjust PLL settings stub
      *
      *  Arg0 	- 1 - GEN1 2 - GEN2
      *  
@@ -119,7 +120,26 @@ DefinitionBlock (
     Method (procPcieAdjustPll, 1, NotSerialized) {
       //stub function
     }
-	
+    Name (AD0B, 0)
+    /*----------------------------------------------------------------------------------------*/
+    /**
+     *  APM/PDM stub
+     *
+     *  Arg0  - 0 (AC)   1 (DC)
+     *
+     */
+    Method (procApmPdmActivate, 1, NotSerialized) {
+      if (LEqual (AD0B, 1)) {
+        Store (Or(ShiftLeft (0x18, 3), 4), Local1)
+        Store (procPciDwordRead (Local1, 0x15C), Local2)
+        if (LEqual (Arg0, DEF_PSPP_STATE_AC)) {
+          Or (Local2, 0x01, Local2)
+        } else {
+          And (Local2, 0xfffffffc, Local2)
+        }
+        procPciDwordWrite (Local1, 0x15C, Local2)
+      }
+    }
   } //End of Scope(\_SB)
 }   //End of DefinitionBlock